VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 44360

Last change on this file since 44360 was 44351, checked in by vboxsync, 12 years ago

PDM,++: Change APIs used by Main from PVM to PUVM.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 137.2 KB
Line 
1/* $Id: HM.cpp 44351 2013-01-24 12:04:39Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/stam.h>
24#include <VBox/vmm/mm.h>
25#include <VBox/vmm/pdmapi.h>
26#include <VBox/vmm/pgm.h>
27#include <VBox/vmm/ssm.h>
28#include <VBox/vmm/trpm.h>
29#include <VBox/vmm/dbgf.h>
30#include <VBox/vmm/iom.h>
31#include <VBox/vmm/patm.h>
32#include <VBox/vmm/csam.h>
33#include <VBox/vmm/selm.h>
34#ifdef VBOX_WITH_REM
35# include <VBox/vmm/rem.h>
36#endif
37#include <VBox/vmm/hm_vmx.h>
38#include <VBox/vmm/hm_svm.h>
39#include "HMInternal.h"
40#include <VBox/vmm/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/asm-amd64-x86.h>
48#include <iprt/string.h>
49#include <iprt/env.h>
50#include <iprt/thread.h>
51
52/*******************************************************************************
53* Global Variables *
54*******************************************************************************/
55#ifdef VBOX_WITH_STATISTICS
56# define EXIT_REASON(def, val, str) #def " - " #val " - " str
57# define EXIT_REASON_NIL() NULL
58/** Exit reason descriptions for VT-x, used to describe statistics. */
59static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
60{
61 EXIT_REASON(VMX_EXIT_XCPT_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
62 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
63 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
64 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
65 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
66 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
67 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
68 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
69 EXIT_REASON_NIL(),
70 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
71 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
72 EXIT_REASON_NIL(),
73 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
74 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
75 EXIT_REASON(VMX_EXIT_INVLPG , 14, "Guest software attempted to execute INVLPG."),
76 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
77 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
78 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
79 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
80 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
81 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
82 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
83 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
84 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
85 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
86 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
87 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
88 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
89 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
90 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
91 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
92 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
93 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
94 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
95 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
96 EXIT_REASON_NIL(),
97 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
98 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
99 EXIT_REASON_NIL(),
100 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
101 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
102 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
103 EXIT_REASON_NIL(),
104 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
105 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
106 EXIT_REASON_NIL(),
107 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
108 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
109 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
110 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
111 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
112 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "Guest software attempted to execute RDTSCP."),
113 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
114 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
115 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
116 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
117 EXIT_REASON_NIL()
118};
119/** Exit reason descriptions for AMD-V, used to describe statistics. */
120static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
121{
122 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
123 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
124 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
125 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
126 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
127 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
128 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
129 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
130 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
131 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
132 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
133 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
134 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
135 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
136 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
137 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
138 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
154 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
155 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
156 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
157 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
158 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
159 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
160 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
161 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
162 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
163 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
164 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
165 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
166 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
167 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
168 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
169 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
170 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
186 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
218 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt."),
219 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt."),
220 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt."),
221 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal."),
222 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt."),
223 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
224 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
225 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
226 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
227 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
228 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
229 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
230 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
231 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
232 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
233 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
234 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
235 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
236 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
237 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
238 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
239 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
240 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
241 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
242 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
243 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
244 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
245 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
246 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
247 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
248 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
249 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
250 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
251 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
252 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
253 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
254 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
255 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
256 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
257 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
258 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
259 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
260 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
261 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
262 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
263 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
264 EXIT_REASON_NIL()
265};
266# undef EXIT_REASON
267# undef EXIT_REASON_NIL
268#endif /* VBOX_WITH_STATISTICS */
269
270/*******************************************************************************
271* Internal Functions *
272*******************************************************************************/
273static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
274static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
275static int hmR3InitCPU(PVM pVM);
276static int hmR3InitFinalizeR0(PVM pVM);
277static int hmR3TermCPU(PVM pVM);
278
279
280/**
281 * Initializes the HM.
282 *
283 * @returns VBox status code.
284 * @param pVM Pointer to the VM.
285 */
286VMMR3DECL(int) HMR3Init(PVM pVM)
287{
288 LogFlow(("HMR3Init\n"));
289
290 /*
291 * Assert alignment and sizes.
292 */
293 AssertCompileMemberAlignment(VM, hm.s, 32);
294 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
295
296 /* Some structure checks. */
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
300
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.TR) == 0x490, ("guest.TR offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.TR)));
303 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8CPL) == 0x4CB, ("guest.u8CPL offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8CPL)));
304 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64EFER) == 0x4D0, ("guest.u64EFER offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64EFER)));
305 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR4) == 0x548, ("guest.u64CR4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR4)));
306 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RIP) == 0x578, ("guest.u64RIP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RIP)));
307 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RSP) == 0x5D8, ("guest.u64RSP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RSP)));
308 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR2) == 0x640, ("guest.u64CR2 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR2)));
309 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64GPAT) == 0x668, ("guest.u64GPAT offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64GPAT)));
310 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO) == 0x690, ("guest.u64LASTEXCPTO offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO)));
311 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
312
313 /*
314 * Register the saved state data unit.
315 */
316 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SSM_VERSION, sizeof(HM),
317 NULL, NULL, NULL,
318 NULL, hmR3Save, NULL,
319 NULL, hmR3Load, NULL);
320 if (RT_FAILURE(rc))
321 return rc;
322
323 /* Misc initialisation. */
324 pVM->hm.s.vmx.fSupported = false;
325 pVM->hm.s.svm.fSupported = false;
326 pVM->hm.s.vmx.fEnabled = false;
327 pVM->hm.s.svm.fEnabled = false;
328
329 pVM->hm.s.fNestedPaging = false;
330 pVM->hm.s.fLargePages = false;
331
332 /* Disabled by default. */
333 pVM->fHMEnabled = false;
334
335 /*
336 * Check CFGM options.
337 */
338 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
339 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
340 /* Nested paging: disabled by default. */
341 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
342 AssertRC(rc);
343
344 /* Large pages: disabled by default. */
345 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableLargePages", &pVM->hm.s.fLargePages, false);
346 AssertRC(rc);
347
348 /* VT-x VPID: disabled by default. */
349 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
350 AssertRC(rc);
351
352 /* HM support must be explicitely enabled in the configuration file. */
353 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hm.s.fAllowed, false);
354 AssertRC(rc);
355
356 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
357 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hm.s.fTRPPatchingAllowed, false);
358 AssertRC(rc);
359
360#ifdef RT_OS_DARWIN
361 if (VMMIsHwVirtExtForced(pVM) != pVM->hm.s.fAllowed)
362#else
363 if (VMMIsHwVirtExtForced(pVM) && !pVM->hm.s.fAllowed)
364#endif
365 {
366 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
367 VMMIsHwVirtExtForced(pVM), pVM->hm.s.fAllowed));
368 return VERR_HM_CONFIG_MISMATCH;
369 }
370
371 if (VMMIsHwVirtExtForced(pVM))
372 pVM->fHMEnabled = true;
373
374#if HC_ARCH_BITS == 32
375 /*
376 * 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
377 * (To use the default, don't set 64bitEnabled in CFGM.)
378 */
379 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, false);
380 AssertLogRelRCReturn(rc, rc);
381 if (pVM->hm.s.fAllow64BitGuests)
382 {
383# ifdef RT_OS_DARWIN
384 if (!VMMIsHwVirtExtForced(pVM))
385# else
386 if (!pVM->hm.s.fAllowed)
387# endif
388 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
389 }
390#else
391 /*
392 * On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
393 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.)*
394 */
395 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, true);
396 AssertLogRelRCReturn(rc, rc);
397#endif
398
399
400 /*
401 * Determine the init method for AMD-V and VT-x; either one global init for each host CPU
402 * or local init each time we wish to execute guest code.
403 *
404 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
405 */
406 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hm.s.fGlobalInit,
407#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
408 false
409#else
410 true
411#endif
412 );
413
414 /* Max number of resume loops. */
415 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
416 AssertRC(rc);
417
418 return rc;
419}
420
421
422/**
423 * Initializes the per-VCPU HM.
424 *
425 * @returns VBox status code.
426 * @param pVM Pointer to the VM.
427 */
428static int hmR3InitCPU(PVM pVM)
429{
430 LogFlow(("HMR3InitCPU\n"));
431
432 for (VMCPUID i = 0; i < pVM->cCpus; i++)
433 {
434 PVMCPU pVCpu = &pVM->aCpus[i];
435
436 pVCpu->hm.s.fActive = false;
437 }
438
439#ifdef VBOX_WITH_STATISTICS
440 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
441 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
442 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
443 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
444
445 /*
446 * Statistics.
447 */
448 for (VMCPUID i = 0; i < pVM->cCpus; i++)
449 {
450 PVMCPU pVCpu = &pVM->aCpus[i];
451 int rc;
452
453 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
454 "Profiling of RTMpPokeCpu",
455 "/PROF/HM/CPU%d/Poke", i);
456 AssertRC(rc);
457 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
458 "Profiling of poke wait",
459 "/PROF/HM/CPU%d/PokeWait", i);
460 AssertRC(rc);
461 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
462 "Profiling of poke wait when RTMpPokeCpu fails",
463 "/PROF/HM/CPU%d/PokeWaitFailed", i);
464 AssertRC(rc);
465 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
466 "Profiling of VMXR0RunGuestCode entry",
467 "/PROF/HM/CPU%d/SwitchToGC", i);
468 AssertRC(rc);
469 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
470 "Profiling of VMXR0RunGuestCode exit part 1",
471 "/PROF/HM/CPU%d/SwitchFromGC_1", i);
472 AssertRC(rc);
473 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
474 "Profiling of VMXR0RunGuestCode exit part 2",
475 "/PROF/HM/CPU%d/SwitchFromGC_2", i);
476 AssertRC(rc);
477# if 1 /* temporary for tracking down darwin holdup. */
478 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
479 "Temporary - I/O",
480 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub1", i);
481 AssertRC(rc);
482 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
483 "Temporary - CRx RWs",
484 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub2", i);
485 AssertRC(rc);
486 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
487 "Temporary - Exceptions",
488 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub3", i);
489 AssertRC(rc);
490# endif
491 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
492 "Profiling of vmlaunch",
493 "/PROF/HM/CPU%d/InGC", i);
494 AssertRC(rc);
495
496# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
497 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
498 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
499 "/PROF/HM/CPU%d/Switcher3264", i);
500 AssertRC(rc);
501# endif
502
503# define HM_REG_COUNTER(a, b) \
504 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
505 AssertRC(rc);
506
507 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM");
508 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM");
509 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF");
510 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM");
511 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF");
512 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD");
513 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS");
514 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP");
515 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP");
516 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF");
517 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE");
518 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB");
519 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP");
520 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF");
521 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other");
522 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg");
523 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd");
524 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd");
525 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause");
526 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid");
527 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc");
528 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp");
529 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc");
530 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand");
531 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr");
532 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr");
533 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait");
534 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor");
535 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write");
536 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read");
537 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS");
538 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW");
539 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli");
540 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti");
541 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf");
542 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf");
543 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret");
544 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int");
545 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt");
546 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess");
547 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write");
548 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read");
549 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString");
550 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString");
551 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow");
552 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMaxResume, "/HM/CPU%d/Exit/MaxResume");
553 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptPending, "/HM/CPU%d/Exit/PreemptPending");
554 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer");
555 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold");
556 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch");
557 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag");
558 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess");
559
560 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending");
561 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchToR3, "/HM/CPU%d/Switch/ToR3");
562
563 HM_REG_COUNTER(&pVCpu->hm.s.StatIntInject, "/HM/CPU%d/Irq/Inject");
564 HM_REG_COUNTER(&pVCpu->hm.s.StatIntReinject, "/HM/CPU%d/Irq/Reinject");
565 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Irq/PendingOnHost");
566
567 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page");
568 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt");
569 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys");
570 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB");
571 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual");
572 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbCRxChange, "/HM/CPU%d/Flush/TLB/CRx");
573 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageInvlpg, "/HM/CPU%d/Flush/Page/Invlpg");
574 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Switch");
575 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped");
576 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID");
577 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging");
578 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpga, "/HM/CPU%d/Flush/TLB/PhysInvl");
579 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page");
580 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB");
581
582 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset");
583 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept");
584 HM_REG_COUNTER(&pVCpu->hm.s.StatTscInterceptOverFlow, "/HM/CPU%d/TSC/InterceptOverflow");
585
586 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed");
587 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch");
588 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck");
589
590 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal");
591 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full");
592
593#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
594 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu");
595 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug");
596#endif
597
598 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
599 {
600 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
601 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
602 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
603 AssertRC(rc);
604 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
605 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
606 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
607 AssertRC(rc);
608 }
609
610#undef HM_REG_COUNTER
611
612 pVCpu->hm.s.paStatExitReason = NULL;
613
614 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hm.s.paStatExitReason), 0, MM_TAG_HM,
615 (void **)&pVCpu->hm.s.paStatExitReason);
616 AssertRC(rc);
617 if (RT_SUCCESS(rc))
618 {
619 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
620 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
621 {
622 if (papszDesc[j])
623 {
624 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
625 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
626 AssertRC(rc);
627 }
628 }
629 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
630 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
631 AssertRC(rc);
632 }
633 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
634# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
635 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
636# else
637 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
638# endif
639
640 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
641 AssertRCReturn(rc, rc);
642 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
643# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
644 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
645# else
646 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
647# endif
648 for (unsigned j = 0; j < 255; j++)
649 {
650 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
651 "Forwarded interrupts.",
652 (j < 0x20) ? "/HM/CPU%d/Interrupt/Trap/%02X" : "/HM/CPU%d/Interrupt/IRQ/%02X", i, j);
653 }
654
655 }
656#endif /* VBOX_WITH_STATISTICS */
657
658#ifdef VBOX_WITH_CRASHDUMP_MAGIC
659 /* Magic marker for searching in crash dumps. */
660 for (VMCPUID i = 0; i < pVM->cCpus; i++)
661 {
662 PVMCPU pVCpu = &pVM->aCpus[i];
663
664 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
665 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
666 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
667 }
668#endif
669 return VINF_SUCCESS;
670}
671
672
673/**
674 * Called when a init phase has completed.
675 *
676 * @returns VBox status code.
677 * @param pVM The VM.
678 * @param enmWhat The phase that completed.
679 */
680VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
681{
682 switch (enmWhat)
683 {
684 case VMINITCOMPLETED_RING3:
685 return hmR3InitCPU(pVM);
686 case VMINITCOMPLETED_RING0:
687 return hmR3InitFinalizeR0(pVM);
688 default:
689 return VINF_SUCCESS;
690 }
691}
692
693
694/**
695 * Turns off normal raw mode features.
696 *
697 * @param pVM Pointer to the VM.
698 */
699static void hmR3DisableRawMode(PVM pVM)
700{
701 /* Disable PATM & CSAM. */
702 PATMR3AllowPatching(pVM, false);
703 CSAMDisableScanning(pVM);
704
705 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
706 SELMR3DisableMonitoring(pVM);
707 TRPMR3DisableMonitoring(pVM);
708
709 /* Disable the switcher code (safety precaution). */
710 VMMR3DisableSwitcher(pVM);
711
712 /* Disable mapping of the hypervisor into the shadow page table. */
713 PGMR3MappingsDisable(pVM);
714
715 /* Disable the switcher */
716 VMMR3DisableSwitcher(pVM);
717
718 /* Reinit the paging mode to force the new shadow mode. */
719 for (VMCPUID i = 0; i < pVM->cCpus; i++)
720 {
721 PVMCPU pVCpu = &pVM->aCpus[i];
722
723 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
724 }
725}
726
727
728/**
729 * Initialize VT-x or AMD-V.
730 *
731 * @returns VBox status code.
732 * @param pVM Pointer to the VM.
733 */
734static int hmR3InitFinalizeR0(PVM pVM)
735{
736 int rc;
737
738 /*
739 * Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
740 * is already using AMD-V.
741 */
742 if ( !pVM->hm.s.vmx.fSupported
743 && !pVM->hm.s.svm.fSupported
744 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
745 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
746 {
747 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
748 pVM->hm.s.svm.fSupported = true;
749 pVM->hm.s.svm.fIgnoreInUseError = true;
750 }
751 else
752 if ( !pVM->hm.s.vmx.fSupported
753 && !pVM->hm.s.svm.fSupported)
754 {
755 LogRel(("HM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hm.s.lLastError));
756 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
757
758 if (VMMIsHwVirtExtForced(pVM))
759 {
760 switch (pVM->hm.s.lLastError)
761 {
762 case VERR_VMX_NO_VMX:
763 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
764 case VERR_VMX_IN_VMX_ROOT_MODE:
765 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
766 case VERR_SVM_IN_USE:
767 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
768 case VERR_SVM_NO_SVM:
769 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
770 case VERR_SVM_DISABLED:
771 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
772 default:
773 return pVM->hm.s.lLastError;
774 }
775 }
776 return VINF_SUCCESS;
777 }
778
779 if (pVM->hm.s.vmx.fSupported)
780 {
781 rc = SUPR3QueryVTxSupported();
782 if (RT_FAILURE(rc))
783 {
784#ifdef RT_OS_LINUX
785 LogRel(("HM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
786#else
787 LogRel(("HM: The host kernel does not support VT-x!\n"));
788#endif
789 if ( pVM->cCpus > 1
790 || VMMIsHwVirtExtForced(pVM))
791 return rc;
792
793 /* silently fall back to raw mode */
794 return VINF_SUCCESS;
795 }
796 }
797
798 if (!pVM->hm.s.fAllowed)
799 return VINF_SUCCESS; /* nothing to do */
800
801 /* Enable VT-x or AMD-V on all host CPUs. */
802 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
803 if (RT_FAILURE(rc))
804 {
805 LogRel(("HMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HM_ENABLE failed with %Rrc\n", rc));
806 return rc;
807 }
808 Assert(!pVM->fHMEnabled || VMMIsHwVirtExtForced(pVM));
809
810 pVM->hm.s.fHasIoApic = PDMHasIoApic(pVM);
811 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
812 if (!pVM->hm.s.fHasIoApic)
813 {
814 Assert(!pVM->hm.s.fTRPPatchingAllowed); /* paranoia */
815 pVM->hm.s.fTRPPatchingAllowed = false;
816 }
817
818 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
819 if (pVM->hm.s.vmx.fSupported)
820 {
821 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
822
823 if ( pVM->hm.s.fInitialized == false
824 && pVM->hm.s.vmx.msr.feature_ctrl != 0)
825 {
826 uint64_t val;
827 RTGCPHYS GCPhys = 0;
828
829 LogRel(("HM: Host CR4=%08X\n", pVM->hm.s.vmx.hostCR4));
830 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
831 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hm.s.vmx.msr.vmx_basic_info));
832 LogRel(("HM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.vmx_basic_info)));
833 LogRel(("HM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.vmx_basic_info)));
834 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
835 LogRel(("HM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.vmx_basic_info)));
836 LogRel(("HM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.vmx_basic_info)));
837
838 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_pin_ctls.u));
839 val = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
840 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
841 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
842 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
843 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
844 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
845 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
846 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
847 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
848 val = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
849 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
850 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
851 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
852 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
853 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
854 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
855 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
856 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
857
858 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls.u));
859 val = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
860 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INT_WINDOW_EXIT)
861 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INT_WINDOW_EXIT\n"));
862 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
863 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
864 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
865 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
866 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
867 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
868 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
869 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
870 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
871 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
872 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
873 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
874 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
875 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
876 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
877 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
878 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
879 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
880 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
881 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
882 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
883 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
884 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
885 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
886 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
887 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
888 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
889 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
890 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
891 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
892 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
893 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
894 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
895 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
896 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
897 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
898 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
899 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
900 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
901 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
902
903 val = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
904 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INT_WINDOW_EXIT)
905 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INT_WINDOW_EXIT *must* be set\n"));
906 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
907 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
908 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
909 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
910 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
911 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
912 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
913 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
914 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
915 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
916 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
917 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
918 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
919 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
920 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
921 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
922 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
923 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
924 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
925 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
926 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
927 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
928 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
929 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
930 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
931 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
932 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
933 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
934 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
935 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
936 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
937 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
938 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
939 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
940 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
941 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
942 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
943 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
944 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
945 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
946
947 if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
948 {
949 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls2.u));
950 val = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
951 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
952 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
953 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
954 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
955 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT)
956 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT\n"));
957 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
958 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP\n"));
959 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
960 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
961 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
962 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
963 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
964 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
965 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
966 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE\n"));
967 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
968 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT\n"));
969
970 val = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
971 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
972 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
973 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT)
974 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT *must* be set\n"));
975 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
976 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP *must* be set\n"));
977 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
978 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
979 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
980 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
981 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
982 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
983 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
984 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
985 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
986 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE *must* be set\n"));
987 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
988 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT *must* be set\n"));
989 }
990
991 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_entry.u));
992 val = pVM->hm.s.vmx.msr.vmx_entry.n.allowed1;
993 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
994 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
995 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA32E_MODE_GUEST)
996 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA32E_MODE_GUEST\n"));
997 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
998 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
999 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
1000 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
1001 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
1002 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
1003 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
1004 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
1005 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
1006 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
1007 val = pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0;
1008 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
1009 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
1010 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA32E_MODE_GUEST)
1011 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA32E_MODE_GUEST *must* be set\n"));
1012 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
1013 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
1014 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
1015 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
1016 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
1017 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
1018 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
1019 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
1020 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
1021 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
1022
1023 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_exit.u));
1024 val = pVM->hm.s.vmx.msr.vmx_exit.n.allowed1;
1025 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
1026 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
1027 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_ADDR_SPACE_SIZE)
1028 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_ADDR_SPACE_SIZE\n"));
1029 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXT_INT)
1030 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXT_INT\n"));
1031 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
1032 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
1033 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
1034 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
1035 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
1036 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
1037 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1038 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
1039 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
1040 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
1041 val = pVM->hm.s.vmx.msr.vmx_exit.n.disallowed0;
1042 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
1043 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
1044 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_ADDR_SPACE_SIZE)
1045 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_ADDR_SPACE_SIZE *must* be set\n"));
1046 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXT_INT)
1047 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXT_INT *must* be set\n"));
1048 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
1049 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
1050 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
1051 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
1052 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
1053 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
1054 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1055 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
1056 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
1057 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
1058
1059 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps)
1060 {
1061 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %RX64\n", pVM->hm.s.vmx.msr.vmx_ept_vpid_caps));
1062
1063 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY)
1064 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY\n"));
1065 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY)
1066 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY\n"));
1067 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY)
1068 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY\n"));
1069 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS)
1070 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS\n"));
1071 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS)
1072 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS\n"));
1073 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS)
1074 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS\n"));
1075 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS)
1076 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS\n"));
1077 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS)
1078 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS\n"));
1079 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC)
1080 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC\n"));
1081 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC)
1082 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC\n"));
1083 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT)
1084 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT\n"));
1085 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP)
1086 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP\n"));
1087 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB)
1088 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB\n"));
1089 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS)
1090 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS\n"));
1091 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS)
1092 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS\n"));
1093 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS)
1094 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS\n"));
1095 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS)
1096 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS\n"));
1097 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT)
1098 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVEPT\n"));
1099 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT)
1100 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT\n"));
1101 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
1102 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS\n"));
1103 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID)
1104 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVVPID\n"));
1105 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
1106 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR\n"));
1107 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT)
1108 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT\n"));
1109 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS)
1110 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS\n"));
1111 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1112 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1113 }
1114
1115 LogRel(("HM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hm.s.vmx.msr.vmx_misc));
1116 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc) == pVM->hm.s.vmx.cPreemptTimerShift)
1117 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc)));
1118 else
1119 {
1120 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x - erratum detected, using %x instead\n",
1121 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc), pVM->hm.s.vmx.cPreemptTimerShift));
1122 }
1123 LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.msr.vmx_misc)));
1124 LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hm.s.vmx.msr.vmx_misc)));
1125 LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc)));
1126 LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hm.s.vmx.msr.vmx_misc)));
1127
1128 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed0));
1129 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed1));
1130 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed0));
1131 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed1));
1132 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hm.s.vmx.msr.vmx_vmcs_enum));
1133
1134 LogRel(("HM: APIC-access page physaddr = %RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1135
1136 /* Paranoia */
1137 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc) >= 512);
1138
1139 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1140 {
1141 LogRel(("HM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1142 LogRel(("HM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVMCS));
1143 }
1144
1145 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1146 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1147
1148 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1149 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1150
1151 /*
1152 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1153 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1154 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1155 */
1156 if (!(pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1157 && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1158 {
1159 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1160 }
1161
1162 /* Unrestricted guest execution relies on EPT. */
1163 if ( pVM->hm.s.fNestedPaging
1164 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE))
1165 {
1166 pVM->hm.s.vmx.fUnrestrictedGuest = true;
1167 }
1168
1169 /* Only try once. */
1170 pVM->hm.s.fInitialized = true;
1171
1172 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1173 {
1174 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1175 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1176 if (RT_SUCCESS(rc))
1177 {
1178 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1179 /* Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode" esp. Figure 20-5.*/
1180 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1181 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1182 /* Bit set to 0 means software interrupts are redirected to the 8086 program interrupt handler rather than
1183 switching to protected-mode handler. */
1184 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1185 /* Allow all port IO, so that port IO instructions do not cause exceptions and would instead
1186 cause a VM-exit (based on VT-x's IO bitmap which we currently configure to always cause an exit). */
1187 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1188 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1189
1190 /*
1191 * Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1192 * real and protected mode without paging with EPT.
1193 */
1194 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1195 for (unsigned i = 0; i < X86_PG_ENTRIES; i++)
1196 {
1197 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1198 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1199 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1200 | X86_PDE4M_G;
1201 }
1202
1203 /* We convert it here every time as pci regions could be reconfigured. */
1204 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1205 AssertRC(rc);
1206 LogRel(("HM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1207
1208 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1209 AssertRC(rc);
1210 LogRel(("HM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1211 }
1212 else
1213 {
1214 /** @todo This cannot possibly work, there are other places which assumes
1215 * this allocation cannot fail (see HMR3CanExecuteGuest()). Make this
1216 * a failure case. */
1217 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1218 pVM->hm.s.vmx.pRealModeTSS = NULL;
1219 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1220 }
1221 }
1222
1223 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1224 AssertRC(rc);
1225 if (rc == VINF_SUCCESS)
1226 {
1227 pVM->fHMEnabled = true;
1228 pVM->hm.s.vmx.fEnabled = true;
1229 hmR3DisableRawMode(pVM);
1230
1231 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1232#ifdef VBOX_ENABLE_64_BITS_GUESTS
1233 if (pVM->hm.s.fAllow64BitGuests)
1234 {
1235 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1236 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1237 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1238 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1239 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1240 }
1241 else
1242 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE (we reuse the host EFER in the switcher) */
1243 /* Todo: this needs to be fixed properly!! */
1244 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1245 && (pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1246 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1247
1248 LogRel((pVM->hm.s.fAllow64BitGuests
1249 ? "HM: 32-bit and 64-bit guests supported.\n"
1250 : "HM: 32-bit guests supported.\n"));
1251#else
1252 LogRel(("HM: 32-bit guests supported.\n"));
1253#endif
1254 LogRel(("HM: VMX enabled!\n"));
1255 if (pVM->hm.s.fNestedPaging)
1256 {
1257 LogRel(("HM: Enabled nested paging\n"));
1258 LogRel(("HM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1259 if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_SINGLE_CONTEXT)
1260 LogRel(("HM: enmFlushEpt = VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));
1261 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_ALL_CONTEXTS)
1262 LogRel(("HM: enmFlushEpt = VMX_FLUSH_EPT_ALL_CONTEXTS\n"));
1263 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_NOT_SUPPORTED)
1264 LogRel(("HM: enmFlushEpt = VMX_FLUSH_EPT_NOT_SUPPORTED\n"));
1265 else
1266 LogRel(("HM: enmFlushEpt = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1267
1268 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1269 LogRel(("HM: Unrestricted guest execution enabled!\n"));
1270
1271#if HC_ARCH_BITS == 64
1272 if (pVM->hm.s.fLargePages)
1273 {
1274 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1275 PGMSetLargePageUsage(pVM, true);
1276 LogRel(("HM: Large page support enabled!\n"));
1277 }
1278#endif
1279 }
1280 else
1281 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1282
1283 if (pVM->hm.s.vmx.fVpid)
1284 {
1285 LogRel(("HM: Enabled VPID\n"));
1286 if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_INDIV_ADDR)
1287 LogRel(("HM: enmFlushVpid = VMX_FLUSH_VPID_INDIV_ADDR\n"));
1288 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT)
1289 LogRel(("HM: enmFlushVpid = VMX_FLUSH_VPID_SINGLE_CONTEXT\n"));
1290 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_ALL_CONTEXTS)
1291 LogRel(("HM: enmFlushVpid = VMX_FLUSH_VPID_ALL_CONTEXTS\n"));
1292 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1293 LogRel(("HM: enmFlushVpid = VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1294 else
1295 LogRel(("HM: enmFlushVpid = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1296 }
1297 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_NOT_SUPPORTED)
1298 LogRel(("HM: Ignoring VPID capabilities of CPU.\n"));
1299
1300 /* TPR patching status logging. */
1301 if (pVM->hm.s.fTRPPatchingAllowed)
1302 {
1303 if ( (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1304 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1305 {
1306 pVM->hm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1307 LogRel(("HM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1308 }
1309 else
1310 {
1311 uint32_t u32Eax, u32Dummy;
1312
1313 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1314 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1315 if ( u32Eax < 0x80000001
1316 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
1317 {
1318 pVM->hm.s.fTRPPatchingAllowed = false;
1319 LogRel(("HM: TPR patching disabled (long mode not supported).\n"));
1320 }
1321 }
1322 }
1323 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1324
1325 /*
1326 * Check for preemption timer config override and log the state of it.
1327 */
1328 if (pVM->hm.s.vmx.fUsePreemptTimer)
1329 {
1330 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM");
1331 int rc2 = CFGMR3QueryBoolDef(pCfgHm, "UsePreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
1332 AssertLogRelRC(rc2);
1333 }
1334 if (pVM->hm.s.vmx.fUsePreemptTimer)
1335 LogRel(("HM: Using the VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1336 }
1337 else
1338 {
1339 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1340 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1341 LogRel(("HM: CPU[%ld] Last instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
1342 pVM->fHMEnabled = false;
1343 }
1344 }
1345 }
1346 else
1347 if (pVM->hm.s.svm.fSupported)
1348 {
1349 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1350
1351 if (pVM->hm.s.fInitialized == false)
1352 {
1353 /* Erratum 170 which requires a forced TLB flush for each world switch:
1354 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1355 *
1356 * All BH-G1/2 and DH-G1/2 models include a fix:
1357 * Athlon X2: 0x6b 1/2
1358 * 0x68 1/2
1359 * Athlon 64: 0x7f 1
1360 * 0x6f 2
1361 * Sempron: 0x7f 1/2
1362 * 0x6f 2
1363 * 0x6c 2
1364 * 0x7c 2
1365 * Turion 64: 0x68 2
1366 *
1367 */
1368 uint32_t u32Dummy;
1369 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1370 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1371 u32BaseFamily= (u32Version >> 8) & 0xf;
1372 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1373 u32Model = ((u32Version >> 4) & 0xf);
1374 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1375 u32Stepping = u32Version & 0xf;
1376 if ( u32Family == 0xf
1377 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1378 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1379 {
1380 LogRel(("HM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1381 }
1382
1383 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1384 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1385 LogRel(("HM: AMD HWCR MSR = %RX64\n", pVM->hm.s.svm.msrHwcr));
1386 LogRel(("HM: AMD-V revision = %X\n", pVM->hm.s.svm.u32Rev));
1387 LogRel(("HM: AMD-V max ASID = %d\n", pVM->hm.s.uMaxAsid));
1388 LogRel(("HM: AMD-V features = %X\n", pVM->hm.s.svm.u32Features));
1389 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1390 {
1391#define FLAG_NAME(a_Define) { a_Define, #a_Define }
1392 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1393 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1394 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1395 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1396 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1397 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1398 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1399 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1400 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE),
1401 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1402 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1403#undef FLAG_NAME
1404 };
1405 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1406 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1407 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1408 {
1409 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1410 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1411 }
1412 if (fSvmFeatures)
1413 for (unsigned iBit = 0; iBit < 32; iBit++)
1414 if (RT_BIT_32(iBit) & fSvmFeatures)
1415 LogRel(("HM: Reserved bit %u\n", iBit));
1416
1417 /* Only try once. */
1418 pVM->hm.s.fInitialized = true;
1419
1420 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1421 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1422
1423 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1424 AssertRC(rc);
1425 if (rc == VINF_SUCCESS)
1426 {
1427 pVM->fHMEnabled = true;
1428 pVM->hm.s.svm.fEnabled = true;
1429
1430 if (pVM->hm.s.fNestedPaging)
1431 {
1432 LogRel(("HM: Enabled nested paging\n"));
1433#if HC_ARCH_BITS == 64
1434 if (pVM->hm.s.fLargePages)
1435 {
1436 /* Use large (2 MB) pages for our nested paging PDEs where possible. */
1437 PGMSetLargePageUsage(pVM, true);
1438 LogRel(("HM: Large page support enabled!\n"));
1439 }
1440#endif
1441 }
1442
1443 hmR3DisableRawMode(pVM);
1444 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1445 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1446#ifdef VBOX_ENABLE_64_BITS_GUESTS
1447 if (pVM->hm.s.fAllow64BitGuests)
1448 {
1449 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1450 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1451 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1452 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1453 }
1454 else
1455 /* Turn on NXE if PAE has been enabled. */
1456 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1457 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1458#endif
1459
1460 LogRel((pVM->hm.s.fAllow64BitGuests
1461 ? "HM: 32-bit and 64-bit guest supported.\n"
1462 : "HM: 32-bit guest supported.\n"));
1463
1464 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1465 }
1466 else
1467 {
1468 pVM->fHMEnabled = false;
1469 }
1470 }
1471 }
1472 if (pVM->fHMEnabled)
1473 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1474 RTLogRelSetBuffering(fOldBuffered);
1475 return VINF_SUCCESS;
1476}
1477
1478
1479/**
1480 * Applies relocations to data and code managed by this
1481 * component. This function will be called at init and
1482 * whenever the VMM need to relocate it self inside the GC.
1483 *
1484 * @param pVM The VM.
1485 */
1486VMMR3DECL(void) HMR3Relocate(PVM pVM)
1487{
1488 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1489
1490 /* Fetch the current paging mode during the relocate callback during state loading. */
1491 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1492 {
1493 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1494 {
1495 PVMCPU pVCpu = &pVM->aCpus[i];
1496
1497 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1498 Assert(pVCpu->hm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1499 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1500 }
1501 }
1502#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1503 if (pVM->fHMEnabled)
1504 {
1505 int rc;
1506 switch (PGMGetHostMode(pVM))
1507 {
1508 case PGMMODE_32_BIT:
1509 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1510 break;
1511
1512 case PGMMODE_PAE:
1513 case PGMMODE_PAE_NX:
1514 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1515 break;
1516
1517 default:
1518 AssertFailed();
1519 break;
1520 }
1521 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hm.s.pfnVMXGCStartVM64);
1522 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1523
1524 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hm.s.pfnSVMGCVMRun64);
1525 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1526
1527 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMSaveGuestFPU64", &pVM->hm.s.pfnSaveGuestFPU64);
1528 AssertReleaseMsgRC(rc, ("HMSetupFPU64 -> rc=%Rrc\n", rc));
1529
1530 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMSaveGuestDebug64", &pVM->hm.s.pfnSaveGuestDebug64);
1531 AssertReleaseMsgRC(rc, ("HMSetupDebug64 -> rc=%Rrc\n", rc));
1532
1533# ifdef DEBUG
1534 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMTestSwitcher64", &pVM->hm.s.pfnTest64);
1535 AssertReleaseMsgRC(rc, ("HMTestSwitcher64 -> rc=%Rrc\n", rc));
1536# endif
1537 }
1538#endif
1539 return;
1540}
1541
1542
1543/**
1544 * Checks if hardware accelerated raw mode is allowed.
1545 *
1546 * @returns true if hardware acceleration is allowed, otherwise false.
1547 * @param pVM Pointer to the VM.
1548 */
1549VMMR3DECL(bool) HMR3IsAllowed(PVM pVM)
1550{
1551 return pVM->hm.s.fAllowed;
1552}
1553
1554
1555/**
1556 * Notification callback which is called whenever there is a chance that a CR3
1557 * value might have changed.
1558 *
1559 * This is called by PGM.
1560 *
1561 * @param pVM Pointer to the VM.
1562 * @param pVCpu Pointer to the VMCPU.
1563 * @param enmShadowMode New shadow paging mode.
1564 * @param enmGuestMode New guest paging mode.
1565 */
1566VMMR3DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1567{
1568 /* Ignore page mode changes during state loading. */
1569 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1570 return;
1571
1572 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1573
1574 if ( pVM->hm.s.vmx.fEnabled
1575 && pVM->fHMEnabled)
1576 {
1577 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1578 && enmGuestMode >= PGMMODE_PROTECTED)
1579 {
1580 PCPUMCTX pCtx;
1581
1582 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1583
1584 /* After a real mode switch to protected mode we must force
1585 CPL to 0. Our real mode emulation had to set it to 3. */
1586 pCtx->ss.Attr.n.u2Dpl = 0;
1587 }
1588 }
1589
1590 if (pVCpu->hm.s.vmx.enmCurrGuestMode != enmGuestMode)
1591 {
1592 /* Keep track of paging mode changes. */
1593 pVCpu->hm.s.vmx.enmPrevGuestMode = pVCpu->hm.s.vmx.enmCurrGuestMode;
1594 pVCpu->hm.s.vmx.enmCurrGuestMode = enmGuestMode;
1595
1596 /* Did we miss a change, because all code was executed in the recompiler? */
1597 if (pVCpu->hm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1598 {
1599 Log(("HMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hm.s.vmx.enmPrevGuestMode),
1600 PGMGetModeName(pVCpu->hm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hm.s.vmx.enmLastSeenGuestMode)));
1601 pVCpu->hm.s.vmx.enmLastSeenGuestMode = pVCpu->hm.s.vmx.enmPrevGuestMode;
1602 }
1603 }
1604
1605 /* Reset the contents of the read cache. */
1606 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1607 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1608 pCache->Read.aFieldVal[j] = 0;
1609}
1610
1611
1612/**
1613 * Terminates the HM.
1614 *
1615 * Termination means cleaning up and freeing all resources,
1616 * the VM itself is, at this point, powered off or suspended.
1617 *
1618 * @returns VBox status code.
1619 * @param pVM Pointer to the VM.
1620 */
1621VMMR3DECL(int) HMR3Term(PVM pVM)
1622{
1623 if (pVM->hm.s.vmx.pRealModeTSS)
1624 {
1625 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1626 pVM->hm.s.vmx.pRealModeTSS = 0;
1627 }
1628 hmR3TermCPU(pVM);
1629 return 0;
1630}
1631
1632
1633/**
1634 * Terminates the per-VCPU HM.
1635 *
1636 * @returns VBox status code.
1637 * @param pVM Pointer to the VM.
1638 */
1639static int hmR3TermCPU(PVM pVM)
1640{
1641 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1642 {
1643 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1644
1645#ifdef VBOX_WITH_STATISTICS
1646 if (pVCpu->hm.s.paStatExitReason)
1647 {
1648 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1649 pVCpu->hm.s.paStatExitReason = NULL;
1650 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1651 }
1652 if (pVCpu->hm.s.paStatInjectedIrqs)
1653 {
1654 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1655 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1656 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1657 }
1658#endif
1659
1660#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1661 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1662 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1663 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1664#endif
1665 }
1666 return 0;
1667}
1668
1669
1670/**
1671 * Resets a virtual CPU.
1672 *
1673 * Used by HMR3Reset and CPU hot plugging.
1674 *
1675 * @param pVCpu The CPU to reset.
1676 */
1677VMMR3DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1678{
1679 /* On first entry we'll sync everything. */
1680 pVCpu->hm.s.fContextUseFlags = HM_CHANGED_ALL;
1681
1682 pVCpu->hm.s.vmx.cr0_mask = 0;
1683 pVCpu->hm.s.vmx.cr4_mask = 0;
1684
1685 pVCpu->hm.s.fActive = false;
1686 pVCpu->hm.s.Event.fPending = false;
1687
1688 /* Reset state information for real-mode emulation in VT-x. */
1689 pVCpu->hm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1690 pVCpu->hm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1691 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1692
1693 /* Reset the contents of the read cache. */
1694 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1695 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1696 pCache->Read.aFieldVal[j] = 0;
1697
1698#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1699 /* Magic marker for searching in crash dumps. */
1700 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1701 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1702#endif
1703}
1704
1705
1706/**
1707 * The VM is being reset.
1708 *
1709 * For the HM component this means that any GDT/LDT/TSS monitors
1710 * needs to be removed.
1711 *
1712 * @param pVM Pointer to the VM.
1713 */
1714VMMR3DECL(void) HMR3Reset(PVM pVM)
1715{
1716 LogFlow(("HMR3Reset:\n"));
1717
1718 if (pVM->fHMEnabled)
1719 hmR3DisableRawMode(pVM);
1720
1721 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1722 {
1723 PVMCPU pVCpu = &pVM->aCpus[i];
1724
1725 HMR3ResetCpu(pVCpu);
1726 }
1727
1728 /* Clear all patch information. */
1729 pVM->hm.s.pGuestPatchMem = 0;
1730 pVM->hm.s.pFreeGuestPatchMem = 0;
1731 pVM->hm.s.cbGuestPatchMem = 0;
1732 pVM->hm.s.cPatches = 0;
1733 pVM->hm.s.PatchTree = 0;
1734 pVM->hm.s.fTPRPatchingActive = false;
1735 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1736}
1737
1738
1739/**
1740 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1741 *
1742 * @returns VBox strict status code.
1743 * @param pVM Pointer to the VM.
1744 * @param pVCpu The VMCPU for the EMT we're being called on.
1745 * @param pvUser Unused.
1746 */
1747DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1748{
1749 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1750
1751 /* Only execute the handler on the VCPU the original patch request was issued. */
1752 if (pVCpu->idCpu != idCpu)
1753 return VINF_SUCCESS;
1754
1755 Log(("hmR3RemovePatches\n"));
1756 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1757 {
1758 uint8_t abInstr[15];
1759 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1760 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1761 int rc;
1762
1763#ifdef LOG_ENABLED
1764 char szOutput[256];
1765
1766 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1767 szOutput, sizeof(szOutput), NULL);
1768 if (RT_SUCCESS(rc))
1769 Log(("Patched instr: %s\n", szOutput));
1770#endif
1771
1772 /* Check if the instruction is still the same. */
1773 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1774 if (rc != VINF_SUCCESS)
1775 {
1776 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1777 continue; /* swapped out or otherwise removed; skip it. */
1778 }
1779
1780 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1781 {
1782 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1783 continue; /* skip it. */
1784 }
1785
1786 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1787 AssertRC(rc);
1788
1789#ifdef LOG_ENABLED
1790 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1791 szOutput, sizeof(szOutput), NULL);
1792 if (RT_SUCCESS(rc))
1793 Log(("Original instr: %s\n", szOutput));
1794#endif
1795 }
1796 pVM->hm.s.cPatches = 0;
1797 pVM->hm.s.PatchTree = 0;
1798 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1799 pVM->hm.s.fTPRPatchingActive = false;
1800 return VINF_SUCCESS;
1801}
1802
1803
1804/**
1805 * Worker for enabling patching in a VT-x/AMD-V guest.
1806 *
1807 * @returns VBox status code.
1808 * @param pVM Pointer to the VM.
1809 * @param idCpu VCPU to execute hmR3RemovePatches on.
1810 * @param pPatchMem Patch memory range.
1811 * @param cbPatchMem Size of the memory range.
1812 */
1813static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1814{
1815 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
1816 AssertRC(rc);
1817
1818 pVM->hm.s.pGuestPatchMem = pPatchMem;
1819 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
1820 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
1821 return VINF_SUCCESS;
1822}
1823
1824
1825/**
1826 * Enable patching in a VT-x/AMD-V guest
1827 *
1828 * @returns VBox status code.
1829 * @param pVM Pointer to the VM.
1830 * @param pPatchMem Patch memory range.
1831 * @param cbPatchMem Size of the memory range.
1832 */
1833VMMR3DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1834{
1835 VM_ASSERT_EMT(pVM);
1836 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1837 if (pVM->cCpus > 1)
1838 {
1839 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1840 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1841 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1842 AssertRC(rc);
1843 return rc;
1844 }
1845 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1846}
1847
1848
1849/**
1850 * Disable patching in a VT-x/AMD-V guest.
1851 *
1852 * @returns VBox status code.
1853 * @param pVM Pointer to the VM.
1854 * @param pPatchMem Patch memory range.
1855 * @param cbPatchMem Size of the memory range.
1856 */
1857VMMR3DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1858{
1859 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1860
1861 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
1862 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
1863
1864 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1865 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
1866 (void *)(uintptr_t)VMMGetCpuId(pVM));
1867 AssertRC(rc);
1868
1869 pVM->hm.s.pGuestPatchMem = 0;
1870 pVM->hm.s.pFreeGuestPatchMem = 0;
1871 pVM->hm.s.cbGuestPatchMem = 0;
1872 pVM->hm.s.fTPRPatchingActive = false;
1873 return VINF_SUCCESS;
1874}
1875
1876
1877/**
1878 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1879 *
1880 * @returns VBox strict status code.
1881 * @param pVM Pointer to the VM.
1882 * @param pVCpu The VMCPU for the EMT we're being called on.
1883 * @param pvUser User specified CPU context.
1884 *
1885 */
1886DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1887{
1888 /*
1889 * Only execute the handler on the VCPU the original patch request was
1890 * issued. (The other CPU(s) might not yet have switched to protected
1891 * mode, nor have the correct memory context.)
1892 */
1893 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1894 if (pVCpu->idCpu != idCpu)
1895 return VINF_SUCCESS;
1896
1897 /*
1898 * We're racing other VCPUs here, so don't try patch the instruction twice
1899 * and make sure there is still room for our patch record.
1900 */
1901 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1902 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1903 if (pPatch)
1904 {
1905 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
1906 return VINF_SUCCESS;
1907 }
1908 uint32_t const idx = pVM->hm.s.cPatches;
1909 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1910 {
1911 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1912 return VINF_SUCCESS;
1913 }
1914 pPatch = &pVM->hm.s.aPatches[idx];
1915
1916 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1917
1918 /*
1919 * Disassembler the instruction and get cracking.
1920 */
1921 DBGFR3DisasInstrCurrentLog(pVCpu, "hmR3ReplaceTprInstr");
1922 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1923 uint32_t cbOp;
1924 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1925 AssertRC(rc);
1926 if ( rc == VINF_SUCCESS
1927 && pDis->pCurInstr->uOpcode == OP_MOV
1928 && cbOp >= 3)
1929 {
1930 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
1931
1932 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1933 AssertRC(rc);
1934
1935 pPatch->cbOp = cbOp;
1936
1937 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1938 {
1939 /* write. */
1940 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
1941 {
1942 pPatch->enmType = HMTPRINSTR_WRITE_REG;
1943 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
1944 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
1945 }
1946 else
1947 {
1948 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
1949 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
1950 pPatch->uSrcOperand = pDis->Param2.uValue;
1951 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
1952 }
1953 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1954 AssertRC(rc);
1955
1956 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1957 pPatch->cbNewOp = sizeof(s_abVMMCall);
1958 }
1959 else
1960 {
1961 /*
1962 * TPR Read.
1963 *
1964 * Found:
1965 * mov eax, dword [fffe0080] (5 bytes)
1966 * Check if next instruction is:
1967 * shr eax, 4
1968 */
1969 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
1970
1971 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
1972 uint8_t const cbOpMmio = cbOp;
1973 uint64_t const uSavedRip = pCtx->rip;
1974
1975 pCtx->rip += cbOp;
1976 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1977 DBGFR3DisasInstrCurrentLog(pVCpu, "Following read");
1978 pCtx->rip = uSavedRip;
1979
1980 if ( rc == VINF_SUCCESS
1981 && pDis->pCurInstr->uOpcode == OP_SHR
1982 && pDis->Param1.fUse == DISUSE_REG_GEN32
1983 && pDis->Param1.Base.idxGenReg == idxMmioReg
1984 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
1985 && pDis->Param2.uValue == 4
1986 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
1987 {
1988 uint8_t abInstr[15];
1989
1990 /* Replacing two instructions now. */
1991 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
1992 AssertRC(rc);
1993
1994 pPatch->cbOp = cbOpMmio + cbOp;
1995
1996 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1997 abInstr[0] = 0xF0;
1998 abInstr[1] = 0x0F;
1999 abInstr[2] = 0x20;
2000 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
2001 for (unsigned i = 4; i < pPatch->cbOp; i++)
2002 abInstr[i] = 0x90; /* nop */
2003
2004 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2005 AssertRC(rc);
2006
2007 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2008 pPatch->cbNewOp = pPatch->cbOp;
2009
2010 Log(("Acceptable read/shr candidate!\n"));
2011 pPatch->enmType = HMTPRINSTR_READ_SHR4;
2012 }
2013 else
2014 {
2015 pPatch->enmType = HMTPRINSTR_READ;
2016 pPatch->uDstOperand = idxMmioReg;
2017
2018 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2019 AssertRC(rc);
2020
2021 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2022 pPatch->cbNewOp = sizeof(s_abVMMCall);
2023 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2024 }
2025 }
2026
2027 pPatch->Core.Key = pCtx->eip;
2028 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2029 AssertRC(rc);
2030
2031 pVM->hm.s.cPatches++;
2032 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccess);
2033 return VINF_SUCCESS;
2034 }
2035
2036 /*
2037 * Save invalid patch, so we will not try again.
2038 */
2039 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2040 pPatch->Core.Key = pCtx->eip;
2041 pPatch->enmType = HMTPRINSTR_INVALID;
2042 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2043 AssertRC(rc);
2044 pVM->hm.s.cPatches++;
2045 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2046 return VINF_SUCCESS;
2047}
2048
2049
2050/**
2051 * Callback to patch a TPR instruction (jump to generated code).
2052 *
2053 * @returns VBox strict status code.
2054 * @param pVM Pointer to the VM.
2055 * @param pVCpu The VMCPU for the EMT we're being called on.
2056 * @param pvUser User specified CPU context.
2057 *
2058 */
2059DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2060{
2061 /*
2062 * Only execute the handler on the VCPU the original patch request was
2063 * issued. (The other CPU(s) might not yet have switched to protected
2064 * mode, nor have the correct memory context.)
2065 */
2066 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2067 if (pVCpu->idCpu != idCpu)
2068 return VINF_SUCCESS;
2069
2070 /*
2071 * We're racing other VCPUs here, so don't try patch the instruction twice
2072 * and make sure there is still room for our patch record.
2073 */
2074 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2075 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2076 if (pPatch)
2077 {
2078 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2079 return VINF_SUCCESS;
2080 }
2081 uint32_t const idx = pVM->hm.s.cPatches;
2082 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2083 {
2084 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2085 return VINF_SUCCESS;
2086 }
2087 pPatch = &pVM->hm.s.aPatches[idx];
2088
2089 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2090 DBGFR3DisasInstrCurrentLog(pVCpu, "hmR3PatchTprInstr");
2091
2092 /*
2093 * Disassemble the instruction and get cracking.
2094 */
2095 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2096 uint32_t cbOp;
2097 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2098 AssertRC(rc);
2099 if ( rc == VINF_SUCCESS
2100 && pDis->pCurInstr->uOpcode == OP_MOV
2101 && cbOp >= 5)
2102 {
2103 uint8_t aPatch[64];
2104 uint32_t off = 0;
2105
2106 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2107 AssertRC(rc);
2108
2109 pPatch->cbOp = cbOp;
2110 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2111
2112 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2113 {
2114 /*
2115 * TPR write:
2116 *
2117 * push ECX [51]
2118 * push EDX [52]
2119 * push EAX [50]
2120 * xor EDX,EDX [31 D2]
2121 * mov EAX,EAX [89 C0]
2122 * or
2123 * mov EAX,0000000CCh [B8 CC 00 00 00]
2124 * mov ECX,0C0000082h [B9 82 00 00 C0]
2125 * wrmsr [0F 30]
2126 * pop EAX [58]
2127 * pop EDX [5A]
2128 * pop ECX [59]
2129 * jmp return_address [E9 return_address]
2130 *
2131 */
2132 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2133
2134 aPatch[off++] = 0x51; /* push ecx */
2135 aPatch[off++] = 0x52; /* push edx */
2136 if (!fUsesEax)
2137 aPatch[off++] = 0x50; /* push eax */
2138 aPatch[off++] = 0x31; /* xor edx, edx */
2139 aPatch[off++] = 0xD2;
2140 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2141 {
2142 if (!fUsesEax)
2143 {
2144 aPatch[off++] = 0x89; /* mov eax, src_reg */
2145 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2146 }
2147 }
2148 else
2149 {
2150 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2151 aPatch[off++] = 0xB8; /* mov eax, immediate */
2152 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2153 off += sizeof(uint32_t);
2154 }
2155 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2156 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2157 off += sizeof(uint32_t);
2158
2159 aPatch[off++] = 0x0F; /* wrmsr */
2160 aPatch[off++] = 0x30;
2161 if (!fUsesEax)
2162 aPatch[off++] = 0x58; /* pop eax */
2163 aPatch[off++] = 0x5A; /* pop edx */
2164 aPatch[off++] = 0x59; /* pop ecx */
2165 }
2166 else
2167 {
2168 /*
2169 * TPR read:
2170 *
2171 * push ECX [51]
2172 * push EDX [52]
2173 * push EAX [50]
2174 * mov ECX,0C0000082h [B9 82 00 00 C0]
2175 * rdmsr [0F 32]
2176 * mov EAX,EAX [89 C0]
2177 * pop EAX [58]
2178 * pop EDX [5A]
2179 * pop ECX [59]
2180 * jmp return_address [E9 return_address]
2181 *
2182 */
2183 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2184
2185 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2186 aPatch[off++] = 0x51; /* push ecx */
2187 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2188 aPatch[off++] = 0x52; /* push edx */
2189 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2190 aPatch[off++] = 0x50; /* push eax */
2191
2192 aPatch[off++] = 0x31; /* xor edx, edx */
2193 aPatch[off++] = 0xD2;
2194
2195 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2196 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2197 off += sizeof(uint32_t);
2198
2199 aPatch[off++] = 0x0F; /* rdmsr */
2200 aPatch[off++] = 0x32;
2201
2202 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2203 {
2204 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2205 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2206 }
2207
2208 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2209 aPatch[off++] = 0x58; /* pop eax */
2210 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2211 aPatch[off++] = 0x5A; /* pop edx */
2212 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2213 aPatch[off++] = 0x59; /* pop ecx */
2214 }
2215 aPatch[off++] = 0xE9; /* jmp return_address */
2216 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2217 off += sizeof(RTRCUINTPTR);
2218
2219 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2220 {
2221 /* Write new code to the patch buffer. */
2222 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2223 AssertRC(rc);
2224
2225#ifdef LOG_ENABLED
2226 uint32_t cbCurInstr;
2227 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2228 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2229 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2230 {
2231 char szOutput[256];
2232 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2233 szOutput, sizeof(szOutput), &cbCurInstr);
2234 if (RT_SUCCESS(rc))
2235 Log(("Patch instr %s\n", szOutput));
2236 else
2237 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2238 }
2239#endif
2240
2241 pPatch->aNewOpcode[0] = 0xE9;
2242 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2243
2244 /* Overwrite the TPR instruction with a jump. */
2245 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2246 AssertRC(rc);
2247
2248 DBGFR3DisasInstrCurrentLog(pVCpu, "Jump");
2249
2250 pVM->hm.s.pFreeGuestPatchMem += off;
2251 pPatch->cbNewOp = 5;
2252
2253 pPatch->Core.Key = pCtx->eip;
2254 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2255 AssertRC(rc);
2256
2257 pVM->hm.s.cPatches++;
2258 pVM->hm.s.fTPRPatchingActive = true;
2259 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2260 return VINF_SUCCESS;
2261 }
2262
2263 Log(("Ran out of space in our patch buffer!\n"));
2264 }
2265 else
2266 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2267
2268
2269 /*
2270 * Save invalid patch, so we will not try again.
2271 */
2272 pPatch = &pVM->hm.s.aPatches[idx];
2273 pPatch->Core.Key = pCtx->eip;
2274 pPatch->enmType = HMTPRINSTR_INVALID;
2275 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2276 AssertRC(rc);
2277 pVM->hm.s.cPatches++;
2278 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2279 return VINF_SUCCESS;
2280}
2281
2282
2283/**
2284 * Attempt to patch TPR mmio instructions.
2285 *
2286 * @returns VBox status code.
2287 * @param pVM Pointer to the VM.
2288 * @param pVCpu Pointer to the VMCPU.
2289 * @param pCtx Pointer to the guest CPU context.
2290 */
2291VMMR3DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2292{
2293 NOREF(pCtx);
2294 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2295 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2296 (void *)(uintptr_t)pVCpu->idCpu);
2297 AssertRC(rc);
2298 return rc;
2299}
2300
2301
2302/**
2303 * Force execution of the current IO code in the recompiler.
2304 *
2305 * @returns VBox status code.
2306 * @param pVM Pointer to the VM.
2307 * @param pCtx Partial VM execution context.
2308 */
2309VMMR3DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2310{
2311 PVMCPU pVCpu = VMMGetCpu(pVM);
2312
2313 Assert(pVM->fHMEnabled);
2314 Log(("HMR3EmulateIoBlock\n"));
2315
2316 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2317 if (HMCanEmulateIoBlockEx(pCtx))
2318 {
2319 Log(("HMR3EmulateIoBlock -> enabled\n"));
2320 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2321 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2322 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2323 return VINF_EM_RESCHEDULE_REM;
2324 }
2325 return VINF_SUCCESS;
2326}
2327
2328
2329/**
2330 * Checks if we can currently use hardware accelerated raw mode.
2331 *
2332 * @returns true if we can currently use hardware acceleration, otherwise false.
2333 * @param pVM Pointer to the VM.
2334 * @param pCtx Partial VM execution context.
2335 */
2336VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2337{
2338 PVMCPU pVCpu = VMMGetCpu(pVM);
2339
2340 Assert(pVM->fHMEnabled);
2341
2342 /* If we're still executing the IO code, then return false. */
2343 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2344 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2345 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2346 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2347 return false;
2348
2349 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2350
2351 /* AMD-V supports real & protected mode with or without paging. */
2352 if (pVM->hm.s.svm.fEnabled)
2353 {
2354 pVCpu->hm.s.fActive = true;
2355 return true;
2356 }
2357
2358 pVCpu->hm.s.fActive = false;
2359
2360 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2361 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2362 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2363
2364 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2365 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2366 {
2367 /*
2368 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2369 * guest execution feature i missing (VT-x only).
2370 */
2371 if (fSupportsRealMode)
2372 {
2373 if (CPUMIsGuestInRealModeEx(pCtx))
2374 {
2375 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2376 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2377 * If this is not true, we cannot execute real mode as V86 and have to fall
2378 * back to emulation.
2379 */
2380 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2381 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2382 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2383 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2384 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2385 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4)
2386 || (pCtx->cs.u32Limit != 0xffff)
2387 || (pCtx->ds.u32Limit != 0xffff)
2388 || (pCtx->es.u32Limit != 0xffff)
2389 || (pCtx->ss.u32Limit != 0xffff)
2390 || (pCtx->fs.u32Limit != 0xffff)
2391 || (pCtx->gs.u32Limit != 0xffff))
2392 {
2393 return false;
2394 }
2395 }
2396 else
2397 {
2398 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2399 /* Verify the requirements for executing code in protected
2400 mode. VT-x can't handle the CPU state right after a switch
2401 from real to protected mode. (all sorts of RPL & DPL assumptions) */
2402 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2403 && enmGuestMode >= PGMMODE_PROTECTED)
2404 {
2405 if ( (pCtx->cs.Sel & X86_SEL_RPL)
2406 || (pCtx->ds.Sel & X86_SEL_RPL)
2407 || (pCtx->es.Sel & X86_SEL_RPL)
2408 || (pCtx->fs.Sel & X86_SEL_RPL)
2409 || (pCtx->gs.Sel & X86_SEL_RPL)
2410 || (pCtx->ss.Sel & X86_SEL_RPL))
2411 {
2412 return false;
2413 }
2414 }
2415 /* VT-x also chokes on invalid tr or ldtr selectors (minix) */
2416 if ( pCtx->gdtr.cbGdt
2417 && ( pCtx->tr.Sel > pCtx->gdtr.cbGdt
2418 || pCtx->ldtr.Sel > pCtx->gdtr.cbGdt))
2419 {
2420 return false;
2421 }
2422 }
2423 }
2424 else
2425 {
2426 if ( !CPUMIsGuestInLongModeEx(pCtx)
2427 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2428 {
2429 /** @todo This should (probably) be set on every excursion to the REM,
2430 * however it's too risky right now. So, only apply it when we go
2431 * back to REM for real mode execution. (The XP hack below doesn't
2432 * work reliably without this.)
2433 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HM. */
2434 for (uint32_t i = 0; i < pVM->cCpus; i++)
2435 pVM->aCpus[i].hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2436
2437 if ( !pVM->hm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2438 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2439 return false;
2440
2441 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2442 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2443 return false;
2444
2445 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2446 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2447 * hidden registers (possible recompiler bug; see load_seg_vm) */
2448 if (pCtx->cs.Attr.n.u1Present == 0)
2449 return false;
2450 if (pCtx->ss.Attr.n.u1Present == 0)
2451 return false;
2452
2453 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2454 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2455 /** @todo This check is actually wrong, it doesn't take the direction of the
2456 * stack segment into account. But, it does the job for now. */
2457 if (pCtx->rsp >= pCtx->ss.u32Limit)
2458 return false;
2459#if 0
2460 if ( pCtx->cs.Sel >= pCtx->gdtr.cbGdt
2461 || pCtx->ss.Sel >= pCtx->gdtr.cbGdt
2462 || pCtx->ds.Sel >= pCtx->gdtr.cbGdt
2463 || pCtx->es.Sel >= pCtx->gdtr.cbGdt
2464 || pCtx->fs.Sel >= pCtx->gdtr.cbGdt
2465 || pCtx->gs.Sel >= pCtx->gdtr.cbGdt)
2466 return false;
2467#endif
2468 }
2469 }
2470 }
2471
2472 if (pVM->hm.s.vmx.fEnabled)
2473 {
2474 uint32_t mask;
2475
2476 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2477 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr0_fixed0;
2478 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2479 mask &= ~X86_CR0_NE;
2480
2481 if (fSupportsRealMode)
2482 {
2483 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2484 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2485 }
2486 else
2487 {
2488 /* We support protected mode without paging using identity mapping. */
2489 mask &= ~X86_CR0_PG;
2490 }
2491 if ((pCtx->cr0 & mask) != mask)
2492 return false;
2493
2494 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2495 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr0_fixed1;
2496 if ((pCtx->cr0 & mask) != 0)
2497 return false;
2498
2499 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2500 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr4_fixed0;
2501 mask &= ~X86_CR4_VMXE;
2502 if ((pCtx->cr4 & mask) != mask)
2503 return false;
2504
2505 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2506 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr4_fixed1;
2507 if ((pCtx->cr4 & mask) != 0)
2508 return false;
2509
2510 pVCpu->hm.s.fActive = true;
2511 return true;
2512 }
2513
2514 return false;
2515}
2516
2517
2518/**
2519 * Checks if we need to reschedule due to VMM device heap changes.
2520 *
2521 * @returns true if a reschedule is required, otherwise false.
2522 * @param pVM Pointer to the VM.
2523 * @param pCtx VM execution context.
2524 */
2525VMMR3DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2526{
2527 /*
2528 * The VMM device heap is a requirement for emulating real mode or protected mode without paging
2529 * when the unrestricted guest execution feature is missing (VT-x only).
2530 */
2531 if ( pVM->hm.s.vmx.fEnabled
2532 && !pVM->hm.s.vmx.fUnrestrictedGuest
2533 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2534 && !PDMVmmDevHeapIsEnabled(pVM)
2535 && (pVM->hm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2536 return true;
2537
2538 return false;
2539}
2540
2541
2542/**
2543 * Notification from EM about a rescheduling into hardware assisted execution
2544 * mode.
2545 *
2546 * @param pVCpu Pointer to the current VMCPU.
2547 */
2548VMMR3DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2549{
2550 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2551}
2552
2553
2554/**
2555 * Notification from EM about returning from instruction emulation (REM / EM).
2556 *
2557 * @param pVCpu Pointer to the VMCPU.
2558 */
2559VMMR3DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2560{
2561 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2562}
2563
2564
2565/**
2566 * Checks if we are currently using hardware accelerated raw mode.
2567 *
2568 * @returns true if hardware acceleration is being used, otherwise false.
2569 * @param pVCpu Pointer to the VMCPU.
2570 */
2571VMMR3DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2572{
2573 return pVCpu->hm.s.fActive;
2574}
2575
2576
2577/**
2578 * Checks if we are currently using nested paging.
2579 *
2580 * @returns true if nested paging is being used, otherwise false.
2581 * @param pVM Pointer to the VM.
2582 */
2583VMMR3DECL(bool) HMR3IsNestedPagingActive(PVM pVM)
2584{
2585 return pVM->hm.s.fNestedPaging;
2586}
2587
2588
2589/**
2590 * Checks if we are currently using VPID in VT-x mode.
2591 *
2592 * @returns true if VPID is being used, otherwise false.
2593 * @param pVM Pointer to the VM.
2594 */
2595VMMR3DECL(bool) HMR3IsVPIDActive(PVM pVM)
2596{
2597 return pVM->hm.s.vmx.fVpid;
2598}
2599
2600
2601/**
2602 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2603 *
2604 * @returns true if an internal event is pending, otherwise false.
2605 * @param pVM Pointer to the VM.
2606 */
2607VMMR3DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
2608{
2609 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
2610}
2611
2612
2613/**
2614 * Checks if the VMX-preemption timer is being used.
2615 *
2616 * @returns true if the VMX-preemption timer is being used, otherwise false.
2617 * @param pVM Pointer to the VM.
2618 */
2619VMMR3DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2620{
2621 return HMIsEnabled(pVM)
2622 && pVM->hm.s.vmx.fEnabled
2623 && pVM->hm.s.vmx.fUsePreemptTimer;
2624}
2625
2626
2627/**
2628 * Restart an I/O instruction that was refused in ring-0
2629 *
2630 * @returns Strict VBox status code. Informational status codes other than the one documented
2631 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2632 * @retval VINF_SUCCESS Success.
2633 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2634 * status code must be passed on to EM.
2635 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2636 *
2637 * @param pVM Pointer to the VM.
2638 * @param pVCpu Pointer to the VMCPU.
2639 * @param pCtx Pointer to the guest CPU context.
2640 */
2641VMMR3DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2642{
2643 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
2644
2645 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
2646
2647 if ( pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip
2648 || enmType == HMPENDINGIO_INVALID)
2649 return VERR_NOT_FOUND;
2650
2651 VBOXSTRICTRC rcStrict;
2652 switch (enmType)
2653 {
2654 case HMPENDINGIO_PORT_READ:
2655 {
2656 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
2657 uint32_t u32Val = 0;
2658
2659 rcStrict = IOMIOPortRead(pVM, pVCpu->hm.s.PendingIO.s.Port.uPort,
2660 &u32Val,
2661 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2662 if (IOM_SUCCESS(rcStrict))
2663 {
2664 /* Write back to the EAX register. */
2665 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2666 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2667 }
2668 break;
2669 }
2670
2671 case HMPENDINGIO_PORT_WRITE:
2672 rcStrict = IOMIOPortWrite(pVM, pVCpu->hm.s.PendingIO.s.Port.uPort,
2673 pCtx->eax & pVCpu->hm.s.PendingIO.s.Port.uAndVal,
2674 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2675 if (IOM_SUCCESS(rcStrict))
2676 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2677 break;
2678
2679 default:
2680 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2681 }
2682
2683 return rcStrict;
2684}
2685
2686
2687/**
2688 * Inject an NMI into a running VM (only VCPU 0!)
2689 *
2690 * @returns VBox status code.
2691 * @param pVM Pointer to the VM.
2692 */
2693VMMR3DECL(int) HMR3InjectNMI(PVM pVM)
2694{
2695 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2696 return VINF_SUCCESS;
2697}
2698
2699
2700/**
2701 * Check fatal VT-x/AMD-V error and produce some meaningful
2702 * log release message.
2703 *
2704 * @param pVM Pointer to the VM.
2705 * @param iStatusCode VBox status code.
2706 */
2707VMMR3DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2708{
2709 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2710 {
2711 switch (iStatusCode)
2712 {
2713 case VERR_VMX_INVALID_VMCS_FIELD:
2714 break;
2715
2716 case VERR_VMX_INVALID_VMCS_PTR:
2717 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hm.s.vmx.HCPhysVMCS));
2718 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32VMCSRevision));
2719 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idEnteredCpu));
2720 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idCurrentCpu));
2721 break;
2722
2723 case VERR_VMX_UNABLE_TO_START_VM:
2724 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
2725 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32ExitReason));
2726 if (pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2727 {
2728 LogRel(("VERR_VMX_UNABLE_TO_START_VM: Cpu%d MSRBitmapPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
2729#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
2730 LogRel(("VERR_VMX_UNABLE_TO_START_VM: Cpu%d GuestMSRPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysGuestMsr));
2731 LogRel(("VERR_VMX_UNABLE_TO_START_VM: Cpu%d HostMsrPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysHostMsr));
2732 LogRel(("VERR_VMX_UNABLE_TO_START_VM: Cpu%d cGuestMSRs %x\n", i, pVM->aCpus[i].hm.s.vmx.cGuestMsrs));
2733#endif
2734 }
2735 /** @todo Log VM-entry event injection control fields
2736 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
2737 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
2738 break;
2739
2740 case VERR_VMX_UNABLE_TO_RESUME_VM:
2741 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
2742 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32ExitReason));
2743 break;
2744
2745 case VERR_VMX_INVALID_VMXON_PTR:
2746 break;
2747 }
2748 }
2749
2750 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
2751 {
2752 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.allowed1));
2753 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0));
2754 }
2755}
2756
2757
2758/**
2759 * Execute state save operation.
2760 *
2761 * @returns VBox status code.
2762 * @param pVM Pointer to the VM.
2763 * @param pSSM SSM operation handle.
2764 */
2765static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
2766{
2767 int rc;
2768
2769 Log(("hmR3Save:\n"));
2770
2771 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2772 {
2773 /*
2774 * Save the basic bits - fortunately all the other things can be resynced on load.
2775 */
2776 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
2777 AssertRCReturn(rc, rc);
2778 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
2779 AssertRCReturn(rc, rc);
2780 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntrInfo);
2781 AssertRCReturn(rc, rc);
2782
2783 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode);
2784 AssertRCReturn(rc, rc);
2785 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode);
2786 AssertRCReturn(rc, rc);
2787 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode);
2788 AssertRCReturn(rc, rc);
2789 }
2790#ifdef VBOX_HM_WITH_GUEST_PATCHING
2791 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
2792 AssertRCReturn(rc, rc);
2793 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
2794 AssertRCReturn(rc, rc);
2795 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
2796 AssertRCReturn(rc, rc);
2797
2798 /* Store all the guest patch records too. */
2799 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
2800 AssertRCReturn(rc, rc);
2801
2802 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2803 {
2804 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2805
2806 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2807 AssertRCReturn(rc, rc);
2808
2809 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2810 AssertRCReturn(rc, rc);
2811
2812 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2813 AssertRCReturn(rc, rc);
2814
2815 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2816 AssertRCReturn(rc, rc);
2817
2818 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2819 AssertRCReturn(rc, rc);
2820
2821 AssertCompileSize(HMTPRINSTR, 4);
2822 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2823 AssertRCReturn(rc, rc);
2824
2825 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2826 AssertRCReturn(rc, rc);
2827
2828 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2829 AssertRCReturn(rc, rc);
2830
2831 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2832 AssertRCReturn(rc, rc);
2833
2834 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2835 AssertRCReturn(rc, rc);
2836 }
2837#endif
2838 return VINF_SUCCESS;
2839}
2840
2841
2842/**
2843 * Execute state load operation.
2844 *
2845 * @returns VBox status code.
2846 * @param pVM Pointer to the VM.
2847 * @param pSSM SSM operation handle.
2848 * @param uVersion Data layout version.
2849 * @param uPass The data pass.
2850 */
2851static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2852{
2853 int rc;
2854
2855 Log(("hmR3Load:\n"));
2856 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2857
2858 /*
2859 * Validate version.
2860 */
2861 if ( uVersion != HM_SSM_VERSION
2862 && uVersion != HM_SSM_VERSION_NO_PATCHING
2863 && uVersion != HM_SSM_VERSION_2_0_X)
2864 {
2865 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
2866 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2867 }
2868 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2869 {
2870 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
2871 AssertRCReturn(rc, rc);
2872 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
2873 AssertRCReturn(rc, rc);
2874 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntrInfo);
2875 AssertRCReturn(rc, rc);
2876
2877 if (uVersion >= HM_SSM_VERSION_NO_PATCHING)
2878 {
2879 uint32_t val;
2880
2881 rc = SSMR3GetU32(pSSM, &val);
2882 AssertRCReturn(rc, rc);
2883 pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2884
2885 rc = SSMR3GetU32(pSSM, &val);
2886 AssertRCReturn(rc, rc);
2887 pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2888
2889 rc = SSMR3GetU32(pSSM, &val);
2890 AssertRCReturn(rc, rc);
2891 pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2892 }
2893 }
2894#ifdef VBOX_HM_WITH_GUEST_PATCHING
2895 if (uVersion > HM_SSM_VERSION_NO_PATCHING)
2896 {
2897 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
2898 AssertRCReturn(rc, rc);
2899 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
2900 AssertRCReturn(rc, rc);
2901 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
2902 AssertRCReturn(rc, rc);
2903
2904 /* Fetch all TPR patch records. */
2905 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
2906 AssertRCReturn(rc, rc);
2907
2908 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2909 {
2910 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2911
2912 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2913 AssertRCReturn(rc, rc);
2914
2915 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2916 AssertRCReturn(rc, rc);
2917
2918 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2919 AssertRCReturn(rc, rc);
2920
2921 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2922 AssertRCReturn(rc, rc);
2923
2924 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2925 AssertRCReturn(rc, rc);
2926
2927 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2928 AssertRCReturn(rc, rc);
2929
2930 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
2931 pVM->hm.s.fTPRPatchingActive = true;
2932
2933 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
2934
2935 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2936 AssertRCReturn(rc, rc);
2937
2938 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2939 AssertRCReturn(rc, rc);
2940
2941 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2942 AssertRCReturn(rc, rc);
2943
2944 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2945 AssertRCReturn(rc, rc);
2946
2947 Log(("hmR3Load: patch %d\n", i));
2948 Log(("Key = %x\n", pPatch->Core.Key));
2949 Log(("cbOp = %d\n", pPatch->cbOp));
2950 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2951 Log(("type = %d\n", pPatch->enmType));
2952 Log(("srcop = %d\n", pPatch->uSrcOperand));
2953 Log(("dstop = %d\n", pPatch->uDstOperand));
2954 Log(("cFaults = %d\n", pPatch->cFaults));
2955 Log(("target = %x\n", pPatch->pJumpTarget));
2956 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2957 AssertRC(rc);
2958 }
2959 }
2960#endif
2961
2962 /* Recheck all VCPUs if we can go straight into hm execution mode. */
2963 if (HMIsEnabled(pVM))
2964 {
2965 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2966 {
2967 PVMCPU pVCpu = &pVM->aCpus[i];
2968
2969 HMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2970 }
2971 }
2972 return VINF_SUCCESS;
2973}
2974
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