HM.cpp@ 100101

Last change on this file since 100101 was 99809, checked in by vboxsync, 16 months ago
VMM/HM: Nested VMX: bugref:10318 Stat name change to make it easier to monitor both guest and nested-guest VM-exits more easily.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
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1	/* $Id: HM.cpp 99809 2023-05-16 06:46:21Z vboxsync $ */
2	/** @file
3	* HM - Intel/AMD VM Hardware Support Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	/** @page pg_hm HM - Hardware Assisted Virtualization Manager
29	*
30	* The HM manages guest execution using the VT-x and AMD-V CPU hardware
31	* extensions.
32	*
33	* {summary of what HM does}
34	*
35	* Hardware assisted virtualization manager was originally abbreviated HWACCM,
36	* however that was cumbersome to write and parse for such a central component,
37	* so it was shortened to HM when refactoring the code in the 4.3 development
38	* cycle.
39	*
40	* {add sections with more details}
41	*
42	* @sa @ref grp_hm
43	*/
44
45
46	/*********************************************************************************************************************************
47	* Header Files *
48	*********************************************************************************************************************************/
49	#define LOG_GROUP LOG_GROUP_HM
50	#define VMCPU_INCL_CPUM_GST_CTX
51	#include <VBox/vmm/cpum.h>
52	#include <VBox/vmm/stam.h>
53	#include <VBox/vmm/em.h>
54	#include <VBox/vmm/pdmapi.h>
55	#include <VBox/vmm/pgm.h>
56	#include <VBox/vmm/ssm.h>
57	#include <VBox/vmm/gim.h>
58	#include <VBox/vmm/gcm.h>
59	#include <VBox/vmm/trpm.h>
60	#include <VBox/vmm/dbgf.h>
61	#include <VBox/vmm/iom.h>
62	#include <VBox/vmm/iem.h>
63	#include <VBox/vmm/selm.h>
64	#include <VBox/vmm/nem.h>
65	#include <VBox/vmm/hm_vmx.h>
66	#include <VBox/vmm/hm_svm.h>
67	#include "HMInternal.h"
68	#include <VBox/vmm/vmcc.h>
69	#include <VBox/err.h>
70	#include <VBox/param.h>
71
72	#include <iprt/assert.h>
73	#include <VBox/log.h>
74	#include <iprt/asm.h>
75	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
76	# include <iprt/asm-amd64-x86.h>
77	#endif
78	#include <iprt/env.h>
79	#include <iprt/thread.h>
80
81
82	/*********************************************************************************************************************************
83	* Defined Constants And Macros *
84	*********************************************************************************************************************************/
85	/** @def HMVMX_REPORT_FEAT
86	* Reports VT-x feature to the release log.
87	*
88	* @param a_uAllowed1 Mask of allowed-1 feature bits.
89	* @param a_uAllowed0 Mask of allowed-0 feature bits.
90	* @param a_StrDesc The description string to report.
91	* @param a_Featflag Mask of the feature to report.
92	*/
93	#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
94	do { \
95	if ((a_uAllowed1) & (a_Featflag)) \
96	{ \
97	if ((a_uAllowed0) & (a_Featflag)) \
98	LogRel(("HM: " a_StrDesc " (must be set)\n")); \
99	else \
100	LogRel(("HM: " a_StrDesc "\n")); \
101	} \
102	else \
103	LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
104	} while (0)
105
106	/** @def HMVMX_REPORT_ALLOWED_FEAT
107	* Reports an allowed VT-x feature to the release log.
108	*
109	* @param a_uAllowed1 Mask of allowed-1 feature bits.
110	* @param a_StrDesc The description string to report.
111	* @param a_FeatFlag Mask of the feature to report.
112	*/
113	#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
114	do { \
115	if ((a_uAllowed1) & (a_FeatFlag)) \
116	LogRel(("HM: " a_StrDesc "\n")); \
117	else \
118	LogRel(("HM: " a_StrDesc " not supported\n")); \
119	} while (0)
120
121	/** @def HMVMX_REPORT_MSR_CAP
122	* Reports MSR feature capability.
123	*
124	* @param a_MsrCaps Mask of MSR feature bits.
125	* @param a_StrDesc The description string to report.
126	* @param a_fCap Mask of the feature to report.
127	*/
128	#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
129	do { \
130	if ((a_MsrCaps) & (a_fCap)) \
131	LogRel(("HM: " a_StrDesc "\n")); \
132	} while (0)
133
134	/** @def HMVMX_LOGREL_FEAT
135	* Dumps a feature flag from a bitmap of features to the release log.
136	*
137	* @param a_fVal The value of all the features.
138	* @param a_fMask The specific bitmask of the feature.
139	*/
140	#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
141	do { \
142	if ((a_fVal) & (a_fMask)) \
143	LogRel(("HM: %s\n", #a_fMask)); \
144	} while (0)
145
146
147	/*********************************************************************************************************************************
148	* Internal Functions *
149	*********************************************************************************************************************************/
150	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
151	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
152	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
153	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
154	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
155	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
156	static int hmR3InitFinalizeR3(PVM pVM);
157	static int hmR3InitFinalizeR0(PVM pVM);
158	static int hmR3InitFinalizeR0Intel(PVM pVM);
159	static int hmR3InitFinalizeR0Amd(PVM pVM);
160	static int hmR3TermCPU(PVM pVM);
161
162
163	#ifdef VBOX_WITH_STATISTICS
164	/**
165	* Returns the name of the hardware exception.
166	*
167	* @returns The name of the hardware exception.
168	* @param uVector The exception vector.
169	*/
170	static const char *hmR3GetXcptName(uint8_t uVector)
171	{
172	switch (uVector)
173	{
174	case X86_XCPT_DE: return "#DE";
175	case X86_XCPT_DB: return "#DB";
176	case X86_XCPT_NMI: return "#NMI";
177	case X86_XCPT_BP: return "#BP";
178	case X86_XCPT_OF: return "#OF";
179	case X86_XCPT_BR: return "#BR";
180	case X86_XCPT_UD: return "#UD";
181	case X86_XCPT_NM: return "#NM";
182	case X86_XCPT_DF: return "#DF";
183	case X86_XCPT_CO_SEG_OVERRUN: return "#CO_SEG_OVERRUN";
184	case X86_XCPT_TS: return "#TS";
185	case X86_XCPT_NP: return "#NP";
186	case X86_XCPT_SS: return "#SS";
187	case X86_XCPT_GP: return "#GP";
188	case X86_XCPT_PF: return "#PF";
189	case X86_XCPT_MF: return "#MF";
190	case X86_XCPT_AC: return "#AC";
191	case X86_XCPT_MC: return "#MC";
192	case X86_XCPT_XF: return "#XF";
193	case X86_XCPT_VE: return "#VE";
194	case X86_XCPT_CP: return "#CP";
195	case X86_XCPT_VC: return "#VC";
196	case X86_XCPT_SX: return "#SX";
197	}
198	return "Reserved";
199	}
200	#endif /* VBOX_WITH_STATISTICS */
201
202
203	/**
204	* Initializes the HM.
205	*
206	* This is the very first component to really do init after CFGM so that we can
207	* establish the predominant execution engine for the VM prior to initializing
208	* other modules. It takes care of NEM initialization if needed (HM disabled or
209	* not available in HW).
210	*
211	* If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
212	* hypervisor API via NEM, and then back on raw-mode if that isn't available
213	* either. The fallback to raw-mode will not happen if /HM/HMForced is set
214	* (like for guest using SMP or 64-bit as well as for complicated guest like OS
215	* X, OS/2 and others).
216	*
217	* Note that a lot of the set up work is done in ring-0 and thus postponed till
218	* the ring-3 and ring-0 callback to HMR3InitCompleted.
219	*
220	* @returns VBox status code.
221	* @param pVM The cross context VM structure.
222	*
223	* @remarks Be careful with what we call here, since most of the VMM components
224	* are uninitialized.
225	*/
226	VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
227	{
228	LogFlowFunc(("\n"));
229
230	/*
231	* Assert alignment and sizes.
232	*/
233	AssertCompileMemberAlignment(VM, hm.s, 32);
234	AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
235
236	/*
237	* Register the saved state data unit.
238	*/
239	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
240	NULL, NULL, NULL,
241	NULL, hmR3Save, NULL,
242	NULL, hmR3Load, NULL);
243	if (RT_FAILURE(rc))
244	return rc;
245
246	/*
247	* Read configuration.
248	*/
249	PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
250
251	/*
252	* Validate the HM settings.
253	*/
254	rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
255	"HMForced" /* implied 'true' these days */
256	"\|UseNEMInstead"
257	"\|FallbackToNEM"
258	"\|FallbackToIEM"
259	"\|EnableNestedPaging"
260	"\|EnableUX"
261	"\|EnableLargePages"
262	"\|EnableVPID"
263	"\|IBPBOnVMExit"
264	"\|IBPBOnVMEntry"
265	"\|SpecCtrlByHost"
266	"\|L1DFlushOnSched"
267	"\|L1DFlushOnVMEntry"
268	"\|MDSClearOnSched"
269	"\|MDSClearOnVMEntry"
270	"\|TPRPatchingEnabled"
271	"\|64bitEnabled"
272	"\|Exclusive"
273	"\|MaxResumeLoops"
274	"\|VmxPleGap"
275	"\|VmxPleWindow"
276	"\|VmxLbr"
277	"\|UseVmxPreemptTimer"
278	"\|SvmPauseFilter"
279	"\|SvmPauseFilterThreshold"
280	"\|SvmVirtVmsaveVmload"
281	"\|SvmVGif"
282	"\|LovelyMesaDrvWorkaround"
283	"\|MissingOS2TlbFlushWorkaround"
284	"\|AlwaysInterceptVmxMovDRx"
285	, "" /* pszValidNodes /, "HM" / pszWho /, 0 / uInstance */);
286	if (RT_FAILURE(rc))
287	return rc;
288
289	/** @cfgm{/HM/HMForced, bool, false}
290	* Forces hardware virtualization, no falling back on raw-mode. HM must be
291	* enabled, i.e. /HMEnabled must be true. */
292	bool const fHMForced = true;
293	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
294	AssertRelease(pVM->fHMEnabled);
295	#else
296	AssertRelease(!pVM->fHMEnabled);
297	#endif
298
299	/** @cfgm{/HM/UseNEMInstead, bool, true}
300	* Don't use HM, use NEM instead. */
301	bool fUseNEMInstead = false;
302	rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
303	AssertRCReturn(rc, rc);
304	if (fUseNEMInstead && pVM->fHMEnabled)
305	{
306	LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
307	pVM->fHMEnabled = false;
308	}
309
310	/** @cfgm{/HM/FallbackToNEM, bool, true}
311	* Enables fallback on NEM. */
312	bool fFallbackToNEM = true;
313	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
314	AssertRCReturn(rc, rc);
315
316	/** @cfgm{/HM/FallbackToIEM, bool, false on AMD64 else true }
317	* Enables fallback on NEM. */
318	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
319	bool fFallbackToIEM = false;
320	#else
321	bool fFallbackToIEM = true;
322	#endif
323	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToIEM", &fFallbackToIEM, fFallbackToIEM);
324	AssertRCReturn(rc, rc);
325
326	/** @cfgm{/HM/EnableNestedPaging, bool, false}
327	* Enables nested paging (aka extended page tables). */
328	bool fAllowNestedPaging = false;
329	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &fAllowNestedPaging, false);
330	AssertRCReturn(rc, rc);
331
332	/** @cfgm{/HM/EnableUX, bool, true}
333	* Enables the VT-x unrestricted execution feature. */
334	bool fAllowUnrestricted = true;
335	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &fAllowUnrestricted, true);
336	AssertRCReturn(rc, rc);
337
338	/** @cfgm{/HM/EnableLargePages, bool, false}
339	* Enables using large pages (2 MB) for guest memory, thus saving on (nested)
340	* page table walking and maybe better TLB hit rate in some cases. */
341	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
342	AssertRCReturn(rc, rc);
343
344	/** @cfgm{/HM/EnableVPID, bool, false}
345	* Enables the VT-x VPID feature. */
346	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
347	AssertRCReturn(rc, rc);
348
349	/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
350	* Enables TPR patching for 32-bit windows guests with IO-APIC. */
351	rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
352	AssertRCReturn(rc, rc);
353
354	/** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
355	* Enables AMD64 cpu features.
356	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
357	* already have the support. */
358	#ifdef VBOX_WITH_64_BITS_GUESTS
359	rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuestsCfg, HC_ARCH_BITS == 64);
360	AssertLogRelRCReturn(rc, rc);
361	#else
362	pVM->hm.s.fAllow64BitGuestsCfg = false;
363	#endif
364
365	/** @cfgm{/HM/VmxPleGap, uint32_t, 0}
366	* The pause-filter exiting gap in TSC ticks. When the number of ticks between
367	* two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
368	* latest PAUSE instruction to be start of a new PAUSE loop.
369	*/
370	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
371	AssertRCReturn(rc, rc);
372
373	/** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
374	* The pause-filter exiting window in TSC ticks. When the number of ticks
375	* between the current PAUSE instruction and first PAUSE of a loop exceeds
376	* VmxPleWindow, a VM-exit is triggered.
377	*
378	* Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
379	*/
380	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
381	AssertRCReturn(rc, rc);
382
383	/** @cfgm{/HM/VmxLbr, bool, false}
384	* Whether to enable LBR for the guest. This is disabled by default as it's only
385	* useful while debugging and enabling it causes a noticeable performance hit. */
386	rc = CFGMR3QueryBoolDef(pCfgHm, "VmxLbr", &pVM->hm.s.vmx.fLbrCfg, false);
387	AssertRCReturn(rc, rc);
388
389	/** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
390	* A counter that is decrement each time a PAUSE instruction is executed by the
391	* guest. When the counter is 0, a \#VMEXIT is triggered.
392	*
393	* Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
394	*/
395	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
396	AssertRCReturn(rc, rc);
397
398	/** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
399	* The pause filter threshold in ticks. When the elapsed time (in ticks) between
400	* two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
401	* PauseFilter count is reset to its initial value. However, if PAUSE is
402	* executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
403	* be triggered.
404	*
405	* Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
406	* activated.
407	*/
408	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
409	AssertRCReturn(rc, rc);
410
411	/** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
412	* Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
413	* available. */
414	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
415	AssertRCReturn(rc, rc);
416
417	/** @cfgm{/HM/SvmVGif, bool, true}
418	* Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
419	* if it's available. */
420	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
421	AssertRCReturn(rc, rc);
422
423	/** @cfgm{/HM/SvmLbrVirt, bool, false}
424	* Whether to make use of the LBR virtualization feature of the CPU if it's
425	* available. This is disabled by default as it's only useful while debugging
426	* and enabling it causes a small hit to performance. */
427	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmLbrVirt", &pVM->hm.s.svm.fLbrVirt, false);
428	AssertRCReturn(rc, rc);
429
430	/** @cfgm{/HM/Exclusive, bool}
431	* Determines the init method for AMD-V and VT-x. If set to true, HM will do a
432	* global init for each host CPU. If false, we do local init each time we wish
433	* to execute guest code.
434	*
435	* On Windows, default is false due to the higher risk of conflicts with other
436	* hypervisors.
437	*
438	* On Mac OS X, this setting is ignored since the code does not handle local
439	* init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
440	*/
441	#if defined(RT_OS_DARWIN)
442	pVM->hm.s.fGlobalInit = true;
443	#else
444	rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
445	# if defined(RT_OS_WINDOWS)
446	false
447	# else
448	true
449	# endif
450	);
451	AssertLogRelRCReturn(rc, rc);
452	#endif
453
454	/** @cfgm{/HM/MaxResumeLoops, uint32_t}
455	* The number of times to resume guest execution before we forcibly return to
456	* ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
457	* determines the default value. */
458	rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoopsCfg, 0 /* set by R0 later */);
459	AssertLogRelRCReturn(rc, rc);
460
461	/** @cfgm{/HM/UseVmxPreemptTimer, bool}
462	* Whether to make use of the VMX-preemption timer feature of the CPU if it's
463	* available. */
464	rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimerCfg, true);
465	AssertLogRelRCReturn(rc, rc);
466
467	/** @cfgm{/HM/IBPBOnVMExit, bool}
468	* Costly paranoia setting. */
469	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
470	AssertLogRelRCReturn(rc, rc);
471
472	/** @cfgm{/HM/IBPBOnVMEntry, bool}
473	* Costly paranoia setting. */
474	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
475	AssertLogRelRCReturn(rc, rc);
476
477	/** @cfgm{/HM/L1DFlushOnSched, bool, true}
478	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
479	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
480	AssertLogRelRCReturn(rc, rc);
481
482	/** @cfgm{/HM/L1DFlushOnVMEntry, bool}
483	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
484	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
485	AssertLogRelRCReturn(rc, rc);
486
487	/* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
488	if (pVM->hm.s.fL1dFlushOnVmEntry)
489	pVM->hm.s.fL1dFlushOnSched = false;
490
491	/** @cfgm{/HM/SpecCtrlByHost, bool}
492	* Another expensive paranoia setting. */
493	rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
494	AssertLogRelRCReturn(rc, rc);
495
496	/** @cfgm{/HM/MDSClearOnSched, bool, true}
497	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
498	* ignored on CPUs that aren't affected. */
499	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
500	AssertLogRelRCReturn(rc, rc);
501
502	/** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
503	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
504	* ignored on CPUs that aren't affected. */
505	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
506	AssertLogRelRCReturn(rc, rc);
507
508	/* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
509	if (pVM->hm.s.fMdsClearOnVmEntry)
510	pVM->hm.s.fMdsClearOnSched = false;
511
512	/** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
513	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
514	* the hypervisor it is running under. */
515	bool fMesaWorkaround;
516	rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &fMesaWorkaround, false);
517	AssertLogRelRCReturn(rc, rc);
518	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
519	{
520	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
521	pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv = fMesaWorkaround;
522	}
523
524	/** @cfgm{/HM/MissingOS2TlbFlushWorkaround,bool}
525	* Workaround OS/2 not flushing the TLB after page directory and page table
526	* modifications when returning to protected mode from a real mode call
527	* (TESTCFG.SYS typically crashes). See ticketref:20625 for details. */
528	rc = CFGMR3QueryBoolDef(pCfgHm, "MissingOS2TlbFlushWorkaround", &pVM->hm.s.fMissingOS2TlbFlushWorkaround, false);
529	AssertLogRelRCReturn(rc, rc);
530
531	/** @cfgm{/HM/AlwaysInterceptVmxMovDRx,int8_t,0}
532	* Whether to always intercept MOV DRx when using VMX.
533	* The value is a tristate: 1 for always intercepting, -1 for lazy intercept,
534	* and 0 for default. The default means that it's always intercepted when the
535	* host DR6 contains bits not known to the guest.
536	*
537	* With the introduction of transactional synchronization extensions new
538	* instructions, aka TSX-NI or RTM, bit 16 in DR6 is cleared to indicate that a
539	* \#DB was related to a transaction. The bit is also cleared when writing zero
540	* to it, so guest lazily resetting DR6 by writing 0 to it, ends up with an
541	* unexpected value. Similiarly, bit 11 in DR7 is used to enabled RTM
542	* debugging support and therefore writable by the guest.
543	*
544	* Out of caution/paranoia, we will by default intercept DRx moves when setting
545	* DR6 to zero (on the host) doesn't result in 0xffff0ff0 (X86_DR6_RA1_MASK).
546	* Note that it seems DR6.RTM remains writable even after the microcode updates
547	* disabling TSX. */
548	rc = CFGMR3QueryS8Def(pCfgHm, "AlwaysInterceptVmxMovDRx", &pVM->hm.s.vmx.fAlwaysInterceptMovDRxCfg, 0);
549	AssertLogRelRCReturn(rc, rc);
550
551	/*
552	* Check if VT-x or AMD-v support according to the users wishes.
553	*/
554	/** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
555	* VERR_SVM_IN_USE. */
556	if (pVM->fHMEnabled)
557	{
558	uint32_t fCaps;
559	rc = SUPR3QueryVTCaps(&fCaps);
560	if (RT_SUCCESS(rc))
561	{
562	if (fCaps & SUPVTCAPS_AMD_V)
563	{
564	pVM->hm.s.svm.fSupported = true;
565	LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
566	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
567	}
568	else if (fCaps & SUPVTCAPS_VT_X)
569	{
570	const char *pszWhy;
571	rc = SUPR3QueryVTxSupported(&pszWhy);
572	if (RT_SUCCESS(rc))
573	{
574	pVM->hm.s.vmx.fSupported = true;
575	LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
576	fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
577	fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
578	(fCaps & (SUPVTCAPS_NESTED_PAGING \| SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
579	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
580	}
581	else
582	{
583	/*
584	* Before failing, try fallback to NEM if we're allowed to do that.
585	*/
586	pVM->fHMEnabled = false;
587	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
588	if (fFallbackToNEM)
589	{
590	LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
591	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
592
593	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
594	if ( RT_SUCCESS(rc2)
595	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
596	rc = VINF_SUCCESS;
597	}
598	if (RT_FAILURE(rc))
599	return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
600	}
601	}
602	else
603	AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
604	VERR_INTERNAL_ERROR_5);
605
606	/*
607	* Disable nested paging and unrestricted guest execution now if they're
608	* configured so that CPUM can make decisions based on our configuration.
609	*/
610	if ( fAllowNestedPaging
611	&& (fCaps & SUPVTCAPS_NESTED_PAGING))
612	{
613	pVM->hm.s.fNestedPagingCfg = true;
614	if (fCaps & SUPVTCAPS_VT_X)
615	{
616	if ( fAllowUnrestricted
617	&& (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST))
618	pVM->hm.s.vmx.fUnrestrictedGuestCfg = true;
619	else
620	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
621	}
622	}
623	else
624	Assert(!pVM->hm.s.fNestedPagingCfg);
625	}
626	else
627	{
628	const char *pszMsg;
629	switch (rc)
630	{
631	case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
632	case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
633	case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
634	case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
635	case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
636	case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
637	case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
638	case VERR_SUP_DRIVERLESS: pszMsg = "Driverless mode"; break;
639	default:
640	return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
641	}
642
643	/*
644	* Before failing, try fallback to NEM if we're allowed to do that.
645	*/
646	pVM->fHMEnabled = false;
647	if (fFallbackToNEM)
648	{
649	LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
650	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
651	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
652	if ( RT_SUCCESS(rc2)
653	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
654	{
655	rc = VINF_SUCCESS;
656
657	/* For some reason, HM is in charge or large pages. Make sure to enable them: */
658	PGMSetLargePageUsage(pVM, pVM->hm.s.fLargePages);
659	}
660	}
661
662	/*
663	* Then try fall back on IEM if NEM isn't available and we're allowed to.
664	*/
665	if (RT_FAILURE(rc))
666	{
667	if ( fFallbackToIEM
668	&& (!fFallbackToNEM \|\| rc == VERR_NEM_NOT_AVAILABLE \|\| rc == VERR_SUP_DRIVERLESS))
669	{
670	LogRel(("HM: HMR3Init: Falling back on IEM: %s\n", !fFallbackToNEM ? pszMsg : "NEM not available"));
671	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_IEM);
672	#ifdef VBOX_WITH_PGM_NEM_MODE
673	PGMR3EnableNemMode(pVM);
674	#endif
675	}
676	else
677	return VM_SET_ERROR(pVM, rc, pszMsg);
678	}
679	}
680	}
681	else
682	{
683	/*
684	* Disabled HM mean raw-mode, unless NEM is supposed to be used.
685	*/
686	rc = VERR_NEM_NOT_AVAILABLE;
687	if (fUseNEMInstead)
688	{
689	rc = NEMR3Init(pVM, false /fFallback/, true);
690	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
691	if (RT_SUCCESS(rc))
692	{
693	/* For some reason, HM is in charge or large pages. Make sure to enable them: */
694	PGMSetLargePageUsage(pVM, pVM->hm.s.fLargePages);
695	}
696	else if (!fFallbackToIEM \|\| rc != VERR_NEM_NOT_AVAILABLE)
697	return rc;
698	}
699
700	if (fFallbackToIEM && rc == VERR_NEM_NOT_AVAILABLE)
701	{
702	LogRel(("HM: HMR3Init: Falling back on IEM%s\n", fUseNEMInstead ? ": NEM not available" : ""));
703	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_IEM);
704	#ifdef VBOX_WITH_PGM_NEM_MODE
705	PGMR3EnableNemMode(pVM);
706	#endif
707	}
708
709	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET
710	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT /* paranoia */)
711	return VM_SET_ERROR(pVM, rc, "Misconfigured VM: No guest execution engine available!");
712	}
713
714	if (pVM->fHMEnabled)
715	{
716	/*
717	* Register info handlers now that HM is used for sure.
718	*/
719	rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
720	AssertRCReturn(rc, rc);
721
722	rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
723	DBGFINFO_FLAGS_ALL_EMTS);
724	AssertRCReturn(rc, rc);
725
726	rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
727	hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
728	AssertRCReturn(rc, rc);
729
730	rc = DBGFR3InfoRegisterInternalEx(pVM, "lbr", "Dumps the HM LBR info.", hmR3InfoLbr, DBGFINFO_FLAGS_ALL_EMTS);
731	AssertRCReturn(rc, rc);
732	}
733
734	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
735	return VINF_SUCCESS;
736	}
737
738
739	/**
740	* Initializes HM components after ring-3 phase has been fully initialized.
741	*
742	* @returns VBox status code.
743	* @param pVM The cross context VM structure.
744	*/
745	static int hmR3InitFinalizeR3(PVM pVM)
746	{
747	LogFlowFunc(("\n"));
748
749	if (!HMIsEnabled(pVM))
750	return VINF_SUCCESS;
751
752	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
753	{
754	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
755	pVCpu->hm.s.fActive = false;
756	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
757	pVCpu->hm.s.fGCMTrapXcptDE = GCMShouldTrapXcptDE(pVCpu); /* Is safe to call now since GCMR3Init() has completed. */
758	}
759
760	#if defined(RT_ARCH_AMD64) \|\|defined(RT_ARCH_X86)
761	/*
762	* Check if L1D flush is needed/possible.
763	*/
764	if ( !g_CpumHostFeatures.s.fFlushCmd
765	\|\| g_CpumHostFeatures.s.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
766	\|\| g_CpumHostFeatures.s.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
767	\|\| g_CpumHostFeatures.s.fArchVmmNeedNotFlushL1d
768	\|\| g_CpumHostFeatures.s.fArchRdclNo)
769	pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
770
771	/*
772	* Check if MDS flush is needed/possible.
773	* On atoms and knight family CPUs, we will only allow clearing on scheduling.
774	*/
775	if ( !g_CpumHostFeatures.s.fMdsClear
776	\|\| g_CpumHostFeatures.s.fArchMdsNo)
777	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
778	else if ( ( g_CpumHostFeatures.s.enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
779	&& g_CpumHostFeatures.s.enmMicroarch < kCpumMicroarch_Intel_Atom_End)
780	\|\| ( g_CpumHostFeatures.s.enmMicroarch >= kCpumMicroarch_Intel_Phi_KnightsLanding
781	&& g_CpumHostFeatures.s.enmMicroarch < kCpumMicroarch_Intel_Phi_End))
782	{
783	if (!pVM->hm.s.fMdsClearOnSched)
784	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
785	pVM->hm.s.fMdsClearOnVmEntry = false;
786	}
787	else if ( g_CpumHostFeatures.s.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
788	\|\| g_CpumHostFeatures.s.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
789	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
790	#endif
791
792	/*
793	* Statistics.
794	*/
795	#ifdef VBOX_WITH_STATISTICS
796	STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
797	STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
798	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8", STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
799	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC", STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
800	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
801	#endif
802
803	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
804	bool const fCpuSupportsVmx = ASMIsIntelCpu() \|\| ASMIsViaCentaurCpu() \|\| ASMIsShanghaiCpu();
805	#else
806	bool const fCpuSupportsVmx = false;
807	#endif
808	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
809	{
810	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
811	PHMCPU pHmCpu = &pVCpu->hm.s;
812	int rc;
813
814	# define HM_REG_STAT(a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szNmFmt, a_szDesc) do { \
815	rc = STAMR3RegisterF(pVM, a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szDesc, a_szNmFmt, idCpu); \
816	AssertRC(rc); \
817	} while (0)
818	# define HM_REG_PROFILE(a_pVar, a_szNmFmt, a_szDesc) \
819	HM_REG_STAT(a_pVar, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, a_szNmFmt, a_szDesc)
820
821	#ifdef VBOX_WITH_STATISTICS
822	HM_REG_PROFILE(&pHmCpu->StatPoke, "/PROF/CPU%u/HM/Poke", "Profiling of RTMpPokeCpu.");
823	HM_REG_PROFILE(&pHmCpu->StatSpinPoke, "/PROF/CPU%u/HM/PokeWait", "Profiling of poke wait.");
824	HM_REG_PROFILE(&pHmCpu->StatSpinPokeFailed, "/PROF/CPU%u/HM/PokeWaitFailed", "Profiling of poke wait when RTMpPokeCpu fails.");
825	HM_REG_PROFILE(&pHmCpu->StatEntry, "/PROF/CPU%u/HM/Entry", "Profiling of entry until entering GC.");
826	HM_REG_PROFILE(&pHmCpu->StatPreExit, "/PROF/CPU%u/HM/SwitchFromGC_1", "Profiling of pre-exit processing after returning from GC.");
827	HM_REG_PROFILE(&pHmCpu->StatExitHandling, "/PROF/CPU%u/HM/SwitchFromGC_2", "Profiling of exit handling (longjmps not included!)");
828	HM_REG_PROFILE(&pHmCpu->StatExitIO, "/PROF/CPU%u/HM/SwitchFromGC_2/IO", "I/O.");
829	HM_REG_PROFILE(&pHmCpu->StatExitMovCRx, "/PROF/CPU%u/HM/SwitchFromGC_2/MovCRx", "MOV CRx.");
830	HM_REG_PROFILE(&pHmCpu->StatExitXcptNmi, "/PROF/CPU%u/HM/SwitchFromGC_2/XcptNmi", "Exceptions, NMIs.");
831	HM_REG_PROFILE(&pHmCpu->StatExitVmentry, "/PROF/CPU%u/HM/SwitchFromGC_2/Vmentry", "VMLAUNCH/VMRESUME on Intel or VMRUN on AMD.");
832	HM_REG_PROFILE(&pHmCpu->StatImportGuestState, "/PROF/CPU%u/HM/ImportGuestState", "Profiling of importing guest state from hardware after VM-exit.");
833	HM_REG_PROFILE(&pHmCpu->StatExportGuestState, "/PROF/CPU%u/HM/ExportGuestState", "Profiling of exporting guest state to hardware before VM-entry.");
834	HM_REG_PROFILE(&pHmCpu->StatLoadGuestFpuState, "/PROF/CPU%u/HM/LoadGuestFpuState", "Profiling of CPUMR0LoadGuestFPU.");
835	HM_REG_PROFILE(&pHmCpu->StatInGC, "/PROF/CPU%u/HM/InGC", "Profiling of execution of guest-code in hardware.");
836	# ifdef HM_PROFILE_EXIT_DISPATCH
837	HM_REG_STAT(&pHmCpu->StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
838	"/PROF/CPU%u/HM/ExitDispatch", "Profiling the dispatching of exit handlers.");
839	# endif
840	#endif
841	# define HM_REG_COUNTER(a, b, desc) HM_REG_STAT(a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, b, desc)
842
843	HM_REG_COUNTER(&pHmCpu->StatImportGuestStateFallback, "/HM/CPU%u/ImportGuestStateFallback", "Times vmxHCImportGuestState took the fallback code path.");
844	HM_REG_COUNTER(&pHmCpu->StatReadToTransientFallback, "/HM/CPU%u/ReadToTransientFallback", "Times vmxHCReadToTransient took the fallback code path.");
845	#ifdef VBOX_WITH_STATISTICS
846	HM_REG_COUNTER(&pHmCpu->StatExitAll, "/HM/CPU%u/Exit/All", "Total exits (excludes nested-guest and debug loops exits).");
847	HM_REG_COUNTER(&pHmCpu->StatDebugExitAll, "/HM/CPU%u/Exit/DebugAll", "Total debug-loop exits.");
848	HM_REG_COUNTER(&pHmCpu->StatNestedExitAll, "/HM/CPU%u/ExitNestedGuest/All", "Total nested-guest exits.");
849	HM_REG_COUNTER(&pHmCpu->StatExitShadowNM, "/HM/CPU%u/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
850	HM_REG_COUNTER(&pHmCpu->StatExitGuestNM, "/HM/CPU%u/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
851	HM_REG_COUNTER(&pHmCpu->StatExitShadowPF, "/HM/CPU%u/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
852	HM_REG_COUNTER(&pHmCpu->StatExitShadowPFEM, "/HM/CPU%u/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
853	HM_REG_COUNTER(&pHmCpu->StatExitGuestPF, "/HM/CPU%u/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
854	HM_REG_COUNTER(&pHmCpu->StatExitGuestUD, "/HM/CPU%u/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
855	HM_REG_COUNTER(&pHmCpu->StatExitGuestSS, "/HM/CPU%u/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
856	HM_REG_COUNTER(&pHmCpu->StatExitGuestNP, "/HM/CPU%u/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
857	HM_REG_COUNTER(&pHmCpu->StatExitGuestTS, "/HM/CPU%u/Exit/Trap/Gst/#TS", "Guest #TS (task switch) exception.");
858	HM_REG_COUNTER(&pHmCpu->StatExitGuestOF, "/HM/CPU%u/Exit/Trap/Gst/#OF", "Guest #OF (overflow) exception.");
859	HM_REG_COUNTER(&pHmCpu->StatExitGuestGP, "/HM/CPU%u/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
860	HM_REG_COUNTER(&pHmCpu->StatExitGuestDE, "/HM/CPU%u/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
861	HM_REG_COUNTER(&pHmCpu->StatExitGuestDF, "/HM/CPU%u/Exit/Trap/Gst/#DF", "Guest #DF (double fault) exception.");
862	HM_REG_COUNTER(&pHmCpu->StatExitGuestBR, "/HM/CPU%u/Exit/Trap/Gst/#BR", "Guest #BR (boundary range exceeded) exception.");
863	#endif
864	HM_REG_COUNTER(&pHmCpu->StatExitGuestAC, "/HM/CPU%u/Exit/Trap/Gst/#AC", "Guest #AC (alignment check) exception.");
865	if (fCpuSupportsVmx)
866	HM_REG_COUNTER(&pHmCpu->StatExitGuestACSplitLock, "/HM/CPU%u/Exit/Trap/Gst/#AC-split-lock", "Guest triggered #AC due to split-lock being enabled on the host (interpreted).");
867	#ifdef VBOX_WITH_STATISTICS
868	HM_REG_COUNTER(&pHmCpu->StatExitGuestDB, "/HM/CPU%u/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
869	HM_REG_COUNTER(&pHmCpu->StatExitGuestMF, "/HM/CPU%u/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
870	HM_REG_COUNTER(&pHmCpu->StatExitGuestBP, "/HM/CPU%u/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
871	HM_REG_COUNTER(&pHmCpu->StatExitGuestXF, "/HM/CPU%u/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
872	HM_REG_COUNTER(&pHmCpu->StatExitGuestXcpUnk, "/HM/CPU%u/Exit/Trap/Gst/Other", "Other guest exceptions.");
873	HM_REG_COUNTER(&pHmCpu->StatExitRdmsr, "/HM/CPU%u/Exit/Instr/Rdmsr", "MSR read.");
874	HM_REG_COUNTER(&pHmCpu->StatExitWrmsr, "/HM/CPU%u/Exit/Instr/Wrmsr", "MSR write.");
875	HM_REG_COUNTER(&pHmCpu->StatExitDRxWrite, "/HM/CPU%u/Exit/Instr/DR-Write", "Debug register write.");
876	HM_REG_COUNTER(&pHmCpu->StatExitDRxRead, "/HM/CPU%u/Exit/Instr/DR-Read", "Debug register read.");
877	HM_REG_COUNTER(&pHmCpu->StatExitCR0Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR0", "CR0 read.");
878	HM_REG_COUNTER(&pHmCpu->StatExitCR2Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR2", "CR2 read.");
879	HM_REG_COUNTER(&pHmCpu->StatExitCR3Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR3", "CR3 read.");
880	HM_REG_COUNTER(&pHmCpu->StatExitCR4Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR4", "CR4 read.");
881	HM_REG_COUNTER(&pHmCpu->StatExitCR8Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR8", "CR8 read.");
882	HM_REG_COUNTER(&pHmCpu->StatExitCR0Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR0", "CR0 write.");
883	HM_REG_COUNTER(&pHmCpu->StatExitCR2Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR2", "CR2 write.");
884	HM_REG_COUNTER(&pHmCpu->StatExitCR3Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR3", "CR3 write.");
885	HM_REG_COUNTER(&pHmCpu->StatExitCR4Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR4", "CR4 write.");
886	HM_REG_COUNTER(&pHmCpu->StatExitCR8Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR8", "CR8 write.");
887	HM_REG_COUNTER(&pHmCpu->StatExitClts, "/HM/CPU%u/Exit/Instr/CLTS", "CLTS instruction.");
888	HM_REG_COUNTER(&pHmCpu->StatExitLmsw, "/HM/CPU%u/Exit/Instr/LMSW", "LMSW instruction.");
889	HM_REG_COUNTER(&pHmCpu->StatExitXdtrAccess, "/HM/CPU%u/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
890	HM_REG_COUNTER(&pHmCpu->StatExitIOWrite, "/HM/CPU%u/Exit/Instr/IO/Write", "I/O write.");
891	HM_REG_COUNTER(&pHmCpu->StatExitIORead, "/HM/CPU%u/Exit/Instr/IO/Read", "I/O read.");
892	HM_REG_COUNTER(&pHmCpu->StatExitIOStringWrite, "/HM/CPU%u/Exit/Instr/IO/WriteString", "String I/O write.");
893	HM_REG_COUNTER(&pHmCpu->StatExitIOStringRead, "/HM/CPU%u/Exit/Instr/IO/ReadString", "String I/O read.");
894	HM_REG_COUNTER(&pHmCpu->StatExitIntWindow, "/HM/CPU%u/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts.");
895	HM_REG_COUNTER(&pHmCpu->StatExitExtInt, "/HM/CPU%u/Exit/ExtInt", "Physical maskable interrupt (host).");
896	#endif
897	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGC, "/HM/CPU%u/Exit/HostNmiInGC", "Host NMI received while in guest context.");
898	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGCIpi, "/HM/CPU%u/Exit/HostNmiInGCIpi", "Host NMI received while in guest context dispatched using IPIs.");
899	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/Exit/PreemptTimer", "VMX-preemption timer expired.");
900	#ifdef VBOX_WITH_STATISTICS
901	HM_REG_COUNTER(&pHmCpu->StatExitTprBelowThreshold, "/HM/CPU%u/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
902	HM_REG_COUNTER(&pHmCpu->StatExitTaskSwitch, "/HM/CPU%u/Exit/TaskSwitch", "Task switch caused through task gate in IDT.");
903	HM_REG_COUNTER(&pHmCpu->StatExitApicAccess, "/HM/CPU%u/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
904
905	HM_REG_COUNTER(&pHmCpu->StatSwitchTprMaskedIrq, "/HM/CPU%u/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
906	HM_REG_COUNTER(&pHmCpu->StatSwitchGuestIrq, "/HM/CPU%u/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
907	HM_REG_COUNTER(&pHmCpu->StatSwitchPendingHostIrq, "/HM/CPU%u/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
908	HM_REG_COUNTER(&pHmCpu->StatSwitchHmToR3FF, "/HM/CPU%u/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
909	HM_REG_COUNTER(&pHmCpu->StatSwitchVmReq, "/HM/CPU%u/Switch/VmReq", "Exit to ring-3 due to pending VM requests.");
910	HM_REG_COUNTER(&pHmCpu->StatSwitchPgmPoolFlush, "/HM/CPU%u/Switch/PgmPoolFlush", "Exit to ring-3 due to pending PGM pool flush.");
911	HM_REG_COUNTER(&pHmCpu->StatSwitchDma, "/HM/CPU%u/Switch/PendingDma", "Exit to ring-3 due to pending DMA requests.");
912	HM_REG_COUNTER(&pHmCpu->StatSwitchExitToR3, "/HM/CPU%u/Switch/ExitToR3", "Exit to ring-3 (total).");
913	HM_REG_COUNTER(&pHmCpu->StatSwitchLongJmpToR3, "/HM/CPU%u/Switch/LongJmpToR3", "Longjump to ring-3.");
914	HM_REG_COUNTER(&pHmCpu->StatSwitchMaxResumeLoops, "/HM/CPU%u/Switch/MaxResumeLoops", "Maximum VMRESUME inner-loop counter reached.");
915	HM_REG_COUNTER(&pHmCpu->StatSwitchHltToR3, "/HM/CPU%u/Switch/HltToR3", "HLT causing us to go to ring-3.");
916	HM_REG_COUNTER(&pHmCpu->StatSwitchApicAccessToR3, "/HM/CPU%u/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
917	#endif
918	HM_REG_COUNTER(&pHmCpu->StatSwitchPreempt, "/HM/CPU%u/Switch/Preempting", "EMT has been preempted while in HM context.");
919	#ifdef VBOX_WITH_STATISTICS
920	HM_REG_COUNTER(&pHmCpu->StatSwitchNstGstVmexit, "/HM/CPU%u/Switch/NstGstVmexit", "Nested-guest VM-exit occurred.");
921
922	HM_REG_COUNTER(&pHmCpu->StatInjectInterrupt, "/HM/CPU%u/EventInject/Interrupt", "Injected an external interrupt into the guest.");
923	HM_REG_COUNTER(&pHmCpu->StatInjectXcpt, "/HM/CPU%u/EventInject/Trap", "Injected an exception into the guest.");
924	HM_REG_COUNTER(&pHmCpu->StatInjectReflect, "/HM/CPU%u/EventInject/Reflect", "Reflecting an exception caused due to event injection.");
925	HM_REG_COUNTER(&pHmCpu->StatInjectConvertDF, "/HM/CPU%u/EventInject/ReflectDF", "Injected a converted #DF caused due to event injection.");
926	HM_REG_COUNTER(&pHmCpu->StatInjectInterpret, "/HM/CPU%u/EventInject/Interpret", "Falling back to interpreter for handling exception caused due to event injection.");
927	HM_REG_COUNTER(&pHmCpu->StatInjectReflectNPF, "/HM/CPU%u/EventInject/ReflectNPF", "Reflecting event that caused an EPT violation / nested #PF.");
928
929	HM_REG_COUNTER(&pHmCpu->StatFlushPage, "/HM/CPU%u/Flush/Page", "Invalidating a guest page on all guest CPUs.");
930	HM_REG_COUNTER(&pHmCpu->StatFlushPageManual, "/HM/CPU%u/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
931	HM_REG_COUNTER(&pHmCpu->StatFlushPhysPageManual, "/HM/CPU%u/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
932	HM_REG_COUNTER(&pHmCpu->StatFlushTlb, "/HM/CPU%u/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
933	HM_REG_COUNTER(&pHmCpu->StatFlushTlbManual, "/HM/CPU%u/Flush/TLB/Manual", "Request a full guest-TLB flush.");
934	HM_REG_COUNTER(&pHmCpu->StatFlushTlbNstGst, "/HM/CPU%u/Flush/TLB/NestedGuest", "Request a nested-guest-TLB flush.");
935	HM_REG_COUNTER(&pHmCpu->StatFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
936	HM_REG_COUNTER(&pHmCpu->StatNoFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/Skipped", "No TLB flushing required.");
937	HM_REG_COUNTER(&pHmCpu->StatFlushEntire, "/HM/CPU%u/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
938	HM_REG_COUNTER(&pHmCpu->StatFlushAsid, "/HM/CPU%u/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
939	HM_REG_COUNTER(&pHmCpu->StatFlushNestedPaging, "/HM/CPU%u/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
940	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgVirt, "/HM/CPU%u/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
941	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgPhys, "/HM/CPU%u/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
942	HM_REG_COUNTER(&pHmCpu->StatTlbShootdown, "/HM/CPU%u/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
943	HM_REG_COUNTER(&pHmCpu->StatTlbShootdownFlush, "/HM/CPU%u/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
944
945	HM_REG_COUNTER(&pHmCpu->StatTscParavirt, "/HM/CPU%u/TSC/Paravirt", "Paravirtualized TSC in effect.");
946	HM_REG_COUNTER(&pHmCpu->StatTscOffset, "/HM/CPU%u/TSC/Offset", "TSC offsetting is in effect.");
947	HM_REG_COUNTER(&pHmCpu->StatTscIntercept, "/HM/CPU%u/TSC/Intercept", "Intercept TSC accesses.");
948
949	HM_REG_COUNTER(&pHmCpu->StatDRxArmed, "/HM/CPU%u/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
950	HM_REG_COUNTER(&pHmCpu->StatDRxContextSwitch, "/HM/CPU%u/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
951	HM_REG_COUNTER(&pHmCpu->StatDRxIoCheck, "/HM/CPU%u/Debug/IOCheck", "Checking for I/O breakpoint.");
952
953	HM_REG_COUNTER(&pHmCpu->StatExportMinimal, "/HM/CPU%u/Export/Minimal", "VM-entry exporting minimal guest-state.");
954	HM_REG_COUNTER(&pHmCpu->StatExportFull, "/HM/CPU%u/Export/Full", "VM-entry exporting the full guest-state.");
955	HM_REG_COUNTER(&pHmCpu->StatLoadGuestFpu, "/HM/CPU%u/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
956	HM_REG_COUNTER(&pHmCpu->StatExportHostState, "/HM/CPU%u/Export/HostState", "VM-entry exporting host-state.");
957
958	if (fCpuSupportsVmx)
959	{
960	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRip, "/HM/CPU%u/WriteHostRIP", "Number of VMX_VMCS_HOST_RIP instructions.");
961	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRsp, "/HM/CPU%u/WriteHostRSP", "Number of VMX_VMCS_HOST_RSP instructions.");
962	HM_REG_COUNTER(&pHmCpu->StatVmxVmLaunch, "/HM/CPU%u/VMLaunch", "Number of VM-entries using VMLAUNCH.");
963	HM_REG_COUNTER(&pHmCpu->StatVmxVmResume, "/HM/CPU%u/VMResume", "Number of VM-entries using VMRESUME.");
964	}
965
966	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelBase, "/HM/CPU%u/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
967	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelLimit, "/HM/CPU%u/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
968	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelAttr, "/HM/CPU%u/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector attributes.");
969
970	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelBase, "/HM/CPU%u/VMXCheck/V86SelBase", "Could not use VMX due to unsuitable v8086-mode selector base.");
971	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelLimit, "/HM/CPU%u/VMXCheck/V86SelLimit", "Could not use VMX due to unsuitable v8086-mode selector limit.");
972	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelAttr, "/HM/CPU%u/VMXCheck/V86SelAttrs", "Could not use VMX due to unsuitable v8086-mode selector attributes.");
973
974	HM_REG_COUNTER(&pHmCpu->StatVmxCheckRmOk, "/HM/CPU%u/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
975	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadSel, "/HM/CPU%u/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
976	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRpl, "/HM/CPU%u/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
977	HM_REG_COUNTER(&pHmCpu->StatVmxCheckPmOk, "/HM/CPU%u/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
978	#endif
979	if (fCpuSupportsVmx)
980	{
981	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/PreemptTimer", "VMX-preemption timer fired.");
982	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadline, "/HM/CPU%u/PreemptTimer/ReusingDeadline", "VMX-preemption timer arming logic using previously calculated deadline");
983	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadlineExpired, "/HM/CPU%u/PreemptTimer/ReusingDeadlineExpired", "VMX-preemption timer arming logic found previous deadline already expired (ignored)");
984	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadline, "/HM/CPU%u/PreemptTimer/RecalcingDeadline", "VMX-preemption timer arming logic recalculating the deadline (slightly expensive)");
985	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadlineExpired, "/HM/CPU%u/PreemptTimer/RecalcingDeadlineExpired", "VMX-preemption timer arming logic found recalculated deadline expired (ignored)");
986	}
987	#ifdef VBOX_WITH_STATISTICS
988	/*
989	* Guest Exit reason stats.
990	*/
991	if (fCpuSupportsVmx)
992	{
993	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
994	{
995	const char *pszExitName = HMGetVmxExitName(j);
996	if (pszExitName)
997	{
998	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
999	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
1000	AssertRCReturn(rc, rc);
1001	}
1002	}
1003	}
1004	else
1005	{
1006	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1007	{
1008	const char *pszExitName = HMGetSvmExitName(j);
1009	if (pszExitName)
1010	{
1011	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1012	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
1013	AssertRC(rc);
1014	}
1015	}
1016	}
1017	HM_REG_COUNTER(&pHmCpu->StatExitReasonNpf, "/HM/CPU%u/Exit/Reason/#NPF", "Nested page faults");
1018
1019	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
1020	/*
1021	* Nested-guest VM-exit reason stats.
1022	*/
1023	if (fCpuSupportsVmx)
1024	{
1025	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1026	{
1027	const char *pszExitName = HMGetVmxExitName(j);
1028	if (pszExitName)
1029	{
1030	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1031	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/ExitNestedGuest/Reason/%02x", idCpu, j);
1032	AssertRC(rc);
1033	}
1034	}
1035	}
1036	else
1037	{
1038	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1039	{
1040	const char *pszExitName = HMGetSvmExitName(j);
1041	if (pszExitName)
1042	{
1043	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1044	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/ExitNestedGuest/Reason/%02x", idCpu, j);
1045	AssertRC(rc);
1046	}
1047	}
1048	}
1049	HM_REG_COUNTER(&pHmCpu->StatNestedExitReasonNpf, "/HM/CPU%u/ExitNestedGuest/Reason/#NPF", "Nested page faults");
1050	#endif
1051
1052	/*
1053	* Injected interrupts stats.
1054	*/
1055	char szDesc[64];
1056	for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedIrqs); j++)
1057	{
1058	RTStrPrintf(&szDesc[0], sizeof(szDesc), "Interrupt %u", j);
1059	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1060	STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectIntr/%02X", idCpu, j);
1061	AssertRC(rc);
1062	}
1063
1064	/*
1065	* Injected exception stats.
1066	*/
1067	for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedXcpts); j++)
1068	{
1069	RTStrPrintf(&szDesc[0], sizeof(szDesc), "%s exception", hmR3GetXcptName(j));
1070	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedXcpts[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1071	STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectXcpt/%02X", idCpu, j);
1072	AssertRC(rc);
1073	}
1074
1075	#endif /* VBOX_WITH_STATISTICS */
1076	#undef HM_REG_COUNTER
1077	#undef HM_REG_PROFILE
1078	#undef HM_REG_STAT
1079	}
1080
1081	return VINF_SUCCESS;
1082	}
1083
1084
1085	/**
1086	* Called when a init phase has completed.
1087	*
1088	* @returns VBox status code.
1089	* @param pVM The cross context VM structure.
1090	* @param enmWhat The phase that completed.
1091	*/
1092	VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1093	{
1094	switch (enmWhat)
1095	{
1096	case VMINITCOMPLETED_RING3:
1097	return hmR3InitFinalizeR3(pVM);
1098	case VMINITCOMPLETED_RING0:
1099	return hmR3InitFinalizeR0(pVM);
1100	default:
1101	return VINF_SUCCESS;
1102	}
1103	}
1104
1105
1106	/**
1107	* Turns off normal raw mode features.
1108	*
1109	* @param pVM The cross context VM structure.
1110	*/
1111	static void hmR3DisableRawMode(PVM pVM)
1112	{
1113	/** @todo r=bird: HM shouldn't be doing this crap. */
1114	/* Reinit the paging mode to force the new shadow mode. */
1115	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1116	{
1117	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1118	PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL, false /* fForce */);
1119	}
1120	}
1121
1122
1123	/**
1124	* Initialize VT-x or AMD-V.
1125	*
1126	* @returns VBox status code.
1127	* @param pVM The cross context VM structure.
1128	*/
1129	static int hmR3InitFinalizeR0(PVM pVM)
1130	{
1131	int rc;
1132
1133	/*
1134	* Since HM is in charge of large pages, if large pages isn't supported on Intel CPUs,
1135	* we must disable it here. Doing it here rather than in hmR3InitFinalizeR0Intel covers
1136	* the case of informing PGM even when NEM is the execution engine.
1137	*/
1138	if ( pVM->hm.s.fLargePages
1139	&& pVM->hm.s.vmx.fSupported
1140	&& !(pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M))
1141	{
1142	pVM->hm.s.fLargePages = false;
1143	PGMSetLargePageUsage(pVM, false);
1144	LogRel(("HM: Disabled large page support as the CPU doesn't allow EPT PDEs to map 2MB pages\n"));
1145	}
1146
1147	if (!HMIsEnabled(pVM))
1148	return VINF_SUCCESS;
1149
1150	/*
1151	* Hack to allow users to work around broken BIOSes that incorrectly set
1152	* EFER.SVME, which makes us believe somebody else is already using AMD-V.
1153	*/
1154	if ( !pVM->hm.s.vmx.fSupported
1155	&& !pVM->hm.s.svm.fSupported
1156	&& pVM->hm.s.ForR3.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1157	&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1158	{
1159	LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1160	pVM->hm.s.svm.fSupported = true;
1161	pVM->hm.s.svm.fIgnoreInUseError = true;
1162	pVM->hm.s.ForR3.rcInit = VINF_SUCCESS;
1163	}
1164
1165	/*
1166	* Report ring-0 init errors.
1167	*/
1168	if ( !pVM->hm.s.vmx.fSupported
1169	&& !pVM->hm.s.svm.fSupported)
1170	{
1171	LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.ForR3.rcInit));
1172	LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.ForR3.vmx.u64HostFeatCtrl));
1173	switch (pVM->hm.s.ForR3.rcInit)
1174	{
1175	case VERR_VMX_IN_VMX_ROOT_MODE:
1176	return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1177	case VERR_VMX_NO_VMX:
1178	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1179	case VERR_VMX_MSR_VMX_DISABLED:
1180	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1181	case VERR_VMX_MSR_ALL_VMX_DISABLED:
1182	return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1183	case VERR_VMX_MSR_LOCKING_FAILED:
1184	return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1185	case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1186	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1187	case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1188	return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1189
1190	case VERR_SVM_IN_USE:
1191	return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1192	case VERR_SVM_NO_SVM:
1193	return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1194	case VERR_SVM_DISABLED:
1195	return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1196	}
1197	return VMSetError(pVM, pVM->hm.s.ForR3.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.ForR3.rcInit);
1198	}
1199
1200	/*
1201	* Enable VT-x or AMD-V on all host CPUs.
1202	*/
1203	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_ENABLE, 0, NULL);
1204	if (RT_FAILURE(rc))
1205	{
1206	LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1207	HMR3CheckError(pVM, rc);
1208	return rc;
1209	}
1210
1211	/*
1212	* No TPR patching is required when the IO-APIC is not enabled for this VM.
1213	* (Main should have taken care of this already)
1214	*/
1215	if (!PDMHasIoApic(pVM))
1216	{
1217	Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1218	pVM->hm.s.fTprPatchingAllowed = false;
1219	}
1220
1221	LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
1222	pVM->hm.s.ForR3.fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
1223	pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
1224
1225	/*
1226	* Do the vendor specific initialization
1227	*
1228	* Note! We disable release log buffering here since we're doing relatively
1229	* lot of logging and doesn't want to hit the disk with each LogRel
1230	* statement.
1231	*/
1232	AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1233	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
1234	if (pVM->hm.s.vmx.fSupported)
1235	rc = hmR3InitFinalizeR0Intel(pVM);
1236	else
1237	rc = hmR3InitFinalizeR0Amd(pVM);
1238	LogRel((pVM->hm.s.fGlobalInit ? "HM: VT-x/AMD-V init method: Global\n"
1239	: "HM: VT-x/AMD-V init method: Local\n"));
1240	RTLogRelSetBuffering(fOldBuffered);
1241	pVM->hm.s.fInitialized = true;
1242
1243	return rc;
1244	}
1245
1246
1247	/**
1248	* @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1249	*/
1250	static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1251	{
1252	NOREF(pVM);
1253	NOREF(pvAllocation);
1254	NOREF(GCPhysAllocation);
1255	}
1256
1257
1258	/**
1259	* Returns a description of the VMCS (and associated regions') memory type given the
1260	* IA32_VMX_BASIC MSR.
1261	*
1262	* @returns The descriptive memory type.
1263	* @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1264	*/
1265	static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1266	{
1267	uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1268	switch (uMemType)
1269	{
1270	case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1271	case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1272	}
1273	return "Unknown";
1274	}
1275
1276
1277	/**
1278	* Returns a single-line description of all the activity-states supported by the CPU
1279	* given the IA32_VMX_MISC MSR.
1280	*
1281	* @returns All supported activity states.
1282	* @param uMsrMisc IA32_VMX_MISC MSR value.
1283	*/
1284	static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1285	{
1286	static const char * const s_apszActStates[] =
1287	{
1288	"",
1289	" ( HLT )",
1290	" ( SHUTDOWN )",
1291	" ( HLT SHUTDOWN )",
1292	" ( SIPI_WAIT )",
1293	" ( HLT SIPI_WAIT )",
1294	" ( SHUTDOWN SIPI_WAIT )",
1295	" ( HLT SHUTDOWN SIPI_WAIT )"
1296	};
1297	uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1298	Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1299	return s_apszActStates[idxActStates];
1300	}
1301
1302
1303	/**
1304	* Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1305	*
1306	* @param fFeatMsr The feature control MSR value.
1307	*/
1308	static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1309	{
1310	uint64_t const val = fFeatMsr;
1311	LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1312	HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1313	HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1314	HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1315	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1316	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1317	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1318	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1319	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1320	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1321	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1322	HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1323	HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1324	HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1325	HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1326	if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1327	LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1328	}
1329
1330
1331	/**
1332	* Reports MSR_IA32_VMX_BASIC MSR to the log.
1333	*
1334	* @param uBasicMsr The VMX basic MSR value.
1335	*/
1336	static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1337	{
1338	LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1339	LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1340	LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1341	LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1342	"< 4 GB" : "None"));
1343	LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1344	LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1345	LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1346	LogRel(("HM: Supports true-capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1347	LogRel(("HM: VM-entry Xcpt error-code optional = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_XCPT_ERRCODE)));
1348	}
1349
1350
1351	/**
1352	* Reports MSR_IA32_PINBASED_CTLS to the log.
1353	*
1354	* @param pVmxMsr Pointer to the VMX MSR.
1355	*/
1356	static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1357	{
1358	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1359	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1360	LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1361	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1362	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1363	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1364	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1365	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1366	}
1367
1368
1369	/**
1370	* Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1371	*
1372	* @param pVmxMsr Pointer to the VMX MSR.
1373	*/
1374	static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1375	{
1376	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1377	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1378	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1379	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1380	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1381	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1382	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1383	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1384	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1385	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1386	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1387	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1388	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TERTIARY_CTLS", VMX_PROC_CTLS_USE_TERTIARY_CTLS);
1389	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1390	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1391	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1392	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1393	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1394	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1395	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1396	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1397	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1398	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1399	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1400	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1401	}
1402
1403
1404	/**
1405	* Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1406	*
1407	* @param pVmxMsr Pointer to the VMX MSR.
1408	*/
1409	static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1410	{
1411	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1412	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1413	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1414	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1415	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1416	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1417	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1418	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1419	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1420	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1421	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1422	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1423	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1424	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1425	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1426	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1427	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1428	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1429	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1430	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1431	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1432	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_XCPT_VE", VMX_PROC_CTLS2_EPT_XCPT_VE);
1433	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1434	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1435	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MODE_BASED_EPT_PERM", VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1436	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SPP_EPT", VMX_PROC_CTLS2_SPP_EPT);
1437	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PT_EPT", VMX_PROC_CTLS2_PT_EPT);
1438	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1439	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USER_WAIT_PAUSE", VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1440	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLV_EXIT", VMX_PROC_CTLS2_ENCLV_EXIT);
1441	}
1442
1443
1444	/**
1445	* Reports MSR_IA32_VMX_PROCBASED_CTLS3 MSR to the log.
1446	*
1447	* @param uProcCtls3 The tertiary processor-based VM-execution control MSR.
1448	*/
1449	static void hmR3VmxReportProcBasedCtls3Msr(uint64_t uProcCtls3)
1450	{
1451	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS3 = %#RX64\n", uProcCtls3));
1452	LogRel(("HM: LOADIWKEY_EXIT = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT)));
1453	}
1454
1455
1456	/**
1457	* Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1458	*
1459	* @param pVmxMsr Pointer to the VMX MSR.
1460	*/
1461	static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1462	{
1463	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1464	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1465	LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1466	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1467	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1468	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1469	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1470	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1471	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1472	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1473	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_BNDCFGS_MSR", VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR);
1474	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
1475	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_RTIT_CTL_MSR", VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR);
1476	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_ENTRY_CTLS_LOAD_CET_STATE);
1477	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_ENTRY_CTLS_LOAD_PKRS_MSR);
1478	}
1479
1480
1481	/**
1482	* Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1483	*
1484	* @param pVmxMsr Pointer to the VMX MSR.
1485	*/
1486	static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1487	{
1488	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1489	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1490	LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1491	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1492	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1493	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1494	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1495	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1496	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1497	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1498	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1499	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1500	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_BNDCFGS_MSR", VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR);
1501	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT);
1502	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_RTIT_CTL_MSR", VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR);
1503	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_EXIT_CTLS_LOAD_CET_STATE);
1504	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_EXIT_CTLS_LOAD_PKRS_MSR);
1505	}
1506
1507
1508	/**
1509	* Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1510	*
1511	* @param fCaps The VMX EPT/VPID capability MSR value.
1512	*/
1513	static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1514	{
1515	LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1516	HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1517	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1518	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_5", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5);
1519	HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_UC", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_UC);
1520	HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_WB", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_WB);
1521	HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1522	HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1523	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1524	HMVMX_REPORT_MSR_CAP(fCaps, "ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
1525	HMVMX_REPORT_MSR_CAP(fCaps, "ADVEXITINFO_EPT_VIOLATION", MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION);
1526	HMVMX_REPORT_MSR_CAP(fCaps, "SUPER_SHW_STACK", MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK);
1527	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1528	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1529	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1530	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1531	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1532	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1533	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1534	}
1535
1536
1537	/**
1538	* Reports MSR_IA32_VMX_MISC MSR to the log.
1539	*
1540	* @param pVM Pointer to the VM.
1541	* @param fMisc The VMX misc. MSR value.
1542	*/
1543	static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1544	{
1545	LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1546	uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1547	if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1548	LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1549	else
1550	{
1551	LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1552	pVM->hm.s.vmx.cPreemptTimerShift));
1553	}
1554	LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1555	LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1556	hmR3VmxGetActivityStateAllDesc(fMisc)));
1557	LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1558	LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1559	LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1560	LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1561	VMX_MISC_MAX_MSRS(fMisc)));
1562	LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1563	LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1564	LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1565	LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1566	}
1567
1568
1569	/**
1570	* Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1571	*
1572	* @param uVmcsEnum The VMX VMCS enum MSR value.
1573	*/
1574	static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1575	{
1576	LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1577	LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1578	}
1579
1580
1581	/**
1582	* Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1583	*
1584	* @param uVmFunc The VMX VMFUNC MSR value.
1585	*/
1586	static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1587	{
1588	LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1589	HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1590	}
1591
1592
1593	/**
1594	* Reports VMX CR0, CR4 fixed MSRs.
1595	*
1596	* @param pMsrs Pointer to the VMX MSRs.
1597	*/
1598	static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1599	{
1600	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1601	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1602	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1603	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1604	}
1605
1606
1607	/**
1608	* Finish VT-x initialization (after ring-0 init).
1609	*
1610	* @returns VBox status code.
1611	* @param pVM The cross context VM structure.
1612	*/
1613	static int hmR3InitFinalizeR0Intel(PVM pVM)
1614	{
1615	int rc;
1616
1617	LogFunc(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1618	AssertLogRelReturn(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl != 0, VERR_HM_IPE_4);
1619
1620	LogRel(("HM: Using VT-x implementation 3.0\n"));
1621	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1622	LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostCr4));
1623	LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostMsrEfer));
1624	LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostSmmMonitorCtl));
1625	LogRel(("HM: Host DR6 zero'ed = %#RX64%s\n", pVM->hm.s.ForR3.vmx.u64HostDr6Zeroed,
1626	pVM->hm.s.ForR3.vmx.fAlwaysInterceptMovDRx ? " - always intercept MOV DRx" : ""));
1627
1628	hmR3VmxReportFeatCtlMsr(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl);
1629	hmR3VmxReportBasicMsr(pVM->hm.s.ForR3.vmx.Msrs.u64Basic);
1630
1631	hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.PinCtls);
1632	hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls);
1633	if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1634	hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2);
1635	if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TERTIARY_CTLS)
1636	hmR3VmxReportProcBasedCtls3Msr(pVM->hm.s.ForR3.vmx.Msrs.u64ProcCtls3);
1637
1638	hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.EntryCtls);
1639	hmR3VmxReportExitCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ExitCtls);
1640
1641	if (RT_BF_GET(pVM->hm.s.ForR3.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1642	{
1643	/* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1644	LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TruePinCtls));
1645	LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueProcCtls));
1646	LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueEntryCtls));
1647	LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueExitCtls));
1648	}
1649
1650	hmR3VmxReportMiscMsr(pVM, pVM->hm.s.ForR3.vmx.Msrs.u64Misc);
1651	hmR3VmxReportVmcsEnumMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmcsEnum);
1652	if (pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps)
1653	hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps);
1654	if (pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc)
1655	hmR3VmxReportVmFuncMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc);
1656	hmR3VmxReportCrFixedMsrs(&pVM->hm.s.ForR3.vmx.Msrs);
1657
1658	#ifdef TODO_9217_VMCSINFO
1659	LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1660	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1661	{
1662	PCVMXVMCSINFOSHARED pVmcsInfo = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfo;
1663	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
1664	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysVmcs));
1665	}
1666	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1667	if (pVM->cpum.ro.GuestFeatures.fVmx)
1668	{
1669	LogRel(("HM: Nested-guest:\n"));
1670	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1671	{
1672	PCVMXVMCSINFOSHARED pVmcsInfoNstGst = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfoNstGst;
1673	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysMsrBitmap));
1674	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysVmcs));
1675	}
1676	}
1677	#endif
1678	#endif /* TODO_9217_VMCSINFO */
1679
1680	/*
1681	* EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1682	*/
1683	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1684	\|\| (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1685	VERR_HM_IPE_1);
1686	AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuestCfg
1687	\|\| ( (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1688	&& pVM->hm.s.fNestedPagingCfg),
1689	VERR_HM_IPE_1);
1690
1691	/*
1692	* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1693	* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1694	* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1695	*/
1696	if ( !(pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1697	&& CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1698	{
1699	CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1700	LogRel(("HM: Disabled RDTSCP\n"));
1701	}
1702
1703	if (!pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1704	{
1705	/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1706	rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1707	if (RT_SUCCESS(rc))
1708	{
1709	/* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1710	Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1711	esp. Figure 20-5.*/
1712	ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1713	pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1714
1715	/* Bit set to 0 means software interrupts are redirected to the
1716	8086 program interrupt handler rather than switching to
1717	protected-mode handler. */
1718	memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1719
1720	/* Allow all port IO, so that port IO instructions do not cause
1721	exceptions and would instead cause a VM-exit (based on VT-x's
1722	IO bitmap which we currently configure to always cause an exit). */
1723	memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, X86_PAGE_SIZE * 2);
1724	((unsigned char )pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1725
1726	/*
1727	* Construct a 1024 element page directory with 4 MB pages for the identity mapped
1728	* page table used in real and protected mode without paging with EPT.
1729	*/
1730	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hm.s.vmx.pRealModeTSS + X86_PAGE_SIZE 3);
1731	for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1732	{
1733	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1734	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US
1735	\| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS
1736	\| X86_PDE4M_G;
1737	}
1738
1739	/* We convert it here every time as PCI regions could be reconfigured. */
1740	if (PDMVmmDevHeapIsEnabled(pVM))
1741	{
1742	RTGCPHYS GCPhys;
1743	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1744	AssertRCReturn(rc, rc);
1745	LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1746
1747	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1748	AssertRCReturn(rc, rc);
1749	LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1750	}
1751	}
1752	else
1753	{
1754	LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1755	pVM->hm.s.vmx.pRealModeTSS = NULL;
1756	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1757	return VMSetError(pVM, rc, RT_SRC_POS,
1758	"HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1759	}
1760	}
1761
1762	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1763	: "HM: Guest support: 32-bit only\n"));
1764
1765	/*
1766	* Call ring-0 to set up the VM.
1767	*/
1768	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /* idCpu /, VMMR0_DO_HM_SETUP_VM, 0 / u64Arg /, NULL / pReqHdr */);
1769	if (rc != VINF_SUCCESS)
1770	{
1771	LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1772	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1773	{
1774	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1775	LogRel(("HM: CPU[%u] Last instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
1776	LogRel(("HM: CPU[%u] HM error %#x (%u)\n", idCpu, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1777	}
1778	HMR3CheckError(pVM, rc);
1779	return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1780	}
1781
1782	LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.ForR3.vmx.fSupportsVmcsEfer));
1783	LogRel(("HM: Enabled VMX\n"));
1784	pVM->hm.s.vmx.fEnabled = true;
1785
1786	hmR3DisableRawMode(pVM); /** @todo make this go away! */
1787
1788	/*
1789	* Log configuration details.
1790	*/
1791	if (pVM->hm.s.fNestedPagingCfg)
1792	{
1793	LogRel(("HM: Enabled nested paging\n"));
1794	if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1795	LogRel(("HM: EPT flush type = Single context\n"));
1796	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1797	LogRel(("HM: EPT flush type = All contexts\n"));
1798	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1799	LogRel(("HM: EPT flush type = Not supported\n"));
1800	else
1801	LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushEpt));
1802
1803	if (pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1804	LogRel(("HM: Enabled unrestricted guest execution\n"));
1805
1806	if (pVM->hm.s.fLargePages)
1807	{
1808	/* Use large (2 MB) pages for our EPT PDEs where possible. */
1809	PGMSetLargePageUsage(pVM, true);
1810	LogRel(("HM: Enabled large page support\n"));
1811	}
1812	}
1813	else
1814	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
1815
1816	if (pVM->hm.s.ForR3.vmx.fVpid)
1817	{
1818	LogRel(("HM: Enabled VPID\n"));
1819	if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1820	LogRel(("HM: VPID flush type = Individual addresses\n"));
1821	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1822	LogRel(("HM: VPID flush type = Single context\n"));
1823	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1824	LogRel(("HM: VPID flush type = All contexts\n"));
1825	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1826	LogRel(("HM: VPID flush type = Single context retain globals\n"));
1827	else
1828	LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushVpid));
1829	}
1830	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1831	LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1832
1833	if (pVM->hm.s.vmx.fUsePreemptTimerCfg)
1834	LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1835	else
1836	LogRel(("HM: Disabled VMX-preemption timer\n"));
1837
1838	if (pVM->hm.s.fVirtApicRegs)
1839	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1840
1841	if (pVM->hm.s.fPostedIntrs)
1842	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1843
1844	if (pVM->hm.s.ForR3.vmx.fUseVmcsShadowing)
1845	{
1846	bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.ForR3.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL);
1847	LogRel(("HM: Enabled %s VMCS shadowing\n", fFullVmcsShadow ? "full" : "partial"));
1848	}
1849
1850	return VINF_SUCCESS;
1851	}
1852
1853
1854	/**
1855	* Finish AMD-V initialization (after ring-0 init).
1856	*
1857	* @returns VBox status code.
1858	* @param pVM The cross context VM structure.
1859	*/
1860	static int hmR3InitFinalizeR0Amd(PVM pVM)
1861	{
1862	LogFunc(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1863
1864	LogRel(("HM: Using AMD-V implementation 2.0\n"));
1865
1866	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1867	uint32_t u32Family;
1868	uint32_t u32Model;
1869	uint32_t u32Stepping;
1870	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
1871	LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1872	#endif
1873	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1874	LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.ForR3.svm.u64MsrHwcr));
1875	LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.ForR3.svm.u32Rev));
1876	LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.ForR3.uMaxAsid));
1877	LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.ForR3.svm.fFeatures));
1878
1879	/*
1880	* Enumerate AMD-V features.
1881	*/
1882	static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1883	{
1884	#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1885	HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1886	HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1887	HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1888	HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1889	HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1890	HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1891	HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1892	HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1893	HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1894	HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1895	HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1896	HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1897	HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1898	HMSVM_REPORT_FEATURE("GMET", X86_CPUID_SVM_FEATURE_EDX_GMET),
1899	HMSVM_REPORT_FEATURE("SSSCHECK", X86_CPUID_SVM_FEATURE_EDX_SSSCHECK),
1900	HMSVM_REPORT_FEATURE("SPEC_CTRL", X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL),
1901	HMSVM_REPORT_FEATURE("HOST_MCE_OVERRIDE", X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE),
1902	HMSVM_REPORT_FEATURE("TLBICTL", X86_CPUID_SVM_FEATURE_EDX_TLBICTL),
1903	#undef HMSVM_REPORT_FEATURE
1904	};
1905
1906	uint32_t fSvmFeatures = pVM->hm.s.ForR3.svm.fFeatures;
1907	for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1908	if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1909	{
1910	LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1911	fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1912	}
1913	if (fSvmFeatures)
1914	for (unsigned iBit = 0; iBit < 32; iBit++)
1915	if (RT_BIT_32(iBit) & fSvmFeatures)
1916	LogRel(("HM: Reserved bit %u\n", iBit));
1917
1918	/*
1919	* Nested paging is determined in HMR3Init, verify the sanity of that.
1920	*/
1921	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1922	\|\| (pVM->hm.s.ForR3.svm.fFeatures & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1923	VERR_HM_IPE_1);
1924
1925	#if 0
1926	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1927	* here. */
1928	if (RTR0IsPostIpiSupport())
1929	pVM->hm.s.fPostedIntrs = true;
1930	#endif
1931
1932	/*
1933	* Determine whether we need to intercept #UD in SVM mode for emulating
1934	* intel SYSENTER/SYSEXIT on AMD64, as these instructions results in #UD
1935	* when executed in long-mode. This is only really applicable when
1936	* non-default CPU profiles are in effect, i.e. guest vendor differs
1937	* from the host one.
1938	*/
1939	if (CPUMGetGuestCpuVendor(pVM) != CPUMGetHostCpuVendor(pVM))
1940	switch (CPUMGetGuestCpuVendor(pVM))
1941	{
1942	case CPUMCPUVENDOR_INTEL:
1943	case CPUMCPUVENDOR_VIA: /?/
1944	case CPUMCPUVENDOR_SHANGHAI: /?/
1945	switch (CPUMGetHostCpuVendor(pVM))
1946	{
1947	case CPUMCPUVENDOR_AMD:
1948	case CPUMCPUVENDOR_HYGON:
1949	if (pVM->hm.s.fAllow64BitGuestsCfg)
1950	{
1951	LogRel(("HM: Intercepting #UD for emulating SYSENTER/SYSEXIT in long mode.\n"));
1952	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1953	pVM->apCpusR3[idCpu]->hm.s.svm.fEmulateLongModeSysEnterExit = true;
1954	}
1955	break;
1956	default: break;
1957	}
1958	default: break;
1959	}
1960
1961	/*
1962	* Call ring-0 to set up the VM.
1963	*/
1964	int rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1965	if (rc != VINF_SUCCESS)
1966	{
1967	AssertMsgFailed(("%Rrc\n", rc));
1968	LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1969	return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1970	}
1971
1972	LogRel(("HM: Enabled SVM\n"));
1973	pVM->hm.s.svm.fEnabled = true;
1974
1975	if (pVM->hm.s.fNestedPagingCfg)
1976	{
1977	LogRel(("HM: Enabled nested paging\n"));
1978
1979	/*
1980	* Enable large pages (2 MB) if applicable.
1981	*/
1982	if (pVM->hm.s.fLargePages)
1983	{
1984	PGMSetLargePageUsage(pVM, true);
1985	LogRel(("HM: Enabled large page support\n"));
1986	}
1987	}
1988
1989	if (pVM->hm.s.fVirtApicRegs)
1990	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1991
1992	if (pVM->hm.s.fPostedIntrs)
1993	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1994
1995	hmR3DisableRawMode(pVM);
1996
1997	LogRel((pVM->hm.s.fTprPatchingAllowed ? "HM: Enabled TPR patching\n"
1998	: "HM: Disabled TPR patching\n"));
1999
2000	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
2001	: "HM: Guest support: 32-bit only\n"));
2002	return VINF_SUCCESS;
2003	}
2004
2005
2006	/**
2007	* Applies relocations to data and code managed by this
2008	* component. This function will be called at init and
2009	* whenever the VMM need to relocate it self inside the GC.
2010	*
2011	* @param pVM The cross context VM structure.
2012	*/
2013	VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
2014	{
2015	/* Fetch the current paging mode during the relocate callback during state loading. */
2016	if (VMR3GetState(pVM) == VMSTATE_LOADING)
2017	{
2018	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2019	{
2020	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2021	pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
2022	}
2023	}
2024	}
2025
2026
2027	/**
2028	* Terminates the HM.
2029	*
2030	* Termination means cleaning up and freeing all resources,
2031	* the VM itself is, at this point, powered off or suspended.
2032	*
2033	* @returns VBox status code.
2034	* @param pVM The cross context VM structure.
2035	*/
2036	VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
2037	{
2038	if (pVM->hm.s.vmx.pRealModeTSS)
2039	{
2040	PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
2041	pVM->hm.s.vmx.pRealModeTSS = 0;
2042	}
2043	hmR3TermCPU(pVM);
2044	return 0;
2045	}
2046
2047
2048	/**
2049	* Terminates the per-VCPU HM.
2050	*
2051	* @returns VBox status code.
2052	* @param pVM The cross context VM structure.
2053	*/
2054	static int hmR3TermCPU(PVM pVM)
2055	{
2056	RT_NOREF(pVM);
2057	return VINF_SUCCESS;
2058	}
2059
2060
2061	/**
2062	* Resets a virtual CPU.
2063	*
2064	* Used by HMR3Reset and CPU hot plugging.
2065	*
2066	* @param pVCpu The cross context virtual CPU structure to reset.
2067	*/
2068	VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
2069	{
2070	/* Sync. entire state on VM reset ring-0 re-entry. It's safe to reset
2071	the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2072	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
2073
2074	pVCpu->hm.s.fActive = false;
2075	pVCpu->hm.s.Event.fPending = false;
2076	pVCpu->hm.s.vmx.u64GstMsrApicBase = 0;
2077	pVCpu->hm.s.vmx.VmcsInfo.fWasInRealMode = true;
2078	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2079	if (pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmx)
2080	pVCpu->hm.s.vmx.VmcsInfoNstGst.fWasInRealMode = true;
2081	#endif
2082	}
2083
2084
2085	/**
2086	* The VM is being reset.
2087	*
2088	* For the HM component this means that any GDT/LDT/TSS monitors
2089	* needs to be removed.
2090	*
2091	* @param pVM The cross context VM structure.
2092	*/
2093	VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2094	{
2095	LogFlow(("HMR3Reset:\n"));
2096
2097	if (HMIsEnabled(pVM))
2098	hmR3DisableRawMode(pVM);
2099
2100	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2101	HMR3ResetCpu(pVM->apCpusR3[idCpu]);
2102
2103	/* Clear all patch information. */
2104	pVM->hm.s.pGuestPatchMem = 0;
2105	pVM->hm.s.pFreeGuestPatchMem = 0;
2106	pVM->hm.s.cbGuestPatchMem = 0;
2107	pVM->hm.s.cPatches = 0;
2108	pVM->hm.s.PatchTree = 0;
2109	pVM->hm.s.fTprPatchingActive = false;
2110	ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2111	}
2112
2113
2114	/**
2115	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2116	*
2117	* @returns VBox strict status code.
2118	* @param pVM The cross context VM structure.
2119	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2120	* @param pvUser Unused.
2121	*/
2122	static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2123	{
2124	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2125
2126	/* Only execute the handler on the VCPU the original patch request was issued. */
2127	if (pVCpu->idCpu != idCpu)
2128	return VINF_SUCCESS;
2129
2130	Log(("hmR3RemovePatches\n"));
2131	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2132	{
2133	uint8_t abInstr[15];
2134	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2135	RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2136	int rc;
2137
2138	#ifdef LOG_ENABLED
2139	char szOutput[256];
2140	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2141	szOutput, sizeof(szOutput), NULL);
2142	if (RT_SUCCESS(rc))
2143	Log(("Patched instr: %s\n", szOutput));
2144	#endif
2145
2146	/* Check if the instruction is still the same. */
2147	rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2148	if (rc != VINF_SUCCESS)
2149	{
2150	Log(("Patched code removed? (rc=%Rrc0\n", rc));
2151	continue; /* swapped out or otherwise removed; skip it. */
2152	}
2153
2154	if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2155	{
2156	Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2157	continue; /* skip it. */
2158	}
2159
2160	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2161	AssertRC(rc);
2162
2163	#ifdef LOG_ENABLED
2164	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2165	szOutput, sizeof(szOutput), NULL);
2166	if (RT_SUCCESS(rc))
2167	Log(("Original instr: %s\n", szOutput));
2168	#endif
2169	}
2170	pVM->hm.s.cPatches = 0;
2171	pVM->hm.s.PatchTree = 0;
2172	pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2173	pVM->hm.s.fTprPatchingActive = false;
2174	return VINF_SUCCESS;
2175	}
2176
2177
2178	/**
2179	* Worker for enabling patching in a VT-x/AMD-V guest.
2180	*
2181	* @returns VBox status code.
2182	* @param pVM The cross context VM structure.
2183	* @param idCpu VCPU to execute hmR3RemovePatches on.
2184	* @param pPatchMem Patch memory range.
2185	* @param cbPatchMem Size of the memory range.
2186	*/
2187	static DECLCALLBACK(int) hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2188	{
2189	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2190	AssertRC(rc);
2191
2192	pVM->hm.s.pGuestPatchMem = pPatchMem;
2193	pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2194	pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2195	return VINF_SUCCESS;
2196	}
2197
2198
2199	/**
2200	* Enable patching in a VT-x/AMD-V guest
2201	*
2202	* @returns VBox status code.
2203	* @param pVM The cross context VM structure.
2204	* @param pPatchMem Patch memory range.
2205	* @param cbPatchMem Size of the memory range.
2206	*/
2207	VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2208	{
2209	VM_ASSERT_EMT(pVM);
2210	Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2211	if (pVM->cCpus > 1)
2212	{
2213	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2214	int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2215	(PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2216	AssertRC(rc);
2217	return rc;
2218	}
2219	return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2220	}
2221
2222
2223	/**
2224	* Disable patching in a VT-x/AMD-V guest.
2225	*
2226	* @returns VBox status code.
2227	* @param pVM The cross context VM structure.
2228	* @param pPatchMem Patch memory range.
2229	* @param cbPatchMem Size of the memory range.
2230	*/
2231	VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2232	{
2233	Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2234	RT_NOREF2(pPatchMem, cbPatchMem);
2235
2236	Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2237	Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2238
2239	/** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2240	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2241	(void *)(uintptr_t)VMMGetCpuId(pVM));
2242	AssertRC(rc);
2243
2244	pVM->hm.s.pGuestPatchMem = 0;
2245	pVM->hm.s.pFreeGuestPatchMem = 0;
2246	pVM->hm.s.cbGuestPatchMem = 0;
2247	pVM->hm.s.fTprPatchingActive = false;
2248	return VINF_SUCCESS;
2249	}
2250
2251
2252	/**
2253	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2254	*
2255	* @returns VBox strict status code.
2256	* @param pVM The cross context VM structure.
2257	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2258	* @param pvUser User specified CPU context.
2259	*
2260	*/
2261	static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2262	{
2263	/*
2264	* Only execute the handler on the VCPU the original patch request was
2265	* issued. (The other CPU(s) might not yet have switched to protected
2266	* mode, nor have the correct memory context.)
2267	*/
2268	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2269	if (pVCpu->idCpu != idCpu)
2270	return VINF_SUCCESS;
2271
2272	/*
2273	* We're racing other VCPUs here, so don't try patch the instruction twice
2274	* and make sure there is still room for our patch record.
2275	*/
2276	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2277	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2278	if (pPatch)
2279	{
2280	Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2281	return VINF_SUCCESS;
2282	}
2283	uint32_t const idx = pVM->hm.s.cPatches;
2284	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2285	{
2286	Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2287	return VINF_SUCCESS;
2288	}
2289	pPatch = &pVM->hm.s.aPatches[idx];
2290
2291	Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2292
2293	/*
2294	* Disassembler the instruction and get cracking.
2295	*/
2296	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2297	DISSTATE Dis;
2298	uint32_t cbOp;
2299	int rc = EMInterpretDisasCurrent(pVCpu, &Dis, &cbOp);
2300	AssertRC(rc);
2301	if ( rc == VINF_SUCCESS
2302	&& Dis.pCurInstr->uOpcode == OP_MOV
2303	&& cbOp >= 3)
2304	{
2305	static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2306
2307	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2308	AssertRC(rc);
2309
2310	pPatch->cbOp = cbOp;
2311
2312	if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2313	{
2314	/* write. */
2315	if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2316	{
2317	pPatch->enmType = HMTPRINSTR_WRITE_REG;
2318	pPatch->uSrcOperand = Dis.Param2.arch.x86.Base.idxGenReg;
2319	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", Dis.Param2.arch.x86.Base.idxGenReg));
2320	}
2321	else
2322	{
2323	Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2324	pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2325	pPatch->uSrcOperand = Dis.Param2.uValue;
2326	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", Dis.Param2.uValue));
2327	}
2328	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2329	AssertRC(rc);
2330
2331	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2332	pPatch->cbNewOp = sizeof(s_abVMMCall);
2333	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2334	}
2335	else
2336	{
2337	/*
2338	* TPR Read.
2339	*
2340	* Found:
2341	* mov eax, dword [fffe0080] (5 bytes)
2342	* Check if next instruction is:
2343	* shr eax, 4
2344	*/
2345	Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2346
2347	uint8_t const idxMmioReg = Dis.Param1.arch.x86.Base.idxGenReg;
2348	uint8_t const cbOpMmio = cbOp;
2349	uint64_t const uSavedRip = pCtx->rip;
2350
2351	pCtx->rip += cbOp;
2352	rc = EMInterpretDisasCurrent(pVCpu, &Dis, &cbOp);
2353	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2354	pCtx->rip = uSavedRip;
2355
2356	if ( rc == VINF_SUCCESS
2357	&& Dis.pCurInstr->uOpcode == OP_SHR
2358	&& Dis.Param1.fUse == DISUSE_REG_GEN32
2359	&& Dis.Param1.arch.x86.Base.idxGenReg == idxMmioReg
2360	&& Dis.Param2.fUse == DISUSE_IMMEDIATE8
2361	&& Dis.Param2.uValue == 4
2362	&& cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2363	{
2364	uint8_t abInstr[15];
2365
2366	/* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2367	access CR8 in 32-bit mode and not cause a #VMEXIT. */
2368	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2369	AssertRC(rc);
2370
2371	pPatch->cbOp = cbOpMmio + cbOp;
2372
2373	/* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2374	abInstr[0] = 0xf0;
2375	abInstr[1] = 0x0f;
2376	abInstr[2] = 0x20;
2377	abInstr[3] = 0xc0 \| Dis.Param1.arch.x86.Base.idxGenReg;
2378	for (unsigned i = 4; i < pPatch->cbOp; i++)
2379	abInstr[i] = 0x90; /* nop */
2380
2381	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2382	AssertRC(rc);
2383
2384	memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2385	pPatch->cbNewOp = pPatch->cbOp;
2386	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2387
2388	Log(("Acceptable read/shr candidate!\n"));
2389	pPatch->enmType = HMTPRINSTR_READ_SHR4;
2390	}
2391	else
2392	{
2393	pPatch->enmType = HMTPRINSTR_READ;
2394	pPatch->uDstOperand = idxMmioReg;
2395
2396	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2397	AssertRC(rc);
2398
2399	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2400	pPatch->cbNewOp = sizeof(s_abVMMCall);
2401	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2402	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2403	}
2404	}
2405
2406	pPatch->Core.Key = pCtx->eip;
2407	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2408	AssertRC(rc);
2409
2410	pVM->hm.s.cPatches++;
2411	return VINF_SUCCESS;
2412	}
2413
2414	/*
2415	* Save invalid patch, so we will not try again.
2416	*/
2417	Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2418	pPatch->Core.Key = pCtx->eip;
2419	pPatch->enmType = HMTPRINSTR_INVALID;
2420	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2421	AssertRC(rc);
2422	pVM->hm.s.cPatches++;
2423	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2424	return VINF_SUCCESS;
2425	}
2426
2427
2428	/**
2429	* Callback to patch a TPR instruction (jump to generated code).
2430	*
2431	* @returns VBox strict status code.
2432	* @param pVM The cross context VM structure.
2433	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2434	* @param pvUser User specified CPU context.
2435	*
2436	*/
2437	static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2438	{
2439	/*
2440	* Only execute the handler on the VCPU the original patch request was
2441	* issued. (The other CPU(s) might not yet have switched to protected
2442	* mode, nor have the correct memory context.)
2443	*/
2444	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2445	if (pVCpu->idCpu != idCpu)
2446	return VINF_SUCCESS;
2447
2448	/*
2449	* We're racing other VCPUs here, so don't try patch the instruction twice
2450	* and make sure there is still room for our patch record.
2451	*/
2452	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2453	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2454	if (pPatch)
2455	{
2456	Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2457	return VINF_SUCCESS;
2458	}
2459	uint32_t const idx = pVM->hm.s.cPatches;
2460	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2461	{
2462	Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2463	return VINF_SUCCESS;
2464	}
2465	pPatch = &pVM->hm.s.aPatches[idx];
2466
2467	Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2468	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2469
2470	/*
2471	* Disassemble the instruction and get cracking.
2472	*/
2473	DISSTATE Dis;
2474	uint32_t cbOp;
2475	int rc = EMInterpretDisasCurrent(pVCpu, &Dis, &cbOp);
2476	AssertRC(rc);
2477	if ( rc == VINF_SUCCESS
2478	&& Dis.pCurInstr->uOpcode == OP_MOV
2479	&& cbOp >= 5)
2480	{
2481	uint8_t aPatch[64];
2482	uint32_t off = 0;
2483
2484	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2485	AssertRC(rc);
2486
2487	pPatch->cbOp = cbOp;
2488	pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2489
2490	if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2491	{
2492	/*
2493	* TPR write:
2494	*
2495	* push ECX [51]
2496	* push EDX [52]
2497	* push EAX [50]
2498	* xor EDX,EDX [31 D2]
2499	* mov EAX,EAX [89 C0]
2500	* or
2501	* mov EAX,0000000CCh [B8 CC 00 00 00]
2502	* mov ECX,0C0000082h [B9 82 00 00 C0]
2503	* wrmsr [0F 30]
2504	* pop EAX [58]
2505	* pop EDX [5A]
2506	* pop ECX [59]
2507	* jmp return_address [E9 return_address]
2508	*/
2509	bool fUsesEax = (Dis.Param2.fUse == DISUSE_REG_GEN32 && Dis.Param2.arch.x86.Base.idxGenReg == DISGREG_EAX);
2510
2511	aPatch[off++] = 0x51; /* push ecx */
2512	aPatch[off++] = 0x52; /* push edx */
2513	if (!fUsesEax)
2514	aPatch[off++] = 0x50; /* push eax */
2515	aPatch[off++] = 0x31; /* xor edx, edx */
2516	aPatch[off++] = 0xd2;
2517	if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2518	{
2519	if (!fUsesEax)
2520	{
2521	aPatch[off++] = 0x89; /* mov eax, src_reg */
2522	aPatch[off++] = MAKE_MODRM(3, Dis.Param2.arch.x86.Base.idxGenReg, DISGREG_EAX);
2523	}
2524	}
2525	else
2526	{
2527	Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2528	aPatch[off++] = 0xb8; /* mov eax, immediate */
2529	(uint32_t )&aPatch[off] = Dis.Param2.uValue;
2530	off += sizeof(uint32_t);
2531	}
2532	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2533	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2534	off += sizeof(uint32_t);
2535
2536	aPatch[off++] = 0x0f; /* wrmsr */
2537	aPatch[off++] = 0x30;
2538	if (!fUsesEax)
2539	aPatch[off++] = 0x58; /* pop eax */
2540	aPatch[off++] = 0x5a; /* pop edx */
2541	aPatch[off++] = 0x59; /* pop ecx */
2542	}
2543	else
2544	{
2545	/*
2546	* TPR read:
2547	*
2548	* push ECX [51]
2549	* push EDX [52]
2550	* push EAX [50]
2551	* mov ECX,0C0000082h [B9 82 00 00 C0]
2552	* rdmsr [0F 32]
2553	* mov EAX,EAX [89 C0]
2554	* pop EAX [58]
2555	* pop EDX [5A]
2556	* pop ECX [59]
2557	* jmp return_address [E9 return_address]
2558	*/
2559	Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2560
2561	if (Dis.Param1.arch.x86.Base.idxGenReg != DISGREG_ECX)
2562	aPatch[off++] = 0x51; /* push ecx */
2563	if (Dis.Param1.arch.x86.Base.idxGenReg != DISGREG_EDX )
2564	aPatch[off++] = 0x52; /* push edx */
2565	if (Dis.Param1.arch.x86.Base.idxGenReg != DISGREG_EAX)
2566	aPatch[off++] = 0x50; /* push eax */
2567
2568	aPatch[off++] = 0x31; /* xor edx, edx */
2569	aPatch[off++] = 0xd2;
2570
2571	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2572	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2573	off += sizeof(uint32_t);
2574
2575	aPatch[off++] = 0x0f; /* rdmsr */
2576	aPatch[off++] = 0x32;
2577
2578	if (Dis.Param1.arch.x86.Base.idxGenReg != DISGREG_EAX)
2579	{
2580	aPatch[off++] = 0x89; /* mov dst_reg, eax */
2581	aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, Dis.Param1.arch.x86.Base.idxGenReg);
2582	}
2583
2584	if (Dis.Param1.arch.x86.Base.idxGenReg != DISGREG_EAX)
2585	aPatch[off++] = 0x58; /* pop eax */
2586	if (Dis.Param1.arch.x86.Base.idxGenReg != DISGREG_EDX )
2587	aPatch[off++] = 0x5a; /* pop edx */
2588	if (Dis.Param1.arch.x86.Base.idxGenReg != DISGREG_ECX)
2589	aPatch[off++] = 0x59; /* pop ecx */
2590	}
2591	aPatch[off++] = 0xe9; /* jmp return_address */
2592	(RTRCUINTPTR )&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2593	off += sizeof(RTRCUINTPTR);
2594
2595	if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2596	{
2597	/* Write new code to the patch buffer. */
2598	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2599	AssertRC(rc);
2600
2601	#ifdef LOG_ENABLED
2602	uint32_t cbCurInstr;
2603	for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2604	GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2605	GCPtrInstr += RT_MAX(cbCurInstr, 1))
2606	{
2607	char szOutput[256];
2608	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2609	szOutput, sizeof(szOutput), &cbCurInstr);
2610	if (RT_SUCCESS(rc))
2611	Log(("Patch instr %s\n", szOutput));
2612	else
2613	Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2614	}
2615	#endif
2616
2617	pPatch->aNewOpcode[0] = 0xE9;
2618	(RTRCUINTPTR )&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2619
2620	/* Overwrite the TPR instruction with a jump. */
2621	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2622	AssertRC(rc);
2623
2624	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2625
2626	pVM->hm.s.pFreeGuestPatchMem += off;
2627	pPatch->cbNewOp = 5;
2628
2629	pPatch->Core.Key = pCtx->eip;
2630	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2631	AssertRC(rc);
2632
2633	pVM->hm.s.cPatches++;
2634	pVM->hm.s.fTprPatchingActive = true;
2635	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2636	return VINF_SUCCESS;
2637	}
2638
2639	Log(("Ran out of space in our patch buffer!\n"));
2640	}
2641	else
2642	Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2643
2644
2645	/*
2646	* Save invalid patch, so we will not try again.
2647	*/
2648	pPatch = &pVM->hm.s.aPatches[idx];
2649	pPatch->Core.Key = pCtx->eip;
2650	pPatch->enmType = HMTPRINSTR_INVALID;
2651	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2652	AssertRC(rc);
2653	pVM->hm.s.cPatches++;
2654	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2655	return VINF_SUCCESS;
2656	}
2657
2658
2659	/**
2660	* Attempt to patch TPR mmio instructions.
2661	*
2662	* @returns VBox status code.
2663	* @param pVM The cross context VM structure.
2664	* @param pVCpu The cross context virtual CPU structure.
2665	*/
2666	VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2667	{
2668	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2669	pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2670	(void *)(uintptr_t)pVCpu->idCpu);
2671	AssertRC(rc);
2672	return rc;
2673	}
2674
2675
2676	/**
2677	* Checks if we need to reschedule due to VMM device heap changes.
2678	*
2679	* @returns true if a reschedule is required, otherwise false.
2680	* @param pVM The cross context VM structure.
2681	* @param pCtx VM execution context.
2682	*/
2683	VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCCPUMCTX pCtx)
2684	{
2685	/*
2686	* The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2687	* when the unrestricted guest execution feature is missing (VT-x only).
2688	*/
2689	if ( pVM->hm.s.vmx.fEnabled
2690	&& !pVM->hm.s.vmx.fUnrestrictedGuestCfg
2691	&& CPUMIsGuestInRealModeEx(pCtx)
2692	&& !PDMVmmDevHeapIsEnabled(pVM))
2693	return true;
2694
2695	return false;
2696	}
2697
2698
2699	/**
2700	* Noticiation callback from DBGF when interrupt breakpoints or generic debug
2701	* event settings changes.
2702	*
2703	* DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2704	* function is just updating the VM globals.
2705	*
2706	* @param pVM The VM cross context VM structure.
2707	* @thread EMT(0)
2708	*/
2709	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2710	{
2711	/* Interrupts. */
2712	bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2713	\|\| pVM->dbgf.ro.cHardIntBreakpoints > 0;
2714
2715	/* CPU Exceptions. */
2716	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2717	!fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2718	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2719	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2720
2721	/* Common VM exits. */
2722	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2723	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2724	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2725	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2726
2727	/* Vendor specific VM exits. */
2728	if (HMR3IsVmxEnabled(pVM->pUVM))
2729	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2730	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2731	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2732	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2733	else
2734	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2735	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2736	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2737	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2738
2739	/* Done. */
2740	pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2741	}
2742
2743
2744	/**
2745	* Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2746	*
2747	* HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2748	* per CPU settings.
2749	*
2750	* @param pVM The VM cross context VM structure.
2751	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2752	*/
2753	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2754	{
2755	pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction \| pVM->hm.s.fUseDebugLoop;
2756	}
2757
2758
2759	/**
2760	* Checks if we are currently using hardware acceleration.
2761	*
2762	* @returns true if hardware acceleration is being used, otherwise false.
2763	* @param pVCpu The cross context virtual CPU structure.
2764	*/
2765	VMMR3_INT_DECL(bool) HMR3IsActive(PCVMCPU pVCpu)
2766	{
2767	return pVCpu->hm.s.fActive;
2768	}
2769
2770
2771	/**
2772	* External interface for querying whether hardware acceleration is enabled.
2773	*
2774	* @returns true if VT-x or AMD-V is being used, otherwise false.
2775	* @param pUVM The user mode VM handle.
2776	* @sa HMIsEnabled, HMIsEnabledNotMacro.
2777	*/
2778	VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2779	{
2780	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2781	PVM pVM = pUVM->pVM;
2782	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2783	return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2784	}
2785
2786
2787	/**
2788	* External interface for querying whether VT-x is being used.
2789	*
2790	* @returns true if VT-x is being used, otherwise false.
2791	* @param pUVM The user mode VM handle.
2792	* @sa HMR3IsSvmEnabled, HMIsEnabled
2793	*/
2794	VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2795	{
2796	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2797	PVM pVM = pUVM->pVM;
2798	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2799	return pVM->hm.s.vmx.fEnabled
2800	&& pVM->hm.s.vmx.fSupported
2801	&& pVM->fHMEnabled;
2802	}
2803
2804
2805	/**
2806	* External interface for querying whether AMD-V is being used.
2807	*
2808	* @returns true if VT-x is being used, otherwise false.
2809	* @param pUVM The user mode VM handle.
2810	* @sa HMR3IsVmxEnabled, HMIsEnabled
2811	*/
2812	VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2813	{
2814	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2815	PVM pVM = pUVM->pVM;
2816	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2817	return pVM->hm.s.svm.fEnabled
2818	&& pVM->hm.s.svm.fSupported
2819	&& pVM->fHMEnabled;
2820	}
2821
2822
2823	/**
2824	* Checks if we are currently using nested paging.
2825	*
2826	* @returns true if nested paging is being used, otherwise false.
2827	* @param pUVM The user mode VM handle.
2828	*/
2829	VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2830	{
2831	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2832	PVM pVM = pUVM->pVM;
2833	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2834	return pVM->hm.s.fNestedPagingCfg;
2835	}
2836
2837
2838	/**
2839	* Checks if virtualized APIC registers are enabled.
2840	*
2841	* When enabled this feature allows the hardware to access most of the
2842	* APIC registers in the virtual-APIC page without causing VM-exits. See
2843	* Intel spec. 29.1.1 "Virtualized APIC Registers".
2844	*
2845	* @returns true if virtualized APIC registers is enabled, otherwise
2846	* false.
2847	* @param pUVM The user mode VM handle.
2848	*/
2849	VMMR3DECL(bool) HMR3AreVirtApicRegsEnabled(PUVM pUVM)
2850	{
2851	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2852	PVM pVM = pUVM->pVM;
2853	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2854	return pVM->hm.s.fVirtApicRegs;
2855	}
2856
2857
2858	/**
2859	* Checks if APIC posted-interrupt processing is enabled.
2860	*
2861	* This returns whether we can deliver interrupts to the guest without
2862	* leaving guest-context by updating APIC state from host-context.
2863	*
2864	* @returns true if APIC posted-interrupt processing is enabled,
2865	* otherwise false.
2866	* @param pUVM The user mode VM handle.
2867	*/
2868	VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2869	{
2870	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2871	PVM pVM = pUVM->pVM;
2872	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2873	return pVM->hm.s.fPostedIntrs;
2874	}
2875
2876
2877	/**
2878	* Checks if we are currently using VPID in VT-x mode.
2879	*
2880	* @returns true if VPID is being used, otherwise false.
2881	* @param pUVM The user mode VM handle.
2882	*/
2883	VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2884	{
2885	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2886	PVM pVM = pUVM->pVM;
2887	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2888	return pVM->hm.s.ForR3.vmx.fVpid;
2889	}
2890
2891
2892	/**
2893	* Checks if we are currently using VT-x unrestricted execution,
2894	* aka UX.
2895	*
2896	* @returns true if UX is being used, otherwise false.
2897	* @param pUVM The user mode VM handle.
2898	*/
2899	VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2900	{
2901	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2902	PVM pVM = pUVM->pVM;
2903	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2904	return pVM->hm.s.vmx.fUnrestrictedGuestCfg
2905	\|\| pVM->hm.s.svm.fSupported;
2906	}
2907
2908
2909	/**
2910	* Checks if the VMX-preemption timer is being used.
2911	*
2912	* @returns true if the VMX-preemption timer is being used, otherwise false.
2913	* @param pVM The cross context VM structure.
2914	*/
2915	VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2916	{
2917	return HMIsEnabled(pVM)
2918	&& pVM->hm.s.vmx.fEnabled
2919	&& pVM->hm.s.vmx.fUsePreemptTimerCfg;
2920	}
2921
2922
2923	#ifdef TODO_9217_VMCSINFO
2924	/**
2925	* Helper for HMR3CheckError to log VMCS controls to the release log.
2926	*
2927	* @param idCpu The Virtual CPU ID.
2928	* @param pVmcsInfo The VMCS info. object.
2929	*/
2930	static void hmR3CheckErrorLogVmcsCtls(VMCPUID idCpu, PCVMXVMCSINFO pVmcsInfo)
2931	{
2932	LogRel(("HM: CPU[%u] PinCtls %#RX32\n", idCpu, pVmcsInfo->u32PinCtls));
2933	{
2934	uint32_t const u32Val = pVmcsInfo->u32PinCtls;
2935	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
2936	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
2937	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
2938	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
2939	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
2940	}
2941	LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls));
2942	{
2943	uint32_t const u32Val = pVmcsInfo->u32ProcCtls;
2944	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
2945	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
2946	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
2947	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
2948	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
2949	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
2950	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
2951	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
2952	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
2953	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TERTIARY_CTLS );
2954	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
2955	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
2956	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
2957	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
2958	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
2959	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
2960	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
2961	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
2962	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
2963	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
2964	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
2965	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
2966	}
2967	LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls2));
2968	{
2969	uint32_t const u32Val = pVmcsInfo->u32ProcCtls2;
2970	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
2971	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
2972	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
2973	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
2974	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
2975	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
2976	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
2977	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST );
2978	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
2979	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
2980	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
2981	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
2982	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
2983	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
2984	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
2985	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
2986	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
2987	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
2988	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_XCPT_VE );
2989	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
2990	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
2991	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
2992	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_SPP_EPT );
2993	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PT_EPT );
2994	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
2995	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_USER_WAIT_PAUSE );
2996	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLV_EXIT );
2997	}
2998	LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", idCpu, pVmcsInfo->u32EntryCtls));
2999	{
3000	uint32_t const u32Val = pVmcsInfo->u32EntryCtls;
3001	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
3002	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
3003	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
3004	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
3005	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
3006	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
3007	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
3008	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR );
3009	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
3010	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR );
3011	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_CET_STATE );
3012	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PKRS_MSR );
3013	}
3014	LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", idCpu, pVmcsInfo->u32ExitCtls));
3015	{
3016	uint32_t const u32Val = pVmcsInfo->u32ExitCtls;
3017	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
3018	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
3019	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
3020	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
3021	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
3022	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
3023	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
3024	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
3025	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
3026	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR );
3027	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT );
3028	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR );
3029	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_CET_STATE );
3030	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PKRS_MSR );
3031	}
3032	}
3033	#endif
3034
3035
3036	/**
3037	* Check fatal VT-x/AMD-V error and produce some meaningful
3038	* log release message.
3039	*
3040	* @param pVM The cross context VM structure.
3041	* @param iStatusCode VBox status code.
3042	*/
3043	VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3044	{
3045	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3046	{
3047	/** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3048	* might be getting inaccurate values for non-guru'ing EMTs. */
3049	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3050	#ifdef TODO_9217_VMCSINFO
3051	PCVMXVMCSINFOSHARED pVmcsInfo = hmGetVmxActiveVmcsInfoShared(pVCpu);
3052	#endif
3053	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3054	switch (iStatusCode)
3055	{
3056	case VERR_VMX_INVALID_VMCS_PTR:
3057	{
3058	LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3059	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3060	#ifdef TODO_9217_VMCSINFO
3061	LogRel(("HM: CPU[%u] Current pointer %#RHp vs %#RHp\n", idCpu, pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs,
3062	pVmcsInfo->HCPhysVmcs));
3063	#endif
3064	LogRel(("HM: CPU[%u] Current VMCS version %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
3065	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3066	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3067	break;
3068	}
3069
3070	case VERR_VMX_UNABLE_TO_START_VM:
3071	{
3072	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3073	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3074	LogRel(("HM: CPU[%u] Instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
3075	LogRel(("HM: CPU[%u] Exit reason %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3076
3077	if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
3078	\|\| pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
3079	{
3080	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3081	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3082	}
3083	else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
3084	{
3085	#ifdef TODO_9217_VMCSINFO
3086	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3087	LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
3088	LogRel(("HM: CPU[%u] HCPhysGuestMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrLoad));
3089	LogRel(("HM: CPU[%u] HCPhysGuestMsrStore %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrStore));
3090	LogRel(("HM: CPU[%u] HCPhysHostMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysHostMsrLoad));
3091	LogRel(("HM: CPU[%u] cEntryMsrLoad %u\n", idCpu, pVmcsInfo->cEntryMsrLoad));
3092	LogRel(("HM: CPU[%u] cExitMsrStore %u\n", idCpu, pVmcsInfo->cExitMsrStore));
3093	LogRel(("HM: CPU[%u] cExitMsrLoad %u\n", idCpu, pVmcsInfo->cExitMsrLoad));
3094	#endif
3095	}
3096	/** @todo Log VM-entry event injection control fields
3097	* VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3098	* and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3099	break;
3100	}
3101
3102	case VERR_VMX_INVALID_GUEST_STATE:
3103	{
3104	LogRel(("HM: VERR_VMX_INVALID_GUEST_STATE:\n"));
3105	LogRel(("HM: CPU[%u] HM error = %#RX32\n", idCpu, pVCpu->hm.s.u32HMError));
3106	LogRel(("HM: CPU[%u] Guest-intr. state = %#RX32\n", idCpu, pVCpu->hm.s.vmx.LastError.u32GuestIntrState));
3107	#ifdef TODO_9217_VMCSINFO
3108	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3109	#endif
3110	break;
3111	}
3112
3113	/* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3114	case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3115	case VERR_VMX_INVALID_VMXON_PTR:
3116	case VERR_VMX_UNEXPECTED_EXIT:
3117	case VERR_VMX_INVALID_VMCS_FIELD:
3118	case VERR_SVM_UNKNOWN_EXIT:
3119	case VERR_SVM_UNEXPECTED_EXIT:
3120	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3121	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3122	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3123	break;
3124	}
3125	}
3126
3127	if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3128	{
3129	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed1));
3130	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed0));
3131	}
3132	else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3133	LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.ForR3.vmx.HCPhysVmxEnableError));
3134	}
3135
3136
3137	/**
3138	* Execute state save operation.
3139	*
3140	* Save only data that cannot be re-loaded while entering HM ring-0 code. This
3141	* is because we always save the VM state from ring-3 and thus most HM state
3142	* will be re-synced dynamically at runtime and don't need to be part of the VM
3143	* saved state.
3144	*
3145	* @returns VBox status code.
3146	* @param pVM The cross context VM structure.
3147	* @param pSSM SSM operation handle.
3148	*/
3149	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3150	{
3151	Log(("hmR3Save:\n"));
3152
3153	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3154	{
3155	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3156	Assert(!pVCpu->hm.s.Event.fPending);
3157	if (pVM->cpum.ro.GuestFeatures.fSvm)
3158	{
3159	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3160	SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3161	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3162	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3163	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3164	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3165	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3166	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3167	SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3168	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3169	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3170	SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3171	SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3172	SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3173	}
3174	}
3175
3176	/* Save the guest patch data. */
3177	SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3178	SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3179	SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3180
3181	/* Store all the guest patch records too. */
3182	int rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3183	if (RT_FAILURE(rc))
3184	return rc;
3185
3186	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3187	{
3188	AssertCompileSize(HMTPRINSTR, 4);
3189	PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3190	SSMR3PutU32(pSSM, pPatch->Core.Key);
3191	SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3192	SSMR3PutU32(pSSM, pPatch->cbOp);
3193	SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3194	SSMR3PutU32(pSSM, pPatch->cbNewOp);
3195	SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3196	SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3197	SSMR3PutU32(pSSM, pPatch->uDstOperand);
3198	SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3199	rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3200	if (RT_FAILURE(rc))
3201	return rc;
3202	}
3203
3204	return VINF_SUCCESS;
3205	}
3206
3207
3208	/**
3209	* Execute state load operation.
3210	*
3211	* @returns VBox status code.
3212	* @param pVM The cross context VM structure.
3213	* @param pSSM SSM operation handle.
3214	* @param uVersion Data layout version.
3215	* @param uPass The data pass.
3216	*/
3217	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3218	{
3219	int rc;
3220
3221	LogFlowFunc(("uVersion=%u\n", uVersion));
3222	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3223
3224	/*
3225	* Validate version.
3226	*/
3227	if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3228	&& uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3229	&& uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3230	&& uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3231	{
3232	AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3233	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3234	}
3235
3236	/*
3237	* Load per-VCPU state.
3238	*/
3239	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3240	{
3241	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3242	if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3243	{
3244	/* Load the SVM nested hw.virt state if the VM is configured for it. */
3245	if (pVM->cpum.ro.GuestFeatures.fSvm)
3246	{
3247	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3248	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3249	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3250	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3251	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3252	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3253	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3254	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3255	SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3256	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3257	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3258	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3259	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3260	rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3261	AssertRCReturn(rc, rc);
3262	}
3263	}
3264	else
3265	{
3266	/* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3267	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.fPending);
3268	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.u32ErrCode);
3269	SSMR3GetU64(pSSM, &pVCpu->hm.s.Event.u64IntInfo);
3270
3271	/* VMX fWasInRealMode related data. */
3272	uint32_t uDummy;
3273	SSMR3GetU32(pSSM, &uDummy);
3274	SSMR3GetU32(pSSM, &uDummy);
3275	rc = SSMR3GetU32(pSSM, &uDummy);
3276	AssertRCReturn(rc, rc);
3277	}
3278	}
3279
3280	/*
3281	* Load TPR patching data.
3282	*/
3283	if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3284	{
3285	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3286	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3287	SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3288
3289	/* Fetch all TPR patch records. */
3290	rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3291	AssertRCReturn(rc, rc);
3292	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3293	{
3294	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3295	SSMR3GetU32(pSSM, &pPatch->Core.Key);
3296	SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3297	SSMR3GetU32(pSSM, &pPatch->cbOp);
3298	SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3299	SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3300	SSM_GET_ENUM32_RET(pSSM, pPatch->enmType, HMTPRINSTR);
3301
3302	if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3303	pVM->hm.s.fTprPatchingActive = true;
3304	Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT \|\| pVM->hm.s.fTprPatchingActive == false);
3305
3306	SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3307	SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3308	SSMR3GetU32(pSSM, &pPatch->cFaults);
3309	rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3310	AssertRCReturn(rc, rc);
3311
3312	LogFlow(("hmR3Load: patch %d\n", i));
3313	LogFlow(("Key = %x\n", pPatch->Core.Key));
3314	LogFlow(("cbOp = %d\n", pPatch->cbOp));
3315	LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3316	LogFlow(("type = %d\n", pPatch->enmType));
3317	LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3318	LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3319	LogFlow(("cFaults = %d\n", pPatch->cFaults));
3320	LogFlow(("target = %x\n", pPatch->pJumpTarget));
3321
3322	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3323	AssertRCReturn(rc, rc);
3324	}
3325	}
3326
3327	return VINF_SUCCESS;
3328	}
3329
3330
3331	/**
3332	* Displays HM info.
3333	*
3334	* @param pVM The cross context VM structure.
3335	* @param pHlp The info helper functions.
3336	* @param pszArgs Arguments, ignored.
3337	*/
3338	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3339	{
3340	NOREF(pszArgs);
3341	PVMCPU pVCpu = VMMGetCpu(pVM);
3342	if (!pVCpu)
3343	pVCpu = pVM->apCpusR3[0];
3344
3345	if (HMIsEnabled(pVM))
3346	{
3347	if (pVM->hm.s.vmx.fSupported)
3348	pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3349	else
3350	pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3351	pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3352	pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3353	if (pVM->hm.s.vmx.fSupported)
3354	{
3355	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3356	bool const fRealOnV86Active = pVmcsInfoShared->RealMode.fRealOnV86Active;
3357	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3358
3359	pHlp->pfnPrintf(pHlp, " %s VMCS active\n", fNstGstVmcsActive ? "Nested-guest" : "Guest");
3360	pHlp->pfnPrintf(pHlp, " Real-on-v86 active = %RTbool\n", fRealOnV86Active);
3361	if (fRealOnV86Active)
3362	{
3363	pHlp->pfnPrintf(pHlp, " EFlags = %#x\n", pVmcsInfoShared->RealMode.Eflags.u32);
3364	pHlp->pfnPrintf(pHlp, " Attr CS = %#x\n", pVmcsInfoShared->RealMode.AttrCS.u);
3365	pHlp->pfnPrintf(pHlp, " Attr SS = %#x\n", pVmcsInfoShared->RealMode.AttrSS.u);
3366	pHlp->pfnPrintf(pHlp, " Attr DS = %#x\n", pVmcsInfoShared->RealMode.AttrDS.u);
3367	pHlp->pfnPrintf(pHlp, " Attr ES = %#x\n", pVmcsInfoShared->RealMode.AttrES.u);
3368	pHlp->pfnPrintf(pHlp, " Attr FS = %#x\n", pVmcsInfoShared->RealMode.AttrFS.u);
3369	pHlp->pfnPrintf(pHlp, " Attr GS = %#x\n", pVmcsInfoShared->RealMode.AttrGS.u);
3370	}
3371	}
3372	}
3373	else
3374	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3375	}
3376
3377
3378	/**
3379	* Displays the HM Last-Branch-Record info. for the guest.
3380	*
3381	* @param pVM The cross context VM structure.
3382	* @param pHlp The info helper functions.
3383	* @param pszArgs Arguments, ignored.
3384	*/
3385	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3386	{
3387	NOREF(pszArgs);
3388	PVMCPU pVCpu = VMMGetCpu(pVM);
3389	if (!pVCpu)
3390	pVCpu = pVM->apCpusR3[0];
3391
3392	if (!HMIsEnabled(pVM))
3393	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3394	else if (HMIsVmxActive(pVM))
3395	{
3396	if (pVM->hm.s.vmx.fLbrCfg)
3397	{
3398	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3399	uint32_t const cLbrStack = pVM->hm.s.ForR3.vmx.idLbrFromIpMsrLast - pVM->hm.s.ForR3.vmx.idLbrFromIpMsrFirst + 1;
3400
3401	/** @todo r=ramshankar: The index technically varies depending on the CPU, but
3402	* 0xf should cover everything we support thus far. Fix if necessary
3403	* later. */
3404	uint32_t const idxTopOfStack = pVmcsInfoShared->u64LbrTosMsr & 0xf;
3405	if (idxTopOfStack > cLbrStack)
3406	{
3407	pHlp->pfnPrintf(pHlp, "Top-of-stack LBR MSR seems corrupt (index=%u, msr=%#RX64) expected index < %u\n",
3408	idxTopOfStack, pVmcsInfoShared->u64LbrTosMsr, cLbrStack);
3409	return;
3410	}
3411
3412	/*
3413	* Dump the circular buffer of LBR records starting from the most recent record (contained in idxTopOfStack).
3414	*/
3415	pHlp->pfnPrintf(pHlp, "CPU[%u]: LBRs (most-recent first)\n", pVCpu->idCpu);
3416	uint32_t idxCurrent = idxTopOfStack;
3417	Assert(idxTopOfStack < cLbrStack);
3418	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrFromIpMsr) <= cLbrStack);
3419	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrToIpMsr) <= cLbrStack);
3420	for (;;)
3421	{
3422	if (pVM->hm.s.ForR3.vmx.idLbrToIpMsrFirst)
3423	pHlp->pfnPrintf(pHlp, " Branch (%2u): From IP=%#016RX64 - To IP=%#016RX64\n", idxCurrent,
3424	pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent], pVmcsInfoShared->au64LbrToIpMsr[idxCurrent]);
3425	else
3426	pHlp->pfnPrintf(pHlp, " Branch (%2u): LBR=%#RX64\n", idxCurrent, pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent]);
3427
3428	idxCurrent = (idxCurrent - 1) % cLbrStack;
3429	if (idxCurrent == idxTopOfStack)
3430	break;
3431	}
3432	}
3433	else
3434	pHlp->pfnPrintf(pHlp, "VM not configured to record LBRs for the guest\n");
3435	}
3436	else
3437	{
3438	Assert(HMIsSvmActive(pVM));
3439	/** @todo SVM: LBRs (get them from VMCB if possible). */
3440	pHlp->pfnPrintf(pHlp, "SVM LBR not implemented.\n");
3441	}
3442	}
3443
3444
3445	/**
3446	* Displays the HM pending event.
3447	*
3448	* @param pVM The cross context VM structure.
3449	* @param pHlp The info helper functions.
3450	* @param pszArgs Arguments, ignored.
3451	*/
3452	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3453	{
3454	NOREF(pszArgs);
3455	PVMCPU pVCpu = VMMGetCpu(pVM);
3456	if (!pVCpu)
3457	pVCpu = pVM->apCpusR3[0];
3458
3459	if (HMIsEnabled(pVM))
3460	{
3461	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3462	if (pVCpu->hm.s.Event.fPending)
3463	{
3464	pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3465	pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3466	pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3467	pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3468	}
3469	}
3470	else
3471	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3472	}
3473
3474
3475	/**
3476	* Displays the SVM nested-guest VMCB cache.
3477	*
3478	* @param pVM The cross context VM structure.
3479	* @param pHlp The info helper functions.
3480	* @param pszArgs Arguments, ignored.
3481	*/
3482	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3483	{
3484	NOREF(pszArgs);
3485	PVMCPU pVCpu = VMMGetCpu(pVM);
3486	if (!pVCpu)
3487	pVCpu = pVM->apCpusR3[0];
3488
3489	bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3490	if ( fSvmEnabled
3491	&& pVM->cpum.ro.GuestFeatures.fSvm)
3492	{
3493	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3494	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3495	pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3496	pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3497	pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3498	pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3499	pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3500	pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3501	pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3502	pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3503	pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3504	pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3505	pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3506	pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3507	pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3508	}
3509	else
3510	{
3511	if (!fSvmEnabled)
3512	pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3513	else
3514	pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3515	}
3516	}
3517

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source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 100101

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