HM.cpp@ 90439

Last change on this file since 90439 was 89976, checked in by vboxsync, 3 years ago
VMM/HMVMX: Deal with #ACs triggered by split-lock detection on the host. bugref:10052
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 156.6 KB

Line
1	/* $Id: HM.cpp 89976 2021-06-30 11:03:22Z vboxsync $ */
2	/** @file
3	* HM - Intel/AMD VM Hardware Support Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19	*
20	* The HM manages guest execution using the VT-x and AMD-V CPU hardware
21	* extensions.
22	*
23	* {summary of what HM does}
24	*
25	* Hardware assisted virtualization manager was originally abbreviated HWACCM,
26	* however that was cumbersome to write and parse for such a central component,
27	* so it was shortened to HM when refactoring the code in the 4.3 development
28	* cycle.
29	*
30	* {add sections with more details}
31	*
32	* @sa @ref grp_hm
33	*/
34
35
36	/*********************************************************************************************************************************
37	* Header Files *
38	*********************************************************************************************************************************/
39	#define LOG_GROUP LOG_GROUP_HM
40	#define VMCPU_INCL_CPUM_GST_CTX
41	#include <VBox/vmm/cpum.h>
42	#include <VBox/vmm/stam.h>
43	#include <VBox/vmm/mm.h>
44	#include <VBox/vmm/em.h>
45	#include <VBox/vmm/pdmapi.h>
46	#include <VBox/vmm/pgm.h>
47	#include <VBox/vmm/ssm.h>
48	#include <VBox/vmm/gim.h>
49	#include <VBox/vmm/trpm.h>
50	#include <VBox/vmm/dbgf.h>
51	#include <VBox/vmm/iom.h>
52	#include <VBox/vmm/iem.h>
53	#include <VBox/vmm/selm.h>
54	#include <VBox/vmm/nem.h>
55	#include <VBox/vmm/hm_vmx.h>
56	#include <VBox/vmm/hm_svm.h>
57	#include "HMInternal.h"
58	#include <VBox/vmm/vmcc.h>
59	#include <VBox/err.h>
60	#include <VBox/param.h>
61
62	#include <iprt/assert.h>
63	#include <VBox/log.h>
64	#include <iprt/asm.h>
65	#include <iprt/asm-amd64-x86.h>
66	#include <iprt/env.h>
67	#include <iprt/thread.h>
68
69
70	/*********************************************************************************************************************************
71	* Defined Constants And Macros *
72	*********************************************************************************************************************************/
73	/** @def HMVMX_REPORT_FEAT
74	* Reports VT-x feature to the release log.
75	*
76	* @param a_uAllowed1 Mask of allowed-1 feature bits.
77	* @param a_uAllowed0 Mask of allowed-0 feature bits.
78	* @param a_StrDesc The description string to report.
79	* @param a_Featflag Mask of the feature to report.
80	*/
81	#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
82	do { \
83	if ((a_uAllowed1) & (a_Featflag)) \
84	{ \
85	if ((a_uAllowed0) & (a_Featflag)) \
86	LogRel(("HM: " a_StrDesc " (must be set)\n")); \
87	else \
88	LogRel(("HM: " a_StrDesc "\n")); \
89	} \
90	else \
91	LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
92	} while (0)
93
94	/** @def HMVMX_REPORT_ALLOWED_FEAT
95	* Reports an allowed VT-x feature to the release log.
96	*
97	* @param a_uAllowed1 Mask of allowed-1 feature bits.
98	* @param a_StrDesc The description string to report.
99	* @param a_FeatFlag Mask of the feature to report.
100	*/
101	#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
102	do { \
103	if ((a_uAllowed1) & (a_FeatFlag)) \
104	LogRel(("HM: " a_StrDesc "\n")); \
105	else \
106	LogRel(("HM: " a_StrDesc " not supported\n")); \
107	} while (0)
108
109	/** @def HMVMX_REPORT_MSR_CAP
110	* Reports MSR feature capability.
111	*
112	* @param a_MsrCaps Mask of MSR feature bits.
113	* @param a_StrDesc The description string to report.
114	* @param a_fCap Mask of the feature to report.
115	*/
116	#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
117	do { \
118	if ((a_MsrCaps) & (a_fCap)) \
119	LogRel(("HM: " a_StrDesc "\n")); \
120	} while (0)
121
122	/** @def HMVMX_LOGREL_FEAT
123	* Dumps a feature flag from a bitmap of features to the release log.
124	*
125	* @param a_fVal The value of all the features.
126	* @param a_fMask The specific bitmask of the feature.
127	*/
128	#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
129	do { \
130	if ((a_fVal) & (a_fMask)) \
131	LogRel(("HM: %s\n", #a_fMask)); \
132	} while (0)
133
134
135	/*********************************************************************************************************************************
136	* Internal Functions *
137	*********************************************************************************************************************************/
138	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
139	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
140	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
141	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
142	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
143	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
144	static int hmR3InitFinalizeR3(PVM pVM);
145	static int hmR3InitFinalizeR0(PVM pVM);
146	static int hmR3InitFinalizeR0Intel(PVM pVM);
147	static int hmR3InitFinalizeR0Amd(PVM pVM);
148	static int hmR3TermCPU(PVM pVM);
149
150
151	#ifdef VBOX_WITH_STATISTICS
152	/**
153	* Returns the name of the hardware exception.
154	*
155	* @returns The name of the hardware exception.
156	* @param uVector The exception vector.
157	*/
158	static const char *hmR3GetXcptName(uint8_t uVector)
159	{
160	switch (uVector)
161	{
162	case X86_XCPT_DE: return "#DE";
163	case X86_XCPT_DB: return "#DB";
164	case X86_XCPT_NMI: return "#NMI";
165	case X86_XCPT_BP: return "#BP";
166	case X86_XCPT_OF: return "#OF";
167	case X86_XCPT_BR: return "#BR";
168	case X86_XCPT_UD: return "#UD";
169	case X86_XCPT_NM: return "#NM";
170	case X86_XCPT_DF: return "#DF";
171	case X86_XCPT_CO_SEG_OVERRUN: return "#CO_SEG_OVERRUN";
172	case X86_XCPT_TS: return "#TS";
173	case X86_XCPT_NP: return "#NP";
174	case X86_XCPT_SS: return "#SS";
175	case X86_XCPT_GP: return "#GP";
176	case X86_XCPT_PF: return "#PF";
177	case X86_XCPT_MF: return "#MF";
178	case X86_XCPT_AC: return "#AC";
179	case X86_XCPT_MC: return "#MC";
180	case X86_XCPT_XF: return "#XF";
181	case X86_XCPT_VE: return "#VE";
182	case X86_XCPT_CP: return "#CP";
183	case X86_XCPT_VC: return "#VC";
184	case X86_XCPT_SX: return "#SX";
185	}
186	return "Reserved";
187	}
188	#endif /* VBOX_WITH_STATISTICS */
189
190
191	/**
192	* Initializes the HM.
193	*
194	* This is the very first component to really do init after CFGM so that we can
195	* establish the predominant execution engine for the VM prior to initializing
196	* other modules. It takes care of NEM initialization if needed (HM disabled or
197	* not available in HW).
198	*
199	* If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
200	* hypervisor API via NEM, and then back on raw-mode if that isn't available
201	* either. The fallback to raw-mode will not happen if /HM/HMForced is set
202	* (like for guest using SMP or 64-bit as well as for complicated guest like OS
203	* X, OS/2 and others).
204	*
205	* Note that a lot of the set up work is done in ring-0 and thus postponed till
206	* the ring-3 and ring-0 callback to HMR3InitCompleted.
207	*
208	* @returns VBox status code.
209	* @param pVM The cross context VM structure.
210	*
211	* @remarks Be careful with what we call here, since most of the VMM components
212	* are uninitialized.
213	*/
214	VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
215	{
216	LogFlowFunc(("\n"));
217
218	/*
219	* Assert alignment and sizes.
220	*/
221	AssertCompileMemberAlignment(VM, hm.s, 32);
222	AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
223
224	/*
225	* Register the saved state data unit.
226	*/
227	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
228	NULL, NULL, NULL,
229	NULL, hmR3Save, NULL,
230	NULL, hmR3Load, NULL);
231	if (RT_FAILURE(rc))
232	return rc;
233
234	/*
235	* Register info handlers.
236	*/
237	rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
238	AssertRCReturn(rc, rc);
239
240	rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
241	DBGFINFO_FLAGS_ALL_EMTS);
242	AssertRCReturn(rc, rc);
243
244	rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
245	hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
246	AssertRCReturn(rc, rc);
247
248	rc = DBGFR3InfoRegisterInternalEx(pVM, "lbr", "Dumps the HM LBR info.", hmR3InfoLbr, DBGFINFO_FLAGS_ALL_EMTS);
249	AssertRCReturn(rc, rc);
250
251	/*
252	* Read configuration.
253	*/
254	PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
255
256	/*
257	* Validate the HM settings.
258	*/
259	rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
260	"HMForced" /* implied 'true' these days */
261	"\|UseNEMInstead"
262	"\|FallbackToNEM"
263	"\|EnableNestedPaging"
264	"\|EnableUX"
265	"\|EnableLargePages"
266	"\|EnableVPID"
267	"\|IBPBOnVMExit"
268	"\|IBPBOnVMEntry"
269	"\|SpecCtrlByHost"
270	"\|L1DFlushOnSched"
271	"\|L1DFlushOnVMEntry"
272	"\|MDSClearOnSched"
273	"\|MDSClearOnVMEntry"
274	"\|TPRPatchingEnabled"
275	"\|64bitEnabled"
276	"\|Exclusive"
277	"\|MaxResumeLoops"
278	"\|VmxPleGap"
279	"\|VmxPleWindow"
280	"\|VmxLbr"
281	"\|UseVmxPreemptTimer"
282	"\|SvmPauseFilter"
283	"\|SvmPauseFilterThreshold"
284	"\|SvmVirtVmsaveVmload"
285	"\|SvmVGif"
286	"\|LovelyMesaDrvWorkaround",
287	"" /* pszValidNodes /, "HM" / pszWho /, 0 / uInstance */);
288	if (RT_FAILURE(rc))
289	return rc;
290
291	/** @cfgm{/HM/HMForced, bool, false}
292	* Forces hardware virtualization, no falling back on raw-mode. HM must be
293	* enabled, i.e. /HMEnabled must be true. */
294	bool fHMForced;
295	AssertRelease(pVM->fHMEnabled);
296	fHMForced = true;
297
298	/** @cfgm{/HM/UseNEMInstead, bool, true}
299	* Don't use HM, use NEM instead. */
300	bool fUseNEMInstead = false;
301	rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
302	AssertRCReturn(rc, rc);
303	if (fUseNEMInstead && pVM->fHMEnabled)
304	{
305	LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
306	pVM->fHMEnabled = false;
307	}
308
309	/** @cfgm{/HM/FallbackToNEM, bool, true}
310	* Enables fallback on NEM. */
311	bool fFallbackToNEM = true;
312	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
313	AssertRCReturn(rc, rc);
314
315	/** @cfgm{/HM/EnableNestedPaging, bool, false}
316	* Enables nested paging (aka extended page tables). */
317	bool fAllowNestedPaging = false;
318	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &fAllowNestedPaging, false);
319	AssertRCReturn(rc, rc);
320
321	/** @cfgm{/HM/EnableUX, bool, true}
322	* Enables the VT-x unrestricted execution feature. */
323	bool fAllowUnrestricted = true;
324	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &fAllowUnrestricted, true);
325	AssertRCReturn(rc, rc);
326
327	/** @cfgm{/HM/EnableLargePages, bool, false}
328	* Enables using large pages (2 MB) for guest memory, thus saving on (nested)
329	* page table walking and maybe better TLB hit rate in some cases. */
330	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
331	AssertRCReturn(rc, rc);
332
333	/** @cfgm{/HM/EnableVPID, bool, false}
334	* Enables the VT-x VPID feature. */
335	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
336	AssertRCReturn(rc, rc);
337
338	/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
339	* Enables TPR patching for 32-bit windows guests with IO-APIC. */
340	rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
341	AssertRCReturn(rc, rc);
342
343	/** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
344	* Enables AMD64 cpu features.
345	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
346	* already have the support. */
347	#ifdef VBOX_WITH_64_BITS_GUESTS
348	rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuestsCfg, HC_ARCH_BITS == 64);
349	AssertLogRelRCReturn(rc, rc);
350	#else
351	pVM->hm.s.fAllow64BitGuestsCfg = false;
352	#endif
353
354	/** @cfgm{/HM/VmxPleGap, uint32_t, 0}
355	* The pause-filter exiting gap in TSC ticks. When the number of ticks between
356	* two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
357	* latest PAUSE instruction to be start of a new PAUSE loop.
358	*/
359	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
360	AssertRCReturn(rc, rc);
361
362	/** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
363	* The pause-filter exiting window in TSC ticks. When the number of ticks
364	* between the current PAUSE instruction and first PAUSE of a loop exceeds
365	* VmxPleWindow, a VM-exit is triggered.
366	*
367	* Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
368	*/
369	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
370	AssertRCReturn(rc, rc);
371
372	/** @cfgm{/HM/VmxLbr, bool, false}
373	* Whether to enable LBR for the guest. This is disabled by default as it's only
374	* useful while debugging and enabling it causes a noticeable performance hit. */
375	rc = CFGMR3QueryBoolDef(pCfgHm, "VmxLbr", &pVM->hm.s.vmx.fLbrCfg, false);
376	AssertRCReturn(rc, rc);
377
378	/** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
379	* A counter that is decrement each time a PAUSE instruction is executed by the
380	* guest. When the counter is 0, a \#VMEXIT is triggered.
381	*
382	* Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
383	*/
384	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
385	AssertRCReturn(rc, rc);
386
387	/** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
388	* The pause filter threshold in ticks. When the elapsed time (in ticks) between
389	* two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
390	* PauseFilter count is reset to its initial value. However, if PAUSE is
391	* executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
392	* be triggered.
393	*
394	* Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
395	* activated.
396	*/
397	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
398	AssertRCReturn(rc, rc);
399
400	/** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
401	* Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
402	* available. */
403	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
404	AssertRCReturn(rc, rc);
405
406	/** @cfgm{/HM/SvmVGif, bool, true}
407	* Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
408	* if it's available. */
409	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
410	AssertRCReturn(rc, rc);
411
412	/** @cfgm{/HM/SvmLbrVirt, bool, false}
413	* Whether to make use of the LBR virtualization feature of the CPU if it's
414	* available. This is disabled by default as it's only useful while debugging
415	* and enabling it causes a small hit to performance. */
416	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmLbrVirt", &pVM->hm.s.svm.fLbrVirt, false);
417	AssertRCReturn(rc, rc);
418
419	/** @cfgm{/HM/Exclusive, bool}
420	* Determines the init method for AMD-V and VT-x. If set to true, HM will do a
421	* global init for each host CPU. If false, we do local init each time we wish
422	* to execute guest code.
423	*
424	* On Windows, default is false due to the higher risk of conflicts with other
425	* hypervisors.
426	*
427	* On Mac OS X, this setting is ignored since the code does not handle local
428	* init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
429	*/
430	#if defined(RT_OS_DARWIN)
431	pVM->hm.s.fGlobalInit = true;
432	#else
433	rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
434	# if defined(RT_OS_WINDOWS)
435	false
436	# else
437	true
438	# endif
439	);
440	AssertLogRelRCReturn(rc, rc);
441	#endif
442
443	/** @cfgm{/HM/MaxResumeLoops, uint32_t}
444	* The number of times to resume guest execution before we forcibly return to
445	* ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
446	* determines the default value. */
447	rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoopsCfg, 0 /* set by R0 later */);
448	AssertLogRelRCReturn(rc, rc);
449
450	/** @cfgm{/HM/UseVmxPreemptTimer, bool}
451	* Whether to make use of the VMX-preemption timer feature of the CPU if it's
452	* available. */
453	rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimerCfg, true);
454	AssertLogRelRCReturn(rc, rc);
455
456	/** @cfgm{/HM/IBPBOnVMExit, bool}
457	* Costly paranoia setting. */
458	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
459	AssertLogRelRCReturn(rc, rc);
460
461	/** @cfgm{/HM/IBPBOnVMEntry, bool}
462	* Costly paranoia setting. */
463	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
464	AssertLogRelRCReturn(rc, rc);
465
466	/** @cfgm{/HM/L1DFlushOnSched, bool, true}
467	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
468	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
469	AssertLogRelRCReturn(rc, rc);
470
471	/** @cfgm{/HM/L1DFlushOnVMEntry, bool}
472	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
473	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
474	AssertLogRelRCReturn(rc, rc);
475
476	/* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
477	if (pVM->hm.s.fL1dFlushOnVmEntry)
478	pVM->hm.s.fL1dFlushOnSched = false;
479
480	/** @cfgm{/HM/SpecCtrlByHost, bool}
481	* Another expensive paranoia setting. */
482	rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
483	AssertLogRelRCReturn(rc, rc);
484
485	/** @cfgm{/HM/MDSClearOnSched, bool, true}
486	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
487	* ignored on CPUs that aren't affected. */
488	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
489	AssertLogRelRCReturn(rc, rc);
490
491	/** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
492	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
493	* ignored on CPUs that aren't affected. */
494	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
495	AssertLogRelRCReturn(rc, rc);
496
497	/* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
498	if (pVM->hm.s.fMdsClearOnVmEntry)
499	pVM->hm.s.fMdsClearOnSched = false;
500
501	/** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
502	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
503	* the hypervisor it is running under. */
504	bool f;
505	rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &f, false);
506	AssertLogRelRCReturn(rc, rc);
507	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
508	{
509	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
510	pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv = f;
511	}
512
513	/*
514	* Check if VT-x or AMD-v support according to the users wishes.
515	*/
516	/** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
517	* VERR_SVM_IN_USE. */
518	if (pVM->fHMEnabled)
519	{
520	uint32_t fCaps;
521	rc = SUPR3QueryVTCaps(&fCaps);
522	if (RT_SUCCESS(rc))
523	{
524	if (fCaps & SUPVTCAPS_AMD_V)
525	{
526	pVM->hm.s.svm.fSupported = true;
527	LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
528	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
529	}
530	else if (fCaps & SUPVTCAPS_VT_X)
531	{
532	const char *pszWhy;
533	rc = SUPR3QueryVTxSupported(&pszWhy);
534	if (RT_SUCCESS(rc))
535	{
536	pVM->hm.s.vmx.fSupported = true;
537	LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
538	fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
539	fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
540	(fCaps & (SUPVTCAPS_NESTED_PAGING \| SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
541	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
542	}
543	else
544	{
545	/*
546	* Before failing, try fallback to NEM if we're allowed to do that.
547	*/
548	pVM->fHMEnabled = false;
549	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
550	if (fFallbackToNEM)
551	{
552	LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
553	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
554
555	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
556	if ( RT_SUCCESS(rc2)
557	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
558	rc = VINF_SUCCESS;
559	}
560	if (RT_FAILURE(rc))
561	return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
562	}
563	}
564	else
565	AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
566	VERR_INTERNAL_ERROR_5);
567
568	/*
569	* Disable nested paging and unrestricted guest execution now if they're
570	* configured so that CPUM can make decisions based on our configuration.
571	*/
572	if ( fAllowNestedPaging
573	&& (fCaps & SUPVTCAPS_NESTED_PAGING))
574	{
575	pVM->hm.s.fNestedPagingCfg = true;
576	if (fCaps & SUPVTCAPS_VT_X)
577	{
578	if ( fAllowUnrestricted
579	&& (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST))
580	pVM->hm.s.vmx.fUnrestrictedGuestCfg = true;
581	else
582	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
583	}
584	}
585	else
586	Assert(!pVM->hm.s.fNestedPagingCfg);
587	}
588	else
589	{
590	const char *pszMsg;
591	switch (rc)
592	{
593	case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
594	case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
595	case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
596	case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
597	case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
598	case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
599	case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
600	default:
601	return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
602	}
603
604	/*
605	* Before failing, try fallback to NEM if we're allowed to do that.
606	*/
607	pVM->fHMEnabled = false;
608	if (fFallbackToNEM)
609	{
610	LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
611	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
612	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
613	if ( RT_SUCCESS(rc2)
614	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
615	rc = VINF_SUCCESS;
616	}
617	if (RT_FAILURE(rc))
618	return VM_SET_ERROR(pVM, rc, pszMsg);
619	}
620	}
621	else
622	{
623	/*
624	* Disabled HM mean raw-mode, unless NEM is supposed to be used.
625	*/
626	if (fUseNEMInstead)
627	{
628	rc = NEMR3Init(pVM, false /fFallback/, true);
629	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
630	if (RT_FAILURE(rc))
631	return rc;
632	}
633	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET
634	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE
635	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT /* paranoia */)
636	return VM_SET_ERROR(pVM, rc, "Misconfigured VM: No guest execution engine available!");
637	}
638
639	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
640	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE);
641	return VINF_SUCCESS;
642	}
643
644
645	/**
646	* Initializes HM components after ring-3 phase has been fully initialized.
647	*
648	* @returns VBox status code.
649	* @param pVM The cross context VM structure.
650	*/
651	static int hmR3InitFinalizeR3(PVM pVM)
652	{
653	LogFlowFunc(("\n"));
654
655	if (!HMIsEnabled(pVM))
656	return VINF_SUCCESS;
657
658	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
659	{
660	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
661	pVCpu->hm.s.fActive = false;
662	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
663	}
664
665	/*
666	* Check if L1D flush is needed/possible.
667	*/
668	if ( !pVM->cpum.ro.HostFeatures.fFlushCmd
669	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
670	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
671	\|\| pVM->cpum.ro.HostFeatures.fArchVmmNeedNotFlushL1d
672	\|\| pVM->cpum.ro.HostFeatures.fArchRdclNo)
673	pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
674
675	/*
676	* Check if MDS flush is needed/possible.
677	* On atoms and knight family CPUs, we will only allow clearing on scheduling.
678	*/
679	if ( !pVM->cpum.ro.HostFeatures.fMdsClear
680	\|\| pVM->cpum.ro.HostFeatures.fArchMdsNo)
681	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
682	else if ( ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
683	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Atom_End)
684	\|\| ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Phi_KnightsLanding
685	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Phi_End))
686	{
687	if (!pVM->hm.s.fMdsClearOnSched)
688	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
689	pVM->hm.s.fMdsClearOnVmEntry = false;
690	}
691	else if ( pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
692	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
693	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
694
695	/*
696	* Statistics.
697	*/
698	#ifdef VBOX_WITH_STATISTICS
699	STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
700	STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
701	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8", STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
702	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC", STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
703	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
704	#endif
705
706	bool const fCpuSupportsVmx = ASMIsIntelCpu() \|\| ASMIsViaCentaurCpu() \|\| ASMIsShanghaiCpu();
707	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
708	{
709	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
710	PHMCPU pHmCpu = &pVCpu->hm.s;
711	int rc;
712
713	# define HM_REG_STAT(a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szNmFmt, a_szDesc) do { \
714	rc = STAMR3RegisterF(pVM, a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szDesc, a_szNmFmt, idCpu); \
715	AssertRC(rc); \
716	} while (0)
717	# define HM_REG_PROFILE(a_pVar, a_szNmFmt, a_szDesc) \
718	HM_REG_STAT(a_pVar, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, a_szNmFmt, a_szDesc)
719
720	#ifdef VBOX_WITH_STATISTICS
721
722	HM_REG_PROFILE(&pHmCpu->StatPoke, "/PROF/CPU%u/HM/Poke", "Profiling of RTMpPokeCpu.");
723	HM_REG_PROFILE(&pHmCpu->StatSpinPoke, "/PROF/CPU%u/HM/PokeWait", "Profiling of poke wait.");
724	HM_REG_PROFILE(&pHmCpu->StatSpinPokeFailed, "/PROF/CPU%u/HM/PokeWaitFailed", "Profiling of poke wait when RTMpPokeCpu fails.");
725	HM_REG_PROFILE(&pHmCpu->StatEntry, "/PROF/CPU%u/HM/Entry", "Profiling of entry until entering GC.");
726	HM_REG_PROFILE(&pHmCpu->StatPreExit, "/PROF/CPU%u/HM/SwitchFromGC_1", "Profiling of pre-exit processing after returning from GC.");
727	HM_REG_PROFILE(&pHmCpu->StatExitHandling, "/PROF/CPU%u/HM/SwitchFromGC_2", "Profiling of exit handling (longjmps not included!)");
728	HM_REG_PROFILE(&pHmCpu->StatExitIO, "/PROF/CPU%u/HM/SwitchFromGC_2/IO", "I/O.");
729	HM_REG_PROFILE(&pHmCpu->StatExitMovCRx, "/PROF/CPU%u/HM/SwitchFromGC_2/MovCRx", "MOV CRx.");
730	HM_REG_PROFILE(&pHmCpu->StatExitXcptNmi, "/PROF/CPU%u/HM/SwitchFromGC_2/XcptNmi", "Exceptions, NMIs.");
731	HM_REG_PROFILE(&pHmCpu->StatExitVmentry, "/PROF/CPU%u/HM/SwitchFromGC_2/Vmentry", "VMLAUNCH/VMRESUME on Intel or VMRUN on AMD.");
732	HM_REG_PROFILE(&pHmCpu->StatImportGuestState, "/PROF/CPU%u/HM/ImportGuestState", "Profiling of importing guest state from hardware after VM-exit.");
733	HM_REG_PROFILE(&pHmCpu->StatExportGuestState, "/PROF/CPU%u/HM/ExportGuestState", "Profiling of exporting guest state to hardware before VM-entry.");
734	HM_REG_PROFILE(&pHmCpu->StatLoadGuestFpuState, "/PROF/CPU%u/HM/LoadGuestFpuState", "Profiling of CPUMR0LoadGuestFPU.");
735	HM_REG_PROFILE(&pHmCpu->StatInGC, "/PROF/CPU%u/HM/InGC", "Profiling of execution of guest-code in hardware.");
736	# ifdef HM_PROFILE_EXIT_DISPATCH
737	HM_REG_STAT(&pHmCpu->StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
738	"/PROF/CPU%u/HM/ExitDispatch", "Profiling the dispatching of exit handlers.");
739	# endif
740	#endif
741	# define HM_REG_COUNTER(a, b, desc) HM_REG_STAT(a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, b, desc)
742
743	#ifdef VBOX_WITH_STATISTICS
744	HM_REG_COUNTER(&pHmCpu->StatExitAll, "/HM/CPU%u/Exit/All", "Total exits (including nested-guest exits).");
745	HM_REG_COUNTER(&pHmCpu->StatNestedExitAll, "/HM/CPU%u/Exit/NestedGuest/All", "Total nested-guest exits.");
746	HM_REG_COUNTER(&pHmCpu->StatExitShadowNM, "/HM/CPU%u/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
747	HM_REG_COUNTER(&pHmCpu->StatExitGuestNM, "/HM/CPU%u/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
748	HM_REG_COUNTER(&pHmCpu->StatExitShadowPF, "/HM/CPU%u/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
749	HM_REG_COUNTER(&pHmCpu->StatExitShadowPFEM, "/HM/CPU%u/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
750	HM_REG_COUNTER(&pHmCpu->StatExitGuestPF, "/HM/CPU%u/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
751	HM_REG_COUNTER(&pHmCpu->StatExitGuestUD, "/HM/CPU%u/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
752	HM_REG_COUNTER(&pHmCpu->StatExitGuestSS, "/HM/CPU%u/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
753	HM_REG_COUNTER(&pHmCpu->StatExitGuestNP, "/HM/CPU%u/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
754	HM_REG_COUNTER(&pHmCpu->StatExitGuestTS, "/HM/CPU%u/Exit/Trap/Gst/#TS", "Guest #TS (task switch) exception.");
755	HM_REG_COUNTER(&pHmCpu->StatExitGuestOF, "/HM/CPU%u/Exit/Trap/Gst/#OF", "Guest #OF (overflow) exception.");
756	HM_REG_COUNTER(&pHmCpu->StatExitGuestGP, "/HM/CPU%u/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
757	HM_REG_COUNTER(&pHmCpu->StatExitGuestDE, "/HM/CPU%u/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
758	HM_REG_COUNTER(&pHmCpu->StatExitGuestDF, "/HM/CPU%u/Exit/Trap/Gst/#DF", "Guest #DF (double fault) exception.");
759	HM_REG_COUNTER(&pHmCpu->StatExitGuestBR, "/HM/CPU%u/Exit/Trap/Gst/#BR", "Guest #BR (boundary range exceeded) exception.");
760	#endif
761	HM_REG_COUNTER(&pHmCpu->StatExitGuestAC, "/HM/CPU%u/Exit/Trap/Gst/#AC", "Guest #AC (alignment check) exception.");
762	if (fCpuSupportsVmx)
763	HM_REG_COUNTER(&pHmCpu->StatExitGuestACSplitLock, "/HM/CPU%u/Exit/Trap/Gst/#AC-split-lock", "Guest triggered #AC due to split-lock being enabled on the host (interpreted).");
764	#ifdef VBOX_WITH_STATISTICS
765	HM_REG_COUNTER(&pHmCpu->StatExitGuestDB, "/HM/CPU%u/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
766	HM_REG_COUNTER(&pHmCpu->StatExitGuestMF, "/HM/CPU%u/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
767	HM_REG_COUNTER(&pHmCpu->StatExitGuestBP, "/HM/CPU%u/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
768	HM_REG_COUNTER(&pHmCpu->StatExitGuestXF, "/HM/CPU%u/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
769	HM_REG_COUNTER(&pHmCpu->StatExitGuestXcpUnk, "/HM/CPU%u/Exit/Trap/Gst/Other", "Other guest exceptions.");
770	HM_REG_COUNTER(&pHmCpu->StatExitRdmsr, "/HM/CPU%u/Exit/Instr/Rdmsr", "MSR read.");
771	HM_REG_COUNTER(&pHmCpu->StatExitWrmsr, "/HM/CPU%u/Exit/Instr/Wrmsr", "MSR write.");
772	HM_REG_COUNTER(&pHmCpu->StatExitDRxWrite, "/HM/CPU%u/Exit/Instr/DR-Write", "Debug register write.");
773	HM_REG_COUNTER(&pHmCpu->StatExitDRxRead, "/HM/CPU%u/Exit/Instr/DR-Read", "Debug register read.");
774	HM_REG_COUNTER(&pHmCpu->StatExitCR0Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR0", "CR0 read.");
775	HM_REG_COUNTER(&pHmCpu->StatExitCR2Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR2", "CR2 read.");
776	HM_REG_COUNTER(&pHmCpu->StatExitCR3Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR3", "CR3 read.");
777	HM_REG_COUNTER(&pHmCpu->StatExitCR4Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR4", "CR4 read.");
778	HM_REG_COUNTER(&pHmCpu->StatExitCR8Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR8", "CR8 read.");
779	HM_REG_COUNTER(&pHmCpu->StatExitCR0Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR0", "CR0 write.");
780	HM_REG_COUNTER(&pHmCpu->StatExitCR2Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR2", "CR2 write.");
781	HM_REG_COUNTER(&pHmCpu->StatExitCR3Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR3", "CR3 write.");
782	HM_REG_COUNTER(&pHmCpu->StatExitCR4Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR4", "CR4 write.");
783	HM_REG_COUNTER(&pHmCpu->StatExitCR8Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR8", "CR8 write.");
784	HM_REG_COUNTER(&pHmCpu->StatExitClts, "/HM/CPU%u/Exit/Instr/CLTS", "CLTS instruction.");
785	HM_REG_COUNTER(&pHmCpu->StatExitLmsw, "/HM/CPU%u/Exit/Instr/LMSW", "LMSW instruction.");
786	HM_REG_COUNTER(&pHmCpu->StatExitXdtrAccess, "/HM/CPU%u/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
787	HM_REG_COUNTER(&pHmCpu->StatExitIOWrite, "/HM/CPU%u/Exit/Instr/IO/Write", "I/O write.");
788	HM_REG_COUNTER(&pHmCpu->StatExitIORead, "/HM/CPU%u/Exit/Instr/IO/Read", "I/O read.");
789	HM_REG_COUNTER(&pHmCpu->StatExitIOStringWrite, "/HM/CPU%u/Exit/Instr/IO/WriteString", "String I/O write.");
790	HM_REG_COUNTER(&pHmCpu->StatExitIOStringRead, "/HM/CPU%u/Exit/Instr/IO/ReadString", "String I/O read.");
791	HM_REG_COUNTER(&pHmCpu->StatExitIntWindow, "/HM/CPU%u/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts.");
792	HM_REG_COUNTER(&pHmCpu->StatExitExtInt, "/HM/CPU%u/Exit/ExtInt", "Physical maskable interrupt (host).");
793	#endif
794	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGC, "/HM/CPU%u/Exit/HostNmiInGC", "Host NMI received while in guest context.");
795	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGCIpi, "/HM/CPU%u/Exit/HostNmiInGCIpi", "Host NMI received while in guest context dispatched using IPIs.");
796	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/Exit/PreemptTimer", "VMX-preemption timer expired.");
797	#ifdef VBOX_WITH_STATISTICS
798	HM_REG_COUNTER(&pHmCpu->StatExitTprBelowThreshold, "/HM/CPU%u/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
799	HM_REG_COUNTER(&pHmCpu->StatExitTaskSwitch, "/HM/CPU%u/Exit/TaskSwitch", "Task switch caused through task gate in IDT.");
800	HM_REG_COUNTER(&pHmCpu->StatExitApicAccess, "/HM/CPU%u/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
801
802	HM_REG_COUNTER(&pHmCpu->StatSwitchTprMaskedIrq, "/HM/CPU%u/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
803	HM_REG_COUNTER(&pHmCpu->StatSwitchGuestIrq, "/HM/CPU%u/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
804	HM_REG_COUNTER(&pHmCpu->StatSwitchPendingHostIrq, "/HM/CPU%u/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
805	HM_REG_COUNTER(&pHmCpu->StatSwitchHmToR3FF, "/HM/CPU%u/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
806	HM_REG_COUNTER(&pHmCpu->StatSwitchVmReq, "/HM/CPU%u/Switch/VmReq", "Exit to ring-3 due to pending VM requests.");
807	HM_REG_COUNTER(&pHmCpu->StatSwitchPgmPoolFlush, "/HM/CPU%u/Switch/PgmPoolFlush", "Exit to ring-3 due to pending PGM pool flush.");
808	HM_REG_COUNTER(&pHmCpu->StatSwitchDma, "/HM/CPU%u/Switch/PendingDma", "Exit to ring-3 due to pending DMA requests.");
809	HM_REG_COUNTER(&pHmCpu->StatSwitchExitToR3, "/HM/CPU%u/Switch/ExitToR3", "Exit to ring-3 (total).");
810	HM_REG_COUNTER(&pHmCpu->StatSwitchLongJmpToR3, "/HM/CPU%u/Switch/LongJmpToR3", "Longjump to ring-3.");
811	HM_REG_COUNTER(&pHmCpu->StatSwitchMaxResumeLoops, "/HM/CPU%u/Switch/MaxResumeLoops", "Maximum VMRESUME inner-loop counter reached.");
812	HM_REG_COUNTER(&pHmCpu->StatSwitchHltToR3, "/HM/CPU%u/Switch/HltToR3", "HLT causing us to go to ring-3.");
813	HM_REG_COUNTER(&pHmCpu->StatSwitchApicAccessToR3, "/HM/CPU%u/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
814	#endif
815	HM_REG_COUNTER(&pHmCpu->StatSwitchPreempt, "/HM/CPU%u/Switch/Preempting", "EMT has been preempted while in HM context.");
816	#ifdef VBOX_WITH_STATISTICS
817	HM_REG_COUNTER(&pHmCpu->StatSwitchNstGstVmexit, "/HM/CPU%u/Switch/NstGstVmexit", "Nested-guest VM-exit occurred.");
818
819	HM_REG_COUNTER(&pHmCpu->StatInjectInterrupt, "/HM/CPU%u/EventInject/Interrupt", "Injected an external interrupt into the guest.");
820	HM_REG_COUNTER(&pHmCpu->StatInjectXcpt, "/HM/CPU%u/EventInject/Trap", "Injected an exception into the guest.");
821	HM_REG_COUNTER(&pHmCpu->StatInjectReflect, "/HM/CPU%u/EventInject/Reflect", "Reflecting an exception caused due to event injection.");
822	HM_REG_COUNTER(&pHmCpu->StatInjectConvertDF, "/HM/CPU%u/EventInject/ReflectDF", "Injected a converted #DF caused due to event injection.");
823	HM_REG_COUNTER(&pHmCpu->StatInjectInterpret, "/HM/CPU%u/EventInject/Interpret", "Falling back to interpreter for handling exception caused due to event injection.");
824	HM_REG_COUNTER(&pHmCpu->StatInjectReflectNPF, "/HM/CPU%u/EventInject/ReflectNPF", "Reflecting event that caused an EPT violation / nested #PF.");
825
826	HM_REG_COUNTER(&pHmCpu->StatFlushPage, "/HM/CPU%u/Flush/Page", "Invalidating a guest page on all guest CPUs.");
827	HM_REG_COUNTER(&pHmCpu->StatFlushPageManual, "/HM/CPU%u/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
828	HM_REG_COUNTER(&pHmCpu->StatFlushPhysPageManual, "/HM/CPU%u/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
829	HM_REG_COUNTER(&pHmCpu->StatFlushTlb, "/HM/CPU%u/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
830	HM_REG_COUNTER(&pHmCpu->StatFlushTlbManual, "/HM/CPU%u/Flush/TLB/Manual", "Request a full guest-TLB flush.");
831	HM_REG_COUNTER(&pHmCpu->StatFlushTlbNstGst, "/HM/CPU%u/Flush/TLB/NestedGuest", "Request a nested-guest-TLB flush.");
832	HM_REG_COUNTER(&pHmCpu->StatFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
833	HM_REG_COUNTER(&pHmCpu->StatNoFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/Skipped", "No TLB flushing required.");
834	HM_REG_COUNTER(&pHmCpu->StatFlushEntire, "/HM/CPU%u/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
835	HM_REG_COUNTER(&pHmCpu->StatFlushAsid, "/HM/CPU%u/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
836	HM_REG_COUNTER(&pHmCpu->StatFlushNestedPaging, "/HM/CPU%u/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
837	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgVirt, "/HM/CPU%u/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
838	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgPhys, "/HM/CPU%u/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
839	HM_REG_COUNTER(&pHmCpu->StatTlbShootdown, "/HM/CPU%u/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
840	HM_REG_COUNTER(&pHmCpu->StatTlbShootdownFlush, "/HM/CPU%u/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
841
842	HM_REG_COUNTER(&pHmCpu->StatTscParavirt, "/HM/CPU%u/TSC/Paravirt", "Paravirtualized TSC in effect.");
843	HM_REG_COUNTER(&pHmCpu->StatTscOffset, "/HM/CPU%u/TSC/Offset", "TSC offsetting is in effect.");
844	HM_REG_COUNTER(&pHmCpu->StatTscIntercept, "/HM/CPU%u/TSC/Intercept", "Intercept TSC accesses.");
845
846	HM_REG_COUNTER(&pHmCpu->StatDRxArmed, "/HM/CPU%u/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
847	HM_REG_COUNTER(&pHmCpu->StatDRxContextSwitch, "/HM/CPU%u/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
848	HM_REG_COUNTER(&pHmCpu->StatDRxIoCheck, "/HM/CPU%u/Debug/IOCheck", "Checking for I/O breakpoint.");
849
850	HM_REG_COUNTER(&pHmCpu->StatExportMinimal, "/HM/CPU%u/Export/Minimal", "VM-entry exporting minimal guest-state.");
851	HM_REG_COUNTER(&pHmCpu->StatExportFull, "/HM/CPU%u/Export/Full", "VM-entry exporting the full guest-state.");
852	HM_REG_COUNTER(&pHmCpu->StatLoadGuestFpu, "/HM/CPU%u/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
853	HM_REG_COUNTER(&pHmCpu->StatExportHostState, "/HM/CPU%u/Export/HostState", "VM-entry exporting host-state.");
854
855	if (fCpuSupportsVmx)
856	{
857	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRip, "/HM/CPU%u/WriteHostRIP", "Number of VMX_VMCS_HOST_RIP instructions.");
858	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRsp, "/HM/CPU%u/WriteHostRSP", "Number of VMX_VMCS_HOST_RSP instructions.");
859	HM_REG_COUNTER(&pHmCpu->StatVmxVmLaunch, "/HM/CPU%u/VMLaunch", "Number of VM-entries using VMLAUNCH.");
860	HM_REG_COUNTER(&pHmCpu->StatVmxVmResume, "/HM/CPU%u/VMResume", "Number of VM-entries using VMRESUME.");
861	}
862
863	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelBase, "/HM/CPU%u/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
864	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelLimit, "/HM/CPU%u/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
865	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelAttr, "/HM/CPU%u/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector attributes.");
866
867	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelBase, "/HM/CPU%u/VMXCheck/V86SelBase", "Could not use VMX due to unsuitable v8086-mode selector base.");
868	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelLimit, "/HM/CPU%u/VMXCheck/V86SelLimit", "Could not use VMX due to unsuitable v8086-mode selector limit.");
869	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelAttr, "/HM/CPU%u/VMXCheck/V86SelAttrs", "Could not use VMX due to unsuitable v8086-mode selector attributes.");
870
871	HM_REG_COUNTER(&pHmCpu->StatVmxCheckRmOk, "/HM/CPU%u/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
872	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadSel, "/HM/CPU%u/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
873	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRpl, "/HM/CPU%u/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
874	HM_REG_COUNTER(&pHmCpu->StatVmxCheckPmOk, "/HM/CPU%u/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
875	#endif
876	if (fCpuSupportsVmx)
877	{
878	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/PreemptTimer", "VMX-preemption timer fired.");
879	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadline, "/HM/CPU%u/PreemptTimer/ReusingDeadline", "VMX-preemption timer arming logic using previously calculated deadline");
880	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadlineExpired, "/HM/CPU%u/PreemptTimer/ReusingDeadlineExpired", "VMX-preemption timer arming logic found previous deadline already expired (ignored)");
881	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadline, "/HM/CPU%u/PreemptTimer/RecalcingDeadline", "VMX-preemption timer arming logic recalculating the deadline (slightly expensive)");
882	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadlineExpired, "/HM/CPU%u/PreemptTimer/RecalcingDeadlineExpired", "VMX-preemption timer arming logic found recalculated deadline expired (ignored)");
883	}
884	#ifdef VBOX_WITH_STATISTICS
885	/*
886	* Guest Exit reason stats.
887	*/
888	pHmCpu->paStatExitReason = NULL;
889	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(pHmCpu->paStatExitReason), 0 / uAlignment */, MM_TAG_HM,
890	(void **)&pHmCpu->paStatExitReason);
891	AssertRCReturn(rc, rc);
892
893	if (fCpuSupportsVmx)
894	{
895	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
896	{
897	const char *pszExitName = HMGetVmxExitName(j);
898	if (pszExitName)
899	{
900	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
901	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
902	AssertRCReturn(rc, rc);
903	}
904	}
905	}
906	else
907	{
908	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
909	{
910	const char *pszExitName = HMGetSvmExitName(j);
911	if (pszExitName)
912	{
913	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
914	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
915	AssertRC(rc);
916	}
917	}
918	}
919	HM_REG_COUNTER(&pHmCpu->StatExitReasonNpf, "/HM/CPU%u/Exit/Reason/#NPF", "Nested page faults");
920
921	pHmCpu->paStatExitReasonR0 = MMHyperR3ToR0(pVM, pHmCpu->paStatExitReason);
922	Assert(pHmCpu->paStatExitReasonR0 != NIL_RTR0PTR);
923
924	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
925	/*
926	* Nested-guest VM-exit reason stats.
927	*/
928	pHmCpu->paStatNestedExitReason = NULL;
929	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(pHmCpu->paStatNestedExitReason), 0 / uAlignment */, MM_TAG_HM,
930	(void **)&pHmCpu->paStatNestedExitReason);
931	AssertRCReturn(rc, rc);
932	if (fCpuSupportsVmx)
933	{
934	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
935	{
936	const char *pszExitName = HMGetVmxExitName(j);
937	if (pszExitName)
938	{
939	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
940	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
941	AssertRC(rc);
942	}
943	}
944	}
945	else
946	{
947	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
948	{
949	const char *pszExitName = HMGetSvmExitName(j);
950	if (pszExitName)
951	{
952	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
953	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
954	AssertRC(rc);
955	}
956	}
957	}
958	HM_REG_COUNTER(&pHmCpu->StatNestedExitReasonNpf, "/HM/CPU%u/Exit/NestedGuest/Reason/#NPF", "Nested page faults");
959	pHmCpu->paStatNestedExitReasonR0 = MMHyperR3ToR0(pVM, pHmCpu->paStatNestedExitReason);
960	Assert(pHmCpu->paStatNestedExitReasonR0 != NIL_RTR0PTR);
961	#endif
962
963	/*
964	* Injected interrupts stats.
965	*/
966	{
967	uint32_t const cInterrupts = 0xff + 1;
968	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * cInterrupts, 8, MM_TAG_HM, (void **)&pHmCpu->paStatInjectedIrqs);
969	AssertRCReturn(rc, rc);
970	pHmCpu->paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pHmCpu->paStatInjectedIrqs);
971	Assert(pHmCpu->paStatInjectedIrqsR0 != NIL_RTR0PTR);
972	for (unsigned j = 0; j < cInterrupts; j++)
973	{
974	char aszIntrName[64];
975	RTStrPrintf(&aszIntrName[0], sizeof(aszIntrName), "Interrupt %u", j);
976	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
977	STAMUNIT_OCCURENCES, aszIntrName,
978	"/HM/CPU%u/EventInject/InjectIntr/%02X", idCpu, j);
979	AssertRC(rc);
980	}
981	}
982
983	/*
984	* Injected exception stats.
985	*/
986	{
987	uint32_t const cXcpts = X86_XCPT_LAST + 1;
988	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * cXcpts, 8, MM_TAG_HM, (void **)&pHmCpu->paStatInjectedXcpts);
989	AssertRCReturn(rc, rc);
990	pHmCpu->paStatInjectedXcptsR0 = MMHyperR3ToR0(pVM, pHmCpu->paStatInjectedXcpts);
991	Assert(pHmCpu->paStatInjectedXcptsR0 != NIL_RTR0PTR);
992	for (unsigned j = 0; j < cXcpts; j++)
993	{
994	char aszXcptName[64];
995	RTStrPrintf(&aszXcptName[0], sizeof(aszXcptName), "%s exception", hmR3GetXcptName(j));
996	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatInjectedXcpts[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
997	STAMUNIT_OCCURENCES, aszXcptName,
998	"/HM/CPU%u/EventInject/InjectXcpt/%02X", idCpu, j);
999	AssertRC(rc);
1000	}
1001	}
1002
1003	#endif /* VBOX_WITH_STATISTICS */
1004	#undef HM_REG_COUNTER
1005	#undef HM_REG_PROFILE
1006	#undef HM_REG_STAT
1007	}
1008
1009	return VINF_SUCCESS;
1010	}
1011
1012
1013	/**
1014	* Called when a init phase has completed.
1015	*
1016	* @returns VBox status code.
1017	* @param pVM The cross context VM structure.
1018	* @param enmWhat The phase that completed.
1019	*/
1020	VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1021	{
1022	switch (enmWhat)
1023	{
1024	case VMINITCOMPLETED_RING3:
1025	return hmR3InitFinalizeR3(pVM);
1026	case VMINITCOMPLETED_RING0:
1027	return hmR3InitFinalizeR0(pVM);
1028	default:
1029	return VINF_SUCCESS;
1030	}
1031	}
1032
1033
1034	/**
1035	* Turns off normal raw mode features.
1036	*
1037	* @param pVM The cross context VM structure.
1038	*/
1039	static void hmR3DisableRawMode(PVM pVM)
1040	{
1041	/** @todo r=bird: HM shouldn't be doing this crap. */
1042	/* Reinit the paging mode to force the new shadow mode. */
1043	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1044	{
1045	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1046	PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1047	}
1048	}
1049
1050
1051	/**
1052	* Initialize VT-x or AMD-V.
1053	*
1054	* @returns VBox status code.
1055	* @param pVM The cross context VM structure.
1056	*/
1057	static int hmR3InitFinalizeR0(PVM pVM)
1058	{
1059	int rc;
1060
1061	if (!HMIsEnabled(pVM))
1062	return VINF_SUCCESS;
1063
1064	/*
1065	* Hack to allow users to work around broken BIOSes that incorrectly set
1066	* EFER.SVME, which makes us believe somebody else is already using AMD-V.
1067	*/
1068	if ( !pVM->hm.s.vmx.fSupported
1069	&& !pVM->hm.s.svm.fSupported
1070	&& pVM->hm.s.ForR3.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1071	&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1072	{
1073	LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1074	pVM->hm.s.svm.fSupported = true;
1075	pVM->hm.s.svm.fIgnoreInUseError = true;
1076	pVM->hm.s.ForR3.rcInit = VINF_SUCCESS;
1077	}
1078
1079	/*
1080	* Report ring-0 init errors.
1081	*/
1082	if ( !pVM->hm.s.vmx.fSupported
1083	&& !pVM->hm.s.svm.fSupported)
1084	{
1085	LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.ForR3.rcInit));
1086	LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.ForR3.vmx.Msrs.u64FeatCtrl));
1087	switch (pVM->hm.s.ForR3.rcInit)
1088	{
1089	case VERR_VMX_IN_VMX_ROOT_MODE:
1090	return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1091	case VERR_VMX_NO_VMX:
1092	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1093	case VERR_VMX_MSR_VMX_DISABLED:
1094	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1095	case VERR_VMX_MSR_ALL_VMX_DISABLED:
1096	return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1097	case VERR_VMX_MSR_LOCKING_FAILED:
1098	return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1099	case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1100	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1101	case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1102	return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1103
1104	case VERR_SVM_IN_USE:
1105	return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1106	case VERR_SVM_NO_SVM:
1107	return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1108	case VERR_SVM_DISABLED:
1109	return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1110	}
1111	return VMSetError(pVM, pVM->hm.s.ForR3.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.ForR3.rcInit);
1112	}
1113
1114	/*
1115	* Enable VT-x or AMD-V on all host CPUs.
1116	*/
1117	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_ENABLE, 0, NULL);
1118	if (RT_FAILURE(rc))
1119	{
1120	LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1121	HMR3CheckError(pVM, rc);
1122	return rc;
1123	}
1124
1125	/*
1126	* No TPR patching is required when the IO-APIC is not enabled for this VM.
1127	* (Main should have taken care of this already)
1128	*/
1129	if (!PDMHasIoApic(pVM))
1130	{
1131	Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1132	pVM->hm.s.fTprPatchingAllowed = false;
1133	}
1134
1135	LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
1136	pVM->hm.s.ForR3.fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
1137	pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
1138
1139	/*
1140	* Do the vendor specific initialization
1141	*
1142	* Note! We disable release log buffering here since we're doing relatively
1143	* lot of logging and doesn't want to hit the disk with each LogRel
1144	* statement.
1145	*/
1146	AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1147	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
1148	if (pVM->hm.s.vmx.fSupported)
1149	rc = hmR3InitFinalizeR0Intel(pVM);
1150	else
1151	rc = hmR3InitFinalizeR0Amd(pVM);
1152	LogRel((pVM->hm.s.fGlobalInit ? "HM: VT-x/AMD-V init method: Global\n"
1153	: "HM: VT-x/AMD-V init method: Local\n"));
1154	RTLogRelSetBuffering(fOldBuffered);
1155	pVM->hm.s.fInitialized = true;
1156
1157	return rc;
1158	}
1159
1160
1161	/**
1162	* @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1163	*/
1164	static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1165	{
1166	NOREF(pVM);
1167	NOREF(pvAllocation);
1168	NOREF(GCPhysAllocation);
1169	}
1170
1171
1172	/**
1173	* Returns a description of the VMCS (and associated regions') memory type given the
1174	* IA32_VMX_BASIC MSR.
1175	*
1176	* @returns The descriptive memory type.
1177	* @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1178	*/
1179	static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1180	{
1181	uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1182	switch (uMemType)
1183	{
1184	case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1185	case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1186	}
1187	return "Unknown";
1188	}
1189
1190
1191	/**
1192	* Returns a single-line description of all the activity-states supported by the CPU
1193	* given the IA32_VMX_MISC MSR.
1194	*
1195	* @returns All supported activity states.
1196	* @param uMsrMisc IA32_VMX_MISC MSR value.
1197	*/
1198	static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1199	{
1200	static const char * const s_apszActStates[] =
1201	{
1202	"",
1203	" ( HLT )",
1204	" ( SHUTDOWN )",
1205	" ( HLT SHUTDOWN )",
1206	" ( SIPI_WAIT )",
1207	" ( HLT SIPI_WAIT )",
1208	" ( SHUTDOWN SIPI_WAIT )",
1209	" ( HLT SHUTDOWN SIPI_WAIT )"
1210	};
1211	uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1212	Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1213	return s_apszActStates[idxActStates];
1214	}
1215
1216
1217	/**
1218	* Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1219	*
1220	* @param fFeatMsr The feature control MSR value.
1221	*/
1222	static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1223	{
1224	uint64_t const val = fFeatMsr;
1225	LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1226	HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1227	HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1228	HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1229	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1230	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1231	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1232	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1233	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1234	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1235	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1236	HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1237	HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1238	HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1239	HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1240	if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1241	LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1242	}
1243
1244
1245	/**
1246	* Reports MSR_IA32_VMX_BASIC MSR to the log.
1247	*
1248	* @param uBasicMsr The VMX basic MSR value.
1249	*/
1250	static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1251	{
1252	LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1253	LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1254	LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1255	LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1256	"< 4 GB" : "None"));
1257	LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1258	LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1259	LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1260	LogRel(("HM: Supports true-capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1261	LogRel(("HM: VM-entry Xcpt error-code optional = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_XCPT_ERRCODE)));
1262	}
1263
1264
1265	/**
1266	* Reports MSR_IA32_PINBASED_CTLS to the log.
1267	*
1268	* @param pVmxMsr Pointer to the VMX MSR.
1269	*/
1270	static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1271	{
1272	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1273	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1274	LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1275	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1276	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1277	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1278	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1279	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1280	}
1281
1282
1283	/**
1284	* Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1285	*
1286	* @param pVmxMsr Pointer to the VMX MSR.
1287	*/
1288	static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1289	{
1290	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1291	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1292	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1293	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1294	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1295	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1296	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1297	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1298	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1299	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1300	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1301	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1302	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1303	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1304	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1305	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1306	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1307	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1308	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1309	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1310	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1311	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1312	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1313	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1314	}
1315
1316
1317	/**
1318	* Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1319	*
1320	* @param pVmxMsr Pointer to the VMX MSR.
1321	*/
1322	static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1323	{
1324	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1325	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1326	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1327	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1328	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1329	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1330	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1331	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1332	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1333	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1334	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1335	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1336	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1337	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1338	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1339	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1340	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1341	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1342	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1343	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1344	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1345	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_VE", VMX_PROC_CTLS2_EPT_VE);
1346	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1347	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1348	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MODE_BASED_EPT_PERM", VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1349	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SPPTP_EPT", VMX_PROC_CTLS2_SPPTP_EPT);
1350	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PT_EPT", VMX_PROC_CTLS2_PT_EPT);
1351	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1352	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USER_WAIT_PAUSE", VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1353	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLV_EXIT", VMX_PROC_CTLS2_ENCLV_EXIT);
1354	}
1355
1356
1357	/**
1358	* Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1359	*
1360	* @param pVmxMsr Pointer to the VMX MSR.
1361	*/
1362	static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1363	{
1364	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1365	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1366	LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1367	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1368	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1369	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1370	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1371	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1372	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1373	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1374	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_BNDCFGS_MSR", VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR);
1375	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
1376	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_RTIT_CTL_MSR", VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR);
1377	}
1378
1379
1380	/**
1381	* Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1382	*
1383	* @param pVmxMsr Pointer to the VMX MSR.
1384	*/
1385	static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1386	{
1387	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1388	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1389	LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1390	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1391	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1392	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1393	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1394	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1395	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1396	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1397	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1398	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1399	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_BNDCFGS_MSR", VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR);
1400	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT);
1401	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_RTIT_CTL_MSR", VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR);
1402	}
1403
1404
1405	/**
1406	* Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1407	*
1408	* @param fCaps The VMX EPT/VPID capability MSR value.
1409	*/
1410	static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1411	{
1412	LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1413	HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1414	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1415	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_5", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5);
1416	HMVMX_REPORT_MSR_CAP(fCaps, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1417	HMVMX_REPORT_MSR_CAP(fCaps, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1418	HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1419	HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1420	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1421	HMVMX_REPORT_MSR_CAP(fCaps, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1422	HMVMX_REPORT_MSR_CAP(fCaps, "ADVEXITINFO_EPT", MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT);
1423	HMVMX_REPORT_MSR_CAP(fCaps, "SSS", MSR_IA32_VMX_EPT_VPID_CAP_SSS);
1424	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1425	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1426	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1427	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1428	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1429	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1430	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1431	}
1432
1433
1434	/**
1435	* Reports MSR_IA32_VMX_MISC MSR to the log.
1436	*
1437	* @param pVM Pointer to the VM.
1438	* @param fMisc The VMX misc. MSR value.
1439	*/
1440	static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1441	{
1442	LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1443	uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1444	if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1445	LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1446	else
1447	{
1448	LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1449	pVM->hm.s.vmx.cPreemptTimerShift));
1450	}
1451	LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1452	LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1453	hmR3VmxGetActivityStateAllDesc(fMisc)));
1454	LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1455	LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1456	LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1457	LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1458	VMX_MISC_MAX_MSRS(fMisc)));
1459	LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1460	LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1461	LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1462	LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1463	}
1464
1465
1466	/**
1467	* Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1468	*
1469	* @param uVmcsEnum The VMX VMCS enum MSR value.
1470	*/
1471	static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1472	{
1473	LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1474	LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1475	}
1476
1477
1478	/**
1479	* Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1480	*
1481	* @param uVmFunc The VMX VMFUNC MSR value.
1482	*/
1483	static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1484	{
1485	LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1486	HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1487	}
1488
1489
1490	/**
1491	* Reports VMX CR0, CR4 fixed MSRs.
1492	*
1493	* @param pMsrs Pointer to the VMX MSRs.
1494	*/
1495	static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1496	{
1497	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1498	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1499	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1500	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1501	}
1502
1503
1504	/**
1505	* Finish VT-x initialization (after ring-0 init).
1506	*
1507	* @returns VBox status code.
1508	* @param pVM The cross context VM structure.
1509	*/
1510	static int hmR3InitFinalizeR0Intel(PVM pVM)
1511	{
1512	int rc;
1513
1514	LogFunc(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1515	AssertLogRelReturn(pVM->hm.s.ForR3.vmx.Msrs.u64FeatCtrl != 0, VERR_HM_IPE_4);
1516
1517	LogRel(("HM: Using VT-x implementation 3.0\n"));
1518	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1519	LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostCr4));
1520	LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostMsrEfer));
1521	LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostSmmMonitorCtl));
1522
1523	hmR3VmxReportFeatCtlMsr(pVM->hm.s.ForR3.vmx.Msrs.u64FeatCtrl);
1524	hmR3VmxReportBasicMsr(pVM->hm.s.ForR3.vmx.Msrs.u64Basic);
1525
1526	hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.PinCtls);
1527	hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls);
1528	if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1529	hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2);
1530
1531	hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.EntryCtls);
1532	hmR3VmxReportExitCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ExitCtls);
1533
1534	if (RT_BF_GET(pVM->hm.s.ForR3.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1535	{
1536	/* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1537	LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TruePinCtls));
1538	LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueProcCtls));
1539	LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueEntryCtls));
1540	LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueExitCtls));
1541	}
1542
1543	hmR3VmxReportMiscMsr(pVM, pVM->hm.s.ForR3.vmx.Msrs.u64Misc);
1544	hmR3VmxReportVmcsEnumMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmcsEnum);
1545	if (pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps)
1546	hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps);
1547	if (pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc)
1548	hmR3VmxReportVmFuncMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc);
1549	hmR3VmxReportCrFixedMsrs(&pVM->hm.s.ForR3.vmx.Msrs);
1550
1551	#ifdef TODO_9217_VMCSINFO
1552	LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1553	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1554	{
1555	PCVMXVMCSINFOSHARED pVmcsInfo = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfo;
1556	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
1557	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysVmcs));
1558	}
1559	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1560	if (pVM->cpum.ro.GuestFeatures.fVmx)
1561	{
1562	LogRel(("HM: Nested-guest:\n"));
1563	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1564	{
1565	PCVMXVMCSINFOSHARED pVmcsInfoNstGst = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfoNstGst;
1566	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysMsrBitmap));
1567	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysVmcs));
1568	}
1569	}
1570	#endif
1571	#endif /* TODO_9217_VMCSINFO */
1572
1573	/*
1574	* EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1575	*/
1576	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1577	\|\| (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1578	VERR_HM_IPE_1);
1579	AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuestCfg
1580	\|\| ( (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1581	&& pVM->hm.s.fNestedPagingCfg),
1582	VERR_HM_IPE_1);
1583
1584	/*
1585	* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1586	* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1587	* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1588	*/
1589	if ( !(pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1590	&& CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1591	{
1592	CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1593	LogRel(("HM: Disabled RDTSCP\n"));
1594	}
1595
1596	if (!pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1597	{
1598	/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1599	rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1600	if (RT_SUCCESS(rc))
1601	{
1602	/* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1603	Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1604	esp. Figure 20-5.*/
1605	ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1606	pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1607
1608	/* Bit set to 0 means software interrupts are redirected to the
1609	8086 program interrupt handler rather than switching to
1610	protected-mode handler. */
1611	memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1612
1613	/* Allow all port IO, so that port IO instructions do not cause
1614	exceptions and would instead cause a VM-exit (based on VT-x's
1615	IO bitmap which we currently configure to always cause an exit). */
1616	memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1617	((unsigned char )pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1618
1619	/*
1620	* Construct a 1024 element page directory with 4 MB pages for the identity mapped
1621	* page table used in real and protected mode without paging with EPT.
1622	*/
1623	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
1624	for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1625	{
1626	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1627	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US
1628	\| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS
1629	\| X86_PDE4M_G;
1630	}
1631
1632	/* We convert it here every time as PCI regions could be reconfigured. */
1633	if (PDMVmmDevHeapIsEnabled(pVM))
1634	{
1635	RTGCPHYS GCPhys;
1636	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1637	AssertRCReturn(rc, rc);
1638	LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1639
1640	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1641	AssertRCReturn(rc, rc);
1642	LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1643	}
1644	}
1645	else
1646	{
1647	LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1648	pVM->hm.s.vmx.pRealModeTSS = NULL;
1649	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1650	return VMSetError(pVM, rc, RT_SRC_POS,
1651	"HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1652	}
1653	}
1654
1655	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1656	: "HM: Guest support: 32-bit only\n"));
1657
1658	/*
1659	* Call ring-0 to set up the VM.
1660	*/
1661	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /* idCpu /, VMMR0_DO_HM_SETUP_VM, 0 / u64Arg /, NULL / pReqHdr */);
1662	if (rc != VINF_SUCCESS)
1663	{
1664	LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1665	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1666	{
1667	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1668	LogRel(("HM: CPU[%u] Last instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
1669	LogRel(("HM: CPU[%u] HM error %#x (%u)\n", idCpu, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1670	}
1671	HMR3CheckError(pVM, rc);
1672	return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1673	}
1674
1675	LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.ForR3.vmx.fSupportsVmcsEfer));
1676	LogRel(("HM: Enabled VMX\n"));
1677	pVM->hm.s.vmx.fEnabled = true;
1678
1679	hmR3DisableRawMode(pVM); /** @todo make this go away! */
1680
1681	/*
1682	* Change the CPU features.
1683	*/
1684	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1685	if (pVM->hm.s.fAllow64BitGuestsCfg)
1686	{
1687	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1688	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1689	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* (Long mode only on Intel CPUs.) */
1690	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1691	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1692	}
1693	/* Given that we're on a long mode host, we can simply enable NX for PAE capable guests. */
1694	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1695	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1696
1697	/*
1698	* Log configuration details.
1699	*/
1700	if (pVM->hm.s.fNestedPagingCfg)
1701	{
1702	LogRel(("HM: Enabled nested paging\n"));
1703	if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1704	LogRel(("HM: EPT flush type = Single context\n"));
1705	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1706	LogRel(("HM: EPT flush type = All contexts\n"));
1707	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1708	LogRel(("HM: EPT flush type = Not supported\n"));
1709	else
1710	LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushEpt));
1711
1712	if (pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1713	LogRel(("HM: Enabled unrestricted guest execution\n"));
1714
1715	if (pVM->hm.s.fLargePages)
1716	{
1717	/* Use large (2 MB) pages for our EPT PDEs where possible. */
1718	PGMSetLargePageUsage(pVM, true);
1719	LogRel(("HM: Enabled large page support\n"));
1720	}
1721	}
1722	else
1723	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
1724
1725	if (pVM->hm.s.ForR3.vmx.fVpid)
1726	{
1727	LogRel(("HM: Enabled VPID\n"));
1728	if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1729	LogRel(("HM: VPID flush type = Individual addresses\n"));
1730	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1731	LogRel(("HM: VPID flush type = Single context\n"));
1732	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1733	LogRel(("HM: VPID flush type = All contexts\n"));
1734	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1735	LogRel(("HM: VPID flush type = Single context retain globals\n"));
1736	else
1737	LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushVpid));
1738	}
1739	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1740	LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1741
1742	if (pVM->hm.s.vmx.fUsePreemptTimerCfg)
1743	LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1744	else
1745	LogRel(("HM: Disabled VMX-preemption timer\n"));
1746
1747	if (pVM->hm.s.fVirtApicRegs)
1748	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1749
1750	if (pVM->hm.s.fPostedIntrs)
1751	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1752
1753	if (pVM->hm.s.ForR3.vmx.fUseVmcsShadowing)
1754	{
1755	bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.ForR3.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL);
1756	LogRel(("HM: Enabled %s VMCS shadowing\n", fFullVmcsShadow ? "full" : "partial"));
1757	}
1758
1759	return VINF_SUCCESS;
1760	}
1761
1762
1763	/**
1764	* Finish AMD-V initialization (after ring-0 init).
1765	*
1766	* @returns VBox status code.
1767	* @param pVM The cross context VM structure.
1768	*/
1769	static int hmR3InitFinalizeR0Amd(PVM pVM)
1770	{
1771	LogFunc(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1772
1773	LogRel(("HM: Using AMD-V implementation 2.0\n"));
1774
1775	uint32_t u32Family;
1776	uint32_t u32Model;
1777	uint32_t u32Stepping;
1778	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
1779	LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1780	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1781	LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.ForR3.svm.u64MsrHwcr));
1782	LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.ForR3.svm.u32Rev));
1783	LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.ForR3.uMaxAsid));
1784	LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.ForR3.svm.fFeatures));
1785
1786	/*
1787	* Enumerate AMD-V features.
1788	*/
1789	static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1790	{
1791	#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1792	HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1793	HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1794	HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1795	HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1796	HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1797	HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1798	HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1799	HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1800	HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1801	HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1802	HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1803	HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1804	HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1805	HMSVM_REPORT_FEATURE("GMET", X86_CPUID_SVM_FEATURE_EDX_GMET),
1806	#undef HMSVM_REPORT_FEATURE
1807	};
1808
1809	uint32_t fSvmFeatures = pVM->hm.s.ForR3.svm.fFeatures;
1810	for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1811	if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1812	{
1813	LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1814	fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1815	}
1816	if (fSvmFeatures)
1817	for (unsigned iBit = 0; iBit < 32; iBit++)
1818	if (RT_BIT_32(iBit) & fSvmFeatures)
1819	LogRel(("HM: Reserved bit %u\n", iBit));
1820
1821	/*
1822	* Nested paging is determined in HMR3Init, verify the sanity of that.
1823	*/
1824	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1825	\|\| (pVM->hm.s.ForR3.svm.fFeatures & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1826	VERR_HM_IPE_1);
1827
1828	#if 0
1829	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1830	* here. */
1831	if (RTR0IsPostIpiSupport())
1832	pVM->hm.s.fPostedIntrs = true;
1833	#endif
1834
1835	/*
1836	* Determine whether we need to intercept #UD in SVM mode for emulating
1837	* intel SYSENTER/SYSEXIT on AMD64, as these instructions results in #UD
1838	* when executed in long-mode. This is only really applicable when
1839	* non-default CPU profiles are in effect, i.e. guest vendor differs
1840	* from the host one.
1841	*/
1842	if (CPUMGetGuestCpuVendor(pVM) != CPUMGetHostCpuVendor(pVM))
1843	switch (CPUMGetGuestCpuVendor(pVM))
1844	{
1845	case CPUMCPUVENDOR_INTEL:
1846	case CPUMCPUVENDOR_VIA: /?/
1847	case CPUMCPUVENDOR_SHANGHAI: /?/
1848	switch (CPUMGetHostCpuVendor(pVM))
1849	{
1850	case CPUMCPUVENDOR_AMD:
1851	case CPUMCPUVENDOR_HYGON:
1852	if (pVM->hm.s.fAllow64BitGuestsCfg)
1853	{
1854	LogRel(("HM: Intercepting #UD for emulating SYSENTER/SYSEXIT in long mode.\n"));
1855	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1856	pVM->apCpusR3[idCpu]->hm.s.svm.fEmulateLongModeSysEnterExit = true;
1857	}
1858	break;
1859	default: break;
1860	}
1861	default: break;
1862	}
1863
1864	/*
1865	* Call ring-0 to set up the VM.
1866	*/
1867	int rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1868	if (rc != VINF_SUCCESS)
1869	{
1870	AssertMsgFailed(("%Rrc\n", rc));
1871	LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1872	return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1873	}
1874
1875	LogRel(("HM: Enabled SVM\n"));
1876	pVM->hm.s.svm.fEnabled = true;
1877
1878	if (pVM->hm.s.fNestedPagingCfg)
1879	{
1880	LogRel(("HM: Enabled nested paging\n"));
1881
1882	/*
1883	* Enable large pages (2 MB) if applicable.
1884	*/
1885	if (pVM->hm.s.fLargePages)
1886	{
1887	PGMSetLargePageUsage(pVM, true);
1888	LogRel(("HM: Enabled large page support\n"));
1889	}
1890	}
1891
1892	if (pVM->hm.s.fVirtApicRegs)
1893	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1894
1895	if (pVM->hm.s.fPostedIntrs)
1896	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1897
1898	hmR3DisableRawMode(pVM);
1899
1900	/*
1901	* Change the CPU features.
1902	*/
1903	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1904	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1905	if (pVM->hm.s.fAllow64BitGuestsCfg)
1906	{
1907	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1908	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1909	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1910	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1911	}
1912	/* Turn on NXE if PAE has been enabled. */
1913	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1914	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1915
1916	LogRel((pVM->hm.s.fTprPatchingAllowed ? "HM: Enabled TPR patching\n"
1917	: "HM: Disabled TPR patching\n"));
1918
1919	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1920	: "HM: Guest support: 32-bit only\n"));
1921	return VINF_SUCCESS;
1922	}
1923
1924
1925	/**
1926	* Applies relocations to data and code managed by this
1927	* component. This function will be called at init and
1928	* whenever the VMM need to relocate it self inside the GC.
1929	*
1930	* @param pVM The cross context VM structure.
1931	*/
1932	VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1933	{
1934	Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1935
1936	/* Fetch the current paging mode during the relocate callback during state loading. */
1937	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1938	{
1939	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1940	{
1941	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1942	pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1943	}
1944	}
1945	}
1946
1947
1948	/**
1949	* Terminates the HM.
1950	*
1951	* Termination means cleaning up and freeing all resources,
1952	* the VM itself is, at this point, powered off or suspended.
1953	*
1954	* @returns VBox status code.
1955	* @param pVM The cross context VM structure.
1956	*/
1957	VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1958	{
1959	if (pVM->hm.s.vmx.pRealModeTSS)
1960	{
1961	PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1962	pVM->hm.s.vmx.pRealModeTSS = 0;
1963	}
1964	hmR3TermCPU(pVM);
1965	return 0;
1966	}
1967
1968
1969	/**
1970	* Terminates the per-VCPU HM.
1971	*
1972	* @returns VBox status code.
1973	* @param pVM The cross context VM structure.
1974	*/
1975	static int hmR3TermCPU(PVM pVM)
1976	{
1977	#ifdef VBOX_WITH_STATISTICS
1978	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1979	{
1980	PVMCPU pVCpu = pVM->apCpusR3[idCpu]; NOREF(pVCpu);
1981	if (pVCpu->hm.s.paStatExitReason)
1982	{
1983	MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1984	pVCpu->hm.s.paStatExitReason = NULL;
1985	pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1986	}
1987	if (pVCpu->hm.s.paStatInjectedIrqs)
1988	{
1989	MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1990	pVCpu->hm.s.paStatInjectedIrqs = NULL;
1991	pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1992	}
1993	if (pVCpu->hm.s.paStatInjectedXcpts)
1994	{
1995	MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedXcpts);
1996	pVCpu->hm.s.paStatInjectedXcpts = NULL;
1997	pVCpu->hm.s.paStatInjectedXcptsR0 = NIL_RTR0PTR;
1998	}
1999	# if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
2000	if (pVCpu->hm.s.paStatNestedExitReason)
2001	{
2002	MMHyperFree(pVM, pVCpu->hm.s.paStatNestedExitReason);
2003	pVCpu->hm.s.paStatNestedExitReason = NULL;
2004	pVCpu->hm.s.paStatNestedExitReasonR0 = NIL_RTR0PTR;
2005	}
2006	# endif
2007	}
2008	#else
2009	RT_NOREF(pVM);
2010	#endif
2011	return VINF_SUCCESS;
2012	}
2013
2014
2015	/**
2016	* Resets a virtual CPU.
2017	*
2018	* Used by HMR3Reset and CPU hot plugging.
2019	*
2020	* @param pVCpu The cross context virtual CPU structure to reset.
2021	*/
2022	VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
2023	{
2024	/* Sync. entire state on VM reset ring-0 re-entry. It's safe to reset
2025	the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2026	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
2027
2028	pVCpu->hm.s.fActive = false;
2029	pVCpu->hm.s.Event.fPending = false;
2030	pVCpu->hm.s.vmx.u64GstMsrApicBase = 0;
2031	pVCpu->hm.s.vmx.VmcsInfo.fWasInRealMode = true;
2032	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2033	if (pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmx)
2034	pVCpu->hm.s.vmx.VmcsInfoNstGst.fWasInRealMode = true;
2035	#endif
2036	}
2037
2038
2039	/**
2040	* The VM is being reset.
2041	*
2042	* For the HM component this means that any GDT/LDT/TSS monitors
2043	* needs to be removed.
2044	*
2045	* @param pVM The cross context VM structure.
2046	*/
2047	VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2048	{
2049	LogFlow(("HMR3Reset:\n"));
2050
2051	if (HMIsEnabled(pVM))
2052	hmR3DisableRawMode(pVM);
2053
2054	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2055	HMR3ResetCpu(pVM->apCpusR3[idCpu]);
2056
2057	/* Clear all patch information. */
2058	pVM->hm.s.pGuestPatchMem = 0;
2059	pVM->hm.s.pFreeGuestPatchMem = 0;
2060	pVM->hm.s.cbGuestPatchMem = 0;
2061	pVM->hm.s.cPatches = 0;
2062	pVM->hm.s.PatchTree = 0;
2063	pVM->hm.s.fTprPatchingActive = false;
2064	ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2065	}
2066
2067
2068	/**
2069	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2070	*
2071	* @returns VBox strict status code.
2072	* @param pVM The cross context VM structure.
2073	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2074	* @param pvUser Unused.
2075	*/
2076	static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2077	{
2078	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2079
2080	/* Only execute the handler on the VCPU the original patch request was issued. */
2081	if (pVCpu->idCpu != idCpu)
2082	return VINF_SUCCESS;
2083
2084	Log(("hmR3RemovePatches\n"));
2085	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2086	{
2087	uint8_t abInstr[15];
2088	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2089	RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2090	int rc;
2091
2092	#ifdef LOG_ENABLED
2093	char szOutput[256];
2094	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2095	szOutput, sizeof(szOutput), NULL);
2096	if (RT_SUCCESS(rc))
2097	Log(("Patched instr: %s\n", szOutput));
2098	#endif
2099
2100	/* Check if the instruction is still the same. */
2101	rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2102	if (rc != VINF_SUCCESS)
2103	{
2104	Log(("Patched code removed? (rc=%Rrc0\n", rc));
2105	continue; /* swapped out or otherwise removed; skip it. */
2106	}
2107
2108	if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2109	{
2110	Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2111	continue; /* skip it. */
2112	}
2113
2114	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2115	AssertRC(rc);
2116
2117	#ifdef LOG_ENABLED
2118	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2119	szOutput, sizeof(szOutput), NULL);
2120	if (RT_SUCCESS(rc))
2121	Log(("Original instr: %s\n", szOutput));
2122	#endif
2123	}
2124	pVM->hm.s.cPatches = 0;
2125	pVM->hm.s.PatchTree = 0;
2126	pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2127	pVM->hm.s.fTprPatchingActive = false;
2128	return VINF_SUCCESS;
2129	}
2130
2131
2132	/**
2133	* Worker for enabling patching in a VT-x/AMD-V guest.
2134	*
2135	* @returns VBox status code.
2136	* @param pVM The cross context VM structure.
2137	* @param idCpu VCPU to execute hmR3RemovePatches on.
2138	* @param pPatchMem Patch memory range.
2139	* @param cbPatchMem Size of the memory range.
2140	*/
2141	static DECLCALLBACK(int) hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2142	{
2143	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2144	AssertRC(rc);
2145
2146	pVM->hm.s.pGuestPatchMem = pPatchMem;
2147	pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2148	pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2149	return VINF_SUCCESS;
2150	}
2151
2152
2153	/**
2154	* Enable patching in a VT-x/AMD-V guest
2155	*
2156	* @returns VBox status code.
2157	* @param pVM The cross context VM structure.
2158	* @param pPatchMem Patch memory range.
2159	* @param cbPatchMem Size of the memory range.
2160	*/
2161	VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2162	{
2163	VM_ASSERT_EMT(pVM);
2164	Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2165	if (pVM->cCpus > 1)
2166	{
2167	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2168	int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2169	(PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2170	AssertRC(rc);
2171	return rc;
2172	}
2173	return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2174	}
2175
2176
2177	/**
2178	* Disable patching in a VT-x/AMD-V guest.
2179	*
2180	* @returns VBox status code.
2181	* @param pVM The cross context VM structure.
2182	* @param pPatchMem Patch memory range.
2183	* @param cbPatchMem Size of the memory range.
2184	*/
2185	VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2186	{
2187	Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2188	RT_NOREF2(pPatchMem, cbPatchMem);
2189
2190	Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2191	Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2192
2193	/** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2194	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2195	(void *)(uintptr_t)VMMGetCpuId(pVM));
2196	AssertRC(rc);
2197
2198	pVM->hm.s.pGuestPatchMem = 0;
2199	pVM->hm.s.pFreeGuestPatchMem = 0;
2200	pVM->hm.s.cbGuestPatchMem = 0;
2201	pVM->hm.s.fTprPatchingActive = false;
2202	return VINF_SUCCESS;
2203	}
2204
2205
2206	/**
2207	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2208	*
2209	* @returns VBox strict status code.
2210	* @param pVM The cross context VM structure.
2211	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2212	* @param pvUser User specified CPU context.
2213	*
2214	*/
2215	static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2216	{
2217	/*
2218	* Only execute the handler on the VCPU the original patch request was
2219	* issued. (The other CPU(s) might not yet have switched to protected
2220	* mode, nor have the correct memory context.)
2221	*/
2222	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2223	if (pVCpu->idCpu != idCpu)
2224	return VINF_SUCCESS;
2225
2226	/*
2227	* We're racing other VCPUs here, so don't try patch the instruction twice
2228	* and make sure there is still room for our patch record.
2229	*/
2230	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2231	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2232	if (pPatch)
2233	{
2234	Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2235	return VINF_SUCCESS;
2236	}
2237	uint32_t const idx = pVM->hm.s.cPatches;
2238	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2239	{
2240	Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2241	return VINF_SUCCESS;
2242	}
2243	pPatch = &pVM->hm.s.aPatches[idx];
2244
2245	Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2246
2247	/*
2248	* Disassembler the instruction and get cracking.
2249	*/
2250	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2251	DISCPUSTATE Dis;
2252	uint32_t cbOp;
2253	int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2254	AssertRC(rc);
2255	if ( rc == VINF_SUCCESS
2256	&& Dis.pCurInstr->uOpcode == OP_MOV
2257	&& cbOp >= 3)
2258	{
2259	static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2260
2261	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2262	AssertRC(rc);
2263
2264	pPatch->cbOp = cbOp;
2265
2266	if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2267	{
2268	/* write. */
2269	if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2270	{
2271	pPatch->enmType = HMTPRINSTR_WRITE_REG;
2272	pPatch->uSrcOperand = Dis.Param2.Base.idxGenReg;
2273	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", Dis.Param2.Base.idxGenReg));
2274	}
2275	else
2276	{
2277	Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2278	pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2279	pPatch->uSrcOperand = Dis.Param2.uValue;
2280	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", Dis.Param2.uValue));
2281	}
2282	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2283	AssertRC(rc);
2284
2285	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2286	pPatch->cbNewOp = sizeof(s_abVMMCall);
2287	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2288	}
2289	else
2290	{
2291	/*
2292	* TPR Read.
2293	*
2294	* Found:
2295	* mov eax, dword [fffe0080] (5 bytes)
2296	* Check if next instruction is:
2297	* shr eax, 4
2298	*/
2299	Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2300
2301	uint8_t const idxMmioReg = Dis.Param1.Base.idxGenReg;
2302	uint8_t const cbOpMmio = cbOp;
2303	uint64_t const uSavedRip = pCtx->rip;
2304
2305	pCtx->rip += cbOp;
2306	rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2307	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2308	pCtx->rip = uSavedRip;
2309
2310	if ( rc == VINF_SUCCESS
2311	&& Dis.pCurInstr->uOpcode == OP_SHR
2312	&& Dis.Param1.fUse == DISUSE_REG_GEN32
2313	&& Dis.Param1.Base.idxGenReg == idxMmioReg
2314	&& Dis.Param2.fUse == DISUSE_IMMEDIATE8
2315	&& Dis.Param2.uValue == 4
2316	&& cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2317	{
2318	uint8_t abInstr[15];
2319
2320	/* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2321	access CR8 in 32-bit mode and not cause a #VMEXIT. */
2322	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2323	AssertRC(rc);
2324
2325	pPatch->cbOp = cbOpMmio + cbOp;
2326
2327	/* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2328	abInstr[0] = 0xf0;
2329	abInstr[1] = 0x0f;
2330	abInstr[2] = 0x20;
2331	abInstr[3] = 0xc0 \| Dis.Param1.Base.idxGenReg;
2332	for (unsigned i = 4; i < pPatch->cbOp; i++)
2333	abInstr[i] = 0x90; /* nop */
2334
2335	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2336	AssertRC(rc);
2337
2338	memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2339	pPatch->cbNewOp = pPatch->cbOp;
2340	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2341
2342	Log(("Acceptable read/shr candidate!\n"));
2343	pPatch->enmType = HMTPRINSTR_READ_SHR4;
2344	}
2345	else
2346	{
2347	pPatch->enmType = HMTPRINSTR_READ;
2348	pPatch->uDstOperand = idxMmioReg;
2349
2350	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2351	AssertRC(rc);
2352
2353	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2354	pPatch->cbNewOp = sizeof(s_abVMMCall);
2355	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2356	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2357	}
2358	}
2359
2360	pPatch->Core.Key = pCtx->eip;
2361	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2362	AssertRC(rc);
2363
2364	pVM->hm.s.cPatches++;
2365	return VINF_SUCCESS;
2366	}
2367
2368	/*
2369	* Save invalid patch, so we will not try again.
2370	*/
2371	Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2372	pPatch->Core.Key = pCtx->eip;
2373	pPatch->enmType = HMTPRINSTR_INVALID;
2374	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2375	AssertRC(rc);
2376	pVM->hm.s.cPatches++;
2377	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2378	return VINF_SUCCESS;
2379	}
2380
2381
2382	/**
2383	* Callback to patch a TPR instruction (jump to generated code).
2384	*
2385	* @returns VBox strict status code.
2386	* @param pVM The cross context VM structure.
2387	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2388	* @param pvUser User specified CPU context.
2389	*
2390	*/
2391	static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2392	{
2393	/*
2394	* Only execute the handler on the VCPU the original patch request was
2395	* issued. (The other CPU(s) might not yet have switched to protected
2396	* mode, nor have the correct memory context.)
2397	*/
2398	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2399	if (pVCpu->idCpu != idCpu)
2400	return VINF_SUCCESS;
2401
2402	/*
2403	* We're racing other VCPUs here, so don't try patch the instruction twice
2404	* and make sure there is still room for our patch record.
2405	*/
2406	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2407	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2408	if (pPatch)
2409	{
2410	Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2411	return VINF_SUCCESS;
2412	}
2413	uint32_t const idx = pVM->hm.s.cPatches;
2414	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2415	{
2416	Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2417	return VINF_SUCCESS;
2418	}
2419	pPatch = &pVM->hm.s.aPatches[idx];
2420
2421	Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2422	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2423
2424	/*
2425	* Disassemble the instruction and get cracking.
2426	*/
2427	DISCPUSTATE Dis;
2428	uint32_t cbOp;
2429	int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2430	AssertRC(rc);
2431	if ( rc == VINF_SUCCESS
2432	&& Dis.pCurInstr->uOpcode == OP_MOV
2433	&& cbOp >= 5)
2434	{
2435	uint8_t aPatch[64];
2436	uint32_t off = 0;
2437
2438	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2439	AssertRC(rc);
2440
2441	pPatch->cbOp = cbOp;
2442	pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2443
2444	if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2445	{
2446	/*
2447	* TPR write:
2448	*
2449	* push ECX [51]
2450	* push EDX [52]
2451	* push EAX [50]
2452	* xor EDX,EDX [31 D2]
2453	* mov EAX,EAX [89 C0]
2454	* or
2455	* mov EAX,0000000CCh [B8 CC 00 00 00]
2456	* mov ECX,0C0000082h [B9 82 00 00 C0]
2457	* wrmsr [0F 30]
2458	* pop EAX [58]
2459	* pop EDX [5A]
2460	* pop ECX [59]
2461	* jmp return_address [E9 return_address]
2462	*/
2463	bool fUsesEax = (Dis.Param2.fUse == DISUSE_REG_GEN32 && Dis.Param2.Base.idxGenReg == DISGREG_EAX);
2464
2465	aPatch[off++] = 0x51; /* push ecx */
2466	aPatch[off++] = 0x52; /* push edx */
2467	if (!fUsesEax)
2468	aPatch[off++] = 0x50; /* push eax */
2469	aPatch[off++] = 0x31; /* xor edx, edx */
2470	aPatch[off++] = 0xd2;
2471	if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2472	{
2473	if (!fUsesEax)
2474	{
2475	aPatch[off++] = 0x89; /* mov eax, src_reg */
2476	aPatch[off++] = MAKE_MODRM(3, Dis.Param2.Base.idxGenReg, DISGREG_EAX);
2477	}
2478	}
2479	else
2480	{
2481	Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2482	aPatch[off++] = 0xb8; /* mov eax, immediate */
2483	(uint32_t )&aPatch[off] = Dis.Param2.uValue;
2484	off += sizeof(uint32_t);
2485	}
2486	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2487	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2488	off += sizeof(uint32_t);
2489
2490	aPatch[off++] = 0x0f; /* wrmsr */
2491	aPatch[off++] = 0x30;
2492	if (!fUsesEax)
2493	aPatch[off++] = 0x58; /* pop eax */
2494	aPatch[off++] = 0x5a; /* pop edx */
2495	aPatch[off++] = 0x59; /* pop ecx */
2496	}
2497	else
2498	{
2499	/*
2500	* TPR read:
2501	*
2502	* push ECX [51]
2503	* push EDX [52]
2504	* push EAX [50]
2505	* mov ECX,0C0000082h [B9 82 00 00 C0]
2506	* rdmsr [0F 32]
2507	* mov EAX,EAX [89 C0]
2508	* pop EAX [58]
2509	* pop EDX [5A]
2510	* pop ECX [59]
2511	* jmp return_address [E9 return_address]
2512	*/
2513	Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2514
2515	if (Dis.Param1.Base.idxGenReg != DISGREG_ECX)
2516	aPatch[off++] = 0x51; /* push ecx */
2517	if (Dis.Param1.Base.idxGenReg != DISGREG_EDX )
2518	aPatch[off++] = 0x52; /* push edx */
2519	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2520	aPatch[off++] = 0x50; /* push eax */
2521
2522	aPatch[off++] = 0x31; /* xor edx, edx */
2523	aPatch[off++] = 0xd2;
2524
2525	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2526	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2527	off += sizeof(uint32_t);
2528
2529	aPatch[off++] = 0x0f; /* rdmsr */
2530	aPatch[off++] = 0x32;
2531
2532	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2533	{
2534	aPatch[off++] = 0x89; /* mov dst_reg, eax */
2535	aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, Dis.Param1.Base.idxGenReg);
2536	}
2537
2538	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2539	aPatch[off++] = 0x58; /* pop eax */
2540	if (Dis.Param1.Base.idxGenReg != DISGREG_EDX )
2541	aPatch[off++] = 0x5a; /* pop edx */
2542	if (Dis.Param1.Base.idxGenReg != DISGREG_ECX)
2543	aPatch[off++] = 0x59; /* pop ecx */
2544	}
2545	aPatch[off++] = 0xe9; /* jmp return_address */
2546	(RTRCUINTPTR )&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2547	off += sizeof(RTRCUINTPTR);
2548
2549	if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2550	{
2551	/* Write new code to the patch buffer. */
2552	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2553	AssertRC(rc);
2554
2555	#ifdef LOG_ENABLED
2556	uint32_t cbCurInstr;
2557	for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2558	GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2559	GCPtrInstr += RT_MAX(cbCurInstr, 1))
2560	{
2561	char szOutput[256];
2562	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2563	szOutput, sizeof(szOutput), &cbCurInstr);
2564	if (RT_SUCCESS(rc))
2565	Log(("Patch instr %s\n", szOutput));
2566	else
2567	Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2568	}
2569	#endif
2570
2571	pPatch->aNewOpcode[0] = 0xE9;
2572	(RTRCUINTPTR )&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2573
2574	/* Overwrite the TPR instruction with a jump. */
2575	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2576	AssertRC(rc);
2577
2578	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2579
2580	pVM->hm.s.pFreeGuestPatchMem += off;
2581	pPatch->cbNewOp = 5;
2582
2583	pPatch->Core.Key = pCtx->eip;
2584	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2585	AssertRC(rc);
2586
2587	pVM->hm.s.cPatches++;
2588	pVM->hm.s.fTprPatchingActive = true;
2589	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2590	return VINF_SUCCESS;
2591	}
2592
2593	Log(("Ran out of space in our patch buffer!\n"));
2594	}
2595	else
2596	Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2597
2598
2599	/*
2600	* Save invalid patch, so we will not try again.
2601	*/
2602	pPatch = &pVM->hm.s.aPatches[idx];
2603	pPatch->Core.Key = pCtx->eip;
2604	pPatch->enmType = HMTPRINSTR_INVALID;
2605	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2606	AssertRC(rc);
2607	pVM->hm.s.cPatches++;
2608	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2609	return VINF_SUCCESS;
2610	}
2611
2612
2613	/**
2614	* Attempt to patch TPR mmio instructions.
2615	*
2616	* @returns VBox status code.
2617	* @param pVM The cross context VM structure.
2618	* @param pVCpu The cross context virtual CPU structure.
2619	*/
2620	VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2621	{
2622	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2623	pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2624	(void *)(uintptr_t)pVCpu->idCpu);
2625	AssertRC(rc);
2626	return rc;
2627	}
2628
2629
2630	/**
2631	* Checks if we need to reschedule due to VMM device heap changes.
2632	*
2633	* @returns true if a reschedule is required, otherwise false.
2634	* @param pVM The cross context VM structure.
2635	* @param pCtx VM execution context.
2636	*/
2637	VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCCPUMCTX pCtx)
2638	{
2639	/*
2640	* The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2641	* when the unrestricted guest execution feature is missing (VT-x only).
2642	*/
2643	if ( pVM->hm.s.vmx.fEnabled
2644	&& !pVM->hm.s.vmx.fUnrestrictedGuestCfg
2645	&& CPUMIsGuestInRealModeEx(pCtx)
2646	&& !PDMVmmDevHeapIsEnabled(pVM))
2647	return true;
2648
2649	return false;
2650	}
2651
2652
2653	/**
2654	* Noticiation callback from DBGF when interrupt breakpoints or generic debug
2655	* event settings changes.
2656	*
2657	* DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2658	* function is just updating the VM globals.
2659	*
2660	* @param pVM The VM cross context VM structure.
2661	* @thread EMT(0)
2662	*/
2663	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2664	{
2665	/* Interrupts. */
2666	bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2667	\|\| pVM->dbgf.ro.cHardIntBreakpoints > 0;
2668
2669	/* CPU Exceptions. */
2670	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2671	!fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2672	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2673	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2674
2675	/* Common VM exits. */
2676	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2677	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2678	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2679	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2680
2681	/* Vendor specific VM exits. */
2682	if (HMR3IsVmxEnabled(pVM->pUVM))
2683	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2684	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2685	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2686	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2687	else
2688	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2689	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2690	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2691	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2692
2693	/* Done. */
2694	pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2695	}
2696
2697
2698	/**
2699	* Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2700	*
2701	* HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2702	* per CPU settings.
2703	*
2704	* @param pVM The VM cross context VM structure.
2705	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2706	*/
2707	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2708	{
2709	pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction \| pVM->hm.s.fUseDebugLoop;
2710	}
2711
2712
2713	/**
2714	* Checks if we are currently using hardware acceleration.
2715	*
2716	* @returns true if hardware acceleration is being used, otherwise false.
2717	* @param pVCpu The cross context virtual CPU structure.
2718	*/
2719	VMMR3_INT_DECL(bool) HMR3IsActive(PCVMCPU pVCpu)
2720	{
2721	return pVCpu->hm.s.fActive;
2722	}
2723
2724
2725	/**
2726	* External interface for querying whether hardware acceleration is enabled.
2727	*
2728	* @returns true if VT-x or AMD-V is being used, otherwise false.
2729	* @param pUVM The user mode VM handle.
2730	* @sa HMIsEnabled, HMIsEnabledNotMacro.
2731	*/
2732	VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2733	{
2734	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2735	PVM pVM = pUVM->pVM;
2736	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2737	return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2738	}
2739
2740
2741	/**
2742	* External interface for querying whether VT-x is being used.
2743	*
2744	* @returns true if VT-x is being used, otherwise false.
2745	* @param pUVM The user mode VM handle.
2746	* @sa HMR3IsSvmEnabled, HMIsEnabled
2747	*/
2748	VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2749	{
2750	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2751	PVM pVM = pUVM->pVM;
2752	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2753	return pVM->hm.s.vmx.fEnabled
2754	&& pVM->hm.s.vmx.fSupported
2755	&& pVM->fHMEnabled;
2756	}
2757
2758
2759	/**
2760	* External interface for querying whether AMD-V is being used.
2761	*
2762	* @returns true if VT-x is being used, otherwise false.
2763	* @param pUVM The user mode VM handle.
2764	* @sa HMR3IsVmxEnabled, HMIsEnabled
2765	*/
2766	VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2767	{
2768	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2769	PVM pVM = pUVM->pVM;
2770	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2771	return pVM->hm.s.svm.fEnabled
2772	&& pVM->hm.s.svm.fSupported
2773	&& pVM->fHMEnabled;
2774	}
2775
2776
2777	/**
2778	* Checks if we are currently using nested paging.
2779	*
2780	* @returns true if nested paging is being used, otherwise false.
2781	* @param pUVM The user mode VM handle.
2782	*/
2783	VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2784	{
2785	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2786	PVM pVM = pUVM->pVM;
2787	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2788	return pVM->hm.s.fNestedPagingCfg;
2789	}
2790
2791
2792	/**
2793	* Checks if virtualized APIC registers are enabled.
2794	*
2795	* When enabled this feature allows the hardware to access most of the
2796	* APIC registers in the virtual-APIC page without causing VM-exits. See
2797	* Intel spec. 29.1.1 "Virtualized APIC Registers".
2798	*
2799	* @returns true if virtualized APIC registers is enabled, otherwise
2800	* false.
2801	* @param pUVM The user mode VM handle.
2802	*/
2803	VMMR3DECL(bool) HMR3AreVirtApicRegsEnabled(PUVM pUVM)
2804	{
2805	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2806	PVM pVM = pUVM->pVM;
2807	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2808	return pVM->hm.s.fVirtApicRegs;
2809	}
2810
2811
2812	/**
2813	* Checks if APIC posted-interrupt processing is enabled.
2814	*
2815	* This returns whether we can deliver interrupts to the guest without
2816	* leaving guest-context by updating APIC state from host-context.
2817	*
2818	* @returns true if APIC posted-interrupt processing is enabled,
2819	* otherwise false.
2820	* @param pUVM The user mode VM handle.
2821	*/
2822	VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2823	{
2824	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2825	PVM pVM = pUVM->pVM;
2826	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2827	return pVM->hm.s.fPostedIntrs;
2828	}
2829
2830
2831	/**
2832	* Checks if we are currently using VPID in VT-x mode.
2833	*
2834	* @returns true if VPID is being used, otherwise false.
2835	* @param pUVM The user mode VM handle.
2836	*/
2837	VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2838	{
2839	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2840	PVM pVM = pUVM->pVM;
2841	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2842	return pVM->hm.s.ForR3.vmx.fVpid;
2843	}
2844
2845
2846	/**
2847	* Checks if we are currently using VT-x unrestricted execution,
2848	* aka UX.
2849	*
2850	* @returns true if UX is being used, otherwise false.
2851	* @param pUVM The user mode VM handle.
2852	*/
2853	VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2854	{
2855	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2856	PVM pVM = pUVM->pVM;
2857	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2858	return pVM->hm.s.vmx.fUnrestrictedGuestCfg
2859	\|\| pVM->hm.s.svm.fSupported;
2860	}
2861
2862
2863	/**
2864	* Checks if the VMX-preemption timer is being used.
2865	*
2866	* @returns true if the VMX-preemption timer is being used, otherwise false.
2867	* @param pVM The cross context VM structure.
2868	*/
2869	VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2870	{
2871	return HMIsEnabled(pVM)
2872	&& pVM->hm.s.vmx.fEnabled
2873	&& pVM->hm.s.vmx.fUsePreemptTimerCfg;
2874	}
2875
2876
2877	#ifdef TODO_9217_VMCSINFO
2878	/**
2879	* Helper for HMR3CheckError to log VMCS controls to the release log.
2880	*
2881	* @param idCpu The Virtual CPU ID.
2882	* @param pVmcsInfo The VMCS info. object.
2883	*/
2884	static void hmR3CheckErrorLogVmcsCtls(VMCPUID idCpu, PCVMXVMCSINFO pVmcsInfo)
2885	{
2886	LogRel(("HM: CPU[%u] PinCtls %#RX32\n", idCpu, pVmcsInfo->u32PinCtls));
2887	{
2888	uint32_t const u32Val = pVmcsInfo->u32PinCtls;
2889	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
2890	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
2891	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
2892	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
2893	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
2894	}
2895	LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls));
2896	{
2897	uint32_t const u32Val = pVmcsInfo->u32ProcCtls;
2898	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
2899	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
2900	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
2901	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
2902	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
2903	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
2904	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
2905	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
2906	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
2907	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
2908	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
2909	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
2910	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
2911	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
2912	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
2913	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
2914	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
2915	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
2916	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
2917	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
2918	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
2919	}
2920	LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls2));
2921	{
2922	uint32_t const u32Val = pVmcsInfo->u32ProcCtls2;
2923	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
2924	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
2925	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
2926	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
2927	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
2928	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
2929	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
2930	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST );
2931	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
2932	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
2933	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
2934	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
2935	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
2936	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
2937	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
2938	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
2939	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
2940	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
2941	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_VE );
2942	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
2943	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
2944	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
2945	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_SPPTP_EPT );
2946	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PT_EPT );
2947	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
2948	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_USER_WAIT_PAUSE );
2949	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLV_EXIT );
2950	}
2951	LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", idCpu, pVmcsInfo->u32EntryCtls));
2952	{
2953	uint32_t const u32Val = pVmcsInfo->u32EntryCtls;
2954	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
2955	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
2956	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
2957	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
2958	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
2959	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
2960	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
2961	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR );
2962	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
2963	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR );
2964	}
2965	LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", idCpu, pVmcsInfo->u32ExitCtls));
2966	{
2967	uint32_t const u32Val = pVmcsInfo->u32ExitCtls;
2968	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
2969	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
2970	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
2971	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
2972	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
2973	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
2974	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
2975	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
2976	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
2977	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR );
2978	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT );
2979	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR );
2980	}
2981	}
2982	#endif
2983
2984
2985	/**
2986	* Check fatal VT-x/AMD-V error and produce some meaningful
2987	* log release message.
2988	*
2989	* @param pVM The cross context VM structure.
2990	* @param iStatusCode VBox status code.
2991	*/
2992	VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2993	{
2994	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2995	{
2996	/** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
2997	* might be getting inaccurate values for non-guru'ing EMTs. */
2998	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2999	#ifdef TODO_9217_VMCSINFO
3000	PCVMXVMCSINFOSHARED pVmcsInfo = hmGetVmxActiveVmcsInfoShared(pVCpu);
3001	#endif
3002	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3003	switch (iStatusCode)
3004	{
3005	case VERR_VMX_INVALID_VMCS_PTR:
3006	{
3007	LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3008	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3009	#ifdef TODO_9217_VMCSINFO
3010	LogRel(("HM: CPU[%u] Current pointer %#RHp vs %#RHp\n", idCpu, pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs,
3011	pVmcsInfo->HCPhysVmcs));
3012	#endif
3013	LogRel(("HM: CPU[%u] Current VMCS version %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
3014	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3015	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3016	break;
3017	}
3018
3019	case VERR_VMX_UNABLE_TO_START_VM:
3020	{
3021	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3022	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3023	LogRel(("HM: CPU[%u] Instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
3024	LogRel(("HM: CPU[%u] Exit reason %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3025
3026	if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
3027	\|\| pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
3028	{
3029	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3030	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3031	}
3032	else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
3033	{
3034	#ifdef TODO_9217_VMCSINFO
3035	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3036	LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
3037	LogRel(("HM: CPU[%u] HCPhysGuestMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrLoad));
3038	LogRel(("HM: CPU[%u] HCPhysGuestMsrStore %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrStore));
3039	LogRel(("HM: CPU[%u] HCPhysHostMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysHostMsrLoad));
3040	LogRel(("HM: CPU[%u] cEntryMsrLoad %u\n", idCpu, pVmcsInfo->cEntryMsrLoad));
3041	LogRel(("HM: CPU[%u] cExitMsrStore %u\n", idCpu, pVmcsInfo->cExitMsrStore));
3042	LogRel(("HM: CPU[%u] cExitMsrLoad %u\n", idCpu, pVmcsInfo->cExitMsrLoad));
3043	#endif
3044	}
3045	/** @todo Log VM-entry event injection control fields
3046	* VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3047	* and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3048	break;
3049	}
3050
3051	case VERR_VMX_INVALID_GUEST_STATE:
3052	{
3053	LogRel(("HM: VERR_VMX_INVALID_GUEST_STATE:\n"));
3054	LogRel(("HM: CPU[%u] HM error = %#RX32\n", idCpu, pVCpu->hm.s.u32HMError));
3055	LogRel(("HM: CPU[%u] Guest-intr. state = %#RX32\n", idCpu, pVCpu->hm.s.vmx.LastError.u32GuestIntrState));
3056	#ifdef TODO_9217_VMCSINFO
3057	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3058	#endif
3059	break;
3060	}
3061
3062	/* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3063	case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3064	case VERR_VMX_INVALID_VMXON_PTR:
3065	case VERR_VMX_UNEXPECTED_EXIT:
3066	case VERR_VMX_INVALID_VMCS_FIELD:
3067	case VERR_SVM_UNKNOWN_EXIT:
3068	case VERR_SVM_UNEXPECTED_EXIT:
3069	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3070	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3071	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3072	break;
3073	}
3074	}
3075
3076	if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3077	{
3078	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed1));
3079	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed0));
3080	}
3081	else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3082	LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.ForR3.vmx.HCPhysVmxEnableError));
3083	}
3084
3085
3086	/**
3087	* Execute state save operation.
3088	*
3089	* Save only data that cannot be re-loaded while entering HM ring-0 code. This
3090	* is because we always save the VM state from ring-3 and thus most HM state
3091	* will be re-synced dynamically at runtime and don't need to be part of the VM
3092	* saved state.
3093	*
3094	* @returns VBox status code.
3095	* @param pVM The cross context VM structure.
3096	* @param pSSM SSM operation handle.
3097	*/
3098	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3099	{
3100	Log(("hmR3Save:\n"));
3101
3102	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3103	{
3104	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3105	Assert(!pVCpu->hm.s.Event.fPending);
3106	if (pVM->cpum.ro.GuestFeatures.fSvm)
3107	{
3108	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3109	SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3110	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3111	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3112	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3113	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3114	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3115	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3116	SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3117	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3118	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3119	SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3120	SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3121	SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3122	}
3123	}
3124
3125	/* Save the guest patch data. */
3126	SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3127	SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3128	SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3129
3130	/* Store all the guest patch records too. */
3131	int rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3132	if (RT_FAILURE(rc))
3133	return rc;
3134
3135	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3136	{
3137	AssertCompileSize(HMTPRINSTR, 4);
3138	PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3139	SSMR3PutU32(pSSM, pPatch->Core.Key);
3140	SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3141	SSMR3PutU32(pSSM, pPatch->cbOp);
3142	SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3143	SSMR3PutU32(pSSM, pPatch->cbNewOp);
3144	SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3145	SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3146	SSMR3PutU32(pSSM, pPatch->uDstOperand);
3147	SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3148	rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3149	if (RT_FAILURE(rc))
3150	return rc;
3151	}
3152
3153	return VINF_SUCCESS;
3154	}
3155
3156
3157	/**
3158	* Execute state load operation.
3159	*
3160	* @returns VBox status code.
3161	* @param pVM The cross context VM structure.
3162	* @param pSSM SSM operation handle.
3163	* @param uVersion Data layout version.
3164	* @param uPass The data pass.
3165	*/
3166	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3167	{
3168	int rc;
3169
3170	LogFlowFunc(("uVersion=%u\n", uVersion));
3171	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3172
3173	/*
3174	* Validate version.
3175	*/
3176	if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3177	&& uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3178	&& uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3179	&& uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3180	{
3181	AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3182	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3183	}
3184
3185	/*
3186	* Load per-VCPU state.
3187	*/
3188	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3189	{
3190	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3191	if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3192	{
3193	/* Load the SVM nested hw.virt state if the VM is configured for it. */
3194	if (pVM->cpum.ro.GuestFeatures.fSvm)
3195	{
3196	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3197	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3198	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3199	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3200	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3201	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3202	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3203	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3204	SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3205	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3206	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3207	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3208	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3209	rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3210	AssertRCReturn(rc, rc);
3211	}
3212	}
3213	else
3214	{
3215	/* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3216	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.fPending);
3217	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.u32ErrCode);
3218	SSMR3GetU64(pSSM, &pVCpu->hm.s.Event.u64IntInfo);
3219
3220	/* VMX fWasInRealMode related data. */
3221	uint32_t uDummy;
3222	SSMR3GetU32(pSSM, &uDummy);
3223	SSMR3GetU32(pSSM, &uDummy);
3224	rc = SSMR3GetU32(pSSM, &uDummy);
3225	AssertRCReturn(rc, rc);
3226	}
3227	}
3228
3229	/*
3230	* Load TPR patching data.
3231	*/
3232	if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3233	{
3234	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3235	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3236	SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3237
3238	/* Fetch all TPR patch records. */
3239	rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3240	AssertRCReturn(rc, rc);
3241	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3242	{
3243	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3244	SSMR3GetU32(pSSM, &pPatch->Core.Key);
3245	SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3246	SSMR3GetU32(pSSM, &pPatch->cbOp);
3247	SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3248	SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3249	SSM_GET_ENUM32_RET(pSSM, pPatch->enmType, HMTPRINSTR);
3250
3251	if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3252	pVM->hm.s.fTprPatchingActive = true;
3253	Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT \|\| pVM->hm.s.fTprPatchingActive == false);
3254
3255	SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3256	SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3257	SSMR3GetU32(pSSM, &pPatch->cFaults);
3258	rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3259	AssertRCReturn(rc, rc);
3260
3261	LogFlow(("hmR3Load: patch %d\n", i));
3262	LogFlow(("Key = %x\n", pPatch->Core.Key));
3263	LogFlow(("cbOp = %d\n", pPatch->cbOp));
3264	LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3265	LogFlow(("type = %d\n", pPatch->enmType));
3266	LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3267	LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3268	LogFlow(("cFaults = %d\n", pPatch->cFaults));
3269	LogFlow(("target = %x\n", pPatch->pJumpTarget));
3270
3271	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3272	AssertRCReturn(rc, rc);
3273	}
3274	}
3275
3276	return VINF_SUCCESS;
3277	}
3278
3279
3280	/**
3281	* Displays HM info.
3282	*
3283	* @param pVM The cross context VM structure.
3284	* @param pHlp The info helper functions.
3285	* @param pszArgs Arguments, ignored.
3286	*/
3287	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3288	{
3289	NOREF(pszArgs);
3290	PVMCPU pVCpu = VMMGetCpu(pVM);
3291	if (!pVCpu)
3292	pVCpu = pVM->apCpusR3[0];
3293
3294	if (HMIsEnabled(pVM))
3295	{
3296	if (pVM->hm.s.vmx.fSupported)
3297	pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3298	else
3299	pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3300	pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3301	pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3302	if (pVM->hm.s.vmx.fSupported)
3303	{
3304	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3305	bool const fRealOnV86Active = pVmcsInfoShared->RealMode.fRealOnV86Active;
3306	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3307
3308	pHlp->pfnPrintf(pHlp, " %s VMCS active\n", fNstGstVmcsActive ? "Nested-guest" : "Guest");
3309	pHlp->pfnPrintf(pHlp, " Real-on-v86 active = %RTbool\n", fRealOnV86Active);
3310	if (fRealOnV86Active)
3311	{
3312	pHlp->pfnPrintf(pHlp, " EFlags = %#x\n", pVmcsInfoShared->RealMode.Eflags.u32);
3313	pHlp->pfnPrintf(pHlp, " Attr CS = %#x\n", pVmcsInfoShared->RealMode.AttrCS.u);
3314	pHlp->pfnPrintf(pHlp, " Attr SS = %#x\n", pVmcsInfoShared->RealMode.AttrSS.u);
3315	pHlp->pfnPrintf(pHlp, " Attr DS = %#x\n", pVmcsInfoShared->RealMode.AttrDS.u);
3316	pHlp->pfnPrintf(pHlp, " Attr ES = %#x\n", pVmcsInfoShared->RealMode.AttrES.u);
3317	pHlp->pfnPrintf(pHlp, " Attr FS = %#x\n", pVmcsInfoShared->RealMode.AttrFS.u);
3318	pHlp->pfnPrintf(pHlp, " Attr GS = %#x\n", pVmcsInfoShared->RealMode.AttrGS.u);
3319	}
3320	}
3321	}
3322	else
3323	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3324	}
3325
3326
3327	/**
3328	* Displays the HM Last-Branch-Record info. for the guest.
3329	*
3330	* @param pVM The cross context VM structure.
3331	* @param pHlp The info helper functions.
3332	* @param pszArgs Arguments, ignored.
3333	*/
3334	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3335	{
3336	NOREF(pszArgs);
3337	PVMCPU pVCpu = VMMGetCpu(pVM);
3338	if (!pVCpu)
3339	pVCpu = pVM->apCpusR3[0];
3340
3341	if (!HMIsEnabled(pVM))
3342	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3343
3344	if (HMIsVmxActive(pVM))
3345	{
3346	if (pVM->hm.s.vmx.fLbrCfg)
3347	{
3348	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3349	uint32_t const cLbrStack = pVM->hm.s.ForR3.vmx.idLbrFromIpMsrLast - pVM->hm.s.ForR3.vmx.idLbrFromIpMsrFirst + 1;
3350
3351	/** @todo r=ramshankar: The index technically varies depending on the CPU, but
3352	* 0xf should cover everything we support thus far. Fix if necessary
3353	* later. */
3354	uint32_t const idxTopOfStack = pVmcsInfoShared->u64LbrTosMsr & 0xf;
3355	if (idxTopOfStack > cLbrStack)
3356	{
3357	pHlp->pfnPrintf(pHlp, "Top-of-stack LBR MSR seems corrupt (index=%u, msr=%#RX64) expected index < %u\n",
3358	idxTopOfStack, pVmcsInfoShared->u64LbrTosMsr, cLbrStack);
3359	return;
3360	}
3361
3362	/*
3363	* Dump the circular buffer of LBR records starting from the most recent record (contained in idxTopOfStack).
3364	*/
3365	pHlp->pfnPrintf(pHlp, "CPU[%u]: LBRs (most-recent first)\n", pVCpu->idCpu);
3366	uint32_t idxCurrent = idxTopOfStack;
3367	Assert(idxTopOfStack < cLbrStack);
3368	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrFromIpMsr) <= cLbrStack);
3369	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrToIpMsr) <= cLbrStack);
3370	for (;;)
3371	{
3372	if (pVM->hm.s.ForR3.vmx.idLbrToIpMsrFirst)
3373	pHlp->pfnPrintf(pHlp, " Branch (%2u): From IP=%#016RX64 - To IP=%#016RX64\n", idxCurrent,
3374	pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent], pVmcsInfoShared->au64LbrToIpMsr[idxCurrent]);
3375	else
3376	pHlp->pfnPrintf(pHlp, " Branch (%2u): LBR=%#RX64\n", idxCurrent, pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent]);
3377
3378	idxCurrent = (idxCurrent - 1) % cLbrStack;
3379	if (idxCurrent == idxTopOfStack)
3380	break;
3381	}
3382	}
3383	else
3384	pHlp->pfnPrintf(pHlp, "VM not configured to record LBRs for the guest\n");
3385	}
3386	else
3387	{
3388	Assert(HMIsSvmActive(pVM));
3389	/** @todo SVM: LBRs (get them from VMCB if possible). */
3390	pHlp->pfnPrintf(pHlp, "SVM LBR not implemented in VM debugger yet\n");
3391	}
3392	}
3393
3394
3395	/**
3396	* Displays the HM pending event.
3397	*
3398	* @param pVM The cross context VM structure.
3399	* @param pHlp The info helper functions.
3400	* @param pszArgs Arguments, ignored.
3401	*/
3402	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3403	{
3404	NOREF(pszArgs);
3405	PVMCPU pVCpu = VMMGetCpu(pVM);
3406	if (!pVCpu)
3407	pVCpu = pVM->apCpusR3[0];
3408
3409	if (HMIsEnabled(pVM))
3410	{
3411	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3412	if (pVCpu->hm.s.Event.fPending)
3413	{
3414	pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3415	pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3416	pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3417	pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3418	}
3419	}
3420	else
3421	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3422	}
3423
3424
3425	/**
3426	* Displays the SVM nested-guest VMCB cache.
3427	*
3428	* @param pVM The cross context VM structure.
3429	* @param pHlp The info helper functions.
3430	* @param pszArgs Arguments, ignored.
3431	*/
3432	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3433	{
3434	NOREF(pszArgs);
3435	PVMCPU pVCpu = VMMGetCpu(pVM);
3436	if (!pVCpu)
3437	pVCpu = pVM->apCpusR3[0];
3438
3439	bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3440	if ( fSvmEnabled
3441	&& pVM->cpum.ro.GuestFeatures.fSvm)
3442	{
3443	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3444	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3445	pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3446	pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3447	pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3448	pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3449	pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3450	pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3451	pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3452	pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3453	pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3454	pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3455	pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3456	pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3457	pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3458	}
3459	else
3460	{
3461	if (!fSvmEnabled)
3462	pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3463	else
3464	pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3465	}
3466	}
3467

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 90439

Download in other formats: