HM.cpp@ 86473

Last change on this file since 86473 was 86183, checked in by vboxsync, 4 years ago
VMM: Implemented sysenter and sysexit in IEM (limited testing). Added an longmode emulation of sysenter/sysexit to SVM.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 155.4 KB

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1	/* $Id: HM.cpp 86183 2020-09-20 11:58:23Z vboxsync $ */
2	/** @file
3	* HM - Intel/AMD VM Hardware Support Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19	*
20	* The HM manages guest execution using the VT-x and AMD-V CPU hardware
21	* extensions.
22	*
23	* {summary of what HM does}
24	*
25	* Hardware assisted virtualization manager was originally abbreviated HWACCM,
26	* however that was cumbersome to write and parse for such a central component,
27	* so it was shortened to HM when refactoring the code in the 4.3 development
28	* cycle.
29	*
30	* {add sections with more details}
31	*
32	* @sa @ref grp_hm
33	*/
34
35
36	/*********************************************************************************************************************************
37	* Header Files *
38	*********************************************************************************************************************************/
39	#define LOG_GROUP LOG_GROUP_HM
40	#define VMCPU_INCL_CPUM_GST_CTX
41	#include <VBox/vmm/cpum.h>
42	#include <VBox/vmm/stam.h>
43	#include <VBox/vmm/mm.h>
44	#include <VBox/vmm/em.h>
45	#include <VBox/vmm/pdmapi.h>
46	#include <VBox/vmm/pgm.h>
47	#include <VBox/vmm/ssm.h>
48	#include <VBox/vmm/gim.h>
49	#include <VBox/vmm/trpm.h>
50	#include <VBox/vmm/dbgf.h>
51	#include <VBox/vmm/iom.h>
52	#include <VBox/vmm/iem.h>
53	#include <VBox/vmm/selm.h>
54	#include <VBox/vmm/nem.h>
55	#include <VBox/vmm/hm_vmx.h>
56	#include <VBox/vmm/hm_svm.h>
57	#include "HMInternal.h"
58	#include <VBox/vmm/vmcc.h>
59	#include <VBox/err.h>
60	#include <VBox/param.h>
61
62	#include <iprt/assert.h>
63	#include <VBox/log.h>
64	#include <iprt/asm.h>
65	#include <iprt/asm-amd64-x86.h>
66	#include <iprt/env.h>
67	#include <iprt/thread.h>
68
69
70	/*********************************************************************************************************************************
71	* Defined Constants And Macros *
72	*********************************************************************************************************************************/
73	/** @def HMVMX_REPORT_FEAT
74	* Reports VT-x feature to the release log.
75	*
76	* @param a_uAllowed1 Mask of allowed-1 feature bits.
77	* @param a_uAllowed0 Mask of allowed-0 feature bits.
78	* @param a_StrDesc The description string to report.
79	* @param a_Featflag Mask of the feature to report.
80	*/
81	#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
82	do { \
83	if ((a_uAllowed1) & (a_Featflag)) \
84	{ \
85	if ((a_uAllowed0) & (a_Featflag)) \
86	LogRel(("HM: " a_StrDesc " (must be set)\n")); \
87	else \
88	LogRel(("HM: " a_StrDesc "\n")); \
89	} \
90	else \
91	LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
92	} while (0)
93
94	/** @def HMVMX_REPORT_ALLOWED_FEAT
95	* Reports an allowed VT-x feature to the release log.
96	*
97	* @param a_uAllowed1 Mask of allowed-1 feature bits.
98	* @param a_StrDesc The description string to report.
99	* @param a_FeatFlag Mask of the feature to report.
100	*/
101	#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
102	do { \
103	if ((a_uAllowed1) & (a_FeatFlag)) \
104	LogRel(("HM: " a_StrDesc "\n")); \
105	else \
106	LogRel(("HM: " a_StrDesc " not supported\n")); \
107	} while (0)
108
109	/** @def HMVMX_REPORT_MSR_CAP
110	* Reports MSR feature capability.
111	*
112	* @param a_MsrCaps Mask of MSR feature bits.
113	* @param a_StrDesc The description string to report.
114	* @param a_fCap Mask of the feature to report.
115	*/
116	#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
117	do { \
118	if ((a_MsrCaps) & (a_fCap)) \
119	LogRel(("HM: " a_StrDesc "\n")); \
120	} while (0)
121
122	/** @def HMVMX_LOGREL_FEAT
123	* Dumps a feature flag from a bitmap of features to the release log.
124	*
125	* @param a_fVal The value of all the features.
126	* @param a_fMask The specific bitmask of the feature.
127	*/
128	#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
129	do { \
130	if ((a_fVal) & (a_fMask)) \
131	LogRel(("HM: %s\n", #a_fMask)); \
132	} while (0)
133
134
135	/*********************************************************************************************************************************
136	* Internal Functions *
137	*********************************************************************************************************************************/
138	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
139	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
140	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
141	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
142	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
143	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
144	static int hmR3InitFinalizeR3(PVM pVM);
145	static int hmR3InitFinalizeR0(PVM pVM);
146	static int hmR3InitFinalizeR0Intel(PVM pVM);
147	static int hmR3InitFinalizeR0Amd(PVM pVM);
148	static int hmR3TermCPU(PVM pVM);
149
150
151	#ifdef VBOX_WITH_STATISTICS
152	/**
153	* Returns the name of the hardware exception.
154	*
155	* @returns The name of the hardware exception.
156	* @param uVector The exception vector.
157	*/
158	static const char *hmR3GetXcptName(uint8_t uVector)
159	{
160	switch (uVector)
161	{
162	case X86_XCPT_DE: return "#DE";
163	case X86_XCPT_DB: return "#DB";
164	case X86_XCPT_NMI: return "#NMI";
165	case X86_XCPT_BP: return "#BP";
166	case X86_XCPT_OF: return "#OF";
167	case X86_XCPT_BR: return "#BR";
168	case X86_XCPT_UD: return "#UD";
169	case X86_XCPT_NM: return "#NM";
170	case X86_XCPT_DF: return "#DF";
171	case X86_XCPT_CO_SEG_OVERRUN: return "#CO_SEG_OVERRUN";
172	case X86_XCPT_TS: return "#TS";
173	case X86_XCPT_NP: return "#NP";
174	case X86_XCPT_SS: return "#SS";
175	case X86_XCPT_GP: return "#GP";
176	case X86_XCPT_PF: return "#PF";
177	case X86_XCPT_MF: return "#MF";
178	case X86_XCPT_AC: return "#AC";
179	case X86_XCPT_MC: return "#MC";
180	case X86_XCPT_XF: return "#XF";
181	case X86_XCPT_VE: return "#VE";
182	case X86_XCPT_CP: return "#CP";
183	case X86_XCPT_VC: return "#VC";
184	case X86_XCPT_SX: return "#SX";
185	}
186	return "Reserved";
187	}
188	#endif /* VBOX_WITH_STATISTICS */
189
190
191	/**
192	* Initializes the HM.
193	*
194	* This is the very first component to really do init after CFGM so that we can
195	* establish the predominant execution engine for the VM prior to initializing
196	* other modules. It takes care of NEM initialization if needed (HM disabled or
197	* not available in HW).
198	*
199	* If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
200	* hypervisor API via NEM, and then back on raw-mode if that isn't available
201	* either. The fallback to raw-mode will not happen if /HM/HMForced is set
202	* (like for guest using SMP or 64-bit as well as for complicated guest like OS
203	* X, OS/2 and others).
204	*
205	* Note that a lot of the set up work is done in ring-0 and thus postponed till
206	* the ring-3 and ring-0 callback to HMR3InitCompleted.
207	*
208	* @returns VBox status code.
209	* @param pVM The cross context VM structure.
210	*
211	* @remarks Be careful with what we call here, since most of the VMM components
212	* are uninitialized.
213	*/
214	VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
215	{
216	LogFlowFunc(("\n"));
217
218	/*
219	* Assert alignment and sizes.
220	*/
221	AssertCompileMemberAlignment(VM, hm.s, 32);
222	AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
223
224	/*
225	* Register the saved state data unit.
226	*/
227	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
228	NULL, NULL, NULL,
229	NULL, hmR3Save, NULL,
230	NULL, hmR3Load, NULL);
231	if (RT_FAILURE(rc))
232	return rc;
233
234	/*
235	* Register info handlers.
236	*/
237	rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
238	AssertRCReturn(rc, rc);
239
240	rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
241	DBGFINFO_FLAGS_ALL_EMTS);
242	AssertRCReturn(rc, rc);
243
244	rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
245	hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
246	AssertRCReturn(rc, rc);
247
248	rc = DBGFR3InfoRegisterInternalEx(pVM, "lbr", "Dumps the HM LBR info.", hmR3InfoLbr, DBGFINFO_FLAGS_ALL_EMTS);
249	AssertRCReturn(rc, rc);
250
251	/*
252	* Read configuration.
253	*/
254	PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
255
256	/*
257	* Validate the HM settings.
258	*/
259	rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
260	"HMForced" /* implied 'true' these days */
261	"\|UseNEMInstead"
262	"\|FallbackToNEM"
263	"\|EnableNestedPaging"
264	"\|EnableUX"
265	"\|EnableLargePages"
266	"\|EnableVPID"
267	"\|IBPBOnVMExit"
268	"\|IBPBOnVMEntry"
269	"\|SpecCtrlByHost"
270	"\|L1DFlushOnSched"
271	"\|L1DFlushOnVMEntry"
272	"\|MDSClearOnSched"
273	"\|MDSClearOnVMEntry"
274	"\|TPRPatchingEnabled"
275	"\|64bitEnabled"
276	"\|Exclusive"
277	"\|MaxResumeLoops"
278	"\|VmxPleGap"
279	"\|VmxPleWindow"
280	"\|VmxLbr"
281	"\|UseVmxPreemptTimer"
282	"\|SvmPauseFilter"
283	"\|SvmPauseFilterThreshold"
284	"\|SvmVirtVmsaveVmload"
285	"\|SvmVGif"
286	"\|LovelyMesaDrvWorkaround",
287	"" /* pszValidNodes /, "HM" / pszWho /, 0 / uInstance */);
288	if (RT_FAILURE(rc))
289	return rc;
290
291	/** @cfgm{/HM/HMForced, bool, false}
292	* Forces hardware virtualization, no falling back on raw-mode. HM must be
293	* enabled, i.e. /HMEnabled must be true. */
294	bool fHMForced;
295	AssertRelease(pVM->fHMEnabled);
296	fHMForced = true;
297
298	/** @cfgm{/HM/UseNEMInstead, bool, true}
299	* Don't use HM, use NEM instead. */
300	bool fUseNEMInstead = false;
301	rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
302	AssertRCReturn(rc, rc);
303	if (fUseNEMInstead && pVM->fHMEnabled)
304	{
305	LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
306	pVM->fHMEnabled = false;
307	}
308
309	/** @cfgm{/HM/FallbackToNEM, bool, true}
310	* Enables fallback on NEM. */
311	bool fFallbackToNEM = true;
312	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
313	AssertRCReturn(rc, rc);
314
315	/** @cfgm{/HM/EnableNestedPaging, bool, false}
316	* Enables nested paging (aka extended page tables). */
317	bool fAllowNestedPaging = false;
318	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &fAllowNestedPaging, false);
319	AssertRCReturn(rc, rc);
320
321	/** @cfgm{/HM/EnableUX, bool, true}
322	* Enables the VT-x unrestricted execution feature. */
323	bool fAllowUnrestricted = true;
324	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &fAllowUnrestricted, true);
325	AssertRCReturn(rc, rc);
326
327	/** @cfgm{/HM/EnableLargePages, bool, false}
328	* Enables using large pages (2 MB) for guest memory, thus saving on (nested)
329	* page table walking and maybe better TLB hit rate in some cases. */
330	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
331	AssertRCReturn(rc, rc);
332
333	/** @cfgm{/HM/EnableVPID, bool, false}
334	* Enables the VT-x VPID feature. */
335	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
336	AssertRCReturn(rc, rc);
337
338	/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
339	* Enables TPR patching for 32-bit windows guests with IO-APIC. */
340	rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
341	AssertRCReturn(rc, rc);
342
343	/** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
344	* Enables AMD64 cpu features.
345	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
346	* already have the support. */
347	#ifdef VBOX_WITH_64_BITS_GUESTS
348	rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
349	AssertLogRelRCReturn(rc, rc);
350	#else
351	pVM->hm.s.fAllow64BitGuests = false;
352	#endif
353
354	/** @cfgm{/HM/VmxPleGap, uint32_t, 0}
355	* The pause-filter exiting gap in TSC ticks. When the number of ticks between
356	* two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
357	* latest PAUSE instruction to be start of a new PAUSE loop.
358	*/
359	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
360	AssertRCReturn(rc, rc);
361
362	/** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
363	* The pause-filter exiting window in TSC ticks. When the number of ticks
364	* between the current PAUSE instruction and first PAUSE of a loop exceeds
365	* VmxPleWindow, a VM-exit is triggered.
366	*
367	* Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
368	*/
369	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
370	AssertRCReturn(rc, rc);
371
372	/** @cfgm{/HM/VmxLbr, bool, false}
373	* Whether to enable LBR for the guest. This is disabled by default as it's only
374	* useful while debugging and enabling it causes a noticeable performance hit. */
375	rc = CFGMR3QueryBoolDef(pCfgHm, "VmxLbr", &pVM->hm.s.vmx.fLbr, false);
376	AssertRCReturn(rc, rc);
377
378	/** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
379	* A counter that is decrement each time a PAUSE instruction is executed by the
380	* guest. When the counter is 0, a \#VMEXIT is triggered.
381	*
382	* Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
383	*/
384	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
385	AssertRCReturn(rc, rc);
386
387	/** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
388	* The pause filter threshold in ticks. When the elapsed time (in ticks) between
389	* two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
390	* PauseFilter count is reset to its initial value. However, if PAUSE is
391	* executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
392	* be triggered.
393	*
394	* Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
395	* activated.
396	*/
397	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
398	AssertRCReturn(rc, rc);
399
400	/** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
401	* Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
402	* available. */
403	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
404	AssertRCReturn(rc, rc);
405
406	/** @cfgm{/HM/SvmVGif, bool, true}
407	* Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
408	* if it's available. */
409	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
410	AssertRCReturn(rc, rc);
411
412	/** @cfgm{/HM/SvmLbrVirt, bool, false}
413	* Whether to make use of the LBR virtualization feature of the CPU if it's
414	* available. This is disabled by default as it's only useful while debugging
415	* and enabling it causes a small hit to performance. */
416	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmLbrVirt", &pVM->hm.s.svm.fLbrVirt, false);
417	AssertRCReturn(rc, rc);
418
419	/** @cfgm{/HM/Exclusive, bool}
420	* Determines the init method for AMD-V and VT-x. If set to true, HM will do a
421	* global init for each host CPU. If false, we do local init each time we wish
422	* to execute guest code.
423	*
424	* On Windows, default is false due to the higher risk of conflicts with other
425	* hypervisors.
426	*
427	* On Mac OS X, this setting is ignored since the code does not handle local
428	* init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
429	*/
430	#if defined(RT_OS_DARWIN)
431	pVM->hm.s.fGlobalInit = true;
432	#else
433	rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
434	# if defined(RT_OS_WINDOWS)
435	false
436	# else
437	true
438	# endif
439	);
440	AssertLogRelRCReturn(rc, rc);
441	#endif
442
443	/** @cfgm{/HM/MaxResumeLoops, uint32_t}
444	* The number of times to resume guest execution before we forcibly return to
445	* ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
446	* determines the default value. */
447	rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
448	AssertLogRelRCReturn(rc, rc);
449
450	/** @cfgm{/HM/UseVmxPreemptTimer, bool}
451	* Whether to make use of the VMX-preemption timer feature of the CPU if it's
452	* available. */
453	rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
454	AssertLogRelRCReturn(rc, rc);
455
456	/** @cfgm{/HM/IBPBOnVMExit, bool}
457	* Costly paranoia setting. */
458	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
459	AssertLogRelRCReturn(rc, rc);
460
461	/** @cfgm{/HM/IBPBOnVMEntry, bool}
462	* Costly paranoia setting. */
463	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
464	AssertLogRelRCReturn(rc, rc);
465
466	/** @cfgm{/HM/L1DFlushOnSched, bool, true}
467	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
468	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
469	AssertLogRelRCReturn(rc, rc);
470
471	/** @cfgm{/HM/L1DFlushOnVMEntry, bool}
472	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
473	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
474	AssertLogRelRCReturn(rc, rc);
475
476	/* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
477	if (pVM->hm.s.fL1dFlushOnVmEntry)
478	pVM->hm.s.fL1dFlushOnSched = false;
479
480	/** @cfgm{/HM/SpecCtrlByHost, bool}
481	* Another expensive paranoia setting. */
482	rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
483	AssertLogRelRCReturn(rc, rc);
484
485	/** @cfgm{/HM/MDSClearOnSched, bool, true}
486	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
487	* ignored on CPUs that aren't affected. */
488	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
489	AssertLogRelRCReturn(rc, rc);
490
491	/** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
492	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
493	* ignored on CPUs that aren't affected. */
494	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
495	AssertLogRelRCReturn(rc, rc);
496
497	/* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
498	if (pVM->hm.s.fMdsClearOnVmEntry)
499	pVM->hm.s.fMdsClearOnSched = false;
500
501	/** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
502	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
503	* the hypervisor it is running under. */
504	bool f;
505	rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &f, false);
506	AssertLogRelRCReturn(rc, rc);
507	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
508	{
509	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
510	pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv = f;
511	}
512
513	/*
514	* Check if VT-x or AMD-v support according to the users wishes.
515	*/
516	/** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
517	* VERR_SVM_IN_USE. */
518	if (pVM->fHMEnabled)
519	{
520	uint32_t fCaps;
521	rc = SUPR3QueryVTCaps(&fCaps);
522	if (RT_SUCCESS(rc))
523	{
524	if (fCaps & SUPVTCAPS_AMD_V)
525	{
526	pVM->hm.s.svm.fSupported = true;
527	LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
528	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
529	}
530	else if (fCaps & SUPVTCAPS_VT_X)
531	{
532	const char *pszWhy;
533	rc = SUPR3QueryVTxSupported(&pszWhy);
534	if (RT_SUCCESS(rc))
535	{
536	pVM->hm.s.vmx.fSupported = true;
537	LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
538	fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
539	fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
540	(fCaps & (SUPVTCAPS_NESTED_PAGING \| SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
541	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
542	}
543	else
544	{
545	/*
546	* Before failing, try fallback to NEM if we're allowed to do that.
547	*/
548	pVM->fHMEnabled = false;
549	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
550	if (fFallbackToNEM)
551	{
552	LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
553	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
554
555	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
556	if ( RT_SUCCESS(rc2)
557	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
558	rc = VINF_SUCCESS;
559	}
560	if (RT_FAILURE(rc))
561	return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
562	}
563	}
564	else
565	AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
566	VERR_INTERNAL_ERROR_5);
567
568	/*
569	* Disable nested paging and unrestricted guest execution now if they're
570	* configured so that CPUM can make decisions based on our configuration.
571	*/
572	if ( fAllowNestedPaging
573	&& (fCaps & SUPVTCAPS_NESTED_PAGING))
574	{
575	pVM->hm.s.fNestedPaging = true;
576	if (fCaps & SUPVTCAPS_VT_X)
577	{
578	if ( fAllowUnrestricted
579	&& (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST))
580	pVM->hm.s.vmx.fUnrestrictedGuest = true;
581	else
582	Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
583	}
584	}
585	else
586	Assert(!pVM->hm.s.fNestedPaging);
587	}
588	else
589	{
590	const char *pszMsg;
591	switch (rc)
592	{
593	case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
594	case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
595	case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
596	case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
597	case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
598	case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
599	case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
600	default:
601	return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
602	}
603
604	/*
605	* Before failing, try fallback to NEM if we're allowed to do that.
606	*/
607	pVM->fHMEnabled = false;
608	if (fFallbackToNEM)
609	{
610	LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
611	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
612	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
613	if ( RT_SUCCESS(rc2)
614	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
615	rc = VINF_SUCCESS;
616	}
617	if (RT_FAILURE(rc))
618	return VM_SET_ERROR(pVM, rc, pszMsg);
619	}
620	}
621	else
622	{
623	/*
624	* Disabled HM mean raw-mode, unless NEM is supposed to be used.
625	*/
626	if (fUseNEMInstead)
627	{
628	rc = NEMR3Init(pVM, false /fFallback/, true);
629	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
630	if (RT_FAILURE(rc))
631	return rc;
632	}
633	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET
634	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE
635	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT /* paranoia */)
636	return VM_SET_ERROR(pVM, rc, "Misconfigured VM: No guest execution engine available!");
637	}
638
639	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
640	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE);
641	return VINF_SUCCESS;
642	}
643
644
645	/**
646	* Initializes HM components after ring-3 phase has been fully initialized.
647	*
648	* @returns VBox status code.
649	* @param pVM The cross context VM structure.
650	*/
651	static int hmR3InitFinalizeR3(PVM pVM)
652	{
653	LogFlowFunc(("\n"));
654
655	if (!HMIsEnabled(pVM))
656	return VINF_SUCCESS;
657
658	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
659	{
660	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
661	pVCpu->hm.s.fActive = false;
662	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
663	}
664
665	#ifdef VBOX_WITH_STATISTICS
666	STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
667	STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
668	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8", STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
669	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC", STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
670	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
671	#endif
672
673	/*
674	* Statistics.
675	*/
676	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
677	{
678	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
679	PHMCPU pHmCpu = &pVCpu->hm.s;
680	int rc;
681
682	# define HM_REG_STAT(a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szNmFmt, a_szDesc) do { \
683	rc = STAMR3RegisterF(pVM, a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szDesc, a_szNmFmt, idCpu); \
684	AssertRC(rc); \
685	} while (0)
686	# define HM_REG_PROFILE(a_pVar, a_szNmFmt, a_szDesc) \
687	HM_REG_STAT(a_pVar, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, a_szNmFmt, a_szDesc)
688
689	#ifdef VBOX_WITH_STATISTICS
690
691	HM_REG_PROFILE(&pHmCpu->StatPoke, "/PROF/CPU%u/HM/Poke", "Profiling of RTMpPokeCpu.");
692	HM_REG_PROFILE(&pHmCpu->StatSpinPoke, "/PROF/CPU%u/HM/PokeWait", "Profiling of poke wait.");
693	HM_REG_PROFILE(&pHmCpu->StatSpinPokeFailed, "/PROF/CPU%u/HM/PokeWaitFailed", "Profiling of poke wait when RTMpPokeCpu fails.");
694	HM_REG_PROFILE(&pHmCpu->StatEntry, "/PROF/CPU%u/HM/Entry", "Profiling of entry until entering GC.");
695	HM_REG_PROFILE(&pHmCpu->StatPreExit, "/PROF/CPU%u/HM/SwitchFromGC_1", "Profiling of pre-exit processing after returning from GC.");
696	HM_REG_PROFILE(&pHmCpu->StatExitHandling, "/PROF/CPU%u/HM/SwitchFromGC_2", "Profiling of exit handling (longjmps not included!)");
697	HM_REG_PROFILE(&pHmCpu->StatExitIO, "/PROF/CPU%u/HM/SwitchFromGC_2/IO", "I/O.");
698	HM_REG_PROFILE(&pHmCpu->StatExitMovCRx, "/PROF/CPU%u/HM/SwitchFromGC_2/MovCRx", "MOV CRx.");
699	HM_REG_PROFILE(&pHmCpu->StatExitXcptNmi, "/PROF/CPU%u/HM/SwitchFromGC_2/XcptNmi", "Exceptions, NMIs.");
700	HM_REG_PROFILE(&pHmCpu->StatExitVmentry, "/PROF/CPU%u/HM/SwitchFromGC_2/Vmentry", "VMLAUNCH/VMRESUME on Intel or VMRUN on AMD.");
701	HM_REG_PROFILE(&pHmCpu->StatImportGuestState, "/PROF/CPU%u/HM/ImportGuestState", "Profiling of importing guest state from hardware after VM-exit.");
702	HM_REG_PROFILE(&pHmCpu->StatExportGuestState, "/PROF/CPU%u/HM/ExportGuestState", "Profiling of exporting guest state to hardware before VM-entry.");
703	HM_REG_PROFILE(&pHmCpu->StatLoadGuestFpuState, "/PROF/CPU%u/HM/LoadGuestFpuState", "Profiling of CPUMR0LoadGuestFPU.");
704	HM_REG_PROFILE(&pHmCpu->StatInGC, "/PROF/CPU%u/HM/InGC", "Profiling of execution of guest-code in hardware.");
705	# ifdef HM_PROFILE_EXIT_DISPATCH
706	HM_REG_STAT(&pHmCpu->StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
707	"/PROF/CPU%u/HM/ExitDispatch", "Profiling the dispatching of exit handlers.");
708	# endif
709	#endif
710	# define HM_REG_COUNTER(a, b, desc) HM_REG_STAT(a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, b, desc)
711
712	#ifdef VBOX_WITH_STATISTICS
713	HM_REG_COUNTER(&pHmCpu->StatExitAll, "/HM/CPU%u/Exit/All", "Total exits (including nested-guest exits).");
714	HM_REG_COUNTER(&pHmCpu->StatNestedExitAll, "/HM/CPU%u/Exit/NestedGuest/All", "Total nested-guest exits.");
715	HM_REG_COUNTER(&pHmCpu->StatExitShadowNM, "/HM/CPU%u/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
716	HM_REG_COUNTER(&pHmCpu->StatExitGuestNM, "/HM/CPU%u/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
717	HM_REG_COUNTER(&pHmCpu->StatExitShadowPF, "/HM/CPU%u/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
718	HM_REG_COUNTER(&pHmCpu->StatExitShadowPFEM, "/HM/CPU%u/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
719	HM_REG_COUNTER(&pHmCpu->StatExitGuestPF, "/HM/CPU%u/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
720	HM_REG_COUNTER(&pHmCpu->StatExitGuestUD, "/HM/CPU%u/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
721	HM_REG_COUNTER(&pHmCpu->StatExitGuestSS, "/HM/CPU%u/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
722	HM_REG_COUNTER(&pHmCpu->StatExitGuestNP, "/HM/CPU%u/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
723	HM_REG_COUNTER(&pHmCpu->StatExitGuestTS, "/HM/CPU%u/Exit/Trap/Gst/#TS", "Guest #TS (task switch) exception.");
724	HM_REG_COUNTER(&pHmCpu->StatExitGuestOF, "/HM/CPU%u/Exit/Trap/Gst/#OF", "Guest #OF (overflow) exception.");
725	HM_REG_COUNTER(&pHmCpu->StatExitGuestGP, "/HM/CPU%u/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
726	HM_REG_COUNTER(&pHmCpu->StatExitGuestDE, "/HM/CPU%u/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
727	HM_REG_COUNTER(&pHmCpu->StatExitGuestDF, "/HM/CPU%u/Exit/Trap/Gst/#DF", "Guest #DF (double fault) exception.");
728	HM_REG_COUNTER(&pHmCpu->StatExitGuestBR, "/HM/CPU%u/Exit/Trap/Gst/#BR", "Guest #BR (boundary range exceeded) exception.");
729	HM_REG_COUNTER(&pHmCpu->StatExitGuestAC, "/HM/CPU%u/Exit/Trap/Gst/#AC", "Guest #AC (alignment check) exception.");
730	HM_REG_COUNTER(&pHmCpu->StatExitGuestDB, "/HM/CPU%u/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
731	HM_REG_COUNTER(&pHmCpu->StatExitGuestMF, "/HM/CPU%u/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
732	HM_REG_COUNTER(&pHmCpu->StatExitGuestBP, "/HM/CPU%u/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
733	HM_REG_COUNTER(&pHmCpu->StatExitGuestXF, "/HM/CPU%u/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
734	HM_REG_COUNTER(&pHmCpu->StatExitGuestXcpUnk, "/HM/CPU%u/Exit/Trap/Gst/Other", "Other guest exceptions.");
735	HM_REG_COUNTER(&pHmCpu->StatExitRdmsr, "/HM/CPU%u/Exit/Instr/Rdmsr", "MSR read.");
736	HM_REG_COUNTER(&pHmCpu->StatExitWrmsr, "/HM/CPU%u/Exit/Instr/Wrmsr", "MSR write.");
737	HM_REG_COUNTER(&pHmCpu->StatExitDRxWrite, "/HM/CPU%u/Exit/Instr/DR-Write", "Debug register write.");
738	HM_REG_COUNTER(&pHmCpu->StatExitDRxRead, "/HM/CPU%u/Exit/Instr/DR-Read", "Debug register read.");
739	HM_REG_COUNTER(&pHmCpu->StatExitCR0Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR0", "CR0 read.");
740	HM_REG_COUNTER(&pHmCpu->StatExitCR2Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR2", "CR2 read.");
741	HM_REG_COUNTER(&pHmCpu->StatExitCR3Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR3", "CR3 read.");
742	HM_REG_COUNTER(&pHmCpu->StatExitCR4Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR4", "CR4 read.");
743	HM_REG_COUNTER(&pHmCpu->StatExitCR8Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR8", "CR8 read.");
744	HM_REG_COUNTER(&pHmCpu->StatExitCR0Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR0", "CR0 write.");
745	HM_REG_COUNTER(&pHmCpu->StatExitCR2Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR2", "CR2 write.");
746	HM_REG_COUNTER(&pHmCpu->StatExitCR3Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR3", "CR3 write.");
747	HM_REG_COUNTER(&pHmCpu->StatExitCR4Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR4", "CR4 write.");
748	HM_REG_COUNTER(&pHmCpu->StatExitCR8Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR8", "CR8 write.");
749	HM_REG_COUNTER(&pHmCpu->StatExitClts, "/HM/CPU%u/Exit/Instr/CLTS", "CLTS instruction.");
750	HM_REG_COUNTER(&pHmCpu->StatExitLmsw, "/HM/CPU%u/Exit/Instr/LMSW", "LMSW instruction.");
751	HM_REG_COUNTER(&pHmCpu->StatExitXdtrAccess, "/HM/CPU%u/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
752	HM_REG_COUNTER(&pHmCpu->StatExitIOWrite, "/HM/CPU%u/Exit/Instr/IO/Write", "I/O write.");
753	HM_REG_COUNTER(&pHmCpu->StatExitIORead, "/HM/CPU%u/Exit/Instr/IO/Read", "I/O read.");
754	HM_REG_COUNTER(&pHmCpu->StatExitIOStringWrite, "/HM/CPU%u/Exit/Instr/IO/WriteString", "String I/O write.");
755	HM_REG_COUNTER(&pHmCpu->StatExitIOStringRead, "/HM/CPU%u/Exit/Instr/IO/ReadString", "String I/O read.");
756	HM_REG_COUNTER(&pHmCpu->StatExitIntWindow, "/HM/CPU%u/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts.");
757	HM_REG_COUNTER(&pHmCpu->StatExitExtInt, "/HM/CPU%u/Exit/ExtInt", "Physical maskable interrupt (host).");
758	#endif
759	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGC, "/HM/CPU%u/Exit/HostNmiInGC", "Host NMI received while in guest context.");
760	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGCIpi, "/HM/CPU%u/Exit/HostNmiInGCIpi", "Host NMI received while in guest context dispatched using IPIs.");
761	#ifdef VBOX_WITH_STATISTICS
762	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/Exit/PreemptTimer", "VMX-preemption timer expired.");
763	HM_REG_COUNTER(&pHmCpu->StatExitTprBelowThreshold, "/HM/CPU%u/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
764	HM_REG_COUNTER(&pHmCpu->StatExitTaskSwitch, "/HM/CPU%u/Exit/TaskSwitch", "Task switch caused through task gate in IDT.");
765	HM_REG_COUNTER(&pHmCpu->StatExitApicAccess, "/HM/CPU%u/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
766
767	HM_REG_COUNTER(&pHmCpu->StatSwitchTprMaskedIrq, "/HM/CPU%u/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
768	HM_REG_COUNTER(&pHmCpu->StatSwitchGuestIrq, "/HM/CPU%u/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
769	HM_REG_COUNTER(&pHmCpu->StatSwitchPendingHostIrq, "/HM/CPU%u/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
770	HM_REG_COUNTER(&pHmCpu->StatSwitchHmToR3FF, "/HM/CPU%u/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
771	HM_REG_COUNTER(&pHmCpu->StatSwitchVmReq, "/HM/CPU%u/Switch/VmReq", "Exit to ring-3 due to pending VM requests.");
772	HM_REG_COUNTER(&pHmCpu->StatSwitchPgmPoolFlush, "/HM/CPU%u/Switch/PgmPoolFlush", "Exit to ring-3 due to pending PGM pool flush.");
773	HM_REG_COUNTER(&pHmCpu->StatSwitchDma, "/HM/CPU%u/Switch/PendingDma", "Exit to ring-3 due to pending DMA requests.");
774	HM_REG_COUNTER(&pHmCpu->StatSwitchExitToR3, "/HM/CPU%u/Switch/ExitToR3", "Exit to ring-3 (total).");
775	HM_REG_COUNTER(&pHmCpu->StatSwitchLongJmpToR3, "/HM/CPU%u/Switch/LongJmpToR3", "Longjump to ring-3.");
776	HM_REG_COUNTER(&pHmCpu->StatSwitchMaxResumeLoops, "/HM/CPU%u/Switch/MaxResumeLoops", "Maximum VMRESUME inner-loop counter reached.");
777	HM_REG_COUNTER(&pHmCpu->StatSwitchHltToR3, "/HM/CPU%u/Switch/HltToR3", "HLT causing us to go to ring-3.");
778	HM_REG_COUNTER(&pHmCpu->StatSwitchApicAccessToR3, "/HM/CPU%u/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
779	#endif
780	HM_REG_COUNTER(&pHmCpu->StatSwitchPreempt, "/HM/CPU%u/Switch/Preempting", "EMT has been preempted while in HM context.");
781	#ifdef VBOX_WITH_STATISTICS
782	HM_REG_COUNTER(&pHmCpu->StatSwitchNstGstVmexit, "/HM/CPU%u/Switch/NstGstVmexit", "Nested-guest VM-exit occurred.");
783
784	HM_REG_COUNTER(&pHmCpu->StatInjectInterrupt, "/HM/CPU%u/EventInject/Interrupt", "Injected an external interrupt into the guest.");
785	HM_REG_COUNTER(&pHmCpu->StatInjectXcpt, "/HM/CPU%u/EventInject/Trap", "Injected an exception into the guest.");
786	HM_REG_COUNTER(&pHmCpu->StatInjectReflect, "/HM/CPU%u/EventInject/Reflect", "Reflecting an exception caused due to event injection.");
787	HM_REG_COUNTER(&pHmCpu->StatInjectConvertDF, "/HM/CPU%u/EventInject/ReflectDF", "Injected a converted #DF caused due to event injection.");
788	HM_REG_COUNTER(&pHmCpu->StatInjectInterpret, "/HM/CPU%u/EventInject/Interpret", "Falling back to interpreter for handling exception caused due to event injection.");
789	HM_REG_COUNTER(&pHmCpu->StatInjectReflectNPF, "/HM/CPU%u/EventInject/ReflectNPF", "Reflecting event that caused an EPT violation / nested #PF.");
790
791	HM_REG_COUNTER(&pHmCpu->StatFlushPage, "/HM/CPU%u/Flush/Page", "Invalidating a guest page on all guest CPUs.");
792	HM_REG_COUNTER(&pHmCpu->StatFlushPageManual, "/HM/CPU%u/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
793	HM_REG_COUNTER(&pHmCpu->StatFlushPhysPageManual, "/HM/CPU%u/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
794	HM_REG_COUNTER(&pHmCpu->StatFlushTlb, "/HM/CPU%u/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
795	HM_REG_COUNTER(&pHmCpu->StatFlushTlbManual, "/HM/CPU%u/Flush/TLB/Manual", "Request a full guest-TLB flush.");
796	HM_REG_COUNTER(&pHmCpu->StatFlushTlbNstGst, "/HM/CPU%u/Flush/TLB/NestedGuest", "Request a nested-guest-TLB flush.");
797	HM_REG_COUNTER(&pHmCpu->StatFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
798	HM_REG_COUNTER(&pHmCpu->StatNoFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/Skipped", "No TLB flushing required.");
799	HM_REG_COUNTER(&pHmCpu->StatFlushEntire, "/HM/CPU%u/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
800	HM_REG_COUNTER(&pHmCpu->StatFlushAsid, "/HM/CPU%u/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
801	HM_REG_COUNTER(&pHmCpu->StatFlushNestedPaging, "/HM/CPU%u/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
802	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgVirt, "/HM/CPU%u/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
803	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgPhys, "/HM/CPU%u/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
804	HM_REG_COUNTER(&pHmCpu->StatTlbShootdown, "/HM/CPU%u/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
805	HM_REG_COUNTER(&pHmCpu->StatTlbShootdownFlush, "/HM/CPU%u/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
806
807	HM_REG_COUNTER(&pHmCpu->StatTscParavirt, "/HM/CPU%u/TSC/Paravirt", "Paravirtualized TSC in effect.");
808	HM_REG_COUNTER(&pHmCpu->StatTscOffset, "/HM/CPU%u/TSC/Offset", "TSC offsetting is in effect.");
809	HM_REG_COUNTER(&pHmCpu->StatTscIntercept, "/HM/CPU%u/TSC/Intercept", "Intercept TSC accesses.");
810
811	HM_REG_COUNTER(&pHmCpu->StatDRxArmed, "/HM/CPU%u/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
812	HM_REG_COUNTER(&pHmCpu->StatDRxContextSwitch, "/HM/CPU%u/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
813	HM_REG_COUNTER(&pHmCpu->StatDRxIoCheck, "/HM/CPU%u/Debug/IOCheck", "Checking for I/O breakpoint.");
814
815	HM_REG_COUNTER(&pHmCpu->StatExportMinimal, "/HM/CPU%u/Export/Minimal", "VM-entry exporting minimal guest-state.");
816	HM_REG_COUNTER(&pHmCpu->StatExportFull, "/HM/CPU%u/Export/Full", "VM-entry exporting the full guest-state.");
817	HM_REG_COUNTER(&pHmCpu->StatLoadGuestFpu, "/HM/CPU%u/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
818	HM_REG_COUNTER(&pHmCpu->StatExportHostState, "/HM/CPU%u/Export/HostState", "VM-entry exporting host-state.");
819
820	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelBase, "/HM/CPU%u/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
821	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelLimit, "/HM/CPU%u/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
822	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelAttr, "/HM/CPU%u/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector attributes.");
823
824	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelBase, "/HM/CPU%u/VMXCheck/V86SelBase", "Could not use VMX due to unsuitable v8086-mode selector base.");
825	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelLimit, "/HM/CPU%u/VMXCheck/V86SelLimit", "Could not use VMX due to unsuitable v8086-mode selector limit.");
826	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelAttr, "/HM/CPU%u/VMXCheck/V86SelAttrs", "Could not use VMX due to unsuitable v8086-mode selector attributes.");
827
828	HM_REG_COUNTER(&pHmCpu->StatVmxCheckRmOk, "/HM/CPU%u/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
829	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadSel, "/HM/CPU%u/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
830	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRpl, "/HM/CPU%u/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
831	HM_REG_COUNTER(&pHmCpu->StatVmxCheckPmOk, "/HM/CPU%u/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
832
833	bool const fCpuSupportsVmx = ASMIsIntelCpu() \|\| ASMIsViaCentaurCpu() \|\| ASMIsShanghaiCpu();
834
835	/*
836	* Guest Exit reason stats.
837	*/
838	pHmCpu->paStatExitReason = NULL;
839	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(pHmCpu->paStatExitReason), 0 / uAlignment */, MM_TAG_HM,
840	(void **)&pHmCpu->paStatExitReason);
841	AssertRCReturn(rc, rc);
842
843	if (fCpuSupportsVmx)
844	{
845	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
846	{
847	const char *pszExitName = HMGetVmxExitName(j);
848	if (pszExitName)
849	{
850	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
851	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
852	AssertRCReturn(rc, rc);
853	}
854	}
855	}
856	else
857	{
858	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
859	{
860	const char *pszExitName = HMGetSvmExitName(j);
861	if (pszExitName)
862	{
863	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
864	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
865	AssertRC(rc);
866	}
867	}
868	}
869	HM_REG_COUNTER(&pHmCpu->StatExitReasonNpf, "/HM/CPU%u/Exit/Reason/#NPF", "Nested page faults");
870
871	pHmCpu->paStatExitReasonR0 = MMHyperR3ToR0(pVM, pHmCpu->paStatExitReason);
872	Assert(pHmCpu->paStatExitReasonR0 != NIL_RTR0PTR);
873
874	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
875	/*
876	* Nested-guest VM-exit reason stats.
877	*/
878	pHmCpu->paStatNestedExitReason = NULL;
879	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(pHmCpu->paStatNestedExitReason), 0 / uAlignment */, MM_TAG_HM,
880	(void **)&pHmCpu->paStatNestedExitReason);
881	AssertRCReturn(rc, rc);
882	if (fCpuSupportsVmx)
883	{
884	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
885	{
886	const char *pszExitName = HMGetVmxExitName(j);
887	if (pszExitName)
888	{
889	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
890	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
891	AssertRC(rc);
892	}
893	}
894	}
895	else
896	{
897	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
898	{
899	const char *pszExitName = HMGetSvmExitName(j);
900	if (pszExitName)
901	{
902	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
903	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
904	AssertRC(rc);
905	}
906	}
907	}
908	HM_REG_COUNTER(&pHmCpu->StatNestedExitReasonNpf, "/HM/CPU%u/Exit/NestedGuest/Reason/#NPF", "Nested page faults");
909	pHmCpu->paStatNestedExitReasonR0 = MMHyperR3ToR0(pVM, pHmCpu->paStatNestedExitReason);
910	Assert(pHmCpu->paStatNestedExitReasonR0 != NIL_RTR0PTR);
911	#endif
912
913	/*
914	* Injected interrupts stats.
915	*/
916	{
917	uint32_t const cInterrupts = 0xff + 1;
918	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * cInterrupts, 8, MM_TAG_HM, (void **)&pHmCpu->paStatInjectedIrqs);
919	AssertRCReturn(rc, rc);
920	pHmCpu->paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pHmCpu->paStatInjectedIrqs);
921	Assert(pHmCpu->paStatInjectedIrqsR0 != NIL_RTR0PTR);
922	for (unsigned j = 0; j < cInterrupts; j++)
923	{
924	char aszIntrName[64];
925	RTStrPrintf(&aszIntrName[0], sizeof(aszIntrName), "Interrupt %u", j);
926	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
927	STAMUNIT_OCCURENCES, aszIntrName,
928	"/HM/CPU%u/EventInject/InjectIntr/%02X", idCpu, j);
929	AssertRC(rc);
930	}
931	}
932
933	/*
934	* Injected exception stats.
935	*/
936	{
937	uint32_t const cXcpts = X86_XCPT_LAST + 1;
938	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * cXcpts, 8, MM_TAG_HM, (void **)&pHmCpu->paStatInjectedXcpts);
939	AssertRCReturn(rc, rc);
940	pHmCpu->paStatInjectedXcptsR0 = MMHyperR3ToR0(pVM, pHmCpu->paStatInjectedXcpts);
941	Assert(pHmCpu->paStatInjectedXcptsR0 != NIL_RTR0PTR);
942	for (unsigned j = 0; j < cXcpts; j++)
943	{
944	char aszXcptName[64];
945	RTStrPrintf(&aszXcptName[0], sizeof(aszXcptName), "%s exception", hmR3GetXcptName(j));
946	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatInjectedXcpts[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
947	STAMUNIT_OCCURENCES, aszXcptName,
948	"/HM/CPU%u/EventInject/InjectXcpt/%02X", idCpu, j);
949	AssertRC(rc);
950	}
951	}
952
953	#endif /* VBOX_WITH_STATISTICS */
954	#undef HM_REG_COUNTER
955	#undef HM_REG_PROFILE
956	#undef HM_REG_STAT
957	}
958
959	return VINF_SUCCESS;
960	}
961
962
963	/**
964	* Called when a init phase has completed.
965	*
966	* @returns VBox status code.
967	* @param pVM The cross context VM structure.
968	* @param enmWhat The phase that completed.
969	*/
970	VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
971	{
972	switch (enmWhat)
973	{
974	case VMINITCOMPLETED_RING3:
975	return hmR3InitFinalizeR3(pVM);
976	case VMINITCOMPLETED_RING0:
977	return hmR3InitFinalizeR0(pVM);
978	default:
979	return VINF_SUCCESS;
980	}
981	}
982
983
984	/**
985	* Turns off normal raw mode features.
986	*
987	* @param pVM The cross context VM structure.
988	*/
989	static void hmR3DisableRawMode(PVM pVM)
990	{
991	/** @todo r=bird: HM shouldn't be doing this crap. */
992	/* Reinit the paging mode to force the new shadow mode. */
993	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
994	{
995	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
996	PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
997	}
998	}
999
1000
1001	/**
1002	* Initialize VT-x or AMD-V.
1003	*
1004	* @returns VBox status code.
1005	* @param pVM The cross context VM structure.
1006	*/
1007	static int hmR3InitFinalizeR0(PVM pVM)
1008	{
1009	int rc;
1010
1011	if (!HMIsEnabled(pVM))
1012	return VINF_SUCCESS;
1013
1014	/*
1015	* Hack to allow users to work around broken BIOSes that incorrectly set
1016	* EFER.SVME, which makes us believe somebody else is already using AMD-V.
1017	*/
1018	if ( !pVM->hm.s.vmx.fSupported
1019	&& !pVM->hm.s.svm.fSupported
1020	&& pVM->hm.s.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1021	&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1022	{
1023	LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1024	pVM->hm.s.svm.fSupported = true;
1025	pVM->hm.s.svm.fIgnoreInUseError = true;
1026	pVM->hm.s.rcInit = VINF_SUCCESS;
1027	}
1028
1029	/*
1030	* Report ring-0 init errors.
1031	*/
1032	if ( !pVM->hm.s.vmx.fSupported
1033	&& !pVM->hm.s.svm.fSupported)
1034	{
1035	LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.rcInit));
1036	LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatCtrl));
1037	switch (pVM->hm.s.rcInit)
1038	{
1039	case VERR_VMX_IN_VMX_ROOT_MODE:
1040	return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1041	case VERR_VMX_NO_VMX:
1042	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1043	case VERR_VMX_MSR_VMX_DISABLED:
1044	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1045	case VERR_VMX_MSR_ALL_VMX_DISABLED:
1046	return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1047	case VERR_VMX_MSR_LOCKING_FAILED:
1048	return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1049	case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1050	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1051	case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1052	return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1053
1054	case VERR_SVM_IN_USE:
1055	return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1056	case VERR_SVM_NO_SVM:
1057	return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1058	case VERR_SVM_DISABLED:
1059	return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1060	}
1061	return VMSetError(pVM, pVM->hm.s.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.rcInit);
1062	}
1063
1064	/*
1065	* Enable VT-x or AMD-V on all host CPUs.
1066	*/
1067	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_ENABLE, 0, NULL);
1068	if (RT_FAILURE(rc))
1069	{
1070	LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1071	HMR3CheckError(pVM, rc);
1072	return rc;
1073	}
1074
1075	/*
1076	* No TPR patching is required when the IO-APIC is not enabled for this VM.
1077	* (Main should have taken care of this already)
1078	*/
1079	if (!PDMHasIoApic(pVM))
1080	{
1081	Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1082	pVM->hm.s.fTprPatchingAllowed = false;
1083	}
1084
1085	/*
1086	* Check if L1D flush is needed/possible.
1087	*/
1088	if ( !pVM->cpum.ro.HostFeatures.fFlushCmd
1089	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
1090	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
1091	\|\| pVM->cpum.ro.HostFeatures.fArchVmmNeedNotFlushL1d
1092	\|\| pVM->cpum.ro.HostFeatures.fArchRdclNo)
1093	pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
1094
1095	/*
1096	* Check if MDS flush is needed/possible.
1097	* On atoms and knight family CPUs, we will only allow clearing on scheduling.
1098	*/
1099	if ( !pVM->cpum.ro.HostFeatures.fMdsClear
1100	\|\| pVM->cpum.ro.HostFeatures.fArchMdsNo)
1101	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
1102	else if ( ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
1103	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Atom_End)
1104	\|\| ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Phi_KnightsLanding
1105	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Phi_End))
1106	{
1107	if (!pVM->hm.s.fMdsClearOnSched)
1108	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
1109	pVM->hm.s.fMdsClearOnVmEntry = false;
1110	}
1111	else if ( pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
1112	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
1113	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
1114
1115	/*
1116	* Sync options.
1117	*/
1118	/** @todo Move this out of of CPUMCTX and into some ring-0 only HM structure.
1119	* That will require a little bit of work, of course. */
1120	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1121	{
1122	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1123	PCPUMCTX pCpuCtx = &pVCpu->cpum.GstCtx;
1124	pCpuCtx->fWorldSwitcher &= ~(CPUMCTX_WSF_IBPB_EXIT \| CPUMCTX_WSF_IBPB_ENTRY);
1125	if (pVM->cpum.ro.HostFeatures.fIbpb)
1126	{
1127	if (pVM->hm.s.fIbpbOnVmExit)
1128	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_IBPB_EXIT;
1129	if (pVM->hm.s.fIbpbOnVmEntry)
1130	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_IBPB_ENTRY;
1131	}
1132	if (pVM->cpum.ro.HostFeatures.fFlushCmd && pVM->hm.s.fL1dFlushOnVmEntry)
1133	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_L1D_ENTRY;
1134	if (pVM->cpum.ro.HostFeatures.fMdsClear && pVM->hm.s.fMdsClearOnVmEntry)
1135	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_MDS_ENTRY;
1136	if (idCpu == 0)
1137	LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
1138	pCpuCtx->fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
1139	pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
1140	}
1141
1142	/*
1143	* Do the vendor specific initialization
1144	*
1145	* Note! We disable release log buffering here since we're doing relatively
1146	* lot of logging and doesn't want to hit the disk with each LogRel
1147	* statement.
1148	*/
1149	AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1150	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
1151	if (pVM->hm.s.vmx.fSupported)
1152	rc = hmR3InitFinalizeR0Intel(pVM);
1153	else
1154	rc = hmR3InitFinalizeR0Amd(pVM);
1155	LogRel((pVM->hm.s.fGlobalInit ? "HM: VT-x/AMD-V init method: Global\n"
1156	: "HM: VT-x/AMD-V init method: Local\n"));
1157	RTLogRelSetBuffering(fOldBuffered);
1158	pVM->hm.s.fInitialized = true;
1159
1160	return rc;
1161	}
1162
1163
1164	/**
1165	* @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1166	*/
1167	static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1168	{
1169	NOREF(pVM);
1170	NOREF(pvAllocation);
1171	NOREF(GCPhysAllocation);
1172	}
1173
1174
1175	/**
1176	* Returns a description of the VMCS (and associated regions') memory type given the
1177	* IA32_VMX_BASIC MSR.
1178	*
1179	* @returns The descriptive memory type.
1180	* @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1181	*/
1182	static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1183	{
1184	uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1185	switch (uMemType)
1186	{
1187	case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1188	case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1189	}
1190	return "Unknown";
1191	}
1192
1193
1194	/**
1195	* Returns a single-line description of all the activity-states supported by the CPU
1196	* given the IA32_VMX_MISC MSR.
1197	*
1198	* @returns All supported activity states.
1199	* @param uMsrMisc IA32_VMX_MISC MSR value.
1200	*/
1201	static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1202	{
1203	static const char * const s_apszActStates[] =
1204	{
1205	"",
1206	" ( HLT )",
1207	" ( SHUTDOWN )",
1208	" ( HLT SHUTDOWN )",
1209	" ( SIPI_WAIT )",
1210	" ( HLT SIPI_WAIT )",
1211	" ( SHUTDOWN SIPI_WAIT )",
1212	" ( HLT SHUTDOWN SIPI_WAIT )"
1213	};
1214	uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1215	Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1216	return s_apszActStates[idxActStates];
1217	}
1218
1219
1220	/**
1221	* Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1222	*
1223	* @param fFeatMsr The feature control MSR value.
1224	*/
1225	static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1226	{
1227	uint64_t const val = fFeatMsr;
1228	LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1229	HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1230	HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1231	HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1232	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1233	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1234	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1235	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1236	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1237	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1238	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1239	HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1240	HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1241	HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1242	HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1243	if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1244	LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1245	}
1246
1247
1248	/**
1249	* Reports MSR_IA32_VMX_BASIC MSR to the log.
1250	*
1251	* @param uBasicMsr The VMX basic MSR value.
1252	*/
1253	static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1254	{
1255	LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1256	LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1257	LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1258	LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1259	"< 4 GB" : "None"));
1260	LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1261	LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1262	LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1263	LogRel(("HM: Supports true-capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1264	LogRel(("HM: VM-entry Xcpt error-code optional = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_XCPT_ERRCODE)));
1265	}
1266
1267
1268	/**
1269	* Reports MSR_IA32_PINBASED_CTLS to the log.
1270	*
1271	* @param pVmxMsr Pointer to the VMX MSR.
1272	*/
1273	static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1274	{
1275	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1276	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1277	LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1278	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1279	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1280	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1281	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1282	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1283	}
1284
1285
1286	/**
1287	* Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1288	*
1289	* @param pVmxMsr Pointer to the VMX MSR.
1290	*/
1291	static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1292	{
1293	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1294	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1295	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1296	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1297	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1298	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1299	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1300	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1301	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1302	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1303	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1304	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1305	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1306	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1307	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1308	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1309	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1310	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1311	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1312	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1313	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1314	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1315	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1316	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1317	}
1318
1319
1320	/**
1321	* Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1322	*
1323	* @param pVmxMsr Pointer to the VMX MSR.
1324	*/
1325	static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1326	{
1327	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1328	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1329	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1330	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1331	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1332	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1333	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1334	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1335	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1336	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1337	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1338	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1339	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1340	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1341	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1342	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1343	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1344	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1345	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1346	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1347	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1348	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_VE", VMX_PROC_CTLS2_EPT_VE);
1349	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1350	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1351	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MODE_BASED_EPT_PERM", VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1352	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SPPTP_EPT", VMX_PROC_CTLS2_SPPTP_EPT);
1353	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PT_EPT", VMX_PROC_CTLS2_PT_EPT);
1354	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1355	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USER_WAIT_PAUSE", VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1356	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLV_EXIT", VMX_PROC_CTLS2_ENCLV_EXIT);
1357	}
1358
1359
1360	/**
1361	* Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1362	*
1363	* @param pVmxMsr Pointer to the VMX MSR.
1364	*/
1365	static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1366	{
1367	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1368	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1369	LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1370	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1371	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1372	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1373	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1374	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1375	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1376	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1377	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_BNDCFGS_MSR", VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR);
1378	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
1379	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_RTIT_CTL_MSR", VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR);
1380	}
1381
1382
1383	/**
1384	* Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1385	*
1386	* @param pVmxMsr Pointer to the VMX MSR.
1387	*/
1388	static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1389	{
1390	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1391	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1392	LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1393	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1394	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1395	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1396	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1397	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1398	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1399	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1400	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1401	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1402	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_BNDCFGS_MSR", VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR);
1403	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT);
1404	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_RTIT_CTL_MSR", VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR);
1405	}
1406
1407
1408	/**
1409	* Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1410	*
1411	* @param fCaps The VMX EPT/VPID capability MSR value.
1412	*/
1413	static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1414	{
1415	LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1416	HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1417	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1418	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_5", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5);
1419	HMVMX_REPORT_MSR_CAP(fCaps, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1420	HMVMX_REPORT_MSR_CAP(fCaps, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1421	HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1422	HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1423	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1424	HMVMX_REPORT_MSR_CAP(fCaps, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1425	HMVMX_REPORT_MSR_CAP(fCaps, "ADVEXITINFO_EPT", MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT);
1426	HMVMX_REPORT_MSR_CAP(fCaps, "SSS", MSR_IA32_VMX_EPT_VPID_CAP_SSS);
1427	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1428	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1429	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1430	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1431	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1432	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1433	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1434	}
1435
1436
1437	/**
1438	* Reports MSR_IA32_VMX_MISC MSR to the log.
1439	*
1440	* @param pVM Pointer to the VM.
1441	* @param fMisc The VMX misc. MSR value.
1442	*/
1443	static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1444	{
1445	LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1446	uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1447	if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1448	LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1449	else
1450	{
1451	LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1452	pVM->hm.s.vmx.cPreemptTimerShift));
1453	}
1454	LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1455	LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1456	hmR3VmxGetActivityStateAllDesc(fMisc)));
1457	LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1458	LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1459	LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1460	LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1461	VMX_MISC_MAX_MSRS(fMisc)));
1462	LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1463	LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1464	LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1465	LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1466	}
1467
1468
1469	/**
1470	* Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1471	*
1472	* @param uVmcsEnum The VMX VMCS enum MSR value.
1473	*/
1474	static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1475	{
1476	LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1477	LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1478	}
1479
1480
1481	/**
1482	* Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1483	*
1484	* @param uVmFunc The VMX VMFUNC MSR value.
1485	*/
1486	static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1487	{
1488	LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1489	HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1490	}
1491
1492
1493	/**
1494	* Reports VMX CR0, CR4 fixed MSRs.
1495	*
1496	* @param pMsrs Pointer to the VMX MSRs.
1497	*/
1498	static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1499	{
1500	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1501	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1502	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1503	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1504	}
1505
1506
1507	/**
1508	* Finish VT-x initialization (after ring-0 init).
1509	*
1510	* @returns VBox status code.
1511	* @param pVM The cross context VM structure.
1512	*/
1513	static int hmR3InitFinalizeR0Intel(PVM pVM)
1514	{
1515	int rc;
1516
1517	LogFunc(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1518	AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatCtrl != 0, VERR_HM_IPE_4);
1519
1520	LogRel(("HM: Using VT-x implementation 3.0\n"));
1521	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1522	LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
1523	LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostMsrEfer));
1524	LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
1525
1526	hmR3VmxReportFeatCtlMsr(pVM->hm.s.vmx.Msrs.u64FeatCtrl);
1527	hmR3VmxReportBasicMsr(pVM->hm.s.vmx.Msrs.u64Basic);
1528
1529	hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.PinCtls);
1530	hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.ProcCtls);
1531	if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1532	hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.vmx.Msrs.ProcCtls2);
1533
1534	hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.vmx.Msrs.EntryCtls);
1535	hmR3VmxReportExitCtlsMsr(&pVM->hm.s.vmx.Msrs.ExitCtls);
1536
1537	if (RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1538	{
1539	/* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1540	LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TruePinCtls));
1541	LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueProcCtls));
1542	LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueEntryCtls));
1543	LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueExitCtls));
1544	}
1545
1546	hmR3VmxReportMiscMsr(pVM, pVM->hm.s.vmx.Msrs.u64Misc);
1547	hmR3VmxReportVmcsEnumMsr(pVM->hm.s.vmx.Msrs.u64VmcsEnum);
1548	if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1549	hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.vmx.Msrs.u64EptVpidCaps);
1550	if (pVM->hm.s.vmx.Msrs.u64VmFunc)
1551	hmR3VmxReportVmFuncMsr(pVM->hm.s.vmx.Msrs.u64VmFunc);
1552	hmR3VmxReportCrFixedMsrs(&pVM->hm.s.vmx.Msrs);
1553
1554	LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1555	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1556	{
1557	PCVMXVMCSINFO pVmcsInfo = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfo;
1558	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
1559	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysVmcs));
1560	}
1561	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1562	if (pVM->cpum.ro.GuestFeatures.fVmx)
1563	{
1564	LogRel(("HM: Nested-guest:\n"));
1565	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1566	{
1567	PCVMXVMCSINFO pVmcsInfoNstGst = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfoNstGst;
1568	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysMsrBitmap));
1569	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysVmcs));
1570	}
1571	}
1572	#endif
1573
1574	/*
1575	* EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1576	*/
1577	AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1578	\|\| (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1579	VERR_HM_IPE_1);
1580	AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
1581	\|\| ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1582	&& pVM->hm.s.fNestedPaging),
1583	VERR_HM_IPE_1);
1584
1585	/*
1586	* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1587	* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1588	* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1589	*/
1590	if ( !(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1591	&& CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1592	{
1593	CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1594	LogRel(("HM: Disabled RDTSCP\n"));
1595	}
1596
1597	if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1598	{
1599	/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1600	rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1601	if (RT_SUCCESS(rc))
1602	{
1603	/* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1604	Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1605	esp. Figure 20-5.*/
1606	ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1607	pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1608
1609	/* Bit set to 0 means software interrupts are redirected to the
1610	8086 program interrupt handler rather than switching to
1611	protected-mode handler. */
1612	memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1613
1614	/* Allow all port IO, so that port IO instructions do not cause
1615	exceptions and would instead cause a VM-exit (based on VT-x's
1616	IO bitmap which we currently configure to always cause an exit). */
1617	memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1618	((unsigned char )pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1619
1620	/*
1621	* Construct a 1024 element page directory with 4 MB pages for the identity mapped
1622	* page table used in real and protected mode without paging with EPT.
1623	*/
1624	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
1625	for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1626	{
1627	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1628	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US
1629	\| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS
1630	\| X86_PDE4M_G;
1631	}
1632
1633	/* We convert it here every time as PCI regions could be reconfigured. */
1634	if (PDMVmmDevHeapIsEnabled(pVM))
1635	{
1636	RTGCPHYS GCPhys;
1637	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1638	AssertRCReturn(rc, rc);
1639	LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1640
1641	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1642	AssertRCReturn(rc, rc);
1643	LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1644	}
1645	}
1646	else
1647	{
1648	LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1649	pVM->hm.s.vmx.pRealModeTSS = NULL;
1650	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1651	return VMSetError(pVM, rc, RT_SRC_POS,
1652	"HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1653	}
1654	}
1655
1656	LogRel((pVM->hm.s.fAllow64BitGuests ? "HM: Guest support: 32-bit and 64-bit\n"
1657	: "HM: Guest support: 32-bit only\n"));
1658
1659	/*
1660	* Call ring-0 to set up the VM.
1661	*/
1662	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /* idCpu /, VMMR0_DO_HM_SETUP_VM, 0 / u64Arg /, NULL / pReqHdr */);
1663	if (rc != VINF_SUCCESS)
1664	{
1665	LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1666	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1667	{
1668	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1669	LogRel(("HM: CPU[%u] Last instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
1670	LogRel(("HM: CPU[%u] HM error %#x (%u)\n", idCpu, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1671	}
1672	HMR3CheckError(pVM, rc);
1673	return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1674	}
1675
1676	LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1677	LogRel(("HM: Enabled VMX\n"));
1678	pVM->hm.s.vmx.fEnabled = true;
1679
1680	hmR3DisableRawMode(pVM); /** @todo make this go away! */
1681
1682	/*
1683	* Change the CPU features.
1684	*/
1685	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1686	if (pVM->hm.s.fAllow64BitGuests)
1687	{
1688	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1689	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1690	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1691	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1692	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1693	}
1694	/* Turn on NXE if PAE has been enabled and the host has turned on NXE
1695	(we reuse the host EFER in the switcher). */
1696	/** @todo this needs to be fixed properly!! */
1697	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1698	{
1699	if (pVM->hm.s.vmx.u64HostMsrEfer & MSR_K6_EFER_NXE)
1700	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1701	else
1702	LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1703	}
1704
1705	/*
1706	* Log configuration details.
1707	*/
1708	if (pVM->hm.s.fNestedPaging)
1709	{
1710	LogRel(("HM: Enabled nested paging\n"));
1711	if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1712	LogRel(("HM: EPT flush type = Single context\n"));
1713	else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1714	LogRel(("HM: EPT flush type = All contexts\n"));
1715	else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1716	LogRel(("HM: EPT flush type = Not supported\n"));
1717	else
1718	LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushEpt));
1719
1720	if (pVM->hm.s.vmx.fUnrestrictedGuest)
1721	LogRel(("HM: Enabled unrestricted guest execution\n"));
1722
1723	if (pVM->hm.s.fLargePages)
1724	{
1725	/* Use large (2 MB) pages for our EPT PDEs where possible. */
1726	PGMSetLargePageUsage(pVM, true);
1727	LogRel(("HM: Enabled large page support\n"));
1728	}
1729	}
1730	else
1731	Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1732
1733	if (pVM->hm.s.vmx.fVpid)
1734	{
1735	LogRel(("HM: Enabled VPID\n"));
1736	if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1737	LogRel(("HM: VPID flush type = Individual addresses\n"));
1738	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1739	LogRel(("HM: VPID flush type = Single context\n"));
1740	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1741	LogRel(("HM: VPID flush type = All contexts\n"));
1742	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1743	LogRel(("HM: VPID flush type = Single context retain globals\n"));
1744	else
1745	LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushVpid));
1746	}
1747	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1748	LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1749
1750	if (pVM->hm.s.vmx.fUsePreemptTimer)
1751	LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1752	else
1753	LogRel(("HM: Disabled VMX-preemption timer\n"));
1754
1755	if (pVM->hm.s.fVirtApicRegs)
1756	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1757
1758	if (pVM->hm.s.fPostedIntrs)
1759	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1760
1761	if (pVM->hm.s.vmx.fUseVmcsShadowing)
1762	{
1763	bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL);
1764	LogRel(("HM: Enabled %s VMCS shadowing\n", fFullVmcsShadow ? "full" : "partial"));
1765	}
1766
1767	return VINF_SUCCESS;
1768	}
1769
1770
1771	/**
1772	* Finish AMD-V initialization (after ring-0 init).
1773	*
1774	* @returns VBox status code.
1775	* @param pVM The cross context VM structure.
1776	*/
1777	static int hmR3InitFinalizeR0Amd(PVM pVM)
1778	{
1779	LogFunc(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1780
1781	LogRel(("HM: Using AMD-V implementation 2.0\n"));
1782
1783	uint32_t u32Family;
1784	uint32_t u32Model;
1785	uint32_t u32Stepping;
1786	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
1787	LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1788	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1789	LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1790	LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1791	LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1792	LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1793
1794	/*
1795	* Enumerate AMD-V features.
1796	*/
1797	static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1798	{
1799	#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1800	HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1801	HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1802	HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1803	HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1804	HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1805	HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1806	HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1807	HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1808	HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1809	HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1810	HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1811	HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1812	HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1813	HMSVM_REPORT_FEATURE("GMET", X86_CPUID_SVM_FEATURE_EDX_GMET),
1814	#undef HMSVM_REPORT_FEATURE
1815	};
1816
1817	uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1818	for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1819	if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1820	{
1821	LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1822	fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1823	}
1824	if (fSvmFeatures)
1825	for (unsigned iBit = 0; iBit < 32; iBit++)
1826	if (RT_BIT_32(iBit) & fSvmFeatures)
1827	LogRel(("HM: Reserved bit %u\n", iBit));
1828
1829	/*
1830	* Nested paging is determined in HMR3Init, verify the sanity of that.
1831	*/
1832	AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1833	\|\| (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1834	VERR_HM_IPE_1);
1835
1836	#if 0
1837	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1838	* here. */
1839	if (RTR0IsPostIpiSupport())
1840	pVM->hm.s.fPostedIntrs = true;
1841	#endif
1842
1843	/*
1844	* Determine whether we need to intercept #UD in SVM mode for emulating
1845	* intel SYSENTER/SYSEXIT on AMD64, as these instructions results in #UD
1846	* when executed in long-mode. This is only really applicable when
1847	* non-default CPU profiles are in effect, i.e. guest vendor differs
1848	* from the host one.
1849	*/
1850	if (CPUMGetGuestCpuVendor(pVM) != CPUMGetHostCpuVendor(pVM))
1851	switch (CPUMGetGuestCpuVendor(pVM))
1852	{
1853	case CPUMCPUVENDOR_INTEL:
1854	case CPUMCPUVENDOR_VIA: /?/
1855	case CPUMCPUVENDOR_SHANGHAI: /?/
1856	switch (CPUMGetHostCpuVendor(pVM))
1857	{
1858	case CPUMCPUVENDOR_AMD:
1859	case CPUMCPUVENDOR_HYGON:
1860	if (pVM->hm.s.fAllow64BitGuests)
1861	{
1862	LogRel(("HM: Intercepting #UD for emulating SYSENTER/SYSEXIT in long mode.\n"));
1863	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1864	pVM->apCpusR3[idCpu]->hm.s.svm.fEmulateLongModeSysEnterExit = true;
1865	}
1866	break;
1867	default: break;
1868	}
1869	default: break;
1870	}
1871
1872	/*
1873	* Call ring-0 to set up the VM.
1874	*/
1875	int rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1876	if (rc != VINF_SUCCESS)
1877	{
1878	AssertMsgFailed(("%Rrc\n", rc));
1879	LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1880	return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1881	}
1882
1883	LogRel(("HM: Enabled SVM\n"));
1884	pVM->hm.s.svm.fEnabled = true;
1885
1886	if (pVM->hm.s.fNestedPaging)
1887	{
1888	LogRel(("HM: Enabled nested paging\n"));
1889
1890	/*
1891	* Enable large pages (2 MB) if applicable.
1892	*/
1893	if (pVM->hm.s.fLargePages)
1894	{
1895	PGMSetLargePageUsage(pVM, true);
1896	LogRel(("HM: Enabled large page support\n"));
1897	}
1898	}
1899
1900	if (pVM->hm.s.fVirtApicRegs)
1901	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1902
1903	if (pVM->hm.s.fPostedIntrs)
1904	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1905
1906	hmR3DisableRawMode(pVM);
1907
1908	/*
1909	* Change the CPU features.
1910	*/
1911	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1912	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1913	if (pVM->hm.s.fAllow64BitGuests)
1914	{
1915	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1916	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1917	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1918	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1919	}
1920	/* Turn on NXE if PAE has been enabled. */
1921	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1922	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1923
1924	LogRel((pVM->hm.s.fTprPatchingAllowed ? "HM: Enabled TPR patching\n"
1925	: "HM: Disabled TPR patching\n"));
1926
1927	LogRel((pVM->hm.s.fAllow64BitGuests ? "HM: Guest support: 32-bit and 64-bit\n"
1928	: "HM: Guest support: 32-bit only\n"));
1929	return VINF_SUCCESS;
1930	}
1931
1932
1933	/**
1934	* Applies relocations to data and code managed by this
1935	* component. This function will be called at init and
1936	* whenever the VMM need to relocate it self inside the GC.
1937	*
1938	* @param pVM The cross context VM structure.
1939	*/
1940	VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1941	{
1942	Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1943
1944	/* Fetch the current paging mode during the relocate callback during state loading. */
1945	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1946	{
1947	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1948	{
1949	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1950	pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1951	}
1952	}
1953	}
1954
1955
1956	/**
1957	* Terminates the HM.
1958	*
1959	* Termination means cleaning up and freeing all resources,
1960	* the VM itself is, at this point, powered off or suspended.
1961	*
1962	* @returns VBox status code.
1963	* @param pVM The cross context VM structure.
1964	*/
1965	VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1966	{
1967	if (pVM->hm.s.vmx.pRealModeTSS)
1968	{
1969	PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1970	pVM->hm.s.vmx.pRealModeTSS = 0;
1971	}
1972	hmR3TermCPU(pVM);
1973	return 0;
1974	}
1975
1976
1977	/**
1978	* Terminates the per-VCPU HM.
1979	*
1980	* @returns VBox status code.
1981	* @param pVM The cross context VM structure.
1982	*/
1983	static int hmR3TermCPU(PVM pVM)
1984	{
1985	#ifdef VBOX_WITH_STATISTICS
1986	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1987	{
1988	PVMCPU pVCpu = pVM->apCpusR3[idCpu]; NOREF(pVCpu);
1989	if (pVCpu->hm.s.paStatExitReason)
1990	{
1991	MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1992	pVCpu->hm.s.paStatExitReason = NULL;
1993	pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1994	}
1995	if (pVCpu->hm.s.paStatInjectedIrqs)
1996	{
1997	MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1998	pVCpu->hm.s.paStatInjectedIrqs = NULL;
1999	pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
2000	}
2001	if (pVCpu->hm.s.paStatInjectedXcpts)
2002	{
2003	MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedXcpts);
2004	pVCpu->hm.s.paStatInjectedXcpts = NULL;
2005	pVCpu->hm.s.paStatInjectedXcptsR0 = NIL_RTR0PTR;
2006	}
2007	# if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
2008	if (pVCpu->hm.s.paStatNestedExitReason)
2009	{
2010	MMHyperFree(pVM, pVCpu->hm.s.paStatNestedExitReason);
2011	pVCpu->hm.s.paStatNestedExitReason = NULL;
2012	pVCpu->hm.s.paStatNestedExitReasonR0 = NIL_RTR0PTR;
2013	}
2014	# endif
2015	}
2016	#else
2017	RT_NOREF(pVM);
2018	#endif
2019	return VINF_SUCCESS;
2020	}
2021
2022
2023	/**
2024	* Resets a virtual CPU.
2025	*
2026	* Used by HMR3Reset and CPU hot plugging.
2027	*
2028	* @param pVCpu The cross context virtual CPU structure to reset.
2029	*/
2030	VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
2031	{
2032	/* Sync. entire state on VM reset ring-0 re-entry. It's safe to reset
2033	the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2034	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
2035
2036	pVCpu->hm.s.fActive = false;
2037	pVCpu->hm.s.Event.fPending = false;
2038	pVCpu->hm.s.vmx.u64GstMsrApicBase = 0;
2039	pVCpu->hm.s.vmx.VmcsInfo.fSwitchedTo64on32Obsolete = false;
2040	pVCpu->hm.s.vmx.VmcsInfo.fWasInRealMode = true;
2041	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2042	if (pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmx)
2043	{
2044	pVCpu->hm.s.vmx.VmcsInfoNstGst.fSwitchedTo64on32Obsolete = false;
2045	pVCpu->hm.s.vmx.VmcsInfoNstGst.fWasInRealMode = true;
2046	}
2047	#endif
2048	}
2049
2050
2051	/**
2052	* The VM is being reset.
2053	*
2054	* For the HM component this means that any GDT/LDT/TSS monitors
2055	* needs to be removed.
2056	*
2057	* @param pVM The cross context VM structure.
2058	*/
2059	VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2060	{
2061	LogFlow(("HMR3Reset:\n"));
2062
2063	if (HMIsEnabled(pVM))
2064	hmR3DisableRawMode(pVM);
2065
2066	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2067	HMR3ResetCpu(pVM->apCpusR3[idCpu]);
2068
2069	/* Clear all patch information. */
2070	pVM->hm.s.pGuestPatchMem = 0;
2071	pVM->hm.s.pFreeGuestPatchMem = 0;
2072	pVM->hm.s.cbGuestPatchMem = 0;
2073	pVM->hm.s.cPatches = 0;
2074	pVM->hm.s.PatchTree = 0;
2075	pVM->hm.s.fTPRPatchingActive = false;
2076	ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2077	}
2078
2079
2080	/**
2081	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2082	*
2083	* @returns VBox strict status code.
2084	* @param pVM The cross context VM structure.
2085	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2086	* @param pvUser Unused.
2087	*/
2088	static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2089	{
2090	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2091
2092	/* Only execute the handler on the VCPU the original patch request was issued. */
2093	if (pVCpu->idCpu != idCpu)
2094	return VINF_SUCCESS;
2095
2096	Log(("hmR3RemovePatches\n"));
2097	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2098	{
2099	uint8_t abInstr[15];
2100	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2101	RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2102	int rc;
2103
2104	#ifdef LOG_ENABLED
2105	char szOutput[256];
2106	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2107	szOutput, sizeof(szOutput), NULL);
2108	if (RT_SUCCESS(rc))
2109	Log(("Patched instr: %s\n", szOutput));
2110	#endif
2111
2112	/* Check if the instruction is still the same. */
2113	rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2114	if (rc != VINF_SUCCESS)
2115	{
2116	Log(("Patched code removed? (rc=%Rrc0\n", rc));
2117	continue; /* swapped out or otherwise removed; skip it. */
2118	}
2119
2120	if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2121	{
2122	Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2123	continue; /* skip it. */
2124	}
2125
2126	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2127	AssertRC(rc);
2128
2129	#ifdef LOG_ENABLED
2130	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2131	szOutput, sizeof(szOutput), NULL);
2132	if (RT_SUCCESS(rc))
2133	Log(("Original instr: %s\n", szOutput));
2134	#endif
2135	}
2136	pVM->hm.s.cPatches = 0;
2137	pVM->hm.s.PatchTree = 0;
2138	pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2139	pVM->hm.s.fTPRPatchingActive = false;
2140	return VINF_SUCCESS;
2141	}
2142
2143
2144	/**
2145	* Worker for enabling patching in a VT-x/AMD-V guest.
2146	*
2147	* @returns VBox status code.
2148	* @param pVM The cross context VM structure.
2149	* @param idCpu VCPU to execute hmR3RemovePatches on.
2150	* @param pPatchMem Patch memory range.
2151	* @param cbPatchMem Size of the memory range.
2152	*/
2153	static DECLCALLBACK(int) hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2154	{
2155	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2156	AssertRC(rc);
2157
2158	pVM->hm.s.pGuestPatchMem = pPatchMem;
2159	pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2160	pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2161	return VINF_SUCCESS;
2162	}
2163
2164
2165	/**
2166	* Enable patching in a VT-x/AMD-V guest
2167	*
2168	* @returns VBox status code.
2169	* @param pVM The cross context VM structure.
2170	* @param pPatchMem Patch memory range.
2171	* @param cbPatchMem Size of the memory range.
2172	*/
2173	VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2174	{
2175	VM_ASSERT_EMT(pVM);
2176	Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2177	if (pVM->cCpus > 1)
2178	{
2179	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2180	int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2181	(PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2182	AssertRC(rc);
2183	return rc;
2184	}
2185	return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2186	}
2187
2188
2189	/**
2190	* Disable patching in a VT-x/AMD-V guest.
2191	*
2192	* @returns VBox status code.
2193	* @param pVM The cross context VM structure.
2194	* @param pPatchMem Patch memory range.
2195	* @param cbPatchMem Size of the memory range.
2196	*/
2197	VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2198	{
2199	Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2200	RT_NOREF2(pPatchMem, cbPatchMem);
2201
2202	Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2203	Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2204
2205	/** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2206	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2207	(void *)(uintptr_t)VMMGetCpuId(pVM));
2208	AssertRC(rc);
2209
2210	pVM->hm.s.pGuestPatchMem = 0;
2211	pVM->hm.s.pFreeGuestPatchMem = 0;
2212	pVM->hm.s.cbGuestPatchMem = 0;
2213	pVM->hm.s.fTPRPatchingActive = false;
2214	return VINF_SUCCESS;
2215	}
2216
2217
2218	/**
2219	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2220	*
2221	* @returns VBox strict status code.
2222	* @param pVM The cross context VM structure.
2223	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2224	* @param pvUser User specified CPU context.
2225	*
2226	*/
2227	static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2228	{
2229	/*
2230	* Only execute the handler on the VCPU the original patch request was
2231	* issued. (The other CPU(s) might not yet have switched to protected
2232	* mode, nor have the correct memory context.)
2233	*/
2234	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2235	if (pVCpu->idCpu != idCpu)
2236	return VINF_SUCCESS;
2237
2238	/*
2239	* We're racing other VCPUs here, so don't try patch the instruction twice
2240	* and make sure there is still room for our patch record.
2241	*/
2242	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2243	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2244	if (pPatch)
2245	{
2246	Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2247	return VINF_SUCCESS;
2248	}
2249	uint32_t const idx = pVM->hm.s.cPatches;
2250	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2251	{
2252	Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2253	return VINF_SUCCESS;
2254	}
2255	pPatch = &pVM->hm.s.aPatches[idx];
2256
2257	Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2258
2259	/*
2260	* Disassembler the instruction and get cracking.
2261	*/
2262	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2263	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2264	uint32_t cbOp;
2265	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2266	AssertRC(rc);
2267	if ( rc == VINF_SUCCESS
2268	&& pDis->pCurInstr->uOpcode == OP_MOV
2269	&& cbOp >= 3)
2270	{
2271	static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2272
2273	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2274	AssertRC(rc);
2275
2276	pPatch->cbOp = cbOp;
2277
2278	if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2279	{
2280	/* write. */
2281	if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2282	{
2283	pPatch->enmType = HMTPRINSTR_WRITE_REG;
2284	pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
2285	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
2286	}
2287	else
2288	{
2289	Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2290	pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2291	pPatch->uSrcOperand = pDis->Param2.uValue;
2292	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
2293	}
2294	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2295	AssertRC(rc);
2296
2297	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2298	pPatch->cbNewOp = sizeof(s_abVMMCall);
2299	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2300	}
2301	else
2302	{
2303	/*
2304	* TPR Read.
2305	*
2306	* Found:
2307	* mov eax, dword [fffe0080] (5 bytes)
2308	* Check if next instruction is:
2309	* shr eax, 4
2310	*/
2311	Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2312
2313	uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
2314	uint8_t const cbOpMmio = cbOp;
2315	uint64_t const uSavedRip = pCtx->rip;
2316
2317	pCtx->rip += cbOp;
2318	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2319	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2320	pCtx->rip = uSavedRip;
2321
2322	if ( rc == VINF_SUCCESS
2323	&& pDis->pCurInstr->uOpcode == OP_SHR
2324	&& pDis->Param1.fUse == DISUSE_REG_GEN32
2325	&& pDis->Param1.Base.idxGenReg == idxMmioReg
2326	&& pDis->Param2.fUse == DISUSE_IMMEDIATE8
2327	&& pDis->Param2.uValue == 4
2328	&& cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2329	{
2330	uint8_t abInstr[15];
2331
2332	/* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2333	access CR8 in 32-bit mode and not cause a #VMEXIT. */
2334	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2335	AssertRC(rc);
2336
2337	pPatch->cbOp = cbOpMmio + cbOp;
2338
2339	/* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2340	abInstr[0] = 0xf0;
2341	abInstr[1] = 0x0f;
2342	abInstr[2] = 0x20;
2343	abInstr[3] = 0xc0 \| pDis->Param1.Base.idxGenReg;
2344	for (unsigned i = 4; i < pPatch->cbOp; i++)
2345	abInstr[i] = 0x90; /* nop */
2346
2347	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2348	AssertRC(rc);
2349
2350	memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2351	pPatch->cbNewOp = pPatch->cbOp;
2352	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2353
2354	Log(("Acceptable read/shr candidate!\n"));
2355	pPatch->enmType = HMTPRINSTR_READ_SHR4;
2356	}
2357	else
2358	{
2359	pPatch->enmType = HMTPRINSTR_READ;
2360	pPatch->uDstOperand = idxMmioReg;
2361
2362	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2363	AssertRC(rc);
2364
2365	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2366	pPatch->cbNewOp = sizeof(s_abVMMCall);
2367	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2368	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2369	}
2370	}
2371
2372	pPatch->Core.Key = pCtx->eip;
2373	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2374	AssertRC(rc);
2375
2376	pVM->hm.s.cPatches++;
2377	return VINF_SUCCESS;
2378	}
2379
2380	/*
2381	* Save invalid patch, so we will not try again.
2382	*/
2383	Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2384	pPatch->Core.Key = pCtx->eip;
2385	pPatch->enmType = HMTPRINSTR_INVALID;
2386	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2387	AssertRC(rc);
2388	pVM->hm.s.cPatches++;
2389	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2390	return VINF_SUCCESS;
2391	}
2392
2393
2394	/**
2395	* Callback to patch a TPR instruction (jump to generated code).
2396	*
2397	* @returns VBox strict status code.
2398	* @param pVM The cross context VM structure.
2399	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2400	* @param pvUser User specified CPU context.
2401	*
2402	*/
2403	static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2404	{
2405	/*
2406	* Only execute the handler on the VCPU the original patch request was
2407	* issued. (The other CPU(s) might not yet have switched to protected
2408	* mode, nor have the correct memory context.)
2409	*/
2410	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2411	if (pVCpu->idCpu != idCpu)
2412	return VINF_SUCCESS;
2413
2414	/*
2415	* We're racing other VCPUs here, so don't try patch the instruction twice
2416	* and make sure there is still room for our patch record.
2417	*/
2418	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2419	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2420	if (pPatch)
2421	{
2422	Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2423	return VINF_SUCCESS;
2424	}
2425	uint32_t const idx = pVM->hm.s.cPatches;
2426	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2427	{
2428	Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2429	return VINF_SUCCESS;
2430	}
2431	pPatch = &pVM->hm.s.aPatches[idx];
2432
2433	Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2434	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2435
2436	/*
2437	* Disassemble the instruction and get cracking.
2438	*/
2439	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2440	uint32_t cbOp;
2441	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2442	AssertRC(rc);
2443	if ( rc == VINF_SUCCESS
2444	&& pDis->pCurInstr->uOpcode == OP_MOV
2445	&& cbOp >= 5)
2446	{
2447	uint8_t aPatch[64];
2448	uint32_t off = 0;
2449
2450	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2451	AssertRC(rc);
2452
2453	pPatch->cbOp = cbOp;
2454	pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2455
2456	if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2457	{
2458	/*
2459	* TPR write:
2460	*
2461	* push ECX [51]
2462	* push EDX [52]
2463	* push EAX [50]
2464	* xor EDX,EDX [31 D2]
2465	* mov EAX,EAX [89 C0]
2466	* or
2467	* mov EAX,0000000CCh [B8 CC 00 00 00]
2468	* mov ECX,0C0000082h [B9 82 00 00 C0]
2469	* wrmsr [0F 30]
2470	* pop EAX [58]
2471	* pop EDX [5A]
2472	* pop ECX [59]
2473	* jmp return_address [E9 return_address]
2474	*/
2475	bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2476
2477	aPatch[off++] = 0x51; /* push ecx */
2478	aPatch[off++] = 0x52; /* push edx */
2479	if (!fUsesEax)
2480	aPatch[off++] = 0x50; /* push eax */
2481	aPatch[off++] = 0x31; /* xor edx, edx */
2482	aPatch[off++] = 0xd2;
2483	if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2484	{
2485	if (!fUsesEax)
2486	{
2487	aPatch[off++] = 0x89; /* mov eax, src_reg */
2488	aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2489	}
2490	}
2491	else
2492	{
2493	Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2494	aPatch[off++] = 0xb8; /* mov eax, immediate */
2495	(uint32_t )&aPatch[off] = pDis->Param2.uValue;
2496	off += sizeof(uint32_t);
2497	}
2498	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2499	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2500	off += sizeof(uint32_t);
2501
2502	aPatch[off++] = 0x0f; /* wrmsr */
2503	aPatch[off++] = 0x30;
2504	if (!fUsesEax)
2505	aPatch[off++] = 0x58; /* pop eax */
2506	aPatch[off++] = 0x5a; /* pop edx */
2507	aPatch[off++] = 0x59; /* pop ecx */
2508	}
2509	else
2510	{
2511	/*
2512	* TPR read:
2513	*
2514	* push ECX [51]
2515	* push EDX [52]
2516	* push EAX [50]
2517	* mov ECX,0C0000082h [B9 82 00 00 C0]
2518	* rdmsr [0F 32]
2519	* mov EAX,EAX [89 C0]
2520	* pop EAX [58]
2521	* pop EDX [5A]
2522	* pop ECX [59]
2523	* jmp return_address [E9 return_address]
2524	*/
2525	Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2526
2527	if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2528	aPatch[off++] = 0x51; /* push ecx */
2529	if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2530	aPatch[off++] = 0x52; /* push edx */
2531	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2532	aPatch[off++] = 0x50; /* push eax */
2533
2534	aPatch[off++] = 0x31; /* xor edx, edx */
2535	aPatch[off++] = 0xd2;
2536
2537	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2538	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2539	off += sizeof(uint32_t);
2540
2541	aPatch[off++] = 0x0f; /* rdmsr */
2542	aPatch[off++] = 0x32;
2543
2544	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2545	{
2546	aPatch[off++] = 0x89; /* mov dst_reg, eax */
2547	aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2548	}
2549
2550	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2551	aPatch[off++] = 0x58; /* pop eax */
2552	if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2553	aPatch[off++] = 0x5a; /* pop edx */
2554	if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2555	aPatch[off++] = 0x59; /* pop ecx */
2556	}
2557	aPatch[off++] = 0xe9; /* jmp return_address */
2558	(RTRCUINTPTR )&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2559	off += sizeof(RTRCUINTPTR);
2560
2561	if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2562	{
2563	/* Write new code to the patch buffer. */
2564	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2565	AssertRC(rc);
2566
2567	#ifdef LOG_ENABLED
2568	uint32_t cbCurInstr;
2569	for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2570	GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2571	GCPtrInstr += RT_MAX(cbCurInstr, 1))
2572	{
2573	char szOutput[256];
2574	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2575	szOutput, sizeof(szOutput), &cbCurInstr);
2576	if (RT_SUCCESS(rc))
2577	Log(("Patch instr %s\n", szOutput));
2578	else
2579	Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2580	}
2581	#endif
2582
2583	pPatch->aNewOpcode[0] = 0xE9;
2584	(RTRCUINTPTR )&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2585
2586	/* Overwrite the TPR instruction with a jump. */
2587	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2588	AssertRC(rc);
2589
2590	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2591
2592	pVM->hm.s.pFreeGuestPatchMem += off;
2593	pPatch->cbNewOp = 5;
2594
2595	pPatch->Core.Key = pCtx->eip;
2596	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2597	AssertRC(rc);
2598
2599	pVM->hm.s.cPatches++;
2600	pVM->hm.s.fTPRPatchingActive = true;
2601	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2602	return VINF_SUCCESS;
2603	}
2604
2605	Log(("Ran out of space in our patch buffer!\n"));
2606	}
2607	else
2608	Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2609
2610
2611	/*
2612	* Save invalid patch, so we will not try again.
2613	*/
2614	pPatch = &pVM->hm.s.aPatches[idx];
2615	pPatch->Core.Key = pCtx->eip;
2616	pPatch->enmType = HMTPRINSTR_INVALID;
2617	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2618	AssertRC(rc);
2619	pVM->hm.s.cPatches++;
2620	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2621	return VINF_SUCCESS;
2622	}
2623
2624
2625	/**
2626	* Attempt to patch TPR mmio instructions.
2627	*
2628	* @returns VBox status code.
2629	* @param pVM The cross context VM structure.
2630	* @param pVCpu The cross context virtual CPU structure.
2631	*/
2632	VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2633	{
2634	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2635	pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2636	(void *)(uintptr_t)pVCpu->idCpu);
2637	AssertRC(rc);
2638	return rc;
2639	}
2640
2641
2642	/**
2643	* Checks if we need to reschedule due to VMM device heap changes.
2644	*
2645	* @returns true if a reschedule is required, otherwise false.
2646	* @param pVM The cross context VM structure.
2647	* @param pCtx VM execution context.
2648	*/
2649	VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCCPUMCTX pCtx)
2650	{
2651	/*
2652	* The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2653	* when the unrestricted guest execution feature is missing (VT-x only).
2654	*/
2655	if ( pVM->hm.s.vmx.fEnabled
2656	&& !pVM->hm.s.vmx.fUnrestrictedGuest
2657	&& CPUMIsGuestInRealModeEx(pCtx)
2658	&& !PDMVmmDevHeapIsEnabled(pVM))
2659	return true;
2660
2661	return false;
2662	}
2663
2664
2665	/**
2666	* Noticiation callback from DBGF when interrupt breakpoints or generic debug
2667	* event settings changes.
2668	*
2669	* DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2670	* function is just updating the VM globals.
2671	*
2672	* @param pVM The VM cross context VM structure.
2673	* @thread EMT(0)
2674	*/
2675	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2676	{
2677	/* Interrupts. */
2678	bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2679	\|\| pVM->dbgf.ro.cHardIntBreakpoints > 0;
2680
2681	/* CPU Exceptions. */
2682	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2683	!fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2684	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2685	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2686
2687	/* Common VM exits. */
2688	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2689	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2690	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2691	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2692
2693	/* Vendor specific VM exits. */
2694	if (HMR3IsVmxEnabled(pVM->pUVM))
2695	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2696	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2697	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2698	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2699	else
2700	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2701	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2702	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2703	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2704
2705	/* Done. */
2706	pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2707	}
2708
2709
2710	/**
2711	* Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2712	*
2713	* HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2714	* per CPU settings.
2715	*
2716	* @param pVM The VM cross context VM structure.
2717	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2718	*/
2719	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2720	{
2721	pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction \| pVM->hm.s.fUseDebugLoop;
2722	}
2723
2724
2725	/**
2726	* Checks if we are currently using hardware acceleration.
2727	*
2728	* @returns true if hardware acceleration is being used, otherwise false.
2729	* @param pVCpu The cross context virtual CPU structure.
2730	*/
2731	VMMR3_INT_DECL(bool) HMR3IsActive(PCVMCPU pVCpu)
2732	{
2733	return pVCpu->hm.s.fActive;
2734	}
2735
2736
2737	/**
2738	* External interface for querying whether hardware acceleration is enabled.
2739	*
2740	* @returns true if VT-x or AMD-V is being used, otherwise false.
2741	* @param pUVM The user mode VM handle.
2742	* @sa HMIsEnabled, HMIsEnabledNotMacro.
2743	*/
2744	VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2745	{
2746	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2747	PVM pVM = pUVM->pVM;
2748	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2749	return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2750	}
2751
2752
2753	/**
2754	* External interface for querying whether VT-x is being used.
2755	*
2756	* @returns true if VT-x is being used, otherwise false.
2757	* @param pUVM The user mode VM handle.
2758	* @sa HMR3IsSvmEnabled, HMIsEnabled
2759	*/
2760	VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2761	{
2762	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2763	PVM pVM = pUVM->pVM;
2764	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2765	return pVM->hm.s.vmx.fEnabled
2766	&& pVM->hm.s.vmx.fSupported
2767	&& pVM->fHMEnabled;
2768	}
2769
2770
2771	/**
2772	* External interface for querying whether AMD-V is being used.
2773	*
2774	* @returns true if VT-x is being used, otherwise false.
2775	* @param pUVM The user mode VM handle.
2776	* @sa HMR3IsVmxEnabled, HMIsEnabled
2777	*/
2778	VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2779	{
2780	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2781	PVM pVM = pUVM->pVM;
2782	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2783	return pVM->hm.s.svm.fEnabled
2784	&& pVM->hm.s.svm.fSupported
2785	&& pVM->fHMEnabled;
2786	}
2787
2788
2789	/**
2790	* Checks if we are currently using nested paging.
2791	*
2792	* @returns true if nested paging is being used, otherwise false.
2793	* @param pUVM The user mode VM handle.
2794	*/
2795	VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2796	{
2797	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2798	PVM pVM = pUVM->pVM;
2799	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2800	return pVM->hm.s.fNestedPaging;
2801	}
2802
2803
2804	/**
2805	* Checks if virtualized APIC registers is enabled.
2806	*
2807	* When enabled this feature allows the hardware to access most of the
2808	* APIC registers in the virtual-APIC page without causing VM-exits. See
2809	* Intel spec. 29.1.1 "Virtualized APIC Registers".
2810	*
2811	* @returns true if virtualized APIC registers is enabled, otherwise
2812	* false.
2813	* @param pUVM The user mode VM handle.
2814	*/
2815	VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
2816	{
2817	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2818	PVM pVM = pUVM->pVM;
2819	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2820	return pVM->hm.s.fVirtApicRegs;
2821	}
2822
2823
2824	/**
2825	* Checks if APIC posted-interrupt processing is enabled.
2826	*
2827	* This returns whether we can deliver interrupts to the guest without
2828	* leaving guest-context by updating APIC state from host-context.
2829	*
2830	* @returns true if APIC posted-interrupt processing is enabled,
2831	* otherwise false.
2832	* @param pUVM The user mode VM handle.
2833	*/
2834	VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2835	{
2836	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2837	PVM pVM = pUVM->pVM;
2838	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2839	return pVM->hm.s.fPostedIntrs;
2840	}
2841
2842
2843	/**
2844	* Checks if we are currently using VPID in VT-x mode.
2845	*
2846	* @returns true if VPID is being used, otherwise false.
2847	* @param pUVM The user mode VM handle.
2848	*/
2849	VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2850	{
2851	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2852	PVM pVM = pUVM->pVM;
2853	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2854	return pVM->hm.s.vmx.fVpid;
2855	}
2856
2857
2858	/**
2859	* Checks if we are currently using VT-x unrestricted execution,
2860	* aka UX.
2861	*
2862	* @returns true if UX is being used, otherwise false.
2863	* @param pUVM The user mode VM handle.
2864	*/
2865	VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2866	{
2867	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2868	PVM pVM = pUVM->pVM;
2869	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2870	return pVM->hm.s.vmx.fUnrestrictedGuest
2871	\|\| pVM->hm.s.svm.fSupported;
2872	}
2873
2874
2875	/**
2876	* Checks if the VMX-preemption timer is being used.
2877	*
2878	* @returns true if the VMX-preemption timer is being used, otherwise false.
2879	* @param pVM The cross context VM structure.
2880	*/
2881	VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2882	{
2883	return HMIsEnabled(pVM)
2884	&& pVM->hm.s.vmx.fEnabled
2885	&& pVM->hm.s.vmx.fUsePreemptTimer;
2886	}
2887
2888
2889	/**
2890	* Helper for HMR3CheckError to log VMCS controls to the release log.
2891	*
2892	* @param idCpu The Virtual CPU ID.
2893	* @param pVmcsInfo The VMCS info. object.
2894	*/
2895	static void hmR3CheckErrorLogVmcsCtls(VMCPUID idCpu, PCVMXVMCSINFO pVmcsInfo)
2896	{
2897	LogRel(("HM: CPU[%u] PinCtls %#RX32\n", idCpu, pVmcsInfo->u32PinCtls));
2898	{
2899	uint32_t const u32Val = pVmcsInfo->u32PinCtls;
2900	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
2901	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
2902	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
2903	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
2904	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
2905	}
2906	LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls));
2907	{
2908	uint32_t const u32Val = pVmcsInfo->u32ProcCtls;
2909	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
2910	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
2911	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
2912	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
2913	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
2914	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
2915	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
2916	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
2917	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
2918	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
2919	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
2920	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
2921	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
2922	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
2923	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
2924	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
2925	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
2926	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
2927	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
2928	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
2929	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
2930	}
2931	LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls2));
2932	{
2933	uint32_t const u32Val = pVmcsInfo->u32ProcCtls2;
2934	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
2935	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
2936	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
2937	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
2938	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
2939	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
2940	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
2941	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST );
2942	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
2943	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
2944	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
2945	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
2946	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
2947	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
2948	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
2949	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
2950	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
2951	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
2952	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_VE );
2953	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
2954	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
2955	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
2956	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_SPPTP_EPT );
2957	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PT_EPT );
2958	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
2959	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_USER_WAIT_PAUSE );
2960	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLV_EXIT );
2961	}
2962	LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", idCpu, pVmcsInfo->u32EntryCtls));
2963	{
2964	uint32_t const u32Val = pVmcsInfo->u32EntryCtls;
2965	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
2966	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
2967	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
2968	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
2969	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
2970	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
2971	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
2972	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR );
2973	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
2974	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR );
2975	}
2976	LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", idCpu, pVmcsInfo->u32ExitCtls));
2977	{
2978	uint32_t const u32Val = pVmcsInfo->u32ExitCtls;
2979	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
2980	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
2981	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
2982	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
2983	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
2984	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
2985	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
2986	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
2987	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
2988	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR );
2989	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT );
2990	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR );
2991	}
2992	}
2993
2994
2995	/**
2996	* Check fatal VT-x/AMD-V error and produce some meaningful
2997	* log release message.
2998	*
2999	* @param pVM The cross context VM structure.
3000	* @param iStatusCode VBox status code.
3001	*/
3002	VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3003	{
3004	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3005	{
3006	/** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3007	* might be getting inaccurate values for non-guru'ing EMTs. */
3008	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3009	PCVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
3010	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcs;
3011	switch (iStatusCode)
3012	{
3013	case VERR_VMX_INVALID_VMCS_PTR:
3014	{
3015	LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3016	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3017	LogRel(("HM: CPU[%u] Current pointer %#RHp vs %#RHp\n", idCpu, pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs,
3018	pVmcsInfo->HCPhysVmcs));
3019	LogRel(("HM: CPU[%u] Current VMCS version %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
3020	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3021	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3022	break;
3023	}
3024
3025	case VERR_VMX_UNABLE_TO_START_VM:
3026	{
3027	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3028	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3029	LogRel(("HM: CPU[%u] Instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
3030	LogRel(("HM: CPU[%u] Exit reason %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3031
3032	if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
3033	\|\| pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
3034	{
3035	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3036	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3037	}
3038	else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
3039	{
3040	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3041	LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
3042	LogRel(("HM: CPU[%u] HCPhysGuestMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrLoad));
3043	LogRel(("HM: CPU[%u] HCPhysGuestMsrStore %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrStore));
3044	LogRel(("HM: CPU[%u] HCPhysHostMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysHostMsrLoad));
3045	LogRel(("HM: CPU[%u] cEntryMsrLoad %u\n", idCpu, pVmcsInfo->cEntryMsrLoad));
3046	LogRel(("HM: CPU[%u] cExitMsrStore %u\n", idCpu, pVmcsInfo->cExitMsrStore));
3047	LogRel(("HM: CPU[%u] cExitMsrLoad %u\n", idCpu, pVmcsInfo->cExitMsrLoad));
3048	}
3049	/** @todo Log VM-entry event injection control fields
3050	* VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3051	* and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3052	break;
3053	}
3054
3055	case VERR_VMX_INVALID_GUEST_STATE:
3056	{
3057	LogRel(("HM: VERR_VMX_INVALID_GUEST_STATE:\n"));
3058	LogRel(("HM: CPU[%u] HM error = %#RX32\n", idCpu, pVCpu->hm.s.u32HMError));
3059	LogRel(("HM: CPU[%u] Guest-intr. state = %#RX32\n", idCpu, pVCpu->hm.s.vmx.LastError.u32GuestIntrState));
3060	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3061	break;
3062	}
3063
3064	/* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3065	case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3066	case VERR_VMX_INVALID_VMXON_PTR:
3067	case VERR_VMX_UNEXPECTED_EXIT:
3068	case VERR_VMX_INVALID_VMCS_FIELD:
3069	case VERR_SVM_UNKNOWN_EXIT:
3070	case VERR_SVM_UNEXPECTED_EXIT:
3071	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3072	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3073	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3074	break;
3075	}
3076	}
3077
3078	if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3079	{
3080	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1));
3081	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed0));
3082	}
3083	else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3084	LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
3085	}
3086
3087
3088	/**
3089	* Execute state save operation.
3090	*
3091	* Save only data that cannot be re-loaded while entering HM ring-0 code. This
3092	* is because we always save the VM state from ring-3 and thus most HM state
3093	* will be re-synced dynamically at runtime and don't need to be part of the VM
3094	* saved state.
3095	*
3096	* @returns VBox status code.
3097	* @param pVM The cross context VM structure.
3098	* @param pSSM SSM operation handle.
3099	*/
3100	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3101	{
3102	Log(("hmR3Save:\n"));
3103
3104	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3105	{
3106	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3107	Assert(!pVCpu->hm.s.Event.fPending);
3108	if (pVM->cpum.ro.GuestFeatures.fSvm)
3109	{
3110	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3111	SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3112	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3113	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3114	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3115	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3116	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3117	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3118	SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3119	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3120	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3121	SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3122	SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3123	SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3124	}
3125	}
3126
3127	/* Save the guest patch data. */
3128	SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3129	SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3130	SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3131
3132	/* Store all the guest patch records too. */
3133	int rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3134	if (RT_FAILURE(rc))
3135	return rc;
3136
3137	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3138	{
3139	AssertCompileSize(HMTPRINSTR, 4);
3140	PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3141	SSMR3PutU32(pSSM, pPatch->Core.Key);
3142	SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3143	SSMR3PutU32(pSSM, pPatch->cbOp);
3144	SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3145	SSMR3PutU32(pSSM, pPatch->cbNewOp);
3146	SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3147	SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3148	SSMR3PutU32(pSSM, pPatch->uDstOperand);
3149	SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3150	rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3151	if (RT_FAILURE(rc))
3152	return rc;
3153	}
3154
3155	return VINF_SUCCESS;
3156	}
3157
3158
3159	/**
3160	* Execute state load operation.
3161	*
3162	* @returns VBox status code.
3163	* @param pVM The cross context VM structure.
3164	* @param pSSM SSM operation handle.
3165	* @param uVersion Data layout version.
3166	* @param uPass The data pass.
3167	*/
3168	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3169	{
3170	int rc;
3171
3172	LogFlowFunc(("uVersion=%u\n", uVersion));
3173	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3174
3175	/*
3176	* Validate version.
3177	*/
3178	if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3179	&& uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3180	&& uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3181	&& uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3182	{
3183	AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3184	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3185	}
3186
3187	/*
3188	* Load per-VCPU state.
3189	*/
3190	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3191	{
3192	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3193	if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3194	{
3195	/* Load the SVM nested hw.virt state if the VM is configured for it. */
3196	if (pVM->cpum.ro.GuestFeatures.fSvm)
3197	{
3198	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3199	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3200	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3201	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3202	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3203	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3204	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3205	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3206	SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3207	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3208	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3209	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3210	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3211	rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3212	AssertRCReturn(rc, rc);
3213	}
3214	}
3215	else
3216	{
3217	/* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3218	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.fPending);
3219	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.u32ErrCode);
3220	SSMR3GetU64(pSSM, &pVCpu->hm.s.Event.u64IntInfo);
3221
3222	/* VMX fWasInRealMode related data. */
3223	uint32_t uDummy;
3224	SSMR3GetU32(pSSM, &uDummy);
3225	SSMR3GetU32(pSSM, &uDummy);
3226	rc = SSMR3GetU32(pSSM, &uDummy);
3227	AssertRCReturn(rc, rc);
3228	}
3229	}
3230
3231	/*
3232	* Load TPR patching data.
3233	*/
3234	if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3235	{
3236	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3237	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3238	SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3239
3240	/* Fetch all TPR patch records. */
3241	rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3242	AssertRCReturn(rc, rc);
3243	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3244	{
3245	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3246	SSMR3GetU32(pSSM, &pPatch->Core.Key);
3247	SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3248	SSMR3GetU32(pSSM, &pPatch->cbOp);
3249	SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3250	SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3251	SSM_GET_ENUM32_RET(pSSM, pPatch->enmType, HMTPRINSTR);
3252
3253	if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3254	pVM->hm.s.fTPRPatchingActive = true;
3255	Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT \|\| pVM->hm.s.fTPRPatchingActive == false);
3256
3257	SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3258	SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3259	SSMR3GetU32(pSSM, &pPatch->cFaults);
3260	rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3261	AssertRCReturn(rc, rc);
3262
3263	LogFlow(("hmR3Load: patch %d\n", i));
3264	LogFlow(("Key = %x\n", pPatch->Core.Key));
3265	LogFlow(("cbOp = %d\n", pPatch->cbOp));
3266	LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3267	LogFlow(("type = %d\n", pPatch->enmType));
3268	LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3269	LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3270	LogFlow(("cFaults = %d\n", pPatch->cFaults));
3271	LogFlow(("target = %x\n", pPatch->pJumpTarget));
3272
3273	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3274	AssertRCReturn(rc, rc);
3275	}
3276	}
3277
3278	return VINF_SUCCESS;
3279	}
3280
3281
3282	/**
3283	* Displays HM info.
3284	*
3285	* @param pVM The cross context VM structure.
3286	* @param pHlp The info helper functions.
3287	* @param pszArgs Arguments, ignored.
3288	*/
3289	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3290	{
3291	NOREF(pszArgs);
3292	PVMCPU pVCpu = VMMGetCpu(pVM);
3293	if (!pVCpu)
3294	pVCpu = pVM->apCpusR3[0];
3295
3296	if (HMIsEnabled(pVM))
3297	{
3298	if (pVM->hm.s.vmx.fSupported)
3299	pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3300	else
3301	pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3302	pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3303	pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3304	if (pVM->hm.s.vmx.fSupported)
3305	{
3306	PCVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
3307	bool const fRealOnV86Active = pVmcsInfo->RealMode.fRealOnV86Active;
3308	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcs;
3309
3310	pHlp->pfnPrintf(pHlp, " %s VMCS active\n", fNstGstVmcsActive ? "Nested-guest" : "Guest");
3311	pHlp->pfnPrintf(pHlp, " Real-on-v86 active = %RTbool\n", fRealOnV86Active);
3312	if (fRealOnV86Active)
3313	{
3314	pHlp->pfnPrintf(pHlp, " EFlags = %#x\n", pVmcsInfo->RealMode.Eflags.u32);
3315	pHlp->pfnPrintf(pHlp, " Attr CS = %#x\n", pVmcsInfo->RealMode.AttrCS.u);
3316	pHlp->pfnPrintf(pHlp, " Attr SS = %#x\n", pVmcsInfo->RealMode.AttrSS.u);
3317	pHlp->pfnPrintf(pHlp, " Attr DS = %#x\n", pVmcsInfo->RealMode.AttrDS.u);
3318	pHlp->pfnPrintf(pHlp, " Attr ES = %#x\n", pVmcsInfo->RealMode.AttrES.u);
3319	pHlp->pfnPrintf(pHlp, " Attr FS = %#x\n", pVmcsInfo->RealMode.AttrFS.u);
3320	pHlp->pfnPrintf(pHlp, " Attr GS = %#x\n", pVmcsInfo->RealMode.AttrGS.u);
3321	}
3322	}
3323	}
3324	else
3325	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3326	}
3327
3328
3329	/**
3330	* Displays the HM Last-Branch-Record info. for the guest.
3331	*
3332	* @param pVM The cross context VM structure.
3333	* @param pHlp The info helper functions.
3334	* @param pszArgs Arguments, ignored.
3335	*/
3336	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3337	{
3338	NOREF(pszArgs);
3339	PVMCPU pVCpu = VMMGetCpu(pVM);
3340	if (!pVCpu)
3341	pVCpu = pVM->apCpusR3[0];
3342
3343	if (!HMIsEnabled(pVM))
3344	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3345
3346	if (HMIsVmxActive(pVM))
3347	{
3348	if (pVM->hm.s.vmx.fLbr)
3349	{
3350	PCVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
3351	uint32_t const cLbrStack = pVM->hm.s.vmx.idLbrFromIpMsrLast - pVM->hm.s.vmx.idLbrFromIpMsrFirst + 1;
3352
3353	/** @todo r=ramshankar: The index technically varies depending on the CPU, but
3354	* 0xf should cover everything we support thus far. Fix if necessary
3355	* later. */
3356	uint32_t const idxTopOfStack = pVmcsInfo->u64LbrTosMsr & 0xf;
3357	if (idxTopOfStack > cLbrStack)
3358	{
3359	pHlp->pfnPrintf(pHlp, "Top-of-stack LBR MSR seems corrupt (index=%u, msr=%#RX64) expected index < %u\n",
3360	idxTopOfStack, pVmcsInfo->u64LbrTosMsr, cLbrStack);
3361	return;
3362	}
3363
3364	/*
3365	* Dump the circular buffer of LBR records starting from the most recent record (contained in idxTopOfStack).
3366	*/
3367	pHlp->pfnPrintf(pHlp, "CPU[%u]: LBRs (most-recent first)\n", pVCpu->idCpu);
3368	uint32_t idxCurrent = idxTopOfStack;
3369	Assert(idxTopOfStack < cLbrStack);
3370	Assert(RT_ELEMENTS(pVmcsInfo->au64LbrFromIpMsr) <= cLbrStack);
3371	Assert(RT_ELEMENTS(pVmcsInfo->au64LbrToIpMsr) <= cLbrStack);
3372	for (;;)
3373	{
3374	if (pVM->hm.s.vmx.idLbrToIpMsrFirst)
3375	{
3376	pHlp->pfnPrintf(pHlp, " Branch (%2u): From IP=%#016RX64 - To IP=%#016RX64\n", idxCurrent,
3377	pVmcsInfo->au64LbrFromIpMsr[idxCurrent], pVmcsInfo->au64LbrToIpMsr[idxCurrent]);
3378	}
3379	else
3380	pHlp->pfnPrintf(pHlp, " Branch (%2u): LBR=%#RX64\n", idxCurrent, pVmcsInfo->au64LbrFromIpMsr[idxCurrent]);
3381
3382	idxCurrent = (idxCurrent - 1) % cLbrStack;
3383	if (idxCurrent == idxTopOfStack)
3384	break;
3385	}
3386	}
3387	else
3388	pHlp->pfnPrintf(pHlp, "VM not configured to record LBRs for the guest\n");
3389	}
3390	else
3391	{
3392	Assert(HMIsSvmActive(pVM));
3393	/** @todo SVM: LBRs (get them from VMCB if possible). */
3394	pHlp->pfnPrintf(pHlp, "SVM LBR not implemented in VM debugger yet\n");
3395	}
3396	}
3397
3398
3399	/**
3400	* Displays the HM pending event.
3401	*
3402	* @param pVM The cross context VM structure.
3403	* @param pHlp The info helper functions.
3404	* @param pszArgs Arguments, ignored.
3405	*/
3406	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3407	{
3408	NOREF(pszArgs);
3409	PVMCPU pVCpu = VMMGetCpu(pVM);
3410	if (!pVCpu)
3411	pVCpu = pVM->apCpusR3[0];
3412
3413	if (HMIsEnabled(pVM))
3414	{
3415	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3416	if (pVCpu->hm.s.Event.fPending)
3417	{
3418	pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3419	pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3420	pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3421	pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3422	}
3423	}
3424	else
3425	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3426	}
3427
3428
3429	/**
3430	* Displays the SVM nested-guest VMCB cache.
3431	*
3432	* @param pVM The cross context VM structure.
3433	* @param pHlp The info helper functions.
3434	* @param pszArgs Arguments, ignored.
3435	*/
3436	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3437	{
3438	NOREF(pszArgs);
3439	PVMCPU pVCpu = VMMGetCpu(pVM);
3440	if (!pVCpu)
3441	pVCpu = pVM->apCpusR3[0];
3442
3443	bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3444	if ( fSvmEnabled
3445	&& pVM->cpum.ro.GuestFeatures.fSvm)
3446	{
3447	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3448	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3449	pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3450	pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3451	pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3452	pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3453	pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3454	pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3455	pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3456	pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3457	pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3458	pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3459	pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3460	pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3461	pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3462	}
3463	else
3464	{
3465	if (!fSvmEnabled)
3466	pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3467	else
3468	pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3469	}
3470	}
3471

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source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 86473

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