VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 47682

Last change on this file since 47682 was 47681, checked in by vboxsync, 11 years ago

VMM: I/O breakpoints.
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File size: 134.7 KB
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1/* $Id: HM.cpp 47681 2013-08-12 22:51:55Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_HM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/vmm/mm.h>
26#include <VBox/vmm/pdmapi.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/ssm.h>
29#include <VBox/vmm/trpm.h>
30#include <VBox/vmm/dbgf.h>
31#include <VBox/vmm/iom.h>
32#include <VBox/vmm/patm.h>
33#include <VBox/vmm/csam.h>
34#include <VBox/vmm/selm.h>
35#ifdef VBOX_WITH_REM
36# include <VBox/vmm/rem.h>
37#endif
38#include <VBox/vmm/hm_vmx.h>
39#include <VBox/vmm/hm_svm.h>
40#include "HMInternal.h"
41#include <VBox/vmm/vm.h>
42#include <VBox/vmm/uvm.h>
43#include <VBox/err.h>
44#include <VBox/param.h>
45
46#include <iprt/assert.h>
47#include <VBox/log.h>
48#include <iprt/asm.h>
49#include <iprt/asm-amd64-x86.h>
50#include <iprt/string.h>
51#include <iprt/env.h>
52#include <iprt/thread.h>
53
54
55/*******************************************************************************
56* Global Variables *
57*******************************************************************************/
58#ifdef VBOX_WITH_STATISTICS
59# define EXIT_REASON(def, val, str) #def " - " #val " - " str
60# define EXIT_REASON_NIL() NULL
61/** Exit reason descriptions for VT-x, used to describe statistics. */
62static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
63{
64 EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
65 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
66 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
67 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
68 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
69 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
70 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
71 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
72 EXIT_REASON_NIL(),
73 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
74 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest attempted to execute CPUID."),
75 EXIT_REASON_NIL(),
76 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest attempted to execute HLT."),
77 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest attempted to execute INVD."),
78 EXIT_REASON(VMX_EXIT_INVLPG , 14, "Guest attempted to execute INVLPG."),
79 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest attempted to execute RDPMC."),
80 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest attempted to execute RDTSC."),
81 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest attempted to execute RSM in SMM."),
82 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest attempted to execute VMCALL."),
83 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest attempted to execute VMCLEAR."),
84 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest attempted to execute VMLAUNCH."),
85 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest attempted to execute VMPTRLD."),
86 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest attempted to execute VMPTRST."),
87 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest attempted to execute VMREAD."),
88 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest attempted to execute VMRESUME."),
89 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest attempted to execute VMWRITE."),
90 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest attempted to execute VMXOFF."),
91 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest attempted to execute VMXON."),
92 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
93 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
94 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
95 EXIT_REASON(VMX_EXIT_RDMSR , 31, "Guest attempted to execute RDMSR."),
96 EXIT_REASON(VMX_EXIT_WRMSR , 32, "Guest attempted to execute WRMSR."),
97 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
98 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
99 EXIT_REASON_NIL(),
100 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest executed MWAIT."),
101 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
102 EXIT_REASON_NIL(),
103 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest attempted to execute MONITOR."),
104 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest attempted to execute PAUSE."),
105 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
106 EXIT_REASON_NIL(),
107 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD, 43, "TPR below threshold. Guest attempted to execute MOV to CR8."),
108 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest attempted to access memory at a physical address on the APIC-access page."),
109 EXIT_REASON_NIL(),
110 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest attempted to execute LGDT, LIDT, SGDT, or SIDT."),
111 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest attempted to execute LLDT, LTR, SLDT, or STR."),
112 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
113 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
114 EXIT_REASON(VMX_EXIT_INVEPT , 50, "Guest attempted to execute INVEPT."),
115 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "Guest attempted to execute RDTSCP."),
116 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
117 EXIT_REASON(VMX_EXIT_INVVPID , 53, "Guest attempted to execute INVVPID."),
118 EXIT_REASON(VMX_EXIT_WBINVD , 54, "Guest attempted to execute WBINVD."),
119 EXIT_REASON(VMX_EXIT_XSETBV , 55, "Guest attempted to execute XSETBV."),
120 EXIT_REASON_NIL(),
121 EXIT_REASON(VMX_EXIT_RDRAND , 57, "Guest attempted to execute RDRAND."),
122 EXIT_REASON(VMX_EXIT_INVPCID , 58, "Guest attempted to execute INVPCID."),
123 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "Guest attempted to execute VMFUNC.")
124};
125/** Exit reason descriptions for AMD-V, used to describe statistics. */
126static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
127{
128 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
129 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
130 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
131 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
132 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
133 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
134 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
135 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
136 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
137 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
138 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
139 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
140 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
141 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
142 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
143 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
154 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
155 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
156 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
157 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
158 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
159 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
160 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
161 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
162 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
163 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
164 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
165 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
166 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
167 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
168 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
169 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
170 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
171 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
172 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
173 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
174 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
175 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
186 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
187 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
188 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
189 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
190 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
191 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (#DE)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (#DB)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (#NMI)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (#BP)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (#OF)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (#BR)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (#UD)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (#NM)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (#DF)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (#CO_SEG_OVERRUN)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (#TS)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (#NP)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (#SS)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (#GP)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (#PF)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0x0f)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (#MF)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (#AC)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (#MC)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (#XF)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
224 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
225 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
226 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
227 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
228 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt-window exit."),
229 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
230 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
231 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
232 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
233 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
234 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
235 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
236 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
237 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
238 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
239 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
240 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
241 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
242 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
243 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
244 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
245 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
246 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
247 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
248 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
249 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
250 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
251 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port."),
252 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
253 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
254 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "Legacy FPU handling enabled; processor is frozen in an x87/mmx instruction waiting for an interrupt"),
255 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
256 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
257 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
258 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
259 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
260 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
261 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
262 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
263 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
264 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
265 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
266 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
267 EXIT_REASON(SVM_EXIT_MWAIT ,139, "MWAIT instruction."),
268 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
269 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging fault."),
270 EXIT_REASON_NIL()
271};
272# undef EXIT_REASON
273# undef EXIT_REASON_NIL
274#endif /* VBOX_WITH_STATISTICS */
275
276#define HMVMX_REPORT_FEATURE(allowed1, disallowed0, featflag) \
277 do { \
278 if ((allowed1) & (featflag)) \
279 LogRel(("HM: " #featflag "\n")); \
280 else \
281 LogRel(("HM: " #featflag " *must* be cleared\n")); \
282 if ((disallowed0) & (featflag)) \
283 LogRel(("HM: " #featflag " *must* be set\n")); \
284 } while (0)
285
286#define HMVMX_REPORT_ALLOWED_FEATURE(allowed1, featflag) \
287 do { \
288 if ((allowed1) & (featflag)) \
289 LogRel(("HM: " #featflag "\n")); \
290 else \
291 LogRel(("HM: " #featflag " not supported\n")); \
292 } while (0)
293
294#define HMVMX_REPORT_CAPABILITY(msrcaps, cap) \
295 do { \
296 if ((msrcaps) & (cap)) \
297 LogRel(("HM: " #cap "\n")); \
298 } while (0)
299
300
301/*******************************************************************************
302* Internal Functions *
303*******************************************************************************/
304static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
305static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
306static int hmR3InitCPU(PVM pVM);
307static int hmR3InitFinalizeR0(PVM pVM);
308static int hmR3InitFinalizeR0Intel(PVM pVM);
309static int hmR3InitFinalizeR0Amd(PVM pVM);
310static int hmR3TermCPU(PVM pVM);
311
312
313
314/**
315 * Initializes the HM.
316 *
317 * This reads the config and check whether VT-x or AMD-V hardware is available
318 * if configured to use it. This is one of the very first components to be
319 * initialized after CFGM, so that we can fall back to raw-mode early in the
320 * initialization process.
321 *
322 * Note that a lot of the set up work is done in ring-0 and thus postponed till
323 * the ring-3 and ring-0 callback to HMR3InitCompleted.
324 *
325 * @returns VBox status code.
326 * @param pVM Pointer to the VM.
327 *
328 * @remarks Be careful with what we call here, since most of the VMM components
329 * are uninitialized.
330 */
331VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
332{
333 LogFlow(("HMR3Init\n"));
334
335 /*
336 * Assert alignment and sizes.
337 */
338 AssertCompileMemberAlignment(VM, hm.s, 32);
339 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
340
341 /*
342 * Register the saved state data unit.
343 */
344 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SSM_VERSION, sizeof(HM),
345 NULL, NULL, NULL,
346 NULL, hmR3Save, NULL,
347 NULL, hmR3Load, NULL);
348 if (RT_FAILURE(rc))
349 return rc;
350
351 /*
352 * Misc initialisation.
353 */
354 //pVM->hm.s.vmx.fSupported = false;
355 //pVM->hm.s.svm.fSupported = false;
356 //pVM->hm.s.vmx.fEnabled = false;
357 //pVM->hm.s.svm.fEnabled = false;
358 //pVM->hm.s.fNestedPaging = false;
359
360
361 /*
362 * Read configuration.
363 */
364 PCFGMNODE pCfgHM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
365
366 /** @cfgm{/HM/HMForced, bool, false}
367 * Forces hardware virtualization, no falling back on raw-mode. HM must be
368 * enabled, i.e. /HMEnabled must be true. */
369 bool fHMForced;
370#ifdef VBOX_WITH_RAW_MODE
371 rc = CFGMR3QueryBoolDef(pCfgHM, "HMForced", &fHMForced, false);
372 AssertRCReturn(rc, rc);
373 AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
374 VERR_INVALID_PARAMETER);
375# if defined(RT_OS_DARWIN)
376 if (pVM->fHMEnabled)
377 fHMForced = true;
378# endif
379 AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
380 VERR_INVALID_PARAMETER);
381 if (pVM->cCpus > 1)
382 fHMForced = true;
383#else /* !VBOX_WITH_RAW_MODE */
384 AssertRelease(pVM->fHMEnabled);
385 fHMForced = true;
386#endif /* !VBOX_WITH_RAW_MODE */
387
388 /** @cfgm{/HM/EnableNestedPaging, bool, false}
389 * Enables nested paging (aka extended page tables). */
390 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
391 AssertRCReturn(rc, rc);
392
393 /** @cfgm{/HM/EnableUX, bool, true}
394 * Enables the VT-x unrestricted execution feature. */
395 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
396 AssertRCReturn(rc, rc);
397
398 /** @cfgm{/HM/EnableLargePages, bool, false}
399 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
400 * page table walking and maybe better TLB hit rate in some cases. */
401 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableLargePages", &pVM->hm.s.fLargePages, false);
402 AssertRCReturn(rc, rc);
403
404 /** @cfgm{/HM/EnableVPID, bool, false}
405 * Enables the VT-x VPID feature. */
406 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
407 AssertRCReturn(rc, rc);
408
409 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
410 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
411 rc = CFGMR3QueryBoolDef(pCfgHM, "TPRPatchingEnabled", &pVM->hm.s.fTRPPatchingAllowed, false);
412 AssertRCReturn(rc, rc);
413
414 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
415 * Enables AMD64 cpu features.
416 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
417 * already have the support. */
418#ifdef VBOX_ENABLE_64_BITS_GUESTS
419 rc = CFGMR3QueryBoolDef(pCfgHM, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
420 AssertLogRelRCReturn(rc, rc);
421#else
422 pVM->hm.s.fAllow64BitGuests = false;
423#endif
424
425 /** @cfgm{/HM/Exclusive, bool}
426 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
427 * global init for each host CPU. If false, we do local init each time we wish
428 * to execute guest code.
429 *
430 * Default is false for Mac OS X and Windows due to the higher risk of conflicts
431 * with other hypervisors.
432 */
433 rc = CFGMR3QueryBoolDef(pCfgHM, "Exclusive", &pVM->hm.s.fGlobalInit,
434#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
435 false
436#else
437 true
438#endif
439 );
440 AssertLogRelRCReturn(rc, rc);
441
442 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
443 * The number of times to resume guest execution before we forcibly return to
444 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
445 * determines the default value. */
446 rc = CFGMR3QueryU32Def(pCfgHM, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
447 AssertLogRelRCReturn(rc, rc);
448
449 /*
450 * Check if VT-x or AMD-v support according to the users wishes.
451 */
452 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
453 * VERR_SVM_IN_USE. */
454 if (pVM->fHMEnabled)
455 {
456 uint32_t fCaps;
457 rc = SUPR3QueryVTCaps(&fCaps);
458 if (RT_SUCCESS(rc))
459 {
460 if (fCaps & SUPVTCAPS_AMD_V)
461 LogRel(("HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
462 else if (fCaps & SUPVTCAPS_VT_X)
463 {
464 rc = SUPR3QueryVTxSupported();
465 if (RT_SUCCESS(rc))
466 LogRel(("HMR3Init: VT-x%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
467 else
468 {
469#ifdef RT_OS_LINUX
470 const char *pszMinReq = " Linux 2.6.13 or newer required!";
471#else
472 const char *pszMinReq = "";
473#endif
474 if (fHMForced)
475 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x.%s\n", pszMinReq);
476
477 /* Fall back to raw-mode. */
478 LogRel(("HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x.%s\n", pszMinReq));
479 pVM->fHMEnabled = false;
480 }
481 }
482 else
483 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
484 VERR_INTERNAL_ERROR_5);
485
486 /*
487 * Do we require a little bit or raw-mode for 64-bit guest execution?
488 */
489 pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
490 && pVM->fHMEnabled
491 && pVM->hm.s.fAllow64BitGuests;
492 }
493 else
494 {
495 const char *pszMsg;
496 switch (rc)
497 {
498 case VERR_UNSUPPORTED_CPU:
499 pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained.";
500 break;
501
502 case VERR_VMX_NO_VMX:
503 pszMsg = "VT-x is not available.";
504 break;
505
506 case VERR_VMX_MSR_LOCKED_OR_DISABLED:
507 pszMsg = "VT-x is disabled in the BIOS (or by the host OS).";
508 break;
509
510 case VERR_SVM_NO_SVM:
511 pszMsg = "AMD-V is not available.";
512 break;
513
514 case VERR_SVM_DISABLED:
515 pszMsg = "AMD-V is disabled in the BIOS (or by the host OS).";
516 break;
517
518 default:
519 pszMsg = NULL;
520 break;
521 }
522 if (fHMForced && pszMsg)
523 return VM_SET_ERROR(pVM, rc, pszMsg);
524 if (!pszMsg)
525 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
526
527 /* Fall back to raw-mode. */
528 LogRel(("HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
529 pVM->fHMEnabled = false;
530 }
531 }
532
533 /* It's now OK to use the predicate function. */
534 pVM->fHMEnabledFixed = true;
535 return VINF_SUCCESS;
536}
537
538
539/**
540 * Initializes the per-VCPU HM.
541 *
542 * @returns VBox status code.
543 * @param pVM Pointer to the VM.
544 */
545static int hmR3InitCPU(PVM pVM)
546{
547 LogFlow(("HMR3InitCPU\n"));
548
549 if (!HMIsEnabled(pVM))
550 return VINF_SUCCESS;
551
552 for (VMCPUID i = 0; i < pVM->cCpus; i++)
553 {
554 PVMCPU pVCpu = &pVM->aCpus[i];
555 pVCpu->hm.s.fActive = false;
556 }
557
558#ifdef VBOX_WITH_STATISTICS
559 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
560 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
561 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
562 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
563#endif
564
565 /*
566 * Statistics.
567 */
568 for (VMCPUID i = 0; i < pVM->cCpus; i++)
569 {
570 PVMCPU pVCpu = &pVM->aCpus[i];
571 int rc;
572
573#ifdef VBOX_WITH_STATISTICS
574 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
575 "Profiling of RTMpPokeCpu",
576 "/PROF/CPU%d/HM/Poke", i);
577 AssertRC(rc);
578 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
579 "Profiling of poke wait",
580 "/PROF/CPU%d/HM/PokeWait", i);
581 AssertRC(rc);
582 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
583 "Profiling of poke wait when RTMpPokeCpu fails",
584 "/PROF/CPU%d/HM/PokeWaitFailed", i);
585 AssertRC(rc);
586 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
587 "Profiling of VMXR0RunGuestCode entry",
588 "/PROF/CPU%d/HM/StatEntry", i);
589 AssertRC(rc);
590 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
591 "Profiling of VMXR0RunGuestCode exit part 1",
592 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
593 AssertRC(rc);
594 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
595 "Profiling of VMXR0RunGuestCode exit part 2",
596 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
597 AssertRC(rc);
598
599 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
600 "I/O",
601 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
602 AssertRC(rc);
603 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
604 "MOV CRx",
605 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
606 AssertRC(rc);
607 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
608 "Exceptions, NMIs",
609 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
610 AssertRC(rc);
611
612 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
613 "Profiling of VMXR0LoadGuestState",
614 "/PROF/CPU%d/HM/StatLoadGuestState", i);
615 AssertRC(rc);
616 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
617 "Profiling of VMLAUNCH/VMRESUME.",
618 "/PROF/CPU%d/HM/InGC", i);
619 AssertRC(rc);
620
621# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
622 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
623 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
624 "/PROF/CPU%d/HM/Switcher3264", i);
625 AssertRC(rc);
626# endif
627
628# ifdef HM_PROFILE_EXIT_DISPATCH
629 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
630 STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
631 "/PROF/CPU%d/HM/ExitDispatch", i);
632 AssertRC(rc);
633# endif
634
635#endif
636# define HM_REG_COUNTER(a, b, desc) \
637 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
638 AssertRC(rc);
639
640#ifdef VBOX_WITH_STATISTICS
641 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
642 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
643 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
644 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
645 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
646 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
647 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
648 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
649 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) execption.");
650 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
651 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
652 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
653 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
654 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
655 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
656 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg", "Guest attempted to execute INVLPG.");
657 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd", "Guest attempted to execute INVD.");
658 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd", "Guest attempted to execute WBINVD.");
659 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause", "Guest attempted to execute PAUSE.");
660 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid", "Guest attempted to execute CPUID.");
661 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc", "Guest attempted to execute RDTSC.");
662 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp", "Guest attempted to execute RDTSCP.");
663 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc", "Guest attempted to execute RDPMC.");
664 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand", "Guest attempted to execute RDRAND.");
665 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "Guest attempted to execute RDMSR.");
666 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "Guest attempted to execute WRMSR.");
667 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "Guest attempted to execute MWAIT.");
668 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "Guest attempted to execute MONITOR.");
669 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write", "Guest attempted to write a debug register.");
670 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read", "Guest attempted to read a debug register.");
671 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "Guest attempted to execute CLTS.");
672 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "Guest attempted to execute LMSW.");
673 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "Guest attempted to execute CLI.");
674 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "Guest attempted to execute STI.");
675 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "Guest attempted to execute PUSHF.");
676 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "Guest attempted to execute POPF.");
677 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "Guest attempted to execute IRET.");
678 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "Guest attempted to execute INT.");
679 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "Guest attempted to execute HLT.");
680 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "Guest attempted to access descriptor table register (GDTR, IDTR, LDTR).");
681 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
682 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
683 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
684 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
685 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
686 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMaxResume, "/HM/CPU%d/Exit/MaxResume", "Maximum VMRESUME inner-loop counter reached.");
687 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Host interrupt received.");
688#endif
689 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmi, "/HM/CPU%d/Exit/HostNmi", "Host NMI received.");
690#ifdef VBOX_WITH_STATISTICS
691 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
692 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
693 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Guest attempted a task switch.");
694 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
695 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
696
697 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
698 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
699 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
700 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
701 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
702
703 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
704 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
705 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception back to the guest.");
706
707 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
708 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
709 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
710 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
711 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
712 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
713 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
714 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
715 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
716 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
717 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
718 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
719 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
720 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
721
722 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
723 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Guest is in catchup mode, intercept TSC accesses.");
724 HM_REG_COUNTER(&pVCpu->hm.s.StatTscInterceptOverFlow, "/HM/CPU%d/TSC/InterceptOverflow", "TSC offset overflow, fallback to intercept TSC accesses.");
725
726 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
727 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
728 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
729
730 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading minimal guest-state.");
731 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading the full guest-state.");
732
733 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
734 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
735 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
736 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
737 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
738 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
739 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
740 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
741
742#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
743 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
744 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
745#endif
746
747 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
748 {
749 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
750 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
751 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
752 AssertRC(rc);
753 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
754 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
755 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
756 AssertRC(rc);
757 }
758
759#undef HM_REG_COUNTER
760
761 pVCpu->hm.s.paStatExitReason = NULL;
762
763 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hm.s.paStatExitReason), 0, MM_TAG_HM,
764 (void **)&pVCpu->hm.s.paStatExitReason);
765 AssertRC(rc);
766 if (RT_SUCCESS(rc))
767 {
768 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
769 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
770 {
771 if (papszDesc[j])
772 {
773 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
774 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
775 AssertRC(rc);
776 }
777 }
778 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
779 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
780 AssertRC(rc);
781 }
782 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
783# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
784 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
785# else
786 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
787# endif
788
789 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
790 AssertRCReturn(rc, rc);
791 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
792# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
793 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
794# else
795 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
796# endif
797 for (unsigned j = 0; j < 255; j++)
798 {
799 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
800 "Injected event.",
801 (j < 0x20) ? "/HM/CPU%d/EventInject/Event/Trap/%02X" : "/HM/CPU%d/EventInject/Event/IRQ/%02X", i, j);
802 }
803
804#endif /* VBOX_WITH_STATISTICS */
805 }
806
807#ifdef VBOX_WITH_CRASHDUMP_MAGIC
808 /*
809 * Magic marker for searching in crash dumps.
810 */
811 for (VMCPUID i = 0; i < pVM->cCpus; i++)
812 {
813 PVMCPU pVCpu = &pVM->aCpus[i];
814
815 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
816 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
817 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
818 }
819#endif
820
821 return VINF_SUCCESS;
822}
823
824
825/**
826 * Called when a init phase has completed.
827 *
828 * @returns VBox status code.
829 * @param pVM The VM.
830 * @param enmWhat The phase that completed.
831 */
832VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
833{
834 switch (enmWhat)
835 {
836 case VMINITCOMPLETED_RING3:
837 return hmR3InitCPU(pVM);
838 case VMINITCOMPLETED_RING0:
839 return hmR3InitFinalizeR0(pVM);
840 default:
841 return VINF_SUCCESS;
842 }
843}
844
845
846/**
847 * Turns off normal raw mode features.
848 *
849 * @param pVM Pointer to the VM.
850 */
851static void hmR3DisableRawMode(PVM pVM)
852{
853 /* Reinit the paging mode to force the new shadow mode. */
854 for (VMCPUID i = 0; i < pVM->cCpus; i++)
855 {
856 PVMCPU pVCpu = &pVM->aCpus[i];
857
858 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
859 }
860}
861
862
863/**
864 * Initialize VT-x or AMD-V.
865 *
866 * @returns VBox status code.
867 * @param pVM Pointer to the VM.
868 */
869static int hmR3InitFinalizeR0(PVM pVM)
870{
871 int rc;
872
873 if (!HMIsEnabled(pVM))
874 return VINF_SUCCESS;
875
876 /*
877 * Hack to allow users to work around broken BIOSes that incorrectly set
878 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
879 */
880 if ( !pVM->hm.s.vmx.fSupported
881 && !pVM->hm.s.svm.fSupported
882 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
883 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
884 {
885 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
886 pVM->hm.s.svm.fSupported = true;
887 pVM->hm.s.svm.fIgnoreInUseError = true;
888 pVM->hm.s.lLastError = VINF_SUCCESS;
889 }
890
891 /*
892 * Report ring-0 init errors.
893 */
894 if ( !pVM->hm.s.vmx.fSupported
895 && !pVM->hm.s.svm.fSupported)
896 {
897 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError));
898 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
899 switch (pVM->hm.s.lLastError)
900 {
901 case VERR_VMX_IN_VMX_ROOT_MODE:
902 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
903 case VERR_VMX_NO_VMX:
904 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
905 case VERR_VMX_MSR_LOCKED_OR_DISABLED:
906 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is disabled in the BIOS (or by the host OS).");
907
908 case VERR_SVM_IN_USE:
909 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
910 case VERR_SVM_NO_SVM:
911 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
912 case VERR_SVM_DISABLED:
913 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
914 }
915 return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
916 }
917
918 /*
919 * Enable VT-x or AMD-V on all host CPUs.
920 */
921 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
922 if (RT_FAILURE(rc))
923 {
924 LogRel(("HMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HM_ENABLE failed with %Rrc\n", rc));
925 return rc;
926 }
927
928 /*
929 * No TPR patching is required when the IO-APIC is not enabled for this VM.
930 * (Main should have taken care of this already)
931 */
932 pVM->hm.s.fHasIoApic = PDMHasIoApic(pVM);
933 if (!pVM->hm.s.fHasIoApic)
934 {
935 Assert(!pVM->hm.s.fTRPPatchingAllowed); /* paranoia */
936 pVM->hm.s.fTRPPatchingAllowed = false;
937 }
938
939 /*
940 * Do the vendor specific initalization .
941 * .
942 * Note! We disable release log buffering here since we're doing relatively .
943 * lot of logging and doesn't want to hit the disk with each LogRel .
944 * statement.
945 */
946 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
947 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
948 if (pVM->hm.s.vmx.fSupported)
949 rc = hmR3InitFinalizeR0Intel(pVM);
950 else
951 rc = hmR3InitFinalizeR0Amd(pVM);
952 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
953 RTLogRelSetBuffering(fOldBuffered);
954 pVM->hm.s.fInitialized = true;
955
956 return rc;
957}
958
959
960/**
961 * Finish VT-x initialization (after ring-0 init).
962 *
963 * @returns VBox status code.
964 * @param pVM The cross context VM structure.
965 */
966static int hmR3InitFinalizeR0Intel(PVM pVM)
967{
968 int rc;
969
970 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
971 AssertLogRelReturn(pVM->hm.s.vmx.msr.feature_ctrl != 0, VERR_HM_IPE_4);
972
973 uint64_t val;
974 uint64_t zap;
975 RTGCPHYS GCPhys = 0;
976
977 LogRel(("HM: Using VT-x implementation 2.0!\n"));
978 LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.hostCR4));
979 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
980 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %#RX64\n", pVM->hm.s.vmx.msr.vmx_basic_info));
981 LogRel(("HM: VMCS id = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.vmx_basic_info)));
982 LogRel(("HM: VMCS size = %u\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.vmx_basic_info)));
983 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
984 LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.vmx_basic_info)));
985 LogRel(("HM: Dual-monitor treatment = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.vmx_basic_info)));
986 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.msr.vmx_basic_info)));
987 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
988
989 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.msr.vmx_pin_ctls.u));
990 val = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
991 zap = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
992 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
993 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
994 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
995 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
996
997 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls.u));
998 val = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
999 zap = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
1000 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
1001 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
1002 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
1003 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
1004 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
1005 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
1006 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
1007 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
1008 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
1009 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
1010 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
1011 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
1012 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
1013 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
1014 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
1015 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
1016 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
1017 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
1018 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
1019 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
1020 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
1021 if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1022 {
1023 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls2.u));
1024 val = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
1025 zap = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
1026 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
1027 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_EPT);
1028 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
1029 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
1030 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
1031 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VPID);
1032 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
1033 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
1034 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
1035 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
1036 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
1037 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
1038 }
1039
1040 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.msr.vmx_entry.u));
1041 val = pVM->hm.s.vmx.msr.vmx_entry.n.allowed1;
1042 zap = pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0;
1043 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
1044 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
1045 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
1046 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
1047 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
1048 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
1049 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
1050
1051 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.msr.vmx_exit.u));
1052 val = pVM->hm.s.vmx.msr.vmx_exit.n.allowed1;
1053 zap = pVM->hm.s.vmx.msr.vmx_exit.n.disallowed0;
1054 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
1055 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
1056 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
1057 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
1058 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
1059 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
1060 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
1061 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
1062 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
1063
1064 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps)
1065 {
1066 val = pVM->hm.s.vmx.msr.vmx_ept_vpid_caps;
1067 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", val));
1068 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1069 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY);
1070 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY);
1071 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS);
1072 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS);
1073 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS);
1074 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS);
1075 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS);
1076 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1077 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC);
1078 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT);
1079 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP);
1080 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1081 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS);
1082 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS);
1083 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS);
1084 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS);
1085 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1086 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1087 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1088 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1089 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1090 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1091 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1092 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1093 }
1094
1095 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", pVM->hm.s.vmx.msr.vmx_misc));
1096 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc) == pVM->hm.s.vmx.cPreemptTimerShift)
1097 {
1098 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x\n",
1099 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc)));
1100 }
1101 else
1102 {
1103 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x - erratum detected, using %#x instead\n",
1104 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc), pVM->hm.s.vmx.cPreemptTimerShift));
1105 }
1106
1107 LogRel(("HM: MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT = %RTbool\n", !!MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(pVM->hm.s.vmx.msr.vmx_misc)));
1108 LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.msr.vmx_misc)));
1109 LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hm.s.vmx.msr.vmx_misc)));
1110 LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc)));
1111 LogRel(("HM: MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM = %RTbool\n", !!MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(pVM->hm.s.vmx.msr.vmx_misc)));
1112 LogRel(("HM: MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2 = %RTbool\n", !!MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(pVM->hm.s.vmx.msr.vmx_misc)));
1113 LogRel(("HM: MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO = %RTbool\n", !!MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(pVM->hm.s.vmx.msr.vmx_misc)));
1114 LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hm.s.vmx.msr.vmx_misc)));
1115
1116 /* Paranoia */
1117 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc) >= 512);
1118
1119 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed0));
1120 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed1));
1121 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed0));
1122 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed1));
1123 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", pVM->hm.s.vmx.msr.vmx_vmcs_enum));
1124 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(pVM->hm.s.vmx.msr.vmx_vmcs_enum)));
1125
1126 val = pVM->hm.s.vmx.msr.vmx_vmfunc;
1127 if (val)
1128 {
1129 LogRel(("HM: MSR_A32_VMX_VMFUNC = %#RX64\n", val));
1130 HMVMX_REPORT_ALLOWED_FEATURE(val, VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
1131 }
1132
1133 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1134
1135 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1136 {
1137 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1138 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1139 }
1140
1141 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1142 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1143
1144 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1145 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1146
1147 /*
1148 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1149 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1150 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1151 */
1152 if ( !(pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1153 && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1154 {
1155 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1156 LogRel(("HM: RDTSCP disabled.\n"));
1157 }
1158
1159 /* Unrestricted guest execution also requires EPT. */
1160 if ( pVM->hm.s.vmx.fAllowUnrestricted
1161 && pVM->hm.s.fNestedPaging
1162 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST))
1163 {
1164 pVM->hm.s.vmx.fUnrestrictedGuest = true;
1165 }
1166
1167 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1168 {
1169 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1170 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1171 if (RT_SUCCESS(rc))
1172 {
1173 /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1174 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1175 esp. Figure 20-5.*/
1176 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1177 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1178
1179 /* Bit set to 0 means software interrupts are redirected to the
1180 8086 program interrupt handler rather than switching to
1181 protected-mode handler. */
1182 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1183
1184 /* Allow all port IO, so that port IO instructions do not cause
1185 exceptions and would instead cause a VM-exit (based on VT-x's
1186 IO bitmap which we currently configure to always cause an exit). */
1187 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1188 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1189
1190 /*
1191 * Construct a 1024 element page directory with 4 MB pages for
1192 * the identity mapped page table used in real and protected mode
1193 * without paging with EPT.
1194 */
1195 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1196 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1197 {
1198 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1199 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1200 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1201 | X86_PDE4M_G;
1202 }
1203
1204 /* We convert it here every time as pci regions could be reconfigured. */
1205 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1206 AssertRCReturn(rc, rc);
1207 LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1208
1209 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1210 AssertRCReturn(rc, rc);
1211 LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1212 }
1213 else
1214 {
1215 /** @todo This cannot possibly work, there are other places which assumes
1216 * this allocation cannot fail (see HMR3CanExecuteGuest()). Make this
1217 * a failure case. */
1218 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1219 pVM->hm.s.vmx.pRealModeTSS = NULL;
1220 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1221 }
1222 }
1223
1224 /*
1225 * Call ring-0 to set up the VM.
1226 */
1227 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1228 if (rc != VINF_SUCCESS)
1229 {
1230 AssertMsgFailed(("%Rrc\n", rc));
1231 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1232 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1233 LogRel(("HM: CPU[%RU32] Last instruction error %#x\n", i, pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError));
1234 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1235 }
1236
1237 LogRel(("HM: VMX enabled!\n"));
1238 pVM->hm.s.vmx.fEnabled = true;
1239
1240 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1241
1242 /*
1243 * Change the CPU features.
1244 */
1245 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1246 if (pVM->hm.s.fAllow64BitGuests)
1247 {
1248 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1249 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1250 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1251 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1252 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1253#if 0 /** @todo r=bird: This ain't making any sense whatsoever. */
1254#if RT_ARCH_X86
1255 if ( !CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1256 || !(pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1257 LogRel(("NX is only supported for 64-bit guests!\n"));
1258#endif
1259#endif
1260 }
1261 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1262 (we reuse the host EFER in the switcher). */
1263 /** @todo this needs to be fixed properly!! */
1264 else if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1265 && (pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1266 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1267 else
1268 LogRel(("HM: NX not supported by the host.\n"));
1269
1270 /*
1271 * Log configuration details.
1272 */
1273 LogRel((pVM->hm.s.fAllow64BitGuests
1274 ? "HM: Guest support: 32-bit and 64-bit.\n"
1275 : "HM: Guest support: 32-bit only.\n"));
1276 if (pVM->hm.s.fNestedPaging)
1277 {
1278 LogRel(("HM: Nested paging enabled!\n"));
1279 LogRel(("HM: EPT root page physaddr = %#RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1280 if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_SINGLE_CONTEXT)
1281 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));
1282 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_ALL_CONTEXTS)
1283 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_ALL_CONTEXTS\n"));
1284 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_NOT_SUPPORTED)
1285 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_NOT_SUPPORTED\n"));
1286 else
1287 LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1288
1289 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1290 LogRel(("HM: Unrestricted guest execution enabled!\n"));
1291
1292#if HC_ARCH_BITS == 64
1293 if (pVM->hm.s.fLargePages)
1294 {
1295 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1296 PGMSetLargePageUsage(pVM, true);
1297 LogRel(("HM: Large page support enabled!\n"));
1298 }
1299#endif
1300 }
1301 else
1302 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1303
1304 if (pVM->hm.s.vmx.fVpid)
1305 {
1306 LogRel(("HM: VPID enabled!\n"));
1307 if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_INDIV_ADDR)
1308 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_INDIV_ADDR\n"));
1309 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT)
1310 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT\n"));
1311 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_ALL_CONTEXTS)
1312 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_ALL_CONTEXTS\n"));
1313 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1314 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1315 else
1316 LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1317 }
1318 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_NOT_SUPPORTED)
1319 LogRel(("HM: Ignoring VPID capabilities of CPU.\n"));
1320
1321 /*
1322 * Check for preemption timer config override and log the state of it.
1323 */
1324 if (pVM->hm.s.vmx.fUsePreemptTimer)
1325 {
1326 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM");
1327 rc = CFGMR3QueryBoolDef(pCfgHm, "UsePreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
1328 AssertLogRelRCReturn(rc, rc);
1329 }
1330 if (pVM->hm.s.vmx.fUsePreemptTimer)
1331 LogRel(("HM: VMX-preemption timer enabled (cPreemptTimerShift=%u).\n", pVM->hm.s.vmx.cPreemptTimerShift));
1332 else
1333 LogRel(("HM: VMX-preemption timer disabled.\n"));
1334
1335 return VINF_SUCCESS;
1336}
1337
1338
1339/**
1340 * Finish AMD-V initialization (after ring-0 init).
1341 *
1342 * @returns VBox status code.
1343 * @param pVM The cross context VM structure.
1344 */
1345static int hmR3InitFinalizeR0Amd(PVM pVM)
1346{
1347 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1348
1349 LogRel(("HM: Using AMD-V implementation 2.0!\n"));
1350
1351 uint32_t u32Family;
1352 uint32_t u32Model;
1353 uint32_t u32Stepping;
1354 if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
1355 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1356 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureECX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1357 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureEDX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1358 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.msrHwcr));
1359 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1360 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1361 LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1362
1363 /*
1364 * Enumerate AMD-V features.
1365 */
1366 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1367 {
1368#define HMSVM_REPORT_FEATURE(a_Define) { a_Define, #a_Define }
1369 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1370 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1371 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1372 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1373 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1374 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1375 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1376 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1377 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1378 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1379 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_AVIC),
1380#undef HMSVM_REPORT_FEATURE
1381 };
1382
1383 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1384 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1385 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1386 {
1387 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1388 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1389 }
1390 if (fSvmFeatures)
1391 for (unsigned iBit = 0; iBit < 32; iBit++)
1392 if (RT_BIT_32(iBit) & fSvmFeatures)
1393 LogRel(("HM: Reserved bit %u\n", iBit));
1394
1395 /*
1396 * Adjust feature(s).
1397 */
1398 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1399 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1400
1401 /*
1402 * Call ring-0 to set up the VM.
1403 */
1404 int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1405 if (rc != VINF_SUCCESS)
1406 {
1407 AssertMsgFailed(("%Rrc\n", rc));
1408 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1409 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1410 }
1411
1412 LogRel(("HM: AMD-V enabled!\n"));
1413 pVM->hm.s.svm.fEnabled = true;
1414
1415 if (pVM->hm.s.fNestedPaging)
1416 {
1417 LogRel(("HM: Nested paging enabled!\n"));
1418
1419 /*
1420 * Enable large pages (2 MB) if applicable.
1421 */
1422#if HC_ARCH_BITS == 64
1423 if (pVM->hm.s.fLargePages)
1424 {
1425 PGMSetLargePageUsage(pVM, true);
1426 LogRel(("HM: Large page support enabled!\n"));
1427 }
1428#endif
1429 }
1430
1431 hmR3DisableRawMode(pVM);
1432
1433 /*
1434 * Change the CPU features.
1435 */
1436 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1437 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1438 if (pVM->hm.s.fAllow64BitGuests)
1439 {
1440 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1441 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1442 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1443 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1444 }
1445 /* Turn on NXE if PAE has been enabled. */
1446 else if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1447 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1448
1449 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1450
1451 LogRel((pVM->hm.s.fAllow64BitGuests
1452 ? "HM: Guest support: 32-bit and 64-bit.\n"
1453 : "HM: Guest support: 32-bit only.\n"));
1454
1455 return VINF_SUCCESS;
1456}
1457
1458
1459/**
1460 * Applies relocations to data and code managed by this
1461 * component. This function will be called at init and
1462 * whenever the VMM need to relocate it self inside the GC.
1463 *
1464 * @param pVM The VM.
1465 */
1466VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1467{
1468 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1469
1470 /* Fetch the current paging mode during the relocate callback during state loading. */
1471 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1472 {
1473 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1474 {
1475 PVMCPU pVCpu = &pVM->aCpus[i];
1476 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1477 }
1478 }
1479#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1480 if (HMIsEnabled(pVM))
1481 {
1482 switch (PGMGetHostMode(pVM))
1483 {
1484 case PGMMODE_32_BIT:
1485 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1486 break;
1487
1488 case PGMMODE_PAE:
1489 case PGMMODE_PAE_NX:
1490 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1491 break;
1492
1493 default:
1494 AssertFailed();
1495 break;
1496 }
1497 }
1498#endif
1499 return;
1500}
1501
1502
1503/**
1504 * Notification callback which is called whenever there is a chance that a CR3
1505 * value might have changed.
1506 *
1507 * This is called by PGM.
1508 *
1509 * @param pVM Pointer to the VM.
1510 * @param pVCpu Pointer to the VMCPU.
1511 * @param enmShadowMode New shadow paging mode.
1512 * @param enmGuestMode New guest paging mode.
1513 */
1514VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1515{
1516 /* Ignore page mode changes during state loading. */
1517 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1518 return;
1519
1520 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1521
1522 /*
1523 * If the guest left protected mode VMX execution, we'll have to be
1524 * extra careful if/when the guest switches back to protected mode.
1525 */
1526 if (enmGuestMode == PGMMODE_REAL)
1527 {
1528 Log(("HMR3PagingModeChanged indicates real mode execution\n"));
1529 pVCpu->hm.s.vmx.fWasInRealMode = true;
1530 }
1531
1532 /** @todo r=ramshankar: Disabling for now. If nothing breaks remove it
1533 * eventually. (Test platforms that use the cache ofc). */
1534#if 0
1535#ifdef VMX_USE_CACHED_VMCS_ACCESSES
1536 /* Reset the contents of the read cache. */
1537 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1538 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1539 pCache->Read.aFieldVal[j] = 0;
1540#endif
1541#endif
1542}
1543
1544
1545/**
1546 * Terminates the HM.
1547 *
1548 * Termination means cleaning up and freeing all resources,
1549 * the VM itself is, at this point, powered off or suspended.
1550 *
1551 * @returns VBox status code.
1552 * @param pVM Pointer to the VM.
1553 */
1554VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1555{
1556 if (pVM->hm.s.vmx.pRealModeTSS)
1557 {
1558 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1559 pVM->hm.s.vmx.pRealModeTSS = 0;
1560 }
1561 hmR3TermCPU(pVM);
1562 return 0;
1563}
1564
1565
1566/**
1567 * Terminates the per-VCPU HM.
1568 *
1569 * @returns VBox status code.
1570 * @param pVM Pointer to the VM.
1571 */
1572static int hmR3TermCPU(PVM pVM)
1573{
1574 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1575 {
1576 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1577
1578#ifdef VBOX_WITH_STATISTICS
1579 if (pVCpu->hm.s.paStatExitReason)
1580 {
1581 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1582 pVCpu->hm.s.paStatExitReason = NULL;
1583 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1584 }
1585 if (pVCpu->hm.s.paStatInjectedIrqs)
1586 {
1587 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1588 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1589 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1590 }
1591#endif
1592
1593#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1594 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1595 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1596 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1597#endif
1598 }
1599 return 0;
1600}
1601
1602
1603/**
1604 * Resets a virtual CPU.
1605 *
1606 * Used by HMR3Reset and CPU hot plugging.
1607 *
1608 * @param pVCpu The CPU to reset.
1609 */
1610VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1611{
1612 /* On first entry we'll sync everything. */
1613 pVCpu->hm.s.fContextUseFlags = (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST);
1614
1615 pVCpu->hm.s.vmx.u32CR0Mask = 0;
1616 pVCpu->hm.s.vmx.u32CR4Mask = 0;
1617 pVCpu->hm.s.fActive = false;
1618 pVCpu->hm.s.Event.fPending = false;
1619 pVCpu->hm.s.vmx.fWasInRealMode = true;
1620
1621 /* Reset the contents of the read cache. */
1622 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1623 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1624 pCache->Read.aFieldVal[j] = 0;
1625
1626#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1627 /* Magic marker for searching in crash dumps. */
1628 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1629 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1630#endif
1631}
1632
1633
1634/**
1635 * The VM is being reset.
1636 *
1637 * For the HM component this means that any GDT/LDT/TSS monitors
1638 * needs to be removed.
1639 *
1640 * @param pVM Pointer to the VM.
1641 */
1642VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1643{
1644 LogFlow(("HMR3Reset:\n"));
1645
1646 if (HMIsEnabled(pVM))
1647 hmR3DisableRawMode(pVM);
1648
1649 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1650 {
1651 PVMCPU pVCpu = &pVM->aCpus[i];
1652
1653 HMR3ResetCpu(pVCpu);
1654 }
1655
1656 /* Clear all patch information. */
1657 pVM->hm.s.pGuestPatchMem = 0;
1658 pVM->hm.s.pFreeGuestPatchMem = 0;
1659 pVM->hm.s.cbGuestPatchMem = 0;
1660 pVM->hm.s.cPatches = 0;
1661 pVM->hm.s.PatchTree = 0;
1662 pVM->hm.s.fTPRPatchingActive = false;
1663 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1664}
1665
1666
1667/**
1668 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1669 *
1670 * @returns VBox strict status code.
1671 * @param pVM Pointer to the VM.
1672 * @param pVCpu The VMCPU for the EMT we're being called on.
1673 * @param pvUser Unused.
1674 */
1675DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1676{
1677 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1678
1679 /* Only execute the handler on the VCPU the original patch request was issued. */
1680 if (pVCpu->idCpu != idCpu)
1681 return VINF_SUCCESS;
1682
1683 Log(("hmR3RemovePatches\n"));
1684 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1685 {
1686 uint8_t abInstr[15];
1687 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1688 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1689 int rc;
1690
1691#ifdef LOG_ENABLED
1692 char szOutput[256];
1693
1694 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1695 szOutput, sizeof(szOutput), NULL);
1696 if (RT_SUCCESS(rc))
1697 Log(("Patched instr: %s\n", szOutput));
1698#endif
1699
1700 /* Check if the instruction is still the same. */
1701 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1702 if (rc != VINF_SUCCESS)
1703 {
1704 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1705 continue; /* swapped out or otherwise removed; skip it. */
1706 }
1707
1708 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1709 {
1710 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1711 continue; /* skip it. */
1712 }
1713
1714 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1715 AssertRC(rc);
1716
1717#ifdef LOG_ENABLED
1718 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1719 szOutput, sizeof(szOutput), NULL);
1720 if (RT_SUCCESS(rc))
1721 Log(("Original instr: %s\n", szOutput));
1722#endif
1723 }
1724 pVM->hm.s.cPatches = 0;
1725 pVM->hm.s.PatchTree = 0;
1726 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1727 pVM->hm.s.fTPRPatchingActive = false;
1728 return VINF_SUCCESS;
1729}
1730
1731
1732/**
1733 * Worker for enabling patching in a VT-x/AMD-V guest.
1734 *
1735 * @returns VBox status code.
1736 * @param pVM Pointer to the VM.
1737 * @param idCpu VCPU to execute hmR3RemovePatches on.
1738 * @param pPatchMem Patch memory range.
1739 * @param cbPatchMem Size of the memory range.
1740 */
1741static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1742{
1743 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
1744 AssertRC(rc);
1745
1746 pVM->hm.s.pGuestPatchMem = pPatchMem;
1747 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
1748 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
1749 return VINF_SUCCESS;
1750}
1751
1752
1753/**
1754 * Enable patching in a VT-x/AMD-V guest
1755 *
1756 * @returns VBox status code.
1757 * @param pVM Pointer to the VM.
1758 * @param pPatchMem Patch memory range.
1759 * @param cbPatchMem Size of the memory range.
1760 */
1761VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1762{
1763 VM_ASSERT_EMT(pVM);
1764 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1765 if (pVM->cCpus > 1)
1766 {
1767 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1768 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1769 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1770 AssertRC(rc);
1771 return rc;
1772 }
1773 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1774}
1775
1776
1777/**
1778 * Disable patching in a VT-x/AMD-V guest.
1779 *
1780 * @returns VBox status code.
1781 * @param pVM Pointer to the VM.
1782 * @param pPatchMem Patch memory range.
1783 * @param cbPatchMem Size of the memory range.
1784 */
1785VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1786{
1787 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1788
1789 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
1790 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
1791
1792 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1793 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
1794 (void *)(uintptr_t)VMMGetCpuId(pVM));
1795 AssertRC(rc);
1796
1797 pVM->hm.s.pGuestPatchMem = 0;
1798 pVM->hm.s.pFreeGuestPatchMem = 0;
1799 pVM->hm.s.cbGuestPatchMem = 0;
1800 pVM->hm.s.fTPRPatchingActive = false;
1801 return VINF_SUCCESS;
1802}
1803
1804
1805/**
1806 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1807 *
1808 * @returns VBox strict status code.
1809 * @param pVM Pointer to the VM.
1810 * @param pVCpu The VMCPU for the EMT we're being called on.
1811 * @param pvUser User specified CPU context.
1812 *
1813 */
1814DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1815{
1816 /*
1817 * Only execute the handler on the VCPU the original patch request was
1818 * issued. (The other CPU(s) might not yet have switched to protected
1819 * mode, nor have the correct memory context.)
1820 */
1821 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1822 if (pVCpu->idCpu != idCpu)
1823 return VINF_SUCCESS;
1824
1825 /*
1826 * We're racing other VCPUs here, so don't try patch the instruction twice
1827 * and make sure there is still room for our patch record.
1828 */
1829 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1830 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1831 if (pPatch)
1832 {
1833 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
1834 return VINF_SUCCESS;
1835 }
1836 uint32_t const idx = pVM->hm.s.cPatches;
1837 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1838 {
1839 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1840 return VINF_SUCCESS;
1841 }
1842 pPatch = &pVM->hm.s.aPatches[idx];
1843
1844 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1845
1846 /*
1847 * Disassembler the instruction and get cracking.
1848 */
1849 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
1850 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1851 uint32_t cbOp;
1852 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1853 AssertRC(rc);
1854 if ( rc == VINF_SUCCESS
1855 && pDis->pCurInstr->uOpcode == OP_MOV
1856 && cbOp >= 3)
1857 {
1858 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
1859
1860 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1861 AssertRC(rc);
1862
1863 pPatch->cbOp = cbOp;
1864
1865 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1866 {
1867 /* write. */
1868 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
1869 {
1870 pPatch->enmType = HMTPRINSTR_WRITE_REG;
1871 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
1872 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
1873 }
1874 else
1875 {
1876 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
1877 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
1878 pPatch->uSrcOperand = pDis->Param2.uValue;
1879 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
1880 }
1881 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1882 AssertRC(rc);
1883
1884 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1885 pPatch->cbNewOp = sizeof(s_abVMMCall);
1886 }
1887 else
1888 {
1889 /*
1890 * TPR Read.
1891 *
1892 * Found:
1893 * mov eax, dword [fffe0080] (5 bytes)
1894 * Check if next instruction is:
1895 * shr eax, 4
1896 */
1897 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
1898
1899 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
1900 uint8_t const cbOpMmio = cbOp;
1901 uint64_t const uSavedRip = pCtx->rip;
1902
1903 pCtx->rip += cbOp;
1904 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1905 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
1906 pCtx->rip = uSavedRip;
1907
1908 if ( rc == VINF_SUCCESS
1909 && pDis->pCurInstr->uOpcode == OP_SHR
1910 && pDis->Param1.fUse == DISUSE_REG_GEN32
1911 && pDis->Param1.Base.idxGenReg == idxMmioReg
1912 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
1913 && pDis->Param2.uValue == 4
1914 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
1915 {
1916 uint8_t abInstr[15];
1917
1918 /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
1919 access CR8 in 32-bit mode and not cause a #VMEXIT. */
1920 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
1921 AssertRC(rc);
1922
1923 pPatch->cbOp = cbOpMmio + cbOp;
1924
1925 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1926 abInstr[0] = 0xF0;
1927 abInstr[1] = 0x0F;
1928 abInstr[2] = 0x20;
1929 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
1930 for (unsigned i = 4; i < pPatch->cbOp; i++)
1931 abInstr[i] = 0x90; /* nop */
1932
1933 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
1934 AssertRC(rc);
1935
1936 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
1937 pPatch->cbNewOp = pPatch->cbOp;
1938
1939 Log(("Acceptable read/shr candidate!\n"));
1940 pPatch->enmType = HMTPRINSTR_READ_SHR4;
1941 }
1942 else
1943 {
1944 pPatch->enmType = HMTPRINSTR_READ;
1945 pPatch->uDstOperand = idxMmioReg;
1946
1947 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1948 AssertRC(rc);
1949
1950 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1951 pPatch->cbNewOp = sizeof(s_abVMMCall);
1952 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
1953 }
1954 }
1955
1956 pPatch->Core.Key = pCtx->eip;
1957 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1958 AssertRC(rc);
1959
1960 pVM->hm.s.cPatches++;
1961 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccess);
1962 return VINF_SUCCESS;
1963 }
1964
1965 /*
1966 * Save invalid patch, so we will not try again.
1967 */
1968 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
1969 pPatch->Core.Key = pCtx->eip;
1970 pPatch->enmType = HMTPRINSTR_INVALID;
1971 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1972 AssertRC(rc);
1973 pVM->hm.s.cPatches++;
1974 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
1975 return VINF_SUCCESS;
1976}
1977
1978
1979/**
1980 * Callback to patch a TPR instruction (jump to generated code).
1981 *
1982 * @returns VBox strict status code.
1983 * @param pVM Pointer to the VM.
1984 * @param pVCpu The VMCPU for the EMT we're being called on.
1985 * @param pvUser User specified CPU context.
1986 *
1987 */
1988DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1989{
1990 /*
1991 * Only execute the handler on the VCPU the original patch request was
1992 * issued. (The other CPU(s) might not yet have switched to protected
1993 * mode, nor have the correct memory context.)
1994 */
1995 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1996 if (pVCpu->idCpu != idCpu)
1997 return VINF_SUCCESS;
1998
1999 /*
2000 * We're racing other VCPUs here, so don't try patch the instruction twice
2001 * and make sure there is still room for our patch record.
2002 */
2003 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2004 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2005 if (pPatch)
2006 {
2007 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2008 return VINF_SUCCESS;
2009 }
2010 uint32_t const idx = pVM->hm.s.cPatches;
2011 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2012 {
2013 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2014 return VINF_SUCCESS;
2015 }
2016 pPatch = &pVM->hm.s.aPatches[idx];
2017
2018 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2019 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2020
2021 /*
2022 * Disassemble the instruction and get cracking.
2023 */
2024 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2025 uint32_t cbOp;
2026 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2027 AssertRC(rc);
2028 if ( rc == VINF_SUCCESS
2029 && pDis->pCurInstr->uOpcode == OP_MOV
2030 && cbOp >= 5)
2031 {
2032 uint8_t aPatch[64];
2033 uint32_t off = 0;
2034
2035 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2036 AssertRC(rc);
2037
2038 pPatch->cbOp = cbOp;
2039 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2040
2041 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2042 {
2043 /*
2044 * TPR write:
2045 *
2046 * push ECX [51]
2047 * push EDX [52]
2048 * push EAX [50]
2049 * xor EDX,EDX [31 D2]
2050 * mov EAX,EAX [89 C0]
2051 * or
2052 * mov EAX,0000000CCh [B8 CC 00 00 00]
2053 * mov ECX,0C0000082h [B9 82 00 00 C0]
2054 * wrmsr [0F 30]
2055 * pop EAX [58]
2056 * pop EDX [5A]
2057 * pop ECX [59]
2058 * jmp return_address [E9 return_address]
2059 *
2060 */
2061 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2062
2063 aPatch[off++] = 0x51; /* push ecx */
2064 aPatch[off++] = 0x52; /* push edx */
2065 if (!fUsesEax)
2066 aPatch[off++] = 0x50; /* push eax */
2067 aPatch[off++] = 0x31; /* xor edx, edx */
2068 aPatch[off++] = 0xD2;
2069 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2070 {
2071 if (!fUsesEax)
2072 {
2073 aPatch[off++] = 0x89; /* mov eax, src_reg */
2074 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2075 }
2076 }
2077 else
2078 {
2079 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2080 aPatch[off++] = 0xB8; /* mov eax, immediate */
2081 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2082 off += sizeof(uint32_t);
2083 }
2084 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2085 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2086 off += sizeof(uint32_t);
2087
2088 aPatch[off++] = 0x0F; /* wrmsr */
2089 aPatch[off++] = 0x30;
2090 if (!fUsesEax)
2091 aPatch[off++] = 0x58; /* pop eax */
2092 aPatch[off++] = 0x5A; /* pop edx */
2093 aPatch[off++] = 0x59; /* pop ecx */
2094 }
2095 else
2096 {
2097 /*
2098 * TPR read:
2099 *
2100 * push ECX [51]
2101 * push EDX [52]
2102 * push EAX [50]
2103 * mov ECX,0C0000082h [B9 82 00 00 C0]
2104 * rdmsr [0F 32]
2105 * mov EAX,EAX [89 C0]
2106 * pop EAX [58]
2107 * pop EDX [5A]
2108 * pop ECX [59]
2109 * jmp return_address [E9 return_address]
2110 *
2111 */
2112 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2113
2114 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2115 aPatch[off++] = 0x51; /* push ecx */
2116 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2117 aPatch[off++] = 0x52; /* push edx */
2118 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2119 aPatch[off++] = 0x50; /* push eax */
2120
2121 aPatch[off++] = 0x31; /* xor edx, edx */
2122 aPatch[off++] = 0xD2;
2123
2124 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2125 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2126 off += sizeof(uint32_t);
2127
2128 aPatch[off++] = 0x0F; /* rdmsr */
2129 aPatch[off++] = 0x32;
2130
2131 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2132 {
2133 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2134 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2135 }
2136
2137 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2138 aPatch[off++] = 0x58; /* pop eax */
2139 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2140 aPatch[off++] = 0x5A; /* pop edx */
2141 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2142 aPatch[off++] = 0x59; /* pop ecx */
2143 }
2144 aPatch[off++] = 0xE9; /* jmp return_address */
2145 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2146 off += sizeof(RTRCUINTPTR);
2147
2148 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2149 {
2150 /* Write new code to the patch buffer. */
2151 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2152 AssertRC(rc);
2153
2154#ifdef LOG_ENABLED
2155 uint32_t cbCurInstr;
2156 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2157 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2158 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2159 {
2160 char szOutput[256];
2161 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2162 szOutput, sizeof(szOutput), &cbCurInstr);
2163 if (RT_SUCCESS(rc))
2164 Log(("Patch instr %s\n", szOutput));
2165 else
2166 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2167 }
2168#endif
2169
2170 pPatch->aNewOpcode[0] = 0xE9;
2171 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2172
2173 /* Overwrite the TPR instruction with a jump. */
2174 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2175 AssertRC(rc);
2176
2177 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2178
2179 pVM->hm.s.pFreeGuestPatchMem += off;
2180 pPatch->cbNewOp = 5;
2181
2182 pPatch->Core.Key = pCtx->eip;
2183 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2184 AssertRC(rc);
2185
2186 pVM->hm.s.cPatches++;
2187 pVM->hm.s.fTPRPatchingActive = true;
2188 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2189 return VINF_SUCCESS;
2190 }
2191
2192 Log(("Ran out of space in our patch buffer!\n"));
2193 }
2194 else
2195 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2196
2197
2198 /*
2199 * Save invalid patch, so we will not try again.
2200 */
2201 pPatch = &pVM->hm.s.aPatches[idx];
2202 pPatch->Core.Key = pCtx->eip;
2203 pPatch->enmType = HMTPRINSTR_INVALID;
2204 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2205 AssertRC(rc);
2206 pVM->hm.s.cPatches++;
2207 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2208 return VINF_SUCCESS;
2209}
2210
2211
2212/**
2213 * Attempt to patch TPR mmio instructions.
2214 *
2215 * @returns VBox status code.
2216 * @param pVM Pointer to the VM.
2217 * @param pVCpu Pointer to the VMCPU.
2218 * @param pCtx Pointer to the guest CPU context.
2219 */
2220VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2221{
2222 NOREF(pCtx);
2223 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2224 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2225 (void *)(uintptr_t)pVCpu->idCpu);
2226 AssertRC(rc);
2227 return rc;
2228}
2229
2230
2231/**
2232 * Checks if a code selector (CS) is suitable for execution
2233 * within VMX when unrestricted execution isn't available.
2234 *
2235 * @returns true if selector is suitable for VMX, otherwise
2236 * false.
2237 * @param pSel Pointer to the selector to check (CS).
2238 * uStackDpl The DPL of the stack segment.
2239 */
2240static bool hmR3IsCodeSelectorOkForVmx(PCPUMSELREG pSel, unsigned uStackDpl)
2241{
2242 bool rc = false;
2243
2244 do
2245 {
2246 /* Segment must be accessed. */
2247 if (!(pSel->Attr.u & X86_SEL_TYPE_ACCESSED))
2248 break;
2249 /* Segment must be a code segment. */
2250 if (!(pSel->Attr.u & X86_SEL_TYPE_CODE))
2251 break;
2252 /* The S bit must be set. */
2253 if (!pSel->Attr.n.u1DescType)
2254 break;
2255 if (pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF)
2256 {
2257 /* For conforming segments, CS.DPL must be <= SS.DPL. */
2258 if (pSel->Attr.n.u2Dpl > uStackDpl)
2259 break;
2260 }
2261 else
2262 {
2263 /* For non-conforming segments, CS.DPL must equal SS.DPL. */
2264 if (pSel->Attr.n.u2Dpl != uStackDpl)
2265 break;
2266 }
2267 /* Segment must be present. */
2268 if (!pSel->Attr.n.u1Present)
2269 break;
2270 /* G bit must be set if any high limit bits are set. */
2271 if ((pSel->u32Limit & 0xfff00000) && !pSel->Attr.n.u1Granularity)
2272 break;
2273 /* G bit must be clear if any low limit bits are clear. */
2274 if ((pSel->u32Limit & 0x0fff) != 0x0fff && pSel->Attr.n.u1Granularity)
2275 break;
2276
2277 rc = true;
2278 } while (0);
2279 return rc;
2280}
2281
2282
2283/**
2284 * Checks if a data selector (DS/ES/FS/GS) is suitable for
2285 * execution within VMX when unrestricted execution isn't
2286 * available.
2287 *
2288 * @returns true if selector is suitable for VMX, otherwise
2289 * false.
2290 * @param pSel Pointer to the selector to check
2291 * (DS/ES/FS/GS).
2292 */
2293static bool hmR3IsDataSelectorOkForVmx(PCPUMSELREG pSel)
2294{
2295 bool rc = false;
2296
2297 /* If attributes are all zero, consider the segment unusable and therefore OK.
2298 * This logic must be in sync with HMVMXR0.cpp!
2299 */
2300 if (!pSel->Attr.u)
2301 return true;
2302
2303 do
2304 {
2305 /* Segment must be accessed. */
2306 if (!(pSel->Attr.u & X86_SEL_TYPE_ACCESSED))
2307 break;
2308 /* Code segments must also be readable. */
2309 if (pSel->Attr.u & X86_SEL_TYPE_CODE && !(pSel->Attr.u & X86_SEL_TYPE_READ))
2310 break;
2311 /* The S bit must be set. */
2312 if (!pSel->Attr.n.u1DescType)
2313 break;
2314 /* Except for conforming segments, DPL >= RPL. */
2315 if (pSel->Attr.n.u4Type <= X86_SEL_TYPE_ER_ACC && pSel->Attr.n.u2Dpl < (pSel->Sel & X86_SEL_RPL))
2316 break;
2317 /* Segment must be present. */
2318 if (!pSel->Attr.n.u1Present)
2319 break;
2320 /* G bit must be set if any high limit bits are set. */
2321 if ((pSel->u32Limit & 0xfff00000) && !pSel->Attr.n.u1Granularity)
2322 break;
2323 /* G bit must be clear if any low limit bits are clear. */
2324 if ((pSel->u32Limit & 0x0fff) != 0x0fff && pSel->Attr.n.u1Granularity)
2325 break;
2326
2327 rc = true;
2328 } while (0);
2329 return rc;
2330}
2331
2332
2333/**
2334 * Checks if the stack selector (SS) is suitable for execution
2335 * within VMX when unrestricted execution isn't available.
2336 *
2337 * @returns true if selector is suitable for VMX, otherwise
2338 * false.
2339 * @param pSel Pointer to the selector to check (SS).
2340 */
2341static bool hmR3IsStackSelectorOkForVmx(PCPUMSELREG pSel)
2342{
2343 bool rc = false;
2344
2345 /* If attributes are all zero, consider the segment unusable and therefore OK.
2346 * This logic must be in sync with HMVMXR0.cpp!
2347 */
2348 if (!pSel->Attr.u)
2349 return true;
2350
2351 do
2352 {
2353 /* Segment must be accessed. */
2354 if (!(pSel->Attr.u & X86_SEL_TYPE_ACCESSED))
2355 break;
2356 /* Segment must be writable. */
2357 if (!(pSel->Attr.u & X86_SEL_TYPE_WRITE))
2358 break;
2359 /* Segment must not be a code segment. */
2360 if (pSel->Attr.u & X86_SEL_TYPE_CODE)
2361 break;
2362 /* The S bit must be set. */
2363 if (!pSel->Attr.n.u1DescType)
2364 break;
2365 /* DPL must equal RPL. */
2366 if (pSel->Attr.n.u2Dpl != (pSel->Sel & X86_SEL_RPL))
2367 break;
2368 /* Segment must be present. */
2369 if (!pSel->Attr.n.u1Present)
2370 break;
2371 /* G bit must be set if any high limit bits are set. */
2372 if ((pSel->u32Limit & 0xfff00000) && !pSel->Attr.n.u1Granularity)
2373 break;
2374 /* G bit must be clear if any low limit bits are clear. */
2375 if ((pSel->u32Limit & 0x0fff) != 0x0fff && pSel->Attr.n.u1Granularity)
2376 break;
2377
2378 rc = true;
2379 } while (0);
2380 return rc;
2381}
2382
2383
2384/**
2385 * Force execution of the current IO code in the recompiler.
2386 *
2387 * @returns VBox status code.
2388 * @param pVM Pointer to the VM.
2389 * @param pCtx Partial VM execution context.
2390 */
2391VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2392{
2393 PVMCPU pVCpu = VMMGetCpu(pVM);
2394
2395 Assert(HMIsEnabled(pVM));
2396 Log(("HMR3EmulateIoBlock\n"));
2397
2398 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2399 if (HMCanEmulateIoBlockEx(pCtx))
2400 {
2401 Log(("HMR3EmulateIoBlock -> enabled\n"));
2402 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2403 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2404 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2405 return VINF_EM_RESCHEDULE_REM;
2406 }
2407 return VINF_SUCCESS;
2408}
2409
2410
2411/**
2412 * Checks if we can currently use hardware accelerated raw mode.
2413 *
2414 * @returns true if we can currently use hardware acceleration, otherwise false.
2415 * @param pVM Pointer to the VM.
2416 * @param pCtx Partial VM execution context.
2417 */
2418VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2419{
2420 PVMCPU pVCpu = VMMGetCpu(pVM);
2421
2422 Assert(HMIsEnabled(pVM));
2423
2424 /* If we're still executing the IO code, then return false. */
2425 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2426 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2427 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2428 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2429 return false;
2430
2431 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2432
2433 /* AMD-V supports real & protected mode with or without paging. */
2434 if (pVM->hm.s.svm.fEnabled)
2435 {
2436 pVCpu->hm.s.fActive = true;
2437 return true;
2438 }
2439
2440 pVCpu->hm.s.fActive = false;
2441
2442 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2443 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2444 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2445
2446 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2447 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2448 {
2449 /*
2450 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2451 * guest execution feature i missing (VT-x only).
2452 */
2453 if (fSupportsRealMode)
2454 {
2455 if (CPUMIsGuestInRealModeEx(pCtx))
2456 {
2457 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2458 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2459 * If this is not true, we cannot execute real mode as V86 and have to fall
2460 * back to emulation.
2461 */
2462 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2463 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2464 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2465 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2466 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2467 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
2468 {
2469 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
2470 return false;
2471 }
2472 if ( (pCtx->cs.u32Limit != 0xffff)
2473 || (pCtx->ds.u32Limit != 0xffff)
2474 || (pCtx->es.u32Limit != 0xffff)
2475 || (pCtx->ss.u32Limit != 0xffff)
2476 || (pCtx->fs.u32Limit != 0xffff)
2477 || (pCtx->gs.u32Limit != 0xffff))
2478 {
2479 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
2480 return false;
2481 }
2482 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
2483 }
2484 else
2485 {
2486 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2487 /* Verify the requirements for executing code in protected
2488 mode. VT-x can't handle the CPU state right after a switch
2489 from real to protected mode. (all sorts of RPL & DPL assumptions). */
2490 if (pVCpu->hm.s.vmx.fWasInRealMode)
2491 {
2492 /** @todo If guest is in V86 mode, these checks should be different! */
2493 if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
2494 {
2495 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
2496 return false;
2497 }
2498 if ( !hmR3IsCodeSelectorOkForVmx(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
2499 || !hmR3IsDataSelectorOkForVmx(&pCtx->ds)
2500 || !hmR3IsDataSelectorOkForVmx(&pCtx->es)
2501 || !hmR3IsDataSelectorOkForVmx(&pCtx->fs)
2502 || !hmR3IsDataSelectorOkForVmx(&pCtx->gs)
2503 || !hmR3IsStackSelectorOkForVmx(&pCtx->ss))
2504 {
2505 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
2506 return false;
2507 }
2508 }
2509 /* VT-x also chokes on invalid TR or LDTR selectors (minix). */
2510 if (pCtx->gdtr.cbGdt)
2511 {
2512 if (pCtx->tr.Sel > pCtx->gdtr.cbGdt)
2513 {
2514 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadTr);
2515 return false;
2516 }
2517 else if (pCtx->ldtr.Sel > pCtx->gdtr.cbGdt)
2518 {
2519 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadLdt);
2520 return false;
2521 }
2522 }
2523 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckPmOk);
2524 }
2525 }
2526 else
2527 {
2528 if ( !CPUMIsGuestInLongModeEx(pCtx)
2529 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2530 {
2531 if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2532 || CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
2533 return false;
2534
2535 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2536 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2537 return false;
2538
2539 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2540 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2541 * hidden registers (possible recompiler bug; see load_seg_vm) */
2542 if (pCtx->cs.Attr.n.u1Present == 0)
2543 return false;
2544 if (pCtx->ss.Attr.n.u1Present == 0)
2545 return false;
2546
2547 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2548 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2549 /** @todo This check is actually wrong, it doesn't take the direction of the
2550 * stack segment into account. But, it does the job for now. */
2551 if (pCtx->rsp >= pCtx->ss.u32Limit)
2552 return false;
2553 }
2554 }
2555 }
2556
2557 if (pVM->hm.s.vmx.fEnabled)
2558 {
2559 uint32_t mask;
2560
2561 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2562 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr0_fixed0;
2563 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2564 mask &= ~X86_CR0_NE;
2565
2566 if (fSupportsRealMode)
2567 {
2568 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2569 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2570 }
2571 else
2572 {
2573 /* We support protected mode without paging using identity mapping. */
2574 mask &= ~X86_CR0_PG;
2575 }
2576 if ((pCtx->cr0 & mask) != mask)
2577 return false;
2578
2579 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2580 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr0_fixed1;
2581 if ((pCtx->cr0 & mask) != 0)
2582 return false;
2583
2584 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2585 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr4_fixed0;
2586 mask &= ~X86_CR4_VMXE;
2587 if ((pCtx->cr4 & mask) != mask)
2588 return false;
2589
2590 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2591 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr4_fixed1;
2592 if ((pCtx->cr4 & mask) != 0)
2593 return false;
2594
2595 pVCpu->hm.s.fActive = true;
2596 return true;
2597 }
2598
2599 return false;
2600}
2601
2602
2603/**
2604 * Checks if we need to reschedule due to VMM device heap changes.
2605 *
2606 * @returns true if a reschedule is required, otherwise false.
2607 * @param pVM Pointer to the VM.
2608 * @param pCtx VM execution context.
2609 */
2610VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2611{
2612 /*
2613 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2614 * when the unrestricted guest execution feature is missing (VT-x only).
2615 */
2616 if ( pVM->hm.s.vmx.fEnabled
2617 && !pVM->hm.s.vmx.fUnrestrictedGuest
2618 && CPUMIsGuestInRealModeEx(pCtx)
2619 && !PDMVmmDevHeapIsEnabled(pVM))
2620 {
2621 return true;
2622 }
2623
2624 return false;
2625}
2626
2627
2628/**
2629 * Notification from EM about a rescheduling into hardware assisted execution
2630 * mode.
2631 *
2632 * @param pVCpu Pointer to the current VMCPU.
2633 */
2634VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2635{
2636 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2637}
2638
2639
2640/**
2641 * Notification from EM about returning from instruction emulation (REM / EM).
2642 *
2643 * @param pVCpu Pointer to the VMCPU.
2644 */
2645VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2646{
2647 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2648}
2649
2650
2651/**
2652 * Checks if we are currently using hardware accelerated raw mode.
2653 *
2654 * @returns true if hardware acceleration is being used, otherwise false.
2655 * @param pVCpu Pointer to the VMCPU.
2656 */
2657VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2658{
2659 return pVCpu->hm.s.fActive;
2660}
2661
2662
2663/**
2664 * External interface for querying whether hardware accelerated raw mode is
2665 * enabled.
2666 *
2667 * @returns true if nested paging is being used, otherwise false.
2668 * @param pUVM The user mode VM handle.
2669 * @sa HMIsEnabled, HMIsEnabledNotMacro.
2670 */
2671VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2672{
2673 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2674 PVM pVM = pUVM->pVM;
2675 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2676 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2677}
2678
2679
2680/**
2681 * Checks if we are currently using nested paging.
2682 *
2683 * @returns true if nested paging is being used, otherwise false.
2684 * @param pUVM The user mode VM handle.
2685 */
2686VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2687{
2688 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2689 PVM pVM = pUVM->pVM;
2690 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2691 return pVM->hm.s.fNestedPaging;
2692}
2693
2694
2695/**
2696 * Checks if we are currently using VPID in VT-x mode.
2697 *
2698 * @returns true if VPID is being used, otherwise false.
2699 * @param pUVM The user mode VM handle.
2700 */
2701VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2702{
2703 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2704 PVM pVM = pUVM->pVM;
2705 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2706 return pVM->hm.s.vmx.fVpid;
2707}
2708
2709
2710/**
2711 * Checks if we are currently using VT-x unrestricted execution,
2712 * aka UX.
2713 *
2714 * @returns true if UX is being used, otherwise false.
2715 * @param pUVM The user mode VM handle.
2716 */
2717VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2718{
2719 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2720 PVM pVM = pUVM->pVM;
2721 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2722 return pVM->hm.s.vmx.fUnrestrictedGuest;
2723}
2724
2725
2726/**
2727 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2728 *
2729 * @returns true if an internal event is pending, otherwise false.
2730 * @param pVM Pointer to the VM.
2731 */
2732VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
2733{
2734 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
2735}
2736
2737
2738/**
2739 * Checks if the VMX-preemption timer is being used.
2740 *
2741 * @returns true if the VMX-preemption timer is being used, otherwise false.
2742 * @param pVM Pointer to the VM.
2743 */
2744VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2745{
2746 return HMIsEnabled(pVM)
2747 && pVM->hm.s.vmx.fEnabled
2748 && pVM->hm.s.vmx.fUsePreemptTimer;
2749}
2750
2751
2752/**
2753 * Restart an I/O instruction that was refused in ring-0
2754 *
2755 * @returns Strict VBox status code. Informational status codes other than the one documented
2756 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2757 * @retval VINF_SUCCESS Success.
2758 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2759 * status code must be passed on to EM.
2760 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2761 *
2762 * @param pVM Pointer to the VM.
2763 * @param pVCpu Pointer to the VMCPU.
2764 * @param pCtx Pointer to the guest CPU context.
2765 */
2766VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2767{
2768 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
2769
2770 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
2771
2772 if ( pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip
2773 || enmType == HMPENDINGIO_INVALID)
2774 return VERR_NOT_FOUND;
2775
2776 VBOXSTRICTRC rcStrict;
2777 switch (enmType)
2778 {
2779 case HMPENDINGIO_PORT_READ:
2780 {
2781 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
2782 uint32_t u32Val = 0;
2783
2784 rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2785 &u32Val,
2786 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2787 if (IOM_SUCCESS(rcStrict))
2788 {
2789 /* Write back to the EAX register. */
2790 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2791 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2792 }
2793 break;
2794 }
2795
2796 case HMPENDINGIO_PORT_WRITE:
2797 rcStrict = IOMIOPortWrite(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2798 pCtx->eax & pVCpu->hm.s.PendingIO.s.Port.uAndVal,
2799 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2800 if (IOM_SUCCESS(rcStrict))
2801 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2802 break;
2803
2804 default:
2805 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2806 }
2807
2808 if (IOM_SUCCESS(rcStrict))
2809 {
2810 /*
2811 * Check for I/O breakpoints.
2812 */
2813 uint32_t const uDr7 = pCtx->dr[7];
2814 if ( ( (uDr7 & X86_DR7_ENABLED_MASK)
2815 && X86_DR7_ANY_RW_IO(uDr7)
2816 && (pCtx->cr4 & X86_CR4_DE))
2817 || DBGFBpIsHwIoArmed(pVM))
2818 {
2819 VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, pVCpu->hm.s.PendingIO.s.Port.uPort,
2820 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2821 if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
2822 rcStrict2 = TRPMAssertTrap(pVCpu, X86_XCPT_DB, TRPM_TRAP);
2823 /* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
2824 else if (rcStrict2 != VINF_SUCCESS && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
2825 rcStrict = rcStrict2;
2826 }
2827 }
2828 return rcStrict;
2829}
2830
2831
2832/**
2833 * Check fatal VT-x/AMD-V error and produce some meaningful
2834 * log release message.
2835 *
2836 * @param pVM Pointer to the VM.
2837 * @param iStatusCode VBox status code.
2838 */
2839VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2840{
2841 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2842 {
2843 switch (iStatusCode)
2844 {
2845 case VERR_VMX_INVALID_VMCS_FIELD:
2846 break;
2847
2848 case VERR_VMX_INVALID_VMCS_PTR:
2849 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2850 LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVM->aCpus[i].hm.s.vmx.LastError.u64VMCSPhys,
2851 pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
2852 LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVM->aCpus[i].hm.s.vmx.LastError.u32VMCSRevision));
2853 LogRel(("HM: CPU[%u] Entered Cpu %u\n", i, pVM->aCpus[i].hm.s.vmx.LastError.idEnteredCpu));
2854 LogRel(("HM: CPU[%u] Current Cpu %u\n", i, pVM->aCpus[i].hm.s.vmx.LastError.idCurrentCpu));
2855 break;
2856
2857 case VERR_VMX_UNABLE_TO_START_VM:
2858 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
2859 LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError));
2860 LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVM->aCpus[i].hm.s.vmx.LastError.u32ExitReason));
2861 if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2862 {
2863 LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32PinCtls));
2864 LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ProcCtls));
2865 LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ProcCtls2));
2866 LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32EntryCtls));
2867 LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ExitCtls));
2868 LogRel(("HM: CPU[%u] MSRBitmapPhys %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
2869#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
2870 LogRel(("HM: CPU[%u] GuestMSRPhys %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysGuestMsr));
2871 LogRel(("HM: CPU[%u] HostMsrPhys %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysHostMsr));
2872 LogRel(("HM: CPU[%u] cGuestMSRs %u\n", i, pVM->aCpus[i].hm.s.vmx.cGuestMsrs));
2873#endif
2874 }
2875 /** @todo Log VM-entry event injection control fields
2876 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
2877 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
2878 break;
2879
2880 case VERR_VMX_INVALID_VMXON_PTR:
2881 break;
2882
2883 case VERR_VMX_INVALID_GUEST_STATE:
2884 case VERR_VMX_UNEXPECTED_EXIT_CODE:
2885 case VERR_SVM_UNKNOWN_EXIT:
2886 case VERR_SVM_UNEXPECTED_EXIT:
2887 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
2888 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
2889 {
2890 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVM->aCpus[i].hm.s.u32HMError, pVM->aCpus[i].hm.s.u32HMError));
2891 break;
2892 }
2893 }
2894 }
2895
2896 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
2897 {
2898 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.msr.vmx_entry.n.allowed1));
2899 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0));
2900 }
2901}
2902
2903
2904/**
2905 * Execute state save operation.
2906 *
2907 * @returns VBox status code.
2908 * @param pVM Pointer to the VM.
2909 * @param pSSM SSM operation handle.
2910 */
2911static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
2912{
2913 int rc;
2914
2915 Log(("hmR3Save:\n"));
2916
2917 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2918 {
2919 /*
2920 * Save the basic bits - fortunately all the other things can be resynced on load.
2921 */
2922 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
2923 AssertRCReturn(rc, rc);
2924 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
2925 AssertRCReturn(rc, rc);
2926 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntrInfo);
2927 AssertRCReturn(rc, rc);
2928
2929 /** @todo We only need to save pVM->aCpus[i].hm.s.vmx.fWasInRealMode and
2930 * perhaps not even that (the initial value of @c true is safe. */
2931 uint32_t u32Dummy = PGMMODE_REAL;
2932 rc = SSMR3PutU32(pSSM, u32Dummy);
2933 AssertRCReturn(rc, rc);
2934 rc = SSMR3PutU32(pSSM, u32Dummy);
2935 AssertRCReturn(rc, rc);
2936 rc = SSMR3PutU32(pSSM, u32Dummy);
2937 AssertRCReturn(rc, rc);
2938 }
2939
2940#ifdef VBOX_HM_WITH_GUEST_PATCHING
2941 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
2942 AssertRCReturn(rc, rc);
2943 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
2944 AssertRCReturn(rc, rc);
2945 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
2946 AssertRCReturn(rc, rc);
2947
2948 /* Store all the guest patch records too. */
2949 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
2950 AssertRCReturn(rc, rc);
2951
2952 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2953 {
2954 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2955
2956 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2957 AssertRCReturn(rc, rc);
2958
2959 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2960 AssertRCReturn(rc, rc);
2961
2962 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2963 AssertRCReturn(rc, rc);
2964
2965 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2966 AssertRCReturn(rc, rc);
2967
2968 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2969 AssertRCReturn(rc, rc);
2970
2971 AssertCompileSize(HMTPRINSTR, 4);
2972 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2973 AssertRCReturn(rc, rc);
2974
2975 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2976 AssertRCReturn(rc, rc);
2977
2978 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2979 AssertRCReturn(rc, rc);
2980
2981 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2982 AssertRCReturn(rc, rc);
2983
2984 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2985 AssertRCReturn(rc, rc);
2986 }
2987#endif
2988 return VINF_SUCCESS;
2989}
2990
2991
2992/**
2993 * Execute state load operation.
2994 *
2995 * @returns VBox status code.
2996 * @param pVM Pointer to the VM.
2997 * @param pSSM SSM operation handle.
2998 * @param uVersion Data layout version.
2999 * @param uPass The data pass.
3000 */
3001static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3002{
3003 int rc;
3004
3005 Log(("hmR3Load:\n"));
3006 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3007
3008 /*
3009 * Validate version.
3010 */
3011 if ( uVersion != HM_SSM_VERSION
3012 && uVersion != HM_SSM_VERSION_NO_PATCHING
3013 && uVersion != HM_SSM_VERSION_2_0_X)
3014 {
3015 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3016 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3017 }
3018 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3019 {
3020 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3021 AssertRCReturn(rc, rc);
3022 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3023 AssertRCReturn(rc, rc);
3024 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntrInfo);
3025 AssertRCReturn(rc, rc);
3026
3027 if (uVersion >= HM_SSM_VERSION_NO_PATCHING)
3028 {
3029 uint32_t val;
3030 /** @todo See note in hmR3Save(). */
3031 rc = SSMR3GetU32(pSSM, &val);
3032 AssertRCReturn(rc, rc);
3033 rc = SSMR3GetU32(pSSM, &val);
3034 AssertRCReturn(rc, rc);
3035 rc = SSMR3GetU32(pSSM, &val);
3036 AssertRCReturn(rc, rc);
3037 }
3038 }
3039#ifdef VBOX_HM_WITH_GUEST_PATCHING
3040 if (uVersion > HM_SSM_VERSION_NO_PATCHING)
3041 {
3042 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3043 AssertRCReturn(rc, rc);
3044 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3045 AssertRCReturn(rc, rc);
3046 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3047 AssertRCReturn(rc, rc);
3048
3049 /* Fetch all TPR patch records. */
3050 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3051 AssertRCReturn(rc, rc);
3052
3053 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3054 {
3055 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3056
3057 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3058 AssertRCReturn(rc, rc);
3059
3060 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3061 AssertRCReturn(rc, rc);
3062
3063 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
3064 AssertRCReturn(rc, rc);
3065
3066 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3067 AssertRCReturn(rc, rc);
3068
3069 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3070 AssertRCReturn(rc, rc);
3071
3072 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3073 AssertRCReturn(rc, rc);
3074
3075 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3076 pVM->hm.s.fTPRPatchingActive = true;
3077
3078 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
3079
3080 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3081 AssertRCReturn(rc, rc);
3082
3083 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3084 AssertRCReturn(rc, rc);
3085
3086 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
3087 AssertRCReturn(rc, rc);
3088
3089 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3090 AssertRCReturn(rc, rc);
3091
3092 Log(("hmR3Load: patch %d\n", i));
3093 Log(("Key = %x\n", pPatch->Core.Key));
3094 Log(("cbOp = %d\n", pPatch->cbOp));
3095 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
3096 Log(("type = %d\n", pPatch->enmType));
3097 Log(("srcop = %d\n", pPatch->uSrcOperand));
3098 Log(("dstop = %d\n", pPatch->uDstOperand));
3099 Log(("cFaults = %d\n", pPatch->cFaults));
3100 Log(("target = %x\n", pPatch->pJumpTarget));
3101 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3102 AssertRC(rc);
3103 }
3104 }
3105#endif
3106
3107 return VINF_SUCCESS;
3108}
3109
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