GICR3.cpp@ 106360

Last change on this file since 106360 was 106061, checked in by vboxsync, 2 months ago
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1	/* $Id: GICR3.cpp 106061 2024-09-16 14:03:52Z vboxsync $ */
2	/** @file
3	* GIC - Generic Interrupt Controller Architecture (GICv3).
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_DEV_APIC
33	#include <VBox/log.h>
34	#include "GICInternal.h"
35	#include <VBox/vmm/gic.h>
36	#include <VBox/vmm/cpum.h>
37	#include <VBox/vmm/hm.h>
38	#include <VBox/vmm/mm.h>
39	#include <VBox/vmm/pdmdev.h>
40	#include <VBox/vmm/ssm.h>
41	#include <VBox/vmm/vm.h>
42
43	#include <iprt/armv8.h>
44
45
46	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
47
48
49	/*********************************************************************************************************************************
50	* Defined Constants And Macros *
51	*********************************************************************************************************************************/
52	/** Some ancient version... */
53	#define GIC_SAVED_STATE_VERSION 1
54
55	# define GIC_SYSREGRANGE(a_uFirst, a_uLast, a_szName) \
56	{ (a_uFirst), (a_uLast), kCpumSysRegRdFn_GicV3Icc, kCpumSysRegWrFn_GicV3Icc, 0, 0, 0, 0, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
57
58
59	/*********************************************************************************************************************************
60	* Global Variables *
61	*********************************************************************************************************************************/
62	/**
63	* System register ranges for the GICv3.
64	*/
65	static CPUMSYSREGRANGE const g_aSysRegRanges_GICv3[] =
66	{
67	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, "ICC_PMR_EL1"),
68	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1, ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1, "ICC_IAR0_EL1 - ICC_AP0R3_EL1"),
69	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1, ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1, "ICC_AP1R0_EL1 - ICC_NMIAR1_EL1"),
70	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_DIR_EL1, ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1, "ICC_DIR_EL1 - ICC_SGI0R_EL1"),
71	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1, ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1, "ICC_IAR1_EL1 - ICC_IGRPEN1_EL1"),
72	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_SRE_EL2, ARMV8_AARCH64_SYSREG_ICC_SRE_EL2, "ICC_SRE_EL2")
73	};
74
75
76	/**
77	* Dumps basic APIC state.
78	*
79	* @param pVM The cross context VM structure.
80	* @param pHlp The info helpers.
81	* @param pszArgs Arguments, ignored.
82	*/
83	static DECLCALLBACK(void) gicR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
84	{
85	RT_NOREF(pVM, pHlp, pszArgs);
86	}
87
88
89	/**
90	* Dumps GIC Distributor information.
91	*
92	* @param pVM The cross context VM structure.
93	* @param pHlp The info helpers.
94	* @param pszArgs Arguments, ignored.
95	*/
96	static DECLCALLBACK(void) gicR3InfoDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
97	{
98	RT_NOREF(pszArgs);
99
100	PGIC pGic = VM_TO_GIC(pVM);
101	PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
102	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
103
104	pHlp->pfnPrintf(pHlp, "GICv3 Distributor:\n");
105	pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicDev->u32RegIGrp0);
106	pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicDev->u32RegICfg0);
107	pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicDev->u32RegICfg1);
108	pHlp->pfnPrintf(pHlp, " bmIntEnabled = %#RX32\n", pGicDev->bmIntEnabled);
109	pHlp->pfnPrintf(pHlp, " bmIntPending = %#RX32\n", pGicDev->bmIntPending);
110	pHlp->pfnPrintf(pHlp, " bmIntActive = %#RX32\n", pGicDev->bmIntActive);
111	pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
112	for (uint32_t i = 0; i < RT_ELEMENTS(pGicDev->abIntPriority); i++)
113	pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", GIC_INTID_RANGE_SPI_START + i, pGicDev->abIntPriority[i]);
114
115	pHlp->pfnPrintf(pHlp, " fIrqGrp0Enabled = %RTbool\n", pGicDev->fIrqGrp0Enabled);
116	pHlp->pfnPrintf(pHlp, " fIrqGrp1Enabled = %RTbool\n", pGicDev->fIrqGrp1Enabled);
117	}
118
119
120	/**
121	* Dumps the GIC Redistributor information.
122	*
123	* @param pVM The cross context VM structure.
124	* @param pHlp The info helpers.
125	* @param pszArgs Arguments, ignored.
126	*/
127	static DECLCALLBACK(void) gicR3InfoReDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
128	{
129	NOREF(pszArgs);
130	PVMCPU pVCpu = VMMGetCpu(pVM);
131	if (!pVCpu)
132	pVCpu = pVM->apCpusR3[0];
133
134	PGICCPU pGicVCpu = VMCPU_TO_GICCPU(pVCpu);
135
136	pHlp->pfnPrintf(pHlp, "VCPU[%u] Redistributor:\n", pVCpu->idCpu);
137	pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicVCpu->u32RegIGrp0);
138	pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicVCpu->u32RegICfg0);
139	pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicVCpu->u32RegICfg1);
140	pHlp->pfnPrintf(pHlp, " bmIntEnabled = %#RX32\n", pGicVCpu->bmIntEnabled);
141	pHlp->pfnPrintf(pHlp, " bmIntPending = %#RX32\n", pGicVCpu->bmIntPending);
142	pHlp->pfnPrintf(pHlp, " bmIntActive = %#RX32\n", pGicVCpu->bmIntActive);
143	pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
144	for (uint32_t i = 0; i < RT_ELEMENTS(pGicVCpu->abIntPriority); i++)
145	pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", i, pGicVCpu->abIntPriority[i]);
146
147	pHlp->pfnPrintf(pHlp, "VCPU[%u] ICC state:\n", pVCpu->idCpu);
148	pHlp->pfnPrintf(pHlp, " fIrqGrp0Enabled = %RTbool\n", pGicVCpu->fIrqGrp0Enabled);
149	pHlp->pfnPrintf(pHlp, " fIrqGrp1Enabled = %RTbool\n", pGicVCpu->fIrqGrp1Enabled);
150	pHlp->pfnPrintf(pHlp, " bInterruptPriority = %u\n", pGicVCpu->bInterruptPriority);
151	pHlp->pfnPrintf(pHlp, " bBinaryPointGrp0 = %u\n", pGicVCpu->bBinaryPointGrp0);
152	pHlp->pfnPrintf(pHlp, " bBinaryPointGrp1 = %u\n", pGicVCpu->bBinaryPointGrp1);
153	pHlp->pfnPrintf(pHlp, " idxRunningPriority = %u\n", pGicVCpu->idxRunningPriority);
154	pHlp->pfnPrintf(pHlp, " Running priority = %u\n", pGicVCpu->abRunningPriorities[pGicVCpu->idxRunningPriority]);
155	}
156
157
158	/**
159	* Worker for saving per-VM GIC data.
160	*
161	* @returns VBox status code.
162	* @param pDevIns The device instance.
163	* @param pVM The cross context VM structure.
164	* @param pSSM The SSM handle.
165	*/
166	static int gicR3SaveVMData(PPDMDEVINS pDevIns, PVM pVM, PSSMHANDLE pSSM)
167	{
168	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
169	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
170
171	pHlp->pfnSSMPutU32( pSSM, pVM->cCpus);
172	pHlp->pfnSSMPutU32( pSSM, GIC_SPI_MAX);
173	pHlp->pfnSSMPutU32( pSSM, pGicDev->u32RegIGrp0);
174	pHlp->pfnSSMPutU32( pSSM, pGicDev->u32RegICfg0);
175	pHlp->pfnSSMPutU32( pSSM, pGicDev->u32RegICfg1);
176	pHlp->pfnSSMPutU32( pSSM, pGicDev->bmIntEnabled);
177	pHlp->pfnSSMPutU32( pSSM, pGicDev->bmIntPending);
178	pHlp->pfnSSMPutU32( pSSM, pGicDev->bmIntActive);
179	pHlp->pfnSSMPutMem( pSSM, (void *)&pGicDev->abIntPriority[0], sizeof(pGicDev->abIntPriority));
180	pHlp->pfnSSMPutBool(pSSM, pGicDev->fIrqGrp0Enabled);
181
182	return pHlp->pfnSSMPutBool(pSSM, pGicDev->fIrqGrp1Enabled);
183	}
184
185
186	/**
187	* Worker for loading per-VM GIC data.
188	*
189	* @returns VBox status code.
190	* @param pDevIns The device instance.
191	* @param pVM The cross context VM structure.
192	* @param pSSM The SSM handle.
193	*/
194	static int gicR3LoadVMData(PPDMDEVINS pDevIns, PVM pVM, PSSMHANDLE pSSM)
195	{
196	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
197	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
198
199	/* Load and verify number of CPUs. */
200	uint32_t cCpus;
201	int rc = pHlp->pfnSSMGetU32(pSSM, &cCpus);
202	AssertRCReturn(rc, rc);
203	if (cCpus != pVM->cCpus)
204	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%u config=%u"), cCpus, pVM->cCpus);
205
206	/* Load and verify maximum number of SPIs. */
207	uint32_t cSpisMax;
208	rc = pHlp->pfnSSMGetU32(pSSM, &cSpisMax);
209	AssertRCReturn(rc, rc);
210	if (cSpisMax != GIC_SPI_MAX)
211	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cSpisMax: saved=%u config=%u"),
212	cSpisMax, GIC_SPI_MAX);
213
214	/* Load the state. */
215	pHlp->pfnSSMGetU32V( pSSM, &pGicDev->u32RegIGrp0);
216	pHlp->pfnSSMGetU32V( pSSM, &pGicDev->u32RegICfg0);
217	pHlp->pfnSSMGetU32V( pSSM, &pGicDev->u32RegICfg1);
218	pHlp->pfnSSMGetU32V( pSSM, &pGicDev->bmIntEnabled);
219	pHlp->pfnSSMGetU32V( pSSM, &pGicDev->bmIntPending);
220	pHlp->pfnSSMGetU32V( pSSM, &pGicDev->bmIntActive);
221	pHlp->pfnSSMGetMem( pSSM, (void *)&pGicDev->abIntPriority[0], sizeof(pGicDev->abIntPriority));
222	pHlp->pfnSSMGetBoolV(pSSM, &pGicDev->fIrqGrp0Enabled);
223	pHlp->pfnSSMGetBoolV(pSSM, &pGicDev->fIrqGrp1Enabled);
224
225	return VINF_SUCCESS;
226	}
227
228
229	/**
230	* @copydoc FNSSMDEVSAVEEXEC
231	*/
232	static DECLCALLBACK(int) gicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
233	{
234	PVM pVM = PDMDevHlpGetVM(pDevIns);
235	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
236
237	AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
238
239	LogFlow(("GIC: gicR3SaveExec\n"));
240
241	/* Save per-VM data. */
242	int rc = gicR3SaveVMData(pDevIns, pVM, pSSM);
243	AssertRCReturn(rc, rc);
244
245	/* Save per-VCPU data.*/
246	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
247	{
248	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
249	PGICCPU pGicVCpu = VMCPU_TO_GICCPU(pVCpu);
250
251	/* Load the redistributor state. */
252	pHlp->pfnSSMPutU32( pSSM, pGicVCpu->u32RegIGrp0);
253	pHlp->pfnSSMPutU32( pSSM, pGicVCpu->u32RegICfg0);
254	pHlp->pfnSSMPutU32( pSSM, pGicVCpu->u32RegICfg1);
255	pHlp->pfnSSMPutU32( pSSM, pGicVCpu->bmIntEnabled);
256	pHlp->pfnSSMPutU32( pSSM, pGicVCpu->bmIntPending);
257	pHlp->pfnSSMPutU32( pSSM, pGicVCpu->bmIntActive);
258	pHlp->pfnSSMPutMem( pSSM, (void *)&pGicVCpu->abIntPriority[0], sizeof(pGicVCpu->abIntPriority));
259
260	pHlp->pfnSSMPutBool(pSSM, pGicVCpu->fIrqGrp0Enabled);
261	pHlp->pfnSSMPutBool(pSSM, pGicVCpu->fIrqGrp1Enabled);
262	pHlp->pfnSSMPutU8( pSSM, pGicVCpu->bInterruptPriority);
263	pHlp->pfnSSMPutU8( pSSM, pGicVCpu->bBinaryPointGrp0);
264	pHlp->pfnSSMPutU8( pSSM, pGicVCpu->bBinaryPointGrp1);
265	pHlp->pfnSSMPutMem( pSSM, (void *)&pGicVCpu->abRunningPriorities[0], sizeof(pGicVCpu->abRunningPriorities));
266	pHlp->pfnSSMPutU8( pSSM, pGicVCpu->idxRunningPriority);
267	}
268
269	return rc;
270	}
271
272
273	/**
274	* @copydoc FNSSMDEVLOADEXEC
275	*/
276	static DECLCALLBACK(int) gicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
277	{
278	PVM pVM = PDMDevHlpGetVM(pDevIns);
279	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
280
281	AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
282	AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
283
284	LogFlow(("GIC: gicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
285
286	/* Weed out invalid versions. */
287	if (uVersion != GIC_SAVED_STATE_VERSION)
288	{
289	LogRel(("GIC: gicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
290	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
291	}
292
293	int rc = gicR3LoadVMData(pDevIns, pVM, pSSM);
294	AssertRCReturn(rc, rc);
295
296	/*
297	* Restore per CPU state.
298	*
299	* Note! PDM will restore the VMCPU_FF_INTERRUPT_IRQ and VMCPU_FF_INTERRUPT_FIQ flags for us.
300	* This code doesn't touch it. No devices should make us touch
301	* it later during the restore either, only during the 'done' phase.
302	*/
303	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
304	{
305	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
306	PGICCPU pGicVCpu = VMCPU_TO_GICCPU(pVCpu);
307
308	/* Load the redistributor state. */
309	pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->u32RegIGrp0);
310	pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->u32RegICfg0);
311	pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->u32RegICfg1);
312	pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->bmIntEnabled);
313	pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->bmIntPending);
314	pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->bmIntActive);
315	pHlp->pfnSSMGetMem( pSSM, (void *)&pGicVCpu->abIntPriority[0], sizeof(pGicVCpu->abIntPriority));
316
317	pHlp->pfnSSMGetBoolV( pSSM, &pGicVCpu->fIrqGrp0Enabled);
318	pHlp->pfnSSMGetBoolV( pSSM, &pGicVCpu->fIrqGrp1Enabled);
319	pHlp->pfnSSMGetU8V( pSSM, &pGicVCpu->bInterruptPriority);
320	pHlp->pfnSSMGetU8( pSSM, &pGicVCpu->bBinaryPointGrp0);
321	pHlp->pfnSSMGetU8( pSSM, &pGicVCpu->bBinaryPointGrp1);
322	pHlp->pfnSSMGetMem( pSSM, (void *)&pGicVCpu->abRunningPriorities[0], sizeof(pGicVCpu->abRunningPriorities));
323	rc = pHlp->pfnSSMGetU8V(pSSM, &pGicVCpu->idxRunningPriority);
324	if (RT_FAILURE(rc))
325	return rc;
326	}
327
328	return rc;
329	}
330
331
332	/**
333	* @interface_method_impl{PDMDEVREG,pfnReset}
334	*/
335	DECLCALLBACK(void) gicR3Reset(PPDMDEVINS pDevIns)
336	{
337	PVM pVM = PDMDevHlpGetVM(pDevIns);
338	VM_ASSERT_EMT0(pVM);
339	VM_ASSERT_IS_NOT_RUNNING(pVM);
340
341	LogFlow(("GIC: gicR3Reset\n"));
342
343	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
344	{
345	PVMCPU pVCpuDest = pVM->apCpusR3[idCpu];
346
347	gicResetCpu(pVCpuDest);
348	}
349	}
350
351
352	/**
353	* @interface_method_impl{PDMDEVREG,pfnRelocate}
354	*/
355	DECLCALLBACK(void) gicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
356	{
357	RT_NOREF(pDevIns, offDelta);
358	}
359
360
361	/**
362	* Initializes the GIC state.
363	*
364	* @returns VBox status code.
365	* @param pVM The cross context VM structure.
366	*/
367	static int gicR3InitState(PVM pVM)
368	{
369	LogFlowFunc(("pVM=%p\n", pVM));
370
371	RT_NOREF(pVM);
372	return VINF_SUCCESS;
373	}
374
375
376	/**
377	* @interface_method_impl{PDMDEVREG,pfnDestruct}
378	*/
379	DECLCALLBACK(int) gicR3Destruct(PPDMDEVINS pDevIns)
380	{
381	LogFlowFunc(("pDevIns=%p\n", pDevIns));
382	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
383
384	return VINF_SUCCESS;
385	}
386
387
388	/**
389	* @interface_method_impl{PDMDEVREG,pfnConstruct}
390	*/
391	DECLCALLBACK(int) gicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
392	{
393	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
394	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
395	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
396	PVM pVM = PDMDevHlpGetVM(pDevIns);
397	PGIC pGic = VM_TO_GIC(pVM);
398	Assert(iInstance == 0); NOREF(iInstance);
399
400	/*
401	* Init the data.
402	*/
403	pGic->pDevInsR3 = pDevIns;
404
405	/*
406	* Validate GIC settings.
407	*/
408	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "DistributorMmioBase\|RedistributorMmioBase", "");
409
410	#if 0
411	/*
412	* Disable automatic PDM locking for this device.
413	*/
414	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
415	AssertRCReturn(rc, rc);
416	#else
417	int rc;
418	#endif
419
420	/*
421	* Register the GIC with PDM.
422	*/
423	rc = PDMDevHlpApicRegister(pDevIns);
424	AssertLogRelRCReturn(rc, rc);
425
426	/*
427	* Initialize the GIC state.
428	*/
429	for (uint32_t i = 0; i < RT_ELEMENTS(g_aSysRegRanges_GICv3); i++)
430	{
431	rc = CPUMR3SysRegRangesInsert(pVM, &g_aSysRegRanges_GICv3[i]);
432	AssertLogRelRCReturn(rc, rc);
433	}
434
435	/* Finally, initialize the state. */
436	rc = gicR3InitState(pVM);
437	AssertRCReturn(rc, rc);
438
439	/*
440	* Register the MMIO ranges.
441	*/
442	RTGCPHYS GCPhysMmioBase = 0;
443	rc = pHlp->pfnCFGMQueryU64(pCfg, "DistributorMmioBase", &GCPhysMmioBase);
444	if (RT_FAILURE(rc))
445	return PDMDEV_SET_ERROR(pDevIns, rc,
446	N_("Configuration error: Failed to get the \"DistributorMmioBase\" value"));
447
448	rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, GIC_DIST_REG_FRAME_SIZE, gicDistMmioWrite, gicDistMmioRead,
449	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GICv3_Dist", &pGicDev->hMmioDist);
450	AssertRCReturn(rc, rc);
451
452	rc = pHlp->pfnCFGMQueryU64(pCfg, "RedistributorMmioBase", &GCPhysMmioBase);
453	if (RT_FAILURE(rc))
454	return PDMDEV_SET_ERROR(pDevIns, rc,
455	N_("Configuration error: Failed to get the \"RedistributorMmioBase\" value"));
456
457	RTGCPHYS cbRegion = pVM->cCpus * (GIC_REDIST_REG_FRAME_SIZE + GIC_REDIST_SGI_PPI_REG_FRAME_SIZE); /* Adjacent and per vCPU. */
458	rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, cbRegion, gicReDistMmioWrite, gicReDistMmioRead,
459	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GICv3_ReDist", &pGicDev->hMmioReDist);
460	AssertRCReturn(rc, rc);
461
462	/*
463	* Register saved state callbacks.
464	*/
465	rc = PDMDevHlpSSMRegister(pDevIns, GIC_SAVED_STATE_VERSION, 0, gicR3SaveExec, gicR3LoadExec);
466	AssertRCReturn(rc, rc);
467
468	/*
469	* Register debugger info callbacks.
470	*
471	* We use separate callbacks rather than arguments so they can also be
472	* dumped in an automated fashion while collecting crash diagnostics and
473	* not just used during live debugging via the VM debugger.
474	*/
475	DBGFR3InfoRegisterInternalEx(pVM, "gic", "Dumps GIC basic information.", gicR3Info, DBGFINFO_FLAGS_ALL_EMTS);
476	DBGFR3InfoRegisterInternalEx(pVM, "gicdist", "Dumps GIC Distributor information.", gicR3InfoDist, DBGFINFO_FLAGS_ALL_EMTS);
477	DBGFR3InfoRegisterInternalEx(pVM, "gicredist", "Dumps GIC Redistributor information.", gicR3InfoReDist, DBGFINFO_FLAGS_ALL_EMTS);
478
479	/*
480	* Statistics.
481	*/
482	#define GIC_REG_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
483	PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, \
484	STAMUNIT_OCCURENCES, a_pszDesc, a_pszNameFmt, idCpu)
485	#define GIC_PROF_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
486	PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, \
487	STAMUNIT_TICKS_PER_CALL, a_pszDesc, a_pszNameFmt, idCpu)
488
489	#ifdef VBOX_WITH_STATISTICS
490	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
491	{
492	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
493	PGICCPU pGicCpu = VMCPU_TO_GICCPU(pVCpu);
494
495	# if 0 /* No R0 for now. */
496	GIC_REG_COUNTER(&pGicCpu->StatMmioReadRZ, "%u/RZ/MmioRead", "Number of APIC MMIO reads in RZ.");
497	GIC_REG_COUNTER(&pGicCpu->StatMmioWriteRZ, "%u/RZ/MmioWrite", "Number of APIC MMIO writes in RZ.");
498	GIC_REG_COUNTER(&pGicCpu->StatMsrReadRZ, "%u/RZ/MsrRead", "Number of APIC MSR reads in RZ.");
499	GIC_REG_COUNTER(&pGicCpu->StatMsrWriteRZ, "%u/RZ/MsrWrite", "Number of APIC MSR writes in RZ.");
500	# endif
501
502	GIC_REG_COUNTER(&pGicCpu->StatMmioReadR3, "%u/R3/MmioRead", "Number of APIC MMIO reads in R3.");
503	GIC_REG_COUNTER(&pGicCpu->StatMmioWriteR3, "%u/R3/MmioWrite", "Number of APIC MMIO writes in R3.");
504	GIC_REG_COUNTER(&pGicCpu->StatSysRegReadR3, "%u/R3/SysRegRead", "Number of GIC system register reads in R3.");
505	GIC_REG_COUNTER(&pGicCpu->StatSysRegWriteR3, "%u/R3/SysRegWrite", "Number of GIC system register writes in R3.");
506	}
507	#endif
508
509	# undef GIC_PROF_COUNTER
510
511	gicR3Reset(pDevIns);
512	return VINF_SUCCESS;
513	}
514
515	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
516

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source: vbox/trunk/src/VBox/VMM/VMMR3/GICR3.cpp@ 106360

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