EMRaw.cpp@ 47820

Last change on this file since 47820 was 47820, checked in by vboxsync, 11 years ago
EMRaw.cpp: Disabled code for using IEM for singled instruction emulation like in EMHM.cpp.
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File size: 58.3 KB

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1	/* $Id: EMRaw.cpp 47820 2013-08-16 19:47:36Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager - software virtualization
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_EM
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/vmm.h>
25	#include <VBox/vmm/patm.h>
26	#include <VBox/vmm/csam.h>
27	#include <VBox/vmm/selm.h>
28	#include <VBox/vmm/trpm.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/dbgf.h>
32	#include <VBox/vmm/pgm.h>
33	#ifdef VBOX_WITH_REM
34	# include <VBox/vmm/rem.h>
35	#endif
36	#include <VBox/vmm/tm.h>
37	#include <VBox/vmm/mm.h>
38	#include <VBox/vmm/ssm.h>
39	#include <VBox/vmm/pdmapi.h>
40	#include <VBox/vmm/pdmcritsect.h>
41	#include <VBox/vmm/pdmqueue.h>
42	#include <VBox/vmm/patm.h>
43	#include "EMInternal.h"
44	#include <VBox/vmm/vm.h>
45	#include <VBox/vmm/cpumdis.h>
46	#include <VBox/dis.h>
47	#include <VBox/disopcode.h>
48	#include <VBox/vmm/dbgf.h>
49	#include "VMMTracing.h"
50
51	#include <VBox/log.h>
52	#include <iprt/asm.h>
53	#include <iprt/string.h>
54	#include <iprt/stream.h>
55
56
57
58	/*******************************************************************************
59	* Internal Functions *
60	*******************************************************************************/
61	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
62	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
63	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
64	static int emR3RawPatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret);
65	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu);
66	static int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
67	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu);
68
69	#define EMHANDLERC_WITH_PATM
70	#define emR3ExecuteInstruction emR3RawExecuteInstruction
71	#define emR3ExecuteIOInstruction emR3RawExecuteIOInstruction
72	#include "EMHandleRCTmpl.h"
73
74
75
76	#ifdef VBOX_WITH_STATISTICS
77	/**
78	* Just a braindead function to keep track of cli addresses.
79	* @param pVM Pointer to the VM.
80	* @param pVMCPU Pointer to the VMCPU.
81	* @param GCPtrInstr The EIP of the cli instruction.
82	*/
83	static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
84	{
85	PCLISTAT pRec;
86
87	pRec = (PCLISTAT)RTAvlGCPtrGet(&pVCpu->em.s.pCliStatTree, GCPtrInstr);
88	if (!pRec)
89	{
90	/* New cli instruction; insert into the tree. */
91	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
92	Assert(pRec);
93	if (!pRec)
94	return;
95	pRec->Core.Key = GCPtrInstr;
96
97	char szCliStatName[32];
98	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
99	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
100
101	bool fRc = RTAvlGCPtrInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
102	Assert(fRc); NOREF(fRc);
103	}
104	STAM_COUNTER_INC(&pRec->Counter);
105	STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
106	}
107	#endif /* VBOX_WITH_STATISTICS */
108
109
110
111	/**
112	* Resumes executing hypervisor after a debug event.
113	*
114	* This is kind of special since our current guest state is
115	* potentially out of sync.
116	*
117	* @returns VBox status code.
118	* @param pVM Pointer to the VM.
119	* @param pVCpu Pointer to the VMCPU.
120	*/
121	int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu)
122	{
123	int rc;
124	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
125	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
126	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags));
127
128	/*
129	* Resume execution.
130	*/
131	CPUMRawEnter(pVCpu, NULL);
132	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_RF);
133	rc = VMMR3ResumeHyper(pVM, pVCpu);
134	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags, rc));
135	rc = CPUMRawLeave(pVCpu, NULL, rc);
136	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
137
138	/*
139	* Deal with the return code.
140	*/
141	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
142	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
143	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
144	return rc;
145	}
146
147
148	/**
149	* Steps rawmode.
150	*
151	* @returns VBox status code.
152	* @param pVM Pointer to the VM.
153	* @param pVCpu Pointer to the VMCPU.
154	*/
155	int emR3RawStep(PVM pVM, PVMCPU pVCpu)
156	{
157	Assert( pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
158	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
159	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
160	int rc;
161	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
162	bool fGuest = pVCpu->em.s.enmState != EMSTATE_DEBUG_HYPER;
163	#ifndef DEBUG_sander
164	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
165	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu)));
166	#endif
167	if (fGuest)
168	{
169	/*
170	* Check vital forced actions, but ignore pending interrupts and timers.
171	*/
172	if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
173	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
174	{
175	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
176	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
177	if (rc != VINF_SUCCESS)
178	return rc;
179	}
180
181	/*
182	* Set flags for single stepping.
183	*/
184	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
185	}
186	else
187	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
188
189	/*
190	* Single step.
191	* We do not start time or anything, if anything we should just do a few nanoseconds.
192	*/
193	CPUMRawEnter(pVCpu, NULL);
194	do
195	{
196	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
197	rc = VMMR3ResumeHyper(pVM, pVCpu);
198	else
199	rc = VMMR3RawRunGC(pVM, pVCpu);
200	#ifndef DEBUG_sander
201	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
202	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu), rc));
203	#endif
204	} while ( rc == VINF_SUCCESS
205	\|\| rc == VINF_EM_RAW_INTERRUPT);
206	rc = CPUMRawLeave(pVCpu, NULL, rc);
207	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
208
209	/*
210	* Make sure the trap flag is cleared.
211	* (Too bad if the guest is trying to single step too.)
212	*/
213	if (fGuest)
214	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
215	else
216	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) & ~X86_EFL_TF);
217
218	/*
219	* Deal with the return codes.
220	*/
221	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
222	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
223	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
224	return rc;
225	}
226
227
228	#ifdef DEBUG
229
230
231	int emR3SingleStepExecRaw(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
232	{
233	int rc = VINF_SUCCESS;
234	EMSTATE enmOldState = pVCpu->em.s.enmState;
235	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
236
237	Log(("Single step BEGIN:\n"));
238	for (uint32_t i = 0; i < cIterations; i++)
239	{
240	DBGFR3PrgStep(pVCpu);
241	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "RSS");
242	rc = emR3RawStep(pVM, pVCpu);
243	if ( rc != VINF_SUCCESS
244	&& rc != VINF_EM_DBG_STEPPED)
245	break;
246	}
247	Log(("Single step END: rc=%Rrc\n", rc));
248	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
249	pVCpu->em.s.enmState = enmOldState;
250	return rc;
251	}
252
253	#endif /* DEBUG */
254
255
256	/**
257	* Executes one (or perhaps a few more) instruction(s).
258	*
259	* @returns VBox status code suitable for EM.
260	*
261	* @param pVM Pointer to the VM.
262	* @param pVCpu Pointer to the VMCPU.
263	* @param rcGC GC return code
264	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
265	* instruction and prefix the log output with this text.
266	*/
267	#ifdef LOG_ENABLED
268	static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
269	#else
270	static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
271	#endif
272	{
273	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
274	int rc;
275
276	#ifdef LOG_ENABLED
277	/*
278	* Disassemble the instruction if requested.
279	*/
280	if (pszPrefix)
281	{
282	DBGFR3_INFO_LOG(pVM, "cpumguest", pszPrefix);
283	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, pszPrefix);
284	}
285	#endif /* LOG_ENABLED */
286
287	/*
288	* PATM is making life more interesting.
289	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
290	* tell PATM there is a trap in this code and have it take the appropriate actions
291	* to allow us execute the code in REM.
292	*/
293	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
294	{
295	Log(("emR3RawExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
296
297	RTGCPTR uNewEip;
298	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &uNewEip);
299	switch (rc)
300	{
301	/*
302	* It's not very useful to emulate a single instruction and then go back to raw
303	* mode; just execute the whole block until IF is set again.
304	*/
305	case VINF_SUCCESS:
306	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
307	uNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
308	pCtx->eip = uNewEip;
309	Assert(pCtx->eip);
310
311	if (pCtx->eflags.Bits.u1IF)
312	{
313	/*
314	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
315	*/
316	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
317	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
318	}
319	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
320	{
321	/* special case: iret, that sets IF, detected a pending irq/event */
322	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIRET");
323	}
324	return VINF_EM_RESCHEDULE_REM;
325
326	/*
327	* One instruction.
328	*/
329	case VINF_PATCH_EMULATE_INSTR:
330	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
331	uNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
332	pCtx->eip = uNewEip;
333	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
334
335	/*
336	* The patch was disabled, hand it to the REM.
337	*/
338	case VERR_PATCH_DISABLED:
339	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
340	uNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
341	pCtx->eip = uNewEip;
342	if (pCtx->eflags.Bits.u1IF)
343	{
344	/*
345	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
346	*/
347	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
348	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
349	}
350	return VINF_EM_RESCHEDULE_REM;
351
352	/* Force continued patch exection; usually due to write monitored stack. */
353	case VINF_PATCH_CONTINUE:
354	return VINF_SUCCESS;
355
356	default:
357	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
358	return VERR_IPE_UNEXPECTED_STATUS;
359	}
360	}
361
362
363	/*
364	* Use IEM and fallback on REM if the functionality is missing.
365	* Once IEM gets mature enough, nothing should ever fall back.
366	*/
367	#if 0/defined(VBOX_WITH_FIRST_IEM_STEP)/ \|\| !defined(VBOX_WITH_REM)
368	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
369	STAM_PROFILE_START(&pVCpu->em.s.StatIEMEmu, a);
370	rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu));
371	STAM_PROFILE_STOP(&pVCpu->em.s.StatIEMEmu, a);
372	if (rc == VINF_SUCCESS)
373	rc = VINF_EM_RESCHEDULE;
374	else if ( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
375	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED)
376	#endif
377	{
378	#ifdef VBOX_WITH_REM
379	STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, b);
380	# if 1 //ndef VBOX_WITH_FIRST_IEM_STEP
381	Log(("EMINS[rem]: %04x:%RGv RSP=%RGv\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
382	//# elif defined(DEBUG_bird)
383	// AssertFailed();
384	# endif
385	EMRemLock(pVM);
386	/* Flush the recompiler TLB if the VCPU has changed. */
387	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
388	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
389	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
390
391	rc = REMR3EmulateInstruction(pVM, pVCpu);
392	EMRemUnlock(pVM);
393	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, b);
394	#else /* !VBOX_WITH_REM */
395	NOREF(pVM);
396	#endif /* !VBOX_WITH_REM */
397	}
398	return rc;
399	}
400
401
402	/**
403	* Executes one (or perhaps a few more) instruction(s).
404	* This is just a wrapper for discarding pszPrefix in non-logging builds.
405	*
406	* @returns VBox status code suitable for EM.
407	* @param pVM Pointer to the VM.
408	* @param pVCpu Pointer to the VMCPU.
409	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
410	* instruction and prefix the log output with this text.
411	* @param rcGC GC return code
412	*/
413	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
414	{
415	#ifdef LOG_ENABLED
416	return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
417	#else
418	return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC);
419	#endif
420	}
421
422	/**
423	* Executes one (or perhaps a few more) IO instruction(s).
424	*
425	* @returns VBox status code suitable for EM.
426	* @param pVM Pointer to the VM.
427	* @param pVCpu Pointer to the VMCPU.
428	*/
429	static int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
430	{
431	#ifdef VBOX_WITH_FIRST_IEM_STEP
432	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
433
434	/* Hand it over to the interpreter. */
435	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
436	LogFlow(("emR3RawExecuteIOInstruction: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
437	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoIem);
438	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
439	return VBOXSTRICTRC_TODO(rcStrict);
440
441	#else
442	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
443
444	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
445
446	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
447	* as io instructions tend to come in packages of more than one
448	*/
449	DISCPUSTATE Cpu;
450	int rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
451	if (RT_SUCCESS(rc))
452	{
453	VBOXSTRICTRC rcStrict = VINF_EM_RAW_EMULATE_INSTR;
454
455	if (!(Cpu.fPrefix & (DISPREFIX_REP \| DISPREFIX_REPNE)))
456	{
457	switch (Cpu.pCurInstr->uOpcode)
458	{
459	case OP_IN:
460	{
461	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
462	rcStrict = IOMInterpretIN(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu);
463	break;
464	}
465
466	case OP_OUT:
467	{
468	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
469	rcStrict = IOMInterpretOUT(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu);
470	break;
471	}
472	}
473	}
474	else if (Cpu.fPrefix & DISPREFIX_REP)
475	{
476	switch (Cpu.pCurInstr->uOpcode)
477	{
478	case OP_INSB:
479	case OP_INSWD:
480	{
481	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
482	rcStrict = IOMInterpretINS(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu);
483	break;
484	}
485
486	case OP_OUTSB:
487	case OP_OUTSWD:
488	{
489	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
490	rcStrict = IOMInterpretOUTS(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu);
491	break;
492	}
493	}
494	}
495
496	/*
497	* Handled the I/O return codes.
498	* (The unhandled cases end up with rcStrict == VINF_EM_RAW_EMULATE_INSTR.)
499	*/
500	if (IOM_SUCCESS(rcStrict))
501	{
502	pCtx->rip += Cpu.cbInstr;
503	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
504	return VBOXSTRICTRC_TODO(rcStrict);
505	}
506
507	if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
508	{
509	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
510	rcStrict = emR3RawGuestTrap(pVM, pVCpu);
511	return VBOXSTRICTRC_TODO(rcStrict);
512	}
513	AssertMsg(rcStrict != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
514
515	if (RT_FAILURE(rcStrict))
516	{
517	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
518	return VBOXSTRICTRC_TODO(rcStrict);
519	}
520	AssertMsg(rcStrict == VINF_EM_RAW_EMULATE_INSTR \|\| rcStrict == VINF_EM_RESCHEDULE_REM, ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
521	}
522	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
523	return emR3RawExecuteInstruction(pVM, pVCpu, "IO: ");
524	#endif
525	}
526
527
528	/**
529	* Handle a guest context trap.
530	*
531	* @returns VBox status code suitable for EM.
532	* @param pVM Pointer to the VM.
533	* @param pVCpu Pointer to the VMCPU.
534	*/
535	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu)
536	{
537	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
538
539	/*
540	* Get the trap info.
541	*/
542	uint8_t u8TrapNo;
543	TRPMEVENT enmType;
544	RTGCUINT uErrorCode;
545	RTGCUINTPTR uCR2;
546	int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2, NULL /* pu8InstrLen */);
547	if (RT_FAILURE(rc))
548	{
549	AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
550	return rc;
551	}
552
553
554	#if 1 /* Experimental: Review, disable if it causes trouble. */
555	/*
556	* Handle traps in patch code first.
557	*
558	* We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
559	* but several traps isn't handled specially by TRPM in RC and we end up here
560	* instead. One example is #DE.
561	*/
562	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
563	if ( uCpl == 0
564	&& PATMIsPatchGCAddr(pVM, pCtx->eip))
565	{
566	LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
567	return emR3RawPatchTrap(pVM, pVCpu, pCtx, rc);
568	}
569	#endif
570
571	/*
572	* If the guest gate is marked unpatched, then we will check again if we can patch it.
573	* (This assumes that we've already tried and failed to dispatch the trap in
574	* RC for the gates that already has been patched. Which is true for most high
575	* volume traps, because these are handled specially, but not for odd ones like #DE.)
576	*/
577	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
578	{
579	CSAMR3CheckGates(pVM, u8TrapNo, 1);
580	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
581
582	/* If it was successful, then we could go back to raw mode. */
583	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
584	{
585	/* Must check pending forced actions as our IDT or GDT might be out of sync. */
586	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
587	AssertRCReturn(rc, rc);
588
589	TRPMERRORCODE enmError = uErrorCode != ~0U
590	? TRPM_TRAP_HAS_ERRORCODE
591	: TRPM_TRAP_NO_ERRORCODE;
592	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
593	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
594	{
595	TRPMResetTrap(pVCpu);
596	return VINF_EM_RESCHEDULE_RAW;
597	}
598	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
599	}
600	}
601
602	/*
603	* Scan kernel code that traps; we might not get another chance.
604	*/
605	/** @todo move this up before the dispatching? */
606	if ( (pCtx->ss.Sel & X86_SEL_RPL) <= 1
607	&& !pCtx->eflags.Bits.u1VM)
608	{
609	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
610	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
611	}
612
613	/*
614	* Trap specific handling.
615	*/
616	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
617	{
618	/*
619	* If MONITOR & MWAIT are supported, then interpret them here.
620	*/
621	DISCPUSTATE cpu;
622	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
623	if ( RT_SUCCESS(rc)
624	&& (cpu.pCurInstr->uOpcode == OP_MONITOR \|\| cpu.pCurInstr->uOpcode == OP_MWAIT))
625	{
626	uint32_t u32Dummy, u32Features, u32ExtFeatures;
627	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
628	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
629	{
630	rc = TRPMResetTrap(pVCpu);
631	AssertRC(rc);
632
633	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR));
634	if (RT_SUCCESS(rc))
635	return rc;
636	return emR3RawExecuteInstruction(pVM, pVCpu, "Monitor: ");
637	}
638	}
639	}
640	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
641	{
642	/*
643	* Handle I/O bitmap?
644	*/
645	/** @todo We're not supposed to be here with a false guest trap concerning
646	* I/O access. We can easily handle those in RC. */
647	DISCPUSTATE cpu;
648	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
649	if ( RT_SUCCESS(rc)
650	&& (cpu.pCurInstr->fOpType & DISOPTYPE_PORTIO))
651	{
652	/*
653	* We should really check the TSS for the IO bitmap, but it's not like this
654	* lazy approach really makes things worse.
655	*/
656	rc = TRPMResetTrap(pVCpu);
657	AssertRC(rc);
658	return emR3RawExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
659	}
660	}
661
662	#ifdef LOG_ENABLED
663	DBGFR3_INFO_LOG(pVM, "cpumguest", "Guest trap");
664	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Guest trap");
665
666	/* Get guest page information. */
667	uint64_t fFlags = 0;
668	RTGCPHYS GCPhys = 0;
669	int rc2 = PGMGstGetPage(pVCpu, uCR2, &fFlags, &GCPhys);
670	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
671	pCtx->cs.Sel, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0,
672	(enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
673	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
674	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
675	#endif
676
677	/*
678	* #PG has CR2.
679	* (Because of stuff like above we must set CR2 in a delayed fashion.)
680	*/
681	if (u8TrapNo == 14 /* #PG */)
682	pCtx->cr2 = uCR2;
683
684	return VINF_EM_RESCHEDULE_REM;
685	}
686
687
688	/**
689	* Handle a ring switch trap.
690	* Need to do statistics and to install patches. The result is going to REM.
691	*
692	* @returns VBox status code suitable for EM.
693	* @param pVM Pointer to the VM.
694	* @param pVCpu Pointer to the VMCPU.
695	*/
696	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu)
697	{
698	int rc;
699	DISCPUSTATE Cpu;
700	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
701
702	/*
703	* sysenter, syscall & callgate
704	*/
705	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
706	if (RT_SUCCESS(rc))
707	{
708	if (Cpu.pCurInstr->uOpcode == OP_SYSENTER)
709	{
710	if (pCtx->SysEnter.cs != 0)
711	{
712	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
713	CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0);
714	if (RT_SUCCESS(rc))
715	{
716	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patched sysenter instruction");
717	return VINF_EM_RESCHEDULE_RAW;
718	}
719	}
720	}
721
722	#ifdef VBOX_WITH_STATISTICS
723	switch (Cpu.pCurInstr->uOpcode)
724	{
725	case OP_SYSENTER:
726	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysEnter);
727	break;
728	case OP_SYSEXIT:
729	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysExit);
730	break;
731	case OP_SYSCALL:
732	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysCall);
733	break;
734	case OP_SYSRET:
735	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysRet);
736	break;
737	}
738	#endif
739	}
740	else
741	AssertRC(rc);
742
743	/* go to the REM to emulate a single instruction */
744	return emR3RawExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
745	}
746
747
748	/**
749	* Handle a trap (\#PF or \#GP) in patch code
750	*
751	* @returns VBox status code suitable for EM.
752	* @param pVM Pointer to the VM.
753	* @param pVCpu Pointer to the VMCPU.
754	* @param pCtx Pointer to the guest CPU context.
755	* @param gcret GC return code.
756	*/
757	static int emR3RawPatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret)
758	{
759	uint8_t u8TrapNo;
760	int rc;
761	TRPMEVENT enmType;
762	RTGCUINT uErrorCode;
763	RTGCUINTPTR uCR2;
764
765	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
766
767	if (gcret == VINF_PATM_PATCH_INT3)
768	{
769	u8TrapNo = 3;
770	uCR2 = 0;
771	uErrorCode = 0;
772	}
773	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
774	{
775	/* No active trap in this case. Kind of ugly. */
776	u8TrapNo = X86_XCPT_GP;
777	uCR2 = 0;
778	uErrorCode = 0;
779	}
780	else
781	{
782	rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2, NULL /* pu8InstrLen */);
783	if (RT_FAILURE(rc))
784	{
785	AssertReleaseMsgFailed(("emR3RawPatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
786	return rc;
787	}
788	/* Reset the trap as we'll execute the original instruction again. */
789	TRPMResetTrap(pVCpu);
790	}
791
792	/*
793	* Deal with traps inside patch code.
794	* (This code won't run outside GC.)
795	*/
796	if (u8TrapNo != 1)
797	{
798	#ifdef LOG_ENABLED
799	DBGFR3_INFO_LOG(pVM, "cpumguest", "Trap in patch code");
800	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patch code");
801
802	DISCPUSTATE Cpu;
803	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->eip, &Cpu, "Patch code: ");
804	if ( RT_SUCCESS(rc)
805	&& Cpu.pCurInstr->uOpcode == OP_IRET)
806	{
807	uint32_t eip, selCS, uEFlags;
808
809	/* Iret crashes are bad as we have already changed the flags on the stack */
810	rc = PGMPhysSimpleReadGCPtr(pVCpu, &eip, pCtx->esp, 4);
811	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selCS, pCtx->esp+4, 4);
812	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &uEFlags, pCtx->esp+8, 4);
813	if (rc == VINF_SUCCESS)
814	{
815	if ( (uEFlags & X86_EFL_VM)
816	\|\| (selCS & X86_SEL_RPL) == 3)
817	{
818	uint32_t selSS, esp;
819
820	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &esp, pCtx->esp + 12, 4);
821	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selSS, pCtx->esp + 16, 4);
822
823	if (uEFlags & X86_EFL_VM)
824	{
825	uint32_t selDS, selES, selFS, selGS;
826	rc = PGMPhysSimpleReadGCPtr(pVCpu, &selES, pCtx->esp + 20, 4);
827	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selDS, pCtx->esp + 24, 4);
828	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selFS, pCtx->esp + 28, 4);
829	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selGS, pCtx->esp + 32, 4);
830	if (rc == VINF_SUCCESS)
831	{
832	Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
833	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
834	}
835	}
836	else
837	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
838	}
839	else
840	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
841	}
842	}
843	#endif /* LOG_ENABLED */
844	Log(("emR3RawPatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
845	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
846
847	RTGCPTR uNewEip;
848	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &uNewEip);
849	switch (rc)
850	{
851	/*
852	* Execute the faulting instruction.
853	*/
854	case VINF_SUCCESS:
855	{
856	/** @todo execute a whole block */
857	Log(("emR3RawPatchTrap: Executing faulting instruction at new address %RGv\n", uNewEip));
858	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
859	Log(("emR3RawPatchTrap: Virtual IF flag disabled!!\n"));
860
861	pCtx->eip = uNewEip;
862	AssertRelease(pCtx->eip);
863
864	if (pCtx->eflags.Bits.u1IF)
865	{
866	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
867	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
868	*/
869	if ( u8TrapNo == X86_XCPT_GP
870	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
871	{
872	/** @todo move to PATMR3HandleTrap */
873	Log(("Possible Windows XP iret fault at %08RX32\n", pCtx->eip));
874	PATMR3RemovePatch(pVM, pCtx->eip);
875	}
876
877	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
878	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
879
880	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
881	/* Interrupts are enabled; just go back to the original instruction.
882	return VINF_SUCCESS; */
883	}
884	return VINF_EM_RESCHEDULE_REM;
885	}
886
887	/*
888	* One instruction.
889	*/
890	case VINF_PATCH_EMULATE_INSTR:
891	Log(("emR3RawPatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
892	uNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
893	pCtx->eip = uNewEip;
894	AssertRelease(pCtx->eip);
895	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
896
897	/*
898	* The patch was disabled, hand it to the REM.
899	*/
900	case VERR_PATCH_DISABLED:
901	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
902	Log(("emR3RawPatchTrap: Virtual IF flag disabled!!\n"));
903	pCtx->eip = uNewEip;
904	AssertRelease(pCtx->eip);
905
906	if (pCtx->eflags.Bits.u1IF)
907	{
908	/*
909	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
910	*/
911	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
912	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
913	}
914	return VINF_EM_RESCHEDULE_REM;
915
916	/* Force continued patch exection; usually due to write monitored stack. */
917	case VINF_PATCH_CONTINUE:
918	return VINF_SUCCESS;
919
920	/*
921	* Anything else is fatal.
922	*/
923	default:
924	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
925	return VERR_IPE_UNEXPECTED_STATUS;
926	}
927	}
928	return VINF_SUCCESS;
929	}
930
931
932	/**
933	* Handle a privileged instruction.
934	*
935	* @returns VBox status code suitable for EM.
936	* @param pVM Pointer to the VM.
937	* @param pVCpu Pointer to the VMCPU.
938	*/
939	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu)
940	{
941	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
942
943	Assert(!pCtx->eflags.Bits.u1VM);
944
945	if (PATMIsEnabled(pVM))
946	{
947	/*
948	* Check if in patch code.
949	*/
950	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
951	{
952	#ifdef LOG_ENABLED
953	DBGFR3_INFO_LOG(pVM, "cpumguest", "PRIV");
954	#endif
955	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08x\n", pCtx->eip));
956	return VERR_EM_RAW_PATCH_CONFLICT;
957	}
958	if ( (pCtx->ss.Sel & X86_SEL_RPL) == 0
959	&& !pCtx->eflags.Bits.u1VM
960	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
961	{
962	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
963	CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0);
964	if (RT_SUCCESS(rc))
965	{
966	#ifdef LOG_ENABLED
967	DBGFR3_INFO_LOG(pVM, "cpumguest", "PRIV");
968	#endif
969	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patched privileged instruction");
970	return VINF_SUCCESS;
971	}
972	}
973	}
974
975	#ifdef LOG_ENABLED
976	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
977	{
978	DBGFR3_INFO_LOG(pVM, "cpumguest", "PRIV");
979	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Privileged instr");
980	}
981	#endif
982
983	/*
984	* Instruction statistics and logging.
985	*/
986	DISCPUSTATE Cpu;
987	int rc;
988
989	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "PRIV: ");
990	if (RT_SUCCESS(rc))
991	{
992	#ifdef VBOX_WITH_STATISTICS
993	PEMSTATS pStats = pVCpu->em.s.CTX_SUFF(pStats);
994	switch (Cpu.pCurInstr->uOpcode)
995	{
996	case OP_INVLPG:
997	STAM_COUNTER_INC(&pStats->StatInvlpg);
998	break;
999	case OP_IRET:
1000	STAM_COUNTER_INC(&pStats->StatIret);
1001	break;
1002	case OP_CLI:
1003	STAM_COUNTER_INC(&pStats->StatCli);
1004	emR3RecordCli(pVM, pVCpu, pCtx->rip);
1005	break;
1006	case OP_STI:
1007	STAM_COUNTER_INC(&pStats->StatSti);
1008	break;
1009	case OP_INSB:
1010	case OP_INSWD:
1011	case OP_IN:
1012	case OP_OUTSB:
1013	case OP_OUTSWD:
1014	case OP_OUT:
1015	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1016	break;
1017
1018	case OP_MOV_CR:
1019	if (Cpu.Param1.fUse & DISUSE_REG_GEN32)
1020	{
1021	//read
1022	Assert(Cpu.Param2.fUse & DISUSE_REG_CR);
1023	Assert(Cpu.Param2.Base.idxCtrlReg <= DISCREG_CR4);
1024	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.Param2.Base.idxCtrlReg]);
1025	}
1026	else
1027	{
1028	//write
1029	Assert(Cpu.Param1.fUse & DISUSE_REG_CR);
1030	Assert(Cpu.Param1.Base.idxCtrlReg <= DISCREG_CR4);
1031	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.Param1.Base.idxCtrlReg]);
1032	}
1033	break;
1034
1035	case OP_MOV_DR:
1036	STAM_COUNTER_INC(&pStats->StatMovDRx);
1037	break;
1038	case OP_LLDT:
1039	STAM_COUNTER_INC(&pStats->StatMovLldt);
1040	break;
1041	case OP_LIDT:
1042	STAM_COUNTER_INC(&pStats->StatMovLidt);
1043	break;
1044	case OP_LGDT:
1045	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1046	break;
1047	case OP_SYSENTER:
1048	STAM_COUNTER_INC(&pStats->StatSysEnter);
1049	break;
1050	case OP_SYSEXIT:
1051	STAM_COUNTER_INC(&pStats->StatSysExit);
1052	break;
1053	case OP_SYSCALL:
1054	STAM_COUNTER_INC(&pStats->StatSysCall);
1055	break;
1056	case OP_SYSRET:
1057	STAM_COUNTER_INC(&pStats->StatSysRet);
1058	break;
1059	case OP_HLT:
1060	STAM_COUNTER_INC(&pStats->StatHlt);
1061	break;
1062	default:
1063	STAM_COUNTER_INC(&pStats->StatMisc);
1064	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->uOpcode));
1065	break;
1066	}
1067	#endif /* VBOX_WITH_STATISTICS */
1068	if ( (pCtx->ss.Sel & X86_SEL_RPL) == 0
1069	&& !pCtx->eflags.Bits.u1VM
1070	&& CPUMGetGuestCodeBits(pVCpu) == 32)
1071	{
1072	STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
1073	switch (Cpu.pCurInstr->uOpcode)
1074	{
1075	case OP_CLI:
1076	pCtx->eflags.u32 &= ~X86_EFL_IF;
1077	Assert(Cpu.cbInstr == 1);
1078	pCtx->rip += Cpu.cbInstr;
1079	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1080	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1081
1082	case OP_STI:
1083	pCtx->eflags.u32 \|= X86_EFL_IF;
1084	EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + Cpu.cbInstr);
1085	Assert(Cpu.cbInstr == 1);
1086	pCtx->rip += Cpu.cbInstr;
1087	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1088	return VINF_SUCCESS;
1089
1090	case OP_HLT:
1091	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1092	{
1093	PATMTRANSSTATE enmState;
1094	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1095
1096	if (enmState == PATMTRANS_OVERWRITTEN)
1097	{
1098	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1099	Assert(rc == VERR_PATCH_DISABLED);
1100	/* Conflict detected, patch disabled */
1101	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pCtx->eip));
1102
1103	enmState = PATMTRANS_SAFE;
1104	}
1105
1106	/* The translation had better be successful. Otherwise we can't recover. */
1107	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
1108	if (enmState != PATMTRANS_OVERWRITTEN)
1109	pCtx->eip = pOrgInstrGC;
1110	}
1111	/* no break; we could just return VINF_EM_HALT here */
1112
1113	case OP_MOV_CR:
1114	case OP_MOV_DR:
1115	#ifdef LOG_ENABLED
1116	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1117	{
1118	DBGFR3_INFO_LOG(pVM, "cpumguest", "PRIV");
1119	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Privileged instr");
1120	}
1121	#endif
1122
1123	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR));
1124	if (RT_SUCCESS(rc))
1125	{
1126	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1127
1128	if ( Cpu.pCurInstr->uOpcode == OP_MOV_CR
1129	&& Cpu.Param1.fUse == DISUSE_REG_CR /* write */
1130	)
1131	{
1132	/* Deal with CR0 updates inside patch code that force
1133	* us to go to the recompiler.
1134	*/
1135	if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
1136	&& (pCtx->cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
1137	{
1138	PATMTRANSSTATE enmState;
1139	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
1140
1141	Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
1142	if (enmState == PATMTRANS_OVERWRITTEN)
1143	{
1144	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1145	Assert(rc == VERR_PATCH_DISABLED);
1146	/* Conflict detected, patch disabled */
1147	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pCtx->rip));
1148	enmState = PATMTRANS_SAFE;
1149	}
1150	/* The translation had better be successful. Otherwise we can't recover. */
1151	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
1152	if (enmState != PATMTRANS_OVERWRITTEN)
1153	pCtx->rip = pOrgInstrGC;
1154	}
1155
1156	/* Reschedule is necessary as the execution/paging mode might have changed. */
1157	return VINF_EM_RESCHEDULE;
1158	}
1159	return rc; /* can return VINF_EM_HALT as well. */
1160	}
1161	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
1162	break; /* fall back to the recompiler */
1163	}
1164	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1165	}
1166	}
1167
1168	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1169	return emR3RawPatchTrap(pVM, pVCpu, pCtx, VINF_PATM_PATCH_TRAP_GP);
1170
1171	return emR3RawExecuteInstruction(pVM, pVCpu, "PRIV");
1172	}
1173
1174
1175	/**
1176	* Update the forced rawmode execution modifier.
1177	*
1178	* This function is called when we're returning from the raw-mode loop(s). If we're
1179	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1180	* if not in patch code, the flag will be cleared.
1181	*
1182	* We should never interrupt patch code while it's being executed. Cli patches can
1183	* contain big code blocks, but they are always executed with IF=0. Other patches
1184	* replace single instructions and should be atomic.
1185	*
1186	* @returns Updated rc.
1187	*
1188	* @param pVM Pointer to the VM.
1189	* @param pVCpu Pointer to the VMCPU.
1190	* @param pCtx Pointer to the guest CPU context.
1191	* @param rc The result code.
1192	*/
1193	int emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
1194	{
1195	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1196	{
1197	/* ignore reschedule attempts. */
1198	switch (rc)
1199	{
1200	case VINF_EM_RESCHEDULE:
1201	case VINF_EM_RESCHEDULE_REM:
1202	LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
1203	rc = VINF_SUCCESS;
1204	break;
1205	}
1206	pVCpu->em.s.fForceRAW = true;
1207	}
1208	else
1209	pVCpu->em.s.fForceRAW = false;
1210	return rc;
1211	}
1212
1213
1214	/**
1215	* Check for pending raw actions
1216	*
1217	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1218	* EM statuses.
1219	* @param pVM Pointer to the VM.
1220	* @param pVCpu Pointer to the VMCPU.
1221	*/
1222	VMMR3_INT_DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
1223	{
1224	int rc = emR3RawForcedActions(pVM, pVCpu, pVCpu->em.s.pCtx);
1225	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1226	return rc;
1227	}
1228
1229
1230	/**
1231	* Process raw-mode specific forced actions.
1232	*
1233	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
1234	*
1235	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1236	* EM statuses.
1237	* @param pVM Pointer to the VM.
1238	* @param pVCpu Pointer to the VMCPU.
1239	* @param pCtx Pointer to the guest CPU context.
1240	*/
1241	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1242	{
1243	/*
1244	* Note that the order is vitally important!
1245	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
1246	*/
1247	VBOXVMM_EM_FF_RAW(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions);
1248
1249	/*
1250	* Sync selector tables.
1251	*/
1252	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT))
1253	{
1254	VBOXSTRICTRC rcStrict = SELMR3UpdateFromCPUM(pVM, pVCpu);
1255	if (rcStrict != VINF_SUCCESS)
1256	return VBOXSTRICTRC_TODO(rcStrict);
1257	}
1258
1259	/*
1260	* Sync IDT.
1261	*
1262	* The CSAMR3CheckGates call in TRPMR3SyncIDT may call PGMPrefetchPage
1263	* and PGMShwModifyPage, so we're in for trouble if for instance a
1264	* PGMSyncCR3+pgmR3PoolClearAll is pending.
1265	*/
1266	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
1267	{
1268	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1269	&& EMIsRawRing0Enabled(pVM)
1270	&& CSAMIsEnabled(pVM))
1271	{
1272	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1273	if (RT_FAILURE(rc))
1274	return rc;
1275	}
1276
1277	int rc = TRPMR3SyncIDT(pVM, pVCpu);
1278	if (RT_FAILURE(rc))
1279	return rc;
1280	}
1281
1282	/*
1283	* Sync TSS.
1284	*/
1285	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1286	{
1287	int rc = SELMR3SyncTSS(pVM, pVCpu);
1288	if (RT_FAILURE(rc))
1289	return rc;
1290	}
1291
1292	/*
1293	* Sync page directory.
1294	*/
1295	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1296	{
1297	Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1298	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1299	if (RT_FAILURE(rc))
1300	return rc;
1301
1302	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1303
1304	/* Prefetch pages for EIP and ESP. */
1305	/** @todo This is rather expensive. Should investigate if it really helps at all. */
1306	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
1307	if (rc == VINF_SUCCESS)
1308	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
1309	if (rc != VINF_SUCCESS)
1310	{
1311	if (rc != VINF_PGM_SYNC_CR3)
1312	{
1313	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
1314	return rc;
1315	}
1316	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1317	if (RT_FAILURE(rc))
1318	return rc;
1319	}
1320	/** @todo maybe prefetch the supervisor stack page as well */
1321	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1322	}
1323
1324	/*
1325	* Allocate handy pages (just in case the above actions have consumed some pages).
1326	*/
1327	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1328	{
1329	int rc = PGMR3PhysAllocateHandyPages(pVM);
1330	if (RT_FAILURE(rc))
1331	return rc;
1332	}
1333
1334	/*
1335	* Check whether we're out of memory now.
1336	*
1337	* This may stem from some of the above actions or operations that has been executed
1338	* since we ran FFs. The allocate handy pages must for instance always be followed by
1339	* this check.
1340	*/
1341	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
1342	return VINF_EM_NO_MEMORY;
1343
1344	return VINF_SUCCESS;
1345	}
1346
1347
1348	/**
1349	* Executes raw code.
1350	*
1351	* This function contains the raw-mode version of the inner
1352	* execution loop (the outer loop being in EMR3ExecuteVM()).
1353	*
1354	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1355	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1356	*
1357	* @param pVM Pointer to the VM.
1358	* @param pVCpu Pointer to the VMCPU.
1359	* @param pfFFDone Where to store an indicator telling whether or not
1360	* FFs were done before returning.
1361	*/
1362	int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1363	{
1364	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTotal, a);
1365
1366	int rc = VERR_IPE_UNINITIALIZED_STATUS;
1367	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1368	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs.Sel, pCtx->eip));
1369	pVCpu->em.s.fForceRAW = false;
1370	*pfFFDone = false;
1371
1372
1373	/*
1374	*
1375	* Spin till we get a forced action or raw mode status code resulting in
1376	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
1377	*
1378	*/
1379	for (;;)
1380	{
1381	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWEntry, b);
1382
1383	/*
1384	* Check various preconditions.
1385	*/
1386	#ifdef VBOX_STRICT
1387	# ifdef VBOX_WITH_REM
1388	Assert(REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ);
1389	# endif
1390	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss.Sel & X86_SEL_RPL) == 3 \|\| (pCtx->ss.Sel & X86_SEL_RPL) == 0
1391	\|\| (EMIsRawRing1Enabled(pVM) && (pCtx->ss.Sel & X86_SEL_RPL) == 1));
1392	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
1393	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
1394	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
1395	if ( !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1396	&& PGMMapHasConflicts(pVM))
1397	{
1398	PGMMapCheck(pVM);
1399	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
1400	return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1401	}
1402	#endif /* VBOX_STRICT */
1403
1404	/*
1405	* Process high priority pre-execution raw-mode FFs.
1406	*/
1407	if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1408	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1409	{
1410	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1411	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1412	if (rc != VINF_SUCCESS)
1413	break;
1414	}
1415
1416	/*
1417	* If we're going to execute ring-0 code, the guest state needs to
1418	* be modified a bit and some of the state components (IF, SS/CS RPL,
1419	* and perhaps EIP) needs to be stored with PATM.
1420	*/
1421	rc = CPUMRawEnter(pVCpu, NULL);
1422	if (rc != VINF_SUCCESS)
1423	{
1424	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1425	break;
1426	}
1427
1428	/*
1429	* Scan code before executing it. Don't bother with user mode or V86 code
1430	*/
1431	if ( (pCtx->ss.Sel & X86_SEL_RPL) <= 1
1432	&& !pCtx->eflags.Bits.u1VM
1433	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1434	{
1435	STAM_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWEntry, b);
1436	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1437	STAM_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWEntry, b);
1438	if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1439	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1440	{
1441	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1442	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1443	if (rc != VINF_SUCCESS)
1444	{
1445	rc = CPUMRawLeave(pVCpu, NULL, rc);
1446	break;
1447	}
1448	}
1449	}
1450
1451	#ifdef LOG_ENABLED
1452	/*
1453	* Log important stuff before entering GC.
1454	*/
1455	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
1456	if (pCtx->eflags.Bits.u1VM)
1457	Log(("RV86: %04x:%08x IF=%d VMFlags=%x\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1458	else if ((pCtx->ss.Sel & X86_SEL_RPL) == 1)
1459	Log(("RR0: %x:%08x ESP=%x:%08x EFL=%x IF=%d/%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n",
1460	pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, CPUMRawGetEFlags(pVCpu), !!(pGCState->uVMFlags & X86_EFL_IF), pCtx->eflags.Bits.u1IF,
1461	pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss.Sel & X86_SEL_RPL), CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip)));
1462	# ifdef VBOX_WITH_RAW_RING1
1463	else if ((pCtx->ss.Sel & X86_SEL_RPL) == 2)
1464	Log(("RR1: %x:%08x ESP=%x:%08x IF=%d VMFlags=%x CPL=%x\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, (pCtx->ss.Sel & X86_SEL_RPL)));
1465	# endif
1466	else if ((pCtx->ss.Sel & X86_SEL_RPL) == 3)
1467	Log(("RR3: %x:%08x ESP=%x:%08x IF=%d VMFlags=%x\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1468	#endif /* LOG_ENABLED */
1469
1470
1471
1472	/*
1473	* Execute the code.
1474	*/
1475	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1476	if (RT_LIKELY(emR3IsExecutionAllowed(pVM, pVCpu)))
1477	{
1478	STAM_PROFILE_START(&pVCpu->em.s.StatRAWExec, c);
1479	VBOXVMM_EM_RAW_RUN_PRE(pVCpu, pCtx);
1480	rc = VMMR3RawRunGC(pVM, pVCpu);
1481	VBOXVMM_EM_RAW_RUN_RET(pVCpu, pCtx, rc);
1482	STAM_PROFILE_STOP(&pVCpu->em.s.StatRAWExec, c);
1483	}
1484	else
1485	{
1486	/* Give up this time slice; virtual time continues */
1487	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1488	RTThreadSleep(5);
1489	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1490	rc = VINF_SUCCESS;
1491	}
1492	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTail, d);
1493
1494	LogFlow(("RR%u-E: %08x ESP=%08x EFL=%x IF=%d/%d VMFlags=%x PIF=%d\n",
1495	(pCtx->ss.Sel & X86_SEL_RPL), pCtx->eip, pCtx->esp, CPUMRawGetEFlags(pVCpu),
1496	!!(pGCState->uVMFlags & X86_EFL_IF), pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF));
1497	LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
1498
1499
1500
1501	/*
1502	* Restore the real CPU state and deal with high priority post
1503	* execution FFs before doing anything else.
1504	*/
1505	rc = CPUMRawLeave(pVCpu, NULL, rc);
1506	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1507	if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1508	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1509	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1510
1511	#ifdef VBOX_STRICT
1512	/*
1513	* Assert TSS consistency & rc vs patch code.
1514	*/
1515	if ( !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
1516	&& EMIsRawRing0Enabled(pVM))
1517	SELMR3CheckTSS(pVM);
1518	switch (rc)
1519	{
1520	case VINF_SUCCESS:
1521	case VINF_EM_RAW_INTERRUPT:
1522	case VINF_PATM_PATCH_TRAP_PF:
1523	case VINF_PATM_PATCH_TRAP_GP:
1524	case VINF_PATM_PATCH_INT3:
1525	case VINF_PATM_CHECK_PATCH_PAGE:
1526	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1527	case VINF_EM_RAW_GUEST_TRAP:
1528	case VINF_EM_RESCHEDULE_RAW:
1529	break;
1530
1531	default:
1532	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
1533	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVCpu), rc));
1534	break;
1535	}
1536	/*
1537	* Let's go paranoid!
1538	*/
1539	if ( !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1540	&& PGMMapHasConflicts(pVM))
1541	{
1542	PGMMapCheck(pVM);
1543	AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
1544	return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1545	}
1546	#endif /* VBOX_STRICT */
1547
1548	/*
1549	* Process the returned status code.
1550	*/
1551	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1552	{
1553	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1554	break;
1555	}
1556	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1557	if (rc != VINF_SUCCESS)
1558	{
1559	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1560	if (rc != VINF_SUCCESS)
1561	{
1562	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1563	break;
1564	}
1565	}
1566
1567	/*
1568	* Check and execute forced actions.
1569	*/
1570	#ifdef VBOX_HIGH_RES_TIMERS_HACK
1571	TMTimerPollVoid(pVM, pVCpu);
1572	#endif
1573	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1574	if ( VM_FF_IS_PENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VM_FF_PGM_NO_MEMORY)
1575	\|\| VMCPU_FF_IS_PENDING(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1576	{
1577	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss.Sel & X86_SEL_RPL) != (EMIsRawRing1Enabled(pVM) ? 2 : 1));
1578
1579	STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a);
1580	rc = emR3ForcedActions(pVM, pVCpu, rc);
1581	VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
1582	STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWTotal, a);
1583	if ( rc != VINF_SUCCESS
1584	&& rc != VINF_EM_RESCHEDULE_RAW)
1585	{
1586	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1587	if (rc != VINF_SUCCESS)
1588	{
1589	*pfFFDone = true;
1590	break;
1591	}
1592	}
1593	}
1594	}
1595
1596	/*
1597	* Return to outer loop.
1598	*/
1599	#if defined(LOG_ENABLED) && defined(DEBUG)
1600	RTLogFlush(NULL);
1601	#endif
1602	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTotal, a);
1603	return rc;
1604	}
1605

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source: vbox/trunk/src/VBox/VMM/VMMR3/EMRaw.cpp@ 47820

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