EMRaw.cpp@ 47682

Last change on this file since 47682 was 47421, checked in by vboxsync, 11 years ago
VMM: Use IEM for I/O that's been deferred to ring-3.
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1	/* $Id: EMRaw.cpp 47421 2013-07-26 12:15:44Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager - software virtualization
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_EM
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/vmm.h>
25	#include <VBox/vmm/patm.h>
26	#include <VBox/vmm/csam.h>
27	#include <VBox/vmm/selm.h>
28	#include <VBox/vmm/trpm.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/dbgf.h>
32	#include <VBox/vmm/pgm.h>
33	#ifdef VBOX_WITH_REM
34	# include <VBox/vmm/rem.h>
35	#endif
36	#include <VBox/vmm/tm.h>
37	#include <VBox/vmm/mm.h>
38	#include <VBox/vmm/ssm.h>
39	#include <VBox/vmm/pdmapi.h>
40	#include <VBox/vmm/pdmcritsect.h>
41	#include <VBox/vmm/pdmqueue.h>
42	#include <VBox/vmm/patm.h>
43	#include "EMInternal.h"
44	#include <VBox/vmm/vm.h>
45	#include <VBox/vmm/cpumdis.h>
46	#include <VBox/dis.h>
47	#include <VBox/disopcode.h>
48	#include <VBox/vmm/dbgf.h>
49	#include "VMMTracing.h"
50
51	#include <VBox/log.h>
52	#include <iprt/asm.h>
53	#include <iprt/string.h>
54	#include <iprt/stream.h>
55
56
57
58	/*******************************************************************************
59	* Internal Functions *
60	*******************************************************************************/
61	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
62	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
63	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
64	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret);
65	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu);
66	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
67	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu);
68
69	#define EMHANDLERC_WITH_PATM
70	#include "EMHandleRCTmpl.h"
71
72
73
74	#ifdef VBOX_WITH_STATISTICS
75	/**
76	* Just a braindead function to keep track of cli addresses.
77	* @param pVM Pointer to the VM.
78	* @param pVMCPU Pointer to the VMCPU.
79	* @param GCPtrInstr The EIP of the cli instruction.
80	*/
81	static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
82	{
83	PCLISTAT pRec;
84
85	pRec = (PCLISTAT)RTAvlGCPtrGet(&pVCpu->em.s.pCliStatTree, GCPtrInstr);
86	if (!pRec)
87	{
88	/* New cli instruction; insert into the tree. */
89	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
90	Assert(pRec);
91	if (!pRec)
92	return;
93	pRec->Core.Key = GCPtrInstr;
94
95	char szCliStatName[32];
96	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
97	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
98
99	bool fRc = RTAvlGCPtrInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
100	Assert(fRc); NOREF(fRc);
101	}
102	STAM_COUNTER_INC(&pRec->Counter);
103	STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
104	}
105	#endif /* VBOX_WITH_STATISTICS */
106
107
108
109	/**
110	* Resumes executing hypervisor after a debug event.
111	*
112	* This is kind of special since our current guest state is
113	* potentially out of sync.
114	*
115	* @returns VBox status code.
116	* @param pVM Pointer to the VM.
117	* @param pVCpu Pointer to the VMCPU.
118	*/
119	int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu)
120	{
121	int rc;
122	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
123	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
124	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags));
125
126	/*
127	* Resume execution.
128	*/
129	CPUMRawEnter(pVCpu, NULL);
130	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_RF);
131	rc = VMMR3ResumeHyper(pVM, pVCpu);
132	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags, rc));
133	rc = CPUMRawLeave(pVCpu, NULL, rc);
134	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
135
136	/*
137	* Deal with the return code.
138	*/
139	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
140	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
141	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
142	return rc;
143	}
144
145
146	/**
147	* Steps rawmode.
148	*
149	* @returns VBox status code.
150	* @param pVM Pointer to the VM.
151	* @param pVCpu Pointer to the VMCPU.
152	*/
153	int emR3RawStep(PVM pVM, PVMCPU pVCpu)
154	{
155	Assert( pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
156	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
157	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
158	int rc;
159	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
160	bool fGuest = pVCpu->em.s.enmState != EMSTATE_DEBUG_HYPER;
161	#ifndef DEBUG_sander
162	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
163	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu)));
164	#endif
165	if (fGuest)
166	{
167	/*
168	* Check vital forced actions, but ignore pending interrupts and timers.
169	*/
170	if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
171	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
172	{
173	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
174	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
175	if (rc != VINF_SUCCESS)
176	return rc;
177	}
178
179	/*
180	* Set flags for single stepping.
181	*/
182	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
183	}
184	else
185	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
186
187	/*
188	* Single step.
189	* We do not start time or anything, if anything we should just do a few nanoseconds.
190	*/
191	CPUMRawEnter(pVCpu, NULL);
192	do
193	{
194	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
195	rc = VMMR3ResumeHyper(pVM, pVCpu);
196	else
197	rc = VMMR3RawRunGC(pVM, pVCpu);
198	#ifndef DEBUG_sander
199	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
200	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu), rc));
201	#endif
202	} while ( rc == VINF_SUCCESS
203	\|\| rc == VINF_EM_RAW_INTERRUPT);
204	rc = CPUMRawLeave(pVCpu, NULL, rc);
205	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
206
207	/*
208	* Make sure the trap flag is cleared.
209	* (Too bad if the guest is trying to single step too.)
210	*/
211	if (fGuest)
212	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
213	else
214	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) & ~X86_EFL_TF);
215
216	/*
217	* Deal with the return codes.
218	*/
219	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
220	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
221	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
222	return rc;
223	}
224
225
226	#ifdef DEBUG
227
228
229	int emR3SingleStepExecRaw(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
230	{
231	int rc = VINF_SUCCESS;
232	EMSTATE enmOldState = pVCpu->em.s.enmState;
233	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
234
235	Log(("Single step BEGIN:\n"));
236	for (uint32_t i = 0; i < cIterations; i++)
237	{
238	DBGFR3PrgStep(pVCpu);
239	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "RSS");
240	rc = emR3RawStep(pVM, pVCpu);
241	if ( rc != VINF_SUCCESS
242	&& rc != VINF_EM_DBG_STEPPED)
243	break;
244	}
245	Log(("Single step END: rc=%Rrc\n", rc));
246	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
247	pVCpu->em.s.enmState = enmOldState;
248	return rc;
249	}
250
251	#endif /* DEBUG */
252
253
254	/**
255	* Executes one (or perhaps a few more) instruction(s).
256	*
257	* @returns VBox status code suitable for EM.
258	*
259	* @param pVM Pointer to the VM.
260	* @param pVCpu Pointer to the VMCPU.
261	* @param rcGC GC return code
262	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
263	* instruction and prefix the log output with this text.
264	*/
265	#ifdef LOG_ENABLED
266	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
267	#else
268	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
269	#endif
270	{
271	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
272	int rc;
273
274	/*
275	*
276	* The simple solution is to use the recompiler.
277	* The better solution is to disassemble the current instruction and
278	* try handle as many as possible without using REM.
279	*
280	*/
281
282	#ifdef LOG_ENABLED
283	/*
284	* Disassemble the instruction if requested.
285	*/
286	if (pszPrefix)
287	{
288	DBGFR3_INFO_LOG(pVM, "cpumguest", pszPrefix);
289	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, pszPrefix);
290	}
291	#endif /* LOG_ENABLED */
292
293	/*
294	* PATM is making life more interesting.
295	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
296	* tell PATM there is a trap in this code and have it take the appropriate actions
297	* to allow us execute the code in REM.
298	*/
299	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
300	{
301	Log(("emR3ExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
302
303	RTGCPTR pNewEip;
304	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
305	switch (rc)
306	{
307	/*
308	* It's not very useful to emulate a single instruction and then go back to raw
309	* mode; just execute the whole block until IF is set again.
310	*/
311	case VINF_SUCCESS:
312	Log(("emR3ExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
313	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
314	pCtx->eip = pNewEip;
315	Assert(pCtx->eip);
316
317	if (pCtx->eflags.Bits.u1IF)
318	{
319	/*
320	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
321	*/
322	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
323	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
324	}
325	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
326	{
327	/* special case: iret, that sets IF, detected a pending irq/event */
328	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIRET");
329	}
330	return VINF_EM_RESCHEDULE_REM;
331
332	/*
333	* One instruction.
334	*/
335	case VINF_PATCH_EMULATE_INSTR:
336	Log(("emR3ExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
337	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
338	pCtx->eip = pNewEip;
339	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
340
341	/*
342	* The patch was disabled, hand it to the REM.
343	*/
344	case VERR_PATCH_DISABLED:
345	Log(("emR3ExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
346	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
347	pCtx->eip = pNewEip;
348	if (pCtx->eflags.Bits.u1IF)
349	{
350	/*
351	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
352	*/
353	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
354	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
355	}
356	return VINF_EM_RESCHEDULE_REM;
357
358	/* Force continued patch exection; usually due to write monitored stack. */
359	case VINF_PATCH_CONTINUE:
360	return VINF_SUCCESS;
361
362	default:
363	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
364	return VERR_IPE_UNEXPECTED_STATUS;
365	}
366	}
367
368	STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
369	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
370	#ifdef VBOX_WITH_REM
371	EMRemLock(pVM);
372	/* Flush the recompiler TLB if the VCPU has changed. */
373	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
374	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
375	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
376
377	rc = REMR3EmulateInstruction(pVM, pVCpu);
378	EMRemUnlock(pVM);
379	#else
380	rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu));
381	#endif
382	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a);
383
384	return rc;
385	}
386
387
388	/**
389	* Executes one (or perhaps a few more) instruction(s).
390	* This is just a wrapper for discarding pszPrefix in non-logging builds.
391	*
392	* @returns VBox status code suitable for EM.
393	* @param pVM Pointer to the VM.
394	* @param pVCpu Pointer to the VMCPU.
395	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
396	* instruction and prefix the log output with this text.
397	* @param rcGC GC return code
398	*/
399	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
400	{
401	#ifdef LOG_ENABLED
402	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
403	#else
404	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC);
405	#endif
406	}
407
408	/**
409	* Executes one (or perhaps a few more) IO instruction(s).
410	*
411	* @returns VBox status code suitable for EM.
412	* @param pVM Pointer to the VM.
413	* @param pVCpu Pointer to the VMCPU.
414	*/
415	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
416	{
417	#ifdef VBOX_WITH_FIRST_IEM_STEP
418	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
419
420	/* Hand it over to the interpreter. */
421	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
422	LogFlow(("emR3ExecuteIOInstruction: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
423	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoIem);
424	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
425	return VBOXSTRICTRC_TODO(rcStrict);
426
427	#else
428	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
429
430	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
431
432	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
433	* as io instructions tend to come in packages of more than one
434	*/
435	DISCPUSTATE Cpu;
436	int rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
437	if (RT_SUCCESS(rc))
438	{
439	VBOXSTRICTRC rcStrict = VINF_EM_RAW_EMULATE_INSTR;
440
441	if (!(Cpu.fPrefix & (DISPREFIX_REP \| DISPREFIX_REPNE)))
442	{
443	switch (Cpu.pCurInstr->uOpcode)
444	{
445	case OP_IN:
446	{
447	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
448	rcStrict = IOMInterpretIN(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu);
449	break;
450	}
451
452	case OP_OUT:
453	{
454	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
455	rcStrict = IOMInterpretOUT(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu);
456	break;
457	}
458	}
459	}
460	else if (Cpu.fPrefix & DISPREFIX_REP)
461	{
462	switch (Cpu.pCurInstr->uOpcode)
463	{
464	case OP_INSB:
465	case OP_INSWD:
466	{
467	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
468	rcStrict = IOMInterpretINS(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu);
469	break;
470	}
471
472	case OP_OUTSB:
473	case OP_OUTSWD:
474	{
475	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
476	rcStrict = IOMInterpretOUTS(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu);
477	break;
478	}
479	}
480	}
481
482	/*
483	* Handled the I/O return codes.
484	* (The unhandled cases end up with rcStrict == VINF_EM_RAW_EMULATE_INSTR.)
485	*/
486	if (IOM_SUCCESS(rcStrict))
487	{
488	pCtx->rip += Cpu.cbInstr;
489	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
490	return VBOXSTRICTRC_TODO(rcStrict);
491	}
492
493	if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
494	{
495	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
496	rcStrict = emR3RawGuestTrap(pVM, pVCpu);
497	return VBOXSTRICTRC_TODO(rcStrict);
498	}
499	AssertMsg(rcStrict != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
500
501	if (RT_FAILURE(rcStrict))
502	{
503	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
504	return VBOXSTRICTRC_TODO(rcStrict);
505	}
506	AssertMsg(rcStrict == VINF_EM_RAW_EMULATE_INSTR \|\| rcStrict == VINF_EM_RESCHEDULE_REM, ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
507	}
508	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
509	return emR3ExecuteInstruction(pVM, pVCpu, "IO: ");
510	#endif
511	}
512
513
514	/**
515	* Handle a guest context trap.
516	*
517	* @returns VBox status code suitable for EM.
518	* @param pVM Pointer to the VM.
519	* @param pVCpu Pointer to the VMCPU.
520	*/
521	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu)
522	{
523	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
524
525	/*
526	* Get the trap info.
527	*/
528	uint8_t u8TrapNo;
529	TRPMEVENT enmType;
530	RTGCUINT uErrorCode;
531	RTGCUINTPTR uCR2;
532	int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2, NULL /* pu8InstrLen */);
533	if (RT_FAILURE(rc))
534	{
535	AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
536	return rc;
537	}
538
539
540	#if 1 /* Experimental: Review, disable if it causes trouble. */
541	/*
542	* Handle traps in patch code first.
543	*
544	* We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
545	* but several traps isn't handled specially by TRPM in RC and we end up here
546	* instead. One example is #DE.
547	*/
548	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
549	if ( uCpl == 0
550	&& PATMIsPatchGCAddr(pVM, pCtx->eip))
551	{
552	LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
553	return emR3PatchTrap(pVM, pVCpu, pCtx, rc);
554	}
555	#endif
556
557	/*
558	* If the guest gate is marked unpatched, then we will check again if we can patch it.
559	* (This assumes that we've already tried and failed to dispatch the trap in
560	* RC for the gates that already has been patched. Which is true for most high
561	* volume traps, because these are handled specially, but not for odd ones like #DE.)
562	*/
563	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
564	{
565	CSAMR3CheckGates(pVM, u8TrapNo, 1);
566	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
567
568	/* If it was successful, then we could go back to raw mode. */
569	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
570	{
571	/* Must check pending forced actions as our IDT or GDT might be out of sync. */
572	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
573	AssertRCReturn(rc, rc);
574
575	TRPMERRORCODE enmError = uErrorCode != ~0U
576	? TRPM_TRAP_HAS_ERRORCODE
577	: TRPM_TRAP_NO_ERRORCODE;
578	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
579	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
580	{
581	TRPMResetTrap(pVCpu);
582	return VINF_EM_RESCHEDULE_RAW;
583	}
584	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
585	}
586	}
587
588	/*
589	* Scan kernel code that traps; we might not get another chance.
590	*/
591	/** @todo move this up before the dispatching? */
592	if ( (pCtx->ss.Sel & X86_SEL_RPL) <= 1
593	&& !pCtx->eflags.Bits.u1VM)
594	{
595	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
596	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
597	}
598
599	/*
600	* Trap specific handling.
601	*/
602	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
603	{
604	/*
605	* If MONITOR & MWAIT are supported, then interpret them here.
606	*/
607	DISCPUSTATE cpu;
608	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
609	if ( RT_SUCCESS(rc)
610	&& (cpu.pCurInstr->uOpcode == OP_MONITOR \|\| cpu.pCurInstr->uOpcode == OP_MWAIT))
611	{
612	uint32_t u32Dummy, u32Features, u32ExtFeatures;
613	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
614	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
615	{
616	rc = TRPMResetTrap(pVCpu);
617	AssertRC(rc);
618
619	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR));
620	if (RT_SUCCESS(rc))
621	return rc;
622	return emR3ExecuteInstruction(pVM, pVCpu, "Monitor: ");
623	}
624	}
625	}
626	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
627	{
628	/*
629	* Handle I/O bitmap?
630	*/
631	/** @todo We're not supposed to be here with a false guest trap concerning
632	* I/O access. We can easily handle those in RC. */
633	DISCPUSTATE cpu;
634	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
635	if ( RT_SUCCESS(rc)
636	&& (cpu.pCurInstr->fOpType & DISOPTYPE_PORTIO))
637	{
638	/*
639	* We should really check the TSS for the IO bitmap, but it's not like this
640	* lazy approach really makes things worse.
641	*/
642	rc = TRPMResetTrap(pVCpu);
643	AssertRC(rc);
644	return emR3ExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
645	}
646	}
647
648	#ifdef LOG_ENABLED
649	DBGFR3_INFO_LOG(pVM, "cpumguest", "Guest trap");
650	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Guest trap");
651
652	/* Get guest page information. */
653	uint64_t fFlags = 0;
654	RTGCPHYS GCPhys = 0;
655	int rc2 = PGMGstGetPage(pVCpu, uCR2, &fFlags, &GCPhys);
656	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
657	pCtx->cs.Sel, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0,
658	(enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
659	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
660	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
661	#endif
662
663	/*
664	* #PG has CR2.
665	* (Because of stuff like above we must set CR2 in a delayed fashion.)
666	*/
667	if (u8TrapNo == 14 /* #PG */)
668	pCtx->cr2 = uCR2;
669
670	return VINF_EM_RESCHEDULE_REM;
671	}
672
673
674	/**
675	* Handle a ring switch trap.
676	* Need to do statistics and to install patches. The result is going to REM.
677	*
678	* @returns VBox status code suitable for EM.
679	* @param pVM Pointer to the VM.
680	* @param pVCpu Pointer to the VMCPU.
681	*/
682	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu)
683	{
684	int rc;
685	DISCPUSTATE Cpu;
686	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
687
688	/*
689	* sysenter, syscall & callgate
690	*/
691	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
692	if (RT_SUCCESS(rc))
693	{
694	if (Cpu.pCurInstr->uOpcode == OP_SYSENTER)
695	{
696	if (pCtx->SysEnter.cs != 0)
697	{
698	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
699	CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0);
700	if (RT_SUCCESS(rc))
701	{
702	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patched sysenter instruction");
703	return VINF_EM_RESCHEDULE_RAW;
704	}
705	}
706	}
707
708	#ifdef VBOX_WITH_STATISTICS
709	switch (Cpu.pCurInstr->uOpcode)
710	{
711	case OP_SYSENTER:
712	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysEnter);
713	break;
714	case OP_SYSEXIT:
715	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysExit);
716	break;
717	case OP_SYSCALL:
718	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysCall);
719	break;
720	case OP_SYSRET:
721	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysRet);
722	break;
723	}
724	#endif
725	}
726	else
727	AssertRC(rc);
728
729	/* go to the REM to emulate a single instruction */
730	return emR3ExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
731	}
732
733
734	/**
735	* Handle a trap (\#PF or \#GP) in patch code
736	*
737	* @returns VBox status code suitable for EM.
738	* @param pVM Pointer to the VM.
739	* @param pVCpu Pointer to the VMCPU.
740	* @param pCtx Pointer to the guest CPU context.
741	* @param gcret GC return code.
742	*/
743	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret)
744	{
745	uint8_t u8TrapNo;
746	int rc;
747	TRPMEVENT enmType;
748	RTGCUINT uErrorCode;
749	RTGCUINTPTR uCR2;
750
751	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
752
753	if (gcret == VINF_PATM_PATCH_INT3)
754	{
755	u8TrapNo = 3;
756	uCR2 = 0;
757	uErrorCode = 0;
758	}
759	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
760	{
761	/* No active trap in this case. Kind of ugly. */
762	u8TrapNo = X86_XCPT_GP;
763	uCR2 = 0;
764	uErrorCode = 0;
765	}
766	else
767	{
768	rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2, NULL /* pu8InstrLen */);
769	if (RT_FAILURE(rc))
770	{
771	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
772	return rc;
773	}
774	/* Reset the trap as we'll execute the original instruction again. */
775	TRPMResetTrap(pVCpu);
776	}
777
778	/*
779	* Deal with traps inside patch code.
780	* (This code won't run outside GC.)
781	*/
782	if (u8TrapNo != 1)
783	{
784	#ifdef LOG_ENABLED
785	DBGFR3_INFO_LOG(pVM, "cpumguest", "Trap in patch code");
786	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patch code");
787
788	DISCPUSTATE Cpu;
789	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->eip, &Cpu, "Patch code: ");
790	if ( RT_SUCCESS(rc)
791	&& Cpu.pCurInstr->uOpcode == OP_IRET)
792	{
793	uint32_t eip, selCS, uEFlags;
794
795	/* Iret crashes are bad as we have already changed the flags on the stack */
796	rc = PGMPhysSimpleReadGCPtr(pVCpu, &eip, pCtx->esp, 4);
797	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selCS, pCtx->esp+4, 4);
798	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &uEFlags, pCtx->esp+8, 4);
799	if (rc == VINF_SUCCESS)
800	{
801	if ( (uEFlags & X86_EFL_VM)
802	\|\| (selCS & X86_SEL_RPL) == 3)
803	{
804	uint32_t selSS, esp;
805
806	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &esp, pCtx->esp + 12, 4);
807	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selSS, pCtx->esp + 16, 4);
808
809	if (uEFlags & X86_EFL_VM)
810	{
811	uint32_t selDS, selES, selFS, selGS;
812	rc = PGMPhysSimpleReadGCPtr(pVCpu, &selES, pCtx->esp + 20, 4);
813	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selDS, pCtx->esp + 24, 4);
814	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selFS, pCtx->esp + 28, 4);
815	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selGS, pCtx->esp + 32, 4);
816	if (rc == VINF_SUCCESS)
817	{
818	Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
819	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
820	}
821	}
822	else
823	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
824	}
825	else
826	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
827	}
828	}
829	#endif /* LOG_ENABLED */
830	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
831	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
832
833	RTGCPTR pNewEip;
834	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
835	switch (rc)
836	{
837	/*
838	* Execute the faulting instruction.
839	*/
840	case VINF_SUCCESS:
841	{
842	/** @todo execute a whole block */
843	Log(("emR3PatchTrap: Executing faulting instruction at new address %RGv\n", pNewEip));
844	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
845	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
846
847	pCtx->eip = pNewEip;
848	AssertRelease(pCtx->eip);
849
850	if (pCtx->eflags.Bits.u1IF)
851	{
852	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
853	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
854	*/
855	if ( u8TrapNo == X86_XCPT_GP
856	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
857	{
858	/** @todo move to PATMR3HandleTrap */
859	Log(("Possible Windows XP iret fault at %08RX32\n", pCtx->eip));
860	PATMR3RemovePatch(pVM, pCtx->eip);
861	}
862
863	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
864	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
865
866	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
867	/* Interrupts are enabled; just go back to the original instruction.
868	return VINF_SUCCESS; */
869	}
870	return VINF_EM_RESCHEDULE_REM;
871	}
872
873	/*
874	* One instruction.
875	*/
876	case VINF_PATCH_EMULATE_INSTR:
877	Log(("emR3PatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
878	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
879	pCtx->eip = pNewEip;
880	AssertRelease(pCtx->eip);
881	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
882
883	/*
884	* The patch was disabled, hand it to the REM.
885	*/
886	case VERR_PATCH_DISABLED:
887	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
888	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
889	pCtx->eip = pNewEip;
890	AssertRelease(pCtx->eip);
891
892	if (pCtx->eflags.Bits.u1IF)
893	{
894	/*
895	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
896	*/
897	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
898	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
899	}
900	return VINF_EM_RESCHEDULE_REM;
901
902	/* Force continued patch exection; usually due to write monitored stack. */
903	case VINF_PATCH_CONTINUE:
904	return VINF_SUCCESS;
905
906	/*
907	* Anything else is fatal.
908	*/
909	default:
910	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
911	return VERR_IPE_UNEXPECTED_STATUS;
912	}
913	}
914	return VINF_SUCCESS;
915	}
916
917
918	/**
919	* Handle a privileged instruction.
920	*
921	* @returns VBox status code suitable for EM.
922	* @param pVM Pointer to the VM.
923	* @param pVCpu Pointer to the VMCPU.
924	*/
925	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu)
926	{
927	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
928
929	Assert(!pCtx->eflags.Bits.u1VM);
930
931	if (PATMIsEnabled(pVM))
932	{
933	/*
934	* Check if in patch code.
935	*/
936	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
937	{
938	#ifdef LOG_ENABLED
939	DBGFR3_INFO_LOG(pVM, "cpumguest", "PRIV");
940	#endif
941	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08x\n", pCtx->eip));
942	return VERR_EM_RAW_PATCH_CONFLICT;
943	}
944	if ( (pCtx->ss.Sel & X86_SEL_RPL) == 0
945	&& !pCtx->eflags.Bits.u1VM
946	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
947	{
948	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
949	CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0);
950	if (RT_SUCCESS(rc))
951	{
952	#ifdef LOG_ENABLED
953	DBGFR3_INFO_LOG(pVM, "cpumguest", "PRIV");
954	#endif
955	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patched privileged instruction");
956	return VINF_SUCCESS;
957	}
958	}
959	}
960
961	#ifdef LOG_ENABLED
962	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
963	{
964	DBGFR3_INFO_LOG(pVM, "cpumguest", "PRIV");
965	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Privileged instr");
966	}
967	#endif
968
969	/*
970	* Instruction statistics and logging.
971	*/
972	DISCPUSTATE Cpu;
973	int rc;
974
975	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "PRIV: ");
976	if (RT_SUCCESS(rc))
977	{
978	#ifdef VBOX_WITH_STATISTICS
979	PEMSTATS pStats = pVCpu->em.s.CTX_SUFF(pStats);
980	switch (Cpu.pCurInstr->uOpcode)
981	{
982	case OP_INVLPG:
983	STAM_COUNTER_INC(&pStats->StatInvlpg);
984	break;
985	case OP_IRET:
986	STAM_COUNTER_INC(&pStats->StatIret);
987	break;
988	case OP_CLI:
989	STAM_COUNTER_INC(&pStats->StatCli);
990	emR3RecordCli(pVM, pVCpu, pCtx->rip);
991	break;
992	case OP_STI:
993	STAM_COUNTER_INC(&pStats->StatSti);
994	break;
995	case OP_INSB:
996	case OP_INSWD:
997	case OP_IN:
998	case OP_OUTSB:
999	case OP_OUTSWD:
1000	case OP_OUT:
1001	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1002	break;
1003
1004	case OP_MOV_CR:
1005	if (Cpu.Param1.fUse & DISUSE_REG_GEN32)
1006	{
1007	//read
1008	Assert(Cpu.Param2.fUse & DISUSE_REG_CR);
1009	Assert(Cpu.Param2.Base.idxCtrlReg <= DISCREG_CR4);
1010	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.Param2.Base.idxCtrlReg]);
1011	}
1012	else
1013	{
1014	//write
1015	Assert(Cpu.Param1.fUse & DISUSE_REG_CR);
1016	Assert(Cpu.Param1.Base.idxCtrlReg <= DISCREG_CR4);
1017	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.Param1.Base.idxCtrlReg]);
1018	}
1019	break;
1020
1021	case OP_MOV_DR:
1022	STAM_COUNTER_INC(&pStats->StatMovDRx);
1023	break;
1024	case OP_LLDT:
1025	STAM_COUNTER_INC(&pStats->StatMovLldt);
1026	break;
1027	case OP_LIDT:
1028	STAM_COUNTER_INC(&pStats->StatMovLidt);
1029	break;
1030	case OP_LGDT:
1031	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1032	break;
1033	case OP_SYSENTER:
1034	STAM_COUNTER_INC(&pStats->StatSysEnter);
1035	break;
1036	case OP_SYSEXIT:
1037	STAM_COUNTER_INC(&pStats->StatSysExit);
1038	break;
1039	case OP_SYSCALL:
1040	STAM_COUNTER_INC(&pStats->StatSysCall);
1041	break;
1042	case OP_SYSRET:
1043	STAM_COUNTER_INC(&pStats->StatSysRet);
1044	break;
1045	case OP_HLT:
1046	STAM_COUNTER_INC(&pStats->StatHlt);
1047	break;
1048	default:
1049	STAM_COUNTER_INC(&pStats->StatMisc);
1050	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->uOpcode));
1051	break;
1052	}
1053	#endif /* VBOX_WITH_STATISTICS */
1054	if ( (pCtx->ss.Sel & X86_SEL_RPL) == 0
1055	&& !pCtx->eflags.Bits.u1VM
1056	&& CPUMGetGuestCodeBits(pVCpu) == 32)
1057	{
1058	STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
1059	switch (Cpu.pCurInstr->uOpcode)
1060	{
1061	case OP_CLI:
1062	pCtx->eflags.u32 &= ~X86_EFL_IF;
1063	Assert(Cpu.cbInstr == 1);
1064	pCtx->rip += Cpu.cbInstr;
1065	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1066	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1067
1068	case OP_STI:
1069	pCtx->eflags.u32 \|= X86_EFL_IF;
1070	EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + Cpu.cbInstr);
1071	Assert(Cpu.cbInstr == 1);
1072	pCtx->rip += Cpu.cbInstr;
1073	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1074	return VINF_SUCCESS;
1075
1076	case OP_HLT:
1077	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1078	{
1079	PATMTRANSSTATE enmState;
1080	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1081
1082	if (enmState == PATMTRANS_OVERWRITTEN)
1083	{
1084	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1085	Assert(rc == VERR_PATCH_DISABLED);
1086	/* Conflict detected, patch disabled */
1087	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pCtx->eip));
1088
1089	enmState = PATMTRANS_SAFE;
1090	}
1091
1092	/* The translation had better be successful. Otherwise we can't recover. */
1093	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
1094	if (enmState != PATMTRANS_OVERWRITTEN)
1095	pCtx->eip = pOrgInstrGC;
1096	}
1097	/* no break; we could just return VINF_EM_HALT here */
1098
1099	case OP_MOV_CR:
1100	case OP_MOV_DR:
1101	#ifdef LOG_ENABLED
1102	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1103	{
1104	DBGFR3_INFO_LOG(pVM, "cpumguest", "PRIV");
1105	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Privileged instr");
1106	}
1107	#endif
1108
1109	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR));
1110	if (RT_SUCCESS(rc))
1111	{
1112	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1113
1114	if ( Cpu.pCurInstr->uOpcode == OP_MOV_CR
1115	&& Cpu.Param1.fUse == DISUSE_REG_CR /* write */
1116	)
1117	{
1118	/* Deal with CR0 updates inside patch code that force
1119	* us to go to the recompiler.
1120	*/
1121	if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
1122	&& (pCtx->cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
1123	{
1124	PATMTRANSSTATE enmState;
1125	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
1126
1127	Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
1128	if (enmState == PATMTRANS_OVERWRITTEN)
1129	{
1130	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1131	Assert(rc == VERR_PATCH_DISABLED);
1132	/* Conflict detected, patch disabled */
1133	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pCtx->rip));
1134	enmState = PATMTRANS_SAFE;
1135	}
1136	/* The translation had better be successful. Otherwise we can't recover. */
1137	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
1138	if (enmState != PATMTRANS_OVERWRITTEN)
1139	pCtx->rip = pOrgInstrGC;
1140	}
1141
1142	/* Reschedule is necessary as the execution/paging mode might have changed. */
1143	return VINF_EM_RESCHEDULE;
1144	}
1145	return rc; /* can return VINF_EM_HALT as well. */
1146	}
1147	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
1148	break; /* fall back to the recompiler */
1149	}
1150	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1151	}
1152	}
1153
1154	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1155	return emR3PatchTrap(pVM, pVCpu, pCtx, VINF_PATM_PATCH_TRAP_GP);
1156
1157	return emR3ExecuteInstruction(pVM, pVCpu, "PRIV");
1158	}
1159
1160
1161	/**
1162	* Update the forced rawmode execution modifier.
1163	*
1164	* This function is called when we're returning from the raw-mode loop(s). If we're
1165	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1166	* if not in patch code, the flag will be cleared.
1167	*
1168	* We should never interrupt patch code while it's being executed. Cli patches can
1169	* contain big code blocks, but they are always executed with IF=0. Other patches
1170	* replace single instructions and should be atomic.
1171	*
1172	* @returns Updated rc.
1173	*
1174	* @param pVM Pointer to the VM.
1175	* @param pVCpu Pointer to the VMCPU.
1176	* @param pCtx Pointer to the guest CPU context.
1177	* @param rc The result code.
1178	*/
1179	int emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
1180	{
1181	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1182	{
1183	/* ignore reschedule attempts. */
1184	switch (rc)
1185	{
1186	case VINF_EM_RESCHEDULE:
1187	case VINF_EM_RESCHEDULE_REM:
1188	LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
1189	rc = VINF_SUCCESS;
1190	break;
1191	}
1192	pVCpu->em.s.fForceRAW = true;
1193	}
1194	else
1195	pVCpu->em.s.fForceRAW = false;
1196	return rc;
1197	}
1198
1199
1200	/**
1201	* Check for pending raw actions
1202	*
1203	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1204	* EM statuses.
1205	* @param pVM Pointer to the VM.
1206	* @param pVCpu Pointer to the VMCPU.
1207	*/
1208	VMMR3_INT_DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
1209	{
1210	int rc = emR3RawForcedActions(pVM, pVCpu, pVCpu->em.s.pCtx);
1211	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1212	return rc;
1213	}
1214
1215
1216	/**
1217	* Process raw-mode specific forced actions.
1218	*
1219	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
1220	*
1221	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1222	* EM statuses.
1223	* @param pVM Pointer to the VM.
1224	* @param pVCpu Pointer to the VMCPU.
1225	* @param pCtx Pointer to the guest CPU context.
1226	*/
1227	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1228	{
1229	/*
1230	* Note that the order is vitally important!
1231	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
1232	*/
1233	VBOXVMM_EM_FF_RAW(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions);
1234
1235	/*
1236	* Sync selector tables.
1237	*/
1238	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT))
1239	{
1240	VBOXSTRICTRC rcStrict = SELMR3UpdateFromCPUM(pVM, pVCpu);
1241	if (rcStrict != VINF_SUCCESS)
1242	return VBOXSTRICTRC_TODO(rcStrict);
1243	}
1244
1245	/*
1246	* Sync IDT.
1247	*
1248	* The CSAMR3CheckGates call in TRPMR3SyncIDT may call PGMPrefetchPage
1249	* and PGMShwModifyPage, so we're in for trouble if for instance a
1250	* PGMSyncCR3+pgmR3PoolClearAll is pending.
1251	*/
1252	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
1253	{
1254	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1255	&& EMIsRawRing0Enabled(pVM)
1256	&& CSAMIsEnabled(pVM))
1257	{
1258	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1259	if (RT_FAILURE(rc))
1260	return rc;
1261	}
1262
1263	int rc = TRPMR3SyncIDT(pVM, pVCpu);
1264	if (RT_FAILURE(rc))
1265	return rc;
1266	}
1267
1268	/*
1269	* Sync TSS.
1270	*/
1271	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1272	{
1273	int rc = SELMR3SyncTSS(pVM, pVCpu);
1274	if (RT_FAILURE(rc))
1275	return rc;
1276	}
1277
1278	/*
1279	* Sync page directory.
1280	*/
1281	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1282	{
1283	Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1284	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1285	if (RT_FAILURE(rc))
1286	return rc;
1287
1288	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1289
1290	/* Prefetch pages for EIP and ESP. */
1291	/** @todo This is rather expensive. Should investigate if it really helps at all. */
1292	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
1293	if (rc == VINF_SUCCESS)
1294	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
1295	if (rc != VINF_SUCCESS)
1296	{
1297	if (rc != VINF_PGM_SYNC_CR3)
1298	{
1299	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
1300	return rc;
1301	}
1302	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1303	if (RT_FAILURE(rc))
1304	return rc;
1305	}
1306	/** @todo maybe prefetch the supervisor stack page as well */
1307	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1308	}
1309
1310	/*
1311	* Allocate handy pages (just in case the above actions have consumed some pages).
1312	*/
1313	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1314	{
1315	int rc = PGMR3PhysAllocateHandyPages(pVM);
1316	if (RT_FAILURE(rc))
1317	return rc;
1318	}
1319
1320	/*
1321	* Check whether we're out of memory now.
1322	*
1323	* This may stem from some of the above actions or operations that has been executed
1324	* since we ran FFs. The allocate handy pages must for instance always be followed by
1325	* this check.
1326	*/
1327	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
1328	return VINF_EM_NO_MEMORY;
1329
1330	return VINF_SUCCESS;
1331	}
1332
1333
1334	/**
1335	* Executes raw code.
1336	*
1337	* This function contains the raw-mode version of the inner
1338	* execution loop (the outer loop being in EMR3ExecuteVM()).
1339	*
1340	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1341	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1342	*
1343	* @param pVM Pointer to the VM.
1344	* @param pVCpu Pointer to the VMCPU.
1345	* @param pfFFDone Where to store an indicator telling whether or not
1346	* FFs were done before returning.
1347	*/
1348	int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1349	{
1350	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTotal, a);
1351
1352	int rc = VERR_IPE_UNINITIALIZED_STATUS;
1353	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1354	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs.Sel, pCtx->eip));
1355	pVCpu->em.s.fForceRAW = false;
1356	*pfFFDone = false;
1357
1358
1359	/*
1360	*
1361	* Spin till we get a forced action or raw mode status code resulting in
1362	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
1363	*
1364	*/
1365	for (;;)
1366	{
1367	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWEntry, b);
1368
1369	/*
1370	* Check various preconditions.
1371	*/
1372	#ifdef VBOX_STRICT
1373	# ifdef VBOX_WITH_REM
1374	Assert(REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ);
1375	# endif
1376	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss.Sel & X86_SEL_RPL) == 3 \|\| (pCtx->ss.Sel & X86_SEL_RPL) == 0
1377	\|\| (EMIsRawRing1Enabled(pVM) && (pCtx->ss.Sel & X86_SEL_RPL) == 1));
1378	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
1379	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
1380	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
1381	if ( !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1382	&& PGMMapHasConflicts(pVM))
1383	{
1384	PGMMapCheck(pVM);
1385	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
1386	return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1387	}
1388	#endif /* VBOX_STRICT */
1389
1390	/*
1391	* Process high priority pre-execution raw-mode FFs.
1392	*/
1393	if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1394	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1395	{
1396	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1397	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1398	if (rc != VINF_SUCCESS)
1399	break;
1400	}
1401
1402	/*
1403	* If we're going to execute ring-0 code, the guest state needs to
1404	* be modified a bit and some of the state components (IF, SS/CS RPL,
1405	* and perhaps EIP) needs to be stored with PATM.
1406	*/
1407	rc = CPUMRawEnter(pVCpu, NULL);
1408	if (rc != VINF_SUCCESS)
1409	{
1410	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1411	break;
1412	}
1413
1414	/*
1415	* Scan code before executing it. Don't bother with user mode or V86 code
1416	*/
1417	if ( (pCtx->ss.Sel & X86_SEL_RPL) <= 1
1418	&& !pCtx->eflags.Bits.u1VM
1419	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1420	{
1421	STAM_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWEntry, b);
1422	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1423	STAM_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWEntry, b);
1424	if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1425	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1426	{
1427	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1428	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1429	if (rc != VINF_SUCCESS)
1430	{
1431	rc = CPUMRawLeave(pVCpu, NULL, rc);
1432	break;
1433	}
1434	}
1435	}
1436
1437	#ifdef LOG_ENABLED
1438	/*
1439	* Log important stuff before entering GC.
1440	*/
1441	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
1442	if (pCtx->eflags.Bits.u1VM)
1443	Log(("RV86: %04x:%08x IF=%d VMFlags=%x\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1444	else if ((pCtx->ss.Sel & X86_SEL_RPL) == 1)
1445	Log(("RR0: %x:%08x ESP=%x:%08x EFL=%x IF=%d/%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n",
1446	pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, CPUMRawGetEFlags(pVCpu), !!(pGCState->uVMFlags & X86_EFL_IF), pCtx->eflags.Bits.u1IF,
1447	pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss.Sel & X86_SEL_RPL), CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip)));
1448	# ifdef VBOX_WITH_RAW_RING1
1449	else if ((pCtx->ss.Sel & X86_SEL_RPL) == 2)
1450	Log(("RR1: %x:%08x ESP=%x:%08x IF=%d VMFlags=%x CPL=%x\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, (pCtx->ss.Sel & X86_SEL_RPL)));
1451	# endif
1452	else if ((pCtx->ss.Sel & X86_SEL_RPL) == 3)
1453	Log(("RR3: %x:%08x ESP=%x:%08x IF=%d VMFlags=%x\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1454	#endif /* LOG_ENABLED */
1455
1456
1457
1458	/*
1459	* Execute the code.
1460	*/
1461	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1462	if (RT_LIKELY(emR3IsExecutionAllowed(pVM, pVCpu)))
1463	{
1464	STAM_PROFILE_START(&pVCpu->em.s.StatRAWExec, c);
1465	VBOXVMM_EM_RAW_RUN_PRE(pVCpu, pCtx);
1466	rc = VMMR3RawRunGC(pVM, pVCpu);
1467	VBOXVMM_EM_RAW_RUN_RET(pVCpu, pCtx, rc);
1468	STAM_PROFILE_STOP(&pVCpu->em.s.StatRAWExec, c);
1469	}
1470	else
1471	{
1472	/* Give up this time slice; virtual time continues */
1473	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1474	RTThreadSleep(5);
1475	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1476	rc = VINF_SUCCESS;
1477	}
1478	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTail, d);
1479
1480	LogFlow(("RR%u-E: %08x ESP=%08x EFL=%x IF=%d/%d VMFlags=%x PIF=%d\n",
1481	(pCtx->ss.Sel & X86_SEL_RPL), pCtx->eip, pCtx->esp, CPUMRawGetEFlags(pVCpu),
1482	!!(pGCState->uVMFlags & X86_EFL_IF), pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF));
1483	LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
1484
1485
1486
1487	/*
1488	* Restore the real CPU state and deal with high priority post
1489	* execution FFs before doing anything else.
1490	*/
1491	rc = CPUMRawLeave(pVCpu, NULL, rc);
1492	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1493	if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1494	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1495	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1496
1497	#ifdef VBOX_STRICT
1498	/*
1499	* Assert TSS consistency & rc vs patch code.
1500	*/
1501	if ( !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
1502	&& EMIsRawRing0Enabled(pVM))
1503	SELMR3CheckTSS(pVM);
1504	switch (rc)
1505	{
1506	case VINF_SUCCESS:
1507	case VINF_EM_RAW_INTERRUPT:
1508	case VINF_PATM_PATCH_TRAP_PF:
1509	case VINF_PATM_PATCH_TRAP_GP:
1510	case VINF_PATM_PATCH_INT3:
1511	case VINF_PATM_CHECK_PATCH_PAGE:
1512	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1513	case VINF_EM_RAW_GUEST_TRAP:
1514	case VINF_EM_RESCHEDULE_RAW:
1515	break;
1516
1517	default:
1518	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
1519	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVCpu), rc));
1520	break;
1521	}
1522	/*
1523	* Let's go paranoid!
1524	*/
1525	if ( !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1526	&& PGMMapHasConflicts(pVM))
1527	{
1528	PGMMapCheck(pVM);
1529	AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
1530	return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1531	}
1532	#endif /* VBOX_STRICT */
1533
1534	/*
1535	* Process the returned status code.
1536	*/
1537	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1538	{
1539	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1540	break;
1541	}
1542	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1543	if (rc != VINF_SUCCESS)
1544	{
1545	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1546	if (rc != VINF_SUCCESS)
1547	{
1548	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1549	break;
1550	}
1551	}
1552
1553	/*
1554	* Check and execute forced actions.
1555	*/
1556	#ifdef VBOX_HIGH_RES_TIMERS_HACK
1557	TMTimerPollVoid(pVM, pVCpu);
1558	#endif
1559	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1560	if ( VM_FF_IS_PENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VM_FF_PGM_NO_MEMORY)
1561	\|\| VMCPU_FF_IS_PENDING(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1562	{
1563	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss.Sel & X86_SEL_RPL) != (EMIsRawRing1Enabled(pVM) ? 2 : 1));
1564
1565	STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a);
1566	rc = emR3ForcedActions(pVM, pVCpu, rc);
1567	VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
1568	STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWTotal, a);
1569	if ( rc != VINF_SUCCESS
1570	&& rc != VINF_EM_RESCHEDULE_RAW)
1571	{
1572	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1573	if (rc != VINF_SUCCESS)
1574	{
1575	*pfFFDone = true;
1576	break;
1577	}
1578	}
1579	}
1580	}
1581
1582	/*
1583	* Return to outer loop.
1584	*/
1585	#if defined(LOG_ENABLED) && defined(DEBUG)
1586	RTLogFlush(NULL);
1587	#endif
1588	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTotal, a);
1589	return rc;
1590	}
1591

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source: vbox/trunk/src/VBox/VMM/VMMR3/EMRaw.cpp@ 47682

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