VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/EMRaw.cpp@ 42640

Last change on this file since 42640 was 42407, checked in by vboxsync, 12 years ago

VMM: Futher work on dealing with hidden segment register, esp. when going stale.

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1/* $Id: EMRaw.cpp 42407 2012-07-26 11:41:35Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor / Manager - software virtualization
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_EM
23#include <VBox/vmm/em.h>
24#include <VBox/vmm/vmm.h>
25#include <VBox/vmm/patm.h>
26#include <VBox/vmm/csam.h>
27#include <VBox/vmm/selm.h>
28#include <VBox/vmm/trpm.h>
29#include <VBox/vmm/iem.h>
30#include <VBox/vmm/iom.h>
31#include <VBox/vmm/dbgf.h>
32#include <VBox/vmm/pgm.h>
33#ifdef VBOX_WITH_REM
34# include <VBox/vmm/rem.h>
35#endif
36#include <VBox/vmm/tm.h>
37#include <VBox/vmm/mm.h>
38#include <VBox/vmm/ssm.h>
39#include <VBox/vmm/pdmapi.h>
40#include <VBox/vmm/pdmcritsect.h>
41#include <VBox/vmm/pdmqueue.h>
42#include <VBox/vmm/patm.h>
43#include "EMInternal.h"
44#include "internal/em.h"
45#include <VBox/vmm/vm.h>
46#include <VBox/vmm/cpumdis.h>
47#include <VBox/dis.h>
48#include <VBox/disopcode.h>
49#include <VBox/vmm/dbgf.h>
50#include "VMMTracing.h"
51
52#include <VBox/log.h>
53#include <iprt/asm.h>
54#include <iprt/string.h>
55#include <iprt/stream.h>
56
57
58
59/*******************************************************************************
60* Internal Functions *
61*******************************************************************************/
62static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
63DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
64static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
65static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret);
66static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu);
67static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
68static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu);
69
70#define EMHANDLERC_WITH_PATM
71#include "EMHandleRCTmpl.h"
72
73
74
75#ifdef VBOX_WITH_STATISTICS
76/**
77 * Just a braindead function to keep track of cli addresses.
78 * @param pVM Pointer to the VM.
79 * @param pVMCPU Pointer to the VMCPU.
80 * @param GCPtrInstr The EIP of the cli instruction.
81 */
82static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
83{
84 PCLISTAT pRec;
85
86 pRec = (PCLISTAT)RTAvlGCPtrGet(&pVCpu->em.s.pCliStatTree, GCPtrInstr);
87 if (!pRec)
88 {
89 /* New cli instruction; insert into the tree. */
90 pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
91 Assert(pRec);
92 if (!pRec)
93 return;
94 pRec->Core.Key = GCPtrInstr;
95
96 char szCliStatName[32];
97 RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
98 STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
99
100 bool fRc = RTAvlGCPtrInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
101 Assert(fRc); NOREF(fRc);
102 }
103 STAM_COUNTER_INC(&pRec->Counter);
104 STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
105}
106#endif /* VBOX_WITH_STATISTICS */
107
108
109
110/**
111 * Resumes executing hypervisor after a debug event.
112 *
113 * This is kind of special since our current guest state is
114 * potentially out of sync.
115 *
116 * @returns VBox status code.
117 * @param pVM Pointer to the VM.
118 * @param pVCpu Pointer to the VMCPU.
119 */
120int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu)
121{
122 int rc;
123 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
124 Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
125 Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags));
126
127 /*
128 * Resume execution.
129 */
130 CPUMR3RawEnter(pVCpu, NULL);
131 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_RF);
132 rc = VMMR3ResumeHyper(pVM, pVCpu);
133 Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags, rc));
134 rc = CPUMR3RawLeave(pVCpu, NULL, rc);
135 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
136
137 /*
138 * Deal with the return code.
139 */
140 rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
141 rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
142 rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
143 return rc;
144}
145
146
147/**
148 * Steps rawmode.
149 *
150 * @returns VBox status code.
151 * @param pVM Pointer to the VM.
152 * @param pVCpu Pointer to the VMCPU.
153 */
154int emR3RawStep(PVM pVM, PVMCPU pVCpu)
155{
156 Assert( pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
157 || pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
158 || pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
159 int rc;
160 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
161 bool fGuest = pVCpu->em.s.enmState != EMSTATE_DEBUG_HYPER;
162#ifndef DEBUG_sandervl
163 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
164 fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu)));
165#endif
166 if (fGuest)
167 {
168 /*
169 * Check vital forced actions, but ignore pending interrupts and timers.
170 */
171 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
172 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
173 {
174 rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
175 VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
176 if (rc != VINF_SUCCESS)
177 return rc;
178 }
179
180 /*
181 * Set flags for single stepping.
182 */
183 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) | X86_EFL_TF | X86_EFL_RF);
184 }
185 else
186 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_TF | X86_EFL_RF);
187
188 /*
189 * Single step.
190 * We do not start time or anything, if anything we should just do a few nanoseconds.
191 */
192 CPUMR3RawEnter(pVCpu, NULL);
193 do
194 {
195 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
196 rc = VMMR3ResumeHyper(pVM, pVCpu);
197 else
198 rc = VMMR3RawRunGC(pVM, pVCpu);
199#ifndef DEBUG_sandervl
200 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
201 fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu), rc));
202#endif
203 } while ( rc == VINF_SUCCESS
204 || rc == VINF_EM_RAW_INTERRUPT);
205 rc = CPUMR3RawLeave(pVCpu, NULL, rc);
206 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
207
208 /*
209 * Make sure the trap flag is cleared.
210 * (Too bad if the guest is trying to single step too.)
211 */
212 if (fGuest)
213 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
214 else
215 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) & ~X86_EFL_TF);
216
217 /*
218 * Deal with the return codes.
219 */
220 rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
221 rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
222 rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
223 return rc;
224}
225
226
227#ifdef DEBUG
228
229
230int emR3SingleStepExecRaw(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
231{
232 int rc = VINF_SUCCESS;
233 EMSTATE enmOldState = pVCpu->em.s.enmState;
234 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
235
236 Log(("Single step BEGIN:\n"));
237 for (uint32_t i = 0; i < cIterations; i++)
238 {
239 DBGFR3PrgStep(pVCpu);
240 DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
241 rc = emR3RawStep(pVM, pVCpu);
242 if (rc != VINF_SUCCESS)
243 break;
244 }
245 Log(("Single step END: rc=%Rrc\n", rc));
246 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
247 pVCpu->em.s.enmState = enmOldState;
248 return rc;
249}
250
251#endif /* DEBUG */
252
253
254/**
255 * Executes one (or perhaps a few more) instruction(s).
256 *
257 * @returns VBox status code suitable for EM.
258 *
259 * @param pVM Pointer to the VM.
260 * @param pVCpu Pointer to the VMCPU.
261 * @param rcGC GC return code
262 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
263 * instruction and prefix the log output with this text.
264 */
265#ifdef LOG_ENABLED
266static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
267#else
268static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
269#endif
270{
271 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
272 int rc;
273
274 /*
275 *
276 * The simple solution is to use the recompiler.
277 * The better solution is to disassemble the current instruction and
278 * try handle as many as possible without using REM.
279 *
280 */
281
282#ifdef LOG_ENABLED
283 /*
284 * Disassemble the instruction if requested.
285 */
286 if (pszPrefix)
287 {
288 DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
289 DBGFR3DisasInstrCurrentLog(pVCpu, pszPrefix);
290 }
291#endif /* LOG_ENABLED */
292
293 /*
294 * PATM is making life more interesting.
295 * We cannot hand anything to REM which has an EIP inside patch code. So, we'll
296 * tell PATM there is a trap in this code and have it take the appropriate actions
297 * to allow us execute the code in REM.
298 */
299 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
300 {
301 Log(("emR3ExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
302
303 RTGCPTR pNewEip;
304 rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
305 switch (rc)
306 {
307 /*
308 * It's not very useful to emulate a single instruction and then go back to raw
309 * mode; just execute the whole block until IF is set again.
310 */
311 case VINF_SUCCESS:
312 Log(("emR3ExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
313 pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
314 pCtx->eip = pNewEip;
315 Assert(pCtx->eip);
316
317 if (pCtx->eflags.Bits.u1IF)
318 {
319 /*
320 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
321 */
322 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
323 return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
324 }
325 else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
326 {
327 /* special case: iret, that sets IF, detected a pending irq/event */
328 return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIRET");
329 }
330 return VINF_EM_RESCHEDULE_REM;
331
332 /*
333 * One instruction.
334 */
335 case VINF_PATCH_EMULATE_INSTR:
336 Log(("emR3ExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
337 pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
338 pCtx->eip = pNewEip;
339 return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
340
341 /*
342 * The patch was disabled, hand it to the REM.
343 */
344 case VERR_PATCH_DISABLED:
345 Log(("emR3ExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
346 pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
347 pCtx->eip = pNewEip;
348 if (pCtx->eflags.Bits.u1IF)
349 {
350 /*
351 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
352 */
353 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
354 return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
355 }
356 return VINF_EM_RESCHEDULE_REM;
357
358 /* Force continued patch exection; usually due to write monitored stack. */
359 case VINF_PATCH_CONTINUE:
360 return VINF_SUCCESS;
361
362 default:
363 AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
364 return VERR_IPE_UNEXPECTED_STATUS;
365 }
366 }
367
368 STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
369 Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
370#ifdef VBOX_WITH_REM
371 EMRemLock(pVM);
372 /* Flush the recompiler TLB if the VCPU has changed. */
373 if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
374 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
375 pVM->em.s.idLastRemCpu = pVCpu->idCpu;
376
377 rc = REMR3EmulateInstruction(pVM, pVCpu);
378 EMRemUnlock(pVM);
379#else
380 rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu));
381#endif
382 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a);
383
384 return rc;
385}
386
387
388/**
389 * Executes one (or perhaps a few more) instruction(s).
390 * This is just a wrapper for discarding pszPrefix in non-logging builds.
391 *
392 * @returns VBox status code suitable for EM.
393 * @param pVM Pointer to the VM.
394 * @param pVCpu Pointer to the VMCPU.
395 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
396 * instruction and prefix the log output with this text.
397 * @param rcGC GC return code
398 */
399DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
400{
401#ifdef LOG_ENABLED
402 return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
403#else
404 return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC);
405#endif
406}
407
408/**
409 * Executes one (or perhaps a few more) IO instruction(s).
410 *
411 * @returns VBox status code suitable for EM.
412 * @param pVM Pointer to the VM.
413 * @param pVCpu Pointer to the VMCPU.
414 */
415static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
416{
417 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
418
419 STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
420
421 /** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
422 * as io instructions tend to come in packages of more than one
423 */
424 DISCPUSTATE Cpu;
425 int rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
426 if (RT_SUCCESS(rc))
427 {
428 VBOXSTRICTRC rcStrict = VINF_EM_RAW_EMULATE_INSTR;
429
430 if (!(Cpu.fPrefix & (DISPREFIX_REP | DISPREFIX_REPNE)))
431 {
432 switch (Cpu.pCurInstr->uOpcode)
433 {
434 case OP_IN:
435 {
436 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
437 rcStrict = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
438 break;
439 }
440
441 case OP_OUT:
442 {
443 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
444 rcStrict = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
445 break;
446 }
447 }
448 }
449 else if (Cpu.fPrefix & DISPREFIX_REP)
450 {
451 switch (Cpu.pCurInstr->uOpcode)
452 {
453 case OP_INSB:
454 case OP_INSWD:
455 {
456 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
457 rcStrict = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
458 break;
459 }
460
461 case OP_OUTSB:
462 case OP_OUTSWD:
463 {
464 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
465 rcStrict = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
466 break;
467 }
468 }
469 }
470
471 /*
472 * Handled the I/O return codes.
473 * (The unhandled cases end up with rcStrict == VINF_EM_RAW_EMULATE_INSTR.)
474 */
475 if (IOM_SUCCESS(rcStrict))
476 {
477 pCtx->rip += Cpu.cbInstr;
478 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
479 return VBOXSTRICTRC_TODO(rcStrict);
480 }
481
482 if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
483 {
484 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
485 rcStrict = emR3RawGuestTrap(pVM, pVCpu);
486 return VBOXSTRICTRC_TODO(rcStrict);
487 }
488 AssertMsg(rcStrict != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
489
490 if (RT_FAILURE(rcStrict))
491 {
492 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
493 return VBOXSTRICTRC_TODO(rcStrict);
494 }
495 AssertMsg(rcStrict == VINF_EM_RAW_EMULATE_INSTR || rcStrict == VINF_EM_RESCHEDULE_REM, ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
496 }
497 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
498 return emR3ExecuteInstruction(pVM, pVCpu, "IO: ");
499}
500
501
502/**
503 * Handle a guest context trap.
504 *
505 * @returns VBox status code suitable for EM.
506 * @param pVM Pointer to the VM.
507 * @param pVCpu Pointer to the VMCPU.
508 */
509static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu)
510{
511 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
512
513 /*
514 * Get the trap info.
515 */
516 uint8_t u8TrapNo;
517 TRPMEVENT enmType;
518 RTGCUINT uErrorCode;
519 RTGCUINTPTR uCR2;
520 int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
521 if (RT_FAILURE(rc))
522 {
523 AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
524 return rc;
525 }
526
527
528#if 1 /* Experimental: Review, disable if it causes trouble. */
529 /*
530 * Handle traps in patch code first.
531 *
532 * We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
533 * but several traps isn't handled specially by TRPM in RC and we end up here
534 * instead. One example is #DE.
535 */
536 uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
537 if ( uCpl == 0
538 && PATMIsPatchGCAddr(pVM, pCtx->eip))
539 {
540 LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
541 return emR3PatchTrap(pVM, pVCpu, pCtx, rc);
542 }
543#endif
544
545 /*
546 * If the guest gate is marked unpatched, then we will check again if we can patch it.
547 * (This assumes that we've already tried and failed to dispatch the trap in
548 * RC for the gates that already has been patched. Which is true for most high
549 * volume traps, because these are handled specially, but not for odd ones like #DE.)
550 */
551 if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
552 {
553 CSAMR3CheckGates(pVM, u8TrapNo, 1);
554 Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
555
556 /* If it was successful, then we could go back to raw mode. */
557 if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
558 {
559 /* Must check pending forced actions as our IDT or GDT might be out of sync. */
560 rc = EMR3CheckRawForcedActions(pVM, pVCpu);
561 AssertRCReturn(rc, rc);
562
563 TRPMERRORCODE enmError = uErrorCode != ~0U
564 ? TRPM_TRAP_HAS_ERRORCODE
565 : TRPM_TRAP_NO_ERRORCODE;
566 rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
567 if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
568 {
569 TRPMResetTrap(pVCpu);
570 return VINF_EM_RESCHEDULE_RAW;
571 }
572 AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
573 }
574 }
575
576 /*
577 * Scan kernel code that traps; we might not get another chance.
578 */
579 /** @todo move this up before the dispatching? */
580 if ( (pCtx->ss.Sel & X86_SEL_RPL) <= 1
581 && !pCtx->eflags.Bits.u1VM)
582 {
583 Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
584 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
585 }
586
587 /*
588 * Trap specific handling.
589 */
590 if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
591 {
592 /*
593 * If MONITOR & MWAIT are supported, then interpret them here.
594 */
595 DISCPUSTATE cpu;
596 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
597 if ( RT_SUCCESS(rc)
598 && (cpu.pCurInstr->uOpcode == OP_MONITOR || cpu.pCurInstr->uOpcode == OP_MWAIT))
599 {
600 uint32_t u32Dummy, u32Features, u32ExtFeatures;
601 CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
602 if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
603 {
604 rc = TRPMResetTrap(pVCpu);
605 AssertRC(rc);
606
607 rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR));
608 if (RT_SUCCESS(rc))
609 return rc;
610 return emR3ExecuteInstruction(pVM, pVCpu, "Monitor: ");
611 }
612 }
613 }
614 else if (u8TrapNo == 13) /* (#GP) Privileged exception */
615 {
616 /*
617 * Handle I/O bitmap?
618 */
619 /** @todo We're not supposed to be here with a false guest trap concerning
620 * I/O access. We can easily handle those in RC. */
621 DISCPUSTATE cpu;
622 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
623 if ( RT_SUCCESS(rc)
624 && (cpu.pCurInstr->fOpType & DISOPTYPE_PORTIO))
625 {
626 /*
627 * We should really check the TSS for the IO bitmap, but it's not like this
628 * lazy approach really makes things worse.
629 */
630 rc = TRPMResetTrap(pVCpu);
631 AssertRC(rc);
632 return emR3ExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
633 }
634 }
635
636#ifdef LOG_ENABLED
637 DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
638 DBGFR3DisasInstrCurrentLog(pVCpu, "Guest trap");
639
640 /* Get guest page information. */
641 uint64_t fFlags = 0;
642 RTGCPHYS GCPhys = 0;
643 int rc2 = PGMGstGetPage(pVCpu, uCR2, &fFlags, &GCPhys);
644 Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
645 pCtx->cs.Sel, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0,
646 (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
647 fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
648 fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
649#endif
650
651 /*
652 * #PG has CR2.
653 * (Because of stuff like above we must set CR2 in a delayed fashion.)
654 */
655 if (u8TrapNo == 14 /* #PG */)
656 pCtx->cr2 = uCR2;
657
658 return VINF_EM_RESCHEDULE_REM;
659}
660
661
662/**
663 * Handle a ring switch trap.
664 * Need to do statistics and to install patches. The result is going to REM.
665 *
666 * @returns VBox status code suitable for EM.
667 * @param pVM Pointer to the VM.
668 * @param pVCpu Pointer to the VMCPU.
669 */
670static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu)
671{
672 int rc;
673 DISCPUSTATE Cpu;
674 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
675
676 /*
677 * sysenter, syscall & callgate
678 */
679 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
680 if (RT_SUCCESS(rc))
681 {
682 if (Cpu.pCurInstr->uOpcode == OP_SYSENTER)
683 {
684 if (pCtx->SysEnter.cs != 0)
685 {
686 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
687 CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0);
688 if (RT_SUCCESS(rc))
689 {
690 DBGFR3DisasInstrCurrentLog(pVCpu, "Patched sysenter instruction");
691 return VINF_EM_RESCHEDULE_RAW;
692 }
693 }
694 }
695
696#ifdef VBOX_WITH_STATISTICS
697 switch (Cpu.pCurInstr->uOpcode)
698 {
699 case OP_SYSENTER:
700 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysEnter);
701 break;
702 case OP_SYSEXIT:
703 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysExit);
704 break;
705 case OP_SYSCALL:
706 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysCall);
707 break;
708 case OP_SYSRET:
709 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysRet);
710 break;
711 }
712#endif
713 }
714 else
715 AssertRC(rc);
716
717 /* go to the REM to emulate a single instruction */
718 return emR3ExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
719}
720
721
722/**
723 * Handle a trap (\#PF or \#GP) in patch code
724 *
725 * @returns VBox status code suitable for EM.
726 * @param pVM Pointer to the VM.
727 * @param pVCpu Pointer to the VMCPU.
728 * @param pCtx Pointer to the guest CPU context.
729 * @param gcret GC return code.
730 */
731static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret)
732{
733 uint8_t u8TrapNo;
734 int rc;
735 TRPMEVENT enmType;
736 RTGCUINT uErrorCode;
737 RTGCUINTPTR uCR2;
738
739 Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
740
741 if (gcret == VINF_PATM_PATCH_INT3)
742 {
743 u8TrapNo = 3;
744 uCR2 = 0;
745 uErrorCode = 0;
746 }
747 else if (gcret == VINF_PATM_PATCH_TRAP_GP)
748 {
749 /* No active trap in this case. Kind of ugly. */
750 u8TrapNo = X86_XCPT_GP;
751 uCR2 = 0;
752 uErrorCode = 0;
753 }
754 else
755 {
756 rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
757 if (RT_FAILURE(rc))
758 {
759 AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
760 return rc;
761 }
762 /* Reset the trap as we'll execute the original instruction again. */
763 TRPMResetTrap(pVCpu);
764 }
765
766 /*
767 * Deal with traps inside patch code.
768 * (This code won't run outside GC.)
769 */
770 if (u8TrapNo != 1)
771 {
772#ifdef LOG_ENABLED
773 DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
774 DBGFR3DisasInstrCurrentLog(pVCpu, "Patch code");
775
776 DISCPUSTATE Cpu;
777 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->eip, &Cpu, "Patch code: ");
778 if ( RT_SUCCESS(rc)
779 && Cpu.pCurInstr->uOpcode == OP_IRET)
780 {
781 uint32_t eip, selCS, uEFlags;
782
783 /* Iret crashes are bad as we have already changed the flags on the stack */
784 rc = PGMPhysSimpleReadGCPtr(pVCpu, &eip, pCtx->esp, 4);
785 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &selCS, pCtx->esp+4, 4);
786 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &uEFlags, pCtx->esp+8, 4);
787 if (rc == VINF_SUCCESS)
788 {
789 if ( (uEFlags & X86_EFL_VM)
790 || (selCS & X86_SEL_RPL) == 3)
791 {
792 uint32_t selSS, esp;
793
794 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &esp, pCtx->esp + 12, 4);
795 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &selSS, pCtx->esp + 16, 4);
796
797 if (uEFlags & X86_EFL_VM)
798 {
799 uint32_t selDS, selES, selFS, selGS;
800 rc = PGMPhysSimpleReadGCPtr(pVCpu, &selES, pCtx->esp + 20, 4);
801 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &selDS, pCtx->esp + 24, 4);
802 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &selFS, pCtx->esp + 28, 4);
803 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &selGS, pCtx->esp + 32, 4);
804 if (rc == VINF_SUCCESS)
805 {
806 Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
807 Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
808 }
809 }
810 else
811 Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
812 }
813 else
814 Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
815 }
816 }
817#endif /* LOG_ENABLED */
818 Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
819 pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
820
821 RTGCPTR pNewEip;
822 rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
823 switch (rc)
824 {
825 /*
826 * Execute the faulting instruction.
827 */
828 case VINF_SUCCESS:
829 {
830 /** @todo execute a whole block */
831 Log(("emR3PatchTrap: Executing faulting instruction at new address %RGv\n", pNewEip));
832 if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
833 Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
834
835 pCtx->eip = pNewEip;
836 AssertRelease(pCtx->eip);
837
838 if (pCtx->eflags.Bits.u1IF)
839 {
840 /* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
841 * int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
842 */
843 if ( u8TrapNo == X86_XCPT_GP
844 && PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
845 {
846 /** @todo move to PATMR3HandleTrap */
847 Log(("Possible Windows XP iret fault at %08RX32\n", pCtx->eip));
848 PATMR3RemovePatch(pVM, pCtx->eip);
849 }
850
851 /** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
852 /* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
853
854 return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
855 /* Interrupts are enabled; just go back to the original instruction.
856 return VINF_SUCCESS; */
857 }
858 return VINF_EM_RESCHEDULE_REM;
859 }
860
861 /*
862 * One instruction.
863 */
864 case VINF_PATCH_EMULATE_INSTR:
865 Log(("emR3PatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
866 pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
867 pCtx->eip = pNewEip;
868 AssertRelease(pCtx->eip);
869 return emR3ExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
870
871 /*
872 * The patch was disabled, hand it to the REM.
873 */
874 case VERR_PATCH_DISABLED:
875 if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
876 Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
877 pCtx->eip = pNewEip;
878 AssertRelease(pCtx->eip);
879
880 if (pCtx->eflags.Bits.u1IF)
881 {
882 /*
883 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
884 */
885 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
886 return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
887 }
888 return VINF_EM_RESCHEDULE_REM;
889
890 /* Force continued patch exection; usually due to write monitored stack. */
891 case VINF_PATCH_CONTINUE:
892 return VINF_SUCCESS;
893
894 /*
895 * Anything else is *fatal*.
896 */
897 default:
898 AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
899 return VERR_IPE_UNEXPECTED_STATUS;
900 }
901 }
902 return VINF_SUCCESS;
903}
904
905
906/**
907 * Handle a privileged instruction.
908 *
909 * @returns VBox status code suitable for EM.
910 * @param pVM Pointer to the VM.
911 * @param pVCpu Pointer to the VMCPU.
912 */
913static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu)
914{
915 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
916
917 Assert(!pCtx->eflags.Bits.u1VM);
918
919 if (PATMIsEnabled(pVM))
920 {
921 /*
922 * Check if in patch code.
923 */
924 if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
925 {
926#ifdef LOG_ENABLED
927 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
928#endif
929 AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08x\n", pCtx->eip));
930 return VERR_EM_RAW_PATCH_CONFLICT;
931 }
932 if ( (pCtx->ss.Sel & X86_SEL_RPL) == 0
933 && !pCtx->eflags.Bits.u1VM
934 && !PATMIsPatchGCAddr(pVM, pCtx->eip))
935 {
936 int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
937 CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0);
938 if (RT_SUCCESS(rc))
939 {
940#ifdef LOG_ENABLED
941 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
942#endif
943 DBGFR3DisasInstrCurrentLog(pVCpu, "Patched privileged instruction");
944 return VINF_SUCCESS;
945 }
946 }
947 }
948
949#ifdef LOG_ENABLED
950 if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
951 {
952 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
953 DBGFR3DisasInstrCurrentLog(pVCpu, "Privileged instr: ");
954 }
955#endif
956
957 /*
958 * Instruction statistics and logging.
959 */
960 DISCPUSTATE Cpu;
961 int rc;
962
963 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "PRIV: ");
964 if (RT_SUCCESS(rc))
965 {
966#ifdef VBOX_WITH_STATISTICS
967 PEMSTATS pStats = pVCpu->em.s.CTX_SUFF(pStats);
968 switch (Cpu.pCurInstr->uOpcode)
969 {
970 case OP_INVLPG:
971 STAM_COUNTER_INC(&pStats->StatInvlpg);
972 break;
973 case OP_IRET:
974 STAM_COUNTER_INC(&pStats->StatIret);
975 break;
976 case OP_CLI:
977 STAM_COUNTER_INC(&pStats->StatCli);
978 emR3RecordCli(pVM, pVCpu, pCtx->rip);
979 break;
980 case OP_STI:
981 STAM_COUNTER_INC(&pStats->StatSti);
982 break;
983 case OP_INSB:
984 case OP_INSWD:
985 case OP_IN:
986 case OP_OUTSB:
987 case OP_OUTSWD:
988 case OP_OUT:
989 AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
990 break;
991
992 case OP_MOV_CR:
993 if (Cpu.Param1.fUse & DISUSE_REG_GEN32)
994 {
995 //read
996 Assert(Cpu.Param2.fUse & DISUSE_REG_CR);
997 Assert(Cpu.Param2.Base.idxCtrlReg <= DISCREG_CR4);
998 STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.Param2.Base.idxCtrlReg]);
999 }
1000 else
1001 {
1002 //write
1003 Assert(Cpu.Param1.fUse & DISUSE_REG_CR);
1004 Assert(Cpu.Param1.Base.idxCtrlReg <= DISCREG_CR4);
1005 STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.Param1.Base.idxCtrlReg]);
1006 }
1007 break;
1008
1009 case OP_MOV_DR:
1010 STAM_COUNTER_INC(&pStats->StatMovDRx);
1011 break;
1012 case OP_LLDT:
1013 STAM_COUNTER_INC(&pStats->StatMovLldt);
1014 break;
1015 case OP_LIDT:
1016 STAM_COUNTER_INC(&pStats->StatMovLidt);
1017 break;
1018 case OP_LGDT:
1019 STAM_COUNTER_INC(&pStats->StatMovLgdt);
1020 break;
1021 case OP_SYSENTER:
1022 STAM_COUNTER_INC(&pStats->StatSysEnter);
1023 break;
1024 case OP_SYSEXIT:
1025 STAM_COUNTER_INC(&pStats->StatSysExit);
1026 break;
1027 case OP_SYSCALL:
1028 STAM_COUNTER_INC(&pStats->StatSysCall);
1029 break;
1030 case OP_SYSRET:
1031 STAM_COUNTER_INC(&pStats->StatSysRet);
1032 break;
1033 case OP_HLT:
1034 STAM_COUNTER_INC(&pStats->StatHlt);
1035 break;
1036 default:
1037 STAM_COUNTER_INC(&pStats->StatMisc);
1038 Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->uOpcode));
1039 break;
1040 }
1041#endif /* VBOX_WITH_STATISTICS */
1042 if ( (pCtx->ss.Sel & X86_SEL_RPL) == 0
1043 && !pCtx->eflags.Bits.u1VM
1044 && CPUMGetGuestCodeBits(pVCpu) == 32)
1045 {
1046 STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
1047 switch (Cpu.pCurInstr->uOpcode)
1048 {
1049 case OP_CLI:
1050 pCtx->eflags.u32 &= ~X86_EFL_IF;
1051 Assert(Cpu.cbInstr == 1);
1052 pCtx->rip += Cpu.cbInstr;
1053 STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1054 return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1055
1056 case OP_STI:
1057 pCtx->eflags.u32 |= X86_EFL_IF;
1058 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + Cpu.cbInstr);
1059 Assert(Cpu.cbInstr == 1);
1060 pCtx->rip += Cpu.cbInstr;
1061 STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1062 return VINF_SUCCESS;
1063
1064 case OP_HLT:
1065 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1066 {
1067 PATMTRANSSTATE enmState;
1068 RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1069
1070 if (enmState == PATMTRANS_OVERWRITTEN)
1071 {
1072 rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1073 Assert(rc == VERR_PATCH_DISABLED);
1074 /* Conflict detected, patch disabled */
1075 Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pCtx->eip));
1076
1077 enmState = PATMTRANS_SAFE;
1078 }
1079
1080 /* The translation had better be successful. Otherwise we can't recover. */
1081 AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
1082 if (enmState != PATMTRANS_OVERWRITTEN)
1083 pCtx->eip = pOrgInstrGC;
1084 }
1085 /* no break; we could just return VINF_EM_HALT here */
1086
1087 case OP_MOV_CR:
1088 case OP_MOV_DR:
1089#ifdef LOG_ENABLED
1090 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1091 {
1092 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1093 DBGFR3DisasInstrCurrentLog(pVCpu, "Privileged instr: ");
1094 }
1095#endif
1096
1097 rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR));
1098 if (RT_SUCCESS(rc))
1099 {
1100 STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1101
1102 if ( Cpu.pCurInstr->uOpcode == OP_MOV_CR
1103 && Cpu.Param1.fUse == DISUSE_REG_CR /* write */
1104 )
1105 {
1106 /* Deal with CR0 updates inside patch code that force
1107 * us to go to the recompiler.
1108 */
1109 if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
1110 && (pCtx->cr0 & (X86_CR0_WP|X86_CR0_PG|X86_CR0_PE)) != (X86_CR0_WP|X86_CR0_PG|X86_CR0_PE))
1111 {
1112 PATMTRANSSTATE enmState;
1113 RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
1114
1115 Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
1116 if (enmState == PATMTRANS_OVERWRITTEN)
1117 {
1118 rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1119 Assert(rc == VERR_PATCH_DISABLED);
1120 /* Conflict detected, patch disabled */
1121 Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pCtx->rip));
1122 enmState = PATMTRANS_SAFE;
1123 }
1124 /* The translation had better be successful. Otherwise we can't recover. */
1125 AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
1126 if (enmState != PATMTRANS_OVERWRITTEN)
1127 pCtx->rip = pOrgInstrGC;
1128 }
1129
1130 /* Reschedule is necessary as the execution/paging mode might have changed. */
1131 return VINF_EM_RESCHEDULE;
1132 }
1133 return rc; /* can return VINF_EM_HALT as well. */
1134 }
1135 AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
1136 break; /* fall back to the recompiler */
1137 }
1138 STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1139 }
1140 }
1141
1142 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1143 return emR3PatchTrap(pVM, pVCpu, pCtx, VINF_PATM_PATCH_TRAP_GP);
1144
1145 return emR3ExecuteInstruction(pVM, pVCpu, "PRIV");
1146}
1147
1148
1149/**
1150 * Update the forced rawmode execution modifier.
1151 *
1152 * This function is called when we're returning from the raw-mode loop(s). If we're
1153 * in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1154 * if not in patch code, the flag will be cleared.
1155 *
1156 * We should never interrupt patch code while it's being executed. Cli patches can
1157 * contain big code blocks, but they are always executed with IF=0. Other patches
1158 * replace single instructions and should be atomic.
1159 *
1160 * @returns Updated rc.
1161 *
1162 * @param pVM Pointer to the VM.
1163 * @param pVCpu Pointer to the VMCPU.
1164 * @param pCtx Pointer to the guest CPU context.
1165 * @param rc The result code.
1166 */
1167int emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
1168{
1169 if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1170 {
1171 /* ignore reschedule attempts. */
1172 switch (rc)
1173 {
1174 case VINF_EM_RESCHEDULE:
1175 case VINF_EM_RESCHEDULE_REM:
1176 LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
1177 rc = VINF_SUCCESS;
1178 break;
1179 }
1180 pVCpu->em.s.fForceRAW = true;
1181 }
1182 else
1183 pVCpu->em.s.fForceRAW = false;
1184 return rc;
1185}
1186
1187
1188/**
1189 * Check for pending raw actions
1190 *
1191 * @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1192 * EM statuses.
1193 * @param pVM Pointer to the VM.
1194 * @param pVCpu Pointer to the VMCPU.
1195 */
1196VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
1197{
1198 int rc = emR3RawForcedActions(pVM, pVCpu, pVCpu->em.s.pCtx);
1199 VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1200 return rc;
1201}
1202
1203
1204/**
1205 * Process raw-mode specific forced actions.
1206 *
1207 * This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
1208 *
1209 * @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1210 * EM statuses.
1211 * @param pVM Pointer to the VM.
1212 * @param pVCpu Pointer to the VMCPU.
1213 * @param pCtx Pointer to the guest CPU context.
1214 */
1215static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1216{
1217 /*
1218 * Note that the order is *vitally* important!
1219 * Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
1220 */
1221 VBOXVMM_EM_FF_RAW(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions);
1222
1223 /*
1224 * Sync selector tables.
1225 */
1226 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT))
1227 {
1228 VBOXSTRICTRC rcStrict = SELMR3UpdateFromCPUM(pVM, pVCpu);
1229 if (rcStrict != VINF_SUCCESS)
1230 return VBOXSTRICTRC_TODO(rcStrict);
1231 }
1232
1233 /*
1234 * Sync IDT.
1235 *
1236 * The CSAMR3CheckGates call in TRPMR3SyncIDT may call PGMPrefetchPage
1237 * and PGMShwModifyPage, so we're in for trouble if for instance a
1238 * PGMSyncCR3+pgmR3PoolClearAll is pending.
1239 */
1240 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
1241 {
1242 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1243 && EMIsRawRing0Enabled(pVM)
1244 && CSAMIsEnabled(pVM))
1245 {
1246 int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1247 if (RT_FAILURE(rc))
1248 return rc;
1249 }
1250
1251 int rc = TRPMR3SyncIDT(pVM, pVCpu);
1252 if (RT_FAILURE(rc))
1253 return rc;
1254 }
1255
1256 /*
1257 * Sync TSS.
1258 */
1259 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1260 {
1261 int rc = SELMR3SyncTSS(pVM, pVCpu);
1262 if (RT_FAILURE(rc))
1263 return rc;
1264 }
1265
1266 /*
1267 * Sync page directory.
1268 */
1269 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1270 {
1271 Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1272 int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1273 if (RT_FAILURE(rc))
1274 return rc;
1275
1276 Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));
1277
1278 /* Prefetch pages for EIP and ESP. */
1279 /** @todo This is rather expensive. Should investigate if it really helps at all. */
1280 rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
1281 if (rc == VINF_SUCCESS)
1282 rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
1283 if (rc != VINF_SUCCESS)
1284 {
1285 if (rc != VINF_PGM_SYNC_CR3)
1286 {
1287 AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
1288 return rc;
1289 }
1290 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1291 if (RT_FAILURE(rc))
1292 return rc;
1293 }
1294 /** @todo maybe prefetch the supervisor stack page as well */
1295 Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));
1296 }
1297
1298 /*
1299 * Allocate handy pages (just in case the above actions have consumed some pages).
1300 */
1301 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1302 {
1303 int rc = PGMR3PhysAllocateHandyPages(pVM);
1304 if (RT_FAILURE(rc))
1305 return rc;
1306 }
1307
1308 /*
1309 * Check whether we're out of memory now.
1310 *
1311 * This may stem from some of the above actions or operations that has been executed
1312 * since we ran FFs. The allocate handy pages must for instance always be followed by
1313 * this check.
1314 */
1315 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1316 return VINF_EM_NO_MEMORY;
1317
1318 return VINF_SUCCESS;
1319}
1320
1321
1322/**
1323 * Executes raw code.
1324 *
1325 * This function contains the raw-mode version of the inner
1326 * execution loop (the outer loop being in EMR3ExecuteVM()).
1327 *
1328 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1329 * VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1330 *
1331 * @param pVM Pointer to the VM.
1332 * @param pVCpu Pointer to the VMCPU.
1333 * @param pfFFDone Where to store an indicator telling whether or not
1334 * FFs were done before returning.
1335 */
1336int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1337{
1338 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTotal, a);
1339
1340 int rc = VERR_IPE_UNINITIALIZED_STATUS;
1341 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1342 LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs.Sel, pCtx->eip));
1343 pVCpu->em.s.fForceRAW = false;
1344 *pfFFDone = false;
1345
1346
1347 /*
1348 *
1349 * Spin till we get a forced action or raw mode status code resulting in
1350 * in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
1351 *
1352 */
1353 for (;;)
1354 {
1355 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWEntry, b);
1356
1357 /*
1358 * Check various preconditions.
1359 */
1360#ifdef VBOX_STRICT
1361# ifdef VBOX_WITH_REM
1362 Assert(REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ);
1363# endif
1364 Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss.Sel & X86_SEL_RPL) == 3 || (pCtx->ss.Sel & X86_SEL_RPL) == 0);
1365 AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
1366 || PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
1367 ("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
1368 if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1369 && PGMMapHasConflicts(pVM))
1370 {
1371 PGMMapCheck(pVM);
1372 AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
1373 return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1374 }
1375#endif /* VBOX_STRICT */
1376
1377 /*
1378 * Process high priority pre-execution raw-mode FFs.
1379 */
1380 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1381 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1382 {
1383 rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1384 VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1385 if (rc != VINF_SUCCESS)
1386 break;
1387 }
1388
1389 /*
1390 * If we're going to execute ring-0 code, the guest state needs to
1391 * be modified a bit and some of the state components (IF, SS/CS RPL,
1392 * and perhaps EIP) needs to be stored with PATM.
1393 */
1394 rc = CPUMR3RawEnter(pVCpu, NULL);
1395 if (rc != VINF_SUCCESS)
1396 {
1397 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1398 break;
1399 }
1400
1401 /*
1402 * Scan code before executing it. Don't bother with user mode or V86 code
1403 */
1404 if ( (pCtx->ss.Sel & X86_SEL_RPL) <= 1
1405 && !pCtx->eflags.Bits.u1VM
1406 && !PATMIsPatchGCAddr(pVM, pCtx->eip))
1407 {
1408 STAM_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWEntry, b);
1409 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1410 STAM_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWEntry, b);
1411 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1412 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1413 {
1414 rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1415 VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1416 if (rc != VINF_SUCCESS)
1417 {
1418 rc = CPUMR3RawLeave(pVCpu, NULL, rc);
1419 break;
1420 }
1421 }
1422 }
1423
1424#ifdef LOG_ENABLED
1425 /*
1426 * Log important stuff before entering GC.
1427 */
1428 PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
1429 if (pCtx->eflags.Bits.u1VM)
1430 Log(("RV86: %04x:%08x IF=%d VMFlags=%x\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1431 else if ((pCtx->ss.Sel & X86_SEL_RPL) == 1)
1432 {
1433 bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
1434 Log(("RR0: %08x ESP=%08x IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss.Sel & X86_SEL_RPL), fCSAMScanned));
1435 }
1436 else if ((pCtx->ss.Sel & X86_SEL_RPL) == 3)
1437 Log(("RR3: %08x ESP=%08x IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1438#endif /* LOG_ENABLED */
1439
1440
1441
1442 /*
1443 * Execute the code.
1444 */
1445 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1446 if (RT_LIKELY(EMR3IsExecutionAllowed(pVM, pVCpu)))
1447 {
1448 STAM_PROFILE_START(&pVCpu->em.s.StatRAWExec, c);
1449 VBOXVMM_EM_RAW_RUN_PRE(pVCpu, pCtx);
1450 rc = VMMR3RawRunGC(pVM, pVCpu);
1451 VBOXVMM_EM_RAW_RUN_RET(pVCpu, pCtx, rc);
1452 STAM_PROFILE_STOP(&pVCpu->em.s.StatRAWExec, c);
1453 }
1454 else
1455 {
1456 /* Give up this time slice; virtual time continues */
1457 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1458 RTThreadSleep(5);
1459 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1460 rc = VINF_SUCCESS;
1461 }
1462 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTail, d);
1463
1464 LogFlow(("RR%u-E: %08x ESP=%08x IF=%d VMFlags=%x PIF=%d\n", (pCtx->ss.Sel & X86_SEL_RPL), pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF));
1465 LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
1466
1467
1468
1469 /*
1470 * Restore the real CPU state and deal with high priority post
1471 * execution FFs before doing anything else.
1472 */
1473 rc = CPUMR3RawLeave(pVCpu, NULL, rc);
1474 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1475 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1476 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1477 rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1478
1479#ifdef VBOX_STRICT
1480 /*
1481 * Assert TSS consistency & rc vs patch code.
1482 */
1483 if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
1484 && EMIsRawRing0Enabled(pVM))
1485 SELMR3CheckTSS(pVM);
1486 switch (rc)
1487 {
1488 case VINF_SUCCESS:
1489 case VINF_EM_RAW_INTERRUPT:
1490 case VINF_PATM_PATCH_TRAP_PF:
1491 case VINF_PATM_PATCH_TRAP_GP:
1492 case VINF_PATM_PATCH_INT3:
1493 case VINF_PATM_CHECK_PATCH_PAGE:
1494 case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1495 case VINF_EM_RAW_GUEST_TRAP:
1496 case VINF_EM_RESCHEDULE_RAW:
1497 break;
1498
1499 default:
1500 if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
1501 LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVCpu), rc));
1502 break;
1503 }
1504 /*
1505 * Let's go paranoid!
1506 */
1507 if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1508 && PGMMapHasConflicts(pVM))
1509 {
1510 PGMMapCheck(pVM);
1511 AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
1512 return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1513 }
1514#endif /* VBOX_STRICT */
1515
1516 /*
1517 * Process the returned status code.
1518 */
1519 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1520 {
1521 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1522 break;
1523 }
1524 rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1525 if (rc != VINF_SUCCESS)
1526 {
1527 rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1528 if (rc != VINF_SUCCESS)
1529 {
1530 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1531 break;
1532 }
1533 }
1534
1535 /*
1536 * Check and execute forced actions.
1537 */
1538#ifdef VBOX_HIGH_RES_TIMERS_HACK
1539 TMTimerPollVoid(pVM, pVCpu);
1540#endif
1541 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1542 if ( VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK | VM_FF_PGM_NO_MEMORY)
1543 || VMCPU_FF_ISPENDING(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1544 {
1545 Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss.Sel & X86_SEL_RPL) != 1);
1546
1547 STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a);
1548 rc = emR3ForcedActions(pVM, pVCpu, rc);
1549 VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
1550 STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWTotal, a);
1551 if ( rc != VINF_SUCCESS
1552 && rc != VINF_EM_RESCHEDULE_RAW)
1553 {
1554 rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1555 if (rc != VINF_SUCCESS)
1556 {
1557 *pfFFDone = true;
1558 break;
1559 }
1560 }
1561 }
1562 }
1563
1564 /*
1565 * Return to outer loop.
1566 */
1567#if defined(LOG_ENABLED) && defined(DEBUG)
1568 RTLogFlush(NULL);
1569#endif
1570 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTotal, a);
1571 return rc;
1572}
1573
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