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source: vbox/trunk/src/VBox/VMM/VMMR3/EMR3Nem.cpp@ 93744

Last change on this file since 93744 was 93115, checked in by vboxsync, 3 years ago

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1/* $Id: EMR3Nem.cpp 93115 2022-01-01 11:31:46Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor / Manager - NEM interface.
4 */
5
6/*
7 * Copyright (C) 2006-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_EM
23#define VMCPU_INCL_CPUM_GST_CTX
24#include <VBox/vmm/em.h>
25#include <VBox/vmm/vmm.h>
26#include <VBox/vmm/selm.h>
27#include <VBox/vmm/trpm.h>
28#include <VBox/vmm/iem.h>
29#include <VBox/vmm/iom.h>
30#include <VBox/vmm/nem.h>
31#include <VBox/vmm/dbgf.h>
32#include <VBox/vmm/pgm.h>
33#include <VBox/vmm/tm.h>
34#include <VBox/vmm/mm.h>
35#include <VBox/vmm/ssm.h>
36#include <VBox/vmm/pdmapi.h>
37#include <VBox/vmm/pdmcritsect.h>
38#include <VBox/vmm/pdmqueue.h>
39#include "EMInternal.h"
40#include <VBox/vmm/vm.h>
41#include <VBox/vmm/gim.h>
42#include <VBox/vmm/cpumdis.h>
43#include <VBox/dis.h>
44#include <VBox/disopcode.h>
45#include <VBox/err.h>
46#include <VBox/vmm/dbgf.h>
47#include "VMMTracing.h"
48
49#include <iprt/asm.h>
50
51
52/*********************************************************************************************************************************
53* Internal Functions *
54*********************************************************************************************************************************/
55static int emR3NemHandleRC(PVM pVM, PVMCPU pVCpu, int rc);
56DECLINLINE(int) emR3NemExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
57static int emR3NemExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
58static int emR3NemForcedActions(PVM pVM, PVMCPU pVCpu);
59
60#define EMHANDLERC_WITH_NEM
61#define emR3ExecuteInstruction emR3NemExecuteInstruction
62#define emR3ExecuteIOInstruction emR3NemExecuteIOInstruction
63#include "EMHandleRCTmpl.h"
64
65
66/**
67 * Executes instruction in NEM mode if we can.
68 *
69 * This is somewhat comparable to REMR3EmulateInstruction.
70 *
71 * @returns VBox strict status code.
72 * @retval VINF_EM_DBG_STEPPED on success.
73 * @retval VERR_EM_CANNOT_EXEC_GUEST if we cannot execute guest instructions in
74 * HM right now.
75 *
76 * @param pVM The cross context VM structure.
77 * @param pVCpu The cross context virtual CPU structure for the calling EMT.
78 * @param fFlags Combinations of EM_ONE_INS_FLAGS_XXX.
79 * @thread EMT.
80 */
81VBOXSTRICTRC emR3NemSingleInstruction(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
82{
83 Assert(!(fFlags & ~EM_ONE_INS_FLAGS_MASK));
84
85 if (!NEMR3CanExecuteGuest(pVM, pVCpu))
86 return VINF_EM_RESCHEDULE;
87
88 uint64_t const uOldRip = pVCpu->cpum.GstCtx.rip;
89 for (;;)
90 {
91 /*
92 * Service necessary FFs before going into HM.
93 */
94 if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
95 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
96 {
97 VBOXSTRICTRC rcStrict = emR3NemForcedActions(pVM, pVCpu);
98 if (rcStrict != VINF_SUCCESS)
99 {
100 Log(("emR3NemSingleInstruction: FFs before -> %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
101 return rcStrict;
102 }
103 }
104
105 /*
106 * Go execute it.
107 */
108 bool fOld = NEMR3SetSingleInstruction(pVM, pVCpu, true);
109 VBOXSTRICTRC rcStrict = NEMR3RunGC(pVM, pVCpu);
110 NEMR3SetSingleInstruction(pVM, pVCpu, fOld);
111 LogFlow(("emR3NemSingleInstruction: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
112
113 /*
114 * Handle high priority FFs and informational status codes. We don't do
115 * normal FF processing the caller or the next call can deal with them.
116 */
117 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
118 if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
119 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
120 {
121 rcStrict = emR3HighPriorityPostForcedActions(pVM, pVCpu, rcStrict);
122 LogFlow(("emR3NemSingleInstruction: FFs after -> %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
123 }
124
125 if (rcStrict != VINF_SUCCESS && (rcStrict < VINF_EM_FIRST || rcStrict > VINF_EM_LAST))
126 {
127 rcStrict = emR3NemHandleRC(pVM, pVCpu, VBOXSTRICTRC_TODO(rcStrict));
128 Log(("emR3NemSingleInstruction: emR3NemHandleRC -> %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
129 }
130
131 /*
132 * Done?
133 */
134 CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP);
135 if ( (rcStrict != VINF_SUCCESS && rcStrict != VINF_EM_DBG_STEPPED)
136 || !(fFlags & EM_ONE_INS_FLAGS_RIP_CHANGE)
137 || pVCpu->cpum.GstCtx.rip != uOldRip)
138 {
139 if (rcStrict == VINF_SUCCESS && pVCpu->cpum.GstCtx.rip != uOldRip)
140 rcStrict = VINF_EM_DBG_STEPPED;
141 Log(("emR3NemSingleInstruction: returns %Rrc (rip %llx -> %llx)\n",
142 VBOXSTRICTRC_VAL(rcStrict), uOldRip, pVCpu->cpum.GstCtx.rip));
143 CPUM_IMPORT_EXTRN_RET(pVCpu, ~CPUMCTX_EXTRN_KEEPER_MASK);
144 return rcStrict;
145 }
146 }
147}
148
149
150/**
151 * Executes one (or perhaps a few more) instruction(s).
152 *
153 * @returns VBox status code suitable for EM.
154 *
155 * @param pVM The cross context VM structure.
156 * @param pVCpu The cross context virtual CPU structure.
157 * @param rcRC Return code from RC.
158 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
159 * instruction and prefix the log output with this text.
160 */
161#if defined(LOG_ENABLED) || defined(DOXYGEN_RUNNING)
162static int emR3NemExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcRC, const char *pszPrefix)
163#else
164static int emR3NemExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcRC)
165#endif
166{
167 NOREF(rcRC);
168
169#ifdef LOG_ENABLED
170 /*
171 * Log it.
172 */
173 Log(("EMINS: %04x:%RGv RSP=%RGv\n", pVCpu->cpum.GstCtx.cs.Sel, (RTGCPTR)pVCpu->cpum.GstCtx.rip, (RTGCPTR)pVCpu->cpum.GstCtx.rsp));
174 if (pszPrefix)
175 {
176 DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", pszPrefix);
177 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, pszPrefix);
178 }
179#endif
180
181 /*
182 * Use IEM and fallback on REM if the functionality is missing.
183 * Once IEM gets mature enough, nothing should ever fall back.
184 */
185 STAM_PROFILE_START(&pVCpu->em.s.StatIEMEmu, a);
186
187 VBOXSTRICTRC rcStrict;
188 uint32_t idxContinueExitRec = pVCpu->em.s.idxContinueExitRec;
189 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
190 if (idxContinueExitRec >= RT_ELEMENTS(pVCpu->em.s.aExitRecords))
191 {
192 CPUM_IMPORT_EXTRN_RET(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
193 rcStrict = IEMExecOne(pVCpu);
194 }
195 else
196 {
197 RT_UNTRUSTED_VALIDATED_FENCE();
198 rcStrict = EMHistoryExec(pVCpu, &pVCpu->em.s.aExitRecords[idxContinueExitRec], 0);
199 LogFlow(("emR3NemExecuteInstruction: %Rrc (EMHistoryExec)\n", VBOXSTRICTRC_VAL(rcStrict)));
200 }
201
202 STAM_PROFILE_STOP(&pVCpu->em.s.StatIEMEmu, a);
203
204 NOREF(pVM);
205 return VBOXSTRICTRC_TODO(rcStrict);
206}
207
208
209/**
210 * Executes one (or perhaps a few more) instruction(s).
211 * This is just a wrapper for discarding pszPrefix in non-logging builds.
212 *
213 * @returns VBox status code suitable for EM.
214 * @param pVM The cross context VM structure.
215 * @param pVCpu The cross context virtual CPU structure.
216 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
217 * instruction and prefix the log output with this text.
218 * @param rcGC GC return code
219 */
220DECLINLINE(int) emR3NemExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
221{
222#ifdef LOG_ENABLED
223 return emR3NemExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
224#else
225 RT_NOREF_PV(pszPrefix);
226 return emR3NemExecuteInstructionWorker(pVM, pVCpu, rcGC);
227#endif
228}
229
230/**
231 * Executes one (or perhaps a few more) IO instruction(s).
232 *
233 * @returns VBox status code suitable for EM.
234 * @param pVM The cross context VM structure.
235 * @param pVCpu The cross context virtual CPU structure.
236 */
237static int emR3NemExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
238{
239 RT_NOREF_PV(pVM);
240 STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
241
242 /*
243 * Hand it over to the interpreter.
244 */
245 CPUM_IMPORT_EXTRN_RET(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
246 VBOXSTRICTRC rcStrict;
247 uint32_t idxContinueExitRec = pVCpu->em.s.idxContinueExitRec;
248 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
249 if (idxContinueExitRec >= RT_ELEMENTS(pVCpu->em.s.aExitRecords))
250 {
251 rcStrict = IEMExecOne(pVCpu);
252 LogFlow(("emR3NemExecuteIOInstruction: %Rrc (IEMExecOne)\n", VBOXSTRICTRC_VAL(rcStrict)));
253 STAM_COUNTER_INC(&pVCpu->em.s.StatIoIem);
254 }
255 else
256 {
257 RT_UNTRUSTED_VALIDATED_FENCE();
258 rcStrict = EMHistoryExec(pVCpu, &pVCpu->em.s.aExitRecords[idxContinueExitRec], 0);
259 LogFlow(("emR3NemExecuteIOInstruction: %Rrc (EMHistoryExec)\n", VBOXSTRICTRC_VAL(rcStrict)));
260 STAM_COUNTER_INC(&pVCpu->em.s.StatIoRestarted);
261 }
262
263 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
264 return VBOXSTRICTRC_TODO(rcStrict);
265}
266
267
268/**
269 * Process NEM specific forced actions.
270 *
271 * This function is called when any FFs in VM_FF_HIGH_PRIORITY_PRE_RAW_MASK
272 * or/and VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK are pending.
273 *
274 * @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
275 * EM statuses.
276 * @param pVM The cross context VM structure.
277 * @param pVCpu The cross context virtual CPU structure.
278 */
279static int emR3NemForcedActions(PVM pVM, PVMCPU pVCpu)
280{
281 /*
282 * Sync page directory should not happen in NEM mode.
283 */
284 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
285 {
286 Log(("NEM: TODO: Make VMCPU_FF_PGM_SYNC_CR3 / VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL quiet! (%#RX64)\n", (uint64_t)pVCpu->fLocalForcedActions));
287 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
288 }
289
290 /*
291 * Allocate handy pages (just in case the above actions have consumed some pages).
292 */
293 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
294 {
295 int rc = PGMR3PhysAllocateHandyPages(pVM);
296 if (RT_FAILURE(rc))
297 return rc;
298 }
299
300 /*
301 * Check whether we're out of memory now.
302 *
303 * This may stem from some of the above actions or operations that has been executed
304 * since we ran FFs. The allocate handy pages must for instance always be followed by
305 * this check.
306 */
307 if (VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
308 return VINF_EM_NO_MEMORY;
309
310 return VINF_SUCCESS;
311}
312
313
314/**
315 * Executes hardware accelerated raw code. (Intel VT-x & AMD-V)
316 *
317 * This function contains the raw-mode version of the inner
318 * execution loop (the outer loop being in EMR3ExecuteVM()).
319 *
320 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
321 * VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
322 *
323 * @param pVM The cross context VM structure.
324 * @param pVCpu The cross context virtual CPU structure.
325 * @param pfFFDone Where to store an indicator telling whether or not
326 * FFs were done before returning.
327 */
328VBOXSTRICTRC emR3NemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
329{
330 VBOXSTRICTRC rcStrict = VERR_IPE_UNINITIALIZED_STATUS;
331
332 LogFlow(("emR3NemExecute%d: (cs:eip=%04x:%RGv)\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, (RTGCPTR)pVCpu->cpum.GstCtx.rip));
333 *pfFFDone = false;
334
335 STAM_REL_COUNTER_INC(&pVCpu->em.s.StatNEMExecuteCalled);
336
337 /*
338 * Spin till we get a forced action which returns anything but VINF_SUCCESS.
339 */
340 for (;;)
341 {
342 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatNEMEntry, a);
343
344 /*
345 * Check that we can execute in NEM mode.
346 */
347 if (NEMR3CanExecuteGuest(pVM, pVCpu))
348 { /* likely */ }
349 else
350 {
351 rcStrict = VINF_EM_RESCHEDULE_REM;
352 break;
353 }
354
355 /*
356 * Process high priority pre-execution raw-mode FFs.
357 */
358 if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
359 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
360 {
361 rcStrict = emR3NemForcedActions(pVM, pVCpu);
362 if (rcStrict != VINF_SUCCESS)
363 break;
364 }
365
366#ifdef LOG_ENABLED
367 /*
368 * Log important stuff before entering GC.
369 */
370 if (TRPMHasTrap(pVCpu))
371 Log(("CPU%d: Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", pVCpu->idCpu, TRPMGetTrapNo(pVCpu), pVCpu->cpum.GstCtx.cs.Sel, (RTGCPTR)pVCpu->cpum.GstCtx.rip));
372
373 if (!(pVCpu->cpum.GstCtx.fExtrn & ( CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS
374 | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_EFER)))
375 {
376 uint32_t cpl = CPUMGetGuestCPL(pVCpu);
377 if (pVM->cCpus == 1)
378 {
379 if (pVCpu->cpum.GstCtx.eflags.Bits.u1VM)
380 Log(("NEMV86: %08x IF=%d\n", pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.Bits.u1IF));
381 else if (CPUMIsGuestIn64BitCodeEx(&pVCpu->cpum.GstCtx))
382 Log(("NEMR%d: %04x:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->cpum.GstCtx.cs.Sel, (RTGCPTR)pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rsp, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pVCpu->cpum.GstCtx.eflags.Bits.u2IOPL, (uint32_t)pVCpu->cpum.GstCtx.cr0, (uint32_t)pVCpu->cpum.GstCtx.cr4, (uint32_t)pVCpu->cpum.GstCtx.msrEFER));
383 else
384 Log(("NEMR%d: %04x:%08x ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.esp, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pVCpu->cpum.GstCtx.eflags.Bits.u2IOPL, (uint32_t)pVCpu->cpum.GstCtx.cr0, (uint32_t)pVCpu->cpum.GstCtx.cr4, (uint32_t)pVCpu->cpum.GstCtx.msrEFER));
385 }
386 else
387 {
388 if (pVCpu->cpum.GstCtx.eflags.Bits.u1VM)
389 Log(("NEMV86-CPU%d: %08x IF=%d\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.Bits.u1IF));
390 else if (CPUMIsGuestIn64BitCodeEx(&pVCpu->cpum.GstCtx))
391 Log(("NEMR%d-CPU%d: %04x:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, (RTGCPTR)pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rsp, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pVCpu->cpum.GstCtx.eflags.Bits.u2IOPL, (uint32_t)pVCpu->cpum.GstCtx.cr0, (uint32_t)pVCpu->cpum.GstCtx.cr4, (uint32_t)pVCpu->cpum.GstCtx.msrEFER));
392 else
393 Log(("NEMR%d-CPU%d: %04x:%08x ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.esp, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pVCpu->cpum.GstCtx.eflags.Bits.u2IOPL, (uint32_t)pVCpu->cpum.GstCtx.cr0, (uint32_t)pVCpu->cpum.GstCtx.cr4, (uint32_t)pVCpu->cpum.GstCtx.msrEFER));
394 }
395 }
396 else if (pVM->cCpus == 1)
397 Log(("NEMRx: -> NEMR3RunGC\n"));
398 else
399 Log(("NEMRx-CPU%u: -> NEMR3RunGC\n", pVCpu->idCpu));
400#endif /* LOG_ENABLED */
401
402 /*
403 * Execute the code.
404 */
405 if (RT_LIKELY(emR3IsExecutionAllowed(pVM, pVCpu)))
406 {
407 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatNEMEntry, a);
408 STAM_REL_PROFILE_START(&pVCpu->em.s.StatNEMExec, x);
409 rcStrict = NEMR3RunGC(pVM, pVCpu);
410 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatNEMExec, x);
411 }
412 else
413 {
414 /* Give up this time slice; virtual time continues */
415 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatNEMEntry, a);
416 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
417 RTThreadSleep(5);
418 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
419 rcStrict = VINF_SUCCESS;
420 }
421
422
423 /*
424 * Deal with high priority post execution FFs before doing anything else.
425 */
426 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
427 if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
428 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
429 rcStrict = emR3HighPriorityPostForcedActions(pVM, pVCpu, rcStrict);
430
431 /*
432 * Process the returned status code.
433 */
434 if (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
435 break;
436
437 rcStrict = emR3NemHandleRC(pVM, pVCpu, VBOXSTRICTRC_TODO(rcStrict));
438 if (rcStrict != VINF_SUCCESS)
439 break;
440
441 /*
442 * Check and execute forced actions.
443 */
444#ifdef VBOX_HIGH_RES_TIMERS_HACK
445 TMTimerPollVoid(pVM, pVCpu);
446#endif
447 if ( VM_FF_IS_ANY_SET(pVM, VM_FF_ALL_MASK)
448 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_ALL_MASK))
449 {
450 rcStrict = emR3ForcedActions(pVM, pVCpu, VBOXSTRICTRC_TODO(rcStrict));
451 VBOXVMM_EM_FF_ALL_RET(pVCpu, VBOXSTRICTRC_VAL(rcStrict));
452 if ( rcStrict != VINF_SUCCESS
453 && rcStrict != VINF_EM_RESCHEDULE_HM)
454 {
455 *pfFFDone = true;
456 break;
457 }
458 }
459 }
460
461 /*
462 * Return to outer loop, making sure the fetch all state as we leave.
463 *
464 * Note! Not using CPUM_IMPORT_EXTRN_RET here, to prioritize an rcStrict error
465 * status over import errors.
466 */
467 if (pVCpu->cpum.GstCtx.fExtrn)
468 {
469 int rcImport = NEMImportStateOnDemand(pVCpu, pVCpu->cpum.GstCtx.fExtrn);
470 AssertReturn(RT_SUCCESS(rcImport) || RT_FAILURE_NP(rcStrict), rcImport);
471 }
472#if defined(LOG_ENABLED) && defined(DEBUG)
473 RTLogFlush(NULL);
474#endif
475 return rcStrict;
476}
477
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