EMHwaccm.cpp@ 41783

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1	/* $Id: EMHwaccm.cpp 41783 2012-06-16 19:24:15Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager - hardware virtualization
4	*/
5
6	/*
7	* Copyright (C) 2006-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_EM
22	#include <VBox/vmm/em.h>
23	#include <VBox/vmm/vmm.h>
24	#include <VBox/vmm/csam.h>
25	#include <VBox/vmm/selm.h>
26	#include <VBox/vmm/trpm.h>
27	#include <VBox/vmm/iem.h>
28	#include <VBox/vmm/iom.h>
29	#include <VBox/vmm/dbgf.h>
30	#include <VBox/vmm/pgm.h>
31	#ifdef VBOX_WITH_REM
32	# include <VBox/vmm/rem.h>
33	#endif
34	#include <VBox/vmm/tm.h>
35	#include <VBox/vmm/mm.h>
36	#include <VBox/vmm/ssm.h>
37	#include <VBox/vmm/pdmapi.h>
38	#include <VBox/vmm/pdmcritsect.h>
39	#include <VBox/vmm/pdmqueue.h>
40	#include <VBox/vmm/hwaccm.h>
41	#include "EMInternal.h"
42	#include "internal/em.h"
43	#include <VBox/vmm/vm.h>
44	#include <VBox/vmm/cpumdis.h>
45	#include <VBox/dis.h>
46	#include <VBox/disopcode.h>
47	#include <VBox/vmm/dbgf.h>
48	#include "VMMTracing.h"
49
50	#include <iprt/asm.h>
51
52
53	/*******************************************************************************
54	* Defined Constants And Macros *
55	*******************************************************************************/
56	#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
57	#define EM_NOTIFY_HWACCM
58	#endif
59
60
61	/*******************************************************************************
62	* Internal Functions *
63	*******************************************************************************/
64	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
65	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
66	static int emR3HwaccmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
67
68	#define EMHANDLERC_WITH_HWACCM
69	#include "EMHandleRCTmpl.h"
70
71
72	#if defined(DEBUG) && defined(SOME_UNUSED_FUNCTIONS)
73
74	/**
75	* Steps hardware accelerated mode.
76	*
77	* @returns VBox status code.
78	* @param pVM Pointer to the VM.
79	* @param pVCpu The VMCPU handle.
80	*/
81	static int emR3HwAccStep(PVM pVM, PVMCPU pVCpu)
82	{
83	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
84
85	int rc;
86	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
87	VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS));
88
89	/*
90	* Check vital forced actions, but ignore pending interrupts and timers.
91	*/
92	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
93	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
94	{
95	rc = emR3HwaccmForcedActions(pVM, pVCpu, pCtx);
96	if (rc != VINF_SUCCESS)
97	return rc;
98	}
99	/*
100	* Set flags for single stepping.
101	*/
102	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
103
104	/*
105	* Single step.
106	* We do not start time or anything, if anything we should just do a few nanoseconds.
107	*/
108	do
109	{
110	rc = VMMR3HwAccRunGC(pVM, pVCpu);
111	} while ( rc == VINF_SUCCESS
112	\|\| rc == VINF_EM_RAW_INTERRUPT);
113	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
114
115	/*
116	* Make sure the trap flag is cleared.
117	* (Too bad if the guest is trying to single step too.)
118	*/
119	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
120
121	/*
122	* Deal with the return codes.
123	*/
124	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
125	rc = emR3HwaccmHandleRC(pVM, pVCpu, pCtx, rc);
126	return rc;
127	}
128
129
130	static int emR3SingleStepExecHwAcc(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
131	{
132	int rc = VINF_SUCCESS;
133	EMSTATE enmOldState = pVCpu->em.s.enmState;
134	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
135
136	Log(("Single step BEGIN:\n"));
137	for (uint32_t i = 0; i < cIterations; i++)
138	{
139	DBGFR3PrgStep(pVCpu);
140	DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
141	rc = emR3HwAccStep(pVM, pVCpu);
142	if ( rc != VINF_SUCCESS
143	\|\| !HWACCMR3CanExecuteGuest(pVM, pVCpu->em.s.pCtx))
144	break;
145	}
146	Log(("Single step END: rc=%Rrc\n", rc));
147	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
148	pVCpu->em.s.enmState = enmOldState;
149	return rc == VINF_SUCCESS ? VINF_EM_RESCHEDULE_REM : rc;
150	}
151
152	#endif /* DEBUG */
153
154
155	/**
156	* Executes one (or perhaps a few more) instruction(s).
157	*
158	* @returns VBox status code suitable for EM.
159	*
160	* @param pVM VM handle.
161	* @param pVCpu VMCPU handle
162	* @param rcRC Return code from RC.
163	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
164	* instruction and prefix the log output with this text.
165	*/
166	#ifdef LOG_ENABLED
167	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcRC, const char *pszPrefix)
168	#else
169	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcRC)
170	#endif
171	{
172	#ifdef LOG_ENABLED
173	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
174	#endif
175	int rc;
176	NOREF(rcRC);
177
178	/*
179	*
180	* The simple solution is to use the recompiler.
181	* The better solution is to disassemble the current instruction and
182	* try handle as many as possible without using REM.
183	*
184	*/
185
186	#ifdef LOG_ENABLED
187	/*
188	* Disassemble the instruction if requested.
189	*/
190	if (pszPrefix)
191	{
192	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
193	DBGFR3DisasInstrCurrentLog(pVCpu, pszPrefix);
194	}
195	#endif /* LOG_ENABLED */
196
197	#if 0
198	/* Try our own instruction emulator before falling back to the recompiler. */
199	DISCPUSTATE Cpu;
200	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "GEN EMU");
201	if (RT_SUCCESS(rc))
202	{
203	switch (Cpu.pCurInstr->uOpcode)
204	{
205	/* @todo we can do more now */
206	case OP_MOV:
207	case OP_AND:
208	case OP_OR:
209	case OP_XOR:
210	case OP_POP:
211	case OP_INC:
212	case OP_DEC:
213	case OP_XCHG:
214	STAM_PROFILE_START(&pVCpu->em.s.StatMiscEmu, a);
215	rc = EMInterpretInstructionCpuUpdtPC(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0);
216	if (RT_SUCCESS(rc))
217	{
218	#ifdef EM_NOTIFY_HWACCM
219	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
220	HWACCMR3NotifyEmulated(pVCpu);
221	#endif
222	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
223	return rc;
224	}
225	if (rc != VERR_EM_INTERPRETER)
226	AssertMsgFailedReturn(("rc=%Rrc\n", rc), rc);
227	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
228	break;
229	}
230	}
231	#endif /* 0 */
232	STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
233	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
234	#ifdef VBOX_WITH_REM
235	EMRemLock(pVM);
236	/* Flush the recompiler TLB if the VCPU has changed. */
237	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
238	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
239	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
240
241	rc = REMR3EmulateInstruction(pVM, pVCpu);
242	EMRemUnlock(pVM);
243	#else
244	rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu)); NOREF(pVM);
245	#endif
246	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a);
247
248	#ifdef EM_NOTIFY_HWACCM
249	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
250	HWACCMR3NotifyEmulated(pVCpu);
251	#endif
252	return rc;
253	}
254
255
256	/**
257	* Executes one (or perhaps a few more) instruction(s).
258	* This is just a wrapper for discarding pszPrefix in non-logging builds.
259	*
260	* @returns VBox status code suitable for EM.
261	* @param pVM VM handle.
262	* @param pVCpu VMCPU handle.
263	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
264	* instruction and prefix the log output with this text.
265	* @param rcGC GC return code
266	*/
267	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
268	{
269	#ifdef LOG_ENABLED
270	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
271	#else
272	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC);
273	#endif
274	}
275
276	/**
277	* Executes one (or perhaps a few more) IO instruction(s).
278	*
279	* @returns VBox status code suitable for EM.
280	* @param pVM VM handle.
281	* @param pVCpu VMCPU handle.
282	*/
283	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
284	{
285	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
286
287	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
288
289	/* Try to restart the io instruction that was refused in ring-0. */
290	VBOXSTRICTRC rcStrict = HWACCMR3RestartPendingIOInstr(pVM, pVCpu, pCtx);
291	if (IOM_SUCCESS(rcStrict))
292	{
293	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoRestarted);
294	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
295	return VBOXSTRICTRC_TODO(rcStrict); /* rip already updated. */
296	}
297	AssertMsgReturn(rcStrict == VERR_NOT_FOUND, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)),
298	RT_SUCCESS_NP(rcStrict) ? VERR_IPE_UNEXPECTED_INFO_STATUS : VBOXSTRICTRC_TODO(rcStrict));
299
300	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
301	* as io instructions tend to come in packages of more than one
302	*/
303	DISCPUSTATE Cpu;
304	int rc2 = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
305	if (RT_SUCCESS(rc2))
306	{
307	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
308
309	if (!(Cpu.fPrefix & (DISPREFIX_REP \| DISPREFIX_REPNE)))
310	{
311	switch (Cpu.pCurInstr->uOpcode)
312	{
313	case OP_IN:
314	{
315	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
316	rcStrict = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
317	break;
318	}
319
320	case OP_OUT:
321	{
322	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
323	rcStrict = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
324	break;
325	}
326	}
327	}
328	else if (Cpu.fPrefix & DISPREFIX_REP)
329	{
330	switch (Cpu.pCurInstr->uOpcode)
331	{
332	case OP_INSB:
333	case OP_INSWD:
334	{
335	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
336	rcStrict = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
337	break;
338	}
339
340	case OP_OUTSB:
341	case OP_OUTSWD:
342	{
343	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
344	rcStrict = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
345	break;
346	}
347	}
348	}
349
350	/*
351	* Handled the I/O return codes.
352	* (The unhandled cases end up with rcStrict == VINF_EM_RAW_EMULATE_INSTR.)
353	*/
354	if (IOM_SUCCESS(rcStrict))
355	{
356	pCtx->rip += Cpu.cbInstr;
357	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
358	return VBOXSTRICTRC_TODO(rcStrict);
359	}
360
361	if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
362	{
363	/* The active trap will be dispatched. */
364	Assert(TRPMHasTrap(pVCpu));
365	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
366	return VINF_SUCCESS;
367	}
368	AssertMsg(rcStrict != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
369
370	if (RT_FAILURE(rcStrict))
371	{
372	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
373	return VBOXSTRICTRC_TODO(rcStrict);
374	}
375	AssertMsg(rcStrict == VINF_EM_RAW_EMULATE_INSTR \|\| rcStrict == VINF_EM_RESCHEDULE_REM, ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
376	}
377
378	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
379	return emR3ExecuteInstruction(pVM, pVCpu, "IO: ");
380	}
381
382
383	/**
384	* Process raw-mode specific forced actions.
385	*
386	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
387	*
388	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
389	* EM statuses.
390	* @param pVM Pointer to the VM.
391	* @param pVCpu The VMCPU handle.
392	* @param pCtx The guest CPUM register context.
393	*/
394	static int emR3HwaccmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
395	{
396	/*
397	* Sync page directory.
398	*/
399	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
400	{
401	Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
402	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
403	if (RT_FAILURE(rc))
404	return rc;
405
406	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
407
408	/* Prefetch pages for EIP and ESP. */
409	/** @todo This is rather expensive. Should investigate if it really helps at all. */
410	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
411	if (rc == VINF_SUCCESS)
412	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
413	if (rc != VINF_SUCCESS)
414	{
415	if (rc != VINF_PGM_SYNC_CR3)
416	{
417	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
418	return rc;
419	}
420	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
421	if (RT_FAILURE(rc))
422	return rc;
423	}
424	/** @todo maybe prefetch the supervisor stack page as well */
425	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
426	}
427
428	/*
429	* Allocate handy pages (just in case the above actions have consumed some pages).
430	*/
431	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
432	{
433	int rc = PGMR3PhysAllocateHandyPages(pVM);
434	if (RT_FAILURE(rc))
435	return rc;
436	}
437
438	/*
439	* Check whether we're out of memory now.
440	*
441	* This may stem from some of the above actions or operations that has been executed
442	* since we ran FFs. The allocate handy pages must for instance always be followed by
443	* this check.
444	*/
445	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
446	return VINF_EM_NO_MEMORY;
447
448	return VINF_SUCCESS;
449	}
450
451
452	/**
453	* Executes hardware accelerated raw code. (Intel VT-x & AMD-V)
454	*
455	* This function contains the raw-mode version of the inner
456	* execution loop (the outer loop being in EMR3ExecuteVM()).
457	*
458	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
459	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
460	*
461	* @param pVM VM handle.
462	* @param pVCpu VMCPU handle.
463	* @param pfFFDone Where to store an indicator telling whether or not
464	* FFs were done before returning.
465	*/
466	int emR3HwAccExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
467	{
468	int rc = VERR_IPE_UNINITIALIZED_STATUS;
469	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
470
471	LogFlow(("emR3HwAccExecute%d: (cs:eip=%04x:%RGv)\n", pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip));
472	*pfFFDone = false;
473
474	STAM_COUNTER_INC(&pVCpu->em.s.StatHwAccExecuteEntry);
475
476	#ifdef EM_NOTIFY_HWACCM
477	HWACCMR3NotifyScheduled(pVCpu);
478	#endif
479
480	/*
481	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
482	*/
483	for (;;)
484	{
485	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatHwAccEntry, a);
486
487	/* Check if a forced reschedule is pending. */
488	if (HWACCMR3IsRescheduleRequired(pVM, pCtx))
489	{
490	rc = VINF_EM_RESCHEDULE;
491	break;
492	}
493
494	/*
495	* Process high priority pre-execution raw-mode FFs.
496	*/
497	VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS)); /* not relevant in HWACCM mode; shouldn't be set really. */
498	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
499	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
500	{
501	rc = emR3HwaccmForcedActions(pVM, pVCpu, pCtx);
502	if (rc != VINF_SUCCESS)
503	break;
504	}
505
506	#ifdef LOG_ENABLED
507	/*
508	* Log important stuff before entering GC.
509	*/
510	if (TRPMHasTrap(pVCpu))
511	Log(("CPU%d: Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", pVCpu->idCpu, TRPMGetTrapNo(pVCpu), pCtx->cs, (RTGCPTR)pCtx->rip));
512
513	uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
514
515	if (pVM->cCpus == 1)
516	{
517	if (pCtx->eflags.Bits.u1VM)
518	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
519	else if (CPUMIsGuestIn64BitCodeEx(pCtx))
520	Log(("HWR%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
521	else
522	Log(("HWR%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
523	}
524	else
525	{
526	if (pCtx->eflags.Bits.u1VM)
527	Log(("HWV86-CPU%d: %08X IF=%d\n", pVCpu->idCpu, pCtx->eip, pCtx->eflags.Bits.u1IF));
528	else if (CPUMIsGuestIn64BitCodeEx(pCtx))
529	Log(("HWR%d-CPU%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
530	else
531	Log(("HWR%d-CPU%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
532	}
533	#endif /* LOG_ENABLED */
534
535	/*
536	* Execute the code.
537	*/
538	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatHwAccEntry, a);
539
540	if (RT_LIKELY(EMR3IsExecutionAllowed(pVM, pVCpu)))
541	{
542	STAM_PROFILE_START(&pVCpu->em.s.StatHwAccExec, x);
543	rc = VMMR3HwAccRunGC(pVM, pVCpu);
544	STAM_PROFILE_STOP(&pVCpu->em.s.StatHwAccExec, x);
545	}
546	else
547	{
548	/* Give up this time slice; virtual time continues */
549	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
550	RTThreadSleep(5);
551	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
552	rc = VINF_SUCCESS;
553	}
554
555
556	/*
557	* Deal with high priority post execution FFs before doing anything else.
558	*/
559	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
560	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
561	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
562	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
563
564	/*
565	* Process the returned status code.
566	*/
567	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
568	break;
569
570	rc = emR3HwaccmHandleRC(pVM, pVCpu, pCtx, rc);
571	if (rc != VINF_SUCCESS)
572	break;
573
574	/*
575	* Check and execute forced actions.
576	*/
577	#ifdef VBOX_HIGH_RES_TIMERS_HACK
578	TMTimerPollVoid(pVM, pVCpu);
579	#endif
580	if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK)
581	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_MASK))
582	{
583	rc = emR3ForcedActions(pVM, pVCpu, rc);
584	VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
585	if ( rc != VINF_SUCCESS
586	&& rc != VINF_EM_RESCHEDULE_HWACC)
587	{
588	*pfFFDone = true;
589	break;
590	}
591	}
592	}
593
594	/*
595	* Return to outer loop.
596	*/
597	#if defined(LOG_ENABLED) && defined(DEBUG)
598	RTLogFlush(NULL);
599	#endif
600	return rc;
601	}
602

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source: vbox/trunk/src/VBox/VMM/VMMR3/EMHwaccm.cpp@ 41783

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