EMHwaccm.cpp@ 40274

Last change on this file since 40274 was 40274, checked in by vboxsync, 13 years ago
Introduced VBOX_WITH_REM in Config.kmk and the VMM.
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1	/* $Id: EMHwaccm.cpp 40274 2012-02-28 13:17:35Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager - hardware virtualization
4	*/
5
6	/*
7	* Copyright (C) 2006-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_EM
22	#include <VBox/vmm/em.h>
23	#include <VBox/vmm/vmm.h>
24	#include <VBox/vmm/csam.h>
25	#include <VBox/vmm/selm.h>
26	#include <VBox/vmm/trpm.h>
27	#include <VBox/vmm/iem.h>
28	#include <VBox/vmm/iom.h>
29	#include <VBox/vmm/dbgf.h>
30	#include <VBox/vmm/pgm.h>
31	#ifdef VBOX_WITH_REM
32	# include <VBox/vmm/rem.h>
33	#endif
34	#include <VBox/vmm/tm.h>
35	#include <VBox/vmm/mm.h>
36	#include <VBox/vmm/ssm.h>
37	#include <VBox/vmm/pdmapi.h>
38	#include <VBox/vmm/pdmcritsect.h>
39	#include <VBox/vmm/pdmqueue.h>
40	#include <VBox/vmm/hwaccm.h>
41	#include "EMInternal.h"
42	#include "internal/em.h"
43	#include <VBox/vmm/vm.h>
44	#include <VBox/vmm/cpumdis.h>
45	#include <VBox/dis.h>
46	#include <VBox/disopcode.h>
47	#include <VBox/vmm/dbgf.h>
48
49	#include <iprt/asm.h>
50
51
52	/*******************************************************************************
53	* Defined Constants And Macros *
54	*******************************************************************************/
55	#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
56	#define EM_NOTIFY_HWACCM
57	#endif
58
59
60	/*******************************************************************************
61	* Internal Functions *
62	*******************************************************************************/
63	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
64	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
65	static int emR3HwaccmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
66
67	#define EMHANDLERC_WITH_HWACCM
68	#include "EMHandleRCTmpl.h"
69
70
71	#if defined(DEBUG) && defined(SOME_UNUSED_FUNCTIONS)
72
73	/**
74	* Steps hardware accelerated mode.
75	*
76	* @returns VBox status code.
77	* @param pVM The VM handle.
78	* @param pVCpu The VMCPU handle.
79	*/
80	static int emR3HwAccStep(PVM pVM, PVMCPU pVCpu)
81	{
82	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
83
84	int rc;
85	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
86	VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS));
87
88	/*
89	* Check vital forced actions, but ignore pending interrupts and timers.
90	*/
91	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
92	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
93	{
94	rc = emR3HwaccmForcedActions(pVM, pVCpu, pCtx);
95	if (rc != VINF_SUCCESS)
96	return rc;
97	}
98	/*
99	* Set flags for single stepping.
100	*/
101	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
102
103	/*
104	* Single step.
105	* We do not start time or anything, if anything we should just do a few nanoseconds.
106	*/
107	do
108	{
109	rc = VMMR3HwAccRunGC(pVM, pVCpu);
110	} while ( rc == VINF_SUCCESS
111	\|\| rc == VINF_EM_RAW_INTERRUPT);
112	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
113
114	/*
115	* Make sure the trap flag is cleared.
116	* (Too bad if the guest is trying to single step too.)
117	*/
118	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
119
120	/*
121	* Deal with the return codes.
122	*/
123	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
124	rc = emR3HwaccmHandleRC(pVM, pVCpu, pCtx, rc);
125	return rc;
126	}
127
128
129	static int emR3SingleStepExecHwAcc(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
130	{
131	int rc = VINF_SUCCESS;
132	EMSTATE enmOldState = pVCpu->em.s.enmState;
133	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
134
135	Log(("Single step BEGIN:\n"));
136	for (uint32_t i = 0; i < cIterations; i++)
137	{
138	DBGFR3PrgStep(pVCpu);
139	DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
140	rc = emR3HwAccStep(pVM, pVCpu);
141	if ( rc != VINF_SUCCESS
142	\|\| !HWACCMR3CanExecuteGuest(pVM, pVCpu->em.s.pCtx))
143	break;
144	}
145	Log(("Single step END: rc=%Rrc\n", rc));
146	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
147	pVCpu->em.s.enmState = enmOldState;
148	return rc == VINF_SUCCESS ? VINF_EM_RESCHEDULE_REM : rc;
149	}
150
151	#endif /* DEBUG */
152
153
154	/**
155	* Executes one (or perhaps a few more) instruction(s).
156	*
157	* @returns VBox status code suitable for EM.
158	*
159	* @param pVM VM handle.
160	* @param pVCpu VMCPU handle
161	* @param rcRC Return code from RC.
162	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
163	* instruction and prefix the log output with this text.
164	*/
165	#ifdef LOG_ENABLED
166	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcRC, const char *pszPrefix)
167	#else
168	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcRC)
169	#endif
170	{
171	#ifdef LOG_ENABLED
172	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
173	#endif
174	int rc;
175	NOREF(rcRC);
176
177	/*
178	*
179	* The simple solution is to use the recompiler.
180	* The better solution is to disassemble the current instruction and
181	* try handle as many as possible without using REM.
182	*
183	*/
184
185	#ifdef LOG_ENABLED
186	/*
187	* Disassemble the instruction if requested.
188	*/
189	if (pszPrefix)
190	{
191	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
192	DBGFR3DisasInstrCurrentLog(pVCpu, pszPrefix);
193	}
194	#endif /* LOG_ENABLED */
195
196	#if 0
197	/* Try our own instruction emulator before falling back to the recompiler. */
198	DISCPUSTATE Cpu;
199	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "GEN EMU");
200	if (RT_SUCCESS(rc))
201	{
202	uint32_t size;
203
204	switch (Cpu.pCurInstr->opcode)
205	{
206	/* @todo we can do more now */
207	case OP_MOV:
208	case OP_AND:
209	case OP_OR:
210	case OP_XOR:
211	case OP_POP:
212	case OP_INC:
213	case OP_DEC:
214	case OP_XCHG:
215	STAM_PROFILE_START(&pVCpu->em.s.StatMiscEmu, a);
216	rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
217	if (RT_SUCCESS(rc))
218	{
219	pCtx->rip += Cpu.opsize;
220	#ifdef EM_NOTIFY_HWACCM
221	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
222	HWACCMR3NotifyEmulated(pVCpu);
223	#endif
224	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
225	return rc;
226	}
227	if (rc != VERR_EM_INTERPRETER)
228	AssertMsgFailedReturn(("rc=%Rrc\n", rc), rc);
229	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
230	break;
231	}
232	}
233	#endif /* 0 */
234	STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
235	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
236	#ifdef VBOX_WITH_REM
237	EMRemLock(pVM);
238	/* Flush the recompiler TLB if the VCPU has changed. */
239	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
240	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
241	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
242
243	rc = REMR3EmulateInstruction(pVM, pVCpu);
244	EMRemUnlock(pVM);
245	#else
246	rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu)); NOREF(pVM);
247	#endif
248	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a);
249
250	#ifdef EM_NOTIFY_HWACCM
251	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
252	HWACCMR3NotifyEmulated(pVCpu);
253	#endif
254	return rc;
255	}
256
257
258	/**
259	* Executes one (or perhaps a few more) instruction(s).
260	* This is just a wrapper for discarding pszPrefix in non-logging builds.
261	*
262	* @returns VBox status code suitable for EM.
263	* @param pVM VM handle.
264	* @param pVCpu VMCPU handle.
265	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
266	* instruction and prefix the log output with this text.
267	* @param rcGC GC return code
268	*/
269	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
270	{
271	#ifdef LOG_ENABLED
272	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
273	#else
274	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC);
275	#endif
276	}
277
278	/**
279	* Executes one (or perhaps a few more) IO instruction(s).
280	*
281	* @returns VBox status code suitable for EM.
282	* @param pVM VM handle.
283	* @param pVCpu VMCPU handle.
284	*/
285	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
286	{
287	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
288
289	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
290
291	/* Try to restart the io instruction that was refused in ring-0. */
292	VBOXSTRICTRC rcStrict = HWACCMR3RestartPendingIOInstr(pVM, pVCpu, pCtx);
293	if (IOM_SUCCESS(rcStrict))
294	{
295	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoRestarted);
296	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
297	return VBOXSTRICTRC_TODO(rcStrict); /* rip already updated. */
298	}
299	AssertMsgReturn(rcStrict == VERR_NOT_FOUND, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)),
300	RT_SUCCESS_NP(rcStrict) ? VERR_IPE_UNEXPECTED_INFO_STATUS : VBOXSTRICTRC_TODO(rcStrict));
301
302	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
303	* as io instructions tend to come in packages of more than one
304	*/
305	DISCPUSTATE Cpu;
306	int rc2 = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
307	if (RT_SUCCESS(rc2))
308	{
309	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
310
311	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
312	{
313	switch (Cpu.pCurInstr->opcode)
314	{
315	case OP_IN:
316	{
317	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
318	rcStrict = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
319	break;
320	}
321
322	case OP_OUT:
323	{
324	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
325	rcStrict = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
326	break;
327	}
328	}
329	}
330	else if (Cpu.prefix & PREFIX_REP)
331	{
332	switch (Cpu.pCurInstr->opcode)
333	{
334	case OP_INSB:
335	case OP_INSWD:
336	{
337	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
338	rcStrict = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
339	break;
340	}
341
342	case OP_OUTSB:
343	case OP_OUTSWD:
344	{
345	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
346	rcStrict = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
347	break;
348	}
349	}
350	}
351
352	/*
353	* Handled the I/O return codes.
354	* (The unhandled cases end up with rcStrict == VINF_EM_RAW_EMULATE_INSTR.)
355	*/
356	if (IOM_SUCCESS(rcStrict))
357	{
358	pCtx->rip += Cpu.opsize;
359	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
360	return VBOXSTRICTRC_TODO(rcStrict);
361	}
362
363	if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
364	{
365	/* The active trap will be dispatched. */
366	Assert(TRPMHasTrap(pVCpu));
367	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
368	return VINF_SUCCESS;
369	}
370	AssertMsg(rcStrict != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
371
372	if (RT_FAILURE(rcStrict))
373	{
374	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
375	return VBOXSTRICTRC_TODO(rcStrict);
376	}
377	AssertMsg(rcStrict == VINF_EM_RAW_EMULATE_INSTR \|\| rcStrict == VINF_EM_RESCHEDULE_REM, ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
378	}
379
380	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
381	return emR3ExecuteInstruction(pVM, pVCpu, "IO: ");
382	}
383
384
385	/**
386	* Process raw-mode specific forced actions.
387	*
388	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
389	*
390	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
391	* EM statuses.
392	* @param pVM The VM handle.
393	* @param pVCpu The VMCPU handle.
394	* @param pCtx The guest CPUM register context.
395	*/
396	static int emR3HwaccmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
397	{
398	/*
399	* Sync page directory.
400	*/
401	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
402	{
403	Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
404	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
405	if (RT_FAILURE(rc))
406	return rc;
407
408	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
409
410	/* Prefetch pages for EIP and ESP. */
411	/** @todo This is rather expensive. Should investigate if it really helps at all. */
412	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
413	if (rc == VINF_SUCCESS)
414	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
415	if (rc != VINF_SUCCESS)
416	{
417	if (rc != VINF_PGM_SYNC_CR3)
418	{
419	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
420	return rc;
421	}
422	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
423	if (RT_FAILURE(rc))
424	return rc;
425	}
426	/** @todo maybe prefetch the supervisor stack page as well */
427	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
428	}
429
430	/*
431	* Allocate handy pages (just in case the above actions have consumed some pages).
432	*/
433	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
434	{
435	int rc = PGMR3PhysAllocateHandyPages(pVM);
436	if (RT_FAILURE(rc))
437	return rc;
438	}
439
440	/*
441	* Check whether we're out of memory now.
442	*
443	* This may stem from some of the above actions or operations that has been executed
444	* since we ran FFs. The allocate handy pages must for instance always be followed by
445	* this check.
446	*/
447	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
448	return VINF_EM_NO_MEMORY;
449
450	return VINF_SUCCESS;
451	}
452
453
454	/**
455	* Executes hardware accelerated raw code. (Intel VT-x & AMD-V)
456	*
457	* This function contains the raw-mode version of the inner
458	* execution loop (the outer loop being in EMR3ExecuteVM()).
459	*
460	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
461	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
462	*
463	* @param pVM VM handle.
464	* @param pVCpu VMCPU handle.
465	* @param pfFFDone Where to store an indicator telling whether or not
466	* FFs were done before returning.
467	*/
468	int emR3HwAccExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
469	{
470	int rc = VERR_IPE_UNINITIALIZED_STATUS;
471	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
472
473	LogFlow(("emR3HwAccExecute%d: (cs:eip=%04x:%RGv)\n", pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip));
474	*pfFFDone = false;
475
476	STAM_COUNTER_INC(&pVCpu->em.s.StatHwAccExecuteEntry);
477
478	#ifdef EM_NOTIFY_HWACCM
479	HWACCMR3NotifyScheduled(pVCpu);
480	#endif
481
482	/*
483	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
484	*/
485	for (;;)
486	{
487	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatHwAccEntry, a);
488
489	/* Check if a forced reschedule is pending. */
490	if (HWACCMR3IsRescheduleRequired(pVM, pCtx))
491	{
492	rc = VINF_EM_RESCHEDULE;
493	break;
494	}
495
496	/*
497	* Process high priority pre-execution raw-mode FFs.
498	*/
499	VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS)); /* not relevant in HWACCM mode; shouldn't be set really. */
500	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
501	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
502	{
503	rc = emR3HwaccmForcedActions(pVM, pVCpu, pCtx);
504	if (rc != VINF_SUCCESS)
505	break;
506	}
507
508	#ifdef LOG_ENABLED
509	/*
510	* Log important stuff before entering GC.
511	*/
512	if (TRPMHasTrap(pVCpu))
513	Log(("CPU%d: Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", pVCpu->idCpu, TRPMGetTrapNo(pVCpu), pCtx->cs, (RTGCPTR)pCtx->rip));
514
515	uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
516
517	if (pVM->cCpus == 1)
518	{
519	if (pCtx->eflags.Bits.u1VM)
520	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
521	else if (CPUMIsGuestIn64BitCodeEx(pCtx))
522	Log(("HWR%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
523	else
524	Log(("HWR%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
525	}
526	else
527	{
528	if (pCtx->eflags.Bits.u1VM)
529	Log(("HWV86-CPU%d: %08X IF=%d\n", pVCpu->idCpu, pCtx->eip, pCtx->eflags.Bits.u1IF));
530	else if (CPUMIsGuestIn64BitCodeEx(pCtx))
531	Log(("HWR%d-CPU%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
532	else
533	Log(("HWR%d-CPU%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
534	}
535	#endif /* LOG_ENABLED */
536
537	/*
538	* Execute the code.
539	*/
540	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatHwAccEntry, a);
541
542	if (RT_LIKELY(EMR3IsExecutionAllowed(pVM, pVCpu)))
543	{
544	STAM_PROFILE_START(&pVCpu->em.s.StatHwAccExec, x);
545	rc = VMMR3HwAccRunGC(pVM, pVCpu);
546	STAM_PROFILE_STOP(&pVCpu->em.s.StatHwAccExec, x);
547	}
548	else
549	{
550	/* Give up this time slice; virtual time continues */
551	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
552	RTThreadSleep(5);
553	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
554	rc = VINF_SUCCESS;
555	}
556
557
558	/*
559	* Deal with high priority post execution FFs before doing anything else.
560	*/
561	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
562	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
563	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
564	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
565
566	/*
567	* Process the returned status code.
568	*/
569	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
570	break;
571
572	rc = emR3HwaccmHandleRC(pVM, pVCpu, pCtx, rc);
573	if (rc != VINF_SUCCESS)
574	break;
575
576	/*
577	* Check and execute forced actions.
578	*/
579	#ifdef VBOX_HIGH_RES_TIMERS_HACK
580	TMTimerPollVoid(pVM, pVCpu);
581	#endif
582	if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK)
583	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_MASK))
584	{
585	rc = emR3ForcedActions(pVM, pVCpu, rc);
586	if ( rc != VINF_SUCCESS
587	&& rc != VINF_EM_RESCHEDULE_HWACC)
588	{
589	*pfFFDone = true;
590	break;
591	}
592	}
593	}
594
595	/*
596	* Return to outer loop.
597	*/
598	#if defined(LOG_ENABLED) && defined(DEBUG)
599	RTLogFlush(NULL);
600	#endif
601	return rc;
602	}
603

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source: vbox/trunk/src/VBox/VMM/VMMR3/EMHwaccm.cpp@ 40274

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