EMHwaccm.cpp@ 37423

Last change on this file since 37423 was 35346, checked in by vboxsync, 14 years ago
VMM reorg: Moving the public include files from include/VBox to include/VBox/vmm.
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1	/* $Id: EMHwaccm.cpp 35346 2010-12-27 16:13:13Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager - hardware virtualization
4	*/
5
6	/*
7	* Copyright (C) 2006-2009 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_em EM - The Execution Monitor / Manager
19	*
20	* The Execution Monitor/Manager is responsible for running the VM, scheduling
21	* the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
22	* Interpreted), and keeping the CPU states in sync. The function
23	* EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
24	* modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
25	* emR3RemExecute).
26	*
27	* The interpreted execution is only used to avoid switching between
28	* raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
29	* The interpretation is thus implemented as part of EM.
30	*
31	* @see grp_em
32	*/
33
34	/*******************************************************************************
35	* Header Files *
36	*******************************************************************************/
37	#define LOG_GROUP LOG_GROUP_EM
38	#include <VBox/vmm/em.h>
39	#include <VBox/vmm/vmm.h>
40	#include <VBox/vmm/csam.h>
41	#include <VBox/vmm/selm.h>
42	#include <VBox/vmm/trpm.h>
43	#include <VBox/vmm/iom.h>
44	#include <VBox/vmm/dbgf.h>
45	#include <VBox/vmm/pgm.h>
46	#include <VBox/vmm/rem.h>
47	#include <VBox/vmm/tm.h>
48	#include <VBox/vmm/mm.h>
49	#include <VBox/vmm/ssm.h>
50	#include <VBox/vmm/pdmapi.h>
51	#include <VBox/vmm/pdmcritsect.h>
52	#include <VBox/vmm/pdmqueue.h>
53	#include <VBox/vmm/hwaccm.h>
54	#include "EMInternal.h"
55	#include "internal/em.h"
56	#include <VBox/vmm/vm.h>
57	#include <VBox/vmm/cpumdis.h>
58	#include <VBox/dis.h>
59	#include <VBox/disopcode.h>
60	#include <VBox/vmm/dbgf.h>
61
62	#include <iprt/asm.h>
63
64
65	/*******************************************************************************
66	* Defined Constants And Macros *
67	*******************************************************************************/
68	#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
69	#define EM_NOTIFY_HWACCM
70	#endif
71
72
73	/*******************************************************************************
74	* Internal Functions *
75	*******************************************************************************/
76	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
77	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
78	static int emR3HwaccmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
79
80	#define EMHANDLERC_WITH_HWACCM
81	#include "EMHandleRCTmpl.h"
82
83
84	#ifdef DEBUG
85
86	/**
87	* Steps hardware accelerated mode.
88	*
89	* @returns VBox status code.
90	* @param pVM The VM handle.
91	* @param pVCpu The VMCPU handle.
92	*/
93	static int emR3HwAccStep(PVM pVM, PVMCPU pVCpu)
94	{
95	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
96
97	int rc;
98	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
99	VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS));
100
101	/*
102	* Check vital forced actions, but ignore pending interrupts and timers.
103	*/
104	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
105	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
106	{
107	rc = emR3HwaccmForcedActions(pVM, pVCpu, pCtx);
108	if (rc != VINF_SUCCESS)
109	return rc;
110	}
111	/*
112	* Set flags for single stepping.
113	*/
114	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
115
116	/*
117	* Single step.
118	* We do not start time or anything, if anything we should just do a few nanoseconds.
119	*/
120	do
121	{
122	rc = VMMR3HwAccRunGC(pVM, pVCpu);
123	} while ( rc == VINF_SUCCESS
124	\|\| rc == VINF_EM_RAW_INTERRUPT);
125	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
126
127	/*
128	* Make sure the trap flag is cleared.
129	* (Too bad if the guest is trying to single step too.)
130	*/
131	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
132
133	/*
134	* Deal with the return codes.
135	*/
136	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
137	rc = emR3HwaccmHandleRC(pVM, pVCpu, pCtx, rc);
138	return rc;
139	}
140
141
142	static int emR3SingleStepExecHwAcc(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
143	{
144	int rc = VINF_SUCCESS;
145	EMSTATE enmOldState = pVCpu->em.s.enmState;
146	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
147
148	Log(("Single step BEGIN:\n"));
149	for (uint32_t i = 0; i < cIterations; i++)
150	{
151	DBGFR3PrgStep(pVCpu);
152	DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
153	rc = emR3HwAccStep(pVM, pVCpu);
154	if ( rc != VINF_SUCCESS
155	\|\| !HWACCMR3CanExecuteGuest(pVM, pVCpu->em.s.pCtx))
156	break;
157	}
158	Log(("Single step END: rc=%Rrc\n", rc));
159	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
160	pVCpu->em.s.enmState = enmOldState;
161	return rc == VINF_SUCCESS ? VINF_EM_RESCHEDULE_REM : rc;
162	}
163
164	#endif /* DEBUG */
165
166
167	/**
168	* Executes one (or perhaps a few more) instruction(s).
169	*
170	* @returns VBox status code suitable for EM.
171	*
172	* @param pVM VM handle.
173	* @param pVCpu VMCPU handle
174	* @param rcGC GC return code
175	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
176	* instruction and prefix the log output with this text.
177	*/
178	#ifdef LOG_ENABLED
179	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
180	#else
181	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
182	#endif
183	{
184	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
185	int rc;
186
187	/*
188	*
189	* The simple solution is to use the recompiler.
190	* The better solution is to disassemble the current instruction and
191	* try handle as many as possible without using REM.
192	*
193	*/
194
195	#ifdef LOG_ENABLED
196	/*
197	* Disassemble the instruction if requested.
198	*/
199	if (pszPrefix)
200	{
201	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
202	DBGFR3DisasInstrCurrentLog(pVCpu, pszPrefix);
203	}
204	#endif /* LOG_ENABLED */
205
206	#if 0
207	/* Try our own instruction emulator before falling back to the recompiler. */
208	DISCPUSTATE Cpu;
209	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "GEN EMU");
210	if (RT_SUCCESS(rc))
211	{
212	uint32_t size;
213
214	switch (Cpu.pCurInstr->opcode)
215	{
216	/* @todo we can do more now */
217	case OP_MOV:
218	case OP_AND:
219	case OP_OR:
220	case OP_XOR:
221	case OP_POP:
222	case OP_INC:
223	case OP_DEC:
224	case OP_XCHG:
225	STAM_PROFILE_START(&pVCpu->em.s.StatMiscEmu, a);
226	rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
227	if (RT_SUCCESS(rc))
228	{
229	pCtx->rip += Cpu.opsize;
230	#ifdef EM_NOTIFY_HWACCM
231	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
232	HWACCMR3NotifyEmulated(pVCpu);
233	#endif
234	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
235	return rc;
236	}
237	if (rc != VERR_EM_INTERPRETER)
238	AssertMsgFailedReturn(("rc=%Rrc\n", rc), rc);
239	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
240	break;
241	}
242	}
243	#endif /* 0 */
244	STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
245	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
246	EMRemLock(pVM);
247	/* Flush the recompiler TLB if the VCPU has changed. */
248	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
249	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
250	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
251
252	rc = REMR3EmulateInstruction(pVM, pVCpu);
253	EMRemUnlock(pVM);
254	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a);
255
256	#ifdef EM_NOTIFY_HWACCM
257	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
258	HWACCMR3NotifyEmulated(pVCpu);
259	#endif
260	return rc;
261	}
262
263
264	/**
265	* Executes one (or perhaps a few more) instruction(s).
266	* This is just a wrapper for discarding pszPrefix in non-logging builds.
267	*
268	* @returns VBox status code suitable for EM.
269	* @param pVM VM handle.
270	* @param pVCpu VMCPU handle.
271	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
272	* instruction and prefix the log output with this text.
273	* @param rcGC GC return code
274	*/
275	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
276	{
277	#ifdef LOG_ENABLED
278	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
279	#else
280	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC);
281	#endif
282	}
283
284	/**
285	* Executes one (or perhaps a few more) IO instruction(s).
286	*
287	* @returns VBox status code suitable for EM.
288	* @param pVM VM handle.
289	* @param pVCpu VMCPU handle.
290	*/
291	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
292	{
293	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
294
295	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
296
297	/* Try to restart the io instruction that was refused in ring-0. */
298	VBOXSTRICTRC rcStrict = HWACCMR3RestartPendingIOInstr(pVM, pVCpu, pCtx);
299	if (IOM_SUCCESS(rcStrict))
300	{
301	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoRestarted);
302	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
303	return VBOXSTRICTRC_TODO(rcStrict); /* rip already updated. */
304	}
305	AssertMsgReturn(rcStrict == VERR_NOT_FOUND, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)),
306	RT_SUCCESS_NP(rcStrict) ? VERR_INTERNAL_ERROR_5 : VBOXSTRICTRC_TODO(rcStrict));
307
308	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
309	* as io instructions tend to come in packages of more than one
310	*/
311	DISCPUSTATE Cpu;
312	int rc2 = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
313	if (RT_SUCCESS(rc2))
314	{
315	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
316
317	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
318	{
319	switch (Cpu.pCurInstr->opcode)
320	{
321	case OP_IN:
322	{
323	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
324	rcStrict = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
325	break;
326	}
327
328	case OP_OUT:
329	{
330	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
331	rcStrict = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
332	break;
333	}
334	}
335	}
336	else if (Cpu.prefix & PREFIX_REP)
337	{
338	switch (Cpu.pCurInstr->opcode)
339	{
340	case OP_INSB:
341	case OP_INSWD:
342	{
343	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
344	rcStrict = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
345	break;
346	}
347
348	case OP_OUTSB:
349	case OP_OUTSWD:
350	{
351	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
352	rcStrict = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
353	break;
354	}
355	}
356	}
357
358	/*
359	* Handled the I/O return codes.
360	* (The unhandled cases end up with rcStrict == VINF_EM_RAW_EMULATE_INSTR.)
361	*/
362	if (IOM_SUCCESS(rcStrict))
363	{
364	pCtx->rip += Cpu.opsize;
365	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
366	return VBOXSTRICTRC_TODO(rcStrict);
367	}
368
369	if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
370	{
371	/* The active trap will be dispatched. */
372	Assert(TRPMHasTrap(pVCpu));
373	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
374	return VINF_SUCCESS;
375	}
376	AssertMsg(rcStrict != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
377
378	if (RT_FAILURE(rcStrict))
379	{
380	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
381	return VBOXSTRICTRC_TODO(rcStrict);
382	}
383	AssertMsg(rcStrict == VINF_EM_RAW_EMULATE_INSTR \|\| rcStrict == VINF_EM_RESCHEDULE_REM, ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
384	}
385
386	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
387	return emR3ExecuteInstruction(pVM, pVCpu, "IO: ");
388	}
389
390
391	/**
392	* Process raw-mode specific forced actions.
393	*
394	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
395	*
396	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
397	* EM statuses.
398	* @param pVM The VM handle.
399	* @param pVCpu The VMCPU handle.
400	* @param pCtx The guest CPUM register context.
401	*/
402	static int emR3HwaccmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
403	{
404	/*
405	* Sync page directory.
406	*/
407	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
408	{
409	Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
410	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
411	if (RT_FAILURE(rc))
412	return rc;
413
414	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
415
416	/* Prefetch pages for EIP and ESP. */
417	/** @todo This is rather expensive. Should investigate if it really helps at all. */
418	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
419	if (rc == VINF_SUCCESS)
420	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
421	if (rc != VINF_SUCCESS)
422	{
423	if (rc != VINF_PGM_SYNC_CR3)
424	{
425	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
426	return rc;
427	}
428	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
429	if (RT_FAILURE(rc))
430	return rc;
431	}
432	/** @todo maybe prefetch the supervisor stack page as well */
433	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
434	}
435
436	/*
437	* Allocate handy pages (just in case the above actions have consumed some pages).
438	*/
439	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
440	{
441	int rc = PGMR3PhysAllocateHandyPages(pVM);
442	if (RT_FAILURE(rc))
443	return rc;
444	}
445
446	/*
447	* Check whether we're out of memory now.
448	*
449	* This may stem from some of the above actions or operations that has been executed
450	* since we ran FFs. The allocate handy pages must for instance always be followed by
451	* this check.
452	*/
453	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
454	return VINF_EM_NO_MEMORY;
455
456	return VINF_SUCCESS;
457	}
458
459
460	/**
461	* Executes hardware accelerated raw code. (Intel VT-x & AMD-V)
462	*
463	* This function contains the raw-mode version of the inner
464	* execution loop (the outer loop being in EMR3ExecuteVM()).
465	*
466	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
467	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
468	*
469	* @param pVM VM handle.
470	* @param pVCpu VMCPU handle.
471	* @param pfFFDone Where to store an indicator telling whether or not
472	* FFs were done before returning.
473	*/
474	int emR3HwAccExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
475	{
476	int rc = VERR_INTERNAL_ERROR;
477	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
478
479	LogFlow(("emR3HwAccExecute%d: (cs:eip=%04x:%RGv)\n", pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip));
480	*pfFFDone = false;
481
482	STAM_COUNTER_INC(&pVCpu->em.s.StatHwAccExecuteEntry);
483
484	#ifdef EM_NOTIFY_HWACCM
485	HWACCMR3NotifyScheduled(pVCpu);
486	#endif
487
488	/*
489	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
490	*/
491	for (;;)
492	{
493	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatHwAccEntry, a);
494
495	/* Check if a forced reschedule is pending. */
496	if (HWACCMR3IsRescheduleRequired(pVM, pCtx))
497	{
498	rc = VINF_EM_RESCHEDULE;
499	break;
500	}
501
502	/*
503	* Process high priority pre-execution raw-mode FFs.
504	*/
505	VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS)); /* not relevant in HWACCM mode; shouldn't be set really. */
506	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
507	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
508	{
509	rc = emR3HwaccmForcedActions(pVM, pVCpu, pCtx);
510	if (rc != VINF_SUCCESS)
511	break;
512	}
513
514	#ifdef LOG_ENABLED
515	/*
516	* Log important stuff before entering GC.
517	*/
518	if (TRPMHasTrap(pVCpu))
519	Log(("CPU%d: Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", pVCpu->idCpu, TRPMGetTrapNo(pVCpu), pCtx->cs, (RTGCPTR)pCtx->rip));
520
521	uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
522
523	if (pVM->cCpus == 1)
524	{
525	if (pCtx->eflags.Bits.u1VM)
526	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
527	else if (CPUMIsGuestIn64BitCodeEx(pCtx))
528	Log(("HWR%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
529	else
530	Log(("HWR%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
531	}
532	else
533	{
534	if (pCtx->eflags.Bits.u1VM)
535	Log(("HWV86-CPU%d: %08X IF=%d\n", pVCpu->idCpu, pCtx->eip, pCtx->eflags.Bits.u1IF));
536	else if (CPUMIsGuestIn64BitCodeEx(pCtx))
537	Log(("HWR%d-CPU%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
538	else
539	Log(("HWR%d-CPU%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
540	}
541	#endif /* LOG_ENABLED */
542
543	/*
544	* Execute the code.
545	*/
546	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatHwAccEntry, a);
547
548	if (RT_LIKELY(EMR3IsExecutionAllowed(pVM, pVCpu)))
549	{
550	STAM_PROFILE_START(&pVCpu->em.s.StatHwAccExec, x);
551	rc = VMMR3HwAccRunGC(pVM, pVCpu);
552	STAM_PROFILE_STOP(&pVCpu->em.s.StatHwAccExec, x);
553	}
554	else
555	{
556	/* Give up this time slice; virtual time continues */
557	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
558	RTThreadSleep(5);
559	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
560	rc = VINF_SUCCESS;
561	}
562
563
564	/*
565	* Deal with high priority post execution FFs before doing anything else.
566	*/
567	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
568	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
569	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
570	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
571
572	/*
573	* Process the returned status code.
574	*/
575	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
576	break;
577
578	rc = emR3HwaccmHandleRC(pVM, pVCpu, pCtx, rc);
579	if (rc != VINF_SUCCESS)
580	break;
581
582	/*
583	* Check and execute forced actions.
584	*/
585	#ifdef VBOX_HIGH_RES_TIMERS_HACK
586	TMTimerPollVoid(pVM, pVCpu);
587	#endif
588	if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK)
589	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_MASK))
590	{
591	rc = emR3ForcedActions(pVM, pVCpu, rc);
592	if ( rc != VINF_SUCCESS
593	&& rc != VINF_EM_RESCHEDULE_HWACC)
594	{
595	*pfFFDone = true;
596	break;
597	}
598	}
599	}
600
601	/*
602	* Return to outer loop.
603	*/
604	#if defined(LOG_ENABLED) && defined(DEBUG)
605	RTLogFlush(NULL);
606	#endif
607	return rc;
608	}
609

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source: vbox/trunk/src/VBox/VMM/VMMR3/EMHwaccm.cpp@ 37423

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