VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/EM.cpp@ 53055

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1/* $Id: EM.cpp 51987 2014-07-11 13:04:44Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_em EM - The Execution Monitor / Manager
19 *
20 * The Execution Monitor/Manager is responsible for running the VM, scheduling
21 * the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
22 * Interpreted), and keeping the CPU states in sync. The function
23 * EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
24 * modes has different inner loops (emR3RawExecute, emR3HmExecute, and
25 * emR3RemExecute).
26 *
27 * The interpreted execution is only used to avoid switching between
28 * raw-mode/hm and the recompiler when fielding virtualization traps/faults.
29 * The interpretation is thus implemented as part of EM.
30 *
31 * @see grp_em
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_EM
38#include <VBox/vmm/em.h>
39#include <VBox/vmm/vmm.h>
40#include <VBox/vmm/patm.h>
41#include <VBox/vmm/csam.h>
42#include <VBox/vmm/selm.h>
43#include <VBox/vmm/trpm.h>
44#include <VBox/vmm/iem.h>
45#include <VBox/vmm/iom.h>
46#include <VBox/vmm/dbgf.h>
47#include <VBox/vmm/pgm.h>
48#ifdef VBOX_WITH_REM
49# include <VBox/vmm/rem.h>
50#endif
51#include <VBox/vmm/tm.h>
52#include <VBox/vmm/mm.h>
53#include <VBox/vmm/ssm.h>
54#include <VBox/vmm/pdmapi.h>
55#include <VBox/vmm/pdmcritsect.h>
56#include <VBox/vmm/pdmqueue.h>
57#include <VBox/vmm/hm.h>
58#include <VBox/vmm/patm.h>
59#include "EMInternal.h"
60#include <VBox/vmm/vm.h>
61#include <VBox/vmm/uvm.h>
62#include <VBox/vmm/cpumdis.h>
63#include <VBox/dis.h>
64#include <VBox/disopcode.h>
65#include <VBox/vmm/dbgf.h>
66#include "VMMTracing.h"
67
68#include <iprt/asm.h>
69#include <iprt/string.h>
70#include <iprt/stream.h>
71#include <iprt/thread.h>
72
73
74/*******************************************************************************
75* Defined Constants And Macros *
76*******************************************************************************/
77#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
78#define EM_NOTIFY_HM
79#endif
80
81
82/*******************************************************************************
83* Internal Functions *
84*******************************************************************************/
85static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
86static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
87#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
88static const char *emR3GetStateName(EMSTATE enmState);
89#endif
90static VBOXSTRICTRC emR3Debug(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc);
91static int emR3RemStep(PVM pVM, PVMCPU pVCpu);
92static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
93int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
94
95
96/**
97 * Initializes the EM.
98 *
99 * @returns VBox status code.
100 * @param pVM Pointer to the VM.
101 */
102VMMR3_INT_DECL(int) EMR3Init(PVM pVM)
103{
104 LogFlow(("EMR3Init\n"));
105 /*
106 * Assert alignment and sizes.
107 */
108 AssertCompileMemberAlignment(VM, em.s, 32);
109 AssertCompile(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
110 AssertCompile(sizeof(pVM->aCpus[0].em.s.u.FatalLongJump) <= sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump));
111
112 /*
113 * Init the structure.
114 */
115 pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
116 PCFGMNODE pCfgRoot = CFGMR3GetRoot(pVM);
117 PCFGMNODE pCfgEM = CFGMR3GetChild(pCfgRoot, "EM");
118
119 bool fEnabled;
120 int rc = CFGMR3QueryBoolDef(pCfgRoot, "RawR3Enabled", &fEnabled, true);
121 AssertLogRelRCReturn(rc, rc);
122 pVM->fRecompileUser = !fEnabled;
123
124 rc = CFGMR3QueryBoolDef(pCfgRoot, "RawR0Enabled", &fEnabled, true);
125 AssertLogRelRCReturn(rc, rc);
126 pVM->fRecompileSupervisor = !fEnabled;
127
128#ifdef VBOX_WITH_RAW_RING1
129 rc = CFGMR3QueryBoolDef(pCfgRoot, "RawR1Enabled", &pVM->fRawRing1Enabled, false);
130 AssertLogRelRCReturn(rc, rc);
131#else
132 pVM->fRawRing1Enabled = false; /* Disabled by default. */
133#endif
134
135 rc = CFGMR3QueryBoolDef(pCfgEM, "IemExecutesAll", &pVM->em.s.fIemExecutesAll, false);
136 AssertLogRelRCReturn(rc, rc);
137
138 rc = CFGMR3QueryBoolDef(pCfgEM, "TripleFaultReset", &fEnabled, false);
139 AssertLogRelRCReturn(rc, rc);
140 pVM->em.s.fGuruOnTripleFault = !fEnabled;
141 if (!pVM->em.s.fGuruOnTripleFault && pVM->cCpus > 1)
142 {
143 LogRel(("EM: Overriding /EM/TripleFaultReset, must be false on SMP.\n"));
144 pVM->em.s.fGuruOnTripleFault = true;
145 }
146
147 Log(("EMR3Init: fRecompileUser=%RTbool fRecompileSupervisor=%RTbool fRawRing1Enabled=%RTbool fIemExecutesAll=%RTbool fGuruOnTripleFault=%RTbool\n",
148 pVM->fRecompileUser, pVM->fRecompileSupervisor, pVM->fRawRing1Enabled, pVM->em.s.fIemExecutesAll, pVM->em.s.fGuruOnTripleFault));
149
150#ifdef VBOX_WITH_REM
151 /*
152 * Initialize the REM critical section.
153 */
154 AssertCompileMemberAlignment(EM, CritSectREM, sizeof(uintptr_t));
155 rc = PDMR3CritSectInit(pVM, &pVM->em.s.CritSectREM, RT_SRC_POS, "EM-REM");
156 AssertRCReturn(rc, rc);
157#endif
158
159 /*
160 * Saved state.
161 */
162 rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
163 NULL, NULL, NULL,
164 NULL, emR3Save, NULL,
165 NULL, emR3Load, NULL);
166 if (RT_FAILURE(rc))
167 return rc;
168
169 for (VMCPUID i = 0; i < pVM->cCpus; i++)
170 {
171 PVMCPU pVCpu = &pVM->aCpus[i];
172
173 pVCpu->em.s.enmState = (i == 0) ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
174 pVCpu->em.s.enmPrevState = EMSTATE_NONE;
175 pVCpu->em.s.fForceRAW = false;
176
177 pVCpu->em.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
178#ifdef VBOX_WITH_RAW_MODE
179 if (!HMIsEnabled(pVM))
180 {
181 pVCpu->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
182 AssertMsg(pVCpu->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
183 }
184#endif
185
186 /* Force reset of the time slice. */
187 pVCpu->em.s.u64TimeSliceStart = 0;
188
189# define EM_REG_COUNTER(a, b, c) \
190 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
191 AssertRC(rc);
192
193# define EM_REG_COUNTER_USED(a, b, c) \
194 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, c, b, i); \
195 AssertRC(rc);
196
197# define EM_REG_PROFILE(a, b, c) \
198 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
199 AssertRC(rc);
200
201# define EM_REG_PROFILE_ADV(a, b, c) \
202 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
203 AssertRC(rc);
204
205 /*
206 * Statistics.
207 */
208#ifdef VBOX_WITH_STATISTICS
209 PEMSTATS pStats;
210 rc = MMHyperAlloc(pVM, sizeof(*pStats), 0, MM_TAG_EM, (void **)&pStats);
211 if (RT_FAILURE(rc))
212 return rc;
213
214 pVCpu->em.s.pStatsR3 = pStats;
215 pVCpu->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
216 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
217
218 EM_REG_PROFILE(&pStats->StatRZEmulate, "/EM/CPU%d/RZ/Interpret", "Profiling of EMInterpretInstruction.");
219 EM_REG_PROFILE(&pStats->StatR3Emulate, "/EM/CPU%d/R3/Interpret", "Profiling of EMInterpretInstruction.");
220
221 EM_REG_PROFILE(&pStats->StatRZInterpretSucceeded, "/EM/CPU%d/RZ/Interpret/Success", "The number of times an instruction was successfully interpreted.");
222 EM_REG_PROFILE(&pStats->StatR3InterpretSucceeded, "/EM/CPU%d/R3/Interpret/Success", "The number of times an instruction was successfully interpreted.");
223
224 EM_REG_COUNTER_USED(&pStats->StatRZAnd, "/EM/CPU%d/RZ/Interpret/Success/And", "The number of times AND was successfully interpreted.");
225 EM_REG_COUNTER_USED(&pStats->StatR3And, "/EM/CPU%d/R3/Interpret/Success/And", "The number of times AND was successfully interpreted.");
226 EM_REG_COUNTER_USED(&pStats->StatRZAdd, "/EM/CPU%d/RZ/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
227 EM_REG_COUNTER_USED(&pStats->StatR3Add, "/EM/CPU%d/R3/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
228 EM_REG_COUNTER_USED(&pStats->StatRZAdc, "/EM/CPU%d/RZ/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
229 EM_REG_COUNTER_USED(&pStats->StatR3Adc, "/EM/CPU%d/R3/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
230 EM_REG_COUNTER_USED(&pStats->StatRZSub, "/EM/CPU%d/RZ/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
231 EM_REG_COUNTER_USED(&pStats->StatR3Sub, "/EM/CPU%d/R3/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
232 EM_REG_COUNTER_USED(&pStats->StatRZCpuId, "/EM/CPU%d/RZ/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
233 EM_REG_COUNTER_USED(&pStats->StatR3CpuId, "/EM/CPU%d/R3/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
234 EM_REG_COUNTER_USED(&pStats->StatRZDec, "/EM/CPU%d/RZ/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
235 EM_REG_COUNTER_USED(&pStats->StatR3Dec, "/EM/CPU%d/R3/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
236 EM_REG_COUNTER_USED(&pStats->StatRZHlt, "/EM/CPU%d/RZ/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
237 EM_REG_COUNTER_USED(&pStats->StatR3Hlt, "/EM/CPU%d/R3/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
238 EM_REG_COUNTER_USED(&pStats->StatRZInc, "/EM/CPU%d/RZ/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
239 EM_REG_COUNTER_USED(&pStats->StatR3Inc, "/EM/CPU%d/R3/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
240 EM_REG_COUNTER_USED(&pStats->StatRZInvlPg, "/EM/CPU%d/RZ/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
241 EM_REG_COUNTER_USED(&pStats->StatR3InvlPg, "/EM/CPU%d/R3/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
242 EM_REG_COUNTER_USED(&pStats->StatRZIret, "/EM/CPU%d/RZ/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
243 EM_REG_COUNTER_USED(&pStats->StatR3Iret, "/EM/CPU%d/R3/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
244 EM_REG_COUNTER_USED(&pStats->StatRZLLdt, "/EM/CPU%d/RZ/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
245 EM_REG_COUNTER_USED(&pStats->StatR3LLdt, "/EM/CPU%d/R3/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
246 EM_REG_COUNTER_USED(&pStats->StatRZLIdt, "/EM/CPU%d/RZ/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
247 EM_REG_COUNTER_USED(&pStats->StatR3LIdt, "/EM/CPU%d/R3/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
248 EM_REG_COUNTER_USED(&pStats->StatRZLGdt, "/EM/CPU%d/RZ/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
249 EM_REG_COUNTER_USED(&pStats->StatR3LGdt, "/EM/CPU%d/R3/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
250 EM_REG_COUNTER_USED(&pStats->StatRZMov, "/EM/CPU%d/RZ/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
251 EM_REG_COUNTER_USED(&pStats->StatR3Mov, "/EM/CPU%d/R3/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
252 EM_REG_COUNTER_USED(&pStats->StatRZMovCRx, "/EM/CPU%d/RZ/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
253 EM_REG_COUNTER_USED(&pStats->StatR3MovCRx, "/EM/CPU%d/R3/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
254 EM_REG_COUNTER_USED(&pStats->StatRZMovDRx, "/EM/CPU%d/RZ/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
255 EM_REG_COUNTER_USED(&pStats->StatR3MovDRx, "/EM/CPU%d/R3/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
256 EM_REG_COUNTER_USED(&pStats->StatRZOr, "/EM/CPU%d/RZ/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
257 EM_REG_COUNTER_USED(&pStats->StatR3Or, "/EM/CPU%d/R3/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
258 EM_REG_COUNTER_USED(&pStats->StatRZPop, "/EM/CPU%d/RZ/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
259 EM_REG_COUNTER_USED(&pStats->StatR3Pop, "/EM/CPU%d/R3/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
260 EM_REG_COUNTER_USED(&pStats->StatRZRdtsc, "/EM/CPU%d/RZ/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
261 EM_REG_COUNTER_USED(&pStats->StatR3Rdtsc, "/EM/CPU%d/R3/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
262 EM_REG_COUNTER_USED(&pStats->StatRZRdpmc, "/EM/CPU%d/RZ/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
263 EM_REG_COUNTER_USED(&pStats->StatR3Rdpmc, "/EM/CPU%d/R3/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
264 EM_REG_COUNTER_USED(&pStats->StatRZSti, "/EM/CPU%d/RZ/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
265 EM_REG_COUNTER_USED(&pStats->StatR3Sti, "/EM/CPU%d/R3/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
266 EM_REG_COUNTER_USED(&pStats->StatRZXchg, "/EM/CPU%d/RZ/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
267 EM_REG_COUNTER_USED(&pStats->StatR3Xchg, "/EM/CPU%d/R3/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
268 EM_REG_COUNTER_USED(&pStats->StatRZXor, "/EM/CPU%d/RZ/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
269 EM_REG_COUNTER_USED(&pStats->StatR3Xor, "/EM/CPU%d/R3/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
270 EM_REG_COUNTER_USED(&pStats->StatRZMonitor, "/EM/CPU%d/RZ/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
271 EM_REG_COUNTER_USED(&pStats->StatR3Monitor, "/EM/CPU%d/R3/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
272 EM_REG_COUNTER_USED(&pStats->StatRZMWait, "/EM/CPU%d/RZ/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
273 EM_REG_COUNTER_USED(&pStats->StatR3MWait, "/EM/CPU%d/R3/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
274 EM_REG_COUNTER_USED(&pStats->StatRZBtr, "/EM/CPU%d/RZ/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
275 EM_REG_COUNTER_USED(&pStats->StatR3Btr, "/EM/CPU%d/R3/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
276 EM_REG_COUNTER_USED(&pStats->StatRZBts, "/EM/CPU%d/RZ/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
277 EM_REG_COUNTER_USED(&pStats->StatR3Bts, "/EM/CPU%d/R3/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
278 EM_REG_COUNTER_USED(&pStats->StatRZBtc, "/EM/CPU%d/RZ/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
279 EM_REG_COUNTER_USED(&pStats->StatR3Btc, "/EM/CPU%d/R3/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
280 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
281 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg, "/EM/CPU%d/R3/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
282 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
283 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg8b, "/EM/CPU%d/R3/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
284 EM_REG_COUNTER_USED(&pStats->StatRZXAdd, "/EM/CPU%d/RZ/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
285 EM_REG_COUNTER_USED(&pStats->StatR3XAdd, "/EM/CPU%d/R3/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
286 EM_REG_COUNTER_USED(&pStats->StatR3Rdmsr, "/EM/CPU%d/R3/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
287 EM_REG_COUNTER_USED(&pStats->StatRZRdmsr, "/EM/CPU%d/RZ/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
288 EM_REG_COUNTER_USED(&pStats->StatR3Wrmsr, "/EM/CPU%d/R3/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
289 EM_REG_COUNTER_USED(&pStats->StatRZWrmsr, "/EM/CPU%d/RZ/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
290 EM_REG_COUNTER_USED(&pStats->StatR3StosWD, "/EM/CPU%d/R3/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
291 EM_REG_COUNTER_USED(&pStats->StatRZStosWD, "/EM/CPU%d/RZ/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
292 EM_REG_COUNTER_USED(&pStats->StatRZWbInvd, "/EM/CPU%d/RZ/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
293 EM_REG_COUNTER_USED(&pStats->StatR3WbInvd, "/EM/CPU%d/R3/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
294 EM_REG_COUNTER_USED(&pStats->StatRZLmsw, "/EM/CPU%d/RZ/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
295 EM_REG_COUNTER_USED(&pStats->StatR3Lmsw, "/EM/CPU%d/R3/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
296 EM_REG_COUNTER_USED(&pStats->StatRZSmsw, "/EM/CPU%d/RZ/Interpret/Success/Smsw", "The number of times SMSW was successfully interpreted.");
297 EM_REG_COUNTER_USED(&pStats->StatR3Smsw, "/EM/CPU%d/R3/Interpret/Success/Smsw", "The number of times SMSW was successfully interpreted.");
298
299 EM_REG_COUNTER(&pStats->StatRZInterpretFailed, "/EM/CPU%d/RZ/Interpret/Failed", "The number of times an instruction was not interpreted.");
300 EM_REG_COUNTER(&pStats->StatR3InterpretFailed, "/EM/CPU%d/R3/Interpret/Failed", "The number of times an instruction was not interpreted.");
301
302 EM_REG_COUNTER_USED(&pStats->StatRZFailedAnd, "/EM/CPU%d/RZ/Interpret/Failed/And", "The number of times AND was not interpreted.");
303 EM_REG_COUNTER_USED(&pStats->StatR3FailedAnd, "/EM/CPU%d/R3/Interpret/Failed/And", "The number of times AND was not interpreted.");
304 EM_REG_COUNTER_USED(&pStats->StatRZFailedCpuId, "/EM/CPU%d/RZ/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
305 EM_REG_COUNTER_USED(&pStats->StatR3FailedCpuId, "/EM/CPU%d/R3/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
306 EM_REG_COUNTER_USED(&pStats->StatRZFailedDec, "/EM/CPU%d/RZ/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
307 EM_REG_COUNTER_USED(&pStats->StatR3FailedDec, "/EM/CPU%d/R3/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
308 EM_REG_COUNTER_USED(&pStats->StatRZFailedHlt, "/EM/CPU%d/RZ/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
309 EM_REG_COUNTER_USED(&pStats->StatR3FailedHlt, "/EM/CPU%d/R3/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
310 EM_REG_COUNTER_USED(&pStats->StatRZFailedInc, "/EM/CPU%d/RZ/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
311 EM_REG_COUNTER_USED(&pStats->StatR3FailedInc, "/EM/CPU%d/R3/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
312 EM_REG_COUNTER_USED(&pStats->StatRZFailedInvlPg, "/EM/CPU%d/RZ/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
313 EM_REG_COUNTER_USED(&pStats->StatR3FailedInvlPg, "/EM/CPU%d/R3/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
314 EM_REG_COUNTER_USED(&pStats->StatRZFailedIret, "/EM/CPU%d/RZ/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
315 EM_REG_COUNTER_USED(&pStats->StatR3FailedIret, "/EM/CPU%d/R3/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
316 EM_REG_COUNTER_USED(&pStats->StatRZFailedLLdt, "/EM/CPU%d/RZ/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
317 EM_REG_COUNTER_USED(&pStats->StatR3FailedLLdt, "/EM/CPU%d/R3/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
318 EM_REG_COUNTER_USED(&pStats->StatRZFailedLIdt, "/EM/CPU%d/RZ/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
319 EM_REG_COUNTER_USED(&pStats->StatR3FailedLIdt, "/EM/CPU%d/R3/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
320 EM_REG_COUNTER_USED(&pStats->StatRZFailedLGdt, "/EM/CPU%d/RZ/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
321 EM_REG_COUNTER_USED(&pStats->StatR3FailedLGdt, "/EM/CPU%d/R3/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
322 EM_REG_COUNTER_USED(&pStats->StatRZFailedMov, "/EM/CPU%d/RZ/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
323 EM_REG_COUNTER_USED(&pStats->StatR3FailedMov, "/EM/CPU%d/R3/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
324 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovCRx, "/EM/CPU%d/RZ/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
325 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovCRx, "/EM/CPU%d/R3/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
326 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovDRx, "/EM/CPU%d/RZ/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
327 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovDRx, "/EM/CPU%d/R3/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
328 EM_REG_COUNTER_USED(&pStats->StatRZFailedOr, "/EM/CPU%d/RZ/Interpret/Failed/Or", "The number of times OR was not interpreted.");
329 EM_REG_COUNTER_USED(&pStats->StatR3FailedOr, "/EM/CPU%d/R3/Interpret/Failed/Or", "The number of times OR was not interpreted.");
330 EM_REG_COUNTER_USED(&pStats->StatRZFailedPop, "/EM/CPU%d/RZ/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
331 EM_REG_COUNTER_USED(&pStats->StatR3FailedPop, "/EM/CPU%d/R3/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
332 EM_REG_COUNTER_USED(&pStats->StatRZFailedSti, "/EM/CPU%d/RZ/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
333 EM_REG_COUNTER_USED(&pStats->StatR3FailedSti, "/EM/CPU%d/R3/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
334 EM_REG_COUNTER_USED(&pStats->StatRZFailedXchg, "/EM/CPU%d/RZ/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
335 EM_REG_COUNTER_USED(&pStats->StatR3FailedXchg, "/EM/CPU%d/R3/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
336 EM_REG_COUNTER_USED(&pStats->StatRZFailedXor, "/EM/CPU%d/RZ/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
337 EM_REG_COUNTER_USED(&pStats->StatR3FailedXor, "/EM/CPU%d/R3/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
338 EM_REG_COUNTER_USED(&pStats->StatRZFailedMonitor, "/EM/CPU%d/RZ/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
339 EM_REG_COUNTER_USED(&pStats->StatR3FailedMonitor, "/EM/CPU%d/R3/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
340 EM_REG_COUNTER_USED(&pStats->StatRZFailedMWait, "/EM/CPU%d/RZ/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
341 EM_REG_COUNTER_USED(&pStats->StatR3FailedMWait, "/EM/CPU%d/R3/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
342 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdtsc, "/EM/CPU%d/RZ/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
343 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdtsc, "/EM/CPU%d/R3/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
344 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdpmc, "/EM/CPU%d/RZ/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
345 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdpmc, "/EM/CPU%d/R3/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
346 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdmsr, "/EM/CPU%d/RZ/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
347 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdmsr, "/EM/CPU%d/R3/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
348 EM_REG_COUNTER_USED(&pStats->StatRZFailedWrmsr, "/EM/CPU%d/RZ/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
349 EM_REG_COUNTER_USED(&pStats->StatR3FailedWrmsr, "/EM/CPU%d/R3/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
350 EM_REG_COUNTER_USED(&pStats->StatRZFailedLmsw, "/EM/CPU%d/RZ/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
351 EM_REG_COUNTER_USED(&pStats->StatR3FailedLmsw, "/EM/CPU%d/R3/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
352 EM_REG_COUNTER_USED(&pStats->StatRZFailedSmsw, "/EM/CPU%d/RZ/Interpret/Failed/Smsw", "The number of times SMSW was not interpreted.");
353 EM_REG_COUNTER_USED(&pStats->StatR3FailedSmsw, "/EM/CPU%d/R3/Interpret/Failed/Smsw", "The number of times SMSW was not interpreted.");
354
355 EM_REG_COUNTER_USED(&pStats->StatRZFailedMisc, "/EM/CPU%d/RZ/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
356 EM_REG_COUNTER_USED(&pStats->StatR3FailedMisc, "/EM/CPU%d/R3/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
357 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdd, "/EM/CPU%d/RZ/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
358 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdd, "/EM/CPU%d/R3/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
359 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdc, "/EM/CPU%d/RZ/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
360 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdc, "/EM/CPU%d/R3/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
361 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtr, "/EM/CPU%d/RZ/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
362 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtr, "/EM/CPU%d/R3/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
363 EM_REG_COUNTER_USED(&pStats->StatRZFailedBts, "/EM/CPU%d/RZ/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
364 EM_REG_COUNTER_USED(&pStats->StatR3FailedBts, "/EM/CPU%d/R3/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
365 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtc, "/EM/CPU%d/RZ/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
366 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtc, "/EM/CPU%d/R3/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
367 EM_REG_COUNTER_USED(&pStats->StatRZFailedCli, "/EM/CPU%d/RZ/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
368 EM_REG_COUNTER_USED(&pStats->StatR3FailedCli, "/EM/CPU%d/R3/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
369 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
370 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
371 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
372 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg8b, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
373 EM_REG_COUNTER_USED(&pStats->StatRZFailedXAdd, "/EM/CPU%d/RZ/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
374 EM_REG_COUNTER_USED(&pStats->StatR3FailedXAdd, "/EM/CPU%d/R3/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
375 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovNTPS, "/EM/CPU%d/RZ/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
376 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovNTPS, "/EM/CPU%d/R3/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
377 EM_REG_COUNTER_USED(&pStats->StatRZFailedStosWD, "/EM/CPU%d/RZ/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
378 EM_REG_COUNTER_USED(&pStats->StatR3FailedStosWD, "/EM/CPU%d/R3/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
379 EM_REG_COUNTER_USED(&pStats->StatRZFailedSub, "/EM/CPU%d/RZ/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
380 EM_REG_COUNTER_USED(&pStats->StatR3FailedSub, "/EM/CPU%d/R3/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
381 EM_REG_COUNTER_USED(&pStats->StatRZFailedWbInvd, "/EM/CPU%d/RZ/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
382 EM_REG_COUNTER_USED(&pStats->StatR3FailedWbInvd, "/EM/CPU%d/R3/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
383
384 EM_REG_COUNTER_USED(&pStats->StatRZFailedUserMode, "/EM/CPU%d/RZ/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
385 EM_REG_COUNTER_USED(&pStats->StatR3FailedUserMode, "/EM/CPU%d/R3/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
386 EM_REG_COUNTER_USED(&pStats->StatRZFailedPrefix, "/EM/CPU%d/RZ/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
387 EM_REG_COUNTER_USED(&pStats->StatR3FailedPrefix, "/EM/CPU%d/R3/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
388
389 EM_REG_COUNTER_USED(&pStats->StatIoRestarted, "/EM/CPU%d/R3/PrivInst/IoRestarted", "I/O instructions restarted in ring-3.");
390# ifdef VBOX_WITH_FIRST_IEM_STEP
391 EM_REG_COUNTER_USED(&pStats->StatIoIem, "/EM/CPU%d/R3/PrivInst/IoIem", "I/O instructions end to IEM in ring-3.");
392# else
393 EM_REG_COUNTER_USED(&pStats->StatIn, "/EM/CPU%d/R3/PrivInst/In", "Number of in instructions.");
394 EM_REG_COUNTER_USED(&pStats->StatOut, "/EM/CPU%d/R3/PrivInst/Out", "Number of out instructions.");
395# endif
396 EM_REG_COUNTER_USED(&pStats->StatCli, "/EM/CPU%d/R3/PrivInst/Cli", "Number of cli instructions.");
397 EM_REG_COUNTER_USED(&pStats->StatSti, "/EM/CPU%d/R3/PrivInst/Sti", "Number of sli instructions.");
398 EM_REG_COUNTER_USED(&pStats->StatHlt, "/EM/CPU%d/R3/PrivInst/Hlt", "Number of hlt instructions not handled in GC because of PATM.");
399 EM_REG_COUNTER_USED(&pStats->StatInvlpg, "/EM/CPU%d/R3/PrivInst/Invlpg", "Number of invlpg instructions.");
400 EM_REG_COUNTER_USED(&pStats->StatMisc, "/EM/CPU%d/R3/PrivInst/Misc", "Number of misc. instructions.");
401 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[0], "/EM/CPU%d/R3/PrivInst/Mov CR0, X", "Number of mov CR0 write instructions.");
402 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[1], "/EM/CPU%d/R3/PrivInst/Mov CR1, X", "Number of mov CR1 write instructions.");
403 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[2], "/EM/CPU%d/R3/PrivInst/Mov CR2, X", "Number of mov CR2 write instructions.");
404 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[3], "/EM/CPU%d/R3/PrivInst/Mov CR3, X", "Number of mov CR3 write instructions.");
405 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[4], "/EM/CPU%d/R3/PrivInst/Mov CR4, X", "Number of mov CR4 write instructions.");
406 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[0], "/EM/CPU%d/R3/PrivInst/Mov X, CR0", "Number of mov CR0 read instructions.");
407 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[1], "/EM/CPU%d/R3/PrivInst/Mov X, CR1", "Number of mov CR1 read instructions.");
408 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[2], "/EM/CPU%d/R3/PrivInst/Mov X, CR2", "Number of mov CR2 read instructions.");
409 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[3], "/EM/CPU%d/R3/PrivInst/Mov X, CR3", "Number of mov CR3 read instructions.");
410 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[4], "/EM/CPU%d/R3/PrivInst/Mov X, CR4", "Number of mov CR4 read instructions.");
411 EM_REG_COUNTER_USED(&pStats->StatMovDRx, "/EM/CPU%d/R3/PrivInst/MovDRx", "Number of mov DRx instructions.");
412 EM_REG_COUNTER_USED(&pStats->StatIret, "/EM/CPU%d/R3/PrivInst/Iret", "Number of iret instructions.");
413 EM_REG_COUNTER_USED(&pStats->StatMovLgdt, "/EM/CPU%d/R3/PrivInst/Lgdt", "Number of lgdt instructions.");
414 EM_REG_COUNTER_USED(&pStats->StatMovLidt, "/EM/CPU%d/R3/PrivInst/Lidt", "Number of lidt instructions.");
415 EM_REG_COUNTER_USED(&pStats->StatMovLldt, "/EM/CPU%d/R3/PrivInst/Lldt", "Number of lldt instructions.");
416 EM_REG_COUNTER_USED(&pStats->StatSysEnter, "/EM/CPU%d/R3/PrivInst/Sysenter", "Number of sysenter instructions.");
417 EM_REG_COUNTER_USED(&pStats->StatSysExit, "/EM/CPU%d/R3/PrivInst/Sysexit", "Number of sysexit instructions.");
418 EM_REG_COUNTER_USED(&pStats->StatSysCall, "/EM/CPU%d/R3/PrivInst/Syscall", "Number of syscall instructions.");
419 EM_REG_COUNTER_USED(&pStats->StatSysRet, "/EM/CPU%d/R3/PrivInst/Sysret", "Number of sysret instructions.");
420
421 EM_REG_COUNTER(&pVCpu->em.s.StatTotalClis, "/EM/CPU%d/Cli/Total", "Total number of cli instructions executed.");
422 pVCpu->em.s.pCliStatTree = 0;
423
424 /* these should be considered for release statistics. */
425 EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%d/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction.");
426 EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%d/EM/Emulation/Priv", "Profiling of emR3RawPrivileged.");
427 EM_REG_PROFILE(&pVCpu->em.s.StatHmEntry, "/PROF/CPU%d/EM/HmEnter", "Profiling Hardware Accelerated Mode entry overhead.");
428 EM_REG_PROFILE(&pVCpu->em.s.StatHmExec, "/PROF/CPU%d/EM/HmExec", "Profiling Hardware Accelerated Mode execution.");
429 EM_REG_PROFILE(&pVCpu->em.s.StatIEMEmu, "/PROF/CPU%d/EM/IEMEmuSingle", "Profiling single instruction IEM execution.");
430 EM_REG_PROFILE(&pVCpu->em.s.StatIEMThenREM, "/PROF/CPU%d/EM/IEMThenRem", "Profiling IEM-then-REM instruction execution (by IEM).");
431 EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%d/EM/REMEmuSingle", "Profiling single instruction REM execution.");
432 EM_REG_PROFILE(&pVCpu->em.s.StatREMExec, "/PROF/CPU%d/EM/REMExec", "Profiling REM execution.");
433 EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%d/EM/REMSync", "Profiling REM context syncing.");
434 EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%d/EM/RAWEnter", "Profiling Raw Mode entry overhead.");
435 EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%d/EM/RAWExec", "Profiling Raw Mode execution.");
436 EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%d/EM/RAWTail", "Profiling Raw Mode tail overhead.");
437
438#endif /* VBOX_WITH_STATISTICS */
439
440 EM_REG_COUNTER(&pVCpu->em.s.StatForcedActions, "/PROF/CPU%d/EM/ForcedActions", "Profiling forced action execution.");
441 EM_REG_COUNTER(&pVCpu->em.s.StatHalted, "/PROF/CPU%d/EM/Halted", "Profiling halted state (VMR3WaitHalted).");
442 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatCapped, "/PROF/CPU%d/EM/Capped", "Profiling capped state (sleep).");
443 EM_REG_COUNTER(&pVCpu->em.s.StatREMTotal, "/PROF/CPU%d/EM/REMTotal", "Profiling emR3RemExecute (excluding FFs).");
444 EM_REG_COUNTER(&pVCpu->em.s.StatRAWTotal, "/PROF/CPU%d/EM/RAWTotal", "Profiling emR3RawExecute (excluding FFs).");
445
446 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatTotal, "/PROF/CPU%d/EM/Total", "Profiling EMR3ExecuteVM.");
447 }
448
449 emR3InitDbg(pVM);
450 return VINF_SUCCESS;
451}
452
453
454/**
455 * Applies relocations to data and code managed by this
456 * component. This function will be called at init and
457 * whenever the VMM need to relocate it self inside the GC.
458 *
459 * @param pVM Pointer to the VM.
460 */
461VMMR3_INT_DECL(void) EMR3Relocate(PVM pVM)
462{
463 LogFlow(("EMR3Relocate\n"));
464 for (VMCPUID i = 0; i < pVM->cCpus; i++)
465 {
466 PVMCPU pVCpu = &pVM->aCpus[i];
467 if (pVCpu->em.s.pStatsR3)
468 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVCpu->em.s.pStatsR3);
469 }
470}
471
472
473/**
474 * Reset the EM state for a CPU.
475 *
476 * Called by EMR3Reset and hot plugging.
477 *
478 * @param pVCpu Pointer to the VMCPU.
479 */
480VMMR3_INT_DECL(void) EMR3ResetCpu(PVMCPU pVCpu)
481{
482 pVCpu->em.s.fForceRAW = false;
483
484 /* VMR3Reset may return VINF_EM_RESET or VINF_EM_SUSPEND, so transition
485 out of the HALTED state here so that enmPrevState doesn't end up as
486 HALTED when EMR3Execute returns. */
487 if (pVCpu->em.s.enmState == EMSTATE_HALTED)
488 {
489 Log(("EMR3ResetCpu: Cpu#%u %s -> %s\n", pVCpu->idCpu, emR3GetStateName(pVCpu->em.s.enmState), pVCpu->idCpu == 0 ? "EMSTATE_NONE" : "EMSTATE_WAIT_SIPI"));
490 pVCpu->em.s.enmState = pVCpu->idCpu == 0 ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
491 }
492}
493
494
495/**
496 * Reset notification.
497 *
498 * @param pVM Pointer to the VM.
499 */
500VMMR3_INT_DECL(void) EMR3Reset(PVM pVM)
501{
502 Log(("EMR3Reset: \n"));
503 for (VMCPUID i = 0; i < pVM->cCpus; i++)
504 EMR3ResetCpu(&pVM->aCpus[i]);
505}
506
507
508/**
509 * Terminates the EM.
510 *
511 * Termination means cleaning up and freeing all resources,
512 * the VM it self is at this point powered off or suspended.
513 *
514 * @returns VBox status code.
515 * @param pVM Pointer to the VM.
516 */
517VMMR3_INT_DECL(int) EMR3Term(PVM pVM)
518{
519 AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
520
521#ifdef VBOX_WITH_REM
522 PDMR3CritSectDelete(&pVM->em.s.CritSectREM);
523#endif
524 return VINF_SUCCESS;
525}
526
527
528/**
529 * Execute state save operation.
530 *
531 * @returns VBox status code.
532 * @param pVM Pointer to the VM.
533 * @param pSSM SSM operation handle.
534 */
535static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
536{
537 for (VMCPUID i = 0; i < pVM->cCpus; i++)
538 {
539 PVMCPU pVCpu = &pVM->aCpus[i];
540
541 int rc = SSMR3PutBool(pSSM, pVCpu->em.s.fForceRAW);
542 AssertRCReturn(rc, rc);
543
544 Assert(pVCpu->em.s.enmState == EMSTATE_SUSPENDED);
545 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
546 rc = SSMR3PutU32(pSSM, pVCpu->em.s.enmPrevState);
547 AssertRCReturn(rc, rc);
548
549 /* Save mwait state. */
550 rc = SSMR3PutU32(pSSM, pVCpu->em.s.MWait.fWait);
551 AssertRCReturn(rc, rc);
552 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMWaitRAX);
553 AssertRCReturn(rc, rc);
554 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMWaitRCX);
555 AssertRCReturn(rc, rc);
556 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRAX);
557 AssertRCReturn(rc, rc);
558 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRCX);
559 AssertRCReturn(rc, rc);
560 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRDX);
561 AssertRCReturn(rc, rc);
562 }
563 return VINF_SUCCESS;
564}
565
566
567/**
568 * Execute state load operation.
569 *
570 * @returns VBox status code.
571 * @param pVM Pointer to the VM.
572 * @param pSSM SSM operation handle.
573 * @param uVersion Data layout version.
574 * @param uPass The data pass.
575 */
576static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
577{
578 /*
579 * Validate version.
580 */
581 if ( uVersion > EM_SAVED_STATE_VERSION
582 || uVersion < EM_SAVED_STATE_VERSION_PRE_SMP)
583 {
584 AssertMsgFailed(("emR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, EM_SAVED_STATE_VERSION));
585 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
586 }
587 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
588
589 /*
590 * Load the saved state.
591 */
592 for (VMCPUID i = 0; i < pVM->cCpus; i++)
593 {
594 PVMCPU pVCpu = &pVM->aCpus[i];
595
596 int rc = SSMR3GetBool(pSSM, &pVCpu->em.s.fForceRAW);
597 if (RT_FAILURE(rc))
598 pVCpu->em.s.fForceRAW = false;
599 AssertRCReturn(rc, rc);
600
601 if (uVersion > EM_SAVED_STATE_VERSION_PRE_SMP)
602 {
603 AssertCompile(sizeof(pVCpu->em.s.enmPrevState) == sizeof(uint32_t));
604 rc = SSMR3GetU32(pSSM, (uint32_t *)&pVCpu->em.s.enmPrevState);
605 AssertRCReturn(rc, rc);
606 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
607
608 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
609 }
610 if (uVersion > EM_SAVED_STATE_VERSION_PRE_MWAIT)
611 {
612 /* Load mwait state. */
613 rc = SSMR3GetU32(pSSM, &pVCpu->em.s.MWait.fWait);
614 AssertRCReturn(rc, rc);
615 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMWaitRAX);
616 AssertRCReturn(rc, rc);
617 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMWaitRCX);
618 AssertRCReturn(rc, rc);
619 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRAX);
620 AssertRCReturn(rc, rc);
621 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRCX);
622 AssertRCReturn(rc, rc);
623 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRDX);
624 AssertRCReturn(rc, rc);
625 }
626
627 Assert(!pVCpu->em.s.pCliStatTree);
628 }
629 return VINF_SUCCESS;
630}
631
632
633/**
634 * Argument packet for emR3SetExecutionPolicy.
635 */
636struct EMR3SETEXECPOLICYARGS
637{
638 EMEXECPOLICY enmPolicy;
639 bool fEnforce;
640};
641
642
643/**
644 * @callback_method_impl{FNVMMEMTRENDEZVOUS, Rendezvous callback for EMR3SetExecutionPolicy.}
645 */
646static DECLCALLBACK(VBOXSTRICTRC) emR3SetExecutionPolicy(PVM pVM, PVMCPU pVCpu, void *pvUser)
647{
648 /*
649 * Only the first CPU changes the variables.
650 */
651 if (pVCpu->idCpu == 0)
652 {
653 struct EMR3SETEXECPOLICYARGS *pArgs = (struct EMR3SETEXECPOLICYARGS *)pvUser;
654 switch (pArgs->enmPolicy)
655 {
656 case EMEXECPOLICY_RECOMPILE_RING0:
657 pVM->fRecompileSupervisor = pArgs->fEnforce;
658 break;
659 case EMEXECPOLICY_RECOMPILE_RING3:
660 pVM->fRecompileUser = pArgs->fEnforce;
661 break;
662 case EMEXECPOLICY_IEM_ALL:
663 pVM->em.s.fIemExecutesAll = pArgs->fEnforce;
664 break;
665 default:
666 AssertFailedReturn(VERR_INVALID_PARAMETER);
667 }
668 Log(("emR3SetExecutionPolicy: fRecompileUser=%RTbool fRecompileSupervisor=%RTbool fIemExecutesAll=%RTbool\n",
669 pVM->fRecompileUser, pVM->fRecompileSupervisor, pVM->em.s.fIemExecutesAll));
670 }
671
672 /*
673 * Force rescheduling if in RAW, HM, IEM, or REM.
674 */
675 return pVCpu->em.s.enmState == EMSTATE_RAW
676 || pVCpu->em.s.enmState == EMSTATE_HM
677 || pVCpu->em.s.enmState == EMSTATE_IEM
678 || pVCpu->em.s.enmState == EMSTATE_REM
679 || pVCpu->em.s.enmState == EMSTATE_IEM_THEN_REM
680 ? VINF_EM_RESCHEDULE
681 : VINF_SUCCESS;
682}
683
684
685/**
686 * Changes an execution scheduling policy parameter.
687 *
688 * This is used to enable or disable raw-mode / hardware-virtualization
689 * execution of user and supervisor code.
690 *
691 * @returns VINF_SUCCESS on success.
692 * @returns VINF_RESCHEDULE if a rescheduling might be required.
693 * @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
694 *
695 * @param pUVM The user mode VM handle.
696 * @param enmPolicy The scheduling policy to change.
697 * @param fEnforce Whether to enforce the policy or not.
698 */
699VMMR3DECL(int) EMR3SetExecutionPolicy(PUVM pUVM, EMEXECPOLICY enmPolicy, bool fEnforce)
700{
701 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
702 VM_ASSERT_VALID_EXT_RETURN(pUVM->pVM, VERR_INVALID_VM_HANDLE);
703 AssertReturn(enmPolicy > EMEXECPOLICY_INVALID && enmPolicy < EMEXECPOLICY_END, VERR_INVALID_PARAMETER);
704
705 struct EMR3SETEXECPOLICYARGS Args = { enmPolicy, fEnforce };
706 return VMMR3EmtRendezvous(pUVM->pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_DESCENDING, emR3SetExecutionPolicy, &Args);
707}
708
709
710/**
711 * Queries an execution scheduling policy parameter.
712 *
713 * @returns VBox status code
714 * @param pUVM The user mode VM handle.
715 * @param enmPolicy The scheduling policy to query.
716 * @param pfEnforced Where to return the current value.
717 */
718VMMR3DECL(int) EMR3QueryExecutionPolicy(PUVM pUVM, EMEXECPOLICY enmPolicy, bool *pfEnforced)
719{
720 AssertReturn(enmPolicy > EMEXECPOLICY_INVALID && enmPolicy < EMEXECPOLICY_END, VERR_INVALID_PARAMETER);
721 AssertPtrReturn(pfEnforced, VERR_INVALID_POINTER);
722 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
723 PVM pVM = pUVM->pVM;
724 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
725
726 /* No need to bother EMTs with a query. */
727 switch (enmPolicy)
728 {
729 case EMEXECPOLICY_RECOMPILE_RING0:
730 *pfEnforced = pVM->fRecompileSupervisor;
731 break;
732 case EMEXECPOLICY_RECOMPILE_RING3:
733 *pfEnforced = pVM->fRecompileUser;
734 break;
735 case EMEXECPOLICY_IEM_ALL:
736 *pfEnforced = pVM->em.s.fIemExecutesAll;
737 break;
738 default:
739 AssertFailedReturn(VERR_INTERNAL_ERROR_2);
740 }
741
742 return VINF_SUCCESS;
743}
744
745
746/**
747 * Raise a fatal error.
748 *
749 * Safely terminate the VM with full state report and stuff. This function
750 * will naturally never return.
751 *
752 * @param pVCpu Pointer to the VMCPU.
753 * @param rc VBox status code.
754 */
755VMMR3DECL(void) EMR3FatalError(PVMCPU pVCpu, int rc)
756{
757 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
758 longjmp(pVCpu->em.s.u.FatalLongJump, rc);
759 AssertReleaseMsgFailed(("longjmp returned!\n"));
760}
761
762
763#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
764/**
765 * Gets the EM state name.
766 *
767 * @returns pointer to read only state name,
768 * @param enmState The state.
769 */
770static const char *emR3GetStateName(EMSTATE enmState)
771{
772 switch (enmState)
773 {
774 case EMSTATE_NONE: return "EMSTATE_NONE";
775 case EMSTATE_RAW: return "EMSTATE_RAW";
776 case EMSTATE_HM: return "EMSTATE_HM";
777 case EMSTATE_IEM: return "EMSTATE_IEM";
778 case EMSTATE_REM: return "EMSTATE_REM";
779 case EMSTATE_HALTED: return "EMSTATE_HALTED";
780 case EMSTATE_WAIT_SIPI: return "EMSTATE_WAIT_SIPI";
781 case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
782 case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
783 case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
784 case EMSTATE_DEBUG_GUEST_HM: return "EMSTATE_DEBUG_GUEST_HM";
785 case EMSTATE_DEBUG_GUEST_IEM: return "EMSTATE_DEBUG_GUEST_IEM";
786 case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
787 case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
788 case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
789 case EMSTATE_IEM_THEN_REM: return "EMSTATE_IEM_THEN_REM";
790 default: return "Unknown!";
791 }
792}
793#endif /* LOG_ENABLED || VBOX_STRICT */
794
795
796/**
797 * Debug loop.
798 *
799 * @returns VBox status code for EM.
800 * @param pVM Pointer to the VM.
801 * @param pVCpu Pointer to the VMCPU.
802 * @param rc Current EM VBox status code.
803 */
804static VBOXSTRICTRC emR3Debug(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc)
805{
806 for (;;)
807 {
808 Log(("emR3Debug: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
809 const VBOXSTRICTRC rcLast = rc;
810
811 /*
812 * Debug related RC.
813 */
814 switch (VBOXSTRICTRC_VAL(rc))
815 {
816 /*
817 * Single step an instruction.
818 */
819 case VINF_EM_DBG_STEP:
820 if ( pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
821 || pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
822 || pVCpu->em.s.fForceRAW /* paranoia */)
823#ifdef VBOX_WITH_RAW_MODE
824 rc = emR3RawStep(pVM, pVCpu);
825#else
826 AssertLogRelMsgFailedStmt(("Bad EM state."), VERR_EM_INTERNAL_ERROR);
827#endif
828 else if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HM)
829 rc = EMR3HmSingleInstruction(pVM, pVCpu, 0 /*fFlags*/);
830#ifdef VBOX_WITH_REM
831 else if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM)
832 rc = emR3RemStep(pVM, pVCpu);
833#endif
834 else
835 {
836 rc = IEMExecOne(pVCpu); /** @todo add dedicated interface... */
837 if (rc == VINF_SUCCESS || rc == VINF_EM_RESCHEDULE)
838 rc = VINF_EM_DBG_STEPPED;
839 }
840 break;
841
842 /*
843 * Simple events: stepped, breakpoint, stop/assertion.
844 */
845 case VINF_EM_DBG_STEPPED:
846 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
847 break;
848
849 case VINF_EM_DBG_BREAKPOINT:
850 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
851 break;
852
853 case VINF_EM_DBG_STOP:
854 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
855 break;
856
857 case VINF_EM_DBG_HYPER_STEPPED:
858 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
859 break;
860
861 case VINF_EM_DBG_HYPER_BREAKPOINT:
862 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
863 break;
864
865 case VINF_EM_DBG_HYPER_ASSERTION:
866 RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
867 RTLogFlush(NULL);
868 rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
869 break;
870
871 /*
872 * Guru meditation.
873 */
874 case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
875 rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
876 break;
877 case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
878 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
879 break;
880
881 default: /** @todo don't use default for guru, but make special errors code! */
882 {
883 LogRel(("emR3Debug: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
884 rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
885 break;
886 }
887 }
888
889 /*
890 * Process the result.
891 */
892 do
893 {
894 switch (VBOXSTRICTRC_VAL(rc))
895 {
896 /*
897 * Continue the debugging loop.
898 */
899 case VINF_EM_DBG_STEP:
900 case VINF_EM_DBG_STOP:
901 case VINF_EM_DBG_STEPPED:
902 case VINF_EM_DBG_BREAKPOINT:
903 case VINF_EM_DBG_HYPER_STEPPED:
904 case VINF_EM_DBG_HYPER_BREAKPOINT:
905 case VINF_EM_DBG_HYPER_ASSERTION:
906 break;
907
908 /*
909 * Resuming execution (in some form) has to be done here if we got
910 * a hypervisor debug event.
911 */
912 case VINF_SUCCESS:
913 case VINF_EM_RESUME:
914 case VINF_EM_SUSPEND:
915 case VINF_EM_RESCHEDULE:
916 case VINF_EM_RESCHEDULE_RAW:
917 case VINF_EM_RESCHEDULE_REM:
918 case VINF_EM_HALT:
919 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
920 {
921#ifdef VBOX_WITH_RAW_MODE
922 rc = emR3RawResumeHyper(pVM, pVCpu);
923 if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
924 continue;
925#else
926 AssertLogRelMsgFailedReturn(("Not implemented\n"), VERR_EM_INTERNAL_ERROR);
927#endif
928 }
929 if (rc == VINF_SUCCESS)
930 rc = VINF_EM_RESCHEDULE;
931 return rc;
932
933 /*
934 * The debugger isn't attached.
935 * We'll simply turn the thing off since that's the easiest thing to do.
936 */
937 case VERR_DBGF_NOT_ATTACHED:
938 switch (VBOXSTRICTRC_VAL(rcLast))
939 {
940 case VINF_EM_DBG_HYPER_STEPPED:
941 case VINF_EM_DBG_HYPER_BREAKPOINT:
942 case VINF_EM_DBG_HYPER_ASSERTION:
943 case VERR_TRPM_PANIC:
944 case VERR_TRPM_DONT_PANIC:
945 case VERR_VMM_RING0_ASSERTION:
946 case VERR_VMM_HYPER_CR3_MISMATCH:
947 case VERR_VMM_RING3_CALL_DISABLED:
948 return rcLast;
949 }
950 return VINF_EM_OFF;
951
952 /*
953 * Status codes terminating the VM in one or another sense.
954 */
955 case VINF_EM_TERMINATE:
956 case VINF_EM_OFF:
957 case VINF_EM_RESET:
958 case VINF_EM_NO_MEMORY:
959 case VINF_EM_RAW_STALE_SELECTOR:
960 case VINF_EM_RAW_IRET_TRAP:
961 case VERR_TRPM_PANIC:
962 case VERR_TRPM_DONT_PANIC:
963 case VERR_IEM_INSTR_NOT_IMPLEMENTED:
964 case VERR_IEM_ASPECT_NOT_IMPLEMENTED:
965 case VERR_VMM_RING0_ASSERTION:
966 case VERR_VMM_HYPER_CR3_MISMATCH:
967 case VERR_VMM_RING3_CALL_DISABLED:
968 case VERR_INTERNAL_ERROR:
969 case VERR_INTERNAL_ERROR_2:
970 case VERR_INTERNAL_ERROR_3:
971 case VERR_INTERNAL_ERROR_4:
972 case VERR_INTERNAL_ERROR_5:
973 case VERR_IPE_UNEXPECTED_STATUS:
974 case VERR_IPE_UNEXPECTED_INFO_STATUS:
975 case VERR_IPE_UNEXPECTED_ERROR_STATUS:
976 return rc;
977
978 /*
979 * The rest is unexpected, and will keep us here.
980 */
981 default:
982 AssertMsgFailed(("Unexpected rc %Rrc!\n", VBOXSTRICTRC_VAL(rc)));
983 break;
984 }
985 } while (false);
986 } /* debug for ever */
987}
988
989
990/**
991 * Steps recompiled code.
992 *
993 * @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
994 * VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
995 *
996 * @param pVM Pointer to the VM.
997 * @param pVCpu Pointer to the VMCPU.
998 */
999static int emR3RemStep(PVM pVM, PVMCPU pVCpu)
1000{
1001 Log3(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
1002
1003#ifdef VBOX_WITH_REM
1004 EMRemLock(pVM);
1005
1006 /*
1007 * Switch to REM, step instruction, switch back.
1008 */
1009 int rc = REMR3State(pVM, pVCpu);
1010 if (RT_SUCCESS(rc))
1011 {
1012 rc = REMR3Step(pVM, pVCpu);
1013 REMR3StateBack(pVM, pVCpu);
1014 }
1015 EMRemUnlock(pVM);
1016
1017#else
1018 int rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu)); NOREF(pVM);
1019#endif
1020
1021 Log3(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
1022 return rc;
1023}
1024
1025
1026/**
1027 * emR3RemExecute helper that syncs the state back from REM and leave the REM
1028 * critical section.
1029 *
1030 * @returns false - new fInREMState value.
1031 * @param pVM Pointer to the VM.
1032 * @param pVCpu Pointer to the VMCPU.
1033 */
1034DECLINLINE(bool) emR3RemExecuteSyncBack(PVM pVM, PVMCPU pVCpu)
1035{
1036#ifdef VBOX_WITH_REM
1037 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, a);
1038 REMR3StateBack(pVM, pVCpu);
1039 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, a);
1040
1041 EMRemUnlock(pVM);
1042#endif
1043 return false;
1044}
1045
1046
1047/**
1048 * Executes recompiled code.
1049 *
1050 * This function contains the recompiler version of the inner
1051 * execution loop (the outer loop being in EMR3ExecuteVM()).
1052 *
1053 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1054 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1055 *
1056 * @param pVM Pointer to the VM.
1057 * @param pVCpu Pointer to the VMCPU.
1058 * @param pfFFDone Where to store an indicator telling whether or not
1059 * FFs were done before returning.
1060 *
1061 */
1062static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1063{
1064#ifdef LOG_ENABLED
1065 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1066 uint32_t cpl = CPUMGetGuestCPL(pVCpu);
1067
1068 if (pCtx->eflags.Bits.u1VM)
1069 Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags.Bits.u1IF));
1070 else
1071 Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x eflags=%x\n", cpl, pCtx->cs.Sel, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, pCtx->eflags.u));
1072#endif
1073 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatREMTotal, a);
1074
1075#if defined(VBOX_STRICT) && defined(DEBUG_bird)
1076 AssertMsg( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1077 || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVCpu)), /** @todo @bugref{1419} - get flat address. */
1078 ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
1079#endif
1080
1081 /*
1082 * Spin till we get a forced action which returns anything but VINF_SUCCESS
1083 * or the REM suggests raw-mode execution.
1084 */
1085 *pfFFDone = false;
1086#ifdef VBOX_WITH_REM
1087 bool fInREMState = false;
1088#endif
1089 int rc = VINF_SUCCESS;
1090 for (;;)
1091 {
1092#ifdef VBOX_WITH_REM
1093 /*
1094 * Lock REM and update the state if not already in sync.
1095 *
1096 * Note! Big lock, but you are not supposed to own any lock when
1097 * coming in here.
1098 */
1099 if (!fInREMState)
1100 {
1101 EMRemLock(pVM);
1102 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, b);
1103
1104 /* Flush the recompiler translation blocks if the VCPU has changed,
1105 also force a full CPU state resync. */
1106 if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
1107 {
1108 REMFlushTBs(pVM);
1109 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1110 }
1111 pVM->em.s.idLastRemCpu = pVCpu->idCpu;
1112
1113 rc = REMR3State(pVM, pVCpu);
1114
1115 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, b);
1116 if (RT_FAILURE(rc))
1117 break;
1118 fInREMState = true;
1119
1120 /*
1121 * We might have missed the raising of VMREQ, TIMER and some other
1122 * important FFs while we were busy switching the state. So, check again.
1123 */
1124 if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_CHECK_VM_STATE | VM_FF_RESET)
1125 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TIMER | VMCPU_FF_REQUEST))
1126 {
1127 LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fGlobalForcedActions));
1128 goto l_REMDoForcedActions;
1129 }
1130 }
1131#endif
1132
1133 /*
1134 * Execute REM.
1135 */
1136 if (RT_LIKELY(emR3IsExecutionAllowed(pVM, pVCpu)))
1137 {
1138 STAM_PROFILE_START(&pVCpu->em.s.StatREMExec, c);
1139#ifdef VBOX_WITH_REM
1140 rc = REMR3Run(pVM, pVCpu);
1141#else
1142 rc = VBOXSTRICTRC_TODO(IEMExecLots(pVCpu));
1143#endif
1144 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMExec, c);
1145 }
1146 else
1147 {
1148 /* Give up this time slice; virtual time continues */
1149 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1150 RTThreadSleep(5);
1151 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1152 rc = VINF_SUCCESS;
1153 }
1154
1155 /*
1156 * Deal with high priority post execution FFs before doing anything
1157 * else. Sync back the state and leave the lock to be on the safe side.
1158 */
1159 if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1160 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1161 {
1162#ifdef VBOX_WITH_REM
1163 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1164#endif
1165 rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1166 }
1167
1168 /*
1169 * Process the returned status code.
1170 */
1171 if (rc != VINF_SUCCESS)
1172 {
1173 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1174 break;
1175 if (rc != VINF_REM_INTERRUPED_FF)
1176 {
1177 /*
1178 * Anything which is not known to us means an internal error
1179 * and the termination of the VM!
1180 */
1181 AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
1182 break;
1183 }
1184 }
1185
1186
1187 /*
1188 * Check and execute forced actions.
1189 *
1190 * Sync back the VM state and leave the lock before calling any of
1191 * these, you never know what's going to happen here.
1192 */
1193#ifdef VBOX_HIGH_RES_TIMERS_HACK
1194 TMTimerPollVoid(pVM, pVCpu);
1195#endif
1196 AssertCompile(VMCPU_FF_ALL_REM_MASK & VMCPU_FF_TIMER);
1197 if ( VM_FF_IS_PENDING(pVM, VM_FF_ALL_REM_MASK)
1198 || VMCPU_FF_IS_PENDING(pVCpu,
1199 VMCPU_FF_ALL_REM_MASK
1200 & VM_WHEN_RAW_MODE(~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE), UINT32_MAX)) )
1201 {
1202l_REMDoForcedActions:
1203#ifdef VBOX_WITH_REM
1204 if (fInREMState)
1205 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1206#endif
1207 STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatREMTotal, a);
1208 rc = emR3ForcedActions(pVM, pVCpu, rc);
1209 VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
1210 STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatREMTotal, a);
1211 if ( rc != VINF_SUCCESS
1212 && rc != VINF_EM_RESCHEDULE_REM)
1213 {
1214 *pfFFDone = true;
1215 break;
1216 }
1217 }
1218
1219 } /* The Inner Loop, recompiled execution mode version. */
1220
1221
1222#ifdef VBOX_WITH_REM
1223 /*
1224 * Returning. Sync back the VM state if required.
1225 */
1226 if (fInREMState)
1227 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1228#endif
1229
1230 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatREMTotal, a);
1231 return rc;
1232}
1233
1234
1235#ifdef DEBUG
1236
1237int emR3SingleStepExecRem(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1238{
1239 EMSTATE enmOldState = pVCpu->em.s.enmState;
1240
1241 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1242
1243 Log(("Single step BEGIN:\n"));
1244 for (uint32_t i = 0; i < cIterations; i++)
1245 {
1246 DBGFR3PrgStep(pVCpu);
1247 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "RSS");
1248 emR3RemStep(pVM, pVCpu);
1249 if (emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx) != EMSTATE_REM)
1250 break;
1251 }
1252 Log(("Single step END:\n"));
1253 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1254 pVCpu->em.s.enmState = enmOldState;
1255 return VINF_EM_RESCHEDULE;
1256}
1257
1258#endif /* DEBUG */
1259
1260
1261/**
1262 * Try execute the problematic code in IEM first, then fall back on REM if there
1263 * is too much of it or if IEM doesn't implement something.
1264 *
1265 * @returns Strict VBox status code from IEMExecLots.
1266 * @param pVM The cross context VM structure.
1267 * @param pVCpu The cross context CPU structure for the calling EMT.
1268 * @param pfFFDone Force flags done indicator.
1269 *
1270 * @thread EMT(pVCpu)
1271 */
1272static VBOXSTRICTRC emR3ExecuteIemThenRem(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1273{
1274 LogFlow(("emR3ExecuteIemThenRem: %04x:%RGv\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestRIP(pVCpu)));
1275 *pfFFDone = false;
1276
1277 /*
1278 * Execute in IEM for a while.
1279 */
1280 while (pVCpu->em.s.cIemThenRemInstructions < 1024)
1281 {
1282 VBOXSTRICTRC rcStrict = IEMExecLots(pVCpu);
1283 if (rcStrict != VINF_SUCCESS)
1284 {
1285 if ( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1286 || rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED)
1287 break;
1288
1289 pVCpu->em.s.cIemThenRemInstructions++;
1290 Log(("emR3ExecuteIemThenRem: returns %Rrc after %u instructions\n",
1291 VBOXSTRICTRC_VAL(rcStrict), pVCpu->em.s.cIemThenRemInstructions));
1292 return rcStrict;
1293 }
1294 pVCpu->em.s.cIemThenRemInstructions++;
1295
1296 EMSTATE enmNewState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1297 if (enmNewState != EMSTATE_REM && enmNewState != EMSTATE_IEM_THEN_REM)
1298 {
1299 LogFlow(("emR3ExecuteIemThenRem: -> %d (%s) after %u instructions\n",
1300 enmNewState, emR3GetStateName(enmNewState), pVCpu->em.s.cIemThenRemInstructions));
1301 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
1302 pVCpu->em.s.enmState = enmNewState;
1303 return VINF_SUCCESS;
1304 }
1305
1306 /*
1307 * Check for pending actions.
1308 */
1309 if ( VM_FF_IS_PENDING(pVM, VM_FF_ALL_REM_MASK)
1310 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_ALL_REM_MASK))
1311 return VINF_SUCCESS;
1312 }
1313
1314 /*
1315 * Switch to REM.
1316 */
1317 Log(("emR3ExecuteIemThenRem: -> EMSTATE_REM (after %u instructions)\n", pVCpu->em.s.cIemThenRemInstructions));
1318 pVCpu->em.s.enmState = EMSTATE_REM;
1319 return VINF_SUCCESS;
1320}
1321
1322
1323/**
1324 * Decides whether to execute RAW, HWACC or REM.
1325 *
1326 * @returns new EM state
1327 * @param pVM Pointer to the VM.
1328 * @param pVCpu Pointer to the VMCPU.
1329 * @param pCtx Pointer to the guest CPU context.
1330 */
1331EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1332{
1333 /*
1334 * When forcing raw-mode execution, things are simple.
1335 */
1336 if (pVCpu->em.s.fForceRAW)
1337 return EMSTATE_RAW;
1338
1339 /*
1340 * We stay in the wait for SIPI state unless explicitly told otherwise.
1341 */
1342 if (pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI)
1343 return EMSTATE_WAIT_SIPI;
1344
1345 /*
1346 * Execute everything in IEM?
1347 */
1348 if (pVM->em.s.fIemExecutesAll)
1349 return EMSTATE_IEM;
1350
1351 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1352 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1353 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1354
1355 X86EFLAGS EFlags = pCtx->eflags;
1356 if (HMIsEnabled(pVM))
1357 {
1358 /*
1359 * Hardware accelerated raw-mode:
1360 */
1361 if ( EMIsHwVirtExecutionEnabled(pVM)
1362 && HMR3CanExecuteGuest(pVM, pCtx))
1363 return EMSTATE_HM;
1364
1365 /*
1366 * Note! Raw mode and hw accelerated mode are incompatible. The latter
1367 * turns off monitoring features essential for raw mode!
1368 */
1369#ifdef VBOX_WITH_FIRST_IEM_STEP
1370 return EMSTATE_IEM_THEN_REM;
1371#else
1372 return EMSTATE_REM;
1373#endif
1374 }
1375
1376 /*
1377 * Standard raw-mode:
1378 *
1379 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1380 * or 32 bits protected mode ring 0 code
1381 *
1382 * The tests are ordered by the likelihood of being true during normal execution.
1383 */
1384 if (EFlags.u32 & (X86_EFL_TF /* | HF_INHIBIT_IRQ_MASK*/))
1385 {
1386 Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
1387 return EMSTATE_REM;
1388 }
1389
1390# ifndef VBOX_RAW_V86
1391 if (EFlags.u32 & X86_EFL_VM) {
1392 Log2(("raw mode refused: VM_MASK\n"));
1393 return EMSTATE_REM;
1394 }
1395# endif
1396
1397 /** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
1398 uint32_t u32CR0 = pCtx->cr0;
1399 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
1400 {
1401 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1402 return EMSTATE_REM;
1403 }
1404
1405 if (pCtx->cr4 & X86_CR4_PAE)
1406 {
1407 uint32_t u32Dummy, u32Features;
1408
1409 CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1410 if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
1411 return EMSTATE_REM;
1412 }
1413
1414 unsigned uSS = pCtx->ss.Sel;
1415 if ( pCtx->eflags.Bits.u1VM
1416 || (uSS & X86_SEL_RPL) == 3)
1417 {
1418 if (!EMIsRawRing3Enabled(pVM))
1419 return EMSTATE_REM;
1420
1421 if (!(EFlags.u32 & X86_EFL_IF))
1422 {
1423 Log2(("raw mode refused: IF (RawR3)\n"));
1424 return EMSTATE_REM;
1425 }
1426
1427 if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
1428 {
1429 Log2(("raw mode refused: CR0.WP + RawR0\n"));
1430 return EMSTATE_REM;
1431 }
1432 }
1433 else
1434 {
1435 if (!EMIsRawRing0Enabled(pVM))
1436 return EMSTATE_REM;
1437
1438 if (EMIsRawRing1Enabled(pVM))
1439 {
1440 /* Only ring 0 and 1 supervisor code. */
1441 if ((uSS & X86_SEL_RPL) == 2) /* ring 1 code is moved into ring 2, so we can't support ring-2 in that case. */
1442 {
1443 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
1444 return EMSTATE_REM;
1445 }
1446 }
1447 /* Only ring 0 supervisor code. */
1448 else if ((uSS & X86_SEL_RPL) != 0)
1449 {
1450 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
1451 return EMSTATE_REM;
1452 }
1453
1454 // Let's start with pure 32 bits ring 0 code first
1455 /** @todo What's pure 32-bit mode? flat? */
1456 if ( !(pCtx->ss.Attr.n.u1DefBig)
1457 || !(pCtx->cs.Attr.n.u1DefBig))
1458 {
1459 Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
1460 return EMSTATE_REM;
1461 }
1462
1463 /* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
1464 if (!(u32CR0 & X86_CR0_WP))
1465 {
1466 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1467 return EMSTATE_REM;
1468 }
1469
1470# ifdef VBOX_WITH_RAW_MODE
1471 if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
1472 {
1473 Log2(("raw r0 mode forced: patch code\n"));
1474# ifdef VBOX_WITH_SAFE_STR
1475 Assert(pCtx->tr.Sel);
1476# endif
1477 return EMSTATE_RAW;
1478 }
1479# endif /* VBOX_WITH_RAW_MODE */
1480
1481# if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1482 if (!(EFlags.u32 & X86_EFL_IF))
1483 {
1484 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
1485 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1486 return EMSTATE_REM;
1487 }
1488# endif
1489
1490# ifndef VBOX_WITH_RAW_RING1
1491 /** @todo still necessary??? */
1492 if (EFlags.Bits.u2IOPL != 0)
1493 {
1494 Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
1495 return EMSTATE_REM;
1496 }
1497# endif
1498 }
1499
1500 /*
1501 * Stale hidden selectors means raw-mode is unsafe (being very careful).
1502 */
1503 if (pCtx->cs.fFlags & CPUMSELREG_FLAGS_STALE)
1504 {
1505 Log2(("raw mode refused: stale CS\n"));
1506 return EMSTATE_REM;
1507 }
1508 if (pCtx->ss.fFlags & CPUMSELREG_FLAGS_STALE)
1509 {
1510 Log2(("raw mode refused: stale SS\n"));
1511 return EMSTATE_REM;
1512 }
1513 if (pCtx->ds.fFlags & CPUMSELREG_FLAGS_STALE)
1514 {
1515 Log2(("raw mode refused: stale DS\n"));
1516 return EMSTATE_REM;
1517 }
1518 if (pCtx->es.fFlags & CPUMSELREG_FLAGS_STALE)
1519 {
1520 Log2(("raw mode refused: stale ES\n"));
1521 return EMSTATE_REM;
1522 }
1523 if (pCtx->fs.fFlags & CPUMSELREG_FLAGS_STALE)
1524 {
1525 Log2(("raw mode refused: stale FS\n"));
1526 return EMSTATE_REM;
1527 }
1528 if (pCtx->gs.fFlags & CPUMSELREG_FLAGS_STALE)
1529 {
1530 Log2(("raw mode refused: stale GS\n"));
1531 return EMSTATE_REM;
1532 }
1533
1534# ifdef VBOX_WITH_SAFE_STR
1535 if (pCtx->tr.Sel == 0)
1536 {
1537 Log(("Raw mode refused -> TR=0\n"));
1538 return EMSTATE_REM;
1539 }
1540# endif
1541
1542 /*Assert(PGMPhysIsA20Enabled(pVCpu));*/
1543 return EMSTATE_RAW;
1544}
1545
1546
1547/**
1548 * Executes all high priority post execution force actions.
1549 *
1550 * @returns rc or a fatal status code.
1551 *
1552 * @param pVM Pointer to the VM.
1553 * @param pVCpu Pointer to the VMCPU.
1554 * @param rc The current rc.
1555 */
1556int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1557{
1558 VBOXVMM_EM_FF_HIGH(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions, rc);
1559
1560 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PDM_CRITSECT))
1561 PDMCritSectBothFF(pVCpu);
1562
1563 /* Update CR3 (Nested Paging case for HM). */
1564 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
1565 {
1566 int rc2 = PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
1567 if (RT_FAILURE(rc2))
1568 return rc2;
1569 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
1570 }
1571
1572 /* Update PAE PDPEs. This must be done *after* PGMUpdateCR3() and used only by the Nested Paging case for HM. */
1573 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
1574 {
1575 if (CPUMIsGuestInPAEMode(pVCpu))
1576 {
1577 PX86PDPE pPdpes = HMGetPaePdpes(pVCpu);
1578 AssertPtr(pPdpes);
1579
1580 PGMGstUpdatePaePdpes(pVCpu, pPdpes);
1581 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
1582 }
1583 else
1584 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
1585 }
1586
1587#ifdef VBOX_WITH_RAW_MODE
1588 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION))
1589 CSAMR3DoPendingAction(pVM, pVCpu);
1590#endif
1591
1592 if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
1593 {
1594 if ( rc > VINF_EM_NO_MEMORY
1595 && rc <= VINF_EM_LAST)
1596 rc = VINF_EM_NO_MEMORY;
1597 }
1598
1599 return rc;
1600}
1601
1602
1603/**
1604 * Executes all pending forced actions.
1605 *
1606 * Forced actions can cause execution delays and execution
1607 * rescheduling. The first we deal with using action priority, so
1608 * that for instance pending timers aren't scheduled and ran until
1609 * right before execution. The rescheduling we deal with using
1610 * return codes. The same goes for VM termination, only in that case
1611 * we exit everything.
1612 *
1613 * @returns VBox status code of equal or greater importance/severity than rc.
1614 * The most important ones are: VINF_EM_RESCHEDULE,
1615 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1616 *
1617 * @param pVM Pointer to the VM.
1618 * @param pVCpu Pointer to the VMCPU.
1619 * @param rc The current rc.
1620 *
1621 */
1622int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1623{
1624 STAM_REL_PROFILE_START(&pVCpu->em.s.StatForcedActions, a);
1625#ifdef VBOX_STRICT
1626 int rcIrq = VINF_SUCCESS;
1627#endif
1628 int rc2;
1629#define UPDATE_RC() \
1630 do { \
1631 AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
1632 if (rc2 == VINF_SUCCESS || rc < VINF_SUCCESS) \
1633 break; \
1634 if (!rc || rc2 < rc) \
1635 rc = rc2; \
1636 } while (0)
1637 VBOXVMM_EM_FF_ALL(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions, rc);
1638
1639 /*
1640 * Post execution chunk first.
1641 */
1642 if ( VM_FF_IS_PENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK)
1643 || (VMCPU_FF_NORMAL_PRIORITY_POST_MASK && VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_POST_MASK)) )
1644 {
1645 /*
1646 * EMT Rendezvous (must be serviced before termination).
1647 */
1648 if (VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1649 {
1650 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1651 UPDATE_RC();
1652 /** @todo HACK ALERT! The following test is to make sure EM+TM
1653 * thinks the VM is stopped/reset before the next VM state change
1654 * is made. We need a better solution for this, or at least make it
1655 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1656 * VINF_EM_SUSPEND). */
1657 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1658 {
1659 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1660 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1661 return rc;
1662 }
1663 }
1664
1665 /*
1666 * State change request (cleared by vmR3SetStateLocked).
1667 */
1668 if (VM_FF_IS_PENDING(pVM, VM_FF_CHECK_VM_STATE))
1669 {
1670 VMSTATE enmState = VMR3GetState(pVM);
1671 switch (enmState)
1672 {
1673 case VMSTATE_FATAL_ERROR:
1674 case VMSTATE_FATAL_ERROR_LS:
1675 Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
1676 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1677 return VINF_EM_SUSPEND;
1678
1679 case VMSTATE_DESTROYING:
1680 Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
1681 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1682 return VINF_EM_TERMINATE;
1683
1684 default:
1685 AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
1686 }
1687 }
1688
1689 /*
1690 * Debugger Facility polling.
1691 */
1692 if (VM_FF_IS_PENDING(pVM, VM_FF_DBGF))
1693 {
1694 rc2 = DBGFR3VMMForcedAction(pVM);
1695 UPDATE_RC();
1696 }
1697
1698 /*
1699 * Postponed reset request.
1700 */
1701 if (VM_FF_TEST_AND_CLEAR(pVM, VM_FF_RESET))
1702 {
1703 rc2 = VMR3Reset(pVM->pUVM);
1704 UPDATE_RC();
1705 }
1706
1707#ifdef VBOX_WITH_RAW_MODE
1708 /*
1709 * CSAM page scanning.
1710 */
1711 if ( !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)
1712 && VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE))
1713 {
1714 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1715
1716 /** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
1717 Log(("Forced action VMCPU_FF_CSAM_SCAN_PAGE\n"));
1718
1719 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1720 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE);
1721 }
1722#endif
1723
1724 /*
1725 * Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
1726 */
1727 if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
1728 {
1729 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1730 UPDATE_RC();
1731 if (rc == VINF_EM_NO_MEMORY)
1732 return rc;
1733 }
1734
1735 /* check that we got them all */
1736 AssertCompile(VM_FF_NORMAL_PRIORITY_POST_MASK == (VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1737 AssertCompile(VMCPU_FF_NORMAL_PRIORITY_POST_MASK == VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0));
1738 }
1739
1740 /*
1741 * Normal priority then.
1742 * (Executed in no particular order.)
1743 */
1744 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_NORMAL_PRIORITY_MASK, VM_FF_PGM_NO_MEMORY))
1745 {
1746 /*
1747 * PDM Queues are pending.
1748 */
1749 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_QUEUES, VM_FF_PGM_NO_MEMORY))
1750 PDMR3QueueFlushAll(pVM);
1751
1752 /*
1753 * PDM DMA transfers are pending.
1754 */
1755 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_DMA, VM_FF_PGM_NO_MEMORY))
1756 PDMR3DmaRun(pVM);
1757
1758 /*
1759 * EMT Rendezvous (make sure they are handled before the requests).
1760 */
1761 if (VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1762 {
1763 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1764 UPDATE_RC();
1765 /** @todo HACK ALERT! The following test is to make sure EM+TM
1766 * thinks the VM is stopped/reset before the next VM state change
1767 * is made. We need a better solution for this, or at least make it
1768 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1769 * VINF_EM_SUSPEND). */
1770 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1771 {
1772 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1773 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1774 return rc;
1775 }
1776 }
1777
1778 /*
1779 * Requests from other threads.
1780 */
1781 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
1782 {
1783 rc2 = VMR3ReqProcessU(pVM->pUVM, VMCPUID_ANY, false /*fPriorityOnly*/);
1784 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE) /** @todo this shouldn't be necessary */
1785 {
1786 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1787 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1788 return rc2;
1789 }
1790 UPDATE_RC();
1791 /** @todo HACK ALERT! The following test is to make sure EM+TM
1792 * thinks the VM is stopped/reset before the next VM state change
1793 * is made. We need a better solution for this, or at least make it
1794 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1795 * VINF_EM_SUSPEND). */
1796 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1797 {
1798 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1799 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1800 return rc;
1801 }
1802 }
1803
1804#ifdef VBOX_WITH_REM
1805 /* Replay the handler notification changes. */
1806 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REM_HANDLER_NOTIFY, VM_FF_PGM_NO_MEMORY))
1807 {
1808 /* Try not to cause deadlocks. */
1809 if ( pVM->cCpus == 1
1810 || ( !PGMIsLockOwner(pVM)
1811 && !IOMIsLockWriteOwner(pVM))
1812 )
1813 {
1814 EMRemLock(pVM);
1815 REMR3ReplayHandlerNotifications(pVM);
1816 EMRemUnlock(pVM);
1817 }
1818 }
1819#endif
1820
1821 /* check that we got them all */
1822 AssertCompile(VM_FF_NORMAL_PRIORITY_MASK == (VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_REM_HANDLER_NOTIFY | VM_FF_EMT_RENDEZVOUS));
1823 }
1824
1825 /*
1826 * Normal priority then. (per-VCPU)
1827 * (Executed in no particular order.)
1828 */
1829 if ( !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)
1830 && VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_MASK))
1831 {
1832 /*
1833 * Requests from other threads.
1834 */
1835 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
1836 {
1837 rc2 = VMR3ReqProcessU(pVM->pUVM, pVCpu->idCpu, false /*fPriorityOnly*/);
1838 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE || rc2 == VINF_EM_RESET)
1839 {
1840 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1841 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1842 return rc2;
1843 }
1844 UPDATE_RC();
1845 /** @todo HACK ALERT! The following test is to make sure EM+TM
1846 * thinks the VM is stopped/reset before the next VM state change
1847 * is made. We need a better solution for this, or at least make it
1848 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1849 * VINF_EM_SUSPEND). */
1850 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1851 {
1852 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1853 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1854 return rc;
1855 }
1856 }
1857
1858 /* check that we got them all */
1859 Assert(!(VMCPU_FF_NORMAL_PRIORITY_MASK & ~(VMCPU_FF_REQUEST)));
1860 }
1861
1862 /*
1863 * High priority pre execution chunk last.
1864 * (Executed in ascending priority order.)
1865 */
1866 if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK)
1867 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_MASK))
1868 {
1869 /*
1870 * Timers before interrupts.
1871 */
1872 if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TIMER)
1873 && !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
1874 TMR3TimerQueuesDo(pVM);
1875
1876 /*
1877 * The instruction following an emulated STI should *always* be executed!
1878 *
1879 * Note! We intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if
1880 * the eip is the same as the inhibited instr address. Before we
1881 * are able to execute this instruction in raw mode (iret to
1882 * guest code) an external interrupt might force a world switch
1883 * again. Possibly allowing a guest interrupt to be dispatched
1884 * in the process. This could break the guest. Sounds very
1885 * unlikely, but such timing sensitive problem are not as rare as
1886 * you might think.
1887 */
1888 if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1889 && !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
1890 {
1891 if (CPUMGetGuestRIP(pVCpu) != EMGetInhibitInterruptsPC(pVCpu))
1892 {
1893 Log(("Clearing VMCPU_FF_INHIBIT_INTERRUPTS at %RGv - successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu), EMGetInhibitInterruptsPC(pVCpu)));
1894 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1895 }
1896 else
1897 Log(("Leaving VMCPU_FF_INHIBIT_INTERRUPTS set at %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu)));
1898 }
1899
1900 /*
1901 * Interrupts.
1902 */
1903 bool fWakeupPending = false;
1904 if ( !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)
1905 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1906 && (!rc || rc >= VINF_EM_RESCHEDULE_HM)
1907 && !TRPMHasTrap(pVCpu) /* an interrupt could already be scheduled for dispatching in the recompiler. */
1908#ifdef VBOX_WITH_RAW_MODE
1909 && PATMAreInterruptsEnabled(pVM)
1910#else
1911 && (pVCpu->em.s.pCtx->eflags.u32 & X86_EFL_IF)
1912#endif
1913 && !HMR3IsEventPending(pVCpu))
1914 {
1915 Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1916 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
1917 {
1918 /* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
1919 /** @todo this really isn't nice, should properly handle this */
1920 rc2 = TRPMR3InjectEvent(pVM, pVCpu, TRPM_HARDWARE_INT);
1921 if (pVM->em.s.fIemExecutesAll && (rc2 == VINF_EM_RESCHEDULE_REM || rc2 == VINF_EM_RESCHEDULE_HM || rc2 == VINF_EM_RESCHEDULE_RAW))
1922 rc2 = VINF_EM_RESCHEDULE;
1923#ifdef VBOX_STRICT
1924 rcIrq = rc2;
1925#endif
1926 UPDATE_RC();
1927 /* Reschedule required: We must not miss the wakeup below! */
1928 fWakeupPending = true;
1929 }
1930#ifdef VBOX_WITH_REM
1931 /** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
1932 else if (REMR3QueryPendingInterrupt(pVM, pVCpu) != REM_NO_PENDING_IRQ)
1933 {
1934 Log2(("REMR3QueryPendingInterrupt -> %#x\n", REMR3QueryPendingInterrupt(pVM, pVCpu)));
1935 rc2 = VINF_EM_RESCHEDULE_REM;
1936 UPDATE_RC();
1937 }
1938#endif
1939 }
1940
1941 /*
1942 * Allocate handy pages.
1943 */
1944 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1945 {
1946 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1947 UPDATE_RC();
1948 }
1949
1950 /*
1951 * Debugger Facility request.
1952 */
1953 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_DBGF, VM_FF_PGM_NO_MEMORY))
1954 {
1955 rc2 = DBGFR3VMMForcedAction(pVM);
1956 UPDATE_RC();
1957 }
1958
1959 /*
1960 * EMT Rendezvous (must be serviced before termination).
1961 */
1962 if ( !fWakeupPending /* don't miss the wakeup from EMSTATE_HALTED! */
1963 && VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1964 {
1965 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1966 UPDATE_RC();
1967 /** @todo HACK ALERT! The following test is to make sure EM+TM thinks the VM is
1968 * stopped/reset before the next VM state change is made. We need a better
1969 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1970 * && rc >= VINF_EM_SUSPEND). */
1971 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1972 {
1973 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1974 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1975 return rc;
1976 }
1977 }
1978
1979 /*
1980 * State change request (cleared by vmR3SetStateLocked).
1981 */
1982 if ( !fWakeupPending /* don't miss the wakeup from EMSTATE_HALTED! */
1983 && VM_FF_IS_PENDING(pVM, VM_FF_CHECK_VM_STATE))
1984 {
1985 VMSTATE enmState = VMR3GetState(pVM);
1986 switch (enmState)
1987 {
1988 case VMSTATE_FATAL_ERROR:
1989 case VMSTATE_FATAL_ERROR_LS:
1990 Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
1991 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1992 return VINF_EM_SUSPEND;
1993
1994 case VMSTATE_DESTROYING:
1995 Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
1996 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1997 return VINF_EM_TERMINATE;
1998
1999 default:
2000 AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
2001 }
2002 }
2003
2004 /*
2005 * Out of memory? Since most of our fellow high priority actions may cause us
2006 * to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
2007 * at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
2008 * than us since we can terminate without allocating more memory.
2009 */
2010 if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
2011 {
2012 rc2 = PGMR3PhysAllocateHandyPages(pVM);
2013 UPDATE_RC();
2014 if (rc == VINF_EM_NO_MEMORY)
2015 return rc;
2016 }
2017
2018 /*
2019 * If the virtual sync clock is still stopped, make TM restart it.
2020 */
2021 if (VM_FF_IS_PENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
2022 TMR3VirtualSyncFF(pVM, pVCpu);
2023
2024#ifdef DEBUG
2025 /*
2026 * Debug, pause the VM.
2027 */
2028 if (VM_FF_IS_PENDING(pVM, VM_FF_DEBUG_SUSPEND))
2029 {
2030 VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
2031 Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
2032 return VINF_EM_SUSPEND;
2033 }
2034#endif
2035
2036 /* check that we got them all */
2037 AssertCompile(VM_FF_HIGH_PRIORITY_PRE_MASK == (VM_FF_TM_VIRTUAL_SYNC | VM_FF_DBGF | VM_FF_CHECK_VM_STATE | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
2038 AssertCompile(VMCPU_FF_HIGH_PRIORITY_PRE_MASK == (VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_INHIBIT_INTERRUPTS | VM_WHEN_RAW_MODE(VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT, 0)));
2039 }
2040
2041#undef UPDATE_RC
2042 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
2043 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
2044 Assert(rcIrq == VINF_SUCCESS || rcIrq == rc);
2045 return rc;
2046}
2047
2048
2049/**
2050 * Check if the preset execution time cap restricts guest execution scheduling.
2051 *
2052 * @returns true if allowed, false otherwise
2053 * @param pVM Pointer to the VM.
2054 * @param pVCpu Pointer to the VMCPU.
2055 */
2056bool emR3IsExecutionAllowed(PVM pVM, PVMCPU pVCpu)
2057{
2058 uint64_t u64UserTime, u64KernelTime;
2059
2060 if ( pVM->uCpuExecutionCap != 100
2061 && RT_SUCCESS(RTThreadGetExecutionTimeMilli(&u64KernelTime, &u64UserTime)))
2062 {
2063 uint64_t u64TimeNow = RTTimeMilliTS();
2064 if (pVCpu->em.s.u64TimeSliceStart + EM_TIME_SLICE < u64TimeNow)
2065 {
2066 /* New time slice. */
2067 pVCpu->em.s.u64TimeSliceStart = u64TimeNow;
2068 pVCpu->em.s.u64TimeSliceStartExec = u64KernelTime + u64UserTime;
2069 pVCpu->em.s.u64TimeSliceExec = 0;
2070 }
2071 pVCpu->em.s.u64TimeSliceExec = u64KernelTime + u64UserTime - pVCpu->em.s.u64TimeSliceStartExec;
2072
2073 Log2(("emR3IsExecutionAllowed: start=%RX64 startexec=%RX64 exec=%RX64 (cap=%x)\n", pVCpu->em.s.u64TimeSliceStart, pVCpu->em.s.u64TimeSliceStartExec, pVCpu->em.s.u64TimeSliceExec, (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100));
2074 if (pVCpu->em.s.u64TimeSliceExec >= (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100)
2075 return false;
2076 }
2077 return true;
2078}
2079
2080
2081/**
2082 * Execute VM.
2083 *
2084 * This function is the main loop of the VM. The emulation thread
2085 * calls this function when the VM has been successfully constructed
2086 * and we're ready for executing the VM.
2087 *
2088 * Returning from this function means that the VM is turned off or
2089 * suspended (state already saved) and deconstruction is next in line.
2090 *
2091 * All interaction from other thread are done using forced actions
2092 * and signaling of the wait object.
2093 *
2094 * @returns VBox status code, informational status codes may indicate failure.
2095 * @param pVM Pointer to the VM.
2096 * @param pVCpu Pointer to the VMCPU.
2097 */
2098VMMR3_INT_DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu)
2099{
2100 Log(("EMR3ExecuteVM: pVM=%p enmVMState=%d (%s) enmState=%d (%s) enmPrevState=%d (%s) fForceRAW=%RTbool\n",
2101 pVM,
2102 pVM->enmVMState, VMR3GetStateName(pVM->enmVMState),
2103 pVCpu->em.s.enmState, emR3GetStateName(pVCpu->em.s.enmState),
2104 pVCpu->em.s.enmPrevState, emR3GetStateName(pVCpu->em.s.enmPrevState),
2105 pVCpu->em.s.fForceRAW));
2106 VM_ASSERT_EMT(pVM);
2107 AssertMsg( pVCpu->em.s.enmState == EMSTATE_NONE
2108 || pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI
2109 || pVCpu->em.s.enmState == EMSTATE_SUSPENDED,
2110 ("%s\n", emR3GetStateName(pVCpu->em.s.enmState)));
2111
2112 int rc = setjmp(pVCpu->em.s.u.FatalLongJump);
2113 if (rc == 0)
2114 {
2115 /*
2116 * Start the virtual time.
2117 */
2118 TMR3NotifyResume(pVM, pVCpu);
2119
2120 /*
2121 * The Outer Main Loop.
2122 */
2123 bool fFFDone = false;
2124
2125 /* Reschedule right away to start in the right state. */
2126 rc = VINF_SUCCESS;
2127
2128 /* If resuming after a pause or a state load, restore the previous
2129 state or else we'll start executing code. Else, just reschedule. */
2130 if ( pVCpu->em.s.enmState == EMSTATE_SUSPENDED
2131 && ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
2132 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED))
2133 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2134 else
2135 pVCpu->em.s.enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
2136 pVCpu->em.s.cIemThenRemInstructions = 0;
2137 Log(("EMR3ExecuteVM: enmState=%s\n", emR3GetStateName(pVCpu->em.s.enmState)));
2138
2139 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2140 for (;;)
2141 {
2142 /*
2143 * Before we can schedule anything (we're here because
2144 * scheduling is required) we must service any pending
2145 * forced actions to avoid any pending action causing
2146 * immediate rescheduling upon entering an inner loop
2147 *
2148 * Do forced actions.
2149 */
2150 if ( !fFFDone
2151 && RT_SUCCESS(rc)
2152 && rc != VINF_EM_TERMINATE
2153 && rc != VINF_EM_OFF
2154 && ( VM_FF_IS_PENDING(pVM, VM_FF_ALL_REM_MASK)
2155 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_ALL_REM_MASK)))
2156 {
2157 rc = emR3ForcedActions(pVM, pVCpu, rc);
2158 VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
2159 if ( ( rc == VINF_EM_RESCHEDULE_REM
2160 || rc == VINF_EM_RESCHEDULE_HM)
2161 && pVCpu->em.s.fForceRAW)
2162 rc = VINF_EM_RESCHEDULE_RAW;
2163 }
2164 else if (fFFDone)
2165 fFFDone = false;
2166
2167 /*
2168 * Now what to do?
2169 */
2170 Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
2171 EMSTATE const enmOldState = pVCpu->em.s.enmState;
2172 switch (rc)
2173 {
2174 /*
2175 * Keep doing what we're currently doing.
2176 */
2177 case VINF_SUCCESS:
2178 break;
2179
2180 /*
2181 * Reschedule - to raw-mode execution.
2182 */
2183 case VINF_EM_RESCHEDULE_RAW:
2184 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", enmOldState, EMSTATE_RAW));
2185 Assert(!pVM->em.s.fIemExecutesAll || pVCpu->em.s.enmState != EMSTATE_IEM);
2186 pVCpu->em.s.enmState = EMSTATE_RAW;
2187 break;
2188
2189 /*
2190 * Reschedule - to hardware accelerated raw-mode execution.
2191 */
2192 case VINF_EM_RESCHEDULE_HM:
2193 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HM: %d -> %d (EMSTATE_HM)\n", enmOldState, EMSTATE_HM));
2194 Assert(!pVM->em.s.fIemExecutesAll || pVCpu->em.s.enmState != EMSTATE_IEM);
2195 Assert(!pVCpu->em.s.fForceRAW);
2196 pVCpu->em.s.enmState = EMSTATE_HM;
2197 break;
2198
2199 /*
2200 * Reschedule - to recompiled execution.
2201 */
2202 case VINF_EM_RESCHEDULE_REM:
2203#ifdef VBOX_WITH_FIRST_IEM_STEP
2204 Assert(!pVM->em.s.fIemExecutesAll || pVCpu->em.s.enmState != EMSTATE_IEM);
2205 if (HMIsEnabled(pVM))
2206 {
2207 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_IEM_THEN_REM)\n",
2208 enmOldState, EMSTATE_IEM_THEN_REM));
2209 if (pVCpu->em.s.enmState != EMSTATE_IEM_THEN_REM)
2210 {
2211 pVCpu->em.s.enmState = EMSTATE_IEM_THEN_REM;
2212 pVCpu->em.s.cIemThenRemInstructions = 0;
2213 }
2214 }
2215 else
2216 {
2217 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", enmOldState, EMSTATE_REM));
2218 pVCpu->em.s.enmState = EMSTATE_REM;
2219 }
2220#else
2221 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", enmOldState, EMSTATE_REM));
2222 Assert(!pVM->em.s.fIemExecutesAll || pVCpu->em.s.enmState != EMSTATE_IEM);
2223 pVCpu->em.s.enmState = EMSTATE_REM;
2224#endif
2225 break;
2226
2227 /*
2228 * Resume.
2229 */
2230 case VINF_EM_RESUME:
2231 Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", enmOldState));
2232 /* Don't reschedule in the halted or wait for SIPI case. */
2233 if ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
2234 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED)
2235 {
2236 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2237 break;
2238 }
2239 /* fall through and get scheduled. */
2240
2241 /*
2242 * Reschedule.
2243 */
2244 case VINF_EM_RESCHEDULE:
2245 {
2246 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
2247 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", enmOldState, enmState, emR3GetStateName(enmState)));
2248 if (pVCpu->em.s.enmState != enmState && enmState == EMSTATE_IEM_THEN_REM)
2249 pVCpu->em.s.cIemThenRemInstructions = 0;
2250 pVCpu->em.s.enmState = enmState;
2251 break;
2252 }
2253
2254 /*
2255 * Halted.
2256 */
2257 case VINF_EM_HALT:
2258 Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", enmOldState, EMSTATE_HALTED));
2259 pVCpu->em.s.enmState = EMSTATE_HALTED;
2260 break;
2261
2262 /*
2263 * Switch to the wait for SIPI state (application processor only)
2264 */
2265 case VINF_EM_WAIT_SIPI:
2266 Assert(pVCpu->idCpu != 0);
2267 Log2(("EMR3ExecuteVM: VINF_EM_WAIT_SIPI: %d -> %d\n", enmOldState, EMSTATE_WAIT_SIPI));
2268 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
2269 break;
2270
2271
2272 /*
2273 * Suspend.
2274 */
2275 case VINF_EM_SUSPEND:
2276 Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", enmOldState, EMSTATE_SUSPENDED));
2277 Assert(enmOldState != EMSTATE_SUSPENDED);
2278 pVCpu->em.s.enmPrevState = enmOldState;
2279 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2280 break;
2281
2282 /*
2283 * Reset.
2284 * We might end up doing a double reset for now, we'll have to clean up the mess later.
2285 */
2286 case VINF_EM_RESET:
2287 {
2288 if (pVCpu->idCpu == 0)
2289 {
2290 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
2291 Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", enmOldState, enmState, emR3GetStateName(enmState)));
2292 if (pVCpu->em.s.enmState != enmState && enmState == EMSTATE_IEM_THEN_REM)
2293 pVCpu->em.s.cIemThenRemInstructions = 0;
2294 pVCpu->em.s.enmState = enmState;
2295 }
2296 else
2297 {
2298 /* All other VCPUs go into the wait for SIPI state. */
2299 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
2300 }
2301 break;
2302 }
2303
2304 /*
2305 * Power Off.
2306 */
2307 case VINF_EM_OFF:
2308 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
2309 Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", enmOldState, EMSTATE_TERMINATING));
2310 TMR3NotifySuspend(pVM, pVCpu);
2311 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2312 return rc;
2313
2314 /*
2315 * Terminate the VM.
2316 */
2317 case VINF_EM_TERMINATE:
2318 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
2319 Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", enmOldState, EMSTATE_TERMINATING));
2320 if (pVM->enmVMState < VMSTATE_DESTROYING) /* ugly */
2321 TMR3NotifySuspend(pVM, pVCpu);
2322 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2323 return rc;
2324
2325
2326 /*
2327 * Out of memory, suspend the VM and stuff.
2328 */
2329 case VINF_EM_NO_MEMORY:
2330 Log2(("EMR3ExecuteVM: VINF_EM_NO_MEMORY: %d -> %d\n", enmOldState, EMSTATE_SUSPENDED));
2331 Assert(enmOldState != EMSTATE_SUSPENDED);
2332 pVCpu->em.s.enmPrevState = enmOldState;
2333 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2334 TMR3NotifySuspend(pVM, pVCpu);
2335 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2336
2337 rc = VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_SUSPEND, "HostMemoryLow",
2338 N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
2339 if (rc != VINF_EM_SUSPEND)
2340 {
2341 if (RT_SUCCESS_NP(rc))
2342 {
2343 AssertLogRelMsgFailed(("%Rrc\n", rc));
2344 rc = VERR_EM_INTERNAL_ERROR;
2345 }
2346 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2347 }
2348 return rc;
2349
2350 /*
2351 * Guest debug events.
2352 */
2353 case VINF_EM_DBG_STEPPED:
2354 case VINF_EM_DBG_STOP:
2355 case VINF_EM_DBG_BREAKPOINT:
2356 case VINF_EM_DBG_STEP:
2357 if (enmOldState == EMSTATE_RAW)
2358 {
2359 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_RAW));
2360 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
2361 }
2362 else if (enmOldState == EMSTATE_HM)
2363 {
2364 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_HM));
2365 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_HM;
2366 }
2367 else if (enmOldState == EMSTATE_REM)
2368 {
2369 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_REM));
2370 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
2371 }
2372 else
2373 {
2374 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_IEM));
2375 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_IEM;
2376 }
2377 break;
2378
2379 /*
2380 * Hypervisor debug events.
2381 */
2382 case VINF_EM_DBG_HYPER_STEPPED:
2383 case VINF_EM_DBG_HYPER_BREAKPOINT:
2384 case VINF_EM_DBG_HYPER_ASSERTION:
2385 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_HYPER));
2386 pVCpu->em.s.enmState = EMSTATE_DEBUG_HYPER;
2387 break;
2388
2389 /*
2390 * Triple fault.
2391 */
2392 case VINF_EM_TRIPLE_FAULT:
2393 if (!pVM->em.s.fGuruOnTripleFault)
2394 {
2395 Log(("EMR3ExecuteVM: VINF_EM_TRIPLE_FAULT: CPU reset...\n"));
2396 Assert(pVM->cCpus == 1);
2397 REMR3Reset(pVM);
2398 PGMR3ResetCpu(pVM, pVCpu);
2399 TRPMR3ResetCpu(pVCpu);
2400 CPUMR3ResetCpu(pVM, pVCpu);
2401 EMR3ResetCpu(pVCpu);
2402 HMR3ResetCpu(pVCpu);
2403 pVCpu->em.s.enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
2404 Log2(("EMR3ExecuteVM: VINF_EM_TRIPLE_FAULT: %d -> %d\n", rc, enmOldState, pVCpu->em.s.enmState));
2405 break;
2406 }
2407 /* Else fall through and trigger a guru. */
2408 case VERR_VMM_RING0_ASSERTION:
2409 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, enmOldState, EMSTATE_GURU_MEDITATION));
2410 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2411 break;
2412
2413 /*
2414 * Any error code showing up here other than the ones we
2415 * know and process above are considered to be FATAL.
2416 *
2417 * Unknown warnings and informational status codes are also
2418 * included in this.
2419 */
2420 default:
2421 if (RT_SUCCESS_NP(rc))
2422 {
2423 AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
2424 rc = VERR_EM_INTERNAL_ERROR;
2425 }
2426 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, enmOldState, EMSTATE_GURU_MEDITATION));
2427 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2428 break;
2429 }
2430
2431 /*
2432 * Act on state transition.
2433 */
2434 EMSTATE const enmNewState = pVCpu->em.s.enmState;
2435 if (enmOldState != enmNewState)
2436 {
2437 VBOXVMM_EM_STATE_CHANGED(pVCpu, enmOldState, enmNewState, rc);
2438
2439 /* Clear MWait flags. */
2440 if ( enmOldState == EMSTATE_HALTED
2441 && (pVCpu->em.s.MWait.fWait & EMMWAIT_FLAG_ACTIVE)
2442 && ( enmNewState == EMSTATE_RAW
2443 || enmNewState == EMSTATE_HM
2444 || enmNewState == EMSTATE_REM
2445 || enmNewState == EMSTATE_IEM_THEN_REM
2446 || enmNewState == EMSTATE_DEBUG_GUEST_RAW
2447 || enmNewState == EMSTATE_DEBUG_GUEST_HM
2448 || enmNewState == EMSTATE_DEBUG_GUEST_IEM
2449 || enmNewState == EMSTATE_DEBUG_GUEST_REM) )
2450 {
2451 LogFlow(("EMR3ExecuteVM: Clearing MWAIT\n"));
2452 pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0);
2453 }
2454 }
2455 else
2456 VBOXVMM_EM_STATE_UNCHANGED(pVCpu, enmNewState, rc);
2457
2458 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x); /* (skip this in release) */
2459 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2460
2461 /*
2462 * Act on the new state.
2463 */
2464 switch (enmNewState)
2465 {
2466 /*
2467 * Execute raw.
2468 */
2469 case EMSTATE_RAW:
2470#ifdef VBOX_WITH_RAW_MODE
2471 rc = emR3RawExecute(pVM, pVCpu, &fFFDone);
2472#else
2473 AssertLogRelMsgFailed(("%Rrc\n", rc));
2474 rc = VERR_EM_INTERNAL_ERROR;
2475#endif
2476 break;
2477
2478 /*
2479 * Execute hardware accelerated raw.
2480 */
2481 case EMSTATE_HM:
2482 rc = emR3HmExecute(pVM, pVCpu, &fFFDone);
2483 break;
2484
2485 /*
2486 * Execute recompiled.
2487 */
2488 case EMSTATE_REM:
2489 rc = emR3RemExecute(pVM, pVCpu, &fFFDone);
2490 Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
2491 break;
2492
2493 /*
2494 * Execute in the interpreter.
2495 */
2496 case EMSTATE_IEM:
2497 {
2498#if 0 /* For testing purposes. */
2499 STAM_PROFILE_START(&pVCpu->em.s.StatHmExec, x1);
2500 rc = VBOXSTRICTRC_TODO(EMR3HmSingleInstruction(pVM, pVCpu, EM_ONE_INS_FLAGS_RIP_CHANGE));
2501 STAM_PROFILE_STOP(&pVCpu->em.s.StatHmExec, x1);
2502 if (rc == VINF_EM_DBG_STEPPED || rc == VINF_EM_RESCHEDULE_HM || rc == VINF_EM_RESCHEDULE_REM || rc == VINF_EM_RESCHEDULE_RAW)
2503 rc = VINF_SUCCESS;
2504 else if (rc == VERR_EM_CANNOT_EXEC_GUEST)
2505#endif
2506 rc = VBOXSTRICTRC_TODO(IEMExecLots(pVCpu));
2507 if (pVM->em.s.fIemExecutesAll)
2508 {
2509 Assert(rc != VINF_EM_RESCHEDULE_REM);
2510 Assert(rc != VINF_EM_RESCHEDULE_RAW);
2511 Assert(rc != VINF_EM_RESCHEDULE_HM);
2512 }
2513 fFFDone = false;
2514 break;
2515 }
2516
2517 /*
2518 * Execute in IEM, hoping we can quickly switch aback to HM
2519 * or RAW execution. If our hopes fail, we go to REM.
2520 */
2521 case EMSTATE_IEM_THEN_REM:
2522 {
2523 STAM_PROFILE_START(&pVCpu->em.s.StatIEMThenREM, pIemThenRem);
2524 rc = VBOXSTRICTRC_TODO(emR3ExecuteIemThenRem(pVM, pVCpu, &fFFDone));
2525 STAM_PROFILE_STOP(&pVCpu->em.s.StatIEMThenREM, pIemThenRem);
2526 break;
2527 }
2528
2529 /*
2530 * Application processor execution halted until SIPI.
2531 */
2532 case EMSTATE_WAIT_SIPI:
2533 /* no break */
2534 /*
2535 * hlt - execution halted until interrupt.
2536 */
2537 case EMSTATE_HALTED:
2538 {
2539 STAM_REL_PROFILE_START(&pVCpu->em.s.StatHalted, y);
2540 /* If HM (or someone else) store a pending interrupt in
2541 TRPM, it must be dispatched ASAP without any halting.
2542 Anything pending in TRPM has been accepted and the CPU
2543 should already be the right state to receive it. */
2544 if (TRPMHasTrap(pVCpu))
2545 rc = VINF_EM_RESCHEDULE;
2546 /* MWAIT has a special extension where it's woken up when
2547 an interrupt is pending even when IF=0. */
2548 else if ( (pVCpu->em.s.MWait.fWait & (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0))
2549 == (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0))
2550 {
2551 rc = VMR3WaitHalted(pVM, pVCpu, false /*fIgnoreInterrupts*/);
2552 if ( rc == VINF_SUCCESS
2553 && VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC
2554 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI))
2555 {
2556 Log(("EMR3ExecuteVM: Triggering reschedule on pending IRQ after MWAIT\n"));
2557 rc = VINF_EM_RESCHEDULE;
2558 }
2559 }
2560 else
2561 {
2562 rc = VMR3WaitHalted(pVM, pVCpu, !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
2563 if ( rc == VINF_SUCCESS
2564 && VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI))
2565 {
2566 Log(("EMR3ExecuteVM: Triggering reschedule on pending NMI/SMI after HLT\n"));
2567 rc = VINF_EM_RESCHEDULE;
2568 }
2569 }
2570
2571 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHalted, y);
2572 break;
2573 }
2574
2575 /*
2576 * Suspended - return to VM.cpp.
2577 */
2578 case EMSTATE_SUSPENDED:
2579 TMR3NotifySuspend(pVM, pVCpu);
2580 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2581 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2582 return VINF_EM_SUSPEND;
2583
2584 /*
2585 * Debugging in the guest.
2586 */
2587 case EMSTATE_DEBUG_GUEST_RAW:
2588 case EMSTATE_DEBUG_GUEST_HM:
2589 case EMSTATE_DEBUG_GUEST_IEM:
2590 case EMSTATE_DEBUG_GUEST_REM:
2591 TMR3NotifySuspend(pVM, pVCpu);
2592 rc = VBOXSTRICTRC_TODO(emR3Debug(pVM, pVCpu, rc));
2593 TMR3NotifyResume(pVM, pVCpu);
2594 Log2(("EMR3ExecuteVM: emR3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2595 break;
2596
2597 /*
2598 * Debugging in the hypervisor.
2599 */
2600 case EMSTATE_DEBUG_HYPER:
2601 {
2602 TMR3NotifySuspend(pVM, pVCpu);
2603 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2604
2605 rc = VBOXSTRICTRC_TODO(emR3Debug(pVM, pVCpu, rc));
2606 Log2(("EMR3ExecuteVM: emR3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2607 if (rc != VINF_SUCCESS)
2608 {
2609 if (rc == VINF_EM_OFF || rc == VINF_EM_TERMINATE)
2610 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
2611 else
2612 {
2613 /* switch to guru meditation mode */
2614 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2615 VMMR3FatalDump(pVM, pVCpu, rc);
2616 }
2617 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2618 return rc;
2619 }
2620
2621 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2622 TMR3NotifyResume(pVM, pVCpu);
2623 break;
2624 }
2625
2626 /*
2627 * Guru meditation takes place in the debugger.
2628 */
2629 case EMSTATE_GURU_MEDITATION:
2630 {
2631 TMR3NotifySuspend(pVM, pVCpu);
2632 VMMR3FatalDump(pVM, pVCpu, rc);
2633 emR3Debug(pVM, pVCpu, rc);
2634 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2635 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2636 return rc;
2637 }
2638
2639 /*
2640 * The states we don't expect here.
2641 */
2642 case EMSTATE_NONE:
2643 case EMSTATE_TERMINATING:
2644 default:
2645 AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVCpu->em.s.enmState));
2646 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2647 TMR3NotifySuspend(pVM, pVCpu);
2648 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2649 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2650 return VERR_EM_INTERNAL_ERROR;
2651 }
2652 } /* The Outer Main Loop */
2653 }
2654 else
2655 {
2656 /*
2657 * Fatal error.
2658 */
2659 Log(("EMR3ExecuteVM: returns %Rrc because of longjmp / fatal error; (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2660 TMR3NotifySuspend(pVM, pVCpu);
2661 VMMR3FatalDump(pVM, pVCpu, rc);
2662 emR3Debug(pVM, pVCpu, rc);
2663 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2664 /** @todo change the VM state! */
2665 return rc;
2666 }
2667
2668 /* (won't ever get here). */
2669 AssertFailed();
2670}
2671
2672/**
2673 * Notify EM of a state change (used by FTM)
2674 *
2675 * @param pVM Pointer to the VM.
2676 */
2677VMMR3_INT_DECL(int) EMR3NotifySuspend(PVM pVM)
2678{
2679 PVMCPU pVCpu = VMMGetCpu(pVM);
2680
2681 TMR3NotifySuspend(pVM, pVCpu); /* Stop the virtual time. */
2682 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
2683 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2684 return VINF_SUCCESS;
2685}
2686
2687/**
2688 * Notify EM of a state change (used by FTM)
2689 *
2690 * @param pVM Pointer to the VM.
2691 */
2692VMMR3_INT_DECL(int) EMR3NotifyResume(PVM pVM)
2693{
2694 PVMCPU pVCpu = VMMGetCpu(pVM);
2695 EMSTATE enmCurState = pVCpu->em.s.enmState;
2696
2697 TMR3NotifyResume(pVM, pVCpu); /* Resume the virtual time. */
2698 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2699 pVCpu->em.s.enmPrevState = enmCurState;
2700 return VINF_SUCCESS;
2701}
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