EM.cpp@ 43346

Last change on this file since 43346 was 42698, checked in by vboxsync, 12 years ago
Flush the log on hyper assertion.
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1	/* $Id: EM.cpp 42698 2012-08-08 23:36:52Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_em EM - The Execution Monitor / Manager
19	*
20	* The Execution Monitor/Manager is responsible for running the VM, scheduling
21	* the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
22	* Interpreted), and keeping the CPU states in sync. The function
23	* EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
24	* modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
25	* emR3RemExecute).
26	*
27	* The interpreted execution is only used to avoid switching between
28	* raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
29	* The interpretation is thus implemented as part of EM.
30	*
31	* @see grp_em
32	*/
33
34	/*******************************************************************************
35	* Header Files *
36	*******************************************************************************/
37	#define LOG_GROUP LOG_GROUP_EM
38	#include <VBox/vmm/em.h>
39	#include <VBox/vmm/vmm.h>
40	#include <VBox/vmm/patm.h>
41	#include <VBox/vmm/csam.h>
42	#include <VBox/vmm/selm.h>
43	#include <VBox/vmm/trpm.h>
44	#include <VBox/vmm/iom.h>
45	#include <VBox/vmm/dbgf.h>
46	#include <VBox/vmm/pgm.h>
47	#ifdef VBOX_WITH_REM
48	# include <VBox/vmm/rem.h>
49	#else
50	# include <VBox/vmm/iem.h>
51	#endif
52	#include <VBox/vmm/tm.h>
53	#include <VBox/vmm/mm.h>
54	#include <VBox/vmm/ssm.h>
55	#include <VBox/vmm/pdmapi.h>
56	#include <VBox/vmm/pdmcritsect.h>
57	#include <VBox/vmm/pdmqueue.h>
58	#include <VBox/vmm/hwaccm.h>
59	#include <VBox/vmm/patm.h>
60	#ifdef IEM_VERIFICATION_MODE
61	# include <VBox/vmm/iem.h>
62	#endif
63	#include "EMInternal.h"
64	#include "internal/em.h"
65	#include <VBox/vmm/vm.h>
66	#include <VBox/vmm/cpumdis.h>
67	#include <VBox/dis.h>
68	#include <VBox/disopcode.h>
69	#include <VBox/vmm/dbgf.h>
70	#include "VMMTracing.h"
71
72	#include <iprt/asm.h>
73	#include <iprt/string.h>
74	#include <iprt/stream.h>
75	#include <iprt/thread.h>
76
77
78	/*******************************************************************************
79	* Defined Constants And Macros *
80	*******************************************************************************/
81	#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
82	#define EM_NOTIFY_HWACCM
83	#endif
84
85
86	/*******************************************************************************
87	* Internal Functions *
88	*******************************************************************************/
89	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
90	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
91	#if defined(LOG_ENABLED) \|\| defined(VBOX_STRICT)
92	static const char *emR3GetStateName(EMSTATE enmState);
93	#endif
94	static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc);
95	static int emR3RemStep(PVM pVM, PVMCPU pVCpu);
96	static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
97	int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
98
99
100	/**
101	* Initializes the EM.
102	*
103	* @returns VBox status code.
104	* @param pVM Pointer to the VM.
105	*/
106	VMMR3DECL(int) EMR3Init(PVM pVM)
107	{
108	LogFlow(("EMR3Init\n"));
109	/*
110	* Assert alignment and sizes.
111	*/
112	AssertCompileMemberAlignment(VM, em.s, 32);
113	AssertCompile(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
114	AssertCompile(sizeof(pVM->aCpus[0].em.s.u.FatalLongJump) <= sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump));
115
116	/*
117	* Init the structure.
118	*/
119	pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
120	bool fEnabled;
121	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &fEnabled);
122	pVM->fRecompileUser = RT_SUCCESS(rc) ? !fEnabled : false;
123	rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &fEnabled);
124	pVM->fRecompileSupervisor = RT_SUCCESS(rc) ? !fEnabled : false;
125	Log(("EMR3Init: fRecompileUser=%RTbool fRecompileSupervisor=%RTbool\n", pVM->fRecompileUser, pVM->fRecompileSupervisor));
126
127	#ifdef VBOX_WITH_REM
128	/*
129	* Initialize the REM critical section.
130	*/
131	AssertCompileMemberAlignment(EM, CritSectREM, sizeof(uintptr_t));
132	rc = PDMR3CritSectInit(pVM, &pVM->em.s.CritSectREM, RT_SRC_POS, "EM-REM");
133	AssertRCReturn(rc, rc);
134	#endif
135
136	/*
137	* Saved state.
138	*/
139	rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
140	NULL, NULL, NULL,
141	NULL, emR3Save, NULL,
142	NULL, emR3Load, NULL);
143	if (RT_FAILURE(rc))
144	return rc;
145
146	for (VMCPUID i = 0; i < pVM->cCpus; i++)
147	{
148	PVMCPU pVCpu = &pVM->aCpus[i];
149
150	pVCpu->em.s.offVMCPU = RT_OFFSETOF(VMCPU, em.s);
151
152	pVCpu->em.s.enmState = (i == 0) ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
153	pVCpu->em.s.enmPrevState = EMSTATE_NONE;
154	pVCpu->em.s.fForceRAW = false;
155
156	pVCpu->em.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
157	pVCpu->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
158	AssertMsg(pVCpu->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
159
160	/* Force reset of the time slice. */
161	pVCpu->em.s.u64TimeSliceStart = 0;
162
163	# define EM_REG_COUNTER(a, b, c) \
164	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
165	AssertRC(rc);
166
167	# define EM_REG_COUNTER_USED(a, b, c) \
168	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, c, b, i); \
169	AssertRC(rc);
170
171	# define EM_REG_PROFILE(a, b, c) \
172	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
173	AssertRC(rc);
174
175	# define EM_REG_PROFILE_ADV(a, b, c) \
176	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
177	AssertRC(rc);
178
179	/*
180	* Statistics.
181	*/
182	#ifdef VBOX_WITH_STATISTICS
183	PEMSTATS pStats;
184	rc = MMHyperAlloc(pVM, sizeof(pStats), 0, MM_TAG_EM, (void *)&pStats);
185	if (RT_FAILURE(rc))
186	return rc;
187
188	pVCpu->em.s.pStatsR3 = pStats;
189	pVCpu->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
190	pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
191
192	EM_REG_PROFILE(&pStats->StatRZEmulate, "/EM/CPU%d/RZ/Interpret", "Profiling of EMInterpretInstruction.");
193	EM_REG_PROFILE(&pStats->StatR3Emulate, "/EM/CPU%d/R3/Interpret", "Profiling of EMInterpretInstruction.");
194
195	EM_REG_PROFILE(&pStats->StatRZInterpretSucceeded, "/EM/CPU%d/RZ/Interpret/Success", "The number of times an instruction was successfully interpreted.");
196	EM_REG_PROFILE(&pStats->StatR3InterpretSucceeded, "/EM/CPU%d/R3/Interpret/Success", "The number of times an instruction was successfully interpreted.");
197
198	EM_REG_COUNTER_USED(&pStats->StatRZAnd, "/EM/CPU%d/RZ/Interpret/Success/And", "The number of times AND was successfully interpreted.");
199	EM_REG_COUNTER_USED(&pStats->StatR3And, "/EM/CPU%d/R3/Interpret/Success/And", "The number of times AND was successfully interpreted.");
200	EM_REG_COUNTER_USED(&pStats->StatRZAdd, "/EM/CPU%d/RZ/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
201	EM_REG_COUNTER_USED(&pStats->StatR3Add, "/EM/CPU%d/R3/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
202	EM_REG_COUNTER_USED(&pStats->StatRZAdc, "/EM/CPU%d/RZ/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
203	EM_REG_COUNTER_USED(&pStats->StatR3Adc, "/EM/CPU%d/R3/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
204	EM_REG_COUNTER_USED(&pStats->StatRZSub, "/EM/CPU%d/RZ/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
205	EM_REG_COUNTER_USED(&pStats->StatR3Sub, "/EM/CPU%d/R3/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
206	EM_REG_COUNTER_USED(&pStats->StatRZCpuId, "/EM/CPU%d/RZ/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
207	EM_REG_COUNTER_USED(&pStats->StatR3CpuId, "/EM/CPU%d/R3/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
208	EM_REG_COUNTER_USED(&pStats->StatRZDec, "/EM/CPU%d/RZ/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
209	EM_REG_COUNTER_USED(&pStats->StatR3Dec, "/EM/CPU%d/R3/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
210	EM_REG_COUNTER_USED(&pStats->StatRZHlt, "/EM/CPU%d/RZ/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
211	EM_REG_COUNTER_USED(&pStats->StatR3Hlt, "/EM/CPU%d/R3/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
212	EM_REG_COUNTER_USED(&pStats->StatRZInc, "/EM/CPU%d/RZ/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
213	EM_REG_COUNTER_USED(&pStats->StatR3Inc, "/EM/CPU%d/R3/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
214	EM_REG_COUNTER_USED(&pStats->StatRZInvlPg, "/EM/CPU%d/RZ/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
215	EM_REG_COUNTER_USED(&pStats->StatR3InvlPg, "/EM/CPU%d/R3/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
216	EM_REG_COUNTER_USED(&pStats->StatRZIret, "/EM/CPU%d/RZ/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
217	EM_REG_COUNTER_USED(&pStats->StatR3Iret, "/EM/CPU%d/R3/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
218	EM_REG_COUNTER_USED(&pStats->StatRZLLdt, "/EM/CPU%d/RZ/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
219	EM_REG_COUNTER_USED(&pStats->StatR3LLdt, "/EM/CPU%d/R3/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
220	EM_REG_COUNTER_USED(&pStats->StatRZLIdt, "/EM/CPU%d/RZ/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
221	EM_REG_COUNTER_USED(&pStats->StatR3LIdt, "/EM/CPU%d/R3/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
222	EM_REG_COUNTER_USED(&pStats->StatRZLGdt, "/EM/CPU%d/RZ/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
223	EM_REG_COUNTER_USED(&pStats->StatR3LGdt, "/EM/CPU%d/R3/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
224	EM_REG_COUNTER_USED(&pStats->StatRZMov, "/EM/CPU%d/RZ/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
225	EM_REG_COUNTER_USED(&pStats->StatR3Mov, "/EM/CPU%d/R3/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
226	EM_REG_COUNTER_USED(&pStats->StatRZMovCRx, "/EM/CPU%d/RZ/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
227	EM_REG_COUNTER_USED(&pStats->StatR3MovCRx, "/EM/CPU%d/R3/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
228	EM_REG_COUNTER_USED(&pStats->StatRZMovDRx, "/EM/CPU%d/RZ/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
229	EM_REG_COUNTER_USED(&pStats->StatR3MovDRx, "/EM/CPU%d/R3/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
230	EM_REG_COUNTER_USED(&pStats->StatRZOr, "/EM/CPU%d/RZ/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
231	EM_REG_COUNTER_USED(&pStats->StatR3Or, "/EM/CPU%d/R3/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
232	EM_REG_COUNTER_USED(&pStats->StatRZPop, "/EM/CPU%d/RZ/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
233	EM_REG_COUNTER_USED(&pStats->StatR3Pop, "/EM/CPU%d/R3/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
234	EM_REG_COUNTER_USED(&pStats->StatRZRdtsc, "/EM/CPU%d/RZ/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
235	EM_REG_COUNTER_USED(&pStats->StatR3Rdtsc, "/EM/CPU%d/R3/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
236	EM_REG_COUNTER_USED(&pStats->StatRZRdpmc, "/EM/CPU%d/RZ/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
237	EM_REG_COUNTER_USED(&pStats->StatR3Rdpmc, "/EM/CPU%d/R3/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
238	EM_REG_COUNTER_USED(&pStats->StatRZSti, "/EM/CPU%d/RZ/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
239	EM_REG_COUNTER_USED(&pStats->StatR3Sti, "/EM/CPU%d/R3/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
240	EM_REG_COUNTER_USED(&pStats->StatRZXchg, "/EM/CPU%d/RZ/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
241	EM_REG_COUNTER_USED(&pStats->StatR3Xchg, "/EM/CPU%d/R3/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
242	EM_REG_COUNTER_USED(&pStats->StatRZXor, "/EM/CPU%d/RZ/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
243	EM_REG_COUNTER_USED(&pStats->StatR3Xor, "/EM/CPU%d/R3/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
244	EM_REG_COUNTER_USED(&pStats->StatRZMonitor, "/EM/CPU%d/RZ/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
245	EM_REG_COUNTER_USED(&pStats->StatR3Monitor, "/EM/CPU%d/R3/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
246	EM_REG_COUNTER_USED(&pStats->StatRZMWait, "/EM/CPU%d/RZ/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
247	EM_REG_COUNTER_USED(&pStats->StatR3MWait, "/EM/CPU%d/R3/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
248	EM_REG_COUNTER_USED(&pStats->StatRZBtr, "/EM/CPU%d/RZ/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
249	EM_REG_COUNTER_USED(&pStats->StatR3Btr, "/EM/CPU%d/R3/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
250	EM_REG_COUNTER_USED(&pStats->StatRZBts, "/EM/CPU%d/RZ/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
251	EM_REG_COUNTER_USED(&pStats->StatR3Bts, "/EM/CPU%d/R3/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
252	EM_REG_COUNTER_USED(&pStats->StatRZBtc, "/EM/CPU%d/RZ/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
253	EM_REG_COUNTER_USED(&pStats->StatR3Btc, "/EM/CPU%d/R3/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
254	EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
255	EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg, "/EM/CPU%d/R3/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
256	EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
257	EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg8b, "/EM/CPU%d/R3/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
258	EM_REG_COUNTER_USED(&pStats->StatRZXAdd, "/EM/CPU%d/RZ/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
259	EM_REG_COUNTER_USED(&pStats->StatR3XAdd, "/EM/CPU%d/R3/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
260	EM_REG_COUNTER_USED(&pStats->StatR3Rdmsr, "/EM/CPU%d/R3/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
261	EM_REG_COUNTER_USED(&pStats->StatRZRdmsr, "/EM/CPU%d/RZ/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
262	EM_REG_COUNTER_USED(&pStats->StatR3Wrmsr, "/EM/CPU%d/R3/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
263	EM_REG_COUNTER_USED(&pStats->StatRZWrmsr, "/EM/CPU%d/RZ/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
264	EM_REG_COUNTER_USED(&pStats->StatR3StosWD, "/EM/CPU%d/R3/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
265	EM_REG_COUNTER_USED(&pStats->StatRZStosWD, "/EM/CPU%d/RZ/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
266	EM_REG_COUNTER_USED(&pStats->StatRZWbInvd, "/EM/CPU%d/RZ/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
267	EM_REG_COUNTER_USED(&pStats->StatR3WbInvd, "/EM/CPU%d/R3/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
268	EM_REG_COUNTER_USED(&pStats->StatRZLmsw, "/EM/CPU%d/RZ/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
269	EM_REG_COUNTER_USED(&pStats->StatR3Lmsw, "/EM/CPU%d/R3/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
270
271	EM_REG_COUNTER(&pStats->StatRZInterpretFailed, "/EM/CPU%d/RZ/Interpret/Failed", "The number of times an instruction was not interpreted.");
272	EM_REG_COUNTER(&pStats->StatR3InterpretFailed, "/EM/CPU%d/R3/Interpret/Failed", "The number of times an instruction was not interpreted.");
273
274	EM_REG_COUNTER_USED(&pStats->StatRZFailedAnd, "/EM/CPU%d/RZ/Interpret/Failed/And", "The number of times AND was not interpreted.");
275	EM_REG_COUNTER_USED(&pStats->StatR3FailedAnd, "/EM/CPU%d/R3/Interpret/Failed/And", "The number of times AND was not interpreted.");
276	EM_REG_COUNTER_USED(&pStats->StatRZFailedCpuId, "/EM/CPU%d/RZ/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
277	EM_REG_COUNTER_USED(&pStats->StatR3FailedCpuId, "/EM/CPU%d/R3/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
278	EM_REG_COUNTER_USED(&pStats->StatRZFailedDec, "/EM/CPU%d/RZ/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
279	EM_REG_COUNTER_USED(&pStats->StatR3FailedDec, "/EM/CPU%d/R3/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
280	EM_REG_COUNTER_USED(&pStats->StatRZFailedHlt, "/EM/CPU%d/RZ/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
281	EM_REG_COUNTER_USED(&pStats->StatR3FailedHlt, "/EM/CPU%d/R3/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
282	EM_REG_COUNTER_USED(&pStats->StatRZFailedInc, "/EM/CPU%d/RZ/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
283	EM_REG_COUNTER_USED(&pStats->StatR3FailedInc, "/EM/CPU%d/R3/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
284	EM_REG_COUNTER_USED(&pStats->StatRZFailedInvlPg, "/EM/CPU%d/RZ/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
285	EM_REG_COUNTER_USED(&pStats->StatR3FailedInvlPg, "/EM/CPU%d/R3/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
286	EM_REG_COUNTER_USED(&pStats->StatRZFailedIret, "/EM/CPU%d/RZ/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
287	EM_REG_COUNTER_USED(&pStats->StatR3FailedIret, "/EM/CPU%d/R3/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
288	EM_REG_COUNTER_USED(&pStats->StatRZFailedLLdt, "/EM/CPU%d/RZ/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
289	EM_REG_COUNTER_USED(&pStats->StatR3FailedLLdt, "/EM/CPU%d/R3/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
290	EM_REG_COUNTER_USED(&pStats->StatRZFailedLIdt, "/EM/CPU%d/RZ/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
291	EM_REG_COUNTER_USED(&pStats->StatR3FailedLIdt, "/EM/CPU%d/R3/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
292	EM_REG_COUNTER_USED(&pStats->StatRZFailedLGdt, "/EM/CPU%d/RZ/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
293	EM_REG_COUNTER_USED(&pStats->StatR3FailedLGdt, "/EM/CPU%d/R3/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
294	EM_REG_COUNTER_USED(&pStats->StatRZFailedMov, "/EM/CPU%d/RZ/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
295	EM_REG_COUNTER_USED(&pStats->StatR3FailedMov, "/EM/CPU%d/R3/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
296	EM_REG_COUNTER_USED(&pStats->StatRZFailedMovCRx, "/EM/CPU%d/RZ/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
297	EM_REG_COUNTER_USED(&pStats->StatR3FailedMovCRx, "/EM/CPU%d/R3/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
298	EM_REG_COUNTER_USED(&pStats->StatRZFailedMovDRx, "/EM/CPU%d/RZ/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
299	EM_REG_COUNTER_USED(&pStats->StatR3FailedMovDRx, "/EM/CPU%d/R3/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
300	EM_REG_COUNTER_USED(&pStats->StatRZFailedOr, "/EM/CPU%d/RZ/Interpret/Failed/Or", "The number of times OR was not interpreted.");
301	EM_REG_COUNTER_USED(&pStats->StatR3FailedOr, "/EM/CPU%d/R3/Interpret/Failed/Or", "The number of times OR was not interpreted.");
302	EM_REG_COUNTER_USED(&pStats->StatRZFailedPop, "/EM/CPU%d/RZ/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
303	EM_REG_COUNTER_USED(&pStats->StatR3FailedPop, "/EM/CPU%d/R3/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
304	EM_REG_COUNTER_USED(&pStats->StatRZFailedSti, "/EM/CPU%d/RZ/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
305	EM_REG_COUNTER_USED(&pStats->StatR3FailedSti, "/EM/CPU%d/R3/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
306	EM_REG_COUNTER_USED(&pStats->StatRZFailedXchg, "/EM/CPU%d/RZ/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
307	EM_REG_COUNTER_USED(&pStats->StatR3FailedXchg, "/EM/CPU%d/R3/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
308	EM_REG_COUNTER_USED(&pStats->StatRZFailedXor, "/EM/CPU%d/RZ/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
309	EM_REG_COUNTER_USED(&pStats->StatR3FailedXor, "/EM/CPU%d/R3/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
310	EM_REG_COUNTER_USED(&pStats->StatRZFailedMonitor, "/EM/CPU%d/RZ/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
311	EM_REG_COUNTER_USED(&pStats->StatR3FailedMonitor, "/EM/CPU%d/R3/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
312	EM_REG_COUNTER_USED(&pStats->StatRZFailedMWait, "/EM/CPU%d/RZ/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
313	EM_REG_COUNTER_USED(&pStats->StatR3FailedMWait, "/EM/CPU%d/R3/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
314	EM_REG_COUNTER_USED(&pStats->StatRZFailedRdtsc, "/EM/CPU%d/RZ/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
315	EM_REG_COUNTER_USED(&pStats->StatR3FailedRdtsc, "/EM/CPU%d/R3/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
316	EM_REG_COUNTER_USED(&pStats->StatRZFailedRdpmc, "/EM/CPU%d/RZ/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
317	EM_REG_COUNTER_USED(&pStats->StatR3FailedRdpmc, "/EM/CPU%d/R3/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
318	EM_REG_COUNTER_USED(&pStats->StatRZFailedRdmsr, "/EM/CPU%d/RZ/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
319	EM_REG_COUNTER_USED(&pStats->StatR3FailedRdmsr, "/EM/CPU%d/R3/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
320	EM_REG_COUNTER_USED(&pStats->StatRZFailedWrmsr, "/EM/CPU%d/RZ/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
321	EM_REG_COUNTER_USED(&pStats->StatR3FailedWrmsr, "/EM/CPU%d/R3/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
322	EM_REG_COUNTER_USED(&pStats->StatRZFailedLmsw, "/EM/CPU%d/RZ/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
323	EM_REG_COUNTER_USED(&pStats->StatR3FailedLmsw, "/EM/CPU%d/R3/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
324
325	EM_REG_COUNTER_USED(&pStats->StatRZFailedMisc, "/EM/CPU%d/RZ/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
326	EM_REG_COUNTER_USED(&pStats->StatR3FailedMisc, "/EM/CPU%d/R3/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
327	EM_REG_COUNTER_USED(&pStats->StatRZFailedAdd, "/EM/CPU%d/RZ/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
328	EM_REG_COUNTER_USED(&pStats->StatR3FailedAdd, "/EM/CPU%d/R3/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
329	EM_REG_COUNTER_USED(&pStats->StatRZFailedAdc, "/EM/CPU%d/RZ/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
330	EM_REG_COUNTER_USED(&pStats->StatR3FailedAdc, "/EM/CPU%d/R3/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
331	EM_REG_COUNTER_USED(&pStats->StatRZFailedBtr, "/EM/CPU%d/RZ/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
332	EM_REG_COUNTER_USED(&pStats->StatR3FailedBtr, "/EM/CPU%d/R3/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
333	EM_REG_COUNTER_USED(&pStats->StatRZFailedBts, "/EM/CPU%d/RZ/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
334	EM_REG_COUNTER_USED(&pStats->StatR3FailedBts, "/EM/CPU%d/R3/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
335	EM_REG_COUNTER_USED(&pStats->StatRZFailedBtc, "/EM/CPU%d/RZ/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
336	EM_REG_COUNTER_USED(&pStats->StatR3FailedBtc, "/EM/CPU%d/R3/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
337	EM_REG_COUNTER_USED(&pStats->StatRZFailedCli, "/EM/CPU%d/RZ/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
338	EM_REG_COUNTER_USED(&pStats->StatR3FailedCli, "/EM/CPU%d/R3/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
339	EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
340	EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
341	EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
342	EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg8b, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
343	EM_REG_COUNTER_USED(&pStats->StatRZFailedXAdd, "/EM/CPU%d/RZ/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
344	EM_REG_COUNTER_USED(&pStats->StatR3FailedXAdd, "/EM/CPU%d/R3/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
345	EM_REG_COUNTER_USED(&pStats->StatRZFailedMovNTPS, "/EM/CPU%d/RZ/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
346	EM_REG_COUNTER_USED(&pStats->StatR3FailedMovNTPS, "/EM/CPU%d/R3/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
347	EM_REG_COUNTER_USED(&pStats->StatRZFailedStosWD, "/EM/CPU%d/RZ/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
348	EM_REG_COUNTER_USED(&pStats->StatR3FailedStosWD, "/EM/CPU%d/R3/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
349	EM_REG_COUNTER_USED(&pStats->StatRZFailedSub, "/EM/CPU%d/RZ/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
350	EM_REG_COUNTER_USED(&pStats->StatR3FailedSub, "/EM/CPU%d/R3/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
351	EM_REG_COUNTER_USED(&pStats->StatRZFailedWbInvd, "/EM/CPU%d/RZ/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
352	EM_REG_COUNTER_USED(&pStats->StatR3FailedWbInvd, "/EM/CPU%d/R3/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
353
354	EM_REG_COUNTER_USED(&pStats->StatRZFailedUserMode, "/EM/CPU%d/RZ/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
355	EM_REG_COUNTER_USED(&pStats->StatR3FailedUserMode, "/EM/CPU%d/R3/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
356	EM_REG_COUNTER_USED(&pStats->StatRZFailedPrefix, "/EM/CPU%d/RZ/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
357	EM_REG_COUNTER_USED(&pStats->StatR3FailedPrefix, "/EM/CPU%d/R3/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
358
359	EM_REG_COUNTER_USED(&pStats->StatCli, "/EM/CPU%d/R3/PrivInst/Cli", "Number of cli instructions.");
360	EM_REG_COUNTER_USED(&pStats->StatSti, "/EM/CPU%d/R3/PrivInst/Sti", "Number of sli instructions.");
361	EM_REG_COUNTER_USED(&pStats->StatIn, "/EM/CPU%d/R3/PrivInst/In", "Number of in instructions.");
362	EM_REG_COUNTER_USED(&pStats->StatOut, "/EM/CPU%d/R3/PrivInst/Out", "Number of out instructions.");
363	EM_REG_COUNTER_USED(&pStats->StatIoRestarted, "/EM/CPU%d/R3/PrivInst/IoRestarted", "Number of restarted i/o instructions.");
364	EM_REG_COUNTER_USED(&pStats->StatHlt, "/EM/CPU%d/R3/PrivInst/Hlt", "Number of hlt instructions not handled in GC because of PATM.");
365	EM_REG_COUNTER_USED(&pStats->StatInvlpg, "/EM/CPU%d/R3/PrivInst/Invlpg", "Number of invlpg instructions.");
366	EM_REG_COUNTER_USED(&pStats->StatMisc, "/EM/CPU%d/R3/PrivInst/Misc", "Number of misc. instructions.");
367	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[0], "/EM/CPU%d/R3/PrivInst/Mov CR0, X", "Number of mov CR0 write instructions.");
368	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[1], "/EM/CPU%d/R3/PrivInst/Mov CR1, X", "Number of mov CR1 write instructions.");
369	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[2], "/EM/CPU%d/R3/PrivInst/Mov CR2, X", "Number of mov CR2 write instructions.");
370	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[3], "/EM/CPU%d/R3/PrivInst/Mov CR3, X", "Number of mov CR3 write instructions.");
371	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[4], "/EM/CPU%d/R3/PrivInst/Mov CR4, X", "Number of mov CR4 write instructions.");
372	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[0], "/EM/CPU%d/R3/PrivInst/Mov X, CR0", "Number of mov CR0 read instructions.");
373	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[1], "/EM/CPU%d/R3/PrivInst/Mov X, CR1", "Number of mov CR1 read instructions.");
374	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[2], "/EM/CPU%d/R3/PrivInst/Mov X, CR2", "Number of mov CR2 read instructions.");
375	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[3], "/EM/CPU%d/R3/PrivInst/Mov X, CR3", "Number of mov CR3 read instructions.");
376	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[4], "/EM/CPU%d/R3/PrivInst/Mov X, CR4", "Number of mov CR4 read instructions.");
377	EM_REG_COUNTER_USED(&pStats->StatMovDRx, "/EM/CPU%d/R3/PrivInst/MovDRx", "Number of mov DRx instructions.");
378	EM_REG_COUNTER_USED(&pStats->StatIret, "/EM/CPU%d/R3/PrivInst/Iret", "Number of iret instructions.");
379	EM_REG_COUNTER_USED(&pStats->StatMovLgdt, "/EM/CPU%d/R3/PrivInst/Lgdt", "Number of lgdt instructions.");
380	EM_REG_COUNTER_USED(&pStats->StatMovLidt, "/EM/CPU%d/R3/PrivInst/Lidt", "Number of lidt instructions.");
381	EM_REG_COUNTER_USED(&pStats->StatMovLldt, "/EM/CPU%d/R3/PrivInst/Lldt", "Number of lldt instructions.");
382	EM_REG_COUNTER_USED(&pStats->StatSysEnter, "/EM/CPU%d/R3/PrivInst/Sysenter", "Number of sysenter instructions.");
383	EM_REG_COUNTER_USED(&pStats->StatSysExit, "/EM/CPU%d/R3/PrivInst/Sysexit", "Number of sysexit instructions.");
384	EM_REG_COUNTER_USED(&pStats->StatSysCall, "/EM/CPU%d/R3/PrivInst/Syscall", "Number of syscall instructions.");
385	EM_REG_COUNTER_USED(&pStats->StatSysRet, "/EM/CPU%d/R3/PrivInst/Sysret", "Number of sysret instructions.");
386
387	EM_REG_COUNTER(&pVCpu->em.s.StatTotalClis, "/EM/CPU%d/Cli/Total", "Total number of cli instructions executed.");
388	pVCpu->em.s.pCliStatTree = 0;
389
390	/* these should be considered for release statistics. */
391	EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%d/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction.");
392	EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%d/EM/Emulation/Priv", "Profiling of emR3RawPrivileged.");
393	EM_REG_PROFILE(&pVCpu->em.s.StatHwAccEntry, "/PROF/CPU%d/EM/HwAccEnter", "Profiling Hardware Accelerated Mode entry overhead.");
394	EM_REG_PROFILE(&pVCpu->em.s.StatHwAccExec, "/PROF/CPU%d/EM/HwAccExec", "Profiling Hardware Accelerated Mode execution.");
395	EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%d/EM/REMEmuSingle", "Profiling single instruction REM execution.");
396	EM_REG_PROFILE(&pVCpu->em.s.StatREMExec, "/PROF/CPU%d/EM/REMExec", "Profiling REM execution.");
397	EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%d/EM/REMSync", "Profiling REM context syncing.");
398	EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%d/EM/RAWEnter", "Profiling Raw Mode entry overhead.");
399	EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%d/EM/RAWExec", "Profiling Raw Mode execution.");
400	EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%d/EM/RAWTail", "Profiling Raw Mode tail overhead.");
401
402	#endif /* VBOX_WITH_STATISTICS */
403
404	EM_REG_COUNTER(&pVCpu->em.s.StatForcedActions, "/PROF/CPU%d/EM/ForcedActions", "Profiling forced action execution.");
405	EM_REG_COUNTER(&pVCpu->em.s.StatHalted, "/PROF/CPU%d/EM/Halted", "Profiling halted state (VMR3WaitHalted).");
406	EM_REG_PROFILE_ADV(&pVCpu->em.s.StatCapped, "/PROF/CPU%d/EM/Capped", "Profiling capped state (sleep).");
407	EM_REG_COUNTER(&pVCpu->em.s.StatREMTotal, "/PROF/CPU%d/EM/REMTotal", "Profiling emR3RemExecute (excluding FFs).");
408	EM_REG_COUNTER(&pVCpu->em.s.StatRAWTotal, "/PROF/CPU%d/EM/RAWTotal", "Profiling emR3RawExecute (excluding FFs).");
409
410	EM_REG_PROFILE_ADV(&pVCpu->em.s.StatTotal, "/PROF/CPU%d/EM/Total", "Profiling EMR3ExecuteVM.");
411	}
412
413	return VINF_SUCCESS;
414	}
415
416
417	/**
418	* Applies relocations to data and code managed by this
419	* component. This function will be called at init and
420	* whenever the VMM need to relocate it self inside the GC.
421	*
422	* @param pVM Pointer to the VM.
423	*/
424	VMMR3DECL(void) EMR3Relocate(PVM pVM)
425	{
426	LogFlow(("EMR3Relocate\n"));
427	for (VMCPUID i = 0; i < pVM->cCpus; i++)
428	{
429	PVMCPU pVCpu = &pVM->aCpus[i];
430	if (pVCpu->em.s.pStatsR3)
431	pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVCpu->em.s.pStatsR3);
432	}
433	}
434
435
436	/**
437	* Reset the EM state for a CPU.
438	*
439	* Called by EMR3Reset and hot plugging.
440	*
441	* @param pVCpu Pointer to the VMCPU.
442	*/
443	VMMR3DECL(void) EMR3ResetCpu(PVMCPU pVCpu)
444	{
445	pVCpu->em.s.fForceRAW = false;
446
447	/* VMR3Reset may return VINF_EM_RESET or VINF_EM_SUSPEND, so transition
448	out of the HALTED state here so that enmPrevState doesn't end up as
449	HALTED when EMR3Execute returns. */
450	if (pVCpu->em.s.enmState == EMSTATE_HALTED)
451	{
452	Log(("EMR3ResetCpu: Cpu#%u %s -> %s\n", pVCpu->idCpu, emR3GetStateName(pVCpu->em.s.enmState), pVCpu->idCpu == 0 ? "EMSTATE_NONE" : "EMSTATE_WAIT_SIPI"));
453	pVCpu->em.s.enmState = pVCpu->idCpu == 0 ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
454	}
455	}
456
457
458	/**
459	* Reset notification.
460	*
461	* @param pVM Pointer to the VM.
462	*/
463	VMMR3DECL(void) EMR3Reset(PVM pVM)
464	{
465	Log(("EMR3Reset: \n"));
466	for (VMCPUID i = 0; i < pVM->cCpus; i++)
467	EMR3ResetCpu(&pVM->aCpus[i]);
468	}
469
470
471	/**
472	* Terminates the EM.
473	*
474	* Termination means cleaning up and freeing all resources,
475	* the VM it self is at this point powered off or suspended.
476	*
477	* @returns VBox status code.
478	* @param pVM Pointer to the VM.
479	*/
480	VMMR3DECL(int) EMR3Term(PVM pVM)
481	{
482	AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
483
484	#ifdef VBOX_WITH_REM
485	PDMR3CritSectDelete(&pVM->em.s.CritSectREM);
486	#endif
487	return VINF_SUCCESS;
488	}
489
490
491	/**
492	* Execute state save operation.
493	*
494	* @returns VBox status code.
495	* @param pVM Pointer to the VM.
496	* @param pSSM SSM operation handle.
497	*/
498	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
499	{
500	for (VMCPUID i = 0; i < pVM->cCpus; i++)
501	{
502	PVMCPU pVCpu = &pVM->aCpus[i];
503
504	int rc = SSMR3PutBool(pSSM, pVCpu->em.s.fForceRAW);
505	AssertRCReturn(rc, rc);
506
507	Assert(pVCpu->em.s.enmState == EMSTATE_SUSPENDED);
508	Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
509	rc = SSMR3PutU32(pSSM, pVCpu->em.s.enmPrevState);
510	AssertRCReturn(rc, rc);
511
512	/* Save mwait state. */
513	rc = SSMR3PutU32(pSSM, pVCpu->em.s.MWait.fWait);
514	AssertRCReturn(rc, rc);
515	rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMWaitRAX);
516	AssertRCReturn(rc, rc);
517	rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMWaitRCX);
518	AssertRCReturn(rc, rc);
519	rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRAX);
520	AssertRCReturn(rc, rc);
521	rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRCX);
522	AssertRCReturn(rc, rc);
523	rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRDX);
524	AssertRCReturn(rc, rc);
525	}
526	return VINF_SUCCESS;
527	}
528
529
530	/**
531	* Execute state load operation.
532	*
533	* @returns VBox status code.
534	* @param pVM Pointer to the VM.
535	* @param pSSM SSM operation handle.
536	* @param uVersion Data layout version.
537	* @param uPass The data pass.
538	*/
539	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
540	{
541	/*
542	* Validate version.
543	*/
544	if ( uVersion != EM_SAVED_STATE_VERSION
545	&& uVersion != EM_SAVED_STATE_VERSION_PRE_MWAIT
546	&& uVersion != EM_SAVED_STATE_VERSION_PRE_SMP)
547	{
548	AssertMsgFailed(("emR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, EM_SAVED_STATE_VERSION));
549	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
550	}
551	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
552
553	/*
554	* Load the saved state.
555	*/
556	for (VMCPUID i = 0; i < pVM->cCpus; i++)
557	{
558	PVMCPU pVCpu = &pVM->aCpus[i];
559
560	int rc = SSMR3GetBool(pSSM, &pVCpu->em.s.fForceRAW);
561	if (RT_FAILURE(rc))
562	pVCpu->em.s.fForceRAW = false;
563	AssertRCReturn(rc, rc);
564
565	if (uVersion > EM_SAVED_STATE_VERSION_PRE_SMP)
566	{
567	AssertCompile(sizeof(pVCpu->em.s.enmPrevState) == sizeof(uint32_t));
568	rc = SSMR3GetU32(pSSM, (uint32_t *)&pVCpu->em.s.enmPrevState);
569	AssertRCReturn(rc, rc);
570	Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
571
572	pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
573	}
574	if (uVersion > EM_SAVED_STATE_VERSION_PRE_MWAIT)
575	{
576	/* Load mwait state. */
577	rc = SSMR3GetU32(pSSM, &pVCpu->em.s.MWait.fWait);
578	AssertRCReturn(rc, rc);
579	rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMWaitRAX);
580	AssertRCReturn(rc, rc);
581	rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMWaitRCX);
582	AssertRCReturn(rc, rc);
583	rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRAX);
584	AssertRCReturn(rc, rc);
585	rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRCX);
586	AssertRCReturn(rc, rc);
587	rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRDX);
588	AssertRCReturn(rc, rc);
589	}
590
591	Assert(!pVCpu->em.s.pCliStatTree);
592	}
593	return VINF_SUCCESS;
594	}
595
596
597	/**
598	* Argument packet for emR3SetExecutionPolicy.
599	*/
600	struct EMR3SETEXECPOLICYARGS
601	{
602	EMEXECPOLICY enmPolicy;
603	bool fEnforce;
604	};
605
606
607	/**
608	* @callback_method_impl{FNVMMEMTRENDEZVOUS, Rendezvous callback for EMR3SetExecutionPolicy.}
609	*/
610	static DECLCALLBACK(VBOXSTRICTRC) emR3SetExecutionPolicy(PVM pVM, PVMCPU pVCpu, void *pvUser)
611	{
612	/*
613	* Only the first CPU changes the variables.
614	*/
615	if (pVCpu->idCpu == 0)
616	{
617	struct EMR3SETEXECPOLICYARGS pArgs = (struct EMR3SETEXECPOLICYARGS )pvUser;
618	switch (pArgs->enmPolicy)
619	{
620	case EMEXECPOLICY_RECOMPILE_RING0:
621	pVM->fRecompileSupervisor = pArgs->fEnforce;
622	break;
623	case EMEXECPOLICY_RECOMPILE_RING3:
624	pVM->fRecompileUser = pArgs->fEnforce;
625	break;
626	default:
627	AssertFailedReturn(VERR_INVALID_PARAMETER);
628	}
629	Log(("emR3SetExecutionPolicy: fRecompileUser=%RTbool fRecompileSupervisor=%RTbool\n",
630	pVM->fRecompileUser, pVM->fRecompileSupervisor));
631	}
632
633	/*
634	* Force rescheduling if in RAW, HWACCM or REM.
635	*/
636	return pVCpu->em.s.enmState == EMSTATE_RAW
637	\|\| pVCpu->em.s.enmState == EMSTATE_HWACC
638	\|\| pVCpu->em.s.enmState == EMSTATE_REM
639	? VINF_EM_RESCHEDULE
640	: VINF_SUCCESS;
641	}
642
643
644	/**
645	* Changes a the execution scheduling policy.
646	*
647	* This is used to enable or disable raw-mode / hardware-virtualization
648	* execution of user and supervisor code.
649	*
650	* @returns VINF_SUCCESS on success.
651	* @returns VINF_RESCHEDULE if a rescheduling might be required.
652	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
653	*
654	* @param pVM Pointer to the VM.
655	* @param enmPolicy The scheduling policy to change.
656	* @param fEnforce Whether to enforce the policy or not.
657	*/
658	VMMR3DECL(int) EMR3SetExecutionPolicy(PVM pVM, EMEXECPOLICY enmPolicy, bool fEnforce)
659	{
660	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
661	AssertReturn(enmPolicy > EMEXECPOLICY_INVALID && enmPolicy < EMEXECPOLICY_END, VERR_INVALID_PARAMETER);
662
663	struct EMR3SETEXECPOLICYARGS Args = { enmPolicy, fEnforce };
664	return VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_DESCENDING, emR3SetExecutionPolicy, &Args);
665	}
666
667
668	/**
669	* Raise a fatal error.
670	*
671	* Safely terminate the VM with full state report and stuff. This function
672	* will naturally never return.
673	*
674	* @param pVCpu Pointer to the VMCPU.
675	* @param rc VBox status code.
676	*/
677	VMMR3DECL(void) EMR3FatalError(PVMCPU pVCpu, int rc)
678	{
679	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
680	longjmp(pVCpu->em.s.u.FatalLongJump, rc);
681	AssertReleaseMsgFailed(("longjmp returned!\n"));
682	}
683
684
685	#if defined(LOG_ENABLED) \|\| defined(VBOX_STRICT)
686	/**
687	* Gets the EM state name.
688	*
689	* @returns pointer to read only state name,
690	* @param enmState The state.
691	*/
692	static const char *emR3GetStateName(EMSTATE enmState)
693	{
694	switch (enmState)
695	{
696	case EMSTATE_NONE: return "EMSTATE_NONE";
697	case EMSTATE_RAW: return "EMSTATE_RAW";
698	case EMSTATE_HWACC: return "EMSTATE_HWACC";
699	case EMSTATE_REM: return "EMSTATE_REM";
700	case EMSTATE_HALTED: return "EMSTATE_HALTED";
701	case EMSTATE_WAIT_SIPI: return "EMSTATE_WAIT_SIPI";
702	case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
703	case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
704	case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
705	case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
706	case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
707	case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
708	default: return "Unknown!";
709	}
710	}
711	#endif /* LOG_ENABLED \|\| VBOX_STRICT */
712
713
714	/**
715	* Debug loop.
716	*
717	* @returns VBox status code for EM.
718	* @param pVM Pointer to the VM.
719	* @param pVCpu Pointer to the VMCPU.
720	* @param rc Current EM VBox status code.
721	*/
722	static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc)
723	{
724	for (;;)
725	{
726	Log(("emR3Debug: rc=%Rrc\n", rc));
727	const int rcLast = rc;
728
729	/*
730	* Debug related RC.
731	*/
732	switch (rc)
733	{
734	/*
735	* Single step an instruction.
736	*/
737	case VINF_EM_DBG_STEP:
738	if ( pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
739	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
740	\|\| pVCpu->em.s.fForceRAW /* paranoia */)
741	rc = emR3RawStep(pVM, pVCpu);
742	else
743	{
744	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
745	rc = emR3RemStep(pVM, pVCpu);
746	}
747	break;
748
749	/*
750	* Simple events: stepped, breakpoint, stop/assertion.
751	*/
752	case VINF_EM_DBG_STEPPED:
753	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
754	break;
755
756	case VINF_EM_DBG_BREAKPOINT:
757	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
758	break;
759
760	case VINF_EM_DBG_STOP:
761	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
762	break;
763
764	case VINF_EM_DBG_HYPER_STEPPED:
765	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
766	break;
767
768	case VINF_EM_DBG_HYPER_BREAKPOINT:
769	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
770	break;
771
772	case VINF_EM_DBG_HYPER_ASSERTION:
773	RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
774	RTLogFlush(NULL);
775	rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
776	break;
777
778	/*
779	* Guru meditation.
780	*/
781	case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
782	rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
783	break;
784	case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
785	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
786	break;
787
788	default: /** @todo don't use default for guru, but make special errors code! */
789	rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
790	break;
791	}
792
793	/*
794	* Process the result.
795	*/
796	do
797	{
798	switch (rc)
799	{
800	/*
801	* Continue the debugging loop.
802	*/
803	case VINF_EM_DBG_STEP:
804	case VINF_EM_DBG_STOP:
805	case VINF_EM_DBG_STEPPED:
806	case VINF_EM_DBG_BREAKPOINT:
807	case VINF_EM_DBG_HYPER_STEPPED:
808	case VINF_EM_DBG_HYPER_BREAKPOINT:
809	case VINF_EM_DBG_HYPER_ASSERTION:
810	break;
811
812	/*
813	* Resuming execution (in some form) has to be done here if we got
814	* a hypervisor debug event.
815	*/
816	case VINF_SUCCESS:
817	case VINF_EM_RESUME:
818	case VINF_EM_SUSPEND:
819	case VINF_EM_RESCHEDULE:
820	case VINF_EM_RESCHEDULE_RAW:
821	case VINF_EM_RESCHEDULE_REM:
822	case VINF_EM_HALT:
823	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
824	{
825	rc = emR3RawResumeHyper(pVM, pVCpu);
826	if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
827	continue;
828	}
829	if (rc == VINF_SUCCESS)
830	rc = VINF_EM_RESCHEDULE;
831	return rc;
832
833	/*
834	* The debugger isn't attached.
835	* We'll simply turn the thing off since that's the easiest thing to do.
836	*/
837	case VERR_DBGF_NOT_ATTACHED:
838	switch (rcLast)
839	{
840	case VINF_EM_DBG_HYPER_STEPPED:
841	case VINF_EM_DBG_HYPER_BREAKPOINT:
842	case VINF_EM_DBG_HYPER_ASSERTION:
843	case VERR_TRPM_PANIC:
844	case VERR_TRPM_DONT_PANIC:
845	case VERR_VMM_RING0_ASSERTION:
846	case VERR_VMM_HYPER_CR3_MISMATCH:
847	case VERR_VMM_RING3_CALL_DISABLED:
848	return rcLast;
849	}
850	return VINF_EM_OFF;
851
852	/*
853	* Status codes terminating the VM in one or another sense.
854	*/
855	case VINF_EM_TERMINATE:
856	case VINF_EM_OFF:
857	case VINF_EM_RESET:
858	case VINF_EM_NO_MEMORY:
859	case VINF_EM_RAW_STALE_SELECTOR:
860	case VINF_EM_RAW_IRET_TRAP:
861	case VERR_TRPM_PANIC:
862	case VERR_TRPM_DONT_PANIC:
863	case VERR_IEM_INSTR_NOT_IMPLEMENTED:
864	case VERR_IEM_ASPECT_NOT_IMPLEMENTED:
865	case VERR_VMM_RING0_ASSERTION:
866	case VERR_VMM_HYPER_CR3_MISMATCH:
867	case VERR_VMM_RING3_CALL_DISABLED:
868	case VERR_INTERNAL_ERROR:
869	case VERR_INTERNAL_ERROR_2:
870	case VERR_INTERNAL_ERROR_3:
871	case VERR_INTERNAL_ERROR_4:
872	case VERR_INTERNAL_ERROR_5:
873	case VERR_IPE_UNEXPECTED_STATUS:
874	case VERR_IPE_UNEXPECTED_INFO_STATUS:
875	case VERR_IPE_UNEXPECTED_ERROR_STATUS:
876	return rc;
877
878	/*
879	* The rest is unexpected, and will keep us here.
880	*/
881	default:
882	AssertMsgFailed(("Unexpected rc %Rrc!\n", rc));
883	break;
884	}
885	} while (false);
886	} /* debug for ever */
887	}
888
889	/**
890	* Steps recompiled code.
891	*
892	* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
893	* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
894	*
895	* @param pVM Pointer to the VM.
896	* @param pVCpu Pointer to the VMCPU.
897	*/
898	static int emR3RemStep(PVM pVM, PVMCPU pVCpu)
899	{
900	LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
901
902	#ifdef VBOX_WITH_REM
903	EMRemLock(pVM);
904
905	/*
906	* Switch to REM, step instruction, switch back.
907	*/
908	int rc = REMR3State(pVM, pVCpu);
909	if (RT_SUCCESS(rc))
910	{
911	rc = REMR3Step(pVM, pVCpu);
912	REMR3StateBack(pVM, pVCpu);
913	}
914	EMRemUnlock(pVM);
915
916	#else
917	int rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu)); NOREF(pVM);
918	#endif
919
920	LogFlow(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
921	return rc;
922	}
923
924
925	/**
926	* emR3RemExecute helper that syncs the state back from REM and leave the REM
927	* critical section.
928	*
929	* @returns false - new fInREMState value.
930	* @param pVM Pointer to the VM.
931	* @param pVCpu Pointer to the VMCPU.
932	*/
933	DECLINLINE(bool) emR3RemExecuteSyncBack(PVM pVM, PVMCPU pVCpu)
934	{
935	#ifdef VBOX_WITH_REM
936	STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, a);
937	REMR3StateBack(pVM, pVCpu);
938	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, a);
939
940	EMRemUnlock(pVM);
941	#endif
942	return false;
943	}
944
945
946	/**
947	* Executes recompiled code.
948	*
949	* This function contains the recompiler version of the inner
950	* execution loop (the outer loop being in EMR3ExecuteVM()).
951	*
952	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
953	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
954	*
955	* @param pVM Pointer to the VM.
956	* @param pVCpu Pointer to the VMCPU.
957	* @param pfFFDone Where to store an indicator telling whether or not
958	* FFs were done before returning.
959	*
960	*/
961	static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
962	{
963	#ifdef LOG_ENABLED
964	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
965	uint32_t cpl = CPUMGetGuestCPL(pVCpu);
966
967	if (pCtx->eflags.Bits.u1VM)
968	Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags.Bits.u1IF));
969	else
970	Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x eflags=%x\n", cpl, pCtx->cs.Sel, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, pCtx->eflags.u));
971	#endif
972	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatREMTotal, a);
973
974	#if defined(VBOX_STRICT) && defined(DEBUG_bird)
975	AssertMsg( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
976	\|\| !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVCpu)), /** @todo @bugref{1419} - get flat address. */
977	("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
978	#endif
979
980	/*
981	* Spin till we get a forced action which returns anything but VINF_SUCCESS
982	* or the REM suggests raw-mode execution.
983	*/
984	*pfFFDone = false;
985	#ifdef VBOX_WITH_REM
986	bool fInREMState = false;
987	#endif
988	int rc = VINF_SUCCESS;
989	for (;;)
990	{
991	#ifdef VBOX_WITH_REM
992	/*
993	* Lock REM and update the state if not already in sync.
994	*
995	* Note! Big lock, but you are not supposed to own any lock when
996	* coming in here.
997	*/
998	if (!fInREMState)
999	{
1000	EMRemLock(pVM);
1001	STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, b);
1002
1003	/* Flush the recompiler translation blocks if the VCPU has changed,
1004	also force a full CPU state resync. */
1005	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
1006	{
1007	REMFlushTBs(pVM);
1008	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1009	}
1010	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
1011
1012	rc = REMR3State(pVM, pVCpu);
1013
1014	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, b);
1015	if (RT_FAILURE(rc))
1016	break;
1017	fInREMState = true;
1018
1019	/*
1020	* We might have missed the raising of VMREQ, TIMER and some other
1021	* important FFs while we were busy switching the state. So, check again.
1022	*/
1023	if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_DBGF \| VM_FF_CHECK_VM_STATE \| VM_FF_RESET)
1024	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER \| VMCPU_FF_REQUEST))
1025	{
1026	LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fGlobalForcedActions));
1027	goto l_REMDoForcedActions;
1028	}
1029	}
1030	#endif
1031
1032	/*
1033	* Execute REM.
1034	*/
1035	if (RT_LIKELY(EMR3IsExecutionAllowed(pVM, pVCpu)))
1036	{
1037	STAM_PROFILE_START(&pVCpu->em.s.StatREMExec, c);
1038	#ifdef VBOX_WITH_REM
1039	rc = REMR3Run(pVM, pVCpu);
1040	#else
1041	rc = VBOXSTRICTRC_TODO(IEMExecLots(pVCpu));
1042	#endif
1043	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMExec, c);
1044	}
1045	else
1046	{
1047	/* Give up this time slice; virtual time continues */
1048	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1049	RTThreadSleep(5);
1050	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1051	rc = VINF_SUCCESS;
1052	}
1053
1054	/*
1055	* Deal with high priority post execution FFs before doing anything
1056	* else. Sync back the state and leave the lock to be on the safe side.
1057	*/
1058	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1059	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1060	{
1061	#ifdef VBOX_WITH_REM
1062	fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1063	#endif
1064	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1065	}
1066
1067	/*
1068	* Process the returned status code.
1069	*/
1070	if (rc != VINF_SUCCESS)
1071	{
1072	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1073	break;
1074	if (rc != VINF_REM_INTERRUPED_FF)
1075	{
1076	/*
1077	* Anything which is not known to us means an internal error
1078	* and the termination of the VM!
1079	*/
1080	AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
1081	break;
1082	}
1083	}
1084
1085
1086	/*
1087	* Check and execute forced actions.
1088	*
1089	* Sync back the VM state and leave the lock before calling any of
1090	* these, you never know what's going to happen here.
1091	*/
1092	#ifdef VBOX_HIGH_RES_TIMERS_HACK
1093	TMTimerPollVoid(pVM, pVCpu);
1094	#endif
1095	AssertCompile((VMCPU_FF_ALL_REM_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION \| VMCPU_FF_CSAM_SCAN_PAGE)) & VMCPU_FF_TIMER);
1096	if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_REM_MASK)
1097	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_REM_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION \| VMCPU_FF_CSAM_SCAN_PAGE)))
1098	{
1099	l_REMDoForcedActions:
1100	#ifdef VBOX_WITH_REM
1101	if (fInREMState)
1102	fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1103	#endif
1104	STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatREMTotal, a);
1105	rc = emR3ForcedActions(pVM, pVCpu, rc);
1106	VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
1107	STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatREMTotal, a);
1108	if ( rc != VINF_SUCCESS
1109	&& rc != VINF_EM_RESCHEDULE_REM)
1110	{
1111	*pfFFDone = true;
1112	break;
1113	}
1114	}
1115
1116	} /* The Inner Loop, recompiled execution mode version. */
1117
1118
1119	#ifdef VBOX_WITH_REM
1120	/*
1121	* Returning. Sync back the VM state if required.
1122	*/
1123	if (fInREMState)
1124	fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1125	#endif
1126
1127	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatREMTotal, a);
1128	return rc;
1129	}
1130
1131
1132	#ifdef DEBUG
1133
1134	int emR3SingleStepExecRem(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1135	{
1136	EMSTATE enmOldState = pVCpu->em.s.enmState;
1137
1138	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1139
1140	Log(("Single step BEGIN:\n"));
1141	for (uint32_t i = 0; i < cIterations; i++)
1142	{
1143	DBGFR3PrgStep(pVCpu);
1144	DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
1145	emR3RemStep(pVM, pVCpu);
1146	if (emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx) != EMSTATE_REM)
1147	break;
1148	}
1149	Log(("Single step END:\n"));
1150	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1151	pVCpu->em.s.enmState = enmOldState;
1152	return VINF_EM_RESCHEDULE;
1153	}
1154
1155	#endif /* DEBUG */
1156
1157
1158	/**
1159	* Decides whether to execute RAW, HWACC or REM.
1160	*
1161	* @returns new EM state
1162	* @param pVM Pointer to the VM.
1163	* @param pVCpu Pointer to the VMCPU.
1164	* @param pCtx Pointer to the guest CPU context.
1165	*/
1166	EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1167	{
1168	#ifdef IEM_VERIFICATION_MODE
1169	return EMSTATE_REM;
1170	#else
1171
1172	/*
1173	* When forcing raw-mode execution, things are simple.
1174	*/
1175	if (pVCpu->em.s.fForceRAW)
1176	return EMSTATE_RAW;
1177
1178	/*
1179	* We stay in the wait for SIPI state unless explicitly told otherwise.
1180	*/
1181	if (pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI)
1182	return EMSTATE_WAIT_SIPI;
1183
1184	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1185	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1186	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1187
1188	X86EFLAGS EFlags = pCtx->eflags;
1189	if (HWACCMIsEnabled(pVM))
1190	{
1191	/*
1192	* Hardware accelerated raw-mode:
1193	*
1194	* Typically only 32-bits protected mode, with paging enabled, code is
1195	* allowed here.
1196	*/
1197	if ( EMIsHwVirtExecutionEnabled(pVM)
1198	&& HWACCMR3CanExecuteGuest(pVM, pCtx))
1199	return EMSTATE_HWACC;
1200
1201	/*
1202	* Note! Raw mode and hw accelerated mode are incompatible. The latter
1203	* turns off monitoring features essential for raw mode!
1204	*/
1205	return EMSTATE_REM;
1206	}
1207
1208	/*
1209	* Standard raw-mode:
1210	*
1211	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1212	* or 32 bits protected mode ring 0 code
1213	*
1214	* The tests are ordered by the likelihood of being true during normal execution.
1215	*/
1216	if (EFlags.u32 & (X86_EFL_TF /* \| HF_INHIBIT_IRQ_MASK*/))
1217	{
1218	Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
1219	return EMSTATE_REM;
1220	}
1221
1222	# ifndef VBOX_RAW_V86
1223	if (EFlags.u32 & X86_EFL_VM) {
1224	Log2(("raw mode refused: VM_MASK\n"));
1225	return EMSTATE_REM;
1226	}
1227	# endif
1228
1229	/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
1230	uint32_t u32CR0 = pCtx->cr0;
1231	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
1232	{
1233	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1234	return EMSTATE_REM;
1235	}
1236
1237	if (pCtx->cr4 & X86_CR4_PAE)
1238	{
1239	uint32_t u32Dummy, u32Features;
1240
1241	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1242	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
1243	return EMSTATE_REM;
1244	}
1245
1246	unsigned uSS = pCtx->ss.Sel;
1247	if ( pCtx->eflags.Bits.u1VM
1248	\|\| (uSS & X86_SEL_RPL) == 3)
1249	{
1250	if (!EMIsRawRing3Enabled(pVM))
1251	return EMSTATE_REM;
1252
1253	if (!(EFlags.u32 & X86_EFL_IF))
1254	{
1255	Log2(("raw mode refused: IF (RawR3)\n"));
1256	return EMSTATE_REM;
1257	}
1258
1259	if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
1260	{
1261	Log2(("raw mode refused: CR0.WP + RawR0\n"));
1262	return EMSTATE_REM;
1263	}
1264	}
1265	else
1266	{
1267	if (!EMIsRawRing0Enabled(pVM))
1268	return EMSTATE_REM;
1269
1270	/* Only ring 0 supervisor code. */
1271	if ((uSS & X86_SEL_RPL) != 0)
1272	{
1273	Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
1274	return EMSTATE_REM;
1275	}
1276
1277	// Let's start with pure 32 bits ring 0 code first
1278	/** @todo What's pure 32-bit mode? flat? */
1279	if ( !(pCtx->ss.Attr.n.u1DefBig)
1280	\|\| !(pCtx->cs.Attr.n.u1DefBig))
1281	{
1282	Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
1283	return EMSTATE_REM;
1284	}
1285
1286	/* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
1287	if (!(u32CR0 & X86_CR0_WP))
1288	{
1289	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1290	return EMSTATE_REM;
1291	}
1292
1293	if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
1294	{
1295	Log2(("raw r0 mode forced: patch code\n"));
1296	return EMSTATE_RAW;
1297	}
1298
1299	# if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1300	if (!(EFlags.u32 & X86_EFL_IF))
1301	{
1302	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
1303	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1304	return EMSTATE_REM;
1305	}
1306	# endif
1307
1308	/** @todo still necessary??? */
1309	if (EFlags.Bits.u2IOPL != 0)
1310	{
1311	Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
1312	return EMSTATE_REM;
1313	}
1314	}
1315
1316	/*
1317	* Stale hidden selectors means raw-mode is unsafe (being very careful).
1318	*/
1319	if (pCtx->cs.fFlags & CPUMSELREG_FLAGS_STALE)
1320	{
1321	Log2(("raw mode refused: stale CS\n"));
1322	return EMSTATE_REM;
1323	}
1324	if (pCtx->ss.fFlags & CPUMSELREG_FLAGS_STALE)
1325	{
1326	Log2(("raw mode refused: stale SS\n"));
1327	return EMSTATE_REM;
1328	}
1329	if (pCtx->ds.fFlags & CPUMSELREG_FLAGS_STALE)
1330	{
1331	Log2(("raw mode refused: stale DS\n"));
1332	return EMSTATE_REM;
1333	}
1334	if (pCtx->es.fFlags & CPUMSELREG_FLAGS_STALE)
1335	{
1336	Log2(("raw mode refused: stale ES\n"));
1337	return EMSTATE_REM;
1338	}
1339	if (pCtx->fs.fFlags & CPUMSELREG_FLAGS_STALE)
1340	{
1341	Log2(("raw mode refused: stale FS\n"));
1342	return EMSTATE_REM;
1343	}
1344	if (pCtx->gs.fFlags & CPUMSELREG_FLAGS_STALE)
1345	{
1346	Log2(("raw mode refused: stale GS\n"));
1347	return EMSTATE_REM;
1348	}
1349
1350	/Assert(PGMPhysIsA20Enabled(pVCpu));/
1351	return EMSTATE_RAW;
1352	#endif /* !IEM_VERIFICATION_MODE */
1353
1354	}
1355
1356
1357	/**
1358	* Executes all high priority post execution force actions.
1359	*
1360	* @returns rc or a fatal status code.
1361	*
1362	* @param pVM Pointer to the VM.
1363	* @param pVCpu Pointer to the VMCPU.
1364	* @param rc The current rc.
1365	*/
1366	int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1367	{
1368	VBOXVMM_EM_FF_HIGH(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions, rc);
1369
1370	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PDM_CRITSECT))
1371	PDMCritSectFF(pVCpu);
1372
1373	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION))
1374	CSAMR3DoPendingAction(pVM, pVCpu);
1375
1376	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1377	{
1378	if ( rc > VINF_EM_NO_MEMORY
1379	&& rc <= VINF_EM_LAST)
1380	rc = VINF_EM_NO_MEMORY;
1381	}
1382
1383	return rc;
1384	}
1385
1386
1387	/**
1388	* Executes all pending forced actions.
1389	*
1390	* Forced actions can cause execution delays and execution
1391	* rescheduling. The first we deal with using action priority, so
1392	* that for instance pending timers aren't scheduled and ran until
1393	* right before execution. The rescheduling we deal with using
1394	* return codes. The same goes for VM termination, only in that case
1395	* we exit everything.
1396	*
1397	* @returns VBox status code of equal or greater importance/severity than rc.
1398	* The most important ones are: VINF_EM_RESCHEDULE,
1399	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1400	*
1401	* @param pVM Pointer to the VM.
1402	* @param pVCpu Pointer to the VMCPU.
1403	* @param rc The current rc.
1404	*
1405	*/
1406	int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1407	{
1408	STAM_REL_PROFILE_START(&pVCpu->em.s.StatForcedActions, a);
1409	#ifdef VBOX_STRICT
1410	int rcIrq = VINF_SUCCESS;
1411	#endif
1412	int rc2;
1413	#define UPDATE_RC() \
1414	do { \
1415	AssertMsg(rc2 <= 0 \|\| (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
1416	if (rc2 == VINF_SUCCESS \|\| rc < VINF_SUCCESS) \
1417	break; \
1418	if (!rc \|\| rc2 < rc) \
1419	rc = rc2; \
1420	} while (0)
1421	VBOXVMM_EM_FF_ALL(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions, rc);
1422
1423	/*
1424	* Post execution chunk first.
1425	*/
1426	if ( VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK)
1427	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_POST_MASK))
1428	{
1429	/*
1430	* EMT Rendezvous (must be serviced before termination).
1431	*/
1432	if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1433	{
1434	rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1435	UPDATE_RC();
1436	/** @todo HACK ALERT! The following test is to make sure EM+TM
1437	* thinks the VM is stopped/reset before the next VM state change
1438	* is made. We need a better solution for this, or at least make it
1439	* possible to do: (rc >= VINF_EM_FIRST && rc <=
1440	* VINF_EM_SUSPEND). */
1441	if (RT_UNLIKELY(rc == VINF_EM_SUSPEND \|\| rc == VINF_EM_RESET \|\| rc == VINF_EM_OFF))
1442	{
1443	Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1444	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1445	return rc;
1446	}
1447	}
1448
1449	/*
1450	* State change request (cleared by vmR3SetStateLocked).
1451	*/
1452	if (VM_FF_ISPENDING(pVM, VM_FF_CHECK_VM_STATE))
1453	{
1454	VMSTATE enmState = VMR3GetState(pVM);
1455	switch (enmState)
1456	{
1457	case VMSTATE_FATAL_ERROR:
1458	case VMSTATE_FATAL_ERROR_LS:
1459	Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
1460	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1461	return VINF_EM_SUSPEND;
1462
1463	case VMSTATE_DESTROYING:
1464	Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
1465	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1466	return VINF_EM_TERMINATE;
1467
1468	default:
1469	AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
1470	}
1471	}
1472
1473	/*
1474	* Debugger Facility polling.
1475	*/
1476	if (VM_FF_ISPENDING(pVM, VM_FF_DBGF))
1477	{
1478	rc2 = DBGFR3VMMForcedAction(pVM);
1479	UPDATE_RC();
1480	}
1481
1482	/*
1483	* Postponed reset request.
1484	*/
1485	if (VM_FF_TESTANDCLEAR(pVM, VM_FF_RESET))
1486	{
1487	rc2 = VMR3Reset(pVM);
1488	UPDATE_RC();
1489	}
1490
1491	/*
1492	* CSAM page scanning.
1493	*/
1494	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1495	&& VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE))
1496	{
1497	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1498
1499	/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
1500	Log(("Forced action VMCPU_FF_CSAM_SCAN_PAGE\n"));
1501
1502	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1503	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE);
1504	}
1505
1506	/*
1507	* Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
1508	*/
1509	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1510	{
1511	rc2 = PGMR3PhysAllocateHandyPages(pVM);
1512	UPDATE_RC();
1513	if (rc == VINF_EM_NO_MEMORY)
1514	return rc;
1515	}
1516
1517	/* check that we got them all */
1518	AssertCompile(VM_FF_NORMAL_PRIORITY_POST_MASK == (VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS));
1519	AssertCompile(VMCPU_FF_NORMAL_PRIORITY_POST_MASK == VMCPU_FF_CSAM_SCAN_PAGE);
1520	}
1521
1522	/*
1523	* Normal priority then.
1524	* (Executed in no particular order.)
1525	*/
1526	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_NORMAL_PRIORITY_MASK, VM_FF_PGM_NO_MEMORY))
1527	{
1528	/*
1529	* PDM Queues are pending.
1530	*/
1531	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_QUEUES, VM_FF_PGM_NO_MEMORY))
1532	PDMR3QueueFlushAll(pVM);
1533
1534	/*
1535	* PDM DMA transfers are pending.
1536	*/
1537	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_DMA, VM_FF_PGM_NO_MEMORY))
1538	PDMR3DmaRun(pVM);
1539
1540	/*
1541	* EMT Rendezvous (make sure they are handled before the requests).
1542	*/
1543	if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1544	{
1545	rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1546	UPDATE_RC();
1547	/** @todo HACK ALERT! The following test is to make sure EM+TM
1548	* thinks the VM is stopped/reset before the next VM state change
1549	* is made. We need a better solution for this, or at least make it
1550	* possible to do: (rc >= VINF_EM_FIRST && rc <=
1551	* VINF_EM_SUSPEND). */
1552	if (RT_UNLIKELY(rc == VINF_EM_SUSPEND \|\| rc == VINF_EM_RESET \|\| rc == VINF_EM_OFF))
1553	{
1554	Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1555	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1556	return rc;
1557	}
1558	}
1559
1560	/*
1561	* Requests from other threads.
1562	*/
1563	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
1564	{
1565	rc2 = VMR3ReqProcessU(pVM->pUVM, VMCPUID_ANY, false /fPriorityOnly/);
1566	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE) /** @todo this shouldn't be necessary */
1567	{
1568	Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1569	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1570	return rc2;
1571	}
1572	UPDATE_RC();
1573	/** @todo HACK ALERT! The following test is to make sure EM+TM
1574	* thinks the VM is stopped/reset before the next VM state change
1575	* is made. We need a better solution for this, or at least make it
1576	* possible to do: (rc >= VINF_EM_FIRST && rc <=
1577	* VINF_EM_SUSPEND). */
1578	if (RT_UNLIKELY(rc == VINF_EM_SUSPEND \|\| rc == VINF_EM_RESET \|\| rc == VINF_EM_OFF))
1579	{
1580	Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1581	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1582	return rc;
1583	}
1584	}
1585
1586	#ifdef VBOX_WITH_REM
1587	/* Replay the handler notification changes. */
1588	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REM_HANDLER_NOTIFY, VM_FF_PGM_NO_MEMORY))
1589	{
1590	/* Try not to cause deadlocks. */
1591	if ( pVM->cCpus == 1
1592	\|\| ( !PGMIsLockOwner(pVM)
1593	&& !IOMIsLockOwner(pVM))
1594	)
1595	{
1596	EMRemLock(pVM);
1597	REMR3ReplayHandlerNotifications(pVM);
1598	EMRemUnlock(pVM);
1599	}
1600	}
1601	#endif
1602
1603	/* check that we got them all */
1604	AssertCompile(VM_FF_NORMAL_PRIORITY_MASK == (VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_REM_HANDLER_NOTIFY \| VM_FF_EMT_RENDEZVOUS));
1605	}
1606
1607	/*
1608	* Normal priority then. (per-VCPU)
1609	* (Executed in no particular order.)
1610	*/
1611	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1612	&& VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_MASK))
1613	{
1614	/*
1615	* Requests from other threads.
1616	*/
1617	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1618	{
1619	rc2 = VMR3ReqProcessU(pVM->pUVM, pVCpu->idCpu, false /fPriorityOnly/);
1620	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE \|\| rc2 == VINF_EM_RESET)
1621	{
1622	Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1623	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1624	return rc2;
1625	}
1626	UPDATE_RC();
1627	/** @todo HACK ALERT! The following test is to make sure EM+TM
1628	* thinks the VM is stopped/reset before the next VM state change
1629	* is made. We need a better solution for this, or at least make it
1630	* possible to do: (rc >= VINF_EM_FIRST && rc <=
1631	* VINF_EM_SUSPEND). */
1632	if (RT_UNLIKELY(rc == VINF_EM_SUSPEND \|\| rc == VINF_EM_RESET \|\| rc == VINF_EM_OFF))
1633	{
1634	Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1635	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1636	return rc;
1637	}
1638	}
1639
1640	/* check that we got them all */
1641	Assert(!(VMCPU_FF_NORMAL_PRIORITY_MASK & ~(VMCPU_FF_REQUEST)));
1642	}
1643
1644	/*
1645	* High priority pre execution chunk last.
1646	* (Executed in ascending priority order.)
1647	*/
1648	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK)
1649	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_MASK))
1650	{
1651	/*
1652	* Timers before interrupts.
1653	*/
1654	if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER)
1655	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1656	TMR3TimerQueuesDo(pVM);
1657
1658	/*
1659	* The instruction following an emulated STI should always be executed!
1660	*
1661	* Note! We intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if
1662	* the eip is the same as the inhibited instr address. Before we
1663	* are able to execute this instruction in raw mode (iret to
1664	* guest code) an external interrupt might force a world switch
1665	* again. Possibly allowing a guest interrupt to be dispatched
1666	* in the process. This could break the guest. Sounds very
1667	* unlikely, but such timing sensitive problem are not as rare as
1668	* you might think.
1669	*/
1670	if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1671	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1672	{
1673	if (CPUMGetGuestRIP(pVCpu) != EMGetInhibitInterruptsPC(pVCpu))
1674	{
1675	Log(("Clearing VMCPU_FF_INHIBIT_INTERRUPTS at %RGv - successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu), EMGetInhibitInterruptsPC(pVCpu)));
1676	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1677	}
1678	else
1679	Log(("Leaving VMCPU_FF_INHIBIT_INTERRUPTS set at %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu)));
1680	}
1681
1682	/*
1683	* Interrupts.
1684	*/
1685	bool fWakeupPending = false;
1686	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1687	&& !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1688	&& (!rc \|\| rc >= VINF_EM_RESCHEDULE_HWACC)
1689	&& !TRPMHasTrap(pVCpu) /* an interrupt could already be scheduled for dispatching in the recompiler. */
1690	&& PATMAreInterruptsEnabled(pVM)
1691	&& !HWACCMR3IsEventPending(pVCpu))
1692	{
1693	Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1694	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC))
1695	{
1696	/* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
1697	/** @todo this really isn't nice, should properly handle this */
1698	rc2 = TRPMR3InjectEvent(pVM, pVCpu, TRPM_HARDWARE_INT);
1699	#ifdef VBOX_STRICT
1700	rcIrq = rc2;
1701	#endif
1702	UPDATE_RC();
1703	/* Reschedule required: We must not miss the wakeup below! */
1704	fWakeupPending = true;
1705	}
1706	#ifdef VBOX_WITH_REM
1707	/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
1708	else if (REMR3QueryPendingInterrupt(pVM, pVCpu) != REM_NO_PENDING_IRQ)
1709	{
1710	rc2 = VINF_EM_RESCHEDULE_REM;
1711	UPDATE_RC();
1712	}
1713	#endif
1714	}
1715
1716	/*
1717	* Allocate handy pages.
1718	*/
1719	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1720	{
1721	rc2 = PGMR3PhysAllocateHandyPages(pVM);
1722	UPDATE_RC();
1723	}
1724
1725	/*
1726	* Debugger Facility request.
1727	*/
1728	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_DBGF, VM_FF_PGM_NO_MEMORY))
1729	{
1730	rc2 = DBGFR3VMMForcedAction(pVM);
1731	UPDATE_RC();
1732	}
1733
1734	/*
1735	* EMT Rendezvous (must be serviced before termination).
1736	*/
1737	if ( !fWakeupPending /* don't miss the wakeup from EMSTATE_HALTED! */
1738	&& VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1739	{
1740	rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1741	UPDATE_RC();
1742	/** @todo HACK ALERT! The following test is to make sure EM+TM thinks the VM is
1743	* stopped/reset before the next VM state change is made. We need a better
1744	* solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1745	* && rc >= VINF_EM_SUSPEND). */
1746	if (RT_UNLIKELY(rc == VINF_EM_SUSPEND \|\| rc == VINF_EM_RESET \|\| rc == VINF_EM_OFF))
1747	{
1748	Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1749	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1750	return rc;
1751	}
1752	}
1753
1754	/*
1755	* State change request (cleared by vmR3SetStateLocked).
1756	*/
1757	if ( !fWakeupPending /* don't miss the wakeup from EMSTATE_HALTED! */
1758	&& VM_FF_ISPENDING(pVM, VM_FF_CHECK_VM_STATE))
1759	{
1760	VMSTATE enmState = VMR3GetState(pVM);
1761	switch (enmState)
1762	{
1763	case VMSTATE_FATAL_ERROR:
1764	case VMSTATE_FATAL_ERROR_LS:
1765	Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
1766	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1767	return VINF_EM_SUSPEND;
1768
1769	case VMSTATE_DESTROYING:
1770	Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
1771	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1772	return VINF_EM_TERMINATE;
1773
1774	default:
1775	AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
1776	}
1777	}
1778
1779	/*
1780	* Out of memory? Since most of our fellow high priority actions may cause us
1781	* to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
1782	* at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
1783	* than us since we can terminate without allocating more memory.
1784	*/
1785	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1786	{
1787	rc2 = PGMR3PhysAllocateHandyPages(pVM);
1788	UPDATE_RC();
1789	if (rc == VINF_EM_NO_MEMORY)
1790	return rc;
1791	}
1792
1793	/*
1794	* If the virtual sync clock is still stopped, make TM restart it.
1795	*/
1796	if (VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
1797	TMR3VirtualSyncFF(pVM, pVCpu);
1798
1799	#ifdef DEBUG
1800	/*
1801	* Debug, pause the VM.
1802	*/
1803	if (VM_FF_ISPENDING(pVM, VM_FF_DEBUG_SUSPEND))
1804	{
1805	VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
1806	Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
1807	return VINF_EM_SUSPEND;
1808	}
1809	#endif
1810
1811	/* check that we got them all */
1812	AssertCompile(VM_FF_HIGH_PRIORITY_PRE_MASK == (VM_FF_TM_VIRTUAL_SYNC \| VM_FF_DBGF \| VM_FF_CHECK_VM_STATE \| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS));
1813	AssertCompile(VMCPU_FF_HIGH_PRIORITY_PRE_MASK == (VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_INHIBIT_INTERRUPTS));
1814	}
1815
1816	#undef UPDATE_RC
1817	Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1818	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1819	Assert(rcIrq == VINF_SUCCESS \|\| rcIrq == rc);
1820	return rc;
1821	}
1822
1823
1824	/**
1825	* Check if the preset execution time cap restricts guest execution scheduling.
1826	*
1827	* @returns true if allowed, false otherwise
1828	* @param pVM Pointer to the VM.
1829	* @param pVCpu Pointer to the VMCPU.
1830	*
1831	*/
1832	VMMR3DECL(bool) EMR3IsExecutionAllowed(PVM pVM, PVMCPU pVCpu)
1833	{
1834	uint64_t u64UserTime, u64KernelTime;
1835
1836	if ( pVM->uCpuExecutionCap != 100
1837	&& RT_SUCCESS(RTThreadGetExecutionTimeMilli(&u64KernelTime, &u64UserTime)))
1838	{
1839	uint64_t u64TimeNow = RTTimeMilliTS();
1840	if (pVCpu->em.s.u64TimeSliceStart + EM_TIME_SLICE < u64TimeNow)
1841	{
1842	/* New time slice. */
1843	pVCpu->em.s.u64TimeSliceStart = u64TimeNow;
1844	pVCpu->em.s.u64TimeSliceStartExec = u64KernelTime + u64UserTime;
1845	pVCpu->em.s.u64TimeSliceExec = 0;
1846	}
1847	pVCpu->em.s.u64TimeSliceExec = u64KernelTime + u64UserTime - pVCpu->em.s.u64TimeSliceStartExec;
1848
1849	Log2(("emR3IsExecutionAllowed: start=%RX64 startexec=%RX64 exec=%RX64 (cap=%x)\n", pVCpu->em.s.u64TimeSliceStart, pVCpu->em.s.u64TimeSliceStartExec, pVCpu->em.s.u64TimeSliceExec, (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100));
1850	if (pVCpu->em.s.u64TimeSliceExec >= (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100)
1851	return false;
1852	}
1853	return true;
1854	}
1855
1856
1857	/**
1858	* Execute VM.
1859	*
1860	* This function is the main loop of the VM. The emulation thread
1861	* calls this function when the VM has been successfully constructed
1862	* and we're ready for executing the VM.
1863	*
1864	* Returning from this function means that the VM is turned off or
1865	* suspended (state already saved) and deconstruction is next in line.
1866	*
1867	* All interaction from other thread are done using forced actions
1868	* and signaling of the wait object.
1869	*
1870	* @returns VBox status code, informational status codes may indicate failure.
1871	* @param pVM Pointer to the VM.
1872	* @param pVCpu Pointer to the VMCPU.
1873	*/
1874	VMMR3DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu)
1875	{
1876	Log(("EMR3ExecuteVM: pVM=%p enmVMState=%d (%s) enmState=%d (%s) enmPrevState=%d (%s) fForceRAW=%RTbool\n",
1877	pVM,
1878	pVM->enmVMState, VMR3GetStateName(pVM->enmVMState),
1879	pVCpu->em.s.enmState, emR3GetStateName(pVCpu->em.s.enmState),
1880	pVCpu->em.s.enmPrevState, emR3GetStateName(pVCpu->em.s.enmPrevState),
1881	pVCpu->em.s.fForceRAW));
1882	VM_ASSERT_EMT(pVM);
1883	AssertMsg( pVCpu->em.s.enmState == EMSTATE_NONE
1884	\|\| pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI
1885	\|\| pVCpu->em.s.enmState == EMSTATE_SUSPENDED,
1886	("%s\n", emR3GetStateName(pVCpu->em.s.enmState)));
1887
1888	int rc = setjmp(pVCpu->em.s.u.FatalLongJump);
1889	if (rc == 0)
1890	{
1891	/*
1892	* Start the virtual time.
1893	*/
1894	TMR3NotifyResume(pVM, pVCpu);
1895
1896	/*
1897	* The Outer Main Loop.
1898	*/
1899	bool fFFDone = false;
1900
1901	/* Reschedule right away to start in the right state. */
1902	rc = VINF_SUCCESS;
1903
1904	/* If resuming after a pause or a state load, restore the previous
1905	state or else we'll start executing code. Else, just reschedule. */
1906	if ( pVCpu->em.s.enmState == EMSTATE_SUSPENDED
1907	&& ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
1908	\|\| pVCpu->em.s.enmPrevState == EMSTATE_HALTED))
1909	pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
1910	else
1911	pVCpu->em.s.enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1912
1913	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
1914	for (;;)
1915	{
1916	/*
1917	* Before we can schedule anything (we're here because
1918	* scheduling is required) we must service any pending
1919	* forced actions to avoid any pending action causing
1920	* immediate rescheduling upon entering an inner loop
1921	*
1922	* Do forced actions.
1923	*/
1924	if ( !fFFDone
1925	&& rc != VINF_EM_TERMINATE
1926	&& rc != VINF_EM_OFF
1927	&& ( VM_FF_ISPENDING(pVM, VM_FF_ALL_REM_MASK)
1928	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_REM_MASK)))
1929	{
1930	rc = emR3ForcedActions(pVM, pVCpu, rc);
1931	VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
1932	if ( ( rc == VINF_EM_RESCHEDULE_REM
1933	\|\| rc == VINF_EM_RESCHEDULE_HWACC)
1934	&& pVCpu->em.s.fForceRAW)
1935	rc = VINF_EM_RESCHEDULE_RAW;
1936	}
1937	else if (fFFDone)
1938	fFFDone = false;
1939
1940	/*
1941	* Now what to do?
1942	*/
1943	Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
1944	EMSTATE const enmOldState = pVCpu->em.s.enmState;
1945	switch (rc)
1946	{
1947	/*
1948	* Keep doing what we're currently doing.
1949	*/
1950	case VINF_SUCCESS:
1951	break;
1952
1953	/*
1954	* Reschedule - to raw-mode execution.
1955	*/
1956	case VINF_EM_RESCHEDULE_RAW:
1957	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", enmOldState, EMSTATE_RAW));
1958	pVCpu->em.s.enmState = EMSTATE_RAW;
1959	break;
1960
1961	/*
1962	* Reschedule - to hardware accelerated raw-mode execution.
1963	*/
1964	case VINF_EM_RESCHEDULE_HWACC:
1965	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", enmOldState, EMSTATE_HWACC));
1966	Assert(!pVCpu->em.s.fForceRAW);
1967	pVCpu->em.s.enmState = EMSTATE_HWACC;
1968	break;
1969
1970	/*
1971	* Reschedule - to recompiled execution.
1972	*/
1973	case VINF_EM_RESCHEDULE_REM:
1974	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", enmOldState, EMSTATE_REM));
1975	pVCpu->em.s.enmState = EMSTATE_REM;
1976	break;
1977
1978	/*
1979	* Resume.
1980	*/
1981	case VINF_EM_RESUME:
1982	Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", enmOldState));
1983	/* Don't reschedule in the halted or wait for SIPI case. */
1984	if ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
1985	\|\| pVCpu->em.s.enmPrevState == EMSTATE_HALTED)
1986	{
1987	pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
1988	break;
1989	}
1990	/* fall through and get scheduled. */
1991
1992	/*
1993	* Reschedule.
1994	*/
1995	case VINF_EM_RESCHEDULE:
1996	{
1997	EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1998	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", enmOldState, enmState, emR3GetStateName(enmState)));
1999	pVCpu->em.s.enmState = enmState;
2000	break;
2001	}
2002
2003	/*
2004	* Halted.
2005	*/
2006	case VINF_EM_HALT:
2007	Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", enmOldState, EMSTATE_HALTED));
2008	pVCpu->em.s.enmState = EMSTATE_HALTED;
2009	break;
2010
2011	/*
2012	* Switch to the wait for SIPI state (application processor only)
2013	*/
2014	case VINF_EM_WAIT_SIPI:
2015	Assert(pVCpu->idCpu != 0);
2016	Log2(("EMR3ExecuteVM: VINF_EM_WAIT_SIPI: %d -> %d\n", enmOldState, EMSTATE_WAIT_SIPI));
2017	pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
2018	break;
2019
2020
2021	/*
2022	* Suspend.
2023	*/
2024	case VINF_EM_SUSPEND:
2025	Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", enmOldState, EMSTATE_SUSPENDED));
2026	Assert(enmOldState != EMSTATE_SUSPENDED);
2027	pVCpu->em.s.enmPrevState = enmOldState;
2028	pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2029	break;
2030
2031	/*
2032	* Reset.
2033	* We might end up doing a double reset for now, we'll have to clean up the mess later.
2034	*/
2035	case VINF_EM_RESET:
2036	{
2037	if (pVCpu->idCpu == 0)
2038	{
2039	EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
2040	Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", enmOldState, enmState, emR3GetStateName(enmState)));
2041	pVCpu->em.s.enmState = enmState;
2042	}
2043	else
2044	{
2045	/* All other VCPUs go into the wait for SIPI state. */
2046	pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
2047	}
2048	break;
2049	}
2050
2051	/*
2052	* Power Off.
2053	*/
2054	case VINF_EM_OFF:
2055	pVCpu->em.s.enmState = EMSTATE_TERMINATING;
2056	Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", enmOldState, EMSTATE_TERMINATING));
2057	TMR3NotifySuspend(pVM, pVCpu);
2058	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2059	return rc;
2060
2061	/*
2062	* Terminate the VM.
2063	*/
2064	case VINF_EM_TERMINATE:
2065	pVCpu->em.s.enmState = EMSTATE_TERMINATING;
2066	Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", enmOldState, EMSTATE_TERMINATING));
2067	if (pVM->enmVMState < VMSTATE_DESTROYING) /* ugly */
2068	TMR3NotifySuspend(pVM, pVCpu);
2069	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2070	return rc;
2071
2072
2073	/*
2074	* Out of memory, suspend the VM and stuff.
2075	*/
2076	case VINF_EM_NO_MEMORY:
2077	Log2(("EMR3ExecuteVM: VINF_EM_NO_MEMORY: %d -> %d\n", enmOldState, EMSTATE_SUSPENDED));
2078	Assert(enmOldState != EMSTATE_SUSPENDED);
2079	pVCpu->em.s.enmPrevState = enmOldState;
2080	pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2081	TMR3NotifySuspend(pVM, pVCpu);
2082	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2083
2084	rc = VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_SUSPEND, "HostMemoryLow",
2085	N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
2086	if (rc != VINF_EM_SUSPEND)
2087	{
2088	if (RT_SUCCESS_NP(rc))
2089	{
2090	AssertLogRelMsgFailed(("%Rrc\n", rc));
2091	rc = VERR_EM_INTERNAL_ERROR;
2092	}
2093	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2094	}
2095	return rc;
2096
2097	/*
2098	* Guest debug events.
2099	*/
2100	case VINF_EM_DBG_STEPPED:
2101	AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
2102	case VINF_EM_DBG_STOP:
2103	case VINF_EM_DBG_BREAKPOINT:
2104	case VINF_EM_DBG_STEP:
2105	if (enmOldState == EMSTATE_RAW)
2106	{
2107	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_RAW));
2108	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
2109	}
2110	else
2111	{
2112	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_REM));
2113	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
2114	}
2115	break;
2116
2117	/*
2118	* Hypervisor debug events.
2119	*/
2120	case VINF_EM_DBG_HYPER_STEPPED:
2121	case VINF_EM_DBG_HYPER_BREAKPOINT:
2122	case VINF_EM_DBG_HYPER_ASSERTION:
2123	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_HYPER));
2124	pVCpu->em.s.enmState = EMSTATE_DEBUG_HYPER;
2125	break;
2126
2127	/*
2128	* Guru mediations.
2129	*/
2130	case VERR_VMM_RING0_ASSERTION:
2131	Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, enmOldState, EMSTATE_GURU_MEDITATION));
2132	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2133	break;
2134
2135	/*
2136	* Any error code showing up here other than the ones we
2137	* know and process above are considered to be FATAL.
2138	*
2139	* Unknown warnings and informational status codes are also
2140	* included in this.
2141	*/
2142	default:
2143	if (RT_SUCCESS_NP(rc))
2144	{
2145	AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
2146	rc = VERR_EM_INTERNAL_ERROR;
2147	}
2148	Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, enmOldState, EMSTATE_GURU_MEDITATION));
2149	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2150	break;
2151	}
2152
2153	/*
2154	* Act on state transition.
2155	*/
2156	EMSTATE const enmNewState = pVCpu->em.s.enmState;
2157	if (enmOldState != enmNewState)
2158	{
2159	VBOXVMM_EM_STATE_CHANGED(pVCpu, enmOldState, enmNewState, rc);
2160
2161	/* Clear MWait flags. */
2162	if ( enmOldState == EMSTATE_HALTED
2163	&& (pVCpu->em.s.MWait.fWait & EMMWAIT_FLAG_ACTIVE)
2164	&& ( enmNewState == EMSTATE_RAW
2165	\|\| enmNewState == EMSTATE_HWACC
2166	\|\| enmNewState == EMSTATE_REM
2167	\|\| enmNewState == EMSTATE_DEBUG_GUEST_RAW
2168	\|\| enmNewState == EMSTATE_DEBUG_GUEST_HWACC
2169	\|\| enmNewState == EMSTATE_DEBUG_GUEST_REM) )
2170	{
2171	LogFlow(("EMR3ExecuteVM: Clearing MWAIT\n"));
2172	pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0);
2173	}
2174	}
2175	else
2176	VBOXVMM_EM_STATE_UNCHANGED(pVCpu, enmNewState, rc);
2177
2178	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x); /* (skip this in release) */
2179	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2180
2181	/*
2182	* Act on the new state.
2183	*/
2184	switch (enmNewState)
2185	{
2186	/*
2187	* Execute raw.
2188	*/
2189	case EMSTATE_RAW:
2190	#ifndef IEM_VERIFICATION_MODE /* remove later */
2191	rc = emR3RawExecute(pVM, pVCpu, &fFFDone);
2192	break;
2193	#endif
2194
2195	/*
2196	* Execute hardware accelerated raw.
2197	*/
2198	case EMSTATE_HWACC:
2199	#ifndef IEM_VERIFICATION_MODE /* remove later */
2200	rc = emR3HwAccExecute(pVM, pVCpu, &fFFDone);
2201	break;
2202	#endif
2203
2204	/*
2205	* Execute recompiled.
2206	*/
2207	case EMSTATE_REM:
2208	#ifdef IEM_VERIFICATION_MODE
2209	# if 1
2210	rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu)); fFFDone = false;
2211	# else
2212	rc = VBOXSTRICTRC_TODO(REMR3EmulateInstruction(pVM, pVCpu)); fFFDone = false;
2213	if (rc == VINF_EM_RESCHEDULE)
2214	rc = VINF_SUCCESS;
2215	# endif
2216	#else
2217	rc = emR3RemExecute(pVM, pVCpu, &fFFDone);
2218	#endif
2219	Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
2220	break;
2221
2222	/*
2223	* Application processor execution halted until SIPI.
2224	*/
2225	case EMSTATE_WAIT_SIPI:
2226	/* no break */
2227	/*
2228	* hlt - execution halted until interrupt.
2229	*/
2230	case EMSTATE_HALTED:
2231	{
2232	STAM_REL_PROFILE_START(&pVCpu->em.s.StatHalted, y);
2233	/* MWAIT has a special extension where it's woken up when
2234	an interrupt is pending even when IF=0. */
2235	if ( (pVCpu->em.s.MWait.fWait & (EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0))
2236	== (EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0))
2237	{
2238	rc = VMR3WaitHalted(pVM, pVCpu, false /fIgnoreInterrupts/);
2239	if ( rc == VINF_SUCCESS
2240	&& VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC))
2241	{
2242	Log(("EMR3ExecuteVM: Triggering reschedule on pending IRQ after MWAIT\n"));
2243	rc = VINF_EM_RESCHEDULE;
2244	}
2245	}
2246	else
2247	rc = VMR3WaitHalted(pVM, pVCpu, !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
2248
2249	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHalted, y);
2250	break;
2251	}
2252
2253	/*
2254	* Suspended - return to VM.cpp.
2255	*/
2256	case EMSTATE_SUSPENDED:
2257	TMR3NotifySuspend(pVM, pVCpu);
2258	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2259	Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2260	return VINF_EM_SUSPEND;
2261
2262	/*
2263	* Debugging in the guest.
2264	*/
2265	case EMSTATE_DEBUG_GUEST_REM:
2266	case EMSTATE_DEBUG_GUEST_RAW:
2267	TMR3NotifySuspend(pVM, pVCpu);
2268	rc = emR3Debug(pVM, pVCpu, rc);
2269	TMR3NotifyResume(pVM, pVCpu);
2270	Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2271	break;
2272
2273	/*
2274	* Debugging in the hypervisor.
2275	*/
2276	case EMSTATE_DEBUG_HYPER:
2277	{
2278	TMR3NotifySuspend(pVM, pVCpu);
2279	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2280
2281	rc = emR3Debug(pVM, pVCpu, rc);
2282	Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2283	if (rc != VINF_SUCCESS)
2284	{
2285	/* switch to guru meditation mode */
2286	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2287	VMMR3FatalDump(pVM, pVCpu, rc);
2288	Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2289	return rc;
2290	}
2291
2292	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2293	TMR3NotifyResume(pVM, pVCpu);
2294	break;
2295	}
2296
2297	/*
2298	* Guru meditation takes place in the debugger.
2299	*/
2300	case EMSTATE_GURU_MEDITATION:
2301	{
2302	TMR3NotifySuspend(pVM, pVCpu);
2303	VMMR3FatalDump(pVM, pVCpu, rc);
2304	emR3Debug(pVM, pVCpu, rc);
2305	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2306	Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2307	return rc;
2308	}
2309
2310	/*
2311	* The states we don't expect here.
2312	*/
2313	case EMSTATE_NONE:
2314	case EMSTATE_TERMINATING:
2315	default:
2316	AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVCpu->em.s.enmState));
2317	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2318	TMR3NotifySuspend(pVM, pVCpu);
2319	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2320	Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2321	return VERR_EM_INTERNAL_ERROR;
2322	}
2323	} /* The Outer Main Loop */
2324	}
2325	else
2326	{
2327	/*
2328	* Fatal error.
2329	*/
2330	Log(("EMR3ExecuteVM: returns %Rrc because of longjmp / fatal error; (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2331	TMR3NotifySuspend(pVM, pVCpu);
2332	VMMR3FatalDump(pVM, pVCpu, rc);
2333	emR3Debug(pVM, pVCpu, rc);
2334	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2335	/** @todo change the VM state! */
2336	return rc;
2337	}
2338
2339	/* (won't ever get here). */
2340	AssertFailed();
2341	}
2342
2343	/**
2344	* Notify EM of a state change (used by FTM)
2345	*
2346	* @param pVM Pointer to the VM.
2347	*/
2348	VMMR3DECL(int) EMR3NotifySuspend(PVM pVM)
2349	{
2350	PVMCPU pVCpu = VMMGetCpu(pVM);
2351
2352	TMR3NotifySuspend(pVM, pVCpu); /* Stop the virtual time. */
2353	pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
2354	pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2355	return VINF_SUCCESS;
2356	}
2357
2358	/**
2359	* Notify EM of a state change (used by FTM)
2360	*
2361	* @param pVM Pointer to the VM.
2362	*/
2363	VMMR3DECL(int) EMR3NotifyResume(PVM pVM)
2364	{
2365	PVMCPU pVCpu = VMMGetCpu(pVM);
2366	EMSTATE enmCurState = pVCpu->em.s.enmState;
2367
2368	TMR3NotifyResume(pVM, pVCpu); /* Resume the virtual time. */
2369	pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2370	pVCpu->em.s.enmPrevState = enmCurState;
2371	return VINF_SUCCESS;
2372	}

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source: vbox/trunk/src/VBox/VMM/VMMR3/EM.cpp@ 43346

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