VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/EM.cpp@ 47682

Last change on this file since 47682 was 47671, checked in by vboxsync, 11 years ago

VMM: More debugging related stuff.

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1/* $Id: EM.cpp 47671 2013-08-12 11:16:55Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_em EM - The Execution Monitor / Manager
19 *
20 * The Execution Monitor/Manager is responsible for running the VM, scheduling
21 * the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
22 * Interpreted), and keeping the CPU states in sync. The function
23 * EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
24 * modes has different inner loops (emR3RawExecute, emR3HmExecute, and
25 * emR3RemExecute).
26 *
27 * The interpreted execution is only used to avoid switching between
28 * raw-mode/hm and the recompiler when fielding virtualization traps/faults.
29 * The interpretation is thus implemented as part of EM.
30 *
31 * @see grp_em
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_EM
38#include <VBox/vmm/em.h>
39#include <VBox/vmm/vmm.h>
40#include <VBox/vmm/patm.h>
41#include <VBox/vmm/csam.h>
42#include <VBox/vmm/selm.h>
43#include <VBox/vmm/trpm.h>
44#include <VBox/vmm/iem.h>
45#include <VBox/vmm/iom.h>
46#include <VBox/vmm/dbgf.h>
47#include <VBox/vmm/pgm.h>
48#ifdef VBOX_WITH_REM
49# include <VBox/vmm/rem.h>
50#endif
51#include <VBox/vmm/tm.h>
52#include <VBox/vmm/mm.h>
53#include <VBox/vmm/ssm.h>
54#include <VBox/vmm/pdmapi.h>
55#include <VBox/vmm/pdmcritsect.h>
56#include <VBox/vmm/pdmqueue.h>
57#include <VBox/vmm/hm.h>
58#include <VBox/vmm/patm.h>
59#include "EMInternal.h"
60#include <VBox/vmm/vm.h>
61#include <VBox/vmm/uvm.h>
62#include <VBox/vmm/cpumdis.h>
63#include <VBox/dis.h>
64#include <VBox/disopcode.h>
65#include <VBox/vmm/dbgf.h>
66#include "VMMTracing.h"
67
68#include <iprt/asm.h>
69#include <iprt/string.h>
70#include <iprt/stream.h>
71#include <iprt/thread.h>
72
73
74/*******************************************************************************
75* Defined Constants And Macros *
76*******************************************************************************/
77#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
78#define EM_NOTIFY_HM
79#endif
80
81
82/*******************************************************************************
83* Internal Functions *
84*******************************************************************************/
85static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
86static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
87#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
88static const char *emR3GetStateName(EMSTATE enmState);
89#endif
90static VBOXSTRICTRC emR3Debug(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc);
91static int emR3RemStep(PVM pVM, PVMCPU pVCpu);
92static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
93int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
94
95
96/**
97 * Initializes the EM.
98 *
99 * @returns VBox status code.
100 * @param pVM Pointer to the VM.
101 */
102VMMR3_INT_DECL(int) EMR3Init(PVM pVM)
103{
104 LogFlow(("EMR3Init\n"));
105 /*
106 * Assert alignment and sizes.
107 */
108 AssertCompileMemberAlignment(VM, em.s, 32);
109 AssertCompile(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
110 AssertCompile(sizeof(pVM->aCpus[0].em.s.u.FatalLongJump) <= sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump));
111
112 /*
113 * Init the structure.
114 */
115 pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
116 PCFGMNODE pCfgRoot = CFGMR3GetRoot(pVM);
117 PCFGMNODE pCfgEM = CFGMR3GetChild(pCfgRoot, "EM");
118
119 bool fEnabled;
120 int rc = CFGMR3QueryBoolDef(pCfgRoot, "RawR3Enabled", &fEnabled, true);
121 AssertLogRelRCReturn(rc, rc);
122 pVM->fRecompileUser = !fEnabled;
123
124 rc = CFGMR3QueryBoolDef(pCfgRoot, "RawR0Enabled", &fEnabled, true);
125 AssertLogRelRCReturn(rc, rc);
126 pVM->fRecompileSupervisor = !fEnabled;
127
128#ifdef VBOX_WITH_RAW_RING1
129 rc = CFGMR3QueryBoolDef(pCfgRoot, "RawR1Enabled", &pVM->fRawRing1Enabled, false);
130 AssertLogRelRCReturn(rc, rc);
131#else
132 pVM->fRawRing1Enabled = false; /* Disabled by default. */
133#endif
134
135 rc = CFGMR3QueryBoolDef(pCfgEM, "IemExecutesAll", &pVM->em.s.fIemExecutesAll, false);
136 AssertLogRelRCReturn(rc, rc);
137
138 Log(("EMR3Init: fRecompileUser=%RTbool fRecompileSupervisor=%RTbool fRawRing1Enabled=%RTbool fIemExecutesAll=%RTbool\n",
139 pVM->fRecompileUser, pVM->fRecompileSupervisor, pVM->fRawRing1Enabled, pVM->em.s.fIemExecutesAll));
140
141#ifdef VBOX_WITH_REM
142 /*
143 * Initialize the REM critical section.
144 */
145 AssertCompileMemberAlignment(EM, CritSectREM, sizeof(uintptr_t));
146 rc = PDMR3CritSectInit(pVM, &pVM->em.s.CritSectREM, RT_SRC_POS, "EM-REM");
147 AssertRCReturn(rc, rc);
148#endif
149
150 /*
151 * Saved state.
152 */
153 rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
154 NULL, NULL, NULL,
155 NULL, emR3Save, NULL,
156 NULL, emR3Load, NULL);
157 if (RT_FAILURE(rc))
158 return rc;
159
160 for (VMCPUID i = 0; i < pVM->cCpus; i++)
161 {
162 PVMCPU pVCpu = &pVM->aCpus[i];
163
164 pVCpu->em.s.offVMCPU = RT_OFFSETOF(VMCPU, em.s);
165
166 pVCpu->em.s.enmState = (i == 0) ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
167 pVCpu->em.s.enmPrevState = EMSTATE_NONE;
168 pVCpu->em.s.fForceRAW = false;
169
170 pVCpu->em.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
171#ifdef VBOX_WITH_RAW_MODE
172 if (!HMIsEnabled(pVM))
173 {
174 pVCpu->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
175 AssertMsg(pVCpu->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
176 }
177#endif
178
179 /* Force reset of the time slice. */
180 pVCpu->em.s.u64TimeSliceStart = 0;
181
182# define EM_REG_COUNTER(a, b, c) \
183 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
184 AssertRC(rc);
185
186# define EM_REG_COUNTER_USED(a, b, c) \
187 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, c, b, i); \
188 AssertRC(rc);
189
190# define EM_REG_PROFILE(a, b, c) \
191 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
192 AssertRC(rc);
193
194# define EM_REG_PROFILE_ADV(a, b, c) \
195 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
196 AssertRC(rc);
197
198 /*
199 * Statistics.
200 */
201#ifdef VBOX_WITH_STATISTICS
202 PEMSTATS pStats;
203 rc = MMHyperAlloc(pVM, sizeof(*pStats), 0, MM_TAG_EM, (void **)&pStats);
204 if (RT_FAILURE(rc))
205 return rc;
206
207 pVCpu->em.s.pStatsR3 = pStats;
208 pVCpu->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
209 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
210
211 EM_REG_PROFILE(&pStats->StatRZEmulate, "/EM/CPU%d/RZ/Interpret", "Profiling of EMInterpretInstruction.");
212 EM_REG_PROFILE(&pStats->StatR3Emulate, "/EM/CPU%d/R3/Interpret", "Profiling of EMInterpretInstruction.");
213
214 EM_REG_PROFILE(&pStats->StatRZInterpretSucceeded, "/EM/CPU%d/RZ/Interpret/Success", "The number of times an instruction was successfully interpreted.");
215 EM_REG_PROFILE(&pStats->StatR3InterpretSucceeded, "/EM/CPU%d/R3/Interpret/Success", "The number of times an instruction was successfully interpreted.");
216
217 EM_REG_COUNTER_USED(&pStats->StatRZAnd, "/EM/CPU%d/RZ/Interpret/Success/And", "The number of times AND was successfully interpreted.");
218 EM_REG_COUNTER_USED(&pStats->StatR3And, "/EM/CPU%d/R3/Interpret/Success/And", "The number of times AND was successfully interpreted.");
219 EM_REG_COUNTER_USED(&pStats->StatRZAdd, "/EM/CPU%d/RZ/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
220 EM_REG_COUNTER_USED(&pStats->StatR3Add, "/EM/CPU%d/R3/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
221 EM_REG_COUNTER_USED(&pStats->StatRZAdc, "/EM/CPU%d/RZ/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
222 EM_REG_COUNTER_USED(&pStats->StatR3Adc, "/EM/CPU%d/R3/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
223 EM_REG_COUNTER_USED(&pStats->StatRZSub, "/EM/CPU%d/RZ/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
224 EM_REG_COUNTER_USED(&pStats->StatR3Sub, "/EM/CPU%d/R3/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
225 EM_REG_COUNTER_USED(&pStats->StatRZCpuId, "/EM/CPU%d/RZ/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
226 EM_REG_COUNTER_USED(&pStats->StatR3CpuId, "/EM/CPU%d/R3/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
227 EM_REG_COUNTER_USED(&pStats->StatRZDec, "/EM/CPU%d/RZ/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
228 EM_REG_COUNTER_USED(&pStats->StatR3Dec, "/EM/CPU%d/R3/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
229 EM_REG_COUNTER_USED(&pStats->StatRZHlt, "/EM/CPU%d/RZ/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
230 EM_REG_COUNTER_USED(&pStats->StatR3Hlt, "/EM/CPU%d/R3/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
231 EM_REG_COUNTER_USED(&pStats->StatRZInc, "/EM/CPU%d/RZ/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
232 EM_REG_COUNTER_USED(&pStats->StatR3Inc, "/EM/CPU%d/R3/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
233 EM_REG_COUNTER_USED(&pStats->StatRZInvlPg, "/EM/CPU%d/RZ/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
234 EM_REG_COUNTER_USED(&pStats->StatR3InvlPg, "/EM/CPU%d/R3/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
235 EM_REG_COUNTER_USED(&pStats->StatRZIret, "/EM/CPU%d/RZ/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
236 EM_REG_COUNTER_USED(&pStats->StatR3Iret, "/EM/CPU%d/R3/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
237 EM_REG_COUNTER_USED(&pStats->StatRZLLdt, "/EM/CPU%d/RZ/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
238 EM_REG_COUNTER_USED(&pStats->StatR3LLdt, "/EM/CPU%d/R3/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
239 EM_REG_COUNTER_USED(&pStats->StatRZLIdt, "/EM/CPU%d/RZ/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
240 EM_REG_COUNTER_USED(&pStats->StatR3LIdt, "/EM/CPU%d/R3/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
241 EM_REG_COUNTER_USED(&pStats->StatRZLGdt, "/EM/CPU%d/RZ/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
242 EM_REG_COUNTER_USED(&pStats->StatR3LGdt, "/EM/CPU%d/R3/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
243 EM_REG_COUNTER_USED(&pStats->StatRZMov, "/EM/CPU%d/RZ/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
244 EM_REG_COUNTER_USED(&pStats->StatR3Mov, "/EM/CPU%d/R3/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
245 EM_REG_COUNTER_USED(&pStats->StatRZMovCRx, "/EM/CPU%d/RZ/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
246 EM_REG_COUNTER_USED(&pStats->StatR3MovCRx, "/EM/CPU%d/R3/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
247 EM_REG_COUNTER_USED(&pStats->StatRZMovDRx, "/EM/CPU%d/RZ/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
248 EM_REG_COUNTER_USED(&pStats->StatR3MovDRx, "/EM/CPU%d/R3/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
249 EM_REG_COUNTER_USED(&pStats->StatRZOr, "/EM/CPU%d/RZ/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
250 EM_REG_COUNTER_USED(&pStats->StatR3Or, "/EM/CPU%d/R3/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
251 EM_REG_COUNTER_USED(&pStats->StatRZPop, "/EM/CPU%d/RZ/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
252 EM_REG_COUNTER_USED(&pStats->StatR3Pop, "/EM/CPU%d/R3/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
253 EM_REG_COUNTER_USED(&pStats->StatRZRdtsc, "/EM/CPU%d/RZ/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
254 EM_REG_COUNTER_USED(&pStats->StatR3Rdtsc, "/EM/CPU%d/R3/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
255 EM_REG_COUNTER_USED(&pStats->StatRZRdpmc, "/EM/CPU%d/RZ/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
256 EM_REG_COUNTER_USED(&pStats->StatR3Rdpmc, "/EM/CPU%d/R3/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
257 EM_REG_COUNTER_USED(&pStats->StatRZSti, "/EM/CPU%d/RZ/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
258 EM_REG_COUNTER_USED(&pStats->StatR3Sti, "/EM/CPU%d/R3/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
259 EM_REG_COUNTER_USED(&pStats->StatRZXchg, "/EM/CPU%d/RZ/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
260 EM_REG_COUNTER_USED(&pStats->StatR3Xchg, "/EM/CPU%d/R3/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
261 EM_REG_COUNTER_USED(&pStats->StatRZXor, "/EM/CPU%d/RZ/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
262 EM_REG_COUNTER_USED(&pStats->StatR3Xor, "/EM/CPU%d/R3/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
263 EM_REG_COUNTER_USED(&pStats->StatRZMonitor, "/EM/CPU%d/RZ/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
264 EM_REG_COUNTER_USED(&pStats->StatR3Monitor, "/EM/CPU%d/R3/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
265 EM_REG_COUNTER_USED(&pStats->StatRZMWait, "/EM/CPU%d/RZ/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
266 EM_REG_COUNTER_USED(&pStats->StatR3MWait, "/EM/CPU%d/R3/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
267 EM_REG_COUNTER_USED(&pStats->StatRZBtr, "/EM/CPU%d/RZ/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
268 EM_REG_COUNTER_USED(&pStats->StatR3Btr, "/EM/CPU%d/R3/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
269 EM_REG_COUNTER_USED(&pStats->StatRZBts, "/EM/CPU%d/RZ/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
270 EM_REG_COUNTER_USED(&pStats->StatR3Bts, "/EM/CPU%d/R3/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
271 EM_REG_COUNTER_USED(&pStats->StatRZBtc, "/EM/CPU%d/RZ/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
272 EM_REG_COUNTER_USED(&pStats->StatR3Btc, "/EM/CPU%d/R3/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
273 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
274 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg, "/EM/CPU%d/R3/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
275 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
276 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg8b, "/EM/CPU%d/R3/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
277 EM_REG_COUNTER_USED(&pStats->StatRZXAdd, "/EM/CPU%d/RZ/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
278 EM_REG_COUNTER_USED(&pStats->StatR3XAdd, "/EM/CPU%d/R3/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
279 EM_REG_COUNTER_USED(&pStats->StatR3Rdmsr, "/EM/CPU%d/R3/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
280 EM_REG_COUNTER_USED(&pStats->StatRZRdmsr, "/EM/CPU%d/RZ/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
281 EM_REG_COUNTER_USED(&pStats->StatR3Wrmsr, "/EM/CPU%d/R3/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
282 EM_REG_COUNTER_USED(&pStats->StatRZWrmsr, "/EM/CPU%d/RZ/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
283 EM_REG_COUNTER_USED(&pStats->StatR3StosWD, "/EM/CPU%d/R3/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
284 EM_REG_COUNTER_USED(&pStats->StatRZStosWD, "/EM/CPU%d/RZ/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
285 EM_REG_COUNTER_USED(&pStats->StatRZWbInvd, "/EM/CPU%d/RZ/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
286 EM_REG_COUNTER_USED(&pStats->StatR3WbInvd, "/EM/CPU%d/R3/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
287 EM_REG_COUNTER_USED(&pStats->StatRZLmsw, "/EM/CPU%d/RZ/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
288 EM_REG_COUNTER_USED(&pStats->StatR3Lmsw, "/EM/CPU%d/R3/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
289 EM_REG_COUNTER_USED(&pStats->StatRZSmsw, "/EM/CPU%d/RZ/Interpret/Success/Smsw", "The number of times SMSW was successfully interpreted.");
290 EM_REG_COUNTER_USED(&pStats->StatR3Smsw, "/EM/CPU%d/R3/Interpret/Success/Smsw", "The number of times SMSW was successfully interpreted.");
291
292 EM_REG_COUNTER(&pStats->StatRZInterpretFailed, "/EM/CPU%d/RZ/Interpret/Failed", "The number of times an instruction was not interpreted.");
293 EM_REG_COUNTER(&pStats->StatR3InterpretFailed, "/EM/CPU%d/R3/Interpret/Failed", "The number of times an instruction was not interpreted.");
294
295 EM_REG_COUNTER_USED(&pStats->StatRZFailedAnd, "/EM/CPU%d/RZ/Interpret/Failed/And", "The number of times AND was not interpreted.");
296 EM_REG_COUNTER_USED(&pStats->StatR3FailedAnd, "/EM/CPU%d/R3/Interpret/Failed/And", "The number of times AND was not interpreted.");
297 EM_REG_COUNTER_USED(&pStats->StatRZFailedCpuId, "/EM/CPU%d/RZ/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
298 EM_REG_COUNTER_USED(&pStats->StatR3FailedCpuId, "/EM/CPU%d/R3/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
299 EM_REG_COUNTER_USED(&pStats->StatRZFailedDec, "/EM/CPU%d/RZ/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
300 EM_REG_COUNTER_USED(&pStats->StatR3FailedDec, "/EM/CPU%d/R3/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
301 EM_REG_COUNTER_USED(&pStats->StatRZFailedHlt, "/EM/CPU%d/RZ/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
302 EM_REG_COUNTER_USED(&pStats->StatR3FailedHlt, "/EM/CPU%d/R3/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
303 EM_REG_COUNTER_USED(&pStats->StatRZFailedInc, "/EM/CPU%d/RZ/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
304 EM_REG_COUNTER_USED(&pStats->StatR3FailedInc, "/EM/CPU%d/R3/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
305 EM_REG_COUNTER_USED(&pStats->StatRZFailedInvlPg, "/EM/CPU%d/RZ/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
306 EM_REG_COUNTER_USED(&pStats->StatR3FailedInvlPg, "/EM/CPU%d/R3/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
307 EM_REG_COUNTER_USED(&pStats->StatRZFailedIret, "/EM/CPU%d/RZ/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
308 EM_REG_COUNTER_USED(&pStats->StatR3FailedIret, "/EM/CPU%d/R3/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
309 EM_REG_COUNTER_USED(&pStats->StatRZFailedLLdt, "/EM/CPU%d/RZ/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
310 EM_REG_COUNTER_USED(&pStats->StatR3FailedLLdt, "/EM/CPU%d/R3/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
311 EM_REG_COUNTER_USED(&pStats->StatRZFailedLIdt, "/EM/CPU%d/RZ/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
312 EM_REG_COUNTER_USED(&pStats->StatR3FailedLIdt, "/EM/CPU%d/R3/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
313 EM_REG_COUNTER_USED(&pStats->StatRZFailedLGdt, "/EM/CPU%d/RZ/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
314 EM_REG_COUNTER_USED(&pStats->StatR3FailedLGdt, "/EM/CPU%d/R3/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
315 EM_REG_COUNTER_USED(&pStats->StatRZFailedMov, "/EM/CPU%d/RZ/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
316 EM_REG_COUNTER_USED(&pStats->StatR3FailedMov, "/EM/CPU%d/R3/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
317 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovCRx, "/EM/CPU%d/RZ/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
318 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovCRx, "/EM/CPU%d/R3/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
319 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovDRx, "/EM/CPU%d/RZ/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
320 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovDRx, "/EM/CPU%d/R3/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
321 EM_REG_COUNTER_USED(&pStats->StatRZFailedOr, "/EM/CPU%d/RZ/Interpret/Failed/Or", "The number of times OR was not interpreted.");
322 EM_REG_COUNTER_USED(&pStats->StatR3FailedOr, "/EM/CPU%d/R3/Interpret/Failed/Or", "The number of times OR was not interpreted.");
323 EM_REG_COUNTER_USED(&pStats->StatRZFailedPop, "/EM/CPU%d/RZ/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
324 EM_REG_COUNTER_USED(&pStats->StatR3FailedPop, "/EM/CPU%d/R3/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
325 EM_REG_COUNTER_USED(&pStats->StatRZFailedSti, "/EM/CPU%d/RZ/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
326 EM_REG_COUNTER_USED(&pStats->StatR3FailedSti, "/EM/CPU%d/R3/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
327 EM_REG_COUNTER_USED(&pStats->StatRZFailedXchg, "/EM/CPU%d/RZ/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
328 EM_REG_COUNTER_USED(&pStats->StatR3FailedXchg, "/EM/CPU%d/R3/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
329 EM_REG_COUNTER_USED(&pStats->StatRZFailedXor, "/EM/CPU%d/RZ/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
330 EM_REG_COUNTER_USED(&pStats->StatR3FailedXor, "/EM/CPU%d/R3/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
331 EM_REG_COUNTER_USED(&pStats->StatRZFailedMonitor, "/EM/CPU%d/RZ/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
332 EM_REG_COUNTER_USED(&pStats->StatR3FailedMonitor, "/EM/CPU%d/R3/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
333 EM_REG_COUNTER_USED(&pStats->StatRZFailedMWait, "/EM/CPU%d/RZ/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
334 EM_REG_COUNTER_USED(&pStats->StatR3FailedMWait, "/EM/CPU%d/R3/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
335 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdtsc, "/EM/CPU%d/RZ/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
336 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdtsc, "/EM/CPU%d/R3/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
337 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdpmc, "/EM/CPU%d/RZ/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
338 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdpmc, "/EM/CPU%d/R3/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
339 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdmsr, "/EM/CPU%d/RZ/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
340 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdmsr, "/EM/CPU%d/R3/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
341 EM_REG_COUNTER_USED(&pStats->StatRZFailedWrmsr, "/EM/CPU%d/RZ/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
342 EM_REG_COUNTER_USED(&pStats->StatR3FailedWrmsr, "/EM/CPU%d/R3/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
343 EM_REG_COUNTER_USED(&pStats->StatRZFailedLmsw, "/EM/CPU%d/RZ/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
344 EM_REG_COUNTER_USED(&pStats->StatR3FailedLmsw, "/EM/CPU%d/R3/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
345 EM_REG_COUNTER_USED(&pStats->StatRZFailedSmsw, "/EM/CPU%d/RZ/Interpret/Failed/Smsw", "The number of times SMSW was not interpreted.");
346 EM_REG_COUNTER_USED(&pStats->StatR3FailedSmsw, "/EM/CPU%d/R3/Interpret/Failed/Smsw", "The number of times SMSW was not interpreted.");
347
348 EM_REG_COUNTER_USED(&pStats->StatRZFailedMisc, "/EM/CPU%d/RZ/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
349 EM_REG_COUNTER_USED(&pStats->StatR3FailedMisc, "/EM/CPU%d/R3/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
350 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdd, "/EM/CPU%d/RZ/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
351 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdd, "/EM/CPU%d/R3/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
352 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdc, "/EM/CPU%d/RZ/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
353 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdc, "/EM/CPU%d/R3/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
354 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtr, "/EM/CPU%d/RZ/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
355 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtr, "/EM/CPU%d/R3/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
356 EM_REG_COUNTER_USED(&pStats->StatRZFailedBts, "/EM/CPU%d/RZ/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
357 EM_REG_COUNTER_USED(&pStats->StatR3FailedBts, "/EM/CPU%d/R3/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
358 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtc, "/EM/CPU%d/RZ/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
359 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtc, "/EM/CPU%d/R3/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
360 EM_REG_COUNTER_USED(&pStats->StatRZFailedCli, "/EM/CPU%d/RZ/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
361 EM_REG_COUNTER_USED(&pStats->StatR3FailedCli, "/EM/CPU%d/R3/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
362 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
363 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
364 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
365 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg8b, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
366 EM_REG_COUNTER_USED(&pStats->StatRZFailedXAdd, "/EM/CPU%d/RZ/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
367 EM_REG_COUNTER_USED(&pStats->StatR3FailedXAdd, "/EM/CPU%d/R3/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
368 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovNTPS, "/EM/CPU%d/RZ/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
369 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovNTPS, "/EM/CPU%d/R3/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
370 EM_REG_COUNTER_USED(&pStats->StatRZFailedStosWD, "/EM/CPU%d/RZ/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
371 EM_REG_COUNTER_USED(&pStats->StatR3FailedStosWD, "/EM/CPU%d/R3/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
372 EM_REG_COUNTER_USED(&pStats->StatRZFailedSub, "/EM/CPU%d/RZ/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
373 EM_REG_COUNTER_USED(&pStats->StatR3FailedSub, "/EM/CPU%d/R3/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
374 EM_REG_COUNTER_USED(&pStats->StatRZFailedWbInvd, "/EM/CPU%d/RZ/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
375 EM_REG_COUNTER_USED(&pStats->StatR3FailedWbInvd, "/EM/CPU%d/R3/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
376
377 EM_REG_COUNTER_USED(&pStats->StatRZFailedUserMode, "/EM/CPU%d/RZ/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
378 EM_REG_COUNTER_USED(&pStats->StatR3FailedUserMode, "/EM/CPU%d/R3/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
379 EM_REG_COUNTER_USED(&pStats->StatRZFailedPrefix, "/EM/CPU%d/RZ/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
380 EM_REG_COUNTER_USED(&pStats->StatR3FailedPrefix, "/EM/CPU%d/R3/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
381
382 EM_REG_COUNTER_USED(&pStats->StatIoRestarted, "/EM/CPU%d/R3/PrivInst/IoRestarted", "I/O instructions restarted in ring-3.");
383# ifdef VBOX_WITH_FIRST_IEM_STEP
384 EM_REG_COUNTER_USED(&pStats->StatIoIem, "/EM/CPU%d/R3/PrivInst/IoIem", "I/O instructions end to IEM in ring-3.");
385# else
386 EM_REG_COUNTER_USED(&pStats->StatIn, "/EM/CPU%d/R3/PrivInst/In", "Number of in instructions.");
387 EM_REG_COUNTER_USED(&pStats->StatOut, "/EM/CPU%d/R3/PrivInst/Out", "Number of out instructions.");
388# endif
389 EM_REG_COUNTER_USED(&pStats->StatCli, "/EM/CPU%d/R3/PrivInst/Cli", "Number of cli instructions.");
390 EM_REG_COUNTER_USED(&pStats->StatSti, "/EM/CPU%d/R3/PrivInst/Sti", "Number of sli instructions.");
391 EM_REG_COUNTER_USED(&pStats->StatHlt, "/EM/CPU%d/R3/PrivInst/Hlt", "Number of hlt instructions not handled in GC because of PATM.");
392 EM_REG_COUNTER_USED(&pStats->StatInvlpg, "/EM/CPU%d/R3/PrivInst/Invlpg", "Number of invlpg instructions.");
393 EM_REG_COUNTER_USED(&pStats->StatMisc, "/EM/CPU%d/R3/PrivInst/Misc", "Number of misc. instructions.");
394 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[0], "/EM/CPU%d/R3/PrivInst/Mov CR0, X", "Number of mov CR0 write instructions.");
395 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[1], "/EM/CPU%d/R3/PrivInst/Mov CR1, X", "Number of mov CR1 write instructions.");
396 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[2], "/EM/CPU%d/R3/PrivInst/Mov CR2, X", "Number of mov CR2 write instructions.");
397 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[3], "/EM/CPU%d/R3/PrivInst/Mov CR3, X", "Number of mov CR3 write instructions.");
398 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[4], "/EM/CPU%d/R3/PrivInst/Mov CR4, X", "Number of mov CR4 write instructions.");
399 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[0], "/EM/CPU%d/R3/PrivInst/Mov X, CR0", "Number of mov CR0 read instructions.");
400 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[1], "/EM/CPU%d/R3/PrivInst/Mov X, CR1", "Number of mov CR1 read instructions.");
401 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[2], "/EM/CPU%d/R3/PrivInst/Mov X, CR2", "Number of mov CR2 read instructions.");
402 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[3], "/EM/CPU%d/R3/PrivInst/Mov X, CR3", "Number of mov CR3 read instructions.");
403 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[4], "/EM/CPU%d/R3/PrivInst/Mov X, CR4", "Number of mov CR4 read instructions.");
404 EM_REG_COUNTER_USED(&pStats->StatMovDRx, "/EM/CPU%d/R3/PrivInst/MovDRx", "Number of mov DRx instructions.");
405 EM_REG_COUNTER_USED(&pStats->StatIret, "/EM/CPU%d/R3/PrivInst/Iret", "Number of iret instructions.");
406 EM_REG_COUNTER_USED(&pStats->StatMovLgdt, "/EM/CPU%d/R3/PrivInst/Lgdt", "Number of lgdt instructions.");
407 EM_REG_COUNTER_USED(&pStats->StatMovLidt, "/EM/CPU%d/R3/PrivInst/Lidt", "Number of lidt instructions.");
408 EM_REG_COUNTER_USED(&pStats->StatMovLldt, "/EM/CPU%d/R3/PrivInst/Lldt", "Number of lldt instructions.");
409 EM_REG_COUNTER_USED(&pStats->StatSysEnter, "/EM/CPU%d/R3/PrivInst/Sysenter", "Number of sysenter instructions.");
410 EM_REG_COUNTER_USED(&pStats->StatSysExit, "/EM/CPU%d/R3/PrivInst/Sysexit", "Number of sysexit instructions.");
411 EM_REG_COUNTER_USED(&pStats->StatSysCall, "/EM/CPU%d/R3/PrivInst/Syscall", "Number of syscall instructions.");
412 EM_REG_COUNTER_USED(&pStats->StatSysRet, "/EM/CPU%d/R3/PrivInst/Sysret", "Number of sysret instructions.");
413
414 EM_REG_COUNTER(&pVCpu->em.s.StatTotalClis, "/EM/CPU%d/Cli/Total", "Total number of cli instructions executed.");
415 pVCpu->em.s.pCliStatTree = 0;
416
417 /* these should be considered for release statistics. */
418 EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%d/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction.");
419 EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%d/EM/Emulation/Priv", "Profiling of emR3RawPrivileged.");
420 EM_REG_PROFILE(&pVCpu->em.s.StatHmEntry, "/PROF/CPU%d/EM/HmEnter", "Profiling Hardware Accelerated Mode entry overhead.");
421 EM_REG_PROFILE(&pVCpu->em.s.StatHmExec, "/PROF/CPU%d/EM/HmExec", "Profiling Hardware Accelerated Mode execution.");
422 EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%d/EM/REMEmuSingle", "Profiling single instruction REM execution.");
423 EM_REG_PROFILE(&pVCpu->em.s.StatREMExec, "/PROF/CPU%d/EM/REMExec", "Profiling REM execution.");
424 EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%d/EM/REMSync", "Profiling REM context syncing.");
425 EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%d/EM/RAWEnter", "Profiling Raw Mode entry overhead.");
426 EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%d/EM/RAWExec", "Profiling Raw Mode execution.");
427 EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%d/EM/RAWTail", "Profiling Raw Mode tail overhead.");
428
429#endif /* VBOX_WITH_STATISTICS */
430
431 EM_REG_COUNTER(&pVCpu->em.s.StatForcedActions, "/PROF/CPU%d/EM/ForcedActions", "Profiling forced action execution.");
432 EM_REG_COUNTER(&pVCpu->em.s.StatHalted, "/PROF/CPU%d/EM/Halted", "Profiling halted state (VMR3WaitHalted).");
433 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatCapped, "/PROF/CPU%d/EM/Capped", "Profiling capped state (sleep).");
434 EM_REG_COUNTER(&pVCpu->em.s.StatREMTotal, "/PROF/CPU%d/EM/REMTotal", "Profiling emR3RemExecute (excluding FFs).");
435 EM_REG_COUNTER(&pVCpu->em.s.StatRAWTotal, "/PROF/CPU%d/EM/RAWTotal", "Profiling emR3RawExecute (excluding FFs).");
436
437 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatTotal, "/PROF/CPU%d/EM/Total", "Profiling EMR3ExecuteVM.");
438 }
439
440 emR3InitDbg(pVM);
441 return VINF_SUCCESS;
442}
443
444
445/**
446 * Applies relocations to data and code managed by this
447 * component. This function will be called at init and
448 * whenever the VMM need to relocate it self inside the GC.
449 *
450 * @param pVM Pointer to the VM.
451 */
452VMMR3_INT_DECL(void) EMR3Relocate(PVM pVM)
453{
454 LogFlow(("EMR3Relocate\n"));
455 for (VMCPUID i = 0; i < pVM->cCpus; i++)
456 {
457 PVMCPU pVCpu = &pVM->aCpus[i];
458 if (pVCpu->em.s.pStatsR3)
459 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVCpu->em.s.pStatsR3);
460 }
461}
462
463
464/**
465 * Reset the EM state for a CPU.
466 *
467 * Called by EMR3Reset and hot plugging.
468 *
469 * @param pVCpu Pointer to the VMCPU.
470 */
471VMMR3_INT_DECL(void) EMR3ResetCpu(PVMCPU pVCpu)
472{
473 pVCpu->em.s.fForceRAW = false;
474
475 /* VMR3Reset may return VINF_EM_RESET or VINF_EM_SUSPEND, so transition
476 out of the HALTED state here so that enmPrevState doesn't end up as
477 HALTED when EMR3Execute returns. */
478 if (pVCpu->em.s.enmState == EMSTATE_HALTED)
479 {
480 Log(("EMR3ResetCpu: Cpu#%u %s -> %s\n", pVCpu->idCpu, emR3GetStateName(pVCpu->em.s.enmState), pVCpu->idCpu == 0 ? "EMSTATE_NONE" : "EMSTATE_WAIT_SIPI"));
481 pVCpu->em.s.enmState = pVCpu->idCpu == 0 ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
482 }
483}
484
485
486/**
487 * Reset notification.
488 *
489 * @param pVM Pointer to the VM.
490 */
491VMMR3_INT_DECL(void) EMR3Reset(PVM pVM)
492{
493 Log(("EMR3Reset: \n"));
494 for (VMCPUID i = 0; i < pVM->cCpus; i++)
495 EMR3ResetCpu(&pVM->aCpus[i]);
496}
497
498
499/**
500 * Terminates the EM.
501 *
502 * Termination means cleaning up and freeing all resources,
503 * the VM it self is at this point powered off or suspended.
504 *
505 * @returns VBox status code.
506 * @param pVM Pointer to the VM.
507 */
508VMMR3_INT_DECL(int) EMR3Term(PVM pVM)
509{
510 AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
511
512#ifdef VBOX_WITH_REM
513 PDMR3CritSectDelete(&pVM->em.s.CritSectREM);
514#endif
515 return VINF_SUCCESS;
516}
517
518
519/**
520 * Execute state save operation.
521 *
522 * @returns VBox status code.
523 * @param pVM Pointer to the VM.
524 * @param pSSM SSM operation handle.
525 */
526static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
527{
528 for (VMCPUID i = 0; i < pVM->cCpus; i++)
529 {
530 PVMCPU pVCpu = &pVM->aCpus[i];
531
532 int rc = SSMR3PutBool(pSSM, pVCpu->em.s.fForceRAW);
533 AssertRCReturn(rc, rc);
534
535 Assert(pVCpu->em.s.enmState == EMSTATE_SUSPENDED);
536 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
537 rc = SSMR3PutU32(pSSM, pVCpu->em.s.enmPrevState);
538 AssertRCReturn(rc, rc);
539
540 /* Save mwait state. */
541 rc = SSMR3PutU32(pSSM, pVCpu->em.s.MWait.fWait);
542 AssertRCReturn(rc, rc);
543 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMWaitRAX);
544 AssertRCReturn(rc, rc);
545 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMWaitRCX);
546 AssertRCReturn(rc, rc);
547 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRAX);
548 AssertRCReturn(rc, rc);
549 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRCX);
550 AssertRCReturn(rc, rc);
551 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRDX);
552 AssertRCReturn(rc, rc);
553 }
554 return VINF_SUCCESS;
555}
556
557
558/**
559 * Execute state load operation.
560 *
561 * @returns VBox status code.
562 * @param pVM Pointer to the VM.
563 * @param pSSM SSM operation handle.
564 * @param uVersion Data layout version.
565 * @param uPass The data pass.
566 */
567static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
568{
569 /*
570 * Validate version.
571 */
572 if ( uVersion > EM_SAVED_STATE_VERSION
573 || uVersion < EM_SAVED_STATE_VERSION_PRE_SMP)
574 {
575 AssertMsgFailed(("emR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, EM_SAVED_STATE_VERSION));
576 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
577 }
578 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
579
580 /*
581 * Load the saved state.
582 */
583 for (VMCPUID i = 0; i < pVM->cCpus; i++)
584 {
585 PVMCPU pVCpu = &pVM->aCpus[i];
586
587 int rc = SSMR3GetBool(pSSM, &pVCpu->em.s.fForceRAW);
588 if (RT_FAILURE(rc))
589 pVCpu->em.s.fForceRAW = false;
590 AssertRCReturn(rc, rc);
591
592 if (uVersion > EM_SAVED_STATE_VERSION_PRE_SMP)
593 {
594 AssertCompile(sizeof(pVCpu->em.s.enmPrevState) == sizeof(uint32_t));
595 rc = SSMR3GetU32(pSSM, (uint32_t *)&pVCpu->em.s.enmPrevState);
596 AssertRCReturn(rc, rc);
597 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
598
599 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
600 }
601 if (uVersion > EM_SAVED_STATE_VERSION_PRE_MWAIT)
602 {
603 /* Load mwait state. */
604 rc = SSMR3GetU32(pSSM, &pVCpu->em.s.MWait.fWait);
605 AssertRCReturn(rc, rc);
606 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMWaitRAX);
607 AssertRCReturn(rc, rc);
608 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMWaitRCX);
609 AssertRCReturn(rc, rc);
610 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRAX);
611 AssertRCReturn(rc, rc);
612 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRCX);
613 AssertRCReturn(rc, rc);
614 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRDX);
615 AssertRCReturn(rc, rc);
616 }
617
618 Assert(!pVCpu->em.s.pCliStatTree);
619 }
620 return VINF_SUCCESS;
621}
622
623
624/**
625 * Argument packet for emR3SetExecutionPolicy.
626 */
627struct EMR3SETEXECPOLICYARGS
628{
629 EMEXECPOLICY enmPolicy;
630 bool fEnforce;
631};
632
633
634/**
635 * @callback_method_impl{FNVMMEMTRENDEZVOUS, Rendezvous callback for EMR3SetExecutionPolicy.}
636 */
637static DECLCALLBACK(VBOXSTRICTRC) emR3SetExecutionPolicy(PVM pVM, PVMCPU pVCpu, void *pvUser)
638{
639 /*
640 * Only the first CPU changes the variables.
641 */
642 if (pVCpu->idCpu == 0)
643 {
644 struct EMR3SETEXECPOLICYARGS *pArgs = (struct EMR3SETEXECPOLICYARGS *)pvUser;
645 switch (pArgs->enmPolicy)
646 {
647 case EMEXECPOLICY_RECOMPILE_RING0:
648 pVM->fRecompileSupervisor = pArgs->fEnforce;
649 break;
650 case EMEXECPOLICY_RECOMPILE_RING3:
651 pVM->fRecompileUser = pArgs->fEnforce;
652 break;
653 case EMEXECPOLICY_IEM_ALL:
654 pVM->em.s.fIemExecutesAll = pArgs->fEnforce;
655 break;
656 default:
657 AssertFailedReturn(VERR_INVALID_PARAMETER);
658 }
659 Log(("emR3SetExecutionPolicy: fRecompileUser=%RTbool fRecompileSupervisor=%RTbool fIemExecutesAll=%RTbool\n",
660 pVM->fRecompileUser, pVM->fRecompileSupervisor, pVM->em.s.fIemExecutesAll));
661 }
662
663 /*
664 * Force rescheduling if in RAW, HM, IEM, or REM.
665 */
666 return pVCpu->em.s.enmState == EMSTATE_RAW
667 || pVCpu->em.s.enmState == EMSTATE_HM
668 || pVCpu->em.s.enmState == EMSTATE_IEM
669 || pVCpu->em.s.enmState == EMSTATE_REM
670 ? VINF_EM_RESCHEDULE
671 : VINF_SUCCESS;
672}
673
674
675/**
676 * Changes an execution scheduling policy parameter.
677 *
678 * This is used to enable or disable raw-mode / hardware-virtualization
679 * execution of user and supervisor code.
680 *
681 * @returns VINF_SUCCESS on success.
682 * @returns VINF_RESCHEDULE if a rescheduling might be required.
683 * @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
684 *
685 * @param pUVM The user mode VM handle.
686 * @param enmPolicy The scheduling policy to change.
687 * @param fEnforce Whether to enforce the policy or not.
688 */
689VMMR3DECL(int) EMR3SetExecutionPolicy(PUVM pUVM, EMEXECPOLICY enmPolicy, bool fEnforce)
690{
691 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
692 VM_ASSERT_VALID_EXT_RETURN(pUVM->pVM, VERR_INVALID_VM_HANDLE);
693 AssertReturn(enmPolicy > EMEXECPOLICY_INVALID && enmPolicy < EMEXECPOLICY_END, VERR_INVALID_PARAMETER);
694
695 struct EMR3SETEXECPOLICYARGS Args = { enmPolicy, fEnforce };
696 return VMMR3EmtRendezvous(pUVM->pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_DESCENDING, emR3SetExecutionPolicy, &Args);
697}
698
699
700/**
701 * Queries an execution scheduling policy parameter.
702 *
703 * @returns VBox status code
704 * @param pUVM The user mode VM handle.
705 * @param enmPolicy The scheduling policy to query.
706 * @param pfEnforced Where to return the current value.
707 */
708VMMR3DECL(int) EMR3QueryExecutionPolicy(PUVM pUVM, EMEXECPOLICY enmPolicy, bool *pfEnforced)
709{
710 AssertReturn(enmPolicy > EMEXECPOLICY_INVALID && enmPolicy < EMEXECPOLICY_END, VERR_INVALID_PARAMETER);
711 AssertPtrReturn(pfEnforced, VERR_INVALID_POINTER);
712 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
713 PVM pVM = pUVM->pVM;
714 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
715
716 /* No need to bother EMTs with a query. */
717 switch (enmPolicy)
718 {
719 case EMEXECPOLICY_RECOMPILE_RING0:
720 *pfEnforced = pVM->fRecompileSupervisor;
721 break;
722 case EMEXECPOLICY_RECOMPILE_RING3:
723 *pfEnforced = pVM->fRecompileUser;
724 break;
725 case EMEXECPOLICY_IEM_ALL:
726 *pfEnforced = pVM->em.s.fIemExecutesAll;
727 break;
728 default:
729 AssertFailedReturn(VERR_INTERNAL_ERROR_2);
730 }
731
732 return VINF_SUCCESS;
733}
734
735
736/**
737 * Raise a fatal error.
738 *
739 * Safely terminate the VM with full state report and stuff. This function
740 * will naturally never return.
741 *
742 * @param pVCpu Pointer to the VMCPU.
743 * @param rc VBox status code.
744 */
745VMMR3DECL(void) EMR3FatalError(PVMCPU pVCpu, int rc)
746{
747 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
748 longjmp(pVCpu->em.s.u.FatalLongJump, rc);
749 AssertReleaseMsgFailed(("longjmp returned!\n"));
750}
751
752
753#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
754/**
755 * Gets the EM state name.
756 *
757 * @returns pointer to read only state name,
758 * @param enmState The state.
759 */
760static const char *emR3GetStateName(EMSTATE enmState)
761{
762 switch (enmState)
763 {
764 case EMSTATE_NONE: return "EMSTATE_NONE";
765 case EMSTATE_RAW: return "EMSTATE_RAW";
766 case EMSTATE_HM: return "EMSTATE_HM";
767 case EMSTATE_IEM: return "EMSTATE_IEM";
768 case EMSTATE_REM: return "EMSTATE_REM";
769 case EMSTATE_HALTED: return "EMSTATE_HALTED";
770 case EMSTATE_WAIT_SIPI: return "EMSTATE_WAIT_SIPI";
771 case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
772 case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
773 case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
774 case EMSTATE_DEBUG_GUEST_HM: return "EMSTATE_DEBUG_GUEST_HM";
775 case EMSTATE_DEBUG_GUEST_IEM: return "EMSTATE_DEBUG_GUEST_IEM";
776 case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
777 case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
778 case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
779 default: return "Unknown!";
780 }
781}
782#endif /* LOG_ENABLED || VBOX_STRICT */
783
784
785/**
786 * Debug loop.
787 *
788 * @returns VBox status code for EM.
789 * @param pVM Pointer to the VM.
790 * @param pVCpu Pointer to the VMCPU.
791 * @param rc Current EM VBox status code.
792 */
793static VBOXSTRICTRC emR3Debug(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc)
794{
795 for (;;)
796 {
797 Log(("emR3Debug: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
798 const VBOXSTRICTRC rcLast = rc;
799
800 /*
801 * Debug related RC.
802 */
803 switch (VBOXSTRICTRC_VAL(rc))
804 {
805 /*
806 * Single step an instruction.
807 */
808 case VINF_EM_DBG_STEP:
809 if ( pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
810 || pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
811 || pVCpu->em.s.fForceRAW /* paranoia */)
812#ifdef VBOX_WITH_RAW_MODE
813 rc = emR3RawStep(pVM, pVCpu);
814#else
815 AssertLogRelMsgFailedStmt(("Bad EM state."), VERR_EM_INTERNAL_ERROR);
816#endif
817 else if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HM)
818 rc = EMR3HmSingleInstruction(pVM, pVCpu, 0 /*fFlags*/);
819#ifdef VBOX_WITH_REM
820 else if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM)
821 rc = emR3RemStep(pVM, pVCpu);
822#endif
823 else
824 {
825 rc = IEMExecOne(pVCpu); /** @todo add dedicated interface... */
826 if (rc == VINF_SUCCESS || rc == VINF_EM_RESCHEDULE)
827 rc = VINF_EM_DBG_STEPPED;
828 }
829 break;
830
831 /*
832 * Simple events: stepped, breakpoint, stop/assertion.
833 */
834 case VINF_EM_DBG_STEPPED:
835 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
836 break;
837
838 case VINF_EM_DBG_BREAKPOINT:
839 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
840 break;
841
842 case VINF_EM_DBG_STOP:
843 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
844 break;
845
846 case VINF_EM_DBG_HYPER_STEPPED:
847 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
848 break;
849
850 case VINF_EM_DBG_HYPER_BREAKPOINT:
851 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
852 break;
853
854 case VINF_EM_DBG_HYPER_ASSERTION:
855 RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
856 RTLogFlush(NULL);
857 rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
858 break;
859
860 /*
861 * Guru meditation.
862 */
863 case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
864 rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
865 break;
866 case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
867 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
868 break;
869
870 default: /** @todo don't use default for guru, but make special errors code! */
871 {
872 LogRel(("emR3Debug: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
873 rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
874 break;
875 }
876 }
877
878 /*
879 * Process the result.
880 */
881 do
882 {
883 switch (VBOXSTRICTRC_VAL(rc))
884 {
885 /*
886 * Continue the debugging loop.
887 */
888 case VINF_EM_DBG_STEP:
889 case VINF_EM_DBG_STOP:
890 case VINF_EM_DBG_STEPPED:
891 case VINF_EM_DBG_BREAKPOINT:
892 case VINF_EM_DBG_HYPER_STEPPED:
893 case VINF_EM_DBG_HYPER_BREAKPOINT:
894 case VINF_EM_DBG_HYPER_ASSERTION:
895 break;
896
897 /*
898 * Resuming execution (in some form) has to be done here if we got
899 * a hypervisor debug event.
900 */
901 case VINF_SUCCESS:
902 case VINF_EM_RESUME:
903 case VINF_EM_SUSPEND:
904 case VINF_EM_RESCHEDULE:
905 case VINF_EM_RESCHEDULE_RAW:
906 case VINF_EM_RESCHEDULE_REM:
907 case VINF_EM_HALT:
908 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
909 {
910#ifdef VBOX_WITH_RAW_MODE
911 rc = emR3RawResumeHyper(pVM, pVCpu);
912 if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
913 continue;
914#else
915 AssertLogRelMsgFailedReturn(("Not implemented\n"), VERR_EM_INTERNAL_ERROR);
916#endif
917 }
918 if (rc == VINF_SUCCESS)
919 rc = VINF_EM_RESCHEDULE;
920 return rc;
921
922 /*
923 * The debugger isn't attached.
924 * We'll simply turn the thing off since that's the easiest thing to do.
925 */
926 case VERR_DBGF_NOT_ATTACHED:
927 switch (VBOXSTRICTRC_VAL(rcLast))
928 {
929 case VINF_EM_DBG_HYPER_STEPPED:
930 case VINF_EM_DBG_HYPER_BREAKPOINT:
931 case VINF_EM_DBG_HYPER_ASSERTION:
932 case VERR_TRPM_PANIC:
933 case VERR_TRPM_DONT_PANIC:
934 case VERR_VMM_RING0_ASSERTION:
935 case VERR_VMM_HYPER_CR3_MISMATCH:
936 case VERR_VMM_RING3_CALL_DISABLED:
937 return rcLast;
938 }
939 return VINF_EM_OFF;
940
941 /*
942 * Status codes terminating the VM in one or another sense.
943 */
944 case VINF_EM_TERMINATE:
945 case VINF_EM_OFF:
946 case VINF_EM_RESET:
947 case VINF_EM_NO_MEMORY:
948 case VINF_EM_RAW_STALE_SELECTOR:
949 case VINF_EM_RAW_IRET_TRAP:
950 case VERR_TRPM_PANIC:
951 case VERR_TRPM_DONT_PANIC:
952 case VERR_IEM_INSTR_NOT_IMPLEMENTED:
953 case VERR_IEM_ASPECT_NOT_IMPLEMENTED:
954 case VERR_VMM_RING0_ASSERTION:
955 case VERR_VMM_HYPER_CR3_MISMATCH:
956 case VERR_VMM_RING3_CALL_DISABLED:
957 case VERR_INTERNAL_ERROR:
958 case VERR_INTERNAL_ERROR_2:
959 case VERR_INTERNAL_ERROR_3:
960 case VERR_INTERNAL_ERROR_4:
961 case VERR_INTERNAL_ERROR_5:
962 case VERR_IPE_UNEXPECTED_STATUS:
963 case VERR_IPE_UNEXPECTED_INFO_STATUS:
964 case VERR_IPE_UNEXPECTED_ERROR_STATUS:
965 return rc;
966
967 /*
968 * The rest is unexpected, and will keep us here.
969 */
970 default:
971 AssertMsgFailed(("Unexpected rc %Rrc!\n", VBOXSTRICTRC_VAL(rc)));
972 break;
973 }
974 } while (false);
975 } /* debug for ever */
976}
977
978
979/**
980 * Steps recompiled code.
981 *
982 * @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
983 * VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
984 *
985 * @param pVM Pointer to the VM.
986 * @param pVCpu Pointer to the VMCPU.
987 */
988static int emR3RemStep(PVM pVM, PVMCPU pVCpu)
989{
990 Log3(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
991
992#ifdef VBOX_WITH_REM
993 EMRemLock(pVM);
994
995 /*
996 * Switch to REM, step instruction, switch back.
997 */
998 int rc = REMR3State(pVM, pVCpu);
999 if (RT_SUCCESS(rc))
1000 {
1001 rc = REMR3Step(pVM, pVCpu);
1002 REMR3StateBack(pVM, pVCpu);
1003 }
1004 EMRemUnlock(pVM);
1005
1006#else
1007 int rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu)); NOREF(pVM);
1008#endif
1009
1010 Log3(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
1011 return rc;
1012}
1013
1014
1015/**
1016 * emR3RemExecute helper that syncs the state back from REM and leave the REM
1017 * critical section.
1018 *
1019 * @returns false - new fInREMState value.
1020 * @param pVM Pointer to the VM.
1021 * @param pVCpu Pointer to the VMCPU.
1022 */
1023DECLINLINE(bool) emR3RemExecuteSyncBack(PVM pVM, PVMCPU pVCpu)
1024{
1025#ifdef VBOX_WITH_REM
1026 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, a);
1027 REMR3StateBack(pVM, pVCpu);
1028 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, a);
1029
1030 EMRemUnlock(pVM);
1031#endif
1032 return false;
1033}
1034
1035
1036/**
1037 * Executes recompiled code.
1038 *
1039 * This function contains the recompiler version of the inner
1040 * execution loop (the outer loop being in EMR3ExecuteVM()).
1041 *
1042 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1043 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1044 *
1045 * @param pVM Pointer to the VM.
1046 * @param pVCpu Pointer to the VMCPU.
1047 * @param pfFFDone Where to store an indicator telling whether or not
1048 * FFs were done before returning.
1049 *
1050 */
1051static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1052{
1053#ifdef LOG_ENABLED
1054 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1055 uint32_t cpl = CPUMGetGuestCPL(pVCpu);
1056
1057 if (pCtx->eflags.Bits.u1VM)
1058 Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags.Bits.u1IF));
1059 else
1060 Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x eflags=%x\n", cpl, pCtx->cs.Sel, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, pCtx->eflags.u));
1061#endif
1062 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatREMTotal, a);
1063
1064#if defined(VBOX_STRICT) && defined(DEBUG_bird)
1065 AssertMsg( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1066 || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVCpu)), /** @todo @bugref{1419} - get flat address. */
1067 ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
1068#endif
1069
1070 /*
1071 * Spin till we get a forced action which returns anything but VINF_SUCCESS
1072 * or the REM suggests raw-mode execution.
1073 */
1074 *pfFFDone = false;
1075#ifdef VBOX_WITH_REM
1076 bool fInREMState = false;
1077#endif
1078 int rc = VINF_SUCCESS;
1079 for (;;)
1080 {
1081#ifdef VBOX_WITH_REM
1082 /*
1083 * Lock REM and update the state if not already in sync.
1084 *
1085 * Note! Big lock, but you are not supposed to own any lock when
1086 * coming in here.
1087 */
1088 if (!fInREMState)
1089 {
1090 EMRemLock(pVM);
1091 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, b);
1092
1093 /* Flush the recompiler translation blocks if the VCPU has changed,
1094 also force a full CPU state resync. */
1095 if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
1096 {
1097 REMFlushTBs(pVM);
1098 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1099 }
1100 pVM->em.s.idLastRemCpu = pVCpu->idCpu;
1101
1102 rc = REMR3State(pVM, pVCpu);
1103
1104 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, b);
1105 if (RT_FAILURE(rc))
1106 break;
1107 fInREMState = true;
1108
1109 /*
1110 * We might have missed the raising of VMREQ, TIMER and some other
1111 * important FFs while we were busy switching the state. So, check again.
1112 */
1113 if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_CHECK_VM_STATE | VM_FF_RESET)
1114 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TIMER | VMCPU_FF_REQUEST))
1115 {
1116 LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fGlobalForcedActions));
1117 goto l_REMDoForcedActions;
1118 }
1119 }
1120#endif
1121
1122 /*
1123 * Execute REM.
1124 */
1125 if (RT_LIKELY(emR3IsExecutionAllowed(pVM, pVCpu)))
1126 {
1127 STAM_PROFILE_START(&pVCpu->em.s.StatREMExec, c);
1128#ifdef VBOX_WITH_REM
1129 rc = REMR3Run(pVM, pVCpu);
1130#else
1131 rc = VBOXSTRICTRC_TODO(IEMExecLots(pVCpu));
1132#endif
1133 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMExec, c);
1134 }
1135 else
1136 {
1137 /* Give up this time slice; virtual time continues */
1138 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1139 RTThreadSleep(5);
1140 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1141 rc = VINF_SUCCESS;
1142 }
1143
1144 /*
1145 * Deal with high priority post execution FFs before doing anything
1146 * else. Sync back the state and leave the lock to be on the safe side.
1147 */
1148 if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1149 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1150 {
1151#ifdef VBOX_WITH_REM
1152 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1153#endif
1154 rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1155 }
1156
1157 /*
1158 * Process the returned status code.
1159 */
1160 if (rc != VINF_SUCCESS)
1161 {
1162 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1163 break;
1164 if (rc != VINF_REM_INTERRUPED_FF)
1165 {
1166 /*
1167 * Anything which is not known to us means an internal error
1168 * and the termination of the VM!
1169 */
1170 AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
1171 break;
1172 }
1173 }
1174
1175
1176 /*
1177 * Check and execute forced actions.
1178 *
1179 * Sync back the VM state and leave the lock before calling any of
1180 * these, you never know what's going to happen here.
1181 */
1182#ifdef VBOX_HIGH_RES_TIMERS_HACK
1183 TMTimerPollVoid(pVM, pVCpu);
1184#endif
1185 AssertCompile(VMCPU_FF_ALL_REM_MASK & VMCPU_FF_TIMER);
1186 if ( VM_FF_IS_PENDING(pVM, VM_FF_ALL_REM_MASK)
1187 || VMCPU_FF_IS_PENDING(pVCpu,
1188 VMCPU_FF_ALL_REM_MASK
1189 & VM_WHEN_RAW_MODE(~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE), UINT32_MAX)) )
1190 {
1191l_REMDoForcedActions:
1192#ifdef VBOX_WITH_REM
1193 if (fInREMState)
1194 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1195#endif
1196 STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatREMTotal, a);
1197 rc = emR3ForcedActions(pVM, pVCpu, rc);
1198 VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
1199 STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatREMTotal, a);
1200 if ( rc != VINF_SUCCESS
1201 && rc != VINF_EM_RESCHEDULE_REM)
1202 {
1203 *pfFFDone = true;
1204 break;
1205 }
1206 }
1207
1208 } /* The Inner Loop, recompiled execution mode version. */
1209
1210
1211#ifdef VBOX_WITH_REM
1212 /*
1213 * Returning. Sync back the VM state if required.
1214 */
1215 if (fInREMState)
1216 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1217#endif
1218
1219 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatREMTotal, a);
1220 return rc;
1221}
1222
1223
1224#ifdef DEBUG
1225
1226int emR3SingleStepExecRem(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1227{
1228 EMSTATE enmOldState = pVCpu->em.s.enmState;
1229
1230 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1231
1232 Log(("Single step BEGIN:\n"));
1233 for (uint32_t i = 0; i < cIterations; i++)
1234 {
1235 DBGFR3PrgStep(pVCpu);
1236 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "RSS");
1237 emR3RemStep(pVM, pVCpu);
1238 if (emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx) != EMSTATE_REM)
1239 break;
1240 }
1241 Log(("Single step END:\n"));
1242 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1243 pVCpu->em.s.enmState = enmOldState;
1244 return VINF_EM_RESCHEDULE;
1245}
1246
1247#endif /* DEBUG */
1248
1249
1250/**
1251 * Decides whether to execute RAW, HWACC or REM.
1252 *
1253 * @returns new EM state
1254 * @param pVM Pointer to the VM.
1255 * @param pVCpu Pointer to the VMCPU.
1256 * @param pCtx Pointer to the guest CPU context.
1257 */
1258EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1259{
1260 /*
1261 * When forcing raw-mode execution, things are simple.
1262 */
1263 if (pVCpu->em.s.fForceRAW)
1264 return EMSTATE_RAW;
1265
1266 /*
1267 * We stay in the wait for SIPI state unless explicitly told otherwise.
1268 */
1269 if (pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI)
1270 return EMSTATE_WAIT_SIPI;
1271
1272 /*
1273 * Execute everything in IEM?
1274 */
1275 if (pVM->em.s.fIemExecutesAll)
1276 return EMSTATE_IEM;
1277
1278 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1279 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1280 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1281
1282 X86EFLAGS EFlags = pCtx->eflags;
1283 if (HMIsEnabled(pVM))
1284 {
1285 /*
1286 * Hardware accelerated raw-mode:
1287 */
1288 if ( EMIsHwVirtExecutionEnabled(pVM)
1289 && HMR3CanExecuteGuest(pVM, pCtx))
1290 return EMSTATE_HM;
1291
1292 /*
1293 * Note! Raw mode and hw accelerated mode are incompatible. The latter
1294 * turns off monitoring features essential for raw mode!
1295 */
1296 return EMSTATE_REM;
1297 }
1298
1299 /*
1300 * Standard raw-mode:
1301 *
1302 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1303 * or 32 bits protected mode ring 0 code
1304 *
1305 * The tests are ordered by the likelihood of being true during normal execution.
1306 */
1307 if (EFlags.u32 & (X86_EFL_TF /* | HF_INHIBIT_IRQ_MASK*/))
1308 {
1309 Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
1310 return EMSTATE_REM;
1311 }
1312
1313# ifndef VBOX_RAW_V86
1314 if (EFlags.u32 & X86_EFL_VM) {
1315 Log2(("raw mode refused: VM_MASK\n"));
1316 return EMSTATE_REM;
1317 }
1318# endif
1319
1320 /** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
1321 uint32_t u32CR0 = pCtx->cr0;
1322 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
1323 {
1324 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1325 return EMSTATE_REM;
1326 }
1327
1328 if (pCtx->cr4 & X86_CR4_PAE)
1329 {
1330 uint32_t u32Dummy, u32Features;
1331
1332 CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1333 if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
1334 return EMSTATE_REM;
1335 }
1336
1337 unsigned uSS = pCtx->ss.Sel;
1338 if ( pCtx->eflags.Bits.u1VM
1339 || (uSS & X86_SEL_RPL) == 3)
1340 {
1341 if (!EMIsRawRing3Enabled(pVM))
1342 return EMSTATE_REM;
1343
1344 if (!(EFlags.u32 & X86_EFL_IF))
1345 {
1346 Log2(("raw mode refused: IF (RawR3)\n"));
1347 return EMSTATE_REM;
1348 }
1349
1350 if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
1351 {
1352 Log2(("raw mode refused: CR0.WP + RawR0\n"));
1353 return EMSTATE_REM;
1354 }
1355 }
1356 else
1357 {
1358 if (!EMIsRawRing0Enabled(pVM))
1359 return EMSTATE_REM;
1360
1361 if (EMIsRawRing1Enabled(pVM))
1362 {
1363 /* Only ring 0 and 1 supervisor code. */
1364 if ((uSS & X86_SEL_RPL) == 2) /* ring 1 code is moved into ring 2, so we can't support ring-2 in that case. */
1365 {
1366 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
1367 return EMSTATE_REM;
1368 }
1369 }
1370 /* Only ring 0 supervisor code. */
1371 else if ((uSS & X86_SEL_RPL) != 0)
1372 {
1373 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
1374 return EMSTATE_REM;
1375 }
1376
1377 // Let's start with pure 32 bits ring 0 code first
1378 /** @todo What's pure 32-bit mode? flat? */
1379 if ( !(pCtx->ss.Attr.n.u1DefBig)
1380 || !(pCtx->cs.Attr.n.u1DefBig))
1381 {
1382 Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
1383 return EMSTATE_REM;
1384 }
1385
1386 /* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
1387 if (!(u32CR0 & X86_CR0_WP))
1388 {
1389 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1390 return EMSTATE_REM;
1391 }
1392
1393# ifdef VBOX_WITH_RAW_MODE
1394 if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
1395 {
1396 Log2(("raw r0 mode forced: patch code\n"));
1397# ifdef VBOX_WITH_SAFE_STR
1398 Assert(pCtx->tr.Sel);
1399# endif
1400 return EMSTATE_RAW;
1401 }
1402# endif /* VBOX_WITH_RAW_MODE */
1403
1404# if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1405 if (!(EFlags.u32 & X86_EFL_IF))
1406 {
1407 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
1408 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1409 return EMSTATE_REM;
1410 }
1411# endif
1412
1413# ifndef VBOX_WITH_RAW_RING1
1414 /** @todo still necessary??? */
1415 if (EFlags.Bits.u2IOPL != 0)
1416 {
1417 Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
1418 return EMSTATE_REM;
1419 }
1420# endif
1421 }
1422
1423 /*
1424 * Stale hidden selectors means raw-mode is unsafe (being very careful).
1425 */
1426 if (pCtx->cs.fFlags & CPUMSELREG_FLAGS_STALE)
1427 {
1428 Log2(("raw mode refused: stale CS\n"));
1429 return EMSTATE_REM;
1430 }
1431 if (pCtx->ss.fFlags & CPUMSELREG_FLAGS_STALE)
1432 {
1433 Log2(("raw mode refused: stale SS\n"));
1434 return EMSTATE_REM;
1435 }
1436 if (pCtx->ds.fFlags & CPUMSELREG_FLAGS_STALE)
1437 {
1438 Log2(("raw mode refused: stale DS\n"));
1439 return EMSTATE_REM;
1440 }
1441 if (pCtx->es.fFlags & CPUMSELREG_FLAGS_STALE)
1442 {
1443 Log2(("raw mode refused: stale ES\n"));
1444 return EMSTATE_REM;
1445 }
1446 if (pCtx->fs.fFlags & CPUMSELREG_FLAGS_STALE)
1447 {
1448 Log2(("raw mode refused: stale FS\n"));
1449 return EMSTATE_REM;
1450 }
1451 if (pCtx->gs.fFlags & CPUMSELREG_FLAGS_STALE)
1452 {
1453 Log2(("raw mode refused: stale GS\n"));
1454 return EMSTATE_REM;
1455 }
1456
1457# ifdef VBOX_WITH_SAFE_STR
1458 if (pCtx->tr.Sel == 0)
1459 {
1460 Log(("Raw mode refused -> TR=0\n"));
1461 return EMSTATE_REM;
1462 }
1463# endif
1464
1465 /*Assert(PGMPhysIsA20Enabled(pVCpu));*/
1466 return EMSTATE_RAW;
1467}
1468
1469
1470/**
1471 * Executes all high priority post execution force actions.
1472 *
1473 * @returns rc or a fatal status code.
1474 *
1475 * @param pVM Pointer to the VM.
1476 * @param pVCpu Pointer to the VMCPU.
1477 * @param rc The current rc.
1478 */
1479int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1480{
1481 VBOXVMM_EM_FF_HIGH(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions, rc);
1482
1483 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PDM_CRITSECT))
1484 PDMCritSectBothFF(pVCpu);
1485
1486 /* Update CR3 (Nested Paging case for HM). */
1487 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
1488 {
1489 int rc2 = PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
1490 if (RT_FAILURE(rc2))
1491 return rc2;
1492 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
1493 }
1494
1495 /* Update PAE PDPEs. This must be done *after* PGMUpdateCR3() and used only by the Nested Paging case for HM. */
1496 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
1497 {
1498 if (CPUMIsGuestInPAEMode(pVCpu))
1499 {
1500 PX86PDPE pPdpes = HMGetPaePdpes(pVCpu);
1501 AssertPtr(pPdpes);
1502
1503 PGMGstUpdatePaePdpes(pVCpu, pPdpes);
1504 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
1505 }
1506 else
1507 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
1508 }
1509
1510#ifdef VBOX_WITH_RAW_MODE
1511 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION))
1512 CSAMR3DoPendingAction(pVM, pVCpu);
1513#endif
1514
1515 if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
1516 {
1517 if ( rc > VINF_EM_NO_MEMORY
1518 && rc <= VINF_EM_LAST)
1519 rc = VINF_EM_NO_MEMORY;
1520 }
1521
1522 return rc;
1523}
1524
1525
1526/**
1527 * Executes all pending forced actions.
1528 *
1529 * Forced actions can cause execution delays and execution
1530 * rescheduling. The first we deal with using action priority, so
1531 * that for instance pending timers aren't scheduled and ran until
1532 * right before execution. The rescheduling we deal with using
1533 * return codes. The same goes for VM termination, only in that case
1534 * we exit everything.
1535 *
1536 * @returns VBox status code of equal or greater importance/severity than rc.
1537 * The most important ones are: VINF_EM_RESCHEDULE,
1538 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1539 *
1540 * @param pVM Pointer to the VM.
1541 * @param pVCpu Pointer to the VMCPU.
1542 * @param rc The current rc.
1543 *
1544 */
1545int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1546{
1547 STAM_REL_PROFILE_START(&pVCpu->em.s.StatForcedActions, a);
1548#ifdef VBOX_STRICT
1549 int rcIrq = VINF_SUCCESS;
1550#endif
1551 int rc2;
1552#define UPDATE_RC() \
1553 do { \
1554 AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
1555 if (rc2 == VINF_SUCCESS || rc < VINF_SUCCESS) \
1556 break; \
1557 if (!rc || rc2 < rc) \
1558 rc = rc2; \
1559 } while (0)
1560 VBOXVMM_EM_FF_ALL(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions, rc);
1561
1562 /*
1563 * Post execution chunk first.
1564 */
1565 if ( VM_FF_IS_PENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK)
1566 || (VMCPU_FF_NORMAL_PRIORITY_POST_MASK && VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_POST_MASK)) )
1567 {
1568 /*
1569 * EMT Rendezvous (must be serviced before termination).
1570 */
1571 if (VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1572 {
1573 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1574 UPDATE_RC();
1575 /** @todo HACK ALERT! The following test is to make sure EM+TM
1576 * thinks the VM is stopped/reset before the next VM state change
1577 * is made. We need a better solution for this, or at least make it
1578 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1579 * VINF_EM_SUSPEND). */
1580 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1581 {
1582 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1583 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1584 return rc;
1585 }
1586 }
1587
1588 /*
1589 * State change request (cleared by vmR3SetStateLocked).
1590 */
1591 if (VM_FF_IS_PENDING(pVM, VM_FF_CHECK_VM_STATE))
1592 {
1593 VMSTATE enmState = VMR3GetState(pVM);
1594 switch (enmState)
1595 {
1596 case VMSTATE_FATAL_ERROR:
1597 case VMSTATE_FATAL_ERROR_LS:
1598 Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
1599 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1600 return VINF_EM_SUSPEND;
1601
1602 case VMSTATE_DESTROYING:
1603 Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
1604 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1605 return VINF_EM_TERMINATE;
1606
1607 default:
1608 AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
1609 }
1610 }
1611
1612 /*
1613 * Debugger Facility polling.
1614 */
1615 if (VM_FF_IS_PENDING(pVM, VM_FF_DBGF))
1616 {
1617 rc2 = DBGFR3VMMForcedAction(pVM);
1618 UPDATE_RC();
1619 }
1620
1621 /*
1622 * Postponed reset request.
1623 */
1624 if (VM_FF_TEST_AND_CLEAR(pVM, VM_FF_RESET))
1625 {
1626 rc2 = VMR3Reset(pVM->pUVM);
1627 UPDATE_RC();
1628 }
1629
1630#ifdef VBOX_WITH_RAW_MODE
1631 /*
1632 * CSAM page scanning.
1633 */
1634 if ( !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)
1635 && VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE))
1636 {
1637 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1638
1639 /** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
1640 Log(("Forced action VMCPU_FF_CSAM_SCAN_PAGE\n"));
1641
1642 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1643 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE);
1644 }
1645#endif
1646
1647 /*
1648 * Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
1649 */
1650 if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
1651 {
1652 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1653 UPDATE_RC();
1654 if (rc == VINF_EM_NO_MEMORY)
1655 return rc;
1656 }
1657
1658 /* check that we got them all */
1659 AssertCompile(VM_FF_NORMAL_PRIORITY_POST_MASK == (VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1660 AssertCompile(VMCPU_FF_NORMAL_PRIORITY_POST_MASK == VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0));
1661 }
1662
1663 /*
1664 * Normal priority then.
1665 * (Executed in no particular order.)
1666 */
1667 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_NORMAL_PRIORITY_MASK, VM_FF_PGM_NO_MEMORY))
1668 {
1669 /*
1670 * PDM Queues are pending.
1671 */
1672 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_QUEUES, VM_FF_PGM_NO_MEMORY))
1673 PDMR3QueueFlushAll(pVM);
1674
1675 /*
1676 * PDM DMA transfers are pending.
1677 */
1678 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_DMA, VM_FF_PGM_NO_MEMORY))
1679 PDMR3DmaRun(pVM);
1680
1681 /*
1682 * EMT Rendezvous (make sure they are handled before the requests).
1683 */
1684 if (VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1685 {
1686 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1687 UPDATE_RC();
1688 /** @todo HACK ALERT! The following test is to make sure EM+TM
1689 * thinks the VM is stopped/reset before the next VM state change
1690 * is made. We need a better solution for this, or at least make it
1691 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1692 * VINF_EM_SUSPEND). */
1693 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1694 {
1695 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1696 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1697 return rc;
1698 }
1699 }
1700
1701 /*
1702 * Requests from other threads.
1703 */
1704 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
1705 {
1706 rc2 = VMR3ReqProcessU(pVM->pUVM, VMCPUID_ANY, false /*fPriorityOnly*/);
1707 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE) /** @todo this shouldn't be necessary */
1708 {
1709 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1710 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1711 return rc2;
1712 }
1713 UPDATE_RC();
1714 /** @todo HACK ALERT! The following test is to make sure EM+TM
1715 * thinks the VM is stopped/reset before the next VM state change
1716 * is made. We need a better solution for this, or at least make it
1717 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1718 * VINF_EM_SUSPEND). */
1719 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1720 {
1721 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1722 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1723 return rc;
1724 }
1725 }
1726
1727#ifdef VBOX_WITH_REM
1728 /* Replay the handler notification changes. */
1729 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REM_HANDLER_NOTIFY, VM_FF_PGM_NO_MEMORY))
1730 {
1731 /* Try not to cause deadlocks. */
1732 if ( pVM->cCpus == 1
1733 || ( !PGMIsLockOwner(pVM)
1734 && !IOMIsLockWriteOwner(pVM))
1735 )
1736 {
1737 EMRemLock(pVM);
1738 REMR3ReplayHandlerNotifications(pVM);
1739 EMRemUnlock(pVM);
1740 }
1741 }
1742#endif
1743
1744 /* check that we got them all */
1745 AssertCompile(VM_FF_NORMAL_PRIORITY_MASK == (VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_REM_HANDLER_NOTIFY | VM_FF_EMT_RENDEZVOUS));
1746 }
1747
1748 /*
1749 * Normal priority then. (per-VCPU)
1750 * (Executed in no particular order.)
1751 */
1752 if ( !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)
1753 && VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_MASK))
1754 {
1755 /*
1756 * Requests from other threads.
1757 */
1758 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
1759 {
1760 rc2 = VMR3ReqProcessU(pVM->pUVM, pVCpu->idCpu, false /*fPriorityOnly*/);
1761 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE || rc2 == VINF_EM_RESET)
1762 {
1763 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1764 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1765 return rc2;
1766 }
1767 UPDATE_RC();
1768 /** @todo HACK ALERT! The following test is to make sure EM+TM
1769 * thinks the VM is stopped/reset before the next VM state change
1770 * is made. We need a better solution for this, or at least make it
1771 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1772 * VINF_EM_SUSPEND). */
1773 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1774 {
1775 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1776 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1777 return rc;
1778 }
1779 }
1780
1781 /* check that we got them all */
1782 Assert(!(VMCPU_FF_NORMAL_PRIORITY_MASK & ~(VMCPU_FF_REQUEST)));
1783 }
1784
1785 /*
1786 * High priority pre execution chunk last.
1787 * (Executed in ascending priority order.)
1788 */
1789 if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK)
1790 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_MASK))
1791 {
1792 /*
1793 * Timers before interrupts.
1794 */
1795 if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TIMER)
1796 && !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
1797 TMR3TimerQueuesDo(pVM);
1798
1799 /*
1800 * The instruction following an emulated STI should *always* be executed!
1801 *
1802 * Note! We intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if
1803 * the eip is the same as the inhibited instr address. Before we
1804 * are able to execute this instruction in raw mode (iret to
1805 * guest code) an external interrupt might force a world switch
1806 * again. Possibly allowing a guest interrupt to be dispatched
1807 * in the process. This could break the guest. Sounds very
1808 * unlikely, but such timing sensitive problem are not as rare as
1809 * you might think.
1810 */
1811 if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1812 && !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
1813 {
1814 if (CPUMGetGuestRIP(pVCpu) != EMGetInhibitInterruptsPC(pVCpu))
1815 {
1816 Log(("Clearing VMCPU_FF_INHIBIT_INTERRUPTS at %RGv - successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu), EMGetInhibitInterruptsPC(pVCpu)));
1817 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1818 }
1819 else
1820 Log(("Leaving VMCPU_FF_INHIBIT_INTERRUPTS set at %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu)));
1821 }
1822
1823 /*
1824 * Interrupts.
1825 */
1826 bool fWakeupPending = false;
1827 if ( !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)
1828 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1829 && (!rc || rc >= VINF_EM_RESCHEDULE_HM)
1830 && !TRPMHasTrap(pVCpu) /* an interrupt could already be scheduled for dispatching in the recompiler. */
1831#ifdef VBOX_WITH_RAW_MODE
1832 && PATMAreInterruptsEnabled(pVM)
1833#else
1834 && (pVCpu->em.s.pCtx->eflags.u32 & X86_EFL_IF)
1835#endif
1836 && !HMR3IsEventPending(pVCpu))
1837 {
1838 Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1839 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
1840 {
1841 /* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
1842 /** @todo this really isn't nice, should properly handle this */
1843 rc2 = TRPMR3InjectEvent(pVM, pVCpu, TRPM_HARDWARE_INT);
1844 if (pVM->em.s.fIemExecutesAll && (rc2 == VINF_EM_RESCHEDULE_REM || rc2 == VINF_EM_RESCHEDULE_HM || rc2 == VINF_EM_RESCHEDULE_RAW))
1845 rc2 = VINF_EM_RESCHEDULE;
1846#ifdef VBOX_STRICT
1847 rcIrq = rc2;
1848#endif
1849 UPDATE_RC();
1850 /* Reschedule required: We must not miss the wakeup below! */
1851 fWakeupPending = true;
1852 }
1853#ifdef VBOX_WITH_REM
1854 /** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
1855 else if (REMR3QueryPendingInterrupt(pVM, pVCpu) != REM_NO_PENDING_IRQ)
1856 {
1857 Log2(("REMR3QueryPendingInterrupt -> %#x\n", REMR3QueryPendingInterrupt(pVM, pVCpu)));
1858 rc2 = VINF_EM_RESCHEDULE_REM;
1859 UPDATE_RC();
1860 }
1861#endif
1862 }
1863
1864 /*
1865 * Allocate handy pages.
1866 */
1867 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1868 {
1869 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1870 UPDATE_RC();
1871 }
1872
1873 /*
1874 * Debugger Facility request.
1875 */
1876 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_DBGF, VM_FF_PGM_NO_MEMORY))
1877 {
1878 rc2 = DBGFR3VMMForcedAction(pVM);
1879 UPDATE_RC();
1880 }
1881
1882 /*
1883 * EMT Rendezvous (must be serviced before termination).
1884 */
1885 if ( !fWakeupPending /* don't miss the wakeup from EMSTATE_HALTED! */
1886 && VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1887 {
1888 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1889 UPDATE_RC();
1890 /** @todo HACK ALERT! The following test is to make sure EM+TM thinks the VM is
1891 * stopped/reset before the next VM state change is made. We need a better
1892 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1893 * && rc >= VINF_EM_SUSPEND). */
1894 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1895 {
1896 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1897 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1898 return rc;
1899 }
1900 }
1901
1902 /*
1903 * State change request (cleared by vmR3SetStateLocked).
1904 */
1905 if ( !fWakeupPending /* don't miss the wakeup from EMSTATE_HALTED! */
1906 && VM_FF_IS_PENDING(pVM, VM_FF_CHECK_VM_STATE))
1907 {
1908 VMSTATE enmState = VMR3GetState(pVM);
1909 switch (enmState)
1910 {
1911 case VMSTATE_FATAL_ERROR:
1912 case VMSTATE_FATAL_ERROR_LS:
1913 Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
1914 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1915 return VINF_EM_SUSPEND;
1916
1917 case VMSTATE_DESTROYING:
1918 Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
1919 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1920 return VINF_EM_TERMINATE;
1921
1922 default:
1923 AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
1924 }
1925 }
1926
1927 /*
1928 * Out of memory? Since most of our fellow high priority actions may cause us
1929 * to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
1930 * at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
1931 * than us since we can terminate without allocating more memory.
1932 */
1933 if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
1934 {
1935 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1936 UPDATE_RC();
1937 if (rc == VINF_EM_NO_MEMORY)
1938 return rc;
1939 }
1940
1941 /*
1942 * If the virtual sync clock is still stopped, make TM restart it.
1943 */
1944 if (VM_FF_IS_PENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
1945 TMR3VirtualSyncFF(pVM, pVCpu);
1946
1947#ifdef DEBUG
1948 /*
1949 * Debug, pause the VM.
1950 */
1951 if (VM_FF_IS_PENDING(pVM, VM_FF_DEBUG_SUSPEND))
1952 {
1953 VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
1954 Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
1955 return VINF_EM_SUSPEND;
1956 }
1957#endif
1958
1959 /* check that we got them all */
1960 AssertCompile(VM_FF_HIGH_PRIORITY_PRE_MASK == (VM_FF_TM_VIRTUAL_SYNC | VM_FF_DBGF | VM_FF_CHECK_VM_STATE | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1961 AssertCompile(VMCPU_FF_HIGH_PRIORITY_PRE_MASK == (VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_INHIBIT_INTERRUPTS | VM_WHEN_RAW_MODE(VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT, 0)));
1962 }
1963
1964#undef UPDATE_RC
1965 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1966 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1967 Assert(rcIrq == VINF_SUCCESS || rcIrq == rc);
1968 return rc;
1969}
1970
1971
1972/**
1973 * Check if the preset execution time cap restricts guest execution scheduling.
1974 *
1975 * @returns true if allowed, false otherwise
1976 * @param pVM Pointer to the VM.
1977 * @param pVCpu Pointer to the VMCPU.
1978 */
1979bool emR3IsExecutionAllowed(PVM pVM, PVMCPU pVCpu)
1980{
1981 uint64_t u64UserTime, u64KernelTime;
1982
1983 if ( pVM->uCpuExecutionCap != 100
1984 && RT_SUCCESS(RTThreadGetExecutionTimeMilli(&u64KernelTime, &u64UserTime)))
1985 {
1986 uint64_t u64TimeNow = RTTimeMilliTS();
1987 if (pVCpu->em.s.u64TimeSliceStart + EM_TIME_SLICE < u64TimeNow)
1988 {
1989 /* New time slice. */
1990 pVCpu->em.s.u64TimeSliceStart = u64TimeNow;
1991 pVCpu->em.s.u64TimeSliceStartExec = u64KernelTime + u64UserTime;
1992 pVCpu->em.s.u64TimeSliceExec = 0;
1993 }
1994 pVCpu->em.s.u64TimeSliceExec = u64KernelTime + u64UserTime - pVCpu->em.s.u64TimeSliceStartExec;
1995
1996 Log2(("emR3IsExecutionAllowed: start=%RX64 startexec=%RX64 exec=%RX64 (cap=%x)\n", pVCpu->em.s.u64TimeSliceStart, pVCpu->em.s.u64TimeSliceStartExec, pVCpu->em.s.u64TimeSliceExec, (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100));
1997 if (pVCpu->em.s.u64TimeSliceExec >= (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100)
1998 return false;
1999 }
2000 return true;
2001}
2002
2003
2004/**
2005 * Execute VM.
2006 *
2007 * This function is the main loop of the VM. The emulation thread
2008 * calls this function when the VM has been successfully constructed
2009 * and we're ready for executing the VM.
2010 *
2011 * Returning from this function means that the VM is turned off or
2012 * suspended (state already saved) and deconstruction is next in line.
2013 *
2014 * All interaction from other thread are done using forced actions
2015 * and signaling of the wait object.
2016 *
2017 * @returns VBox status code, informational status codes may indicate failure.
2018 * @param pVM Pointer to the VM.
2019 * @param pVCpu Pointer to the VMCPU.
2020 */
2021VMMR3_INT_DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu)
2022{
2023 Log(("EMR3ExecuteVM: pVM=%p enmVMState=%d (%s) enmState=%d (%s) enmPrevState=%d (%s) fForceRAW=%RTbool\n",
2024 pVM,
2025 pVM->enmVMState, VMR3GetStateName(pVM->enmVMState),
2026 pVCpu->em.s.enmState, emR3GetStateName(pVCpu->em.s.enmState),
2027 pVCpu->em.s.enmPrevState, emR3GetStateName(pVCpu->em.s.enmPrevState),
2028 pVCpu->em.s.fForceRAW));
2029 VM_ASSERT_EMT(pVM);
2030 AssertMsg( pVCpu->em.s.enmState == EMSTATE_NONE
2031 || pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI
2032 || pVCpu->em.s.enmState == EMSTATE_SUSPENDED,
2033 ("%s\n", emR3GetStateName(pVCpu->em.s.enmState)));
2034
2035 int rc = setjmp(pVCpu->em.s.u.FatalLongJump);
2036 if (rc == 0)
2037 {
2038 /*
2039 * Start the virtual time.
2040 */
2041 TMR3NotifyResume(pVM, pVCpu);
2042
2043 /*
2044 * The Outer Main Loop.
2045 */
2046 bool fFFDone = false;
2047
2048 /* Reschedule right away to start in the right state. */
2049 rc = VINF_SUCCESS;
2050
2051 /* If resuming after a pause or a state load, restore the previous
2052 state or else we'll start executing code. Else, just reschedule. */
2053 if ( pVCpu->em.s.enmState == EMSTATE_SUSPENDED
2054 && ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
2055 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED))
2056 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2057 else
2058 pVCpu->em.s.enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
2059 Log(("EMR3ExecuteVM: enmState=%s\n", emR3GetStateName(pVCpu->em.s.enmState)));
2060
2061 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2062 for (;;)
2063 {
2064 /*
2065 * Before we can schedule anything (we're here because
2066 * scheduling is required) we must service any pending
2067 * forced actions to avoid any pending action causing
2068 * immediate rescheduling upon entering an inner loop
2069 *
2070 * Do forced actions.
2071 */
2072 if ( !fFFDone
2073 && RT_SUCCESS(rc)
2074 && rc != VINF_EM_TERMINATE
2075 && rc != VINF_EM_OFF
2076 && ( VM_FF_IS_PENDING(pVM, VM_FF_ALL_REM_MASK)
2077 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_ALL_REM_MASK)))
2078 {
2079 rc = emR3ForcedActions(pVM, pVCpu, rc);
2080 VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
2081 if ( ( rc == VINF_EM_RESCHEDULE_REM
2082 || rc == VINF_EM_RESCHEDULE_HM)
2083 && pVCpu->em.s.fForceRAW)
2084 rc = VINF_EM_RESCHEDULE_RAW;
2085 }
2086 else if (fFFDone)
2087 fFFDone = false;
2088
2089 /*
2090 * Now what to do?
2091 */
2092 Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
2093 EMSTATE const enmOldState = pVCpu->em.s.enmState;
2094 switch (rc)
2095 {
2096 /*
2097 * Keep doing what we're currently doing.
2098 */
2099 case VINF_SUCCESS:
2100 break;
2101
2102 /*
2103 * Reschedule - to raw-mode execution.
2104 */
2105 case VINF_EM_RESCHEDULE_RAW:
2106 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", enmOldState, EMSTATE_RAW));
2107 Assert(!pVM->em.s.fIemExecutesAll || pVCpu->em.s.enmState != EMSTATE_IEM);
2108 pVCpu->em.s.enmState = EMSTATE_RAW;
2109 break;
2110
2111 /*
2112 * Reschedule - to hardware accelerated raw-mode execution.
2113 */
2114 case VINF_EM_RESCHEDULE_HM:
2115 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HM: %d -> %d (EMSTATE_HM)\n", enmOldState, EMSTATE_HM));
2116 Assert(!pVM->em.s.fIemExecutesAll || pVCpu->em.s.enmState != EMSTATE_IEM);
2117 Assert(!pVCpu->em.s.fForceRAW);
2118 pVCpu->em.s.enmState = EMSTATE_HM;
2119 break;
2120
2121 /*
2122 * Reschedule - to recompiled execution.
2123 */
2124 case VINF_EM_RESCHEDULE_REM:
2125 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", enmOldState, EMSTATE_REM));
2126 Assert(!pVM->em.s.fIemExecutesAll || pVCpu->em.s.enmState != EMSTATE_IEM);
2127 pVCpu->em.s.enmState = EMSTATE_REM;
2128 break;
2129
2130 /*
2131 * Resume.
2132 */
2133 case VINF_EM_RESUME:
2134 Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", enmOldState));
2135 /* Don't reschedule in the halted or wait for SIPI case. */
2136 if ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
2137 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED)
2138 {
2139 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2140 break;
2141 }
2142 /* fall through and get scheduled. */
2143
2144 /*
2145 * Reschedule.
2146 */
2147 case VINF_EM_RESCHEDULE:
2148 {
2149 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
2150 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", enmOldState, enmState, emR3GetStateName(enmState)));
2151 pVCpu->em.s.enmState = enmState;
2152 break;
2153 }
2154
2155 /*
2156 * Halted.
2157 */
2158 case VINF_EM_HALT:
2159 Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", enmOldState, EMSTATE_HALTED));
2160 pVCpu->em.s.enmState = EMSTATE_HALTED;
2161 break;
2162
2163 /*
2164 * Switch to the wait for SIPI state (application processor only)
2165 */
2166 case VINF_EM_WAIT_SIPI:
2167 Assert(pVCpu->idCpu != 0);
2168 Log2(("EMR3ExecuteVM: VINF_EM_WAIT_SIPI: %d -> %d\n", enmOldState, EMSTATE_WAIT_SIPI));
2169 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
2170 break;
2171
2172
2173 /*
2174 * Suspend.
2175 */
2176 case VINF_EM_SUSPEND:
2177 Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", enmOldState, EMSTATE_SUSPENDED));
2178 Assert(enmOldState != EMSTATE_SUSPENDED);
2179 pVCpu->em.s.enmPrevState = enmOldState;
2180 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2181 break;
2182
2183 /*
2184 * Reset.
2185 * We might end up doing a double reset for now, we'll have to clean up the mess later.
2186 */
2187 case VINF_EM_RESET:
2188 {
2189 if (pVCpu->idCpu == 0)
2190 {
2191 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
2192 Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", enmOldState, enmState, emR3GetStateName(enmState)));
2193 pVCpu->em.s.enmState = enmState;
2194 }
2195 else
2196 {
2197 /* All other VCPUs go into the wait for SIPI state. */
2198 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
2199 }
2200 break;
2201 }
2202
2203 /*
2204 * Power Off.
2205 */
2206 case VINF_EM_OFF:
2207 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
2208 Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", enmOldState, EMSTATE_TERMINATING));
2209 TMR3NotifySuspend(pVM, pVCpu);
2210 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2211 return rc;
2212
2213 /*
2214 * Terminate the VM.
2215 */
2216 case VINF_EM_TERMINATE:
2217 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
2218 Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", enmOldState, EMSTATE_TERMINATING));
2219 if (pVM->enmVMState < VMSTATE_DESTROYING) /* ugly */
2220 TMR3NotifySuspend(pVM, pVCpu);
2221 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2222 return rc;
2223
2224
2225 /*
2226 * Out of memory, suspend the VM and stuff.
2227 */
2228 case VINF_EM_NO_MEMORY:
2229 Log2(("EMR3ExecuteVM: VINF_EM_NO_MEMORY: %d -> %d\n", enmOldState, EMSTATE_SUSPENDED));
2230 Assert(enmOldState != EMSTATE_SUSPENDED);
2231 pVCpu->em.s.enmPrevState = enmOldState;
2232 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2233 TMR3NotifySuspend(pVM, pVCpu);
2234 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2235
2236 rc = VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_SUSPEND, "HostMemoryLow",
2237 N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
2238 if (rc != VINF_EM_SUSPEND)
2239 {
2240 if (RT_SUCCESS_NP(rc))
2241 {
2242 AssertLogRelMsgFailed(("%Rrc\n", rc));
2243 rc = VERR_EM_INTERNAL_ERROR;
2244 }
2245 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2246 }
2247 return rc;
2248
2249 /*
2250 * Guest debug events.
2251 */
2252 case VINF_EM_DBG_STEPPED:
2253 case VINF_EM_DBG_STOP:
2254 case VINF_EM_DBG_BREAKPOINT:
2255 case VINF_EM_DBG_STEP:
2256 if (enmOldState == EMSTATE_RAW)
2257 {
2258 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_RAW));
2259 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
2260 }
2261 else if (enmOldState == EMSTATE_HM)
2262 {
2263 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_HM));
2264 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_HM;
2265 }
2266 else if (enmOldState == EMSTATE_REM)
2267 {
2268 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_REM));
2269 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
2270 }
2271 else
2272 {
2273 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_IEM));
2274 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_IEM;
2275 }
2276 break;
2277
2278 /*
2279 * Hypervisor debug events.
2280 */
2281 case VINF_EM_DBG_HYPER_STEPPED:
2282 case VINF_EM_DBG_HYPER_BREAKPOINT:
2283 case VINF_EM_DBG_HYPER_ASSERTION:
2284 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_HYPER));
2285 pVCpu->em.s.enmState = EMSTATE_DEBUG_HYPER;
2286 break;
2287
2288 /*
2289 * Guru mediations.
2290 */
2291 case VERR_VMM_RING0_ASSERTION:
2292 case VINF_EM_TRIPLE_FAULT:
2293 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, enmOldState, EMSTATE_GURU_MEDITATION));
2294 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2295 break;
2296
2297 /*
2298 * Any error code showing up here other than the ones we
2299 * know and process above are considered to be FATAL.
2300 *
2301 * Unknown warnings and informational status codes are also
2302 * included in this.
2303 */
2304 default:
2305 if (RT_SUCCESS_NP(rc))
2306 {
2307 AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
2308 rc = VERR_EM_INTERNAL_ERROR;
2309 }
2310 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, enmOldState, EMSTATE_GURU_MEDITATION));
2311 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2312 break;
2313 }
2314
2315 /*
2316 * Act on state transition.
2317 */
2318 EMSTATE const enmNewState = pVCpu->em.s.enmState;
2319 if (enmOldState != enmNewState)
2320 {
2321 VBOXVMM_EM_STATE_CHANGED(pVCpu, enmOldState, enmNewState, rc);
2322
2323 /* Clear MWait flags. */
2324 if ( enmOldState == EMSTATE_HALTED
2325 && (pVCpu->em.s.MWait.fWait & EMMWAIT_FLAG_ACTIVE)
2326 && ( enmNewState == EMSTATE_RAW
2327 || enmNewState == EMSTATE_HM
2328 || enmNewState == EMSTATE_REM
2329 || enmNewState == EMSTATE_DEBUG_GUEST_RAW
2330 || enmNewState == EMSTATE_DEBUG_GUEST_HM
2331 || enmNewState == EMSTATE_DEBUG_GUEST_IEM
2332 || enmNewState == EMSTATE_DEBUG_GUEST_REM) )
2333 {
2334 LogFlow(("EMR3ExecuteVM: Clearing MWAIT\n"));
2335 pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0);
2336 }
2337 }
2338 else
2339 VBOXVMM_EM_STATE_UNCHANGED(pVCpu, enmNewState, rc);
2340
2341 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x); /* (skip this in release) */
2342 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2343
2344 /*
2345 * Act on the new state.
2346 */
2347 switch (enmNewState)
2348 {
2349 /*
2350 * Execute raw.
2351 */
2352 case EMSTATE_RAW:
2353#ifdef VBOX_WITH_RAW_MODE
2354 rc = emR3RawExecute(pVM, pVCpu, &fFFDone);
2355#else
2356 AssertLogRelMsgFailed(("%Rrc\n", rc));
2357 rc = VERR_EM_INTERNAL_ERROR;
2358#endif
2359 break;
2360
2361 /*
2362 * Execute hardware accelerated raw.
2363 */
2364 case EMSTATE_HM:
2365 rc = emR3HmExecute(pVM, pVCpu, &fFFDone);
2366 break;
2367
2368 /*
2369 * Execute recompiled.
2370 */
2371 case EMSTATE_REM:
2372 rc = emR3RemExecute(pVM, pVCpu, &fFFDone);
2373 Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
2374 break;
2375
2376 /*
2377 * Execute in the interpreter.
2378 */
2379 case EMSTATE_IEM:
2380#if 0 /* For testing purposes. */
2381 rc = VBOXSTRICTRC_TODO(EMR3HmSingleInstruction(pVM, pVCpu, EM_ONE_INS_FLAGS_RIP_CHANGE));
2382 if (rc == VINF_EM_DBG_STEPPED || rc == VINF_EM_RESCHEDULE_HM || rc == VINF_EM_RESCHEDULE_REM || rc == VINF_EM_RESCHEDULE_RAW)
2383 rc = VINF_SUCCESS;
2384 else if (rc == VERR_EM_CANNOT_EXEC_GUEST)
2385#endif
2386 rc = VBOXSTRICTRC_TODO(IEMExecLots(pVCpu));
2387 if (pVM->em.s.fIemExecutesAll)
2388 {
2389 Assert(rc != VINF_EM_RESCHEDULE_REM);
2390 Assert(rc != VINF_EM_RESCHEDULE_RAW);
2391 Assert(rc != VINF_EM_RESCHEDULE_HM);
2392 }
2393 fFFDone = false;
2394 break;
2395
2396 /*
2397 * Application processor execution halted until SIPI.
2398 */
2399 case EMSTATE_WAIT_SIPI:
2400 /* no break */
2401 /*
2402 * hlt - execution halted until interrupt.
2403 */
2404 case EMSTATE_HALTED:
2405 {
2406 STAM_REL_PROFILE_START(&pVCpu->em.s.StatHalted, y);
2407 /* MWAIT has a special extension where it's woken up when
2408 an interrupt is pending even when IF=0. */
2409 if ( (pVCpu->em.s.MWait.fWait & (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0))
2410 == (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0))
2411 {
2412 rc = VMR3WaitHalted(pVM, pVCpu, false /*fIgnoreInterrupts*/);
2413 if ( rc == VINF_SUCCESS
2414 && VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
2415 {
2416 Log(("EMR3ExecuteVM: Triggering reschedule on pending IRQ after MWAIT\n"));
2417 rc = VINF_EM_RESCHEDULE;
2418 }
2419 }
2420 else
2421 rc = VMR3WaitHalted(pVM, pVCpu, !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
2422
2423 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHalted, y);
2424 break;
2425 }
2426
2427 /*
2428 * Suspended - return to VM.cpp.
2429 */
2430 case EMSTATE_SUSPENDED:
2431 TMR3NotifySuspend(pVM, pVCpu);
2432 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2433 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2434 return VINF_EM_SUSPEND;
2435
2436 /*
2437 * Debugging in the guest.
2438 */
2439 case EMSTATE_DEBUG_GUEST_RAW:
2440 case EMSTATE_DEBUG_GUEST_HM:
2441 case EMSTATE_DEBUG_GUEST_IEM:
2442 case EMSTATE_DEBUG_GUEST_REM:
2443 TMR3NotifySuspend(pVM, pVCpu);
2444 rc = VBOXSTRICTRC_TODO(emR3Debug(pVM, pVCpu, rc));
2445 TMR3NotifyResume(pVM, pVCpu);
2446 Log2(("EMR3ExecuteVM: emR3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2447 break;
2448
2449 /*
2450 * Debugging in the hypervisor.
2451 */
2452 case EMSTATE_DEBUG_HYPER:
2453 {
2454 TMR3NotifySuspend(pVM, pVCpu);
2455 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2456
2457 rc = VBOXSTRICTRC_TODO(emR3Debug(pVM, pVCpu, rc));
2458 Log2(("EMR3ExecuteVM: emR3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2459 if (rc != VINF_SUCCESS)
2460 {
2461 if (rc == VINF_EM_OFF || rc == VINF_EM_TERMINATE)
2462 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
2463 else
2464 {
2465 /* switch to guru meditation mode */
2466 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2467 VMMR3FatalDump(pVM, pVCpu, rc);
2468 }
2469 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2470 return rc;
2471 }
2472
2473 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2474 TMR3NotifyResume(pVM, pVCpu);
2475 break;
2476 }
2477
2478 /*
2479 * Guru meditation takes place in the debugger.
2480 */
2481 case EMSTATE_GURU_MEDITATION:
2482 {
2483 TMR3NotifySuspend(pVM, pVCpu);
2484 VMMR3FatalDump(pVM, pVCpu, rc);
2485 emR3Debug(pVM, pVCpu, rc);
2486 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2487 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2488 return rc;
2489 }
2490
2491 /*
2492 * The states we don't expect here.
2493 */
2494 case EMSTATE_NONE:
2495 case EMSTATE_TERMINATING:
2496 default:
2497 AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVCpu->em.s.enmState));
2498 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2499 TMR3NotifySuspend(pVM, pVCpu);
2500 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2501 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2502 return VERR_EM_INTERNAL_ERROR;
2503 }
2504 } /* The Outer Main Loop */
2505 }
2506 else
2507 {
2508 /*
2509 * Fatal error.
2510 */
2511 Log(("EMR3ExecuteVM: returns %Rrc because of longjmp / fatal error; (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2512 TMR3NotifySuspend(pVM, pVCpu);
2513 VMMR3FatalDump(pVM, pVCpu, rc);
2514 emR3Debug(pVM, pVCpu, rc);
2515 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2516 /** @todo change the VM state! */
2517 return rc;
2518 }
2519
2520 /* (won't ever get here). */
2521 AssertFailed();
2522}
2523
2524/**
2525 * Notify EM of a state change (used by FTM)
2526 *
2527 * @param pVM Pointer to the VM.
2528 */
2529VMMR3_INT_DECL(int) EMR3NotifySuspend(PVM pVM)
2530{
2531 PVMCPU pVCpu = VMMGetCpu(pVM);
2532
2533 TMR3NotifySuspend(pVM, pVCpu); /* Stop the virtual time. */
2534 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
2535 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2536 return VINF_SUCCESS;
2537}
2538
2539/**
2540 * Notify EM of a state change (used by FTM)
2541 *
2542 * @param pVM Pointer to the VM.
2543 */
2544VMMR3_INT_DECL(int) EMR3NotifyResume(PVM pVM)
2545{
2546 PVMCPU pVCpu = VMMGetCpu(pVM);
2547 EMSTATE enmCurState = pVCpu->em.s.enmState;
2548
2549 TMR3NotifyResume(pVM, pVCpu); /* Resume the virtual time. */
2550 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2551 pVCpu->em.s.enmPrevState = enmCurState;
2552 return VINF_SUCCESS;
2553}
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