VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/EM.cpp@ 39895

Last change on this file since 39895 was 39070, checked in by vboxsync, 13 years ago

VMM,IPRT: -Wunused-function.
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1/* $Id: EM.cpp 39070 2011-10-21 09:41:18Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2011 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_em EM - The Execution Monitor / Manager
19 *
20 * The Execution Monitor/Manager is responsible for running the VM, scheduling
21 * the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
22 * Interpreted), and keeping the CPU states in sync. The function
23 * EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
24 * modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
25 * emR3RemExecute).
26 *
27 * The interpreted execution is only used to avoid switching between
28 * raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
29 * The interpretation is thus implemented as part of EM.
30 *
31 * @see grp_em
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_EM
38#include <VBox/vmm/em.h>
39#include <VBox/vmm/vmm.h>
40#include <VBox/vmm/patm.h>
41#include <VBox/vmm/csam.h>
42#include <VBox/vmm/selm.h>
43#include <VBox/vmm/trpm.h>
44#include <VBox/vmm/iom.h>
45#include <VBox/vmm/dbgf.h>
46#include <VBox/vmm/pgm.h>
47#include <VBox/vmm/rem.h>
48#include <VBox/vmm/tm.h>
49#include <VBox/vmm/mm.h>
50#include <VBox/vmm/ssm.h>
51#include <VBox/vmm/pdmapi.h>
52#include <VBox/vmm/pdmcritsect.h>
53#include <VBox/vmm/pdmqueue.h>
54#include <VBox/vmm/hwaccm.h>
55#include <VBox/vmm/patm.h>
56#ifdef IEM_VERIFICATION_MODE
57# include <VBox/vmm/iem.h>
58#endif
59#include "EMInternal.h"
60#include "internal/em.h"
61#include <VBox/vmm/vm.h>
62#include <VBox/vmm/cpumdis.h>
63#include <VBox/dis.h>
64#include <VBox/disopcode.h>
65#include <VBox/vmm/dbgf.h>
66
67#include <iprt/asm.h>
68#include <iprt/string.h>
69#include <iprt/stream.h>
70#include <iprt/thread.h>
71
72
73/*******************************************************************************
74* Defined Constants And Macros *
75*******************************************************************************/
76#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
77#define EM_NOTIFY_HWACCM
78#endif
79
80
81/*******************************************************************************
82* Internal Functions *
83*******************************************************************************/
84static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
85static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
86#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
87static const char *emR3GetStateName(EMSTATE enmState);
88#endif
89static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc);
90static int emR3RemStep(PVM pVM, PVMCPU pVCpu);
91static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
92int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
93
94
95/**
96 * Initializes the EM.
97 *
98 * @returns VBox status code.
99 * @param pVM The VM to operate on.
100 */
101VMMR3DECL(int) EMR3Init(PVM pVM)
102{
103 LogFlow(("EMR3Init\n"));
104 /*
105 * Assert alignment and sizes.
106 */
107 AssertCompileMemberAlignment(VM, em.s, 32);
108 AssertCompile(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
109 AssertCompile(sizeof(pVM->aCpus[0].em.s.u.FatalLongJump) <= sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump));
110 AssertCompileMemberAlignment(EM, CritSectREM, sizeof(uintptr_t));
111
112 /*
113 * Init the structure.
114 */
115 pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
116 bool fEnabled;
117 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &fEnabled);
118 pVM->fRecompileUser = RT_SUCCESS(rc) ? !fEnabled : false;
119 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &fEnabled);
120 pVM->fRecompileSupervisor = RT_SUCCESS(rc) ? !fEnabled : false;
121 Log(("EMR3Init: fRecompileUser=%RTbool fRecompileSupervisor=%RTbool\n", pVM->fRecompileUser, pVM->fRecompileSupervisor));
122
123 /*
124 * Initialize the REM critical section.
125 */
126 rc = PDMR3CritSectInit(pVM, &pVM->em.s.CritSectREM, RT_SRC_POS, "EM-REM");
127 AssertRCReturn(rc, rc);
128
129 /*
130 * Saved state.
131 */
132 rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
133 NULL, NULL, NULL,
134 NULL, emR3Save, NULL,
135 NULL, emR3Load, NULL);
136 if (RT_FAILURE(rc))
137 return rc;
138
139 for (VMCPUID i = 0; i < pVM->cCpus; i++)
140 {
141 PVMCPU pVCpu = &pVM->aCpus[i];
142
143 pVCpu->em.s.offVMCPU = RT_OFFSETOF(VMCPU, em.s);
144
145 pVCpu->em.s.enmState = (i == 0) ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
146 pVCpu->em.s.enmPrevState = EMSTATE_NONE;
147 pVCpu->em.s.fForceRAW = false;
148
149 pVCpu->em.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
150 pVCpu->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
151 AssertMsg(pVCpu->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
152
153 /* Force reset of the time slice. */
154 pVCpu->em.s.u64TimeSliceStart = 0;
155
156# define EM_REG_COUNTER(a, b, c) \
157 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
158 AssertRC(rc);
159
160# define EM_REG_COUNTER_USED(a, b, c) \
161 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, c, b, i); \
162 AssertRC(rc);
163
164# define EM_REG_PROFILE(a, b, c) \
165 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
166 AssertRC(rc);
167
168# define EM_REG_PROFILE_ADV(a, b, c) \
169 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
170 AssertRC(rc);
171
172 /*
173 * Statistics.
174 */
175#ifdef VBOX_WITH_STATISTICS
176 PEMSTATS pStats;
177 rc = MMHyperAlloc(pVM, sizeof(*pStats), 0, MM_TAG_EM, (void **)&pStats);
178 if (RT_FAILURE(rc))
179 return rc;
180
181 pVCpu->em.s.pStatsR3 = pStats;
182 pVCpu->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
183 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
184
185 EM_REG_PROFILE(&pStats->StatRZEmulate, "/EM/CPU%d/RZ/Interpret", "Profiling of EMInterpretInstruction.");
186 EM_REG_PROFILE(&pStats->StatR3Emulate, "/EM/CPU%d/R3/Interpret", "Profiling of EMInterpretInstruction.");
187
188 EM_REG_PROFILE(&pStats->StatRZInterpretSucceeded, "/EM/CPU%d/RZ/Interpret/Success", "The number of times an instruction was successfully interpreted.");
189 EM_REG_PROFILE(&pStats->StatR3InterpretSucceeded, "/EM/CPU%d/R3/Interpret/Success", "The number of times an instruction was successfully interpreted.");
190
191 EM_REG_COUNTER_USED(&pStats->StatRZAnd, "/EM/CPU%d/RZ/Interpret/Success/And", "The number of times AND was successfully interpreted.");
192 EM_REG_COUNTER_USED(&pStats->StatR3And, "/EM/CPU%d/R3/Interpret/Success/And", "The number of times AND was successfully interpreted.");
193 EM_REG_COUNTER_USED(&pStats->StatRZAdd, "/EM/CPU%d/RZ/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
194 EM_REG_COUNTER_USED(&pStats->StatR3Add, "/EM/CPU%d/R3/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
195 EM_REG_COUNTER_USED(&pStats->StatRZAdc, "/EM/CPU%d/RZ/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
196 EM_REG_COUNTER_USED(&pStats->StatR3Adc, "/EM/CPU%d/R3/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
197 EM_REG_COUNTER_USED(&pStats->StatRZSub, "/EM/CPU%d/RZ/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
198 EM_REG_COUNTER_USED(&pStats->StatR3Sub, "/EM/CPU%d/R3/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
199 EM_REG_COUNTER_USED(&pStats->StatRZCpuId, "/EM/CPU%d/RZ/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
200 EM_REG_COUNTER_USED(&pStats->StatR3CpuId, "/EM/CPU%d/R3/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
201 EM_REG_COUNTER_USED(&pStats->StatRZDec, "/EM/CPU%d/RZ/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
202 EM_REG_COUNTER_USED(&pStats->StatR3Dec, "/EM/CPU%d/R3/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
203 EM_REG_COUNTER_USED(&pStats->StatRZHlt, "/EM/CPU%d/RZ/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
204 EM_REG_COUNTER_USED(&pStats->StatR3Hlt, "/EM/CPU%d/R3/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
205 EM_REG_COUNTER_USED(&pStats->StatRZInc, "/EM/CPU%d/RZ/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
206 EM_REG_COUNTER_USED(&pStats->StatR3Inc, "/EM/CPU%d/R3/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
207 EM_REG_COUNTER_USED(&pStats->StatRZInvlPg, "/EM/CPU%d/RZ/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
208 EM_REG_COUNTER_USED(&pStats->StatR3InvlPg, "/EM/CPU%d/R3/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
209 EM_REG_COUNTER_USED(&pStats->StatRZIret, "/EM/CPU%d/RZ/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
210 EM_REG_COUNTER_USED(&pStats->StatR3Iret, "/EM/CPU%d/R3/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
211 EM_REG_COUNTER_USED(&pStats->StatRZLLdt, "/EM/CPU%d/RZ/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
212 EM_REG_COUNTER_USED(&pStats->StatR3LLdt, "/EM/CPU%d/R3/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
213 EM_REG_COUNTER_USED(&pStats->StatRZLIdt, "/EM/CPU%d/RZ/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
214 EM_REG_COUNTER_USED(&pStats->StatR3LIdt, "/EM/CPU%d/R3/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
215 EM_REG_COUNTER_USED(&pStats->StatRZLGdt, "/EM/CPU%d/RZ/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
216 EM_REG_COUNTER_USED(&pStats->StatR3LGdt, "/EM/CPU%d/R3/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
217 EM_REG_COUNTER_USED(&pStats->StatRZMov, "/EM/CPU%d/RZ/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
218 EM_REG_COUNTER_USED(&pStats->StatR3Mov, "/EM/CPU%d/R3/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
219 EM_REG_COUNTER_USED(&pStats->StatRZMovCRx, "/EM/CPU%d/RZ/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
220 EM_REG_COUNTER_USED(&pStats->StatR3MovCRx, "/EM/CPU%d/R3/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
221 EM_REG_COUNTER_USED(&pStats->StatRZMovDRx, "/EM/CPU%d/RZ/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
222 EM_REG_COUNTER_USED(&pStats->StatR3MovDRx, "/EM/CPU%d/R3/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
223 EM_REG_COUNTER_USED(&pStats->StatRZOr, "/EM/CPU%d/RZ/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
224 EM_REG_COUNTER_USED(&pStats->StatR3Or, "/EM/CPU%d/R3/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
225 EM_REG_COUNTER_USED(&pStats->StatRZPop, "/EM/CPU%d/RZ/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
226 EM_REG_COUNTER_USED(&pStats->StatR3Pop, "/EM/CPU%d/R3/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
227 EM_REG_COUNTER_USED(&pStats->StatRZRdtsc, "/EM/CPU%d/RZ/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
228 EM_REG_COUNTER_USED(&pStats->StatR3Rdtsc, "/EM/CPU%d/R3/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
229 EM_REG_COUNTER_USED(&pStats->StatRZRdpmc, "/EM/CPU%d/RZ/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
230 EM_REG_COUNTER_USED(&pStats->StatR3Rdpmc, "/EM/CPU%d/R3/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
231 EM_REG_COUNTER_USED(&pStats->StatRZSti, "/EM/CPU%d/RZ/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
232 EM_REG_COUNTER_USED(&pStats->StatR3Sti, "/EM/CPU%d/R3/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
233 EM_REG_COUNTER_USED(&pStats->StatRZXchg, "/EM/CPU%d/RZ/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
234 EM_REG_COUNTER_USED(&pStats->StatR3Xchg, "/EM/CPU%d/R3/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
235 EM_REG_COUNTER_USED(&pStats->StatRZXor, "/EM/CPU%d/RZ/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
236 EM_REG_COUNTER_USED(&pStats->StatR3Xor, "/EM/CPU%d/R3/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
237 EM_REG_COUNTER_USED(&pStats->StatRZMonitor, "/EM/CPU%d/RZ/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
238 EM_REG_COUNTER_USED(&pStats->StatR3Monitor, "/EM/CPU%d/R3/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
239 EM_REG_COUNTER_USED(&pStats->StatRZMWait, "/EM/CPU%d/RZ/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
240 EM_REG_COUNTER_USED(&pStats->StatR3MWait, "/EM/CPU%d/R3/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
241 EM_REG_COUNTER_USED(&pStats->StatRZBtr, "/EM/CPU%d/RZ/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
242 EM_REG_COUNTER_USED(&pStats->StatR3Btr, "/EM/CPU%d/R3/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
243 EM_REG_COUNTER_USED(&pStats->StatRZBts, "/EM/CPU%d/RZ/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
244 EM_REG_COUNTER_USED(&pStats->StatR3Bts, "/EM/CPU%d/R3/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
245 EM_REG_COUNTER_USED(&pStats->StatRZBtc, "/EM/CPU%d/RZ/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
246 EM_REG_COUNTER_USED(&pStats->StatR3Btc, "/EM/CPU%d/R3/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
247 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
248 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg, "/EM/CPU%d/R3/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
249 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
250 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg8b, "/EM/CPU%d/R3/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
251 EM_REG_COUNTER_USED(&pStats->StatRZXAdd, "/EM/CPU%d/RZ/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
252 EM_REG_COUNTER_USED(&pStats->StatR3XAdd, "/EM/CPU%d/R3/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
253 EM_REG_COUNTER_USED(&pStats->StatR3Rdmsr, "/EM/CPU%d/R3/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
254 EM_REG_COUNTER_USED(&pStats->StatRZRdmsr, "/EM/CPU%d/RZ/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
255 EM_REG_COUNTER_USED(&pStats->StatR3Wrmsr, "/EM/CPU%d/R3/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
256 EM_REG_COUNTER_USED(&pStats->StatRZWrmsr, "/EM/CPU%d/RZ/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
257 EM_REG_COUNTER_USED(&pStats->StatR3StosWD, "/EM/CPU%d/R3/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
258 EM_REG_COUNTER_USED(&pStats->StatRZStosWD, "/EM/CPU%d/RZ/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
259 EM_REG_COUNTER_USED(&pStats->StatRZWbInvd, "/EM/CPU%d/RZ/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
260 EM_REG_COUNTER_USED(&pStats->StatR3WbInvd, "/EM/CPU%d/R3/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
261 EM_REG_COUNTER_USED(&pStats->StatRZLmsw, "/EM/CPU%d/RZ/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
262 EM_REG_COUNTER_USED(&pStats->StatR3Lmsw, "/EM/CPU%d/R3/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
263
264 EM_REG_COUNTER(&pStats->StatRZInterpretFailed, "/EM/CPU%d/RZ/Interpret/Failed", "The number of times an instruction was not interpreted.");
265 EM_REG_COUNTER(&pStats->StatR3InterpretFailed, "/EM/CPU%d/R3/Interpret/Failed", "The number of times an instruction was not interpreted.");
266
267 EM_REG_COUNTER_USED(&pStats->StatRZFailedAnd, "/EM/CPU%d/RZ/Interpret/Failed/And", "The number of times AND was not interpreted.");
268 EM_REG_COUNTER_USED(&pStats->StatR3FailedAnd, "/EM/CPU%d/R3/Interpret/Failed/And", "The number of times AND was not interpreted.");
269 EM_REG_COUNTER_USED(&pStats->StatRZFailedCpuId, "/EM/CPU%d/RZ/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
270 EM_REG_COUNTER_USED(&pStats->StatR3FailedCpuId, "/EM/CPU%d/R3/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
271 EM_REG_COUNTER_USED(&pStats->StatRZFailedDec, "/EM/CPU%d/RZ/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
272 EM_REG_COUNTER_USED(&pStats->StatR3FailedDec, "/EM/CPU%d/R3/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
273 EM_REG_COUNTER_USED(&pStats->StatRZFailedHlt, "/EM/CPU%d/RZ/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
274 EM_REG_COUNTER_USED(&pStats->StatR3FailedHlt, "/EM/CPU%d/R3/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
275 EM_REG_COUNTER_USED(&pStats->StatRZFailedInc, "/EM/CPU%d/RZ/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
276 EM_REG_COUNTER_USED(&pStats->StatR3FailedInc, "/EM/CPU%d/R3/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
277 EM_REG_COUNTER_USED(&pStats->StatRZFailedInvlPg, "/EM/CPU%d/RZ/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
278 EM_REG_COUNTER_USED(&pStats->StatR3FailedInvlPg, "/EM/CPU%d/R3/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
279 EM_REG_COUNTER_USED(&pStats->StatRZFailedIret, "/EM/CPU%d/RZ/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
280 EM_REG_COUNTER_USED(&pStats->StatR3FailedIret, "/EM/CPU%d/R3/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
281 EM_REG_COUNTER_USED(&pStats->StatRZFailedLLdt, "/EM/CPU%d/RZ/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
282 EM_REG_COUNTER_USED(&pStats->StatR3FailedLLdt, "/EM/CPU%d/R3/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
283 EM_REG_COUNTER_USED(&pStats->StatRZFailedLIdt, "/EM/CPU%d/RZ/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
284 EM_REG_COUNTER_USED(&pStats->StatR3FailedLIdt, "/EM/CPU%d/R3/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
285 EM_REG_COUNTER_USED(&pStats->StatRZFailedLGdt, "/EM/CPU%d/RZ/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
286 EM_REG_COUNTER_USED(&pStats->StatR3FailedLGdt, "/EM/CPU%d/R3/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
287 EM_REG_COUNTER_USED(&pStats->StatRZFailedMov, "/EM/CPU%d/RZ/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
288 EM_REG_COUNTER_USED(&pStats->StatR3FailedMov, "/EM/CPU%d/R3/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
289 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovCRx, "/EM/CPU%d/RZ/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
290 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovCRx, "/EM/CPU%d/R3/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
291 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovDRx, "/EM/CPU%d/RZ/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
292 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovDRx, "/EM/CPU%d/R3/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
293 EM_REG_COUNTER_USED(&pStats->StatRZFailedOr, "/EM/CPU%d/RZ/Interpret/Failed/Or", "The number of times OR was not interpreted.");
294 EM_REG_COUNTER_USED(&pStats->StatR3FailedOr, "/EM/CPU%d/R3/Interpret/Failed/Or", "The number of times OR was not interpreted.");
295 EM_REG_COUNTER_USED(&pStats->StatRZFailedPop, "/EM/CPU%d/RZ/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
296 EM_REG_COUNTER_USED(&pStats->StatR3FailedPop, "/EM/CPU%d/R3/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
297 EM_REG_COUNTER_USED(&pStats->StatRZFailedSti, "/EM/CPU%d/RZ/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
298 EM_REG_COUNTER_USED(&pStats->StatR3FailedSti, "/EM/CPU%d/R3/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
299 EM_REG_COUNTER_USED(&pStats->StatRZFailedXchg, "/EM/CPU%d/RZ/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
300 EM_REG_COUNTER_USED(&pStats->StatR3FailedXchg, "/EM/CPU%d/R3/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
301 EM_REG_COUNTER_USED(&pStats->StatRZFailedXor, "/EM/CPU%d/RZ/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
302 EM_REG_COUNTER_USED(&pStats->StatR3FailedXor, "/EM/CPU%d/R3/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
303 EM_REG_COUNTER_USED(&pStats->StatRZFailedMonitor, "/EM/CPU%d/RZ/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
304 EM_REG_COUNTER_USED(&pStats->StatR3FailedMonitor, "/EM/CPU%d/R3/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
305 EM_REG_COUNTER_USED(&pStats->StatRZFailedMWait, "/EM/CPU%d/RZ/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
306 EM_REG_COUNTER_USED(&pStats->StatR3FailedMWait, "/EM/CPU%d/R3/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
307 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdtsc, "/EM/CPU%d/RZ/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
308 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdtsc, "/EM/CPU%d/R3/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
309 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdpmc, "/EM/CPU%d/RZ/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
310 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdpmc, "/EM/CPU%d/R3/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
311 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdmsr, "/EM/CPU%d/RZ/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
312 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdmsr, "/EM/CPU%d/R3/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
313 EM_REG_COUNTER_USED(&pStats->StatRZFailedWrmsr, "/EM/CPU%d/RZ/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
314 EM_REG_COUNTER_USED(&pStats->StatR3FailedWrmsr, "/EM/CPU%d/R3/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
315 EM_REG_COUNTER_USED(&pStats->StatRZFailedLmsw, "/EM/CPU%d/RZ/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
316 EM_REG_COUNTER_USED(&pStats->StatR3FailedLmsw, "/EM/CPU%d/R3/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
317
318 EM_REG_COUNTER_USED(&pStats->StatRZFailedMisc, "/EM/CPU%d/RZ/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
319 EM_REG_COUNTER_USED(&pStats->StatR3FailedMisc, "/EM/CPU%d/R3/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
320 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdd, "/EM/CPU%d/RZ/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
321 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdd, "/EM/CPU%d/R3/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
322 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdc, "/EM/CPU%d/RZ/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
323 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdc, "/EM/CPU%d/R3/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
324 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtr, "/EM/CPU%d/RZ/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
325 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtr, "/EM/CPU%d/R3/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
326 EM_REG_COUNTER_USED(&pStats->StatRZFailedBts, "/EM/CPU%d/RZ/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
327 EM_REG_COUNTER_USED(&pStats->StatR3FailedBts, "/EM/CPU%d/R3/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
328 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtc, "/EM/CPU%d/RZ/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
329 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtc, "/EM/CPU%d/R3/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
330 EM_REG_COUNTER_USED(&pStats->StatRZFailedCli, "/EM/CPU%d/RZ/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
331 EM_REG_COUNTER_USED(&pStats->StatR3FailedCli, "/EM/CPU%d/R3/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
332 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
333 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
334 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
335 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg8b, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
336 EM_REG_COUNTER_USED(&pStats->StatRZFailedXAdd, "/EM/CPU%d/RZ/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
337 EM_REG_COUNTER_USED(&pStats->StatR3FailedXAdd, "/EM/CPU%d/R3/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
338 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovNTPS, "/EM/CPU%d/RZ/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
339 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovNTPS, "/EM/CPU%d/R3/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
340 EM_REG_COUNTER_USED(&pStats->StatRZFailedStosWD, "/EM/CPU%d/RZ/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
341 EM_REG_COUNTER_USED(&pStats->StatR3FailedStosWD, "/EM/CPU%d/R3/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
342 EM_REG_COUNTER_USED(&pStats->StatRZFailedSub, "/EM/CPU%d/RZ/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
343 EM_REG_COUNTER_USED(&pStats->StatR3FailedSub, "/EM/CPU%d/R3/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
344 EM_REG_COUNTER_USED(&pStats->StatRZFailedWbInvd, "/EM/CPU%d/RZ/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
345 EM_REG_COUNTER_USED(&pStats->StatR3FailedWbInvd, "/EM/CPU%d/R3/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
346
347 EM_REG_COUNTER_USED(&pStats->StatRZFailedUserMode, "/EM/CPU%d/RZ/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
348 EM_REG_COUNTER_USED(&pStats->StatR3FailedUserMode, "/EM/CPU%d/R3/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
349 EM_REG_COUNTER_USED(&pStats->StatRZFailedPrefix, "/EM/CPU%d/RZ/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
350 EM_REG_COUNTER_USED(&pStats->StatR3FailedPrefix, "/EM/CPU%d/R3/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
351
352 EM_REG_COUNTER_USED(&pStats->StatCli, "/EM/CPU%d/R3/PrivInst/Cli", "Number of cli instructions.");
353 EM_REG_COUNTER_USED(&pStats->StatSti, "/EM/CPU%d/R3/PrivInst/Sti", "Number of sli instructions.");
354 EM_REG_COUNTER_USED(&pStats->StatIn, "/EM/CPU%d/R3/PrivInst/In", "Number of in instructions.");
355 EM_REG_COUNTER_USED(&pStats->StatOut, "/EM/CPU%d/R3/PrivInst/Out", "Number of out instructions.");
356 EM_REG_COUNTER_USED(&pStats->StatIoRestarted, "/EM/CPU%d/R3/PrivInst/IoRestarted", "Number of restarted i/o instructions.");
357 EM_REG_COUNTER_USED(&pStats->StatHlt, "/EM/CPU%d/R3/PrivInst/Hlt", "Number of hlt instructions not handled in GC because of PATM.");
358 EM_REG_COUNTER_USED(&pStats->StatInvlpg, "/EM/CPU%d/R3/PrivInst/Invlpg", "Number of invlpg instructions.");
359 EM_REG_COUNTER_USED(&pStats->StatMisc, "/EM/CPU%d/R3/PrivInst/Misc", "Number of misc. instructions.");
360 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[0], "/EM/CPU%d/R3/PrivInst/Mov CR0, X", "Number of mov CR0 read instructions.");
361 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[1], "/EM/CPU%d/R3/PrivInst/Mov CR1, X", "Number of mov CR1 read instructions.");
362 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[2], "/EM/CPU%d/R3/PrivInst/Mov CR2, X", "Number of mov CR2 read instructions.");
363 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[3], "/EM/CPU%d/R3/PrivInst/Mov CR3, X", "Number of mov CR3 read instructions.");
364 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[4], "/EM/CPU%d/R3/PrivInst/Mov CR4, X", "Number of mov CR4 read instructions.");
365 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[0], "/EM/CPU%d/R3/PrivInst/Mov X, CR0", "Number of mov CR0 write instructions.");
366 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[1], "/EM/CPU%d/R3/PrivInst/Mov X, CR1", "Number of mov CR1 write instructions.");
367 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[2], "/EM/CPU%d/R3/PrivInst/Mov X, CR2", "Number of mov CR2 write instructions.");
368 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[3], "/EM/CPU%d/R3/PrivInst/Mov X, CR3", "Number of mov CR3 write instructions.");
369 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[4], "/EM/CPU%d/R3/PrivInst/Mov X, CR4", "Number of mov CR4 write instructions.");
370 EM_REG_COUNTER_USED(&pStats->StatMovDRx, "/EM/CPU%d/R3/PrivInst/MovDRx", "Number of mov DRx instructions.");
371 EM_REG_COUNTER_USED(&pStats->StatIret, "/EM/CPU%d/R3/PrivInst/Iret", "Number of iret instructions.");
372 EM_REG_COUNTER_USED(&pStats->StatMovLgdt, "/EM/CPU%d/R3/PrivInst/Lgdt", "Number of lgdt instructions.");
373 EM_REG_COUNTER_USED(&pStats->StatMovLidt, "/EM/CPU%d/R3/PrivInst/Lidt", "Number of lidt instructions.");
374 EM_REG_COUNTER_USED(&pStats->StatMovLldt, "/EM/CPU%d/R3/PrivInst/Lldt", "Number of lldt instructions.");
375 EM_REG_COUNTER_USED(&pStats->StatSysEnter, "/EM/CPU%d/R3/PrivInst/Sysenter", "Number of sysenter instructions.");
376 EM_REG_COUNTER_USED(&pStats->StatSysExit, "/EM/CPU%d/R3/PrivInst/Sysexit", "Number of sysexit instructions.");
377 EM_REG_COUNTER_USED(&pStats->StatSysCall, "/EM/CPU%d/R3/PrivInst/Syscall", "Number of syscall instructions.");
378 EM_REG_COUNTER_USED(&pStats->StatSysRet, "/EM/CPU%d/R3/PrivInst/Sysret", "Number of sysret instructions.");
379
380 EM_REG_COUNTER(&pVCpu->em.s.StatTotalClis, "/EM/CPU%d/Cli/Total", "Total number of cli instructions executed.");
381 pVCpu->em.s.pCliStatTree = 0;
382
383 /* these should be considered for release statistics. */
384 EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%d/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction.");
385 EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%d/EM/Emulation/Priv", "Profiling of emR3RawPrivileged.");
386 EM_REG_PROFILE(&pVCpu->em.s.StatHwAccEntry, "/PROF/CPU%d/EM/HwAccEnter", "Profiling Hardware Accelerated Mode entry overhead.");
387 EM_REG_PROFILE(&pVCpu->em.s.StatHwAccExec, "/PROF/CPU%d/EM/HwAccExec", "Profiling Hardware Accelerated Mode execution.");
388 EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%d/EM/REMEmuSingle", "Profiling single instruction REM execution.");
389 EM_REG_PROFILE(&pVCpu->em.s.StatREMExec, "/PROF/CPU%d/EM/REMExec", "Profiling REM execution.");
390 EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%d/EM/REMSync", "Profiling REM context syncing.");
391 EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%d/EM/RAWEnter", "Profiling Raw Mode entry overhead.");
392 EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%d/EM/RAWExec", "Profiling Raw Mode execution.");
393 EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%d/EM/RAWTail", "Profiling Raw Mode tail overhead.");
394
395#endif /* VBOX_WITH_STATISTICS */
396
397 EM_REG_COUNTER(&pVCpu->em.s.StatForcedActions, "/PROF/CPU%d/EM/ForcedActions", "Profiling forced action execution.");
398 EM_REG_COUNTER(&pVCpu->em.s.StatHalted, "/PROF/CPU%d/EM/Halted", "Profiling halted state (VMR3WaitHalted).");
399 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatCapped, "/PROF/CPU%d/EM/Capped", "Profiling capped state (sleep).");
400 EM_REG_COUNTER(&pVCpu->em.s.StatREMTotal, "/PROF/CPU%d/EM/REMTotal", "Profiling emR3RemExecute (excluding FFs).");
401 EM_REG_COUNTER(&pVCpu->em.s.StatRAWTotal, "/PROF/CPU%d/EM/RAWTotal", "Profiling emR3RawExecute (excluding FFs).");
402
403 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatTotal, "/PROF/CPU%d/EM/Total", "Profiling EMR3ExecuteVM.");
404 }
405
406 return VINF_SUCCESS;
407}
408
409
410/**
411 * Applies relocations to data and code managed by this
412 * component. This function will be called at init and
413 * whenever the VMM need to relocate it self inside the GC.
414 *
415 * @param pVM The VM.
416 */
417VMMR3DECL(void) EMR3Relocate(PVM pVM)
418{
419 LogFlow(("EMR3Relocate\n"));
420 for (VMCPUID i = 0; i < pVM->cCpus; i++)
421 {
422 PVMCPU pVCpu = &pVM->aCpus[i];
423 if (pVCpu->em.s.pStatsR3)
424 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVCpu->em.s.pStatsR3);
425 }
426}
427
428
429/**
430 * Reset the EM state for a CPU.
431 *
432 * Called by EMR3Reset and hot plugging.
433 *
434 * @param pVCpu The virtual CPU.
435 */
436VMMR3DECL(void) EMR3ResetCpu(PVMCPU pVCpu)
437{
438 pVCpu->em.s.fForceRAW = false;
439
440 /* VMR3Reset may return VINF_EM_RESET or VINF_EM_SUSPEND, so transition
441 out of the HALTED state here so that enmPrevState doesn't end up as
442 HALTED when EMR3Execute returns. */
443 if (pVCpu->em.s.enmState == EMSTATE_HALTED)
444 {
445 Log(("EMR3ResetCpu: Cpu#%u %s -> %s\n", pVCpu->idCpu, emR3GetStateName(pVCpu->em.s.enmState), pVCpu->idCpu == 0 ? "EMSTATE_NONE" : "EMSTATE_WAIT_SIPI"));
446 pVCpu->em.s.enmState = pVCpu->idCpu == 0 ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
447 }
448}
449
450
451/**
452 * Reset notification.
453 *
454 * @param pVM The VM handle.
455 */
456VMMR3DECL(void) EMR3Reset(PVM pVM)
457{
458 Log(("EMR3Reset: \n"));
459 for (VMCPUID i = 0; i < pVM->cCpus; i++)
460 EMR3ResetCpu(&pVM->aCpus[i]);
461}
462
463
464/**
465 * Terminates the EM.
466 *
467 * Termination means cleaning up and freeing all resources,
468 * the VM it self is at this point powered off or suspended.
469 *
470 * @returns VBox status code.
471 * @param pVM The VM to operate on.
472 */
473VMMR3DECL(int) EMR3Term(PVM pVM)
474{
475 AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
476
477 PDMR3CritSectDelete(&pVM->em.s.CritSectREM);
478 return VINF_SUCCESS;
479}
480
481
482/**
483 * Execute state save operation.
484 *
485 * @returns VBox status code.
486 * @param pVM VM Handle.
487 * @param pSSM SSM operation handle.
488 */
489static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
490{
491 for (VMCPUID i = 0; i < pVM->cCpus; i++)
492 {
493 PVMCPU pVCpu = &pVM->aCpus[i];
494
495 int rc = SSMR3PutBool(pSSM, pVCpu->em.s.fForceRAW);
496 AssertRCReturn(rc, rc);
497
498 Assert(pVCpu->em.s.enmState == EMSTATE_SUSPENDED);
499 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
500 rc = SSMR3PutU32(pSSM, pVCpu->em.s.enmPrevState);
501 AssertRCReturn(rc, rc);
502
503 /* Save mwait state. */
504 rc = SSMR3PutU32(pSSM, pVCpu->em.s.mwait.fWait);
505 AssertRCReturn(rc, rc);
506 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.mwait.uMWaitEAX);
507 AssertRCReturn(rc, rc);
508 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.mwait.uMWaitECX);
509 AssertRCReturn(rc, rc);
510 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.mwait.uMonitorEAX);
511 AssertRCReturn(rc, rc);
512 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.mwait.uMonitorECX);
513 AssertRCReturn(rc, rc);
514 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.mwait.uMonitorEDX);
515 AssertRCReturn(rc, rc);
516 }
517 return VINF_SUCCESS;
518}
519
520
521/**
522 * Execute state load operation.
523 *
524 * @returns VBox status code.
525 * @param pVM VM Handle.
526 * @param pSSM SSM operation handle.
527 * @param uVersion Data layout version.
528 * @param uPass The data pass.
529 */
530static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
531{
532 /*
533 * Validate version.
534 */
535 if ( uVersion != EM_SAVED_STATE_VERSION
536 && uVersion != EM_SAVED_STATE_VERSION_PRE_MWAIT
537 && uVersion != EM_SAVED_STATE_VERSION_PRE_SMP)
538 {
539 AssertMsgFailed(("emR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, EM_SAVED_STATE_VERSION));
540 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
541 }
542 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
543
544 /*
545 * Load the saved state.
546 */
547 for (VMCPUID i = 0; i < pVM->cCpus; i++)
548 {
549 PVMCPU pVCpu = &pVM->aCpus[i];
550
551 int rc = SSMR3GetBool(pSSM, &pVCpu->em.s.fForceRAW);
552 if (RT_FAILURE(rc))
553 pVCpu->em.s.fForceRAW = false;
554 AssertRCReturn(rc, rc);
555
556 if (uVersion > EM_SAVED_STATE_VERSION_PRE_SMP)
557 {
558 AssertCompile(sizeof(pVCpu->em.s.enmPrevState) == sizeof(uint32_t));
559 rc = SSMR3GetU32(pSSM, (uint32_t *)&pVCpu->em.s.enmPrevState);
560 AssertRCReturn(rc, rc);
561 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
562
563 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
564 }
565 if (uVersion > EM_SAVED_STATE_VERSION_PRE_MWAIT)
566 {
567 /* Load mwait state. */
568 rc = SSMR3GetU32(pSSM, &pVCpu->em.s.mwait.fWait);
569 AssertRCReturn(rc, rc);
570 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.mwait.uMWaitEAX);
571 AssertRCReturn(rc, rc);
572 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.mwait.uMWaitECX);
573 AssertRCReturn(rc, rc);
574 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.mwait.uMonitorEAX);
575 AssertRCReturn(rc, rc);
576 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.mwait.uMonitorECX);
577 AssertRCReturn(rc, rc);
578 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.mwait.uMonitorEDX);
579 AssertRCReturn(rc, rc);
580 }
581
582 Assert(!pVCpu->em.s.pCliStatTree);
583 }
584 return VINF_SUCCESS;
585}
586
587
588/**
589 * Argument packet for emR3SetExecutionPolicy.
590 */
591struct EMR3SETEXECPOLICYARGS
592{
593 EMEXECPOLICY enmPolicy;
594 bool fEnforce;
595};
596
597
598/**
599 * @callback_method_impl{FNVMMEMTRENDEZVOUS, Rendezvous callback for EMR3SetExecutionPolicy.}
600 */
601static DECLCALLBACK(VBOXSTRICTRC) emR3SetExecutionPolicy(PVM pVM, PVMCPU pVCpu, void *pvUser)
602{
603 /*
604 * Only the first CPU changes the variables.
605 */
606 if (pVCpu->idCpu == 0)
607 {
608 struct EMR3SETEXECPOLICYARGS *pArgs = (struct EMR3SETEXECPOLICYARGS *)pvUser;
609 switch (pArgs->enmPolicy)
610 {
611 case EMEXECPOLICY_RECOMPILE_RING0:
612 pVM->fRecompileSupervisor = pArgs->fEnforce;
613 break;
614 case EMEXECPOLICY_RECOMPILE_RING3:
615 pVM->fRecompileUser = pArgs->fEnforce;
616 break;
617 default:
618 AssertFailedReturn(VERR_INVALID_PARAMETER);
619 }
620 Log(("emR3SetExecutionPolicy: fRecompileUser=%RTbool fRecompileSupervisor=%RTbool\n",
621 pVM->fRecompileUser, pVM->fRecompileSupervisor));
622 }
623
624 /*
625 * Force rescheduling if in RAW, HWACCM or REM.
626 */
627 return pVCpu->em.s.enmState == EMSTATE_RAW
628 || pVCpu->em.s.enmState == EMSTATE_HWACC
629 || pVCpu->em.s.enmState == EMSTATE_REM
630 ? VINF_EM_RESCHEDULE
631 : VINF_SUCCESS;
632}
633
634
635/**
636 * Changes a the execution scheduling policy.
637 *
638 * This is used to enable or disable raw-mode / hardware-virtualization
639 * execution of user and supervisor code.
640 *
641 * @returns VINF_SUCCESS on success.
642 * @returns VINF_RESCHEDULE if a rescheduling might be required.
643 * @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
644 *
645 * @param pVM The VM to operate on.
646 * @param enmPolicy The scheduling policy to change.
647 * @param fEnforce Whether to enforce the policy or not.
648 */
649VMMR3DECL(int) EMR3SetExecutionPolicy(PVM pVM, EMEXECPOLICY enmPolicy, bool fEnforce)
650{
651 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
652 AssertReturn(enmPolicy > EMEXECPOLICY_INVALID && enmPolicy < EMEXECPOLICY_END, VERR_INVALID_PARAMETER);
653
654 struct EMR3SETEXECPOLICYARGS Args = { enmPolicy, fEnforce };
655 return VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_DESCENDING, emR3SetExecutionPolicy, &Args);
656}
657
658
659/**
660 * Raise a fatal error.
661 *
662 * Safely terminate the VM with full state report and stuff. This function
663 * will naturally never return.
664 *
665 * @param pVCpu VMCPU handle.
666 * @param rc VBox status code.
667 */
668VMMR3DECL(void) EMR3FatalError(PVMCPU pVCpu, int rc)
669{
670 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
671 longjmp(pVCpu->em.s.u.FatalLongJump, rc);
672 AssertReleaseMsgFailed(("longjmp returned!\n"));
673}
674
675
676#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
677/**
678 * Gets the EM state name.
679 *
680 * @returns pointer to read only state name,
681 * @param enmState The state.
682 */
683static const char *emR3GetStateName(EMSTATE enmState)
684{
685 switch (enmState)
686 {
687 case EMSTATE_NONE: return "EMSTATE_NONE";
688 case EMSTATE_RAW: return "EMSTATE_RAW";
689 case EMSTATE_HWACC: return "EMSTATE_HWACC";
690 case EMSTATE_REM: return "EMSTATE_REM";
691 case EMSTATE_HALTED: return "EMSTATE_HALTED";
692 case EMSTATE_WAIT_SIPI: return "EMSTATE_WAIT_SIPI";
693 case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
694 case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
695 case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
696 case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
697 case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
698 case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
699 default: return "Unknown!";
700 }
701}
702#endif /* LOG_ENABLED || VBOX_STRICT */
703
704
705/**
706 * Debug loop.
707 *
708 * @returns VBox status code for EM.
709 * @param pVM VM handle.
710 * @param pVCpu VMCPU handle.
711 * @param rc Current EM VBox status code..
712 */
713static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc)
714{
715 for (;;)
716 {
717 Log(("emR3Debug: rc=%Rrc\n", rc));
718 const int rcLast = rc;
719
720 /*
721 * Debug related RC.
722 */
723 switch (rc)
724 {
725 /*
726 * Single step an instruction.
727 */
728 case VINF_EM_DBG_STEP:
729 if ( pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
730 || pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
731 || pVCpu->em.s.fForceRAW /* paranoia */)
732 rc = emR3RawStep(pVM, pVCpu);
733 else
734 {
735 Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
736 rc = emR3RemStep(pVM, pVCpu);
737 }
738 break;
739
740 /*
741 * Simple events: stepped, breakpoint, stop/assertion.
742 */
743 case VINF_EM_DBG_STEPPED:
744 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
745 break;
746
747 case VINF_EM_DBG_BREAKPOINT:
748 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
749 break;
750
751 case VINF_EM_DBG_STOP:
752 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
753 break;
754
755 case VINF_EM_DBG_HYPER_STEPPED:
756 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
757 break;
758
759 case VINF_EM_DBG_HYPER_BREAKPOINT:
760 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
761 break;
762
763 case VINF_EM_DBG_HYPER_ASSERTION:
764 RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
765 rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
766 break;
767
768 /*
769 * Guru meditation.
770 */
771 case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
772 rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
773 break;
774 case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
775 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
776 break;
777
778 default: /** @todo don't use default for guru, but make special errors code! */
779 rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
780 break;
781 }
782
783 /*
784 * Process the result.
785 */
786 do
787 {
788 switch (rc)
789 {
790 /*
791 * Continue the debugging loop.
792 */
793 case VINF_EM_DBG_STEP:
794 case VINF_EM_DBG_STOP:
795 case VINF_EM_DBG_STEPPED:
796 case VINF_EM_DBG_BREAKPOINT:
797 case VINF_EM_DBG_HYPER_STEPPED:
798 case VINF_EM_DBG_HYPER_BREAKPOINT:
799 case VINF_EM_DBG_HYPER_ASSERTION:
800 break;
801
802 /*
803 * Resuming execution (in some form) has to be done here if we got
804 * a hypervisor debug event.
805 */
806 case VINF_SUCCESS:
807 case VINF_EM_RESUME:
808 case VINF_EM_SUSPEND:
809 case VINF_EM_RESCHEDULE:
810 case VINF_EM_RESCHEDULE_RAW:
811 case VINF_EM_RESCHEDULE_REM:
812 case VINF_EM_HALT:
813 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
814 {
815 rc = emR3RawResumeHyper(pVM, pVCpu);
816 if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
817 continue;
818 }
819 if (rc == VINF_SUCCESS)
820 rc = VINF_EM_RESCHEDULE;
821 return rc;
822
823 /*
824 * The debugger isn't attached.
825 * We'll simply turn the thing off since that's the easiest thing to do.
826 */
827 case VERR_DBGF_NOT_ATTACHED:
828 switch (rcLast)
829 {
830 case VINF_EM_DBG_HYPER_STEPPED:
831 case VINF_EM_DBG_HYPER_BREAKPOINT:
832 case VINF_EM_DBG_HYPER_ASSERTION:
833 case VERR_TRPM_PANIC:
834 case VERR_TRPM_DONT_PANIC:
835 case VERR_VMM_RING0_ASSERTION:
836 case VERR_VMM_HYPER_CR3_MISMATCH:
837 case VERR_VMM_RING3_CALL_DISABLED:
838 return rcLast;
839 }
840 return VINF_EM_OFF;
841
842 /*
843 * Status codes terminating the VM in one or another sense.
844 */
845 case VINF_EM_TERMINATE:
846 case VINF_EM_OFF:
847 case VINF_EM_RESET:
848 case VINF_EM_NO_MEMORY:
849 case VINF_EM_RAW_STALE_SELECTOR:
850 case VINF_EM_RAW_IRET_TRAP:
851 case VERR_TRPM_PANIC:
852 case VERR_TRPM_DONT_PANIC:
853 case VERR_VMM_RING0_ASSERTION:
854 case VERR_VMM_HYPER_CR3_MISMATCH:
855 case VERR_VMM_RING3_CALL_DISABLED:
856 case VERR_INTERNAL_ERROR:
857 case VERR_INTERNAL_ERROR_2:
858 case VERR_INTERNAL_ERROR_3:
859 case VERR_INTERNAL_ERROR_4:
860 case VERR_INTERNAL_ERROR_5:
861 case VERR_IPE_UNEXPECTED_STATUS:
862 case VERR_IPE_UNEXPECTED_INFO_STATUS:
863 case VERR_IPE_UNEXPECTED_ERROR_STATUS:
864 return rc;
865
866 /*
867 * The rest is unexpected, and will keep us here.
868 */
869 default:
870 AssertMsgFailed(("Unexpected rc %Rrc!\n", rc));
871 break;
872 }
873 } while (false);
874 } /* debug for ever */
875}
876
877/**
878 * Steps recompiled code.
879 *
880 * @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
881 * VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
882 *
883 * @param pVM VM handle.
884 * @param pVCpu VMCPU handle.
885 */
886static int emR3RemStep(PVM pVM, PVMCPU pVCpu)
887{
888 LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
889
890 EMRemLock(pVM);
891
892 /*
893 * Switch to REM, step instruction, switch back.
894 */
895 int rc = REMR3State(pVM, pVCpu);
896 if (RT_SUCCESS(rc))
897 {
898 rc = REMR3Step(pVM, pVCpu);
899 REMR3StateBack(pVM, pVCpu);
900 }
901 EMRemUnlock(pVM);
902
903 LogFlow(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
904 return rc;
905}
906
907
908/**
909 * emR3RemExecute helper that syncs the state back from REM and leave the REM
910 * critical section.
911 *
912 * @returns false - new fInREMState value.
913 * @param pVM The VM handle.
914 * @param pVCpu The virtual CPU handle.
915 */
916DECLINLINE(bool) emR3RemExecuteSyncBack(PVM pVM, PVMCPU pVCpu)
917{
918 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, a);
919 REMR3StateBack(pVM, pVCpu);
920 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, a);
921
922 EMRemUnlock(pVM);
923 return false;
924}
925
926
927/**
928 * Executes recompiled code.
929 *
930 * This function contains the recompiler version of the inner
931 * execution loop (the outer loop being in EMR3ExecuteVM()).
932 *
933 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
934 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
935 *
936 * @param pVM VM handle.
937 * @param pVCpu VMCPU handle.
938 * @param pfFFDone Where to store an indicator telling whether or not
939 * FFs were done before returning.
940 *
941 */
942static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
943{
944#ifdef LOG_ENABLED
945 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
946 uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
947
948 if (pCtx->eflags.Bits.u1VM)
949 Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
950 else
951 Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x eflags=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, pCtx->eflags.u));
952#endif
953 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatREMTotal, a);
954
955#if defined(VBOX_STRICT) && defined(DEBUG_bird)
956 AssertMsg( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
957 || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVCpu)), /** @todo #1419 - get flat address. */
958 ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
959#endif
960
961 /*
962 * Spin till we get a forced action which returns anything but VINF_SUCCESS
963 * or the REM suggests raw-mode execution.
964 */
965 *pfFFDone = false;
966 bool fInREMState = false;
967 int rc = VINF_SUCCESS;
968 for (;;)
969 {
970 /*
971 * Lock REM and update the state if not already in sync.
972 *
973 * Note! Big lock, but you are not supposed to own any lock when
974 * coming in here.
975 */
976 if (!fInREMState)
977 {
978 EMRemLock(pVM);
979 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, b);
980
981 /* Flush the recompiler translation blocks if the VCPU has changed,
982 also force a full CPU state resync. */
983 if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
984 {
985 REMFlushTBs(pVM);
986 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
987 }
988 pVM->em.s.idLastRemCpu = pVCpu->idCpu;
989
990 rc = REMR3State(pVM, pVCpu);
991
992 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, b);
993 if (RT_FAILURE(rc))
994 break;
995 fInREMState = true;
996
997 /*
998 * We might have missed the raising of VMREQ, TIMER and some other
999 * important FFs while we were busy switching the state. So, check again.
1000 */
1001 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_CHECK_VM_STATE | VM_FF_RESET)
1002 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER | VMCPU_FF_REQUEST))
1003 {
1004 LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fGlobalForcedActions));
1005 goto l_REMDoForcedActions;
1006 }
1007 }
1008
1009
1010 /*
1011 * Execute REM.
1012 */
1013 if (RT_LIKELY(EMR3IsExecutionAllowed(pVM, pVCpu)))
1014 {
1015 STAM_PROFILE_START(&pVCpu->em.s.StatREMExec, c);
1016 rc = REMR3Run(pVM, pVCpu);
1017 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMExec, c);
1018 }
1019 else
1020 {
1021 /* Give up this time slice; virtual time continues */
1022 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1023 RTThreadSleep(5);
1024 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1025 rc = VINF_SUCCESS;
1026 }
1027
1028 /*
1029 * Deal with high priority post execution FFs before doing anything
1030 * else. Sync back the state and leave the lock to be on the safe side.
1031 */
1032 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1033 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1034 {
1035 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1036 rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1037 }
1038
1039 /*
1040 * Process the returned status code.
1041 */
1042 if (rc != VINF_SUCCESS)
1043 {
1044 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1045 break;
1046 if (rc != VINF_REM_INTERRUPED_FF)
1047 {
1048 /*
1049 * Anything which is not known to us means an internal error
1050 * and the termination of the VM!
1051 */
1052 AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
1053 break;
1054 }
1055 }
1056
1057
1058 /*
1059 * Check and execute forced actions.
1060 *
1061 * Sync back the VM state and leave the lock before calling any of
1062 * these, you never know what's going to happen here.
1063 */
1064#ifdef VBOX_HIGH_RES_TIMERS_HACK
1065 TMTimerPollVoid(pVM, pVCpu);
1066#endif
1067 AssertCompile((VMCPU_FF_ALL_REM_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE)) & VMCPU_FF_TIMER);
1068 if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_REM_MASK)
1069 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_REM_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE)))
1070 {
1071l_REMDoForcedActions:
1072 if (fInREMState)
1073 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1074 STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatREMTotal, a);
1075 rc = emR3ForcedActions(pVM, pVCpu, rc);
1076 STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatREMTotal, a);
1077 if ( rc != VINF_SUCCESS
1078 && rc != VINF_EM_RESCHEDULE_REM)
1079 {
1080 *pfFFDone = true;
1081 break;
1082 }
1083 }
1084
1085 } /* The Inner Loop, recompiled execution mode version. */
1086
1087
1088 /*
1089 * Returning. Sync back the VM state if required.
1090 */
1091 if (fInREMState)
1092 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1093
1094 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatREMTotal, a);
1095 return rc;
1096}
1097
1098
1099#ifdef DEBUG
1100
1101int emR3SingleStepExecRem(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1102{
1103 EMSTATE enmOldState = pVCpu->em.s.enmState;
1104
1105 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1106
1107 Log(("Single step BEGIN:\n"));
1108 for (uint32_t i = 0; i < cIterations; i++)
1109 {
1110 DBGFR3PrgStep(pVCpu);
1111 DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
1112 emR3RemStep(pVM, pVCpu);
1113 if (emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx) != EMSTATE_REM)
1114 break;
1115 }
1116 Log(("Single step END:\n"));
1117 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1118 pVCpu->em.s.enmState = enmOldState;
1119 return VINF_EM_RESCHEDULE;
1120}
1121
1122#endif /* DEBUG */
1123
1124
1125/**
1126 * Decides whether to execute RAW, HWACC or REM.
1127 *
1128 * @returns new EM state
1129 * @param pVM The VM.
1130 * @param pVCpu The VMCPU handle.
1131 * @param pCtx The CPU context.
1132 */
1133EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1134{
1135#ifdef IEM_VERIFICATION_MODE
1136 return EMSTATE_REM;
1137#else
1138
1139 /*
1140 * When forcing raw-mode execution, things are simple.
1141 */
1142 if (pVCpu->em.s.fForceRAW)
1143 return EMSTATE_RAW;
1144
1145 /*
1146 * We stay in the wait for SIPI state unless explicitly told otherwise.
1147 */
1148 if (pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI)
1149 return EMSTATE_WAIT_SIPI;
1150
1151 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1152 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1153 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1154
1155 X86EFLAGS EFlags = pCtx->eflags;
1156 if (HWACCMIsEnabled(pVM))
1157 {
1158 /*
1159 * Hardware accelerated raw-mode:
1160 *
1161 * Typically only 32-bits protected mode, with paging enabled, code is
1162 * allowed here.
1163 */
1164 if ( EMIsHwVirtExecutionEnabled(pVM)
1165 && HWACCMR3CanExecuteGuest(pVM, pCtx))
1166 return EMSTATE_HWACC;
1167
1168 /*
1169 * Note! Raw mode and hw accelerated mode are incompatible. The latter
1170 * turns off monitoring features essential for raw mode!
1171 */
1172 return EMSTATE_REM;
1173 }
1174
1175 /*
1176 * Standard raw-mode:
1177 *
1178 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1179 * or 32 bits protected mode ring 0 code
1180 *
1181 * The tests are ordered by the likelihood of being true during normal execution.
1182 */
1183 if (EFlags.u32 & (X86_EFL_TF /* | HF_INHIBIT_IRQ_MASK*/))
1184 {
1185 Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
1186 return EMSTATE_REM;
1187 }
1188
1189# ifndef VBOX_RAW_V86
1190 if (EFlags.u32 & X86_EFL_VM) {
1191 Log2(("raw mode refused: VM_MASK\n"));
1192 return EMSTATE_REM;
1193 }
1194# endif
1195
1196 /** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
1197 uint32_t u32CR0 = pCtx->cr0;
1198 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
1199 {
1200 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1201 return EMSTATE_REM;
1202 }
1203
1204 if (pCtx->cr4 & X86_CR4_PAE)
1205 {
1206 uint32_t u32Dummy, u32Features;
1207
1208 CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1209 if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
1210 return EMSTATE_REM;
1211 }
1212
1213 unsigned uSS = pCtx->ss;
1214 if ( pCtx->eflags.Bits.u1VM
1215 || (uSS & X86_SEL_RPL) == 3)
1216 {
1217 if (!EMIsRawRing3Enabled(pVM))
1218 return EMSTATE_REM;
1219
1220 if (!(EFlags.u32 & X86_EFL_IF))
1221 {
1222 Log2(("raw mode refused: IF (RawR3)\n"));
1223 return EMSTATE_REM;
1224 }
1225
1226 if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
1227 {
1228 Log2(("raw mode refused: CR0.WP + RawR0\n"));
1229 return EMSTATE_REM;
1230 }
1231 }
1232 else
1233 {
1234 if (!EMIsRawRing0Enabled(pVM))
1235 return EMSTATE_REM;
1236
1237 /* Only ring 0 supervisor code. */
1238 if ((uSS & X86_SEL_RPL) != 0)
1239 {
1240 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
1241 return EMSTATE_REM;
1242 }
1243
1244 // Let's start with pure 32 bits ring 0 code first
1245 /** @todo What's pure 32-bit mode? flat? */
1246 if ( !(pCtx->ssHid.Attr.n.u1DefBig)
1247 || !(pCtx->csHid.Attr.n.u1DefBig))
1248 {
1249 Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
1250 return EMSTATE_REM;
1251 }
1252
1253 /* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
1254 if (!(u32CR0 & X86_CR0_WP))
1255 {
1256 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1257 return EMSTATE_REM;
1258 }
1259
1260 if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
1261 {
1262 Log2(("raw r0 mode forced: patch code\n"));
1263 return EMSTATE_RAW;
1264 }
1265
1266# if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1267 if (!(EFlags.u32 & X86_EFL_IF))
1268 {
1269 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
1270 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1271 return EMSTATE_REM;
1272 }
1273# endif
1274
1275 /** @todo still necessary??? */
1276 if (EFlags.Bits.u2IOPL != 0)
1277 {
1278 Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
1279 return EMSTATE_REM;
1280 }
1281 }
1282
1283 Assert(PGMPhysIsA20Enabled(pVCpu));
1284 return EMSTATE_RAW;
1285#endif /* !IEM_VERIFICATION_MODE */
1286
1287}
1288
1289
1290/**
1291 * Executes all high priority post execution force actions.
1292 *
1293 * @returns rc or a fatal status code.
1294 *
1295 * @param pVM VM handle.
1296 * @param pVCpu VMCPU handle.
1297 * @param rc The current rc.
1298 */
1299int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1300{
1301 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PDM_CRITSECT))
1302 PDMCritSectFF(pVCpu);
1303
1304 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION))
1305 CSAMR3DoPendingAction(pVM, pVCpu);
1306
1307 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1308 {
1309 if ( rc > VINF_EM_NO_MEMORY
1310 && rc <= VINF_EM_LAST)
1311 rc = VINF_EM_NO_MEMORY;
1312 }
1313
1314 return rc;
1315}
1316
1317
1318/**
1319 * Executes all pending forced actions.
1320 *
1321 * Forced actions can cause execution delays and execution
1322 * rescheduling. The first we deal with using action priority, so
1323 * that for instance pending timers aren't scheduled and ran until
1324 * right before execution. The rescheduling we deal with using
1325 * return codes. The same goes for VM termination, only in that case
1326 * we exit everything.
1327 *
1328 * @returns VBox status code of equal or greater importance/severity than rc.
1329 * The most important ones are: VINF_EM_RESCHEDULE,
1330 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1331 *
1332 * @param pVM VM handle.
1333 * @param pVCpu VMCPU handle.
1334 * @param rc The current rc.
1335 *
1336 */
1337int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1338{
1339 STAM_REL_PROFILE_START(&pVCpu->em.s.StatForcedActions, a);
1340#ifdef VBOX_STRICT
1341 int rcIrq = VINF_SUCCESS;
1342#endif
1343 int rc2;
1344#define UPDATE_RC() \
1345 do { \
1346 AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
1347 if (rc2 == VINF_SUCCESS || rc < VINF_SUCCESS) \
1348 break; \
1349 if (!rc || rc2 < rc) \
1350 rc = rc2; \
1351 } while (0)
1352
1353 /*
1354 * Post execution chunk first.
1355 */
1356 if ( VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK)
1357 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_POST_MASK))
1358 {
1359 /*
1360 * EMT Rendezvous (must be serviced before termination).
1361 */
1362 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1363 {
1364 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1365 UPDATE_RC();
1366 /** @todo HACK ALERT! The following test is to make sure EM+TM
1367 * thinks the VM is stopped/reset before the next VM state change
1368 * is made. We need a better solution for this, or at least make it
1369 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1370 * VINF_EM_SUSPEND). */
1371 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1372 {
1373 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1374 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1375 return rc;
1376 }
1377 }
1378
1379 /*
1380 * State change request (cleared by vmR3SetStateLocked).
1381 */
1382 if (VM_FF_ISPENDING(pVM, VM_FF_CHECK_VM_STATE))
1383 {
1384 VMSTATE enmState = VMR3GetState(pVM);
1385 switch (enmState)
1386 {
1387 case VMSTATE_FATAL_ERROR:
1388 case VMSTATE_FATAL_ERROR_LS:
1389 Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
1390 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1391 return VINF_EM_SUSPEND;
1392
1393 case VMSTATE_DESTROYING:
1394 Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
1395 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1396 return VINF_EM_TERMINATE;
1397
1398 default:
1399 AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
1400 }
1401 }
1402
1403 /*
1404 * Debugger Facility polling.
1405 */
1406 if (VM_FF_ISPENDING(pVM, VM_FF_DBGF))
1407 {
1408 rc2 = DBGFR3VMMForcedAction(pVM);
1409 UPDATE_RC();
1410 }
1411
1412 /*
1413 * Postponed reset request.
1414 */
1415 if (VM_FF_TESTANDCLEAR(pVM, VM_FF_RESET))
1416 {
1417 rc2 = VMR3Reset(pVM);
1418 UPDATE_RC();
1419 }
1420
1421 /*
1422 * CSAM page scanning.
1423 */
1424 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1425 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE))
1426 {
1427 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1428
1429 /** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
1430 Log(("Forced action VMCPU_FF_CSAM_SCAN_PAGE\n"));
1431
1432 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1433 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE);
1434 }
1435
1436 /*
1437 * Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
1438 */
1439 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1440 {
1441 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1442 UPDATE_RC();
1443 if (rc == VINF_EM_NO_MEMORY)
1444 return rc;
1445 }
1446
1447 /* check that we got them all */
1448 AssertCompile(VM_FF_NORMAL_PRIORITY_POST_MASK == (VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1449 AssertCompile(VMCPU_FF_NORMAL_PRIORITY_POST_MASK == VMCPU_FF_CSAM_SCAN_PAGE);
1450 }
1451
1452 /*
1453 * Normal priority then.
1454 * (Executed in no particular order.)
1455 */
1456 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_NORMAL_PRIORITY_MASK, VM_FF_PGM_NO_MEMORY))
1457 {
1458 /*
1459 * PDM Queues are pending.
1460 */
1461 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_QUEUES, VM_FF_PGM_NO_MEMORY))
1462 PDMR3QueueFlushAll(pVM);
1463
1464 /*
1465 * PDM DMA transfers are pending.
1466 */
1467 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_DMA, VM_FF_PGM_NO_MEMORY))
1468 PDMR3DmaRun(pVM);
1469
1470 /*
1471 * EMT Rendezvous (make sure they are handled before the requests).
1472 */
1473 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1474 {
1475 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1476 UPDATE_RC();
1477 /** @todo HACK ALERT! The following test is to make sure EM+TM
1478 * thinks the VM is stopped/reset before the next VM state change
1479 * is made. We need a better solution for this, or at least make it
1480 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1481 * VINF_EM_SUSPEND). */
1482 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1483 {
1484 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1485 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1486 return rc;
1487 }
1488 }
1489
1490 /*
1491 * Requests from other threads.
1492 */
1493 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
1494 {
1495 rc2 = VMR3ReqProcessU(pVM->pUVM, VMCPUID_ANY, false /*fPriorityOnly*/);
1496 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE) /** @todo this shouldn't be necessary */
1497 {
1498 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1499 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1500 return rc2;
1501 }
1502 UPDATE_RC();
1503 /** @todo HACK ALERT! The following test is to make sure EM+TM
1504 * thinks the VM is stopped/reset before the next VM state change
1505 * is made. We need a better solution for this, or at least make it
1506 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1507 * VINF_EM_SUSPEND). */
1508 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1509 {
1510 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1511 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1512 return rc;
1513 }
1514 }
1515
1516 /* Replay the handler notification changes. */
1517 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REM_HANDLER_NOTIFY, VM_FF_PGM_NO_MEMORY))
1518 {
1519 /* Try not to cause deadlocks. */
1520 if ( pVM->cCpus == 1
1521 || ( !PGMIsLockOwner(pVM)
1522 && !IOMIsLockOwner(pVM))
1523 )
1524 {
1525 EMRemLock(pVM);
1526 REMR3ReplayHandlerNotifications(pVM);
1527 EMRemUnlock(pVM);
1528 }
1529 }
1530
1531 /* check that we got them all */
1532 AssertCompile(VM_FF_NORMAL_PRIORITY_MASK == (VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_REM_HANDLER_NOTIFY | VM_FF_EMT_RENDEZVOUS));
1533 }
1534
1535 /*
1536 * Normal priority then. (per-VCPU)
1537 * (Executed in no particular order.)
1538 */
1539 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1540 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_MASK))
1541 {
1542 /*
1543 * Requests from other threads.
1544 */
1545 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1546 {
1547 rc2 = VMR3ReqProcessU(pVM->pUVM, pVCpu->idCpu, false /*fPriorityOnly*/);
1548 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE || rc2 == VINF_EM_RESET)
1549 {
1550 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1551 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1552 return rc2;
1553 }
1554 UPDATE_RC();
1555 /** @todo HACK ALERT! The following test is to make sure EM+TM
1556 * thinks the VM is stopped/reset before the next VM state change
1557 * is made. We need a better solution for this, or at least make it
1558 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1559 * VINF_EM_SUSPEND). */
1560 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1561 {
1562 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1563 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1564 return rc;
1565 }
1566 }
1567
1568 /* check that we got them all */
1569 Assert(!(VMCPU_FF_NORMAL_PRIORITY_MASK & ~(VMCPU_FF_REQUEST)));
1570 }
1571
1572 /*
1573 * High priority pre execution chunk last.
1574 * (Executed in ascending priority order.)
1575 */
1576 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK)
1577 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_MASK))
1578 {
1579 /*
1580 * Timers before interrupts.
1581 */
1582 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER)
1583 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1584 TMR3TimerQueuesDo(pVM);
1585
1586 /*
1587 * The instruction following an emulated STI should *always* be executed!
1588 *
1589 * Note! We intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if
1590 * the eip is the same as the inhibited instr address. Before we
1591 * are able to execute this instruction in raw mode (iret to
1592 * guest code) an external interrupt might force a world switch
1593 * again. Possibly allowing a guest interrupt to be dispatched
1594 * in the process. This could break the guest. Sounds very
1595 * unlikely, but such timing sensitive problem are not as rare as
1596 * you might think.
1597 */
1598 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1599 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1600 {
1601 if (CPUMGetGuestRIP(pVCpu) != EMGetInhibitInterruptsPC(pVCpu))
1602 {
1603 Log(("Clearing VMCPU_FF_INHIBIT_INTERRUPTS at %RGv - successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu), EMGetInhibitInterruptsPC(pVCpu)));
1604 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1605 }
1606 else
1607 Log(("Leaving VMCPU_FF_INHIBIT_INTERRUPTS set at %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu)));
1608 }
1609
1610 /*
1611 * Interrupts.
1612 */
1613 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1614 && !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1615 && (!rc || rc >= VINF_EM_RESCHEDULE_HWACC)
1616 && !TRPMHasTrap(pVCpu) /* an interrupt could already be scheduled for dispatching in the recompiler. */
1617 && PATMAreInterruptsEnabled(pVM)
1618 && !HWACCMR3IsEventPending(pVCpu))
1619 {
1620 Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1621 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
1622 {
1623 /* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
1624 /** @todo this really isn't nice, should properly handle this */
1625 rc2 = TRPMR3InjectEvent(pVM, pVCpu, TRPM_HARDWARE_INT);
1626#ifdef VBOX_STRICT
1627 rcIrq = rc2;
1628#endif
1629 UPDATE_RC();
1630 }
1631 /** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
1632 else if (REMR3QueryPendingInterrupt(pVM, pVCpu) != REM_NO_PENDING_IRQ)
1633 {
1634 rc2 = VINF_EM_RESCHEDULE_REM;
1635 UPDATE_RC();
1636 }
1637 }
1638
1639 /*
1640 * Allocate handy pages.
1641 */
1642 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1643 {
1644 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1645 UPDATE_RC();
1646 }
1647
1648 /*
1649 * Debugger Facility request.
1650 */
1651 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_DBGF, VM_FF_PGM_NO_MEMORY))
1652 {
1653 rc2 = DBGFR3VMMForcedAction(pVM);
1654 UPDATE_RC();
1655 }
1656
1657 /*
1658 * EMT Rendezvous (must be serviced before termination).
1659 */
1660 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1661 {
1662 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1663 UPDATE_RC();
1664 /** @todo HACK ALERT! The following test is to make sure EM+TM thinks the VM is
1665 * stopped/reset before the next VM state change is made. We need a better
1666 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1667 * && rc >= VINF_EM_SUSPEND). */
1668 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1669 {
1670 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1671 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1672 return rc;
1673 }
1674 }
1675
1676 /*
1677 * State change request (cleared by vmR3SetStateLocked).
1678 */
1679 if (VM_FF_ISPENDING(pVM, VM_FF_CHECK_VM_STATE))
1680 {
1681 VMSTATE enmState = VMR3GetState(pVM);
1682 switch (enmState)
1683 {
1684 case VMSTATE_FATAL_ERROR:
1685 case VMSTATE_FATAL_ERROR_LS:
1686 Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
1687 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1688 return VINF_EM_SUSPEND;
1689
1690 case VMSTATE_DESTROYING:
1691 Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
1692 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1693 return VINF_EM_TERMINATE;
1694
1695 default:
1696 AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
1697 }
1698 }
1699
1700 /*
1701 * Out of memory? Since most of our fellow high priority actions may cause us
1702 * to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
1703 * at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
1704 * than us since we can terminate without allocating more memory.
1705 */
1706 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1707 {
1708 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1709 UPDATE_RC();
1710 if (rc == VINF_EM_NO_MEMORY)
1711 return rc;
1712 }
1713
1714 /*
1715 * If the virtual sync clock is still stopped, make TM restart it.
1716 */
1717 if (VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
1718 TMR3VirtualSyncFF(pVM, pVCpu);
1719
1720#ifdef DEBUG
1721 /*
1722 * Debug, pause the VM.
1723 */
1724 if (VM_FF_ISPENDING(pVM, VM_FF_DEBUG_SUSPEND))
1725 {
1726 VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
1727 Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
1728 return VINF_EM_SUSPEND;
1729 }
1730#endif
1731
1732 /* check that we got them all */
1733 AssertCompile(VM_FF_HIGH_PRIORITY_PRE_MASK == (VM_FF_TM_VIRTUAL_SYNC | VM_FF_DBGF | VM_FF_CHECK_VM_STATE | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1734 AssertCompile(VMCPU_FF_HIGH_PRIORITY_PRE_MASK == (VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_INHIBIT_INTERRUPTS));
1735 }
1736
1737#undef UPDATE_RC
1738 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1739 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1740 Assert(rcIrq == VINF_SUCCESS || rcIrq == rc);
1741 return rc;
1742}
1743
1744
1745/**
1746 * Check if the preset execution time cap restricts guest execution scheduling.
1747 *
1748 * @returns true if allowed, false otherwise
1749 * @param pVM The VM to operate on.
1750 * @param pVCpu The VMCPU to operate on.
1751 *
1752 */
1753VMMR3DECL(bool) EMR3IsExecutionAllowed(PVM pVM, PVMCPU pVCpu)
1754{
1755 uint64_t u64UserTime, u64KernelTime;
1756
1757 if ( pVM->uCpuExecutionCap != 100
1758 && RT_SUCCESS(RTThreadGetExecutionTimeMilli(&u64KernelTime, &u64UserTime)))
1759 {
1760 uint64_t u64TimeNow = RTTimeMilliTS();
1761 if (pVCpu->em.s.u64TimeSliceStart + EM_TIME_SLICE < u64TimeNow)
1762 {
1763 /* New time slice. */
1764 pVCpu->em.s.u64TimeSliceStart = u64TimeNow;
1765 pVCpu->em.s.u64TimeSliceStartExec = u64KernelTime + u64UserTime;
1766 pVCpu->em.s.u64TimeSliceExec = 0;
1767 }
1768 pVCpu->em.s.u64TimeSliceExec = u64KernelTime + u64UserTime - pVCpu->em.s.u64TimeSliceStartExec;
1769
1770 Log2(("emR3IsExecutionAllowed: start=%RX64 startexec=%RX64 exec=%RX64 (cap=%x)\n", pVCpu->em.s.u64TimeSliceStart, pVCpu->em.s.u64TimeSliceStartExec, pVCpu->em.s.u64TimeSliceExec, (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100));
1771 if (pVCpu->em.s.u64TimeSliceExec >= (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100)
1772 return false;
1773 }
1774 return true;
1775}
1776
1777
1778/**
1779 * Execute VM.
1780 *
1781 * This function is the main loop of the VM. The emulation thread
1782 * calls this function when the VM has been successfully constructed
1783 * and we're ready for executing the VM.
1784 *
1785 * Returning from this function means that the VM is turned off or
1786 * suspended (state already saved) and deconstruction in next in line.
1787 *
1788 * All interaction from other thread are done using forced actions
1789 * and signaling of the wait object.
1790 *
1791 * @returns VBox status code, informational status codes may indicate failure.
1792 * @param pVM The VM to operate on.
1793 * @param pVCpu The VMCPU to operate on.
1794 */
1795VMMR3DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu)
1796{
1797 Log(("EMR3ExecuteVM: pVM=%p enmVMState=%d (%s) enmState=%d (%s) enmPrevState=%d (%s) fForceRAW=%RTbool\n",
1798 pVM,
1799 pVM->enmVMState, VMR3GetStateName(pVM->enmVMState),
1800 pVCpu->em.s.enmState, emR3GetStateName(pVCpu->em.s.enmState),
1801 pVCpu->em.s.enmPrevState, emR3GetStateName(pVCpu->em.s.enmPrevState),
1802 pVCpu->em.s.fForceRAW));
1803 VM_ASSERT_EMT(pVM);
1804 AssertMsg( pVCpu->em.s.enmState == EMSTATE_NONE
1805 || pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI
1806 || pVCpu->em.s.enmState == EMSTATE_SUSPENDED,
1807 ("%s\n", emR3GetStateName(pVCpu->em.s.enmState)));
1808
1809 int rc = setjmp(pVCpu->em.s.u.FatalLongJump);
1810 if (rc == 0)
1811 {
1812 /*
1813 * Start the virtual time.
1814 */
1815 TMR3NotifyResume(pVM, pVCpu);
1816
1817 /*
1818 * The Outer Main Loop.
1819 */
1820 bool fFFDone = false;
1821
1822 /* Reschedule right away to start in the right state. */
1823 rc = VINF_SUCCESS;
1824
1825 /* If resuming after a pause or a state load, restore the previous
1826 state or else we'll start executing code. Else, just reschedule. */
1827 if ( pVCpu->em.s.enmState == EMSTATE_SUSPENDED
1828 && ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
1829 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED))
1830 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
1831 else
1832 pVCpu->em.s.enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1833
1834 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
1835 for (;;)
1836 {
1837 /*
1838 * Before we can schedule anything (we're here because
1839 * scheduling is required) we must service any pending
1840 * forced actions to avoid any pending action causing
1841 * immediate rescheduling upon entering an inner loop
1842 *
1843 * Do forced actions.
1844 */
1845 if ( !fFFDone
1846 && rc != VINF_EM_TERMINATE
1847 && rc != VINF_EM_OFF
1848 && ( VM_FF_ISPENDING(pVM, VM_FF_ALL_REM_MASK)
1849 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_REM_MASK)))
1850 {
1851 rc = emR3ForcedActions(pVM, pVCpu, rc);
1852 if ( ( rc == VINF_EM_RESCHEDULE_REM
1853 || rc == VINF_EM_RESCHEDULE_HWACC)
1854 && pVCpu->em.s.fForceRAW)
1855 rc = VINF_EM_RESCHEDULE_RAW;
1856 }
1857 else if (fFFDone)
1858 fFFDone = false;
1859
1860 /*
1861 * Now what to do?
1862 */
1863 Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
1864 switch (rc)
1865 {
1866 /*
1867 * Keep doing what we're currently doing.
1868 */
1869 case VINF_SUCCESS:
1870 break;
1871
1872 /*
1873 * Reschedule - to raw-mode execution.
1874 */
1875 case VINF_EM_RESCHEDULE_RAW:
1876 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVCpu->em.s.enmState, EMSTATE_RAW));
1877 pVCpu->em.s.enmState = EMSTATE_RAW;
1878 break;
1879
1880 /*
1881 * Reschedule - to hardware accelerated raw-mode execution.
1882 */
1883 case VINF_EM_RESCHEDULE_HWACC:
1884 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVCpu->em.s.enmState, EMSTATE_HWACC));
1885 Assert(!pVCpu->em.s.fForceRAW);
1886 pVCpu->em.s.enmState = EMSTATE_HWACC;
1887 break;
1888
1889 /*
1890 * Reschedule - to recompiled execution.
1891 */
1892 case VINF_EM_RESCHEDULE_REM:
1893 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVCpu->em.s.enmState, EMSTATE_REM));
1894 pVCpu->em.s.enmState = EMSTATE_REM;
1895 break;
1896
1897 /*
1898 * Resume.
1899 */
1900 case VINF_EM_RESUME:
1901 Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVCpu->em.s.enmState));
1902 /* Don't reschedule in the halted or wait for SIPI case. */
1903 if ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
1904 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED)
1905 {
1906 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
1907 break;
1908 }
1909 /* fall through and get scheduled. */
1910
1911 /*
1912 * Reschedule.
1913 */
1914 case VINF_EM_RESCHEDULE:
1915 {
1916 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1917 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, emR3GetStateName(enmState)));
1918 pVCpu->em.s.enmState = enmState;
1919 break;
1920 }
1921
1922 /*
1923 * Halted.
1924 */
1925 case VINF_EM_HALT:
1926 Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_HALTED));
1927 pVCpu->em.s.enmState = EMSTATE_HALTED;
1928 break;
1929
1930 /*
1931 * Switch to the wait for SIPI state (application processor only)
1932 */
1933 case VINF_EM_WAIT_SIPI:
1934 Assert(pVCpu->idCpu != 0);
1935 Log2(("EMR3ExecuteVM: VINF_EM_WAIT_SIPI: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_WAIT_SIPI));
1936 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
1937 break;
1938
1939
1940 /*
1941 * Suspend.
1942 */
1943 case VINF_EM_SUSPEND:
1944 Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
1945 Assert(pVCpu->em.s.enmState != EMSTATE_SUSPENDED);
1946 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
1947 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
1948 break;
1949
1950 /*
1951 * Reset.
1952 * We might end up doing a double reset for now, we'll have to clean up the mess later.
1953 */
1954 case VINF_EM_RESET:
1955 {
1956 if (pVCpu->idCpu == 0)
1957 {
1958 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1959 Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, emR3GetStateName(enmState)));
1960 pVCpu->em.s.enmState = enmState;
1961 }
1962 else
1963 {
1964 /* All other VCPUs go into the wait for SIPI state. */
1965 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
1966 }
1967 break;
1968 }
1969
1970 /*
1971 * Power Off.
1972 */
1973 case VINF_EM_OFF:
1974 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
1975 Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
1976 TMR3NotifySuspend(pVM, pVCpu);
1977 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1978 return rc;
1979
1980 /*
1981 * Terminate the VM.
1982 */
1983 case VINF_EM_TERMINATE:
1984 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
1985 Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
1986 if (pVM->enmVMState < VMSTATE_DESTROYING) /* ugly */
1987 TMR3NotifySuspend(pVM, pVCpu);
1988 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1989 return rc;
1990
1991
1992 /*
1993 * Out of memory, suspend the VM and stuff.
1994 */
1995 case VINF_EM_NO_MEMORY:
1996 Log2(("EMR3ExecuteVM: VINF_EM_NO_MEMORY: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
1997 Assert(pVCpu->em.s.enmState != EMSTATE_SUSPENDED);
1998 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
1999 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2000 TMR3NotifySuspend(pVM, pVCpu);
2001 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2002
2003 rc = VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_SUSPEND, "HostMemoryLow",
2004 N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
2005 if (rc != VINF_EM_SUSPEND)
2006 {
2007 if (RT_SUCCESS_NP(rc))
2008 {
2009 AssertLogRelMsgFailed(("%Rrc\n", rc));
2010 rc = VERR_EM_INTERNAL_ERROR;
2011 }
2012 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2013 }
2014 return rc;
2015
2016 /*
2017 * Guest debug events.
2018 */
2019 case VINF_EM_DBG_STEPPED:
2020 AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
2021 case VINF_EM_DBG_STOP:
2022 case VINF_EM_DBG_BREAKPOINT:
2023 case VINF_EM_DBG_STEP:
2024 if (pVCpu->em.s.enmState == EMSTATE_RAW)
2025 {
2026 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
2027 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
2028 }
2029 else
2030 {
2031 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
2032 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
2033 }
2034 break;
2035
2036 /*
2037 * Hypervisor debug events.
2038 */
2039 case VINF_EM_DBG_HYPER_STEPPED:
2040 case VINF_EM_DBG_HYPER_BREAKPOINT:
2041 case VINF_EM_DBG_HYPER_ASSERTION:
2042 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_HYPER));
2043 pVCpu->em.s.enmState = EMSTATE_DEBUG_HYPER;
2044 break;
2045
2046 /*
2047 * Guru mediations.
2048 */
2049 case VERR_VMM_RING0_ASSERTION:
2050 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVCpu->em.s.enmState, EMSTATE_GURU_MEDITATION));
2051 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2052 break;
2053
2054 /*
2055 * Any error code showing up here other than the ones we
2056 * know and process above are considered to be FATAL.
2057 *
2058 * Unknown warnings and informational status codes are also
2059 * included in this.
2060 */
2061 default:
2062 if (RT_SUCCESS_NP(rc))
2063 {
2064 AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
2065 rc = VERR_EM_INTERNAL_ERROR;
2066 }
2067 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVCpu->em.s.enmState, EMSTATE_GURU_MEDITATION));
2068 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2069 break;
2070 }
2071
2072 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x); /* (skip this in release) */
2073 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2074
2075 /*
2076 * Act on the state.
2077 */
2078 switch (pVCpu->em.s.enmState)
2079 {
2080 /*
2081 * Execute raw.
2082 */
2083 case EMSTATE_RAW:
2084#ifndef IEM_VERIFICATION_MODE /* remove later */
2085 rc = emR3RawExecute(pVM, pVCpu, &fFFDone);
2086 break;
2087#endif
2088
2089 /*
2090 * Execute hardware accelerated raw.
2091 */
2092 case EMSTATE_HWACC:
2093#ifndef IEM_VERIFICATION_MODE /* remove later */
2094 rc = emR3HwAccExecute(pVM, pVCpu, &fFFDone);
2095 break;
2096#endif
2097
2098 /*
2099 * Execute recompiled.
2100 */
2101 case EMSTATE_REM:
2102#ifdef IEM_VERIFICATION_MODE
2103# if 1
2104 rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu)); fFFDone = false;
2105# else
2106 rc = VBOXSTRICTRC_TODO(REMR3EmulateInstruction(pVM, pVCpu)); fFFDone = false;
2107 if (rc == VINF_EM_RESCHEDULE)
2108 rc = VINF_SUCCESS;
2109# endif
2110#else
2111 rc = emR3RemExecute(pVM, pVCpu, &fFFDone);
2112#endif
2113 Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
2114 break;
2115
2116 /*
2117 * Application processor execution halted until SIPI.
2118 */
2119 case EMSTATE_WAIT_SIPI:
2120 /* no break */
2121 /*
2122 * hlt - execution halted until interrupt.
2123 */
2124 case EMSTATE_HALTED:
2125 {
2126 STAM_REL_PROFILE_START(&pVCpu->em.s.StatHalted, y);
2127 if (pVCpu->em.s.mwait.fWait & EMMWAIT_FLAG_ACTIVE)
2128 {
2129 /* mwait has a special extension where it's woken up when an interrupt is pending even when IF=0. */
2130 rc = VMR3WaitHalted(pVM, pVCpu, !(pVCpu->em.s.mwait.fWait & EMMWAIT_FLAG_BREAKIRQIF0) && !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
2131 pVCpu->em.s.mwait.fWait &= ~(EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0);
2132 }
2133 else
2134 rc = VMR3WaitHalted(pVM, pVCpu, !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
2135
2136 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHalted, y);
2137 break;
2138 }
2139
2140 /*
2141 * Suspended - return to VM.cpp.
2142 */
2143 case EMSTATE_SUSPENDED:
2144 TMR3NotifySuspend(pVM, pVCpu);
2145 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2146 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2147 return VINF_EM_SUSPEND;
2148
2149 /*
2150 * Debugging in the guest.
2151 */
2152 case EMSTATE_DEBUG_GUEST_REM:
2153 case EMSTATE_DEBUG_GUEST_RAW:
2154 TMR3NotifySuspend(pVM, pVCpu);
2155 rc = emR3Debug(pVM, pVCpu, rc);
2156 TMR3NotifyResume(pVM, pVCpu);
2157 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2158 break;
2159
2160 /*
2161 * Debugging in the hypervisor.
2162 */
2163 case EMSTATE_DEBUG_HYPER:
2164 {
2165 TMR3NotifySuspend(pVM, pVCpu);
2166 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2167
2168 rc = emR3Debug(pVM, pVCpu, rc);
2169 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2170 if (rc != VINF_SUCCESS)
2171 {
2172 /* switch to guru meditation mode */
2173 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2174 VMMR3FatalDump(pVM, pVCpu, rc);
2175 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2176 return rc;
2177 }
2178
2179 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2180 TMR3NotifyResume(pVM, pVCpu);
2181 break;
2182 }
2183
2184 /*
2185 * Guru meditation takes place in the debugger.
2186 */
2187 case EMSTATE_GURU_MEDITATION:
2188 {
2189 TMR3NotifySuspend(pVM, pVCpu);
2190 VMMR3FatalDump(pVM, pVCpu, rc);
2191 emR3Debug(pVM, pVCpu, rc);
2192 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2193 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2194 return rc;
2195 }
2196
2197 /*
2198 * The states we don't expect here.
2199 */
2200 case EMSTATE_NONE:
2201 case EMSTATE_TERMINATING:
2202 default:
2203 AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVCpu->em.s.enmState));
2204 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2205 TMR3NotifySuspend(pVM, pVCpu);
2206 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2207 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2208 return VERR_EM_INTERNAL_ERROR;
2209 }
2210 } /* The Outer Main Loop */
2211 }
2212 else
2213 {
2214 /*
2215 * Fatal error.
2216 */
2217 Log(("EMR3ExecuteVM: returns %Rrc because of longjmp / fatal error; (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2218 TMR3NotifySuspend(pVM, pVCpu);
2219 VMMR3FatalDump(pVM, pVCpu, rc);
2220 emR3Debug(pVM, pVCpu, rc);
2221 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2222 /** @todo change the VM state! */
2223 return rc;
2224 }
2225
2226 /* (won't ever get here). */
2227 AssertFailed();
2228}
2229
2230/**
2231 * Notify EM of a state change (used by FTM)
2232 *
2233 * @param pVM VM Handle.
2234 */
2235VMMR3DECL(int) EMR3NotifySuspend(PVM pVM)
2236{
2237 PVMCPU pVCpu = VMMGetCpu(pVM);
2238
2239 TMR3NotifySuspend(pVM, pVCpu); /* Stop the virtual time. */
2240 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
2241 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2242 return VINF_SUCCESS;
2243}
2244
2245/**
2246 * Notify EM of a state change (used by FTM)
2247 *
2248 * @param pVM VM Handle.
2249 */
2250VMMR3DECL(int) EMR3NotifyResume(PVM pVM)
2251{
2252 PVMCPU pVCpu = VMMGetCpu(pVM);
2253 EMSTATE enmCurState = pVCpu->em.s.enmState;
2254
2255 TMR3NotifyResume(pVM, pVCpu); /* Resume the virtual time. */
2256 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2257 pVCpu->em.s.enmPrevState = enmCurState;
2258 return VINF_SUCCESS;
2259}
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