VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/EM.cpp@ 37423

Last change on this file since 37423 was 36825, checked in by vboxsync, 14 years ago

EM: Check inhibit pc against RIP, not EIP. Corrected logging.
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File size: 101.5 KB
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1/* $Id: EM.cpp 36825 2011-04-23 22:41:20Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2011 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_em EM - The Execution Monitor / Manager
19 *
20 * The Execution Monitor/Manager is responsible for running the VM, scheduling
21 * the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
22 * Interpreted), and keeping the CPU states in sync. The function
23 * EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
24 * modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
25 * emR3RemExecute).
26 *
27 * The interpreted execution is only used to avoid switching between
28 * raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
29 * The interpretation is thus implemented as part of EM.
30 *
31 * @see grp_em
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_EM
38#include <VBox/vmm/em.h>
39#include <VBox/vmm/vmm.h>
40#include <VBox/vmm/patm.h>
41#include <VBox/vmm/csam.h>
42#include <VBox/vmm/selm.h>
43#include <VBox/vmm/trpm.h>
44#include <VBox/vmm/iom.h>
45#include <VBox/vmm/dbgf.h>
46#include <VBox/vmm/pgm.h>
47#include <VBox/vmm/rem.h>
48#include <VBox/vmm/tm.h>
49#include <VBox/vmm/mm.h>
50#include <VBox/vmm/ssm.h>
51#include <VBox/vmm/pdmapi.h>
52#include <VBox/vmm/pdmcritsect.h>
53#include <VBox/vmm/pdmqueue.h>
54#include <VBox/vmm/hwaccm.h>
55#include <VBox/vmm/patm.h>
56#ifdef IEM_VERIFICATION_MODE
57# include <VBox/vmm/iem.h>
58#endif
59#include "EMInternal.h"
60#include "internal/em.h"
61#include <VBox/vmm/vm.h>
62#include <VBox/vmm/cpumdis.h>
63#include <VBox/dis.h>
64#include <VBox/disopcode.h>
65#include <VBox/vmm/dbgf.h>
66
67#include <iprt/asm.h>
68#include <iprt/string.h>
69#include <iprt/stream.h>
70#include <iprt/thread.h>
71
72
73/*******************************************************************************
74* Defined Constants And Macros *
75*******************************************************************************/
76#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
77#define EM_NOTIFY_HWACCM
78#endif
79
80
81/*******************************************************************************
82* Internal Functions *
83*******************************************************************************/
84static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
85static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
86static const char *emR3GetStateName(EMSTATE enmState);
87static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc);
88static int emR3RemStep(PVM pVM, PVMCPU pVCpu);
89static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
90int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
91
92
93/**
94 * Initializes the EM.
95 *
96 * @returns VBox status code.
97 * @param pVM The VM to operate on.
98 */
99VMMR3DECL(int) EMR3Init(PVM pVM)
100{
101 LogFlow(("EMR3Init\n"));
102 /*
103 * Assert alignment and sizes.
104 */
105 AssertCompileMemberAlignment(VM, em.s, 32);
106 AssertCompile(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
107 AssertCompile(sizeof(pVM->aCpus[0].em.s.u.FatalLongJump) <= sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump));
108 AssertCompileMemberAlignment(EM, CritSectREM, sizeof(uintptr_t));
109
110 /*
111 * Init the structure.
112 */
113 pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
114 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
115 if (RT_FAILURE(rc))
116 pVM->fRawR3Enabled = true;
117 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
118 if (RT_FAILURE(rc))
119 pVM->fRawR0Enabled = true;
120 Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
121
122 /*
123 * Initialize the REM critical section.
124 */
125 rc = PDMR3CritSectInit(pVM, &pVM->em.s.CritSectREM, RT_SRC_POS, "EM-REM");
126 AssertRCReturn(rc, rc);
127
128 /*
129 * Saved state.
130 */
131 rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
132 NULL, NULL, NULL,
133 NULL, emR3Save, NULL,
134 NULL, emR3Load, NULL);
135 if (RT_FAILURE(rc))
136 return rc;
137
138 for (VMCPUID i = 0; i < pVM->cCpus; i++)
139 {
140 PVMCPU pVCpu = &pVM->aCpus[i];
141
142 pVCpu->em.s.offVMCPU = RT_OFFSETOF(VMCPU, em.s);
143
144 pVCpu->em.s.enmState = (i == 0) ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
145 pVCpu->em.s.enmPrevState = EMSTATE_NONE;
146 pVCpu->em.s.fForceRAW = false;
147
148 pVCpu->em.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
149 pVCpu->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
150 AssertMsg(pVCpu->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
151
152 /* Force reset of the time slice. */
153 pVCpu->em.s.u64TimeSliceStart = 0;
154
155# define EM_REG_COUNTER(a, b, c) \
156 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
157 AssertRC(rc);
158
159# define EM_REG_COUNTER_USED(a, b, c) \
160 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, c, b, i); \
161 AssertRC(rc);
162
163# define EM_REG_PROFILE(a, b, c) \
164 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
165 AssertRC(rc);
166
167# define EM_REG_PROFILE_ADV(a, b, c) \
168 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
169 AssertRC(rc);
170
171 /*
172 * Statistics.
173 */
174#ifdef VBOX_WITH_STATISTICS
175 PEMSTATS pStats;
176 rc = MMHyperAlloc(pVM, sizeof(*pStats), 0, MM_TAG_EM, (void **)&pStats);
177 if (RT_FAILURE(rc))
178 return rc;
179
180 pVCpu->em.s.pStatsR3 = pStats;
181 pVCpu->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
182 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
183
184 EM_REG_PROFILE(&pStats->StatRZEmulate, "/EM/CPU%d/RZ/Interpret", "Profiling of EMInterpretInstruction.");
185 EM_REG_PROFILE(&pStats->StatR3Emulate, "/EM/CPU%d/R3/Interpret", "Profiling of EMInterpretInstruction.");
186
187 EM_REG_PROFILE(&pStats->StatRZInterpretSucceeded, "/EM/CPU%d/RZ/Interpret/Success", "The number of times an instruction was successfully interpreted.");
188 EM_REG_PROFILE(&pStats->StatR3InterpretSucceeded, "/EM/CPU%d/R3/Interpret/Success", "The number of times an instruction was successfully interpreted.");
189
190 EM_REG_COUNTER_USED(&pStats->StatRZAnd, "/EM/CPU%d/RZ/Interpret/Success/And", "The number of times AND was successfully interpreted.");
191 EM_REG_COUNTER_USED(&pStats->StatR3And, "/EM/CPU%d/R3/Interpret/Success/And", "The number of times AND was successfully interpreted.");
192 EM_REG_COUNTER_USED(&pStats->StatRZAdd, "/EM/CPU%d/RZ/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
193 EM_REG_COUNTER_USED(&pStats->StatR3Add, "/EM/CPU%d/R3/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
194 EM_REG_COUNTER_USED(&pStats->StatRZAdc, "/EM/CPU%d/RZ/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
195 EM_REG_COUNTER_USED(&pStats->StatR3Adc, "/EM/CPU%d/R3/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
196 EM_REG_COUNTER_USED(&pStats->StatRZSub, "/EM/CPU%d/RZ/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
197 EM_REG_COUNTER_USED(&pStats->StatR3Sub, "/EM/CPU%d/R3/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
198 EM_REG_COUNTER_USED(&pStats->StatRZCpuId, "/EM/CPU%d/RZ/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
199 EM_REG_COUNTER_USED(&pStats->StatR3CpuId, "/EM/CPU%d/R3/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
200 EM_REG_COUNTER_USED(&pStats->StatRZDec, "/EM/CPU%d/RZ/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
201 EM_REG_COUNTER_USED(&pStats->StatR3Dec, "/EM/CPU%d/R3/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
202 EM_REG_COUNTER_USED(&pStats->StatRZHlt, "/EM/CPU%d/RZ/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
203 EM_REG_COUNTER_USED(&pStats->StatR3Hlt, "/EM/CPU%d/R3/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
204 EM_REG_COUNTER_USED(&pStats->StatRZInc, "/EM/CPU%d/RZ/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
205 EM_REG_COUNTER_USED(&pStats->StatR3Inc, "/EM/CPU%d/R3/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
206 EM_REG_COUNTER_USED(&pStats->StatRZInvlPg, "/EM/CPU%d/RZ/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
207 EM_REG_COUNTER_USED(&pStats->StatR3InvlPg, "/EM/CPU%d/R3/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
208 EM_REG_COUNTER_USED(&pStats->StatRZIret, "/EM/CPU%d/RZ/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
209 EM_REG_COUNTER_USED(&pStats->StatR3Iret, "/EM/CPU%d/R3/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
210 EM_REG_COUNTER_USED(&pStats->StatRZLLdt, "/EM/CPU%d/RZ/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
211 EM_REG_COUNTER_USED(&pStats->StatR3LLdt, "/EM/CPU%d/R3/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
212 EM_REG_COUNTER_USED(&pStats->StatRZLIdt, "/EM/CPU%d/RZ/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
213 EM_REG_COUNTER_USED(&pStats->StatR3LIdt, "/EM/CPU%d/R3/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
214 EM_REG_COUNTER_USED(&pStats->StatRZLGdt, "/EM/CPU%d/RZ/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
215 EM_REG_COUNTER_USED(&pStats->StatR3LGdt, "/EM/CPU%d/R3/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
216 EM_REG_COUNTER_USED(&pStats->StatRZMov, "/EM/CPU%d/RZ/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
217 EM_REG_COUNTER_USED(&pStats->StatR3Mov, "/EM/CPU%d/R3/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
218 EM_REG_COUNTER_USED(&pStats->StatRZMovCRx, "/EM/CPU%d/RZ/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
219 EM_REG_COUNTER_USED(&pStats->StatR3MovCRx, "/EM/CPU%d/R3/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
220 EM_REG_COUNTER_USED(&pStats->StatRZMovDRx, "/EM/CPU%d/RZ/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
221 EM_REG_COUNTER_USED(&pStats->StatR3MovDRx, "/EM/CPU%d/R3/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
222 EM_REG_COUNTER_USED(&pStats->StatRZOr, "/EM/CPU%d/RZ/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
223 EM_REG_COUNTER_USED(&pStats->StatR3Or, "/EM/CPU%d/R3/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
224 EM_REG_COUNTER_USED(&pStats->StatRZPop, "/EM/CPU%d/RZ/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
225 EM_REG_COUNTER_USED(&pStats->StatR3Pop, "/EM/CPU%d/R3/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
226 EM_REG_COUNTER_USED(&pStats->StatRZRdtsc, "/EM/CPU%d/RZ/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
227 EM_REG_COUNTER_USED(&pStats->StatR3Rdtsc, "/EM/CPU%d/R3/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
228 EM_REG_COUNTER_USED(&pStats->StatRZRdpmc, "/EM/CPU%d/RZ/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
229 EM_REG_COUNTER_USED(&pStats->StatR3Rdpmc, "/EM/CPU%d/R3/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
230 EM_REG_COUNTER_USED(&pStats->StatRZSti, "/EM/CPU%d/RZ/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
231 EM_REG_COUNTER_USED(&pStats->StatR3Sti, "/EM/CPU%d/R3/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
232 EM_REG_COUNTER_USED(&pStats->StatRZXchg, "/EM/CPU%d/RZ/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
233 EM_REG_COUNTER_USED(&pStats->StatR3Xchg, "/EM/CPU%d/R3/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
234 EM_REG_COUNTER_USED(&pStats->StatRZXor, "/EM/CPU%d/RZ/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
235 EM_REG_COUNTER_USED(&pStats->StatR3Xor, "/EM/CPU%d/R3/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
236 EM_REG_COUNTER_USED(&pStats->StatRZMonitor, "/EM/CPU%d/RZ/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
237 EM_REG_COUNTER_USED(&pStats->StatR3Monitor, "/EM/CPU%d/R3/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
238 EM_REG_COUNTER_USED(&pStats->StatRZMWait, "/EM/CPU%d/RZ/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
239 EM_REG_COUNTER_USED(&pStats->StatR3MWait, "/EM/CPU%d/R3/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
240 EM_REG_COUNTER_USED(&pStats->StatRZBtr, "/EM/CPU%d/RZ/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
241 EM_REG_COUNTER_USED(&pStats->StatR3Btr, "/EM/CPU%d/R3/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
242 EM_REG_COUNTER_USED(&pStats->StatRZBts, "/EM/CPU%d/RZ/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
243 EM_REG_COUNTER_USED(&pStats->StatR3Bts, "/EM/CPU%d/R3/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
244 EM_REG_COUNTER_USED(&pStats->StatRZBtc, "/EM/CPU%d/RZ/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
245 EM_REG_COUNTER_USED(&pStats->StatR3Btc, "/EM/CPU%d/R3/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
246 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
247 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg, "/EM/CPU%d/R3/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
248 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
249 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg8b, "/EM/CPU%d/R3/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
250 EM_REG_COUNTER_USED(&pStats->StatRZXAdd, "/EM/CPU%d/RZ/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
251 EM_REG_COUNTER_USED(&pStats->StatR3XAdd, "/EM/CPU%d/R3/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
252 EM_REG_COUNTER_USED(&pStats->StatR3Rdmsr, "/EM/CPU%d/R3/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
253 EM_REG_COUNTER_USED(&pStats->StatRZRdmsr, "/EM/CPU%d/RZ/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
254 EM_REG_COUNTER_USED(&pStats->StatR3Wrmsr, "/EM/CPU%d/R3/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
255 EM_REG_COUNTER_USED(&pStats->StatRZWrmsr, "/EM/CPU%d/RZ/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
256 EM_REG_COUNTER_USED(&pStats->StatR3StosWD, "/EM/CPU%d/R3/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
257 EM_REG_COUNTER_USED(&pStats->StatRZStosWD, "/EM/CPU%d/RZ/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
258 EM_REG_COUNTER_USED(&pStats->StatRZWbInvd, "/EM/CPU%d/RZ/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
259 EM_REG_COUNTER_USED(&pStats->StatR3WbInvd, "/EM/CPU%d/R3/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
260 EM_REG_COUNTER_USED(&pStats->StatRZLmsw, "/EM/CPU%d/RZ/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
261 EM_REG_COUNTER_USED(&pStats->StatR3Lmsw, "/EM/CPU%d/R3/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
262
263 EM_REG_COUNTER(&pStats->StatRZInterpretFailed, "/EM/CPU%d/RZ/Interpret/Failed", "The number of times an instruction was not interpreted.");
264 EM_REG_COUNTER(&pStats->StatR3InterpretFailed, "/EM/CPU%d/R3/Interpret/Failed", "The number of times an instruction was not interpreted.");
265
266 EM_REG_COUNTER_USED(&pStats->StatRZFailedAnd, "/EM/CPU%d/RZ/Interpret/Failed/And", "The number of times AND was not interpreted.");
267 EM_REG_COUNTER_USED(&pStats->StatR3FailedAnd, "/EM/CPU%d/R3/Interpret/Failed/And", "The number of times AND was not interpreted.");
268 EM_REG_COUNTER_USED(&pStats->StatRZFailedCpuId, "/EM/CPU%d/RZ/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
269 EM_REG_COUNTER_USED(&pStats->StatR3FailedCpuId, "/EM/CPU%d/R3/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
270 EM_REG_COUNTER_USED(&pStats->StatRZFailedDec, "/EM/CPU%d/RZ/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
271 EM_REG_COUNTER_USED(&pStats->StatR3FailedDec, "/EM/CPU%d/R3/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
272 EM_REG_COUNTER_USED(&pStats->StatRZFailedHlt, "/EM/CPU%d/RZ/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
273 EM_REG_COUNTER_USED(&pStats->StatR3FailedHlt, "/EM/CPU%d/R3/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
274 EM_REG_COUNTER_USED(&pStats->StatRZFailedInc, "/EM/CPU%d/RZ/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
275 EM_REG_COUNTER_USED(&pStats->StatR3FailedInc, "/EM/CPU%d/R3/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
276 EM_REG_COUNTER_USED(&pStats->StatRZFailedInvlPg, "/EM/CPU%d/RZ/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
277 EM_REG_COUNTER_USED(&pStats->StatR3FailedInvlPg, "/EM/CPU%d/R3/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
278 EM_REG_COUNTER_USED(&pStats->StatRZFailedIret, "/EM/CPU%d/RZ/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
279 EM_REG_COUNTER_USED(&pStats->StatR3FailedIret, "/EM/CPU%d/R3/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
280 EM_REG_COUNTER_USED(&pStats->StatRZFailedLLdt, "/EM/CPU%d/RZ/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
281 EM_REG_COUNTER_USED(&pStats->StatR3FailedLLdt, "/EM/CPU%d/R3/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
282 EM_REG_COUNTER_USED(&pStats->StatRZFailedLIdt, "/EM/CPU%d/RZ/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
283 EM_REG_COUNTER_USED(&pStats->StatR3FailedLIdt, "/EM/CPU%d/R3/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
284 EM_REG_COUNTER_USED(&pStats->StatRZFailedLGdt, "/EM/CPU%d/RZ/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
285 EM_REG_COUNTER_USED(&pStats->StatR3FailedLGdt, "/EM/CPU%d/R3/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
286 EM_REG_COUNTER_USED(&pStats->StatRZFailedMov, "/EM/CPU%d/RZ/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
287 EM_REG_COUNTER_USED(&pStats->StatR3FailedMov, "/EM/CPU%d/R3/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
288 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovCRx, "/EM/CPU%d/RZ/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
289 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovCRx, "/EM/CPU%d/R3/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
290 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovDRx, "/EM/CPU%d/RZ/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
291 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovDRx, "/EM/CPU%d/R3/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
292 EM_REG_COUNTER_USED(&pStats->StatRZFailedOr, "/EM/CPU%d/RZ/Interpret/Failed/Or", "The number of times OR was not interpreted.");
293 EM_REG_COUNTER_USED(&pStats->StatR3FailedOr, "/EM/CPU%d/R3/Interpret/Failed/Or", "The number of times OR was not interpreted.");
294 EM_REG_COUNTER_USED(&pStats->StatRZFailedPop, "/EM/CPU%d/RZ/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
295 EM_REG_COUNTER_USED(&pStats->StatR3FailedPop, "/EM/CPU%d/R3/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
296 EM_REG_COUNTER_USED(&pStats->StatRZFailedSti, "/EM/CPU%d/RZ/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
297 EM_REG_COUNTER_USED(&pStats->StatR3FailedSti, "/EM/CPU%d/R3/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
298 EM_REG_COUNTER_USED(&pStats->StatRZFailedXchg, "/EM/CPU%d/RZ/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
299 EM_REG_COUNTER_USED(&pStats->StatR3FailedXchg, "/EM/CPU%d/R3/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
300 EM_REG_COUNTER_USED(&pStats->StatRZFailedXor, "/EM/CPU%d/RZ/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
301 EM_REG_COUNTER_USED(&pStats->StatR3FailedXor, "/EM/CPU%d/R3/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
302 EM_REG_COUNTER_USED(&pStats->StatRZFailedMonitor, "/EM/CPU%d/RZ/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
303 EM_REG_COUNTER_USED(&pStats->StatR3FailedMonitor, "/EM/CPU%d/R3/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
304 EM_REG_COUNTER_USED(&pStats->StatRZFailedMWait, "/EM/CPU%d/RZ/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
305 EM_REG_COUNTER_USED(&pStats->StatR3FailedMWait, "/EM/CPU%d/R3/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
306 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdtsc, "/EM/CPU%d/RZ/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
307 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdtsc, "/EM/CPU%d/R3/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
308 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdpmc, "/EM/CPU%d/RZ/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
309 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdpmc, "/EM/CPU%d/R3/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
310 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdmsr, "/EM/CPU%d/RZ/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
311 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdmsr, "/EM/CPU%d/R3/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
312 EM_REG_COUNTER_USED(&pStats->StatRZFailedWrmsr, "/EM/CPU%d/RZ/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
313 EM_REG_COUNTER_USED(&pStats->StatR3FailedWrmsr, "/EM/CPU%d/R3/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
314 EM_REG_COUNTER_USED(&pStats->StatRZFailedLmsw, "/EM/CPU%d/RZ/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
315 EM_REG_COUNTER_USED(&pStats->StatR3FailedLmsw, "/EM/CPU%d/R3/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
316
317 EM_REG_COUNTER_USED(&pStats->StatRZFailedMisc, "/EM/CPU%d/RZ/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
318 EM_REG_COUNTER_USED(&pStats->StatR3FailedMisc, "/EM/CPU%d/R3/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
319 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdd, "/EM/CPU%d/RZ/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
320 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdd, "/EM/CPU%d/R3/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
321 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdc, "/EM/CPU%d/RZ/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
322 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdc, "/EM/CPU%d/R3/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
323 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtr, "/EM/CPU%d/RZ/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
324 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtr, "/EM/CPU%d/R3/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
325 EM_REG_COUNTER_USED(&pStats->StatRZFailedBts, "/EM/CPU%d/RZ/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
326 EM_REG_COUNTER_USED(&pStats->StatR3FailedBts, "/EM/CPU%d/R3/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
327 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtc, "/EM/CPU%d/RZ/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
328 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtc, "/EM/CPU%d/R3/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
329 EM_REG_COUNTER_USED(&pStats->StatRZFailedCli, "/EM/CPU%d/RZ/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
330 EM_REG_COUNTER_USED(&pStats->StatR3FailedCli, "/EM/CPU%d/R3/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
331 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
332 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
333 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
334 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg8b, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
335 EM_REG_COUNTER_USED(&pStats->StatRZFailedXAdd, "/EM/CPU%d/RZ/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
336 EM_REG_COUNTER_USED(&pStats->StatR3FailedXAdd, "/EM/CPU%d/R3/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
337 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovNTPS, "/EM/CPU%d/RZ/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
338 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovNTPS, "/EM/CPU%d/R3/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
339 EM_REG_COUNTER_USED(&pStats->StatRZFailedStosWD, "/EM/CPU%d/RZ/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
340 EM_REG_COUNTER_USED(&pStats->StatR3FailedStosWD, "/EM/CPU%d/R3/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
341 EM_REG_COUNTER_USED(&pStats->StatRZFailedSub, "/EM/CPU%d/RZ/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
342 EM_REG_COUNTER_USED(&pStats->StatR3FailedSub, "/EM/CPU%d/R3/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
343 EM_REG_COUNTER_USED(&pStats->StatRZFailedWbInvd, "/EM/CPU%d/RZ/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
344 EM_REG_COUNTER_USED(&pStats->StatR3FailedWbInvd, "/EM/CPU%d/R3/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
345
346 EM_REG_COUNTER_USED(&pStats->StatRZFailedUserMode, "/EM/CPU%d/RZ/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
347 EM_REG_COUNTER_USED(&pStats->StatR3FailedUserMode, "/EM/CPU%d/R3/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
348 EM_REG_COUNTER_USED(&pStats->StatRZFailedPrefix, "/EM/CPU%d/RZ/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
349 EM_REG_COUNTER_USED(&pStats->StatR3FailedPrefix, "/EM/CPU%d/R3/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
350
351 EM_REG_COUNTER_USED(&pStats->StatCli, "/EM/CPU%d/R3/PrivInst/Cli", "Number of cli instructions.");
352 EM_REG_COUNTER_USED(&pStats->StatSti, "/EM/CPU%d/R3/PrivInst/Sti", "Number of sli instructions.");
353 EM_REG_COUNTER_USED(&pStats->StatIn, "/EM/CPU%d/R3/PrivInst/In", "Number of in instructions.");
354 EM_REG_COUNTER_USED(&pStats->StatOut, "/EM/CPU%d/R3/PrivInst/Out", "Number of out instructions.");
355 EM_REG_COUNTER_USED(&pStats->StatIoRestarted, "/EM/CPU%d/R3/PrivInst/IoRestarted", "Number of restarted i/o instructions.");
356 EM_REG_COUNTER_USED(&pStats->StatHlt, "/EM/CPU%d/R3/PrivInst/Hlt", "Number of hlt instructions not handled in GC because of PATM.");
357 EM_REG_COUNTER_USED(&pStats->StatInvlpg, "/EM/CPU%d/R3/PrivInst/Invlpg", "Number of invlpg instructions.");
358 EM_REG_COUNTER_USED(&pStats->StatMisc, "/EM/CPU%d/R3/PrivInst/Misc", "Number of misc. instructions.");
359 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[0], "/EM/CPU%d/R3/PrivInst/Mov CR0, X", "Number of mov CR0 read instructions.");
360 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[1], "/EM/CPU%d/R3/PrivInst/Mov CR1, X", "Number of mov CR1 read instructions.");
361 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[2], "/EM/CPU%d/R3/PrivInst/Mov CR2, X", "Number of mov CR2 read instructions.");
362 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[3], "/EM/CPU%d/R3/PrivInst/Mov CR3, X", "Number of mov CR3 read instructions.");
363 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[4], "/EM/CPU%d/R3/PrivInst/Mov CR4, X", "Number of mov CR4 read instructions.");
364 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[0], "/EM/CPU%d/R3/PrivInst/Mov X, CR0", "Number of mov CR0 write instructions.");
365 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[1], "/EM/CPU%d/R3/PrivInst/Mov X, CR1", "Number of mov CR1 write instructions.");
366 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[2], "/EM/CPU%d/R3/PrivInst/Mov X, CR2", "Number of mov CR2 write instructions.");
367 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[3], "/EM/CPU%d/R3/PrivInst/Mov X, CR3", "Number of mov CR3 write instructions.");
368 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[4], "/EM/CPU%d/R3/PrivInst/Mov X, CR4", "Number of mov CR4 write instructions.");
369 EM_REG_COUNTER_USED(&pStats->StatMovDRx, "/EM/CPU%d/R3/PrivInst/MovDRx", "Number of mov DRx instructions.");
370 EM_REG_COUNTER_USED(&pStats->StatIret, "/EM/CPU%d/R3/PrivInst/Iret", "Number of iret instructions.");
371 EM_REG_COUNTER_USED(&pStats->StatMovLgdt, "/EM/CPU%d/R3/PrivInst/Lgdt", "Number of lgdt instructions.");
372 EM_REG_COUNTER_USED(&pStats->StatMovLidt, "/EM/CPU%d/R3/PrivInst/Lidt", "Number of lidt instructions.");
373 EM_REG_COUNTER_USED(&pStats->StatMovLldt, "/EM/CPU%d/R3/PrivInst/Lldt", "Number of lldt instructions.");
374 EM_REG_COUNTER_USED(&pStats->StatSysEnter, "/EM/CPU%d/R3/PrivInst/Sysenter", "Number of sysenter instructions.");
375 EM_REG_COUNTER_USED(&pStats->StatSysExit, "/EM/CPU%d/R3/PrivInst/Sysexit", "Number of sysexit instructions.");
376 EM_REG_COUNTER_USED(&pStats->StatSysCall, "/EM/CPU%d/R3/PrivInst/Syscall", "Number of syscall instructions.");
377 EM_REG_COUNTER_USED(&pStats->StatSysRet, "/EM/CPU%d/R3/PrivInst/Sysret", "Number of sysret instructions.");
378
379 EM_REG_COUNTER(&pVCpu->em.s.StatTotalClis, "/EM/CPU%d/Cli/Total", "Total number of cli instructions executed.");
380 pVCpu->em.s.pCliStatTree = 0;
381
382 /* these should be considered for release statistics. */
383 EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%d/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction.");
384 EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%d/EM/Emulation/Priv", "Profiling of emR3RawPrivileged.");
385 EM_REG_PROFILE(&pVCpu->em.s.StatHwAccEntry, "/PROF/CPU%d/EM/HwAccEnter", "Profiling Hardware Accelerated Mode entry overhead.");
386 EM_REG_PROFILE(&pVCpu->em.s.StatHwAccExec, "/PROF/CPU%d/EM/HwAccExec", "Profiling Hardware Accelerated Mode execution.");
387 EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%d/EM/REMEmuSingle", "Profiling single instruction REM execution.");
388 EM_REG_PROFILE(&pVCpu->em.s.StatREMExec, "/PROF/CPU%d/EM/REMExec", "Profiling REM execution.");
389 EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%d/EM/REMSync", "Profiling REM context syncing.");
390 EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%d/EM/RAWEnter", "Profiling Raw Mode entry overhead.");
391 EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%d/EM/RAWExec", "Profiling Raw Mode execution.");
392 EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%d/EM/RAWTail", "Profiling Raw Mode tail overhead.");
393
394#endif /* VBOX_WITH_STATISTICS */
395
396 EM_REG_COUNTER(&pVCpu->em.s.StatForcedActions, "/PROF/CPU%d/EM/ForcedActions", "Profiling forced action execution.");
397 EM_REG_COUNTER(&pVCpu->em.s.StatHalted, "/PROF/CPU%d/EM/Halted", "Profiling halted state (VMR3WaitHalted).");
398 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatCapped, "/PROF/CPU%d/EM/Capped", "Profiling capped state (sleep).");
399 EM_REG_COUNTER(&pVCpu->em.s.StatREMTotal, "/PROF/CPU%d/EM/REMTotal", "Profiling emR3RemExecute (excluding FFs).");
400 EM_REG_COUNTER(&pVCpu->em.s.StatRAWTotal, "/PROF/CPU%d/EM/RAWTotal", "Profiling emR3RawExecute (excluding FFs).");
401
402 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatTotal, "/PROF/CPU%d/EM/Total", "Profiling EMR3ExecuteVM.");
403 }
404
405 return VINF_SUCCESS;
406}
407
408
409/**
410 * Applies relocations to data and code managed by this
411 * component. This function will be called at init and
412 * whenever the VMM need to relocate it self inside the GC.
413 *
414 * @param pVM The VM.
415 */
416VMMR3DECL(void) EMR3Relocate(PVM pVM)
417{
418 LogFlow(("EMR3Relocate\n"));
419 for (VMCPUID i = 0; i < pVM->cCpus; i++)
420 {
421 PVMCPU pVCpu = &pVM->aCpus[i];
422 if (pVCpu->em.s.pStatsR3)
423 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVCpu->em.s.pStatsR3);
424 }
425}
426
427
428/**
429 * Reset the EM state for a CPU.
430 *
431 * Called by EMR3Reset and hot plugging.
432 *
433 * @param pVCpu The virtual CPU.
434 */
435VMMR3DECL(void) EMR3ResetCpu(PVMCPU pVCpu)
436{
437 pVCpu->em.s.fForceRAW = false;
438
439 /* VMR3Reset may return VINF_EM_RESET or VINF_EM_SUSPEND, so transition
440 out of the HALTED state here so that enmPrevState doesn't end up as
441 HALTED when EMR3Execute returns. */
442 if (pVCpu->em.s.enmState == EMSTATE_HALTED)
443 {
444 Log(("EMR3ResetCpu: Cpu#%u %s -> %s\n", pVCpu->idCpu, emR3GetStateName(pVCpu->em.s.enmState), pVCpu->idCpu == 0 ? "EMSTATE_NONE" : "EMSTATE_WAIT_SIPI"));
445 pVCpu->em.s.enmState = pVCpu->idCpu == 0 ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
446 }
447}
448
449
450/**
451 * Reset notification.
452 *
453 * @param pVM The VM handle.
454 */
455VMMR3DECL(void) EMR3Reset(PVM pVM)
456{
457 Log(("EMR3Reset: \n"));
458 for (VMCPUID i = 0; i < pVM->cCpus; i++)
459 EMR3ResetCpu(&pVM->aCpus[i]);
460}
461
462
463/**
464 * Terminates the EM.
465 *
466 * Termination means cleaning up and freeing all resources,
467 * the VM it self is at this point powered off or suspended.
468 *
469 * @returns VBox status code.
470 * @param pVM The VM to operate on.
471 */
472VMMR3DECL(int) EMR3Term(PVM pVM)
473{
474 AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
475
476 PDMR3CritSectDelete(&pVM->em.s.CritSectREM);
477 return VINF_SUCCESS;
478}
479
480
481/**
482 * Execute state save operation.
483 *
484 * @returns VBox status code.
485 * @param pVM VM Handle.
486 * @param pSSM SSM operation handle.
487 */
488static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
489{
490 for (VMCPUID i = 0; i < pVM->cCpus; i++)
491 {
492 PVMCPU pVCpu = &pVM->aCpus[i];
493
494 int rc = SSMR3PutBool(pSSM, pVCpu->em.s.fForceRAW);
495 AssertRCReturn(rc, rc);
496
497 Assert(pVCpu->em.s.enmState == EMSTATE_SUSPENDED);
498 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
499 rc = SSMR3PutU32(pSSM, pVCpu->em.s.enmPrevState);
500 AssertRCReturn(rc, rc);
501
502 /* Save mwait state. */
503 rc = SSMR3PutU32(pSSM, pVCpu->em.s.mwait.fWait);
504 AssertRCReturn(rc, rc);
505 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.mwait.uMWaitEAX);
506 AssertRCReturn(rc, rc);
507 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.mwait.uMWaitECX);
508 AssertRCReturn(rc, rc);
509 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.mwait.uMonitorEAX);
510 AssertRCReturn(rc, rc);
511 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.mwait.uMonitorECX);
512 AssertRCReturn(rc, rc);
513 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.mwait.uMonitorEDX);
514 AssertRCReturn(rc, rc);
515 }
516 return VINF_SUCCESS;
517}
518
519
520/**
521 * Execute state load operation.
522 *
523 * @returns VBox status code.
524 * @param pVM VM Handle.
525 * @param pSSM SSM operation handle.
526 * @param uVersion Data layout version.
527 * @param uPass The data pass.
528 */
529static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
530{
531 /*
532 * Validate version.
533 */
534 if ( uVersion != EM_SAVED_STATE_VERSION
535 && uVersion != EM_SAVED_STATE_VERSION_PRE_MWAIT
536 && uVersion != EM_SAVED_STATE_VERSION_PRE_SMP)
537 {
538 AssertMsgFailed(("emR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, EM_SAVED_STATE_VERSION));
539 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
540 }
541 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
542
543 /*
544 * Load the saved state.
545 */
546 for (VMCPUID i = 0; i < pVM->cCpus; i++)
547 {
548 PVMCPU pVCpu = &pVM->aCpus[i];
549
550 int rc = SSMR3GetBool(pSSM, &pVCpu->em.s.fForceRAW);
551 if (RT_FAILURE(rc))
552 pVCpu->em.s.fForceRAW = false;
553 AssertRCReturn(rc, rc);
554
555 if (uVersion > EM_SAVED_STATE_VERSION_PRE_SMP)
556 {
557 AssertCompile(sizeof(pVCpu->em.s.enmPrevState) == sizeof(uint32_t));
558 rc = SSMR3GetU32(pSSM, (uint32_t *)&pVCpu->em.s.enmPrevState);
559 AssertRCReturn(rc, rc);
560 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
561
562 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
563 }
564 if (uVersion > EM_SAVED_STATE_VERSION_PRE_MWAIT)
565 {
566 /* Load mwait state. */
567 rc = SSMR3GetU32(pSSM, &pVCpu->em.s.mwait.fWait);
568 AssertRCReturn(rc, rc);
569 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.mwait.uMWaitEAX);
570 AssertRCReturn(rc, rc);
571 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.mwait.uMWaitECX);
572 AssertRCReturn(rc, rc);
573 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.mwait.uMonitorEAX);
574 AssertRCReturn(rc, rc);
575 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.mwait.uMonitorECX);
576 AssertRCReturn(rc, rc);
577 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.mwait.uMonitorEDX);
578 AssertRCReturn(rc, rc);
579 }
580
581 Assert(!pVCpu->em.s.pCliStatTree);
582 }
583 return VINF_SUCCESS;
584}
585
586
587/**
588 * Raise a fatal error.
589 *
590 * Safely terminate the VM with full state report and stuff. This function
591 * will naturally never return.
592 *
593 * @param pVCpu VMCPU handle.
594 * @param rc VBox status code.
595 */
596VMMR3DECL(void) EMR3FatalError(PVMCPU pVCpu, int rc)
597{
598 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
599 longjmp(pVCpu->em.s.u.FatalLongJump, rc);
600 AssertReleaseMsgFailed(("longjmp returned!\n"));
601}
602
603
604/**
605 * Gets the EM state name.
606 *
607 * @returns pointer to read only state name,
608 * @param enmState The state.
609 */
610static const char *emR3GetStateName(EMSTATE enmState)
611{
612 switch (enmState)
613 {
614 case EMSTATE_NONE: return "EMSTATE_NONE";
615 case EMSTATE_RAW: return "EMSTATE_RAW";
616 case EMSTATE_HWACC: return "EMSTATE_HWACC";
617 case EMSTATE_REM: return "EMSTATE_REM";
618 case EMSTATE_PARAV: return "EMSTATE_PARAV";
619 case EMSTATE_HALTED: return "EMSTATE_HALTED";
620 case EMSTATE_WAIT_SIPI: return "EMSTATE_WAIT_SIPI";
621 case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
622 case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
623 case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
624 case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
625 case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
626 case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
627 default: return "Unknown!";
628 }
629}
630
631
632/**
633 * Debug loop.
634 *
635 * @returns VBox status code for EM.
636 * @param pVM VM handle.
637 * @param pVCpu VMCPU handle.
638 * @param rc Current EM VBox status code..
639 */
640static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc)
641{
642 for (;;)
643 {
644 Log(("emR3Debug: rc=%Rrc\n", rc));
645 const int rcLast = rc;
646
647 /*
648 * Debug related RC.
649 */
650 switch (rc)
651 {
652 /*
653 * Single step an instruction.
654 */
655 case VINF_EM_DBG_STEP:
656 if ( pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
657 || pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
658 || pVCpu->em.s.fForceRAW /* paranoia */)
659 rc = emR3RawStep(pVM, pVCpu);
660 else
661 {
662 Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
663 rc = emR3RemStep(pVM, pVCpu);
664 }
665 break;
666
667 /*
668 * Simple events: stepped, breakpoint, stop/assertion.
669 */
670 case VINF_EM_DBG_STEPPED:
671 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
672 break;
673
674 case VINF_EM_DBG_BREAKPOINT:
675 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
676 break;
677
678 case VINF_EM_DBG_STOP:
679 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
680 break;
681
682 case VINF_EM_DBG_HYPER_STEPPED:
683 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
684 break;
685
686 case VINF_EM_DBG_HYPER_BREAKPOINT:
687 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
688 break;
689
690 case VINF_EM_DBG_HYPER_ASSERTION:
691 RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
692 rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
693 break;
694
695 /*
696 * Guru meditation.
697 */
698 case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
699 rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
700 break;
701 case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
702 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
703 break;
704
705 default: /** @todo don't use default for guru, but make special errors code! */
706 rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
707 break;
708 }
709
710 /*
711 * Process the result.
712 */
713 do
714 {
715 switch (rc)
716 {
717 /*
718 * Continue the debugging loop.
719 */
720 case VINF_EM_DBG_STEP:
721 case VINF_EM_DBG_STOP:
722 case VINF_EM_DBG_STEPPED:
723 case VINF_EM_DBG_BREAKPOINT:
724 case VINF_EM_DBG_HYPER_STEPPED:
725 case VINF_EM_DBG_HYPER_BREAKPOINT:
726 case VINF_EM_DBG_HYPER_ASSERTION:
727 break;
728
729 /*
730 * Resuming execution (in some form) has to be done here if we got
731 * a hypervisor debug event.
732 */
733 case VINF_SUCCESS:
734 case VINF_EM_RESUME:
735 case VINF_EM_SUSPEND:
736 case VINF_EM_RESCHEDULE:
737 case VINF_EM_RESCHEDULE_RAW:
738 case VINF_EM_RESCHEDULE_REM:
739 case VINF_EM_HALT:
740 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
741 {
742 rc = emR3RawResumeHyper(pVM, pVCpu);
743 if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
744 continue;
745 }
746 if (rc == VINF_SUCCESS)
747 rc = VINF_EM_RESCHEDULE;
748 return rc;
749
750 /*
751 * The debugger isn't attached.
752 * We'll simply turn the thing off since that's the easiest thing to do.
753 */
754 case VERR_DBGF_NOT_ATTACHED:
755 switch (rcLast)
756 {
757 case VINF_EM_DBG_HYPER_STEPPED:
758 case VINF_EM_DBG_HYPER_BREAKPOINT:
759 case VINF_EM_DBG_HYPER_ASSERTION:
760 case VERR_TRPM_PANIC:
761 case VERR_TRPM_DONT_PANIC:
762 case VERR_VMM_RING0_ASSERTION:
763 case VERR_VMM_HYPER_CR3_MISMATCH:
764 case VERR_VMM_RING3_CALL_DISABLED:
765 return rcLast;
766 }
767 return VINF_EM_OFF;
768
769 /*
770 * Status codes terminating the VM in one or another sense.
771 */
772 case VINF_EM_TERMINATE:
773 case VINF_EM_OFF:
774 case VINF_EM_RESET:
775 case VINF_EM_NO_MEMORY:
776 case VINF_EM_RAW_STALE_SELECTOR:
777 case VINF_EM_RAW_IRET_TRAP:
778 case VERR_TRPM_PANIC:
779 case VERR_TRPM_DONT_PANIC:
780 case VERR_VMM_RING0_ASSERTION:
781 case VERR_VMM_HYPER_CR3_MISMATCH:
782 case VERR_VMM_RING3_CALL_DISABLED:
783 case VERR_INTERNAL_ERROR:
784 case VERR_INTERNAL_ERROR_2:
785 case VERR_INTERNAL_ERROR_3:
786 case VERR_INTERNAL_ERROR_4:
787 case VERR_INTERNAL_ERROR_5:
788 case VERR_IPE_UNEXPECTED_STATUS:
789 case VERR_IPE_UNEXPECTED_INFO_STATUS:
790 case VERR_IPE_UNEXPECTED_ERROR_STATUS:
791 return rc;
792
793 /*
794 * The rest is unexpected, and will keep us here.
795 */
796 default:
797 AssertMsgFailed(("Unexpected rc %Rrc!\n", rc));
798 break;
799 }
800 } while (false);
801 } /* debug for ever */
802}
803
804/**
805 * Steps recompiled code.
806 *
807 * @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
808 * VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
809 *
810 * @param pVM VM handle.
811 * @param pVCpu VMCPU handle.
812 */
813static int emR3RemStep(PVM pVM, PVMCPU pVCpu)
814{
815 LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
816
817 EMRemLock(pVM);
818
819 /*
820 * Switch to REM, step instruction, switch back.
821 */
822 int rc = REMR3State(pVM, pVCpu);
823 if (RT_SUCCESS(rc))
824 {
825 rc = REMR3Step(pVM, pVCpu);
826 REMR3StateBack(pVM, pVCpu);
827 }
828 EMRemUnlock(pVM);
829
830 LogFlow(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
831 return rc;
832}
833
834
835/**
836 * emR3RemExecute helper that syncs the state back from REM and leave the REM
837 * critical section.
838 *
839 * @returns false - new fInREMState value.
840 * @param pVM The VM handle.
841 * @param pVCpu The virtual CPU handle.
842 */
843DECLINLINE(bool) emR3RemExecuteSyncBack(PVM pVM, PVMCPU pVCpu)
844{
845 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, a);
846 REMR3StateBack(pVM, pVCpu);
847 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, a);
848
849 EMRemUnlock(pVM);
850 return false;
851}
852
853
854/**
855 * Executes recompiled code.
856 *
857 * This function contains the recompiler version of the inner
858 * execution loop (the outer loop being in EMR3ExecuteVM()).
859 *
860 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
861 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
862 *
863 * @param pVM VM handle.
864 * @param pVCpu VMCPU handle.
865 * @param pfFFDone Where to store an indicator telling whether or not
866 * FFs were done before returning.
867 *
868 */
869static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
870{
871#ifdef LOG_ENABLED
872 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
873 uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
874
875 if (pCtx->eflags.Bits.u1VM)
876 Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
877 else
878 Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x eflags=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, pCtx->eflags.u));
879#endif
880 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatREMTotal, a);
881
882#if defined(VBOX_STRICT) && defined(DEBUG_bird)
883 AssertMsg( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
884 || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVCpu)), /** @todo #1419 - get flat address. */
885 ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
886#endif
887
888 /*
889 * Spin till we get a forced action which returns anything but VINF_SUCCESS
890 * or the REM suggests raw-mode execution.
891 */
892 *pfFFDone = false;
893 bool fInREMState = false;
894 int rc = VINF_SUCCESS;
895 for (;;)
896 {
897 /*
898 * Lock REM and update the state if not already in sync.
899 *
900 * Note! Big lock, but you are not supposed to own any lock when
901 * coming in here.
902 */
903 if (!fInREMState)
904 {
905 EMRemLock(pVM);
906 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, b);
907
908 /* Flush the recompiler translation blocks if the VCPU has changed,
909 also force a full CPU state resync. */
910 if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
911 {
912 REMFlushTBs(pVM);
913 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
914 }
915 pVM->em.s.idLastRemCpu = pVCpu->idCpu;
916
917 rc = REMR3State(pVM, pVCpu);
918
919 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, b);
920 if (RT_FAILURE(rc))
921 break;
922 fInREMState = true;
923
924 /*
925 * We might have missed the raising of VMREQ, TIMER and some other
926 * important FFs while we were busy switching the state. So, check again.
927 */
928 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_CHECK_VM_STATE | VM_FF_RESET)
929 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER | VMCPU_FF_REQUEST))
930 {
931 LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fGlobalForcedActions));
932 goto l_REMDoForcedActions;
933 }
934 }
935
936
937 /*
938 * Execute REM.
939 */
940 if (RT_LIKELY(EMR3IsExecutionAllowed(pVM, pVCpu)))
941 {
942 STAM_PROFILE_START(&pVCpu->em.s.StatREMExec, c);
943 rc = REMR3Run(pVM, pVCpu);
944 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMExec, c);
945 }
946 else
947 {
948 /* Give up this time slice; virtual time continues */
949 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
950 RTThreadSleep(5);
951 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
952 rc = VINF_SUCCESS;
953 }
954
955 /*
956 * Deal with high priority post execution FFs before doing anything
957 * else. Sync back the state and leave the lock to be on the safe side.
958 */
959 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
960 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
961 {
962 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
963 rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
964 }
965
966 /*
967 * Process the returned status code.
968 */
969 if (rc != VINF_SUCCESS)
970 {
971 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
972 break;
973 if (rc != VINF_REM_INTERRUPED_FF)
974 {
975 /*
976 * Anything which is not known to us means an internal error
977 * and the termination of the VM!
978 */
979 AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
980 break;
981 }
982 }
983
984
985 /*
986 * Check and execute forced actions.
987 *
988 * Sync back the VM state and leave the lock before calling any of
989 * these, you never know what's going to happen here.
990 */
991#ifdef VBOX_HIGH_RES_TIMERS_HACK
992 TMTimerPollVoid(pVM, pVCpu);
993#endif
994 AssertCompile((VMCPU_FF_ALL_REM_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE)) & VMCPU_FF_TIMER);
995 if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_REM_MASK)
996 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_REM_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE)))
997 {
998l_REMDoForcedActions:
999 if (fInREMState)
1000 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1001 STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatREMTotal, a);
1002 rc = emR3ForcedActions(pVM, pVCpu, rc);
1003 STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatREMTotal, a);
1004 if ( rc != VINF_SUCCESS
1005 && rc != VINF_EM_RESCHEDULE_REM)
1006 {
1007 *pfFFDone = true;
1008 break;
1009 }
1010 }
1011
1012 } /* The Inner Loop, recompiled execution mode version. */
1013
1014
1015 /*
1016 * Returning. Sync back the VM state if required.
1017 */
1018 if (fInREMState)
1019 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1020
1021 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatREMTotal, a);
1022 return rc;
1023}
1024
1025
1026#ifdef DEBUG
1027
1028int emR3SingleStepExecRem(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1029{
1030 EMSTATE enmOldState = pVCpu->em.s.enmState;
1031
1032 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1033
1034 Log(("Single step BEGIN:\n"));
1035 for (uint32_t i = 0; i < cIterations; i++)
1036 {
1037 DBGFR3PrgStep(pVCpu);
1038 DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
1039 emR3RemStep(pVM, pVCpu);
1040 if (emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx) != EMSTATE_REM)
1041 break;
1042 }
1043 Log(("Single step END:\n"));
1044 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1045 pVCpu->em.s.enmState = enmOldState;
1046 return VINF_EM_RESCHEDULE;
1047}
1048
1049#endif /* DEBUG */
1050
1051
1052/**
1053 * Decides whether to execute RAW, HWACC or REM.
1054 *
1055 * @returns new EM state
1056 * @param pVM The VM.
1057 * @param pVCpu The VMCPU handle.
1058 * @param pCtx The CPU context.
1059 */
1060EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1061{
1062#ifdef IEM_VERIFICATION_MODE
1063 return EMSTATE_REM;
1064#else
1065
1066 /*
1067 * When forcing raw-mode execution, things are simple.
1068 */
1069 if (pVCpu->em.s.fForceRAW)
1070 return EMSTATE_RAW;
1071
1072 /*
1073 * We stay in the wait for SIPI state unless explicitly told otherwise.
1074 */
1075 if (pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI)
1076 return EMSTATE_WAIT_SIPI;
1077
1078 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1079 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1080 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1081
1082 X86EFLAGS EFlags = pCtx->eflags;
1083 if (HWACCMIsEnabled(pVM))
1084 {
1085 /* Hardware accelerated raw-mode:
1086 *
1087 * Typically only 32-bits protected mode, with paging enabled, code is allowed here.
1088 */
1089 if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
1090 return EMSTATE_HWACC;
1091
1092 /* Note: Raw mode and hw accelerated mode are incompatible. The latter turns
1093 * off monitoring features essential for raw mode! */
1094 return EMSTATE_REM;
1095 }
1096
1097 /*
1098 * Standard raw-mode:
1099 *
1100 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1101 * or 32 bits protected mode ring 0 code
1102 *
1103 * The tests are ordered by the likelihood of being true during normal execution.
1104 */
1105 if (EFlags.u32 & (X86_EFL_TF /* | HF_INHIBIT_IRQ_MASK*/))
1106 {
1107 Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
1108 return EMSTATE_REM;
1109 }
1110
1111# ifndef VBOX_RAW_V86
1112 if (EFlags.u32 & X86_EFL_VM) {
1113 Log2(("raw mode refused: VM_MASK\n"));
1114 return EMSTATE_REM;
1115 }
1116# endif
1117
1118 /** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
1119 uint32_t u32CR0 = pCtx->cr0;
1120 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
1121 {
1122 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1123 return EMSTATE_REM;
1124 }
1125
1126 if (pCtx->cr4 & X86_CR4_PAE)
1127 {
1128 uint32_t u32Dummy, u32Features;
1129
1130 CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1131 if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
1132 return EMSTATE_REM;
1133 }
1134
1135 unsigned uSS = pCtx->ss;
1136 if ( pCtx->eflags.Bits.u1VM
1137 || (uSS & X86_SEL_RPL) == 3)
1138 {
1139 if (!EMIsRawRing3Enabled(pVM))
1140 return EMSTATE_REM;
1141
1142 if (!(EFlags.u32 & X86_EFL_IF))
1143 {
1144 Log2(("raw mode refused: IF (RawR3)\n"));
1145 return EMSTATE_REM;
1146 }
1147
1148 if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
1149 {
1150 Log2(("raw mode refused: CR0.WP + RawR0\n"));
1151 return EMSTATE_REM;
1152 }
1153 }
1154 else
1155 {
1156 if (!EMIsRawRing0Enabled(pVM))
1157 return EMSTATE_REM;
1158
1159 /* Only ring 0 supervisor code. */
1160 if ((uSS & X86_SEL_RPL) != 0)
1161 {
1162 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
1163 return EMSTATE_REM;
1164 }
1165
1166 // Let's start with pure 32 bits ring 0 code first
1167 /** @todo What's pure 32-bit mode? flat? */
1168 if ( !(pCtx->ssHid.Attr.n.u1DefBig)
1169 || !(pCtx->csHid.Attr.n.u1DefBig))
1170 {
1171 Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
1172 return EMSTATE_REM;
1173 }
1174
1175 /* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
1176 if (!(u32CR0 & X86_CR0_WP))
1177 {
1178 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1179 return EMSTATE_REM;
1180 }
1181
1182 if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
1183 {
1184 Log2(("raw r0 mode forced: patch code\n"));
1185 return EMSTATE_RAW;
1186 }
1187
1188# if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1189 if (!(EFlags.u32 & X86_EFL_IF))
1190 {
1191 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
1192 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1193 return EMSTATE_REM;
1194 }
1195# endif
1196
1197 /** @todo still necessary??? */
1198 if (EFlags.Bits.u2IOPL != 0)
1199 {
1200 Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
1201 return EMSTATE_REM;
1202 }
1203 }
1204
1205 Assert(PGMPhysIsA20Enabled(pVCpu));
1206 return EMSTATE_RAW;
1207#endif /* !IEM_VERIFICATION_MODE */
1208
1209}
1210
1211
1212/**
1213 * Executes all high priority post execution force actions.
1214 *
1215 * @returns rc or a fatal status code.
1216 *
1217 * @param pVM VM handle.
1218 * @param pVCpu VMCPU handle.
1219 * @param rc The current rc.
1220 */
1221int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1222{
1223 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PDM_CRITSECT))
1224 PDMCritSectFF(pVCpu);
1225
1226 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION))
1227 CSAMR3DoPendingAction(pVM, pVCpu);
1228
1229 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1230 {
1231 if ( rc > VINF_EM_NO_MEMORY
1232 && rc <= VINF_EM_LAST)
1233 rc = VINF_EM_NO_MEMORY;
1234 }
1235
1236 return rc;
1237}
1238
1239
1240/**
1241 * Executes all pending forced actions.
1242 *
1243 * Forced actions can cause execution delays and execution
1244 * rescheduling. The first we deal with using action priority, so
1245 * that for instance pending timers aren't scheduled and ran until
1246 * right before execution. The rescheduling we deal with using
1247 * return codes. The same goes for VM termination, only in that case
1248 * we exit everything.
1249 *
1250 * @returns VBox status code of equal or greater importance/severity than rc.
1251 * The most important ones are: VINF_EM_RESCHEDULE,
1252 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1253 *
1254 * @param pVM VM handle.
1255 * @param pVCpu VMCPU handle.
1256 * @param rc The current rc.
1257 *
1258 */
1259int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1260{
1261 STAM_REL_PROFILE_START(&pVCpu->em.s.StatForcedActions, a);
1262#ifdef VBOX_STRICT
1263 int rcIrq = VINF_SUCCESS;
1264#endif
1265 int rc2;
1266#define UPDATE_RC() \
1267 do { \
1268 AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
1269 if (rc2 == VINF_SUCCESS || rc < VINF_SUCCESS) \
1270 break; \
1271 if (!rc || rc2 < rc) \
1272 rc = rc2; \
1273 } while (0)
1274
1275 /*
1276 * Post execution chunk first.
1277 */
1278 if ( VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK)
1279 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_POST_MASK))
1280 {
1281 /*
1282 * EMT Rendezvous (must be serviced before termination).
1283 */
1284 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1285 {
1286 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1287 UPDATE_RC();
1288 /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
1289 * stopped/reset before the next VM state change is made. We need a better
1290 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1291 * && rc >= VINF_EM_SUSPEND). */
1292 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1293 {
1294 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1295 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1296 return rc;
1297 }
1298 }
1299
1300 /*
1301 * State change request (cleared by vmR3SetStateLocked).
1302 */
1303 if (VM_FF_ISPENDING(pVM, VM_FF_CHECK_VM_STATE))
1304 {
1305 VMSTATE enmState = VMR3GetState(pVM);
1306 switch (enmState)
1307 {
1308 case VMSTATE_FATAL_ERROR:
1309 case VMSTATE_FATAL_ERROR_LS:
1310 Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
1311 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1312 return VINF_EM_SUSPEND;
1313
1314 case VMSTATE_DESTROYING:
1315 Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
1316 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1317 return VINF_EM_TERMINATE;
1318
1319 default:
1320 AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
1321 }
1322 }
1323
1324 /*
1325 * Debugger Facility polling.
1326 */
1327 if (VM_FF_ISPENDING(pVM, VM_FF_DBGF))
1328 {
1329 rc2 = DBGFR3VMMForcedAction(pVM);
1330 UPDATE_RC();
1331 }
1332
1333 /*
1334 * Postponed reset request.
1335 */
1336 if (VM_FF_TESTANDCLEAR(pVM, VM_FF_RESET))
1337 {
1338 rc2 = VMR3Reset(pVM);
1339 UPDATE_RC();
1340 }
1341
1342 /*
1343 * CSAM page scanning.
1344 */
1345 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1346 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE))
1347 {
1348 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1349
1350 /** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
1351 Log(("Forced action VMCPU_FF_CSAM_SCAN_PAGE\n"));
1352
1353 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1354 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE);
1355 }
1356
1357 /*
1358 * Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
1359 */
1360 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1361 {
1362 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1363 UPDATE_RC();
1364 if (rc == VINF_EM_NO_MEMORY)
1365 return rc;
1366 }
1367
1368 /* check that we got them all */
1369 AssertCompile(VM_FF_NORMAL_PRIORITY_POST_MASK == (VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1370 AssertCompile(VMCPU_FF_NORMAL_PRIORITY_POST_MASK == VMCPU_FF_CSAM_SCAN_PAGE);
1371 }
1372
1373 /*
1374 * Normal priority then.
1375 * (Executed in no particular order.)
1376 */
1377 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_NORMAL_PRIORITY_MASK, VM_FF_PGM_NO_MEMORY))
1378 {
1379 /*
1380 * PDM Queues are pending.
1381 */
1382 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_QUEUES, VM_FF_PGM_NO_MEMORY))
1383 PDMR3QueueFlushAll(pVM);
1384
1385 /*
1386 * PDM DMA transfers are pending.
1387 */
1388 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_DMA, VM_FF_PGM_NO_MEMORY))
1389 PDMR3DmaRun(pVM);
1390
1391 /*
1392 * EMT Rendezvous (make sure they are handled before the requests).
1393 */
1394 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1395 {
1396 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1397 UPDATE_RC();
1398 /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
1399 * stopped/reset before the next VM state change is made. We need a better
1400 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1401 * && rc >= VINF_EM_SUSPEND). */
1402 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1403 {
1404 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1405 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1406 return rc;
1407 }
1408 }
1409
1410 /*
1411 * Requests from other threads.
1412 */
1413 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
1414 {
1415 rc2 = VMR3ReqProcessU(pVM->pUVM, VMCPUID_ANY);
1416 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE) /** @todo this shouldn't be necessary */
1417 {
1418 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1419 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1420 return rc2;
1421 }
1422 UPDATE_RC();
1423 /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
1424 * stopped/reset before the next VM state change is made. We need a better
1425 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1426 * && rc >= VINF_EM_SUSPEND). */
1427 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1428 {
1429 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1430 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1431 return rc;
1432 }
1433 }
1434
1435 /* Replay the handler notification changes. */
1436 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REM_HANDLER_NOTIFY, VM_FF_PGM_NO_MEMORY))
1437 {
1438 /* Try not to cause deadlocks. */
1439 if ( pVM->cCpus == 1
1440 || ( !PGMIsLockOwner(pVM)
1441 && !IOMIsLockOwner(pVM))
1442 )
1443 {
1444 EMRemLock(pVM);
1445 REMR3ReplayHandlerNotifications(pVM);
1446 EMRemUnlock(pVM);
1447 }
1448 }
1449
1450 /* check that we got them all */
1451 AssertCompile(VM_FF_NORMAL_PRIORITY_MASK == (VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_REM_HANDLER_NOTIFY | VM_FF_EMT_RENDEZVOUS));
1452 }
1453
1454 /*
1455 * Normal priority then. (per-VCPU)
1456 * (Executed in no particular order.)
1457 */
1458 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1459 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_MASK))
1460 {
1461 /*
1462 * Requests from other threads.
1463 */
1464 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1465 {
1466 rc2 = VMR3ReqProcessU(pVM->pUVM, pVCpu->idCpu);
1467 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE || rc2 == VINF_EM_RESET)
1468 {
1469 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1470 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1471 return rc2;
1472 }
1473 UPDATE_RC();
1474 /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
1475 * stopped/reset before the next VM state change is made. We need a better
1476 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1477 * && rc >= VINF_EM_SUSPEND). */
1478 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1479 {
1480 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1481 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1482 return rc;
1483 }
1484 }
1485
1486 /* check that we got them all */
1487 Assert(!(VMCPU_FF_NORMAL_PRIORITY_MASK & ~(VMCPU_FF_REQUEST)));
1488 }
1489
1490 /*
1491 * High priority pre execution chunk last.
1492 * (Executed in ascending priority order.)
1493 */
1494 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK)
1495 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_MASK))
1496 {
1497 /*
1498 * Timers before interrupts.
1499 */
1500 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER)
1501 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1502 TMR3TimerQueuesDo(pVM);
1503
1504 /*
1505 * The instruction following an emulated STI should *always* be executed!
1506 */
1507 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1508 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1509 {
1510 Log(("VMCPU_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu), EMGetInhibitInterruptsPC(pVCpu)));
1511 if (CPUMGetGuestRIP(pVCpu) != EMGetInhibitInterruptsPC(pVCpu))
1512 {
1513 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
1514 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1515 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1516 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1517 */
1518 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1519 }
1520 if (HWACCMR3IsActive(pVCpu))
1521 rc2 = VINF_EM_RESCHEDULE_HWACC;
1522 else
1523 rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
1524
1525 UPDATE_RC();
1526 }
1527
1528 /*
1529 * Interrupts.
1530 */
1531 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1532 && !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1533 && (!rc || rc >= VINF_EM_RESCHEDULE_HWACC)
1534 && !TRPMHasTrap(pVCpu) /* an interrupt could already be scheduled for dispatching in the recompiler. */
1535 && PATMAreInterruptsEnabled(pVM)
1536 && !HWACCMR3IsEventPending(pVCpu))
1537 {
1538 Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1539 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
1540 {
1541 /* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
1542 /** @todo this really isn't nice, should properly handle this */
1543 rc2 = TRPMR3InjectEvent(pVM, pVCpu, TRPM_HARDWARE_INT);
1544#ifdef VBOX_STRICT
1545 rcIrq = rc2;
1546#endif
1547 UPDATE_RC();
1548 }
1549 /** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
1550 else if (REMR3QueryPendingInterrupt(pVM, pVCpu) != REM_NO_PENDING_IRQ)
1551 {
1552 rc2 = VINF_EM_RESCHEDULE_REM;
1553 UPDATE_RC();
1554 }
1555 }
1556
1557 /*
1558 * Allocate handy pages.
1559 */
1560 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1561 {
1562 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1563 UPDATE_RC();
1564 }
1565
1566 /*
1567 * Debugger Facility request.
1568 */
1569 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_DBGF, VM_FF_PGM_NO_MEMORY))
1570 {
1571 rc2 = DBGFR3VMMForcedAction(pVM);
1572 UPDATE_RC();
1573 }
1574
1575 /*
1576 * EMT Rendezvous (must be serviced before termination).
1577 */
1578 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1579 {
1580 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1581 UPDATE_RC();
1582 /** @todo HACK ALERT! The following test is to make sure EM+TM thinks the VM is
1583 * stopped/reset before the next VM state change is made. We need a better
1584 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1585 * && rc >= VINF_EM_SUSPEND). */
1586 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1587 {
1588 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1589 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1590 return rc;
1591 }
1592 }
1593
1594 /*
1595 * State change request (cleared by vmR3SetStateLocked).
1596 */
1597 if (VM_FF_ISPENDING(pVM, VM_FF_CHECK_VM_STATE))
1598 {
1599 VMSTATE enmState = VMR3GetState(pVM);
1600 switch (enmState)
1601 {
1602 case VMSTATE_FATAL_ERROR:
1603 case VMSTATE_FATAL_ERROR_LS:
1604 Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
1605 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1606 return VINF_EM_SUSPEND;
1607
1608 case VMSTATE_DESTROYING:
1609 Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
1610 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1611 return VINF_EM_TERMINATE;
1612
1613 default:
1614 AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
1615 }
1616 }
1617
1618 /*
1619 * Out of memory? Since most of our fellow high priority actions may cause us
1620 * to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
1621 * at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
1622 * than us since we can terminate without allocating more memory.
1623 */
1624 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1625 {
1626 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1627 UPDATE_RC();
1628 if (rc == VINF_EM_NO_MEMORY)
1629 return rc;
1630 }
1631
1632 /*
1633 * If the virtual sync clock is still stopped, make TM restart it.
1634 */
1635 if (VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
1636 TMR3VirtualSyncFF(pVM, pVCpu);
1637
1638#ifdef DEBUG
1639 /*
1640 * Debug, pause the VM.
1641 */
1642 if (VM_FF_ISPENDING(pVM, VM_FF_DEBUG_SUSPEND))
1643 {
1644 VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
1645 Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
1646 return VINF_EM_SUSPEND;
1647 }
1648#endif
1649
1650 /* check that we got them all */
1651 AssertCompile(VM_FF_HIGH_PRIORITY_PRE_MASK == (VM_FF_TM_VIRTUAL_SYNC | VM_FF_DBGF | VM_FF_CHECK_VM_STATE | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1652 AssertCompile(VMCPU_FF_HIGH_PRIORITY_PRE_MASK == (VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_INHIBIT_INTERRUPTS));
1653 }
1654
1655#undef UPDATE_RC
1656 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1657 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1658 Assert(rcIrq == VINF_SUCCESS || rcIrq == rc);
1659 return rc;
1660}
1661
1662
1663/**
1664 * Check if the preset execution time cap restricts guest execution scheduling.
1665 *
1666 * @returns true if allowed, false otherwise
1667 * @param pVM The VM to operate on.
1668 * @param pVCpu The VMCPU to operate on.
1669 *
1670 */
1671VMMR3DECL(bool) EMR3IsExecutionAllowed(PVM pVM, PVMCPU pVCpu)
1672{
1673 uint64_t u64UserTime, u64KernelTime;
1674
1675 if ( pVM->uCpuExecutionCap != 100
1676 && RT_SUCCESS(RTThreadGetExecutionTimeMilli(&u64KernelTime, &u64UserTime)))
1677 {
1678 uint64_t u64TimeNow = RTTimeMilliTS();
1679 if (pVCpu->em.s.u64TimeSliceStart + EM_TIME_SLICE < u64TimeNow)
1680 {
1681 /* New time slice. */
1682 pVCpu->em.s.u64TimeSliceStart = u64TimeNow;
1683 pVCpu->em.s.u64TimeSliceStartExec = u64KernelTime + u64UserTime;
1684 pVCpu->em.s.u64TimeSliceExec = 0;
1685 }
1686 pVCpu->em.s.u64TimeSliceExec = u64KernelTime + u64UserTime - pVCpu->em.s.u64TimeSliceStartExec;
1687
1688 Log2(("emR3IsExecutionAllowed: start=%RX64 startexec=%RX64 exec=%RX64 (cap=%x)\n", pVCpu->em.s.u64TimeSliceStart, pVCpu->em.s.u64TimeSliceStartExec, pVCpu->em.s.u64TimeSliceExec, (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100));
1689 if (pVCpu->em.s.u64TimeSliceExec >= (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100)
1690 return false;
1691 }
1692 return true;
1693}
1694
1695
1696/**
1697 * Execute VM.
1698 *
1699 * This function is the main loop of the VM. The emulation thread
1700 * calls this function when the VM has been successfully constructed
1701 * and we're ready for executing the VM.
1702 *
1703 * Returning from this function means that the VM is turned off or
1704 * suspended (state already saved) and deconstruction in next in line.
1705 *
1706 * All interaction from other thread are done using forced actions
1707 * and signaling of the wait object.
1708 *
1709 * @returns VBox status code, informational status codes may indicate failure.
1710 * @param pVM The VM to operate on.
1711 * @param pVCpu The VMCPU to operate on.
1712 */
1713VMMR3DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu)
1714{
1715 Log(("EMR3ExecuteVM: pVM=%p enmVMState=%d (%s) enmState=%d (%s) enmPrevState=%d (%s) fForceRAW=%RTbool\n",
1716 pVM,
1717 pVM->enmVMState, VMR3GetStateName(pVM->enmVMState),
1718 pVCpu->em.s.enmState, emR3GetStateName(pVCpu->em.s.enmState),
1719 pVCpu->em.s.enmPrevState, emR3GetStateName(pVCpu->em.s.enmPrevState),
1720 pVCpu->em.s.fForceRAW));
1721 VM_ASSERT_EMT(pVM);
1722 AssertMsg( pVCpu->em.s.enmState == EMSTATE_NONE
1723 || pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI
1724 || pVCpu->em.s.enmState == EMSTATE_SUSPENDED,
1725 ("%s\n", emR3GetStateName(pVCpu->em.s.enmState)));
1726
1727 int rc = setjmp(pVCpu->em.s.u.FatalLongJump);
1728 if (rc == 0)
1729 {
1730 /*
1731 * Start the virtual time.
1732 */
1733 TMR3NotifyResume(pVM, pVCpu);
1734
1735 /*
1736 * The Outer Main Loop.
1737 */
1738 bool fFFDone = false;
1739
1740 /* Reschedule right away to start in the right state. */
1741 rc = VINF_SUCCESS;
1742
1743 /* If resuming after a pause or a state load, restore the previous
1744 state or else we'll start executing code. Else, just reschedule. */
1745 if ( pVCpu->em.s.enmState == EMSTATE_SUSPENDED
1746 && ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
1747 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED))
1748 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
1749 else
1750 pVCpu->em.s.enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1751
1752 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
1753 for (;;)
1754 {
1755 /*
1756 * Before we can schedule anything (we're here because
1757 * scheduling is required) we must service any pending
1758 * forced actions to avoid any pending action causing
1759 * immediate rescheduling upon entering an inner loop
1760 *
1761 * Do forced actions.
1762 */
1763 if ( !fFFDone
1764 && rc != VINF_EM_TERMINATE
1765 && rc != VINF_EM_OFF
1766 && ( VM_FF_ISPENDING(pVM, VM_FF_ALL_REM_MASK)
1767 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_REM_MASK)))
1768 {
1769 rc = emR3ForcedActions(pVM, pVCpu, rc);
1770 if ( ( rc == VINF_EM_RESCHEDULE_REM
1771 || rc == VINF_EM_RESCHEDULE_HWACC)
1772 && pVCpu->em.s.fForceRAW)
1773 rc = VINF_EM_RESCHEDULE_RAW;
1774 }
1775 else if (fFFDone)
1776 fFFDone = false;
1777
1778 /*
1779 * Now what to do?
1780 */
1781 Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
1782 switch (rc)
1783 {
1784 /*
1785 * Keep doing what we're currently doing.
1786 */
1787 case VINF_SUCCESS:
1788 break;
1789
1790 /*
1791 * Reschedule - to raw-mode execution.
1792 */
1793 case VINF_EM_RESCHEDULE_RAW:
1794 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVCpu->em.s.enmState, EMSTATE_RAW));
1795 pVCpu->em.s.enmState = EMSTATE_RAW;
1796 break;
1797
1798 /*
1799 * Reschedule - to hardware accelerated raw-mode execution.
1800 */
1801 case VINF_EM_RESCHEDULE_HWACC:
1802 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVCpu->em.s.enmState, EMSTATE_HWACC));
1803 Assert(!pVCpu->em.s.fForceRAW);
1804 pVCpu->em.s.enmState = EMSTATE_HWACC;
1805 break;
1806
1807 /*
1808 * Reschedule - to recompiled execution.
1809 */
1810 case VINF_EM_RESCHEDULE_REM:
1811 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVCpu->em.s.enmState, EMSTATE_REM));
1812 pVCpu->em.s.enmState = EMSTATE_REM;
1813 break;
1814
1815 /*
1816 * Resume.
1817 */
1818 case VINF_EM_RESUME:
1819 Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVCpu->em.s.enmState));
1820 /* Don't reschedule in the halted or wait for SIPI case. */
1821 if ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
1822 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED)
1823 break;
1824 /* fall through and get scheduled. */
1825
1826 /*
1827 * Reschedule.
1828 */
1829 case VINF_EM_RESCHEDULE:
1830 {
1831 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1832 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, emR3GetStateName(enmState)));
1833 pVCpu->em.s.enmState = enmState;
1834 break;
1835 }
1836
1837 /*
1838 * Halted.
1839 */
1840 case VINF_EM_HALT:
1841 Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_HALTED));
1842 pVCpu->em.s.enmState = EMSTATE_HALTED;
1843 break;
1844
1845 /*
1846 * Switch to the wait for SIPI state (application processor only)
1847 */
1848 case VINF_EM_WAIT_SIPI:
1849 Assert(pVCpu->idCpu != 0);
1850 Log2(("EMR3ExecuteVM: VINF_EM_WAIT_SIPI: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_WAIT_SIPI));
1851 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
1852 break;
1853
1854
1855 /*
1856 * Suspend.
1857 */
1858 case VINF_EM_SUSPEND:
1859 Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
1860 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
1861 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
1862 break;
1863
1864 /*
1865 * Reset.
1866 * We might end up doing a double reset for now, we'll have to clean up the mess later.
1867 */
1868 case VINF_EM_RESET:
1869 {
1870 if (pVCpu->idCpu == 0)
1871 {
1872 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1873 Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, emR3GetStateName(enmState)));
1874 pVCpu->em.s.enmState = enmState;
1875 }
1876 else
1877 {
1878 /* All other VCPUs go into the wait for SIPI state. */
1879 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
1880 }
1881 break;
1882 }
1883
1884 /*
1885 * Power Off.
1886 */
1887 case VINF_EM_OFF:
1888 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
1889 Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
1890 TMR3NotifySuspend(pVM, pVCpu);
1891 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1892 return rc;
1893
1894 /*
1895 * Terminate the VM.
1896 */
1897 case VINF_EM_TERMINATE:
1898 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
1899 Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
1900 if (pVM->enmVMState < VMSTATE_DESTROYING) /* ugly */
1901 TMR3NotifySuspend(pVM, pVCpu);
1902 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1903 return rc;
1904
1905
1906 /*
1907 * Out of memory, suspend the VM and stuff.
1908 */
1909 case VINF_EM_NO_MEMORY:
1910 Log2(("EMR3ExecuteVM: VINF_EM_NO_MEMORY: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
1911 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
1912 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
1913 TMR3NotifySuspend(pVM, pVCpu);
1914 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1915
1916 rc = VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_SUSPEND, "HostMemoryLow",
1917 N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
1918 if (rc != VINF_EM_SUSPEND)
1919 {
1920 if (RT_SUCCESS_NP(rc))
1921 {
1922 AssertLogRelMsgFailed(("%Rrc\n", rc));
1923 rc = VERR_EM_INTERNAL_ERROR;
1924 }
1925 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
1926 }
1927 return rc;
1928
1929 /*
1930 * Guest debug events.
1931 */
1932 case VINF_EM_DBG_STEPPED:
1933 AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
1934 case VINF_EM_DBG_STOP:
1935 case VINF_EM_DBG_BREAKPOINT:
1936 case VINF_EM_DBG_STEP:
1937 if (pVCpu->em.s.enmState == EMSTATE_RAW)
1938 {
1939 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
1940 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1941 }
1942 else
1943 {
1944 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
1945 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1946 }
1947 break;
1948
1949 /*
1950 * Hypervisor debug events.
1951 */
1952 case VINF_EM_DBG_HYPER_STEPPED:
1953 case VINF_EM_DBG_HYPER_BREAKPOINT:
1954 case VINF_EM_DBG_HYPER_ASSERTION:
1955 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_HYPER));
1956 pVCpu->em.s.enmState = EMSTATE_DEBUG_HYPER;
1957 break;
1958
1959 /*
1960 * Guru mediations.
1961 */
1962 case VERR_VMM_RING0_ASSERTION:
1963 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVCpu->em.s.enmState, EMSTATE_GURU_MEDITATION));
1964 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
1965 break;
1966
1967 /*
1968 * Any error code showing up here other than the ones we
1969 * know and process above are considered to be FATAL.
1970 *
1971 * Unknown warnings and informational status codes are also
1972 * included in this.
1973 */
1974 default:
1975 if (RT_SUCCESS_NP(rc))
1976 {
1977 AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
1978 rc = VERR_EM_INTERNAL_ERROR;
1979 }
1980 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVCpu->em.s.enmState, EMSTATE_GURU_MEDITATION));
1981 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
1982 break;
1983 }
1984
1985 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x); /* (skip this in release) */
1986 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
1987
1988 /*
1989 * Act on the state.
1990 */
1991 switch (pVCpu->em.s.enmState)
1992 {
1993 /*
1994 * Execute raw.
1995 */
1996 case EMSTATE_RAW:
1997#ifndef IEM_VERIFICATION_MODE /* remove later */
1998 rc = emR3RawExecute(pVM, pVCpu, &fFFDone);
1999 break;
2000#endif
2001
2002 /*
2003 * Execute hardware accelerated raw.
2004 */
2005 case EMSTATE_HWACC:
2006#ifndef IEM_VERIFICATION_MODE /* remove later */
2007 rc = emR3HwAccExecute(pVM, pVCpu, &fFFDone);
2008 break;
2009#endif
2010
2011 /*
2012 * Execute recompiled.
2013 */
2014 case EMSTATE_REM:
2015#ifdef IEM_VERIFICATION_MODE
2016# if 1
2017 rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu)); fFFDone = false;
2018# else
2019 rc = VBOXSTRICTRC_TODO(REMR3EmulateInstruction(pVM, pVCpu)); fFFDone = false;
2020 if (rc == VINF_EM_RESCHEDULE)
2021 rc = VINF_SUCCESS;
2022# endif
2023#else
2024 rc = emR3RemExecute(pVM, pVCpu, &fFFDone);
2025#endif
2026 Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
2027 break;
2028
2029 /*
2030 * Application processor execution halted until SIPI.
2031 */
2032 case EMSTATE_WAIT_SIPI:
2033 /* no break */
2034 /*
2035 * hlt - execution halted until interrupt.
2036 */
2037 case EMSTATE_HALTED:
2038 {
2039 STAM_REL_PROFILE_START(&pVCpu->em.s.StatHalted, y);
2040 if (pVCpu->em.s.mwait.fWait & EMMWAIT_FLAG_ACTIVE)
2041 {
2042 /* mwait has a special extension where it's woken up when an interrupt is pending even when IF=0. */
2043 rc = VMR3WaitHalted(pVM, pVCpu, !(pVCpu->em.s.mwait.fWait & EMMWAIT_FLAG_BREAKIRQIF0) && !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
2044 pVCpu->em.s.mwait.fWait &= ~(EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0);
2045 }
2046 else
2047 rc = VMR3WaitHalted(pVM, pVCpu, !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
2048
2049 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHalted, y);
2050 break;
2051 }
2052
2053 /*
2054 * Suspended - return to VM.cpp.
2055 */
2056 case EMSTATE_SUSPENDED:
2057 TMR3NotifySuspend(pVM, pVCpu);
2058 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2059 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2060 return VINF_EM_SUSPEND;
2061
2062 /*
2063 * Debugging in the guest.
2064 */
2065 case EMSTATE_DEBUG_GUEST_REM:
2066 case EMSTATE_DEBUG_GUEST_RAW:
2067 TMR3NotifySuspend(pVM, pVCpu);
2068 rc = emR3Debug(pVM, pVCpu, rc);
2069 TMR3NotifyResume(pVM, pVCpu);
2070 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2071 break;
2072
2073 /*
2074 * Debugging in the hypervisor.
2075 */
2076 case EMSTATE_DEBUG_HYPER:
2077 {
2078 TMR3NotifySuspend(pVM, pVCpu);
2079 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2080
2081 rc = emR3Debug(pVM, pVCpu, rc);
2082 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2083 if (rc != VINF_SUCCESS)
2084 {
2085 /* switch to guru meditation mode */
2086 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2087 VMMR3FatalDump(pVM, pVCpu, rc);
2088 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2089 return rc;
2090 }
2091
2092 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2093 TMR3NotifyResume(pVM, pVCpu);
2094 break;
2095 }
2096
2097 /*
2098 * Guru meditation takes place in the debugger.
2099 */
2100 case EMSTATE_GURU_MEDITATION:
2101 {
2102 TMR3NotifySuspend(pVM, pVCpu);
2103 VMMR3FatalDump(pVM, pVCpu, rc);
2104 emR3Debug(pVM, pVCpu, rc);
2105 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2106 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2107 return rc;
2108 }
2109
2110 /*
2111 * The states we don't expect here.
2112 */
2113 case EMSTATE_NONE:
2114 case EMSTATE_TERMINATING:
2115 default:
2116 AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVCpu->em.s.enmState));
2117 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2118 TMR3NotifySuspend(pVM, pVCpu);
2119 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2120 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2121 return VERR_EM_INTERNAL_ERROR;
2122 }
2123 } /* The Outer Main Loop */
2124 }
2125 else
2126 {
2127 /*
2128 * Fatal error.
2129 */
2130 Log(("EMR3ExecuteVM: returns %Rrc because of longjmp / fatal error; (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2131 TMR3NotifySuspend(pVM, pVCpu);
2132 VMMR3FatalDump(pVM, pVCpu, rc);
2133 emR3Debug(pVM, pVCpu, rc);
2134 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2135 /** @todo change the VM state! */
2136 return rc;
2137 }
2138
2139 /* (won't ever get here). */
2140 AssertFailed();
2141}
2142
2143/**
2144 * Notify EM of a state change (used by FTM)
2145 *
2146 * @param pVM VM Handle.
2147 */
2148VMMR3DECL(int) EMR3NotifySuspend(PVM pVM)
2149{
2150 PVMCPU pVCpu = VMMGetCpu(pVM);
2151
2152 TMR3NotifySuspend(pVM, pVCpu); /* Stop the virtual time. */
2153 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
2154 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2155 return VINF_SUCCESS;
2156}
2157
2158/**
2159 * Notify EM of a state change (used by FTM)
2160 *
2161 * @param pVM VM Handle.
2162 */
2163VMMR3DECL(int) EMR3NotifyResume(PVM pVM)
2164{
2165 PVMCPU pVCpu = VMMGetCpu(pVM);
2166 EMSTATE enmCurState = pVCpu->em.s.enmState;
2167
2168 TMR3NotifyResume(pVM, pVCpu); /* Resume the virtual time. */
2169 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2170 pVCpu->em.s.enmPrevState = enmCurState;
2171 return VINF_SUCCESS;
2172}
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