DBGFDisas.cpp@ 69300

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1	/* $Id: DBGFDisas.cpp 69111 2017-10-17 14:26:02Z vboxsync $ */
2	/** @file
3	* DBGF - Debugger Facility, Disassembler.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DBGF
23	#include <VBox/vmm/dbgf.h>
24	#include <VBox/vmm/selm.h>
25	#include <VBox/vmm/mm.h>
26	#include <VBox/vmm/hm.h>
27	#include <VBox/vmm/pgm.h>
28	#include <VBox/vmm/cpum.h>
29	#ifdef VBOX_WITH_RAW_MODE
30	# include <VBox/vmm/patm.h>
31	#endif
32	#include "DBGFInternal.h"
33	#include <VBox/dis.h>
34	#include <VBox/err.h>
35	#include <VBox/param.h>
36	#include <VBox/vmm/vm.h>
37	#include <VBox/vmm/uvm.h>
38
39	#include <VBox/log.h>
40	#include <iprt/assert.h>
41	#include <iprt/string.h>
42	#include <iprt/alloca.h>
43	#include <iprt/ctype.h>
44
45
46	/*********************************************************************************************************************************
47	* Structures and Typedefs *
48	*********************************************************************************************************************************/
49	/**
50	* Structure used when disassembling and instructions in DBGF.
51	* This is used so the reader function can get the stuff it needs.
52	*/
53	typedef struct
54	{
55	/** The core structure. */
56	DISCPUSTATE Cpu;
57	/** The cross context VM structure. */
58	PVM pVM;
59	/** The cross context virtual CPU structure. */
60	PVMCPU pVCpu;
61	/** The address space for resolving symbol. */
62	RTDBGAS hDbgAs;
63	/** Pointer to the first byte in the segment. */
64	RTGCUINTPTR GCPtrSegBase;
65	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
66	RTGCUINTPTR GCPtrSegEnd;
67	/** The size of the segment minus 1. */
68	RTGCUINTPTR cbSegLimit;
69	/** The guest paging mode. */
70	PGMMODE enmMode;
71	/** Pointer to the current page - R3 Ptr. */
72	void const *pvPageR3;
73	/** Pointer to the current page - GC Ptr. */
74	RTGCPTR GCPtrPage;
75	/** Pointer to the next instruction (relative to GCPtrSegBase). */
76	RTGCUINTPTR GCPtrNext;
77	/** The lock information that PGMPhysReleasePageMappingLock needs. */
78	PGMPAGEMAPLOCK PageMapLock;
79	/** Whether the PageMapLock is valid or not. */
80	bool fLocked;
81	/** 64 bits mode or not. */
82	bool f64Bits;
83	/** Read original unpatched bytes from the patch manager. */
84	bool fUnpatchedBytes;
85	/** Set when fUnpatchedBytes is active and we encounter patched bytes. */
86	bool fPatchedInstr;
87	} DBGFDISASSTATE, *PDBGFDISASSTATE;
88
89
90	/*********************************************************************************************************************************
91	* Internal Functions *
92	*********************************************************************************************************************************/
93	static FNDISREADBYTES dbgfR3DisasInstrRead;
94
95
96
97	/**
98	* Calls the disassembler with the proper reader functions and such for disa
99	*
100	* @returns VBox status code.
101	* @param pVM The cross context VM structure.
102	* @param pVCpu The cross context virtual CPU structure.
103	* @param pSelInfo The selector info.
104	* @param enmMode The guest paging mode.
105	* @param fFlags DBGF_DISAS_FLAGS_XXX.
106	* @param GCPtr The GC pointer (selector offset).
107	* @param pState The disas CPU state.
108	*/
109	static int dbgfR3DisasInstrFirst(PVM pVM, PVMCPU pVCpu, PDBGFSELINFO pSelInfo, PGMMODE enmMode,
110	RTGCPTR GCPtr, uint32_t fFlags, PDBGFDISASSTATE pState)
111	{
112	pState->GCPtrSegBase = pSelInfo->GCPtrBase;
113	pState->GCPtrSegEnd = pSelInfo->cbLimit + 1 + (RTGCUINTPTR)pSelInfo->GCPtrBase;
114	pState->cbSegLimit = pSelInfo->cbLimit;
115	pState->enmMode = enmMode;
116	pState->GCPtrPage = 0;
117	pState->pvPageR3 = NULL;
118	pState->hDbgAs = !HMIsEnabled(pVM)
119	? DBGF_AS_RC_AND_GC_GLOBAL
120	: DBGF_AS_GLOBAL;
121	pState->pVM = pVM;
122	pState->pVCpu = pVCpu;
123	pState->fLocked = false;
124	pState->f64Bits = enmMode >= PGMMODE_AMD64 && pSelInfo->u.Raw.Gen.u1Long;
125	#ifdef VBOX_WITH_RAW_MODE
126	pState->fUnpatchedBytes = RT_BOOL(fFlags & DBGF_DISAS_FLAGS_UNPATCHED_BYTES);
127	pState->fPatchedInstr = false;
128	#endif
129
130	DISCPUMODE enmCpuMode;
131	switch (fFlags & DBGF_DISAS_FLAGS_MODE_MASK)
132	{
133	default:
134	AssertFailed();
135	RT_FALL_THRU();
136	case DBGF_DISAS_FLAGS_DEFAULT_MODE:
137	enmCpuMode = pState->f64Bits
138	? DISCPUMODE_64BIT
139	: pSelInfo->u.Raw.Gen.u1DefBig
140	? DISCPUMODE_32BIT
141	: DISCPUMODE_16BIT;
142	break;
143	case DBGF_DISAS_FLAGS_16BIT_MODE:
144	case DBGF_DISAS_FLAGS_16BIT_REAL_MODE:
145	enmCpuMode = DISCPUMODE_16BIT;
146	break;
147	case DBGF_DISAS_FLAGS_32BIT_MODE:
148	enmCpuMode = DISCPUMODE_32BIT;
149	break;
150	case DBGF_DISAS_FLAGS_64BIT_MODE:
151	enmCpuMode = DISCPUMODE_64BIT;
152	break;
153	}
154
155	uint32_t cbInstr;
156	int rc = DISInstrWithReader(GCPtr,
157	enmCpuMode,
158	dbgfR3DisasInstrRead,
159	&pState->Cpu,
160	&pState->Cpu,
161	&cbInstr);
162	if (RT_SUCCESS(rc))
163	{
164	pState->GCPtrNext = GCPtr + cbInstr;
165	return VINF_SUCCESS;
166	}
167
168	/* cleanup */
169	if (pState->fLocked)
170	{
171	PGMPhysReleasePageMappingLock(pVM, &pState->PageMapLock);
172	pState->fLocked = false;
173	}
174	return rc;
175	}
176
177
178	#if 0
179	/**
180	* Calls the disassembler for disassembling the next instruction.
181	*
182	* @returns VBox status code.
183	* @param pState The disas CPU state.
184	*/
185	static int dbgfR3DisasInstrNext(PDBGFDISASSTATE pState)
186	{
187	uint32_t cbInstr;
188	int rc = DISInstr(&pState->Cpu, (void *)pState->GCPtrNext, 0, &cbInstr, NULL);
189	if (RT_SUCCESS(rc))
190	{
191	pState->GCPtrNext = GCPtr + cbInstr;
192	return VINF_SUCCESS;
193	}
194	return rc;
195	}
196	#endif
197
198
199	/**
200	* Done with the disassembler state, free associated resources.
201	*
202	* @param pState The disas CPU state ++.
203	*/
204	static void dbgfR3DisasInstrDone(PDBGFDISASSTATE pState)
205	{
206	if (pState->fLocked)
207	{
208	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
209	pState->fLocked = false;
210	}
211	}
212
213
214	/**
215	* @callback_method_impl{FNDISREADBYTES}
216	*
217	* @remarks The source is relative to the base address indicated by
218	* DBGFDISASSTATE::GCPtrSegBase.
219	*/
220	static DECLCALLBACK(int) dbgfR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
221	{
222	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pDis;
223	for (;;)
224	{
225	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
226
227	/*
228	* Need to update the page translation?
229	*/
230	if ( !pState->pvPageR3
231	\|\| (GCPtr >> PAGE_SHIFT) != (pState->GCPtrPage >> PAGE_SHIFT))
232	{
233	int rc = VINF_SUCCESS;
234
235	/* translate the address */
236	pState->GCPtrPage = GCPtr & PAGE_BASE_GC_MASK;
237	if ( !HMIsEnabled(pState->pVM)
238	&& MMHyperIsInsideArea(pState->pVM, pState->GCPtrPage))
239	{
240	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->GCPtrPage);
241	if (!pState->pvPageR3)
242	rc = VERR_INVALID_POINTER;
243	}
244	else
245	{
246	if (pState->fLocked)
247	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
248
249	if (pState->enmMode <= PGMMODE_PROTECTED)
250	rc = PGMPhysGCPhys2CCPtrReadOnly(pState->pVM, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
251	else
252	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
253	pState->fLocked = RT_SUCCESS_NP(rc);
254	}
255	if (RT_FAILURE(rc))
256	{
257	pState->pvPageR3 = NULL;
258	return rc;
259	}
260	}
261
262	/*
263	* Check the segment limit.
264	*/
265	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
266	return VERR_OUT_OF_SELECTOR_BOUNDS;
267
268	/*
269	* Calc how much we can read, maxing out the read.
270	*/
271	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
272	if (!pState->f64Bits)
273	{
274	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
275	if (cb > cbSeg && cbSeg)
276	cb = cbSeg;
277	}
278	if (cb > cbMaxRead)
279	cb = cbMaxRead;
280
281	#ifdef VBOX_WITH_RAW_MODE
282	/*
283	* Read original bytes from PATM if asked to do so.
284	*/
285	if (pState->fUnpatchedBytes)
286	{
287	size_t cbRead = cb;
288	int rc = PATMR3ReadOrgInstr(pState->pVM, GCPtr, &pDis->abInstr[offInstr], cbRead, &cbRead);
289	if (RT_SUCCESS(rc))
290	{
291	pState->fPatchedInstr = true;
292	if (cbRead >= cbMinRead)
293	{
294	pDis->cbCachedInstr = offInstr + (uint8_t)cbRead;
295	return rc;
296	}
297
298	cbMinRead -= (uint8_t)cbRead;
299	cbMaxRead -= (uint8_t)cbRead;
300	cb -= (uint8_t)cbRead;
301	offInstr += (uint8_t)cbRead;
302	GCPtr += cbRead;
303	if (!cb)
304	continue;
305	}
306	}
307	#endif /* VBOX_WITH_RAW_MODE */
308
309	/*
310	* Read and advance,
311	*/
312	memcpy(&pDis->abInstr[offInstr], (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
313	offInstr += (uint8_t)cb;
314	if (cb >= cbMinRead)
315	{
316	pDis->cbCachedInstr = offInstr;
317	return VINF_SUCCESS;
318	}
319	cbMaxRead -= (uint8_t)cb;
320	cbMinRead -= (uint8_t)cb;
321	}
322	}
323
324
325	/**
326	* @callback_method_impl{FNDISGETSYMBOL}
327	*/
328	static DECLCALLBACK(int) dbgfR3DisasGetSymbol(PCDISCPUSTATE pDis, uint32_t u32Sel, RTUINTPTR uAddress,
329	char pszBuf, size_t cchBuf, RTINTPTR poff, void *pvUser)
330	{
331	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pDis;
332	PCDBGFSELINFO pSelInfo = (PCDBGFSELINFO)pvUser;
333
334	/*
335	* Address conversion
336	*/
337	DBGFADDRESS Addr;
338	int rc;
339	/* Start with CS. */
340	if ( DIS_FMT_SEL_IS_REG(u32Sel)
341	? DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_CS
342	: pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel))
343	rc = DBGFR3AddrFromSelInfoOff(pState->pVM->pUVM, &Addr, pSelInfo, uAddress);
344	/* In long mode everything but FS and GS is easy. */
345	else if ( pState->Cpu.uCpuMode == DISCPUMODE_64BIT
346	&& DIS_FMT_SEL_IS_REG(u32Sel)
347	&& DIS_FMT_SEL_GET_REG(u32Sel) != DISSELREG_GS
348	&& DIS_FMT_SEL_GET_REG(u32Sel) != DISSELREG_FS)
349	{
350	DBGFR3AddrFromFlat(pState->pVM->pUVM, &Addr, uAddress);
351	rc = VINF_SUCCESS;
352	}
353	/* Here's a quick hack to catch patch manager SS relative access. */
354	else if ( DIS_FMT_SEL_IS_REG(u32Sel)
355	&& DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_SS
356	&& pSelInfo->GCPtrBase == 0
357	&& pSelInfo->cbLimit >= UINT32_MAX
358	#ifdef VBOX_WITH_RAW_MODE
359	&& PATMIsPatchGCAddr(pState->pVM, pState->Cpu.uInstrAddr)
360	#endif
361	)
362	{
363	DBGFR3AddrFromFlat(pState->pVM->pUVM, &Addr, uAddress);
364	rc = VINF_SUCCESS;
365	}
366	else
367	{
368	/** @todo implement a generic solution here. */
369	rc = VERR_SYMBOL_NOT_FOUND;
370	}
371
372	/*
373	* If we got an address, try resolve it into a symbol.
374	*/
375	if (RT_SUCCESS(rc))
376	{
377	RTDBGSYMBOL Sym;
378	RTGCINTPTR off;
379	rc = DBGFR3AsSymbolByAddr(pState->pVM->pUVM, pState->hDbgAs, &Addr, RTDBGSYMADDR_FLAGS_LESS_OR_EQUAL,
380	&off, &Sym, NULL /phMod/);
381	if (RT_SUCCESS(rc))
382	{
383	/*
384	* Return the symbol and offset.
385	*/
386	size_t cchName = strlen(Sym.szName);
387	if (cchName >= cchBuf)
388	cchName = cchBuf - 1;
389	memcpy(pszBuf, Sym.szName, cchName);
390	pszBuf[cchName] = '\0';
391
392	*poff = off;
393	}
394	}
395	return rc;
396	}
397
398
399	/**
400	* Disassembles the one instruction according to the specified flags and
401	* address, internal worker executing on the EMT of the specified virtual CPU.
402	*
403	* @returns VBox status code.
404	* @param pVM The cross context VM structure.
405	* @param pVCpu The cross context virtual CPU structure.
406	* @param Sel The code selector. This used to determine the 32/16 bit ness and
407	* calculation of the actual instruction address.
408	* @param pGCPtr Pointer to the variable holding the code address
409	* relative to the base of Sel.
410	* @param fFlags Flags controlling where to start and how to format.
411	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
412	* @param pszOutput Output buffer.
413	* @param cbOutput Size of the output buffer.
414	* @param pcbInstr Where to return the size of the instruction.
415	* @param pDisState Where to store the disassembler state into.
416	*/
417	static DECLCALLBACK(int)
418	dbgfR3DisasInstrExOnVCpu(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PRTGCPTR pGCPtr, uint32_t fFlags,
419	char pszOutput, uint32_t cbOutput, uint32_t pcbInstr, PDBGFDISSTATE pDisState)
420	{
421	VMCPU_ASSERT_EMT(pVCpu);
422	RTGCPTR GCPtr = *pGCPtr;
423	int rc;
424
425	/*
426	* Get the Sel and GCPtr if fFlags requests that.
427	*/
428	PCCPUMCTXCORE pCtxCore = NULL;
429	PCCPUMSELREG pSRegCS = NULL;
430	if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST)
431	{
432	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
433	Sel = pCtxCore->cs.Sel;
434	pSRegCS = &pCtxCore->cs;
435	GCPtr = pCtxCore->rip;
436	}
437	else if (fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER)
438	{
439	fFlags \|= DBGF_DISAS_FLAGS_HYPER;
440	pCtxCore = CPUMGetHyperCtxCore(pVCpu);
441	Sel = pCtxCore->cs.Sel;
442	GCPtr = pCtxCore->rip;
443	}
444	/*
445	* Check if the selector matches the guest CS, use the hidden
446	* registers from that if they are valid. Saves time and effort.
447	*/
448	else
449	{
450	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
451	if (pCtxCore->cs.Sel == Sel && Sel != DBGF_SEL_FLAT)
452	pSRegCS = &pCtxCore->cs;
453	else
454	pCtxCore = NULL;
455	}
456
457	/*
458	* Read the selector info - assume no stale selectors and nasty stuff like that.
459	*
460	* Note! We CANNOT load invalid hidden selector registers since that would
461	* mean that log/debug statements or the debug will influence the
462	* guest state and make things behave differently.
463	*/
464	DBGFSELINFO SelInfo;
465	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
466	bool fRealModeAddress = false;
467
468	if ( pSRegCS
469	&& CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
470	{
471	SelInfo.Sel = Sel;
472	SelInfo.SelGate = 0;
473	SelInfo.GCPtrBase = pSRegCS->u64Base;
474	SelInfo.cbLimit = pSRegCS->u32Limit;
475	SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
476	? DBGFSELINFO_FLAGS_LONG_MODE
477	: enmMode != PGMMODE_REAL && !pCtxCore->eflags.Bits.u1VM
478	? DBGFSELINFO_FLAGS_PROT_MODE
479	: DBGFSELINFO_FLAGS_REAL_MODE;
480
481	SelInfo.u.Raw.au32[0] = 0;
482	SelInfo.u.Raw.au32[1] = 0;
483	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
484	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
485	SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
486	SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
487	SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
488	SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
489	SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
490	SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
491	fRealModeAddress = !!(SelInfo.fFlags & DBGFSELINFO_FLAGS_REAL_MODE);
492	}
493	else if (Sel == DBGF_SEL_FLAT)
494	{
495	SelInfo.Sel = Sel;
496	SelInfo.SelGate = 0;
497	SelInfo.GCPtrBase = 0;
498	SelInfo.cbLimit = ~(RTGCUINTPTR)0;
499	SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
500	? DBGFSELINFO_FLAGS_LONG_MODE
501	: enmMode != PGMMODE_REAL
502	? DBGFSELINFO_FLAGS_PROT_MODE
503	: DBGFSELINFO_FLAGS_REAL_MODE;
504	SelInfo.u.Raw.au32[0] = 0;
505	SelInfo.u.Raw.au32[1] = 0;
506	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
507	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
508
509	pSRegCS = &CPUMGetGuestCtxCore(pVCpu)->cs;
510	if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
511	{
512	/* Assume the current CS defines the execution mode. */
513	SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
514	SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
515	SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
516	SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
517	SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
518	SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
519	}
520	else
521	{
522	pSRegCS = NULL;
523	SelInfo.u.Raw.Gen.u1Present = 1;
524	SelInfo.u.Raw.Gen.u1Granularity = 1;
525	SelInfo.u.Raw.Gen.u1DefBig = 1;
526	SelInfo.u.Raw.Gen.u1DescType = 1;
527	SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
528	}
529	}
530	else if ( !(fFlags & DBGF_DISAS_FLAGS_HYPER)
531	&& ( (pCtxCore && pCtxCore->eflags.Bits.u1VM)
532	\|\| enmMode == PGMMODE_REAL
533	\|\| (fFlags & DBGF_DISAS_FLAGS_MODE_MASK) == DBGF_DISAS_FLAGS_16BIT_REAL_MODE
534	)
535	)
536	{ /* V86 mode or real mode - real mode addressing */
537	SelInfo.Sel = Sel;
538	SelInfo.SelGate = 0;
539	SelInfo.GCPtrBase = Sel * 16;
540	SelInfo.cbLimit = ~(RTGCUINTPTR)0;
541	SelInfo.fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
542	SelInfo.u.Raw.au32[0] = 0;
543	SelInfo.u.Raw.au32[1] = 0;
544	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
545	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
546	SelInfo.u.Raw.Gen.u1Present = 1;
547	SelInfo.u.Raw.Gen.u1Granularity = 1;
548	SelInfo.u.Raw.Gen.u1DefBig = 0; /* 16 bits */
549	SelInfo.u.Raw.Gen.u1DescType = 1;
550	SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
551	fRealModeAddress = true;
552	}
553	else
554	{
555	if (!(fFlags & DBGF_DISAS_FLAGS_HYPER))
556	rc = SELMR3GetSelectorInfo(pVM, pVCpu, Sel, &SelInfo);
557	else
558	rc = SELMR3GetShadowSelectorInfo(pVM, Sel, &SelInfo);
559	if (RT_FAILURE(rc))
560	{
561	RTStrPrintf(pszOutput, cbOutput, "Sel=%04x -> %Rrc\n", Sel, rc);
562	return rc;
563	}
564	}
565
566	/*
567	* Disassemble it.
568	*/
569	DBGFDISASSTATE State;
570	rc = dbgfR3DisasInstrFirst(pVM, pVCpu, &SelInfo, enmMode, GCPtr, fFlags, &State);
571	if (RT_FAILURE(rc))
572	{
573	if (State.Cpu.cbCachedInstr)
574	RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc; %.*Rhxs\n", rc, (size_t)State.Cpu.cbCachedInstr, State.Cpu.abInstr);
575	else
576	RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc\n", rc);
577	return rc;
578	}
579
580	/*
581	* Format it.
582	*/
583	char szBuf[512];
584	DISFormatYasmEx(&State.Cpu, szBuf, sizeof(szBuf),
585	DIS_FMT_FLAGS_RELATIVE_BRANCH,
586	fFlags & DBGF_DISAS_FLAGS_NO_SYMBOLS ? NULL : dbgfR3DisasGetSymbol,
587	&SelInfo);
588
589	#ifdef VBOX_WITH_RAW_MODE
590	/*
591	* Patched instruction annotations.
592	*/
593	char szPatchAnnotations[256];
594	szPatchAnnotations[0] = '\0';
595	if (fFlags & DBGF_DISAS_FLAGS_ANNOTATE_PATCHED)
596	PATMR3DbgAnnotatePatchedInstruction(pVM, GCPtr, State.Cpu.cbInstr, szPatchAnnotations, sizeof(szPatchAnnotations));
597	#endif
598
599	/*
600	* Print it to the user specified buffer.
601	*/
602	size_t cch;
603	if (fFlags & DBGF_DISAS_FLAGS_NO_BYTES)
604	{
605	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
606	cch = RTStrPrintf(pszOutput, cbOutput, "%s", szBuf);
607	else if (fRealModeAddress)
608	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %s", Sel, (unsigned)GCPtr, szBuf);
609	else if (Sel == DBGF_SEL_FLAT)
610	{
611	if (enmMode >= PGMMODE_AMD64)
612	cch = RTStrPrintf(pszOutput, cbOutput, "%RGv %s", GCPtr, szBuf);
613	else
614	cch = RTStrPrintf(pszOutput, cbOutput, "%08RX32 %s", (uint32_t)GCPtr, szBuf);
615	}
616	else
617	{
618	if (enmMode >= PGMMODE_AMD64)
619	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %s", Sel, GCPtr, szBuf);
620	else
621	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %s", Sel, (uint32_t)GCPtr, szBuf);
622	}
623	}
624	else
625	{
626	uint32_t cbInstr = State.Cpu.cbInstr;
627	uint8_t const *pabInstr = State.Cpu.abInstr;
628	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
629	cch = RTStrPrintf(pszOutput, cbOutput, "%.Rhxs%s %s",
630	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
631	szBuf);
632	else if (fRealModeAddress)
633	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %.Rhxs%s %s",
634	Sel, (unsigned)GCPtr,
635	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
636	szBuf);
637	else if (Sel == DBGF_SEL_FLAT)
638	{
639	if (enmMode >= PGMMODE_AMD64)
640	cch = RTStrPrintf(pszOutput, cbOutput, "%RGv %.Rhxs%s %s",
641	GCPtr,
642	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
643	szBuf);
644	else
645	cch = RTStrPrintf(pszOutput, cbOutput, "%08RX32 %.Rhxs%s %s",
646	(uint32_t)GCPtr,
647	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
648	szBuf);
649	}
650	else
651	{
652	if (enmMode >= PGMMODE_AMD64)
653	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %.Rhxs%s %s",
654	Sel, GCPtr,
655	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
656	szBuf);
657	else
658	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %.Rhxs%s %s",
659	Sel, (uint32_t)GCPtr,
660	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
661	szBuf);
662	}
663	}
664
665	#ifdef VBOX_WITH_RAW_MODE
666	if (szPatchAnnotations[0] && cch + 1 < cbOutput)
667	RTStrPrintf(pszOutput + cch, cbOutput - cch, " ; %s", szPatchAnnotations);
668	#endif
669
670	if (pcbInstr)
671	*pcbInstr = State.Cpu.cbInstr;
672
673	if (pDisState)
674	{
675	pDisState->pCurInstr = State.Cpu.pCurInstr;
676	pDisState->cbInstr = State.Cpu.cbInstr;
677	pDisState->Param1 = State.Cpu.Param1;
678	pDisState->Param2 = State.Cpu.Param2;
679	pDisState->Param3 = State.Cpu.Param3;
680	pDisState->Param4 = State.Cpu.Param4;
681	}
682
683	dbgfR3DisasInstrDone(&State);
684	return VINF_SUCCESS;
685	}
686
687
688	/**
689	* Disassembles the one instruction according to the specified flags and address
690	* returning part of the disassembler state.
691	*
692	* @returns VBox status code.
693	* @param pUVM The user mode VM handle.
694	* @param idCpu The ID of virtual CPU.
695	* @param pAddr The code address.
696	* @param fFlags Flags controlling where to start and how to format.
697	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
698	* @param pszOutput Output buffer. This will always be properly
699	* terminated if @a cbOutput is greater than zero.
700	* @param cbOutput Size of the output buffer.
701	* @param pDisState The disassembler state to fill in.
702	*
703	* @remarks May have to switch to the EMT of the virtual CPU in order to do
704	* address conversion.
705	*/
706	DECLHIDDEN(int) dbgfR3DisasInstrStateEx(PUVM pUVM, VMCPUID idCpu, PDBGFADDRESS pAddr, uint32_t fFlags,
707	char *pszOutput, uint32_t cbOutput, PDBGFDISSTATE pDisState)
708	{
709	AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
710	*pszOutput = '\0';
711	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
712	PVM pVM = pUVM->pVM;
713	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
714	AssertReturn(idCpu < pUVM->cCpus, VERR_INVALID_CPU_ID);
715	AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
716	AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
717
718	/*
719	* Optimize the common case where we're called on the EMT of idCpu since
720	* we're using this all the time when logging.
721	*/
722	int rc;
723	PVMCPU pVCpu = VMMGetCpu(pVM);
724	if ( pVCpu
725	&& pVCpu->idCpu == idCpu)
726	rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, pAddr->Sel, &pAddr->off, fFlags, pszOutput, cbOutput, NULL, pDisState);
727	else
728	rc = VMR3ReqPriorityCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 9,
729	pVM, VMMGetCpuById(pVM, idCpu), pAddr->Sel, &pAddr->off, fFlags, pszOutput, cbOutput, NULL, pDisState);
730	return rc;
731	}
732
733	/**
734	* Disassembles the one instruction according to the specified flags and address.
735	*
736	* @returns VBox status code.
737	* @param pUVM The user mode VM handle.
738	* @param idCpu The ID of virtual CPU.
739	* @param Sel The code selector. This used to determine the 32/16 bit ness and
740	* calculation of the actual instruction address.
741	* @param GCPtr The code address relative to the base of Sel.
742	* @param fFlags Flags controlling where to start and how to format.
743	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
744	* @param pszOutput Output buffer. This will always be properly
745	* terminated if @a cbOutput is greater than zero.
746	* @param cbOutput Size of the output buffer.
747	* @param pcbInstr Where to return the size of the instruction.
748	*
749	* @remarks May have to switch to the EMT of the virtual CPU in order to do
750	* address conversion.
751	*/
752	VMMR3DECL(int) DBGFR3DisasInstrEx(PUVM pUVM, VMCPUID idCpu, RTSEL Sel, RTGCPTR GCPtr, uint32_t fFlags,
753	char pszOutput, uint32_t cbOutput, uint32_t pcbInstr)
754	{
755	AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
756	*pszOutput = '\0';
757	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
758	PVM pVM = pUVM->pVM;
759	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
760	AssertReturn(idCpu < pUVM->cCpus, VERR_INVALID_CPU_ID);
761	AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
762	AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
763
764	/*
765	* Optimize the common case where we're called on the EMT of idCpu since
766	* we're using this all the time when logging.
767	*/
768	int rc;
769	PVMCPU pVCpu = VMMGetCpu(pVM);
770	if ( pVCpu
771	&& pVCpu->idCpu == idCpu)
772	rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr, NULL);
773	else
774	rc = VMR3ReqPriorityCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 9,
775	pVM, VMMGetCpuById(pVM, idCpu), Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr, NULL);
776	return rc;
777	}
778
779
780	/**
781	* Disassembles the current guest context instruction.
782	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
783	*
784	* @returns VBox status code.
785	* @param pVCpu The cross context virtual CPU structure.
786	* @param pszOutput Output buffer. This will always be properly
787	* terminated if @a cbOutput is greater than zero.
788	* @param cbOutput Size of the output buffer.
789	* @thread EMT(pVCpu)
790	*/
791	VMMR3_INT_DECL(int) DBGFR3DisasInstrCurrent(PVMCPU pVCpu, char *pszOutput, uint32_t cbOutput)
792	{
793	AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
794	*pszOutput = '\0';
795	Assert(VMCPU_IS_EMT(pVCpu));
796
797	RTGCPTR GCPtr = 0;
798	return dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, 0, &GCPtr,
799	DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_DEFAULT_MODE
800	\| DBGF_DISAS_FLAGS_ANNOTATE_PATCHED,
801	pszOutput, cbOutput, NULL, NULL);
802	}
803
804
805	/**
806	* Disassembles the current guest context instruction and writes it to the log.
807	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
808	*
809	* @returns VBox status code.
810	* @param pVCpu The cross context virtual CPU structure.
811	* @param pszPrefix Short prefix string to the disassembly string. (optional)
812	* @thread EMT(pVCpu)
813	*/
814	VMMR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVMCPU pVCpu, const char *pszPrefix)
815	{
816	char szBuf[256];
817	szBuf[0] = '\0';
818	int rc = DBGFR3DisasInstrCurrent(pVCpu, &szBuf[0], sizeof(szBuf));
819	if (RT_FAILURE(rc))
820	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrCurrentLog failed with rc=%Rrc\n", rc);
821	if (pszPrefix && *pszPrefix)
822	{
823	if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
824	RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
825	else
826	RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
827	}
828	else
829	RTLogPrintf("%s\n", szBuf);
830	return rc;
831	}
832
833
834
835	/**
836	* Disassembles the specified guest context instruction and writes it to the log.
837	* Addresses will be attempted resolved to symbols.
838	*
839	* @returns VBox status code.
840	* @param pVCpu The cross context virtual CPU structure of the calling
841	* EMT.
842	* @param Sel The code selector. This used to determine the 32/16
843	* bit-ness and calculation of the actual instruction
844	* address.
845	* @param GCPtr The code address relative to the base of Sel.
846	* @param pszPrefix Short prefix string to the disassembly string.
847	* (optional)
848	* @thread EMT(pVCpu)
849	*/
850	VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr, const char *pszPrefix)
851	{
852	Assert(VMCPU_IS_EMT(pVCpu));
853
854	char szBuf[256];
855	RTGCPTR GCPtrTmp = GCPtr;
856	int rc = dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, Sel, &GCPtrTmp, DBGF_DISAS_FLAGS_DEFAULT_MODE,
857	&szBuf[0], sizeof(szBuf), NULL, NULL);
858	if (RT_FAILURE(rc))
859	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrLog(, %RTsel, %RGv) failed with rc=%Rrc\n", Sel, GCPtr, rc);
860	if (pszPrefix && *pszPrefix)
861	{
862	if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
863	RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
864	else
865	RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
866	}
867	else
868	RTLogPrintf("%s\n", szBuf);
869	return rc;
870	}
871

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source: vbox/trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp@ 69300

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