CPUMR3Db.cpp@ 62639

Last change on this file since 62639 was 62478, checked in by vboxsync, 8 years ago
(C) 2016
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1	/* $Id: CPUMR3Db.cpp 62478 2016-07-22 18:29:06Z vboxsync $ */
2	/** @file
3	* CPUM - CPU database part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/mm.h>
27
28	#include <VBox/err.h>
29	#include <iprt/asm-amd64-x86.h>
30	#include <iprt/mem.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Structures and Typedefs *
36	*********************************************************************************************************************************/
37	typedef struct CPUMDBENTRY
38	{
39	/** The CPU name. */
40	const char *pszName;
41	/** The full CPU name. */
42	const char *pszFullName;
43	/** The CPU vendor (CPUMCPUVENDOR). */
44	uint8_t enmVendor;
45	/** The CPU family. */
46	uint8_t uFamily;
47	/** The CPU model. */
48	uint8_t uModel;
49	/** The CPU stepping. */
50	uint8_t uStepping;
51	/** The microarchitecture. */
52	CPUMMICROARCH enmMicroarch;
53	/** Scalable bus frequency used for reporting other frequencies. */
54	uint64_t uScalableBusFreq;
55	/** Flags - CPUDB_F_XXX. */
56	uint32_t fFlags;
57	/** The maximum physical address with of the CPU. This should correspond to
58	* the value in CPUID leaf 0x80000008 when present. */
59	uint8_t cMaxPhysAddrWidth;
60	/** Pointer to an array of CPUID leaves. */
61	PCCPUMCPUIDLEAF paCpuIdLeaves;
62	/** The number of CPUID leaves in the array paCpuIdLeaves points to. */
63	uint32_t cCpuIdLeaves;
64	/** The method used to deal with unknown CPUID leaves. */
65	CPUMUNKNOWNCPUID enmUnknownCpuId;
66	/** The default unknown CPUID value. */
67	CPUMCPUID DefUnknownCpuId;
68
69	/** MSR mask. Several microarchitectures ignore higher bits of the */
70	uint32_t fMsrMask;
71
72	/** The number of ranges in the table pointed to b paMsrRanges. */
73	uint32_t cMsrRanges;
74	/** MSR ranges for this CPU. */
75	PCCPUMMSRRANGE paMsrRanges;
76	} CPUMDBENTRY;
77
78
79	/*********************************************************************************************************************************
80	* Defined Constants And Macros *
81	*********************************************************************************************************************************/
82	/** @name CPUDB_F_XXX - CPUDBENTRY::fFlags
83	* @{ */
84	/** Should execute all in IEM.
85	* @todo Implement this - currently done in Main... */
86	#define CPUDB_F_EXECUTE_ALL_IN_IEM RT_BIT_32(0)
87	/** @} */
88
89
90	/** @def NULL_ALONE
91	* For eliminating an unnecessary data dependency in standalone builds (for
92	* VBoxSVC). */
93	/** @def ZERO_ALONE
94	* For eliminating an unnecessary data size dependency in standalone builds (for
95	* VBoxSVC). */
96	#ifndef CPUM_DB_STANDALONE
97	# define NULL_ALONE(a_aTable) a_aTable
98	# define ZERO_ALONE(a_cTable) a_cTable
99	#else
100	# define NULL_ALONE(a_aTable) NULL
101	# define ZERO_ALONE(a_cTable) 0
102	#endif
103
104
105	/** @name Short macros for the MSR range entries.
106	*
107	* These are rather cryptic, but this is to reduce the attack on the right
108	* margin.
109	*
110	* @{ */
111	/** Alias one MSR onto another (a_uTarget). */
112	#define MAL(a_uMsr, a_szName, a_uTarget) \
113	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
114	/** Functions handles everything. */
115	#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
116	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
117	/** Functions handles everything, with GP mask. */
118	#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
119	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
120	/** Function handlers, read-only. */
121	#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
122	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
123	/** Function handlers, ignore all writes. */
124	#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
125	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
126	/** Function handlers, with value. */
127	#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
128	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
129	/** Function handlers, with write ignore mask. */
130	#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
131	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
132	/** Function handlers, extended version. */
133	#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
134	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
135	/** Function handlers, with CPUMCPU storage variable. */
136	#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
137	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
138	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
139	/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
140	#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
141	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
142	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
143	/** Read-only fixed value. */
144	#define MVO(a_uMsr, a_szName, a_uValue) \
145	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
146	/** Read-only fixed value, ignores all writes. */
147	#define MVI(a_uMsr, a_szName, a_uValue) \
148	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
149	/** Read fixed value, ignore writes outside GP mask. */
150	#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
151	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
152	/** Read fixed value, extended version with both GP and ignore masks. */
153	#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
154	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
155	/** The short form, no CPUM backing. */
156	#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
157	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
158	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
159
160	/** Range: Functions handles everything. */
161	#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
162	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
163	/** Range: Read fixed value, read-only. */
164	#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
165	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
166	/** Range: Read fixed value, ignore writes. */
167	#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
168	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
169	/** Range: The short form, no CPUM backing. */
170	#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
171	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
172	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
173
174	/** Internal form used by the macros. */
175	#ifdef VBOX_WITH_STATISTICS
176	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
177	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
178	{ 0 }, { 0 }, { 0 }, { 0 } }
179	#else
180	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
181	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
182	#endif
183	/** @} */
184
185
186	#include "cpus/Intel_Core_i7_6700K.h"
187	#include "cpus/Intel_Core_i7_5600U.h"
188	#include "cpus/Intel_Core_i7_3960X.h"
189	#include "cpus/Intel_Core_i5_3570.h"
190	#include "cpus/Intel_Core_i7_2635QM.h"
191	#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
192	#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
193	#include "cpus/Intel_Pentium_4_3_00GHz.h"
194	#include "cpus/Intel_Pentium_N3530_2_16GHz.h"
195	#include "cpus/Intel_Atom_330_1_60GHz.h"
196	#include "cpus/Intel_80386.h"
197	#include "cpus/Intel_80286.h"
198	#include "cpus/Intel_80186.h"
199	#include "cpus/Intel_8086.h"
200
201	#include "cpus/AMD_FX_8150_Eight_Core.h"
202	#include "cpus/AMD_Phenom_II_X6_1100T.h"
203	#include "cpus/Quad_Core_AMD_Opteron_2384.h"
204	#include "cpus/AMD_Athlon_64_X2_Dual_Core_4200.h"
205	#include "cpus/AMD_Athlon_64_3200.h"
206
207	#include "cpus/VIA_QuadCore_L4700_1_2_GHz.h"
208
209
210
211	/**
212	* The database entries.
213	*
214	* 1. The first entry is special. It is the fallback for unknown
215	* processors. Thus, it better be pretty representative.
216	*
217	* 2. The first entry for a CPU vendor is likewise important as it is
218	* the default entry for that vendor.
219	*
220	* Generally we put the most recent CPUs first, since these tend to have the
221	* most complicated and backwards compatible list of MSRs.
222	*/
223	static CPUMDBENTRY const * const g_apCpumDbEntries[] =
224	{
225	#ifdef VBOX_CPUDB_Intel_Core_i7_6700K
226	&g_Entry_Intel_Core_i7_6700K,
227	#endif
228	#ifdef VBOX_CPUDB_Intel_Core_i7_5600U
229	&g_Entry_Intel_Core_i7_5600U,
230	#endif
231	#ifdef VBOX_CPUDB_Intel_Core_i5_3570
232	&g_Entry_Intel_Core_i5_3570,
233	#endif
234	#ifdef VBOX_CPUDB_Intel_Core_i7_3960X
235	&g_Entry_Intel_Core_i7_3960X,
236	#endif
237	#ifdef VBOX_CPUDB_Intel_Core_i7_2635QM
238	&g_Entry_Intel_Core_i7_2635QM,
239	#endif
240	#ifdef VBOX_CPUDB_Intel_Pentium_N3530_2_16GHz
241	&g_Entry_Intel_Pentium_N3530_2_16GHz,
242	#endif
243	#ifdef VBOX_CPUDB_Intel_Atom_330_1_60GHz
244	&g_Entry_Intel_Atom_330_1_60GHz,
245	#endif
246	#ifdef Intel_Pentium_M_processor_2_00GHz
247	&g_Entry_Intel_Pentium_M_processor_2_00GHz,
248	#endif
249	#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz
250	&g_Entry_Intel_Xeon_X5482_3_20GHz,
251	#endif
252	#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz
253	&g_Entry_Intel_Pentium_4_3_00GHz,
254	#endif
255	#ifdef VBOX_CPUDB_Intel_80486
256	&g_Entry_Intel_80486,
257	#endif
258	#ifdef VBOX_CPUDB_Intel_80386
259	&g_Entry_Intel_80386,
260	#endif
261	#ifdef VBOX_CPUDB_Intel_80286
262	&g_Entry_Intel_80286,
263	#endif
264	#ifdef VBOX_CPUDB_Intel_80186
265	&g_Entry_Intel_80186,
266	#endif
267	#ifdef VBOX_CPUDB_Intel_8086
268	&g_Entry_Intel_8086,
269	#endif
270
271	#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core
272	&g_Entry_AMD_FX_8150_Eight_Core,
273	#endif
274	#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T
275	&g_Entry_AMD_Phenom_II_X6_1100T,
276	#endif
277	#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384
278	&g_Entry_Quad_Core_AMD_Opteron_2384,
279	#endif
280	#ifdef VBOX_CPUDB_AMD_Athlon_64_X2_Dual_Core_4200
281	&g_Entry_AMD_Athlon_64_X2_Dual_Core_4200,
282	#endif
283	#ifdef VBOX_CPUDB_AMD_Athlon_64_3200
284	&g_Entry_AMD_Athlon_64_3200,
285	#endif
286
287	#ifdef VBOX_CPUDB_VIA_QuadCore_L4700_1_2_GHz
288	&g_Entry_VIA_QuadCore_L4700_1_2_GHz,
289	#endif
290
291	#ifdef VBOX_CPUDB_NEC_V20
292	&g_Entry_NEC_V20,
293	#endif
294	};
295
296
297	#ifndef CPUM_DB_STANDALONE
298
299	/**
300	* Binary search used by cpumR3MsrRangesInsert and has some special properties
301	* wrt to mismatches.
302	*
303	* @returns Insert location.
304	* @param paMsrRanges The MSR ranges to search.
305	* @param cMsrRanges The number of MSR ranges.
306	* @param uMsr What to search for.
307	*/
308	static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
309	{
310	if (!cMsrRanges)
311	return 0;
312
313	uint32_t iStart = 0;
314	uint32_t iLast = cMsrRanges - 1;
315	for (;;)
316	{
317	uint32_t i = iStart + (iLast - iStart + 1) / 2;
318	if ( uMsr >= paMsrRanges[i].uFirst
319	&& uMsr <= paMsrRanges[i].uLast)
320	return i;
321	if (uMsr < paMsrRanges[i].uFirst)
322	{
323	if (i <= iStart)
324	return i;
325	iLast = i - 1;
326	}
327	else
328	{
329	if (i >= iLast)
330	{
331	if (i < cMsrRanges)
332	i++;
333	return i;
334	}
335	iStart = i + 1;
336	}
337	}
338	}
339
340
341	/**
342	* Ensures that there is space for at least @a cNewRanges in the table,
343	* reallocating the table if necessary.
344	*
345	* @returns Pointer to the MSR ranges on success, NULL on failure. On failure
346	* @a *ppaMsrRanges is freed and set to NULL.
347	* @param pVM The cross context VM structure. If NULL,
348	* use the process heap, otherwise the VM's hyper heap.
349	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
350	* @param cMsrRanges The current number of ranges.
351	* @param cNewRanges The number of ranges to be added.
352	*/
353	static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
354	{
355	uint32_t cMsrRangesAllocated;
356	if (!pVM)
357	cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
358	else
359	{
360	/*
361	* We're using the hyper heap now, but when the range array was copied over to it from
362	* the host-context heap, we only copy the exact size and not the ensured size.
363	* See @bugref{7270}.
364	*/
365	cMsrRangesAllocated = cMsrRanges;
366	}
367	if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
368	{
369	void *pvNew;
370	uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
371	if (pVM)
372	{
373	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
374	Assert(cMsrRanges == pVM->cpum.s.GuestInfo.cMsrRanges);
375
376	size_t cb = cMsrRangesAllocated * sizeof(**ppaMsrRanges);
377	size_t cbNew = cNew * sizeof(**ppaMsrRanges);
378	int rc = MMR3HyperRealloc(pVM, *ppaMsrRanges, cb, 32, MM_TAG_CPUM_MSRS, cbNew, &pvNew);
379	if (RT_FAILURE(rc))
380	{
381	*ppaMsrRanges = NULL;
382	pVM->cpum.s.GuestInfo.paMsrRangesR0 = NIL_RTR0PTR;
383	pVM->cpum.s.GuestInfo.paMsrRangesRC = NIL_RTRCPTR;
384	LogRel(("CPUM: cpumR3MsrRangesEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
385	return NULL;
386	}
387	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
388	}
389	else
390	{
391	pvNew = RTMemRealloc(ppaMsrRanges, cNew sizeof(**ppaMsrRanges));
392	if (!pvNew)
393	{
394	RTMemFree(*ppaMsrRanges);
395	*ppaMsrRanges = NULL;
396	return NULL;
397	}
398	}
399	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
400	}
401
402	if (pVM)
403	{
404	/* Update R0 and RC pointers. */
405	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
406	pVM->cpum.s.GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, *ppaMsrRanges);
407	pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, *ppaMsrRanges);
408	}
409
410	return *ppaMsrRanges;
411	}
412
413
414	/**
415	* Inserts a new MSR range in into an sorted MSR range array.
416	*
417	* If the new MSR range overlaps existing ranges, the existing ones will be
418	* adjusted/removed to fit in the new one.
419	*
420	* @returns VBox status code.
421	* @retval VINF_SUCCESS
422	* @retval VERR_NO_MEMORY
423	*
424	* @param pVM The cross context VM structure. If NULL,
425	* use the process heap, otherwise the VM's hyper heap.
426	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
427	* Must be NULL if using the hyper heap.
428	* @param pcMsrRanges The variable holding number of ranges. Must be NULL
429	* if using the hyper heap.
430	* @param pNewRange The new range.
431	*/
432	int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange)
433	{
434	Assert(pNewRange->uLast >= pNewRange->uFirst);
435	Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
436	Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
437
438	/*
439	* Validate and use the VM's MSR ranges array if we are using the hyper heap.
440	*/
441	if (pVM)
442	{
443	AssertReturn(!ppaMsrRanges, VERR_INVALID_PARAMETER);
444	AssertReturn(!pcMsrRanges, VERR_INVALID_PARAMETER);
445
446	ppaMsrRanges = &pVM->cpum.s.GuestInfo.paMsrRangesR3;
447	pcMsrRanges = &pVM->cpum.s.GuestInfo.cMsrRanges;
448	}
449
450	uint32_t cMsrRanges = *pcMsrRanges;
451	PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
452
453	/*
454	* Optimize the linear insertion case where we add new entries at the end.
455	*/
456	if ( cMsrRanges > 0
457	&& paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
458	{
459	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
460	if (!paMsrRanges)
461	return VERR_NO_MEMORY;
462	paMsrRanges[cMsrRanges] = *pNewRange;
463	*pcMsrRanges += 1;
464	}
465	else
466	{
467	uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
468	Assert(i == cMsrRanges \|\| pNewRange->uFirst <= paMsrRanges[i].uLast);
469	Assert(i == 0 \|\| pNewRange->uFirst > paMsrRanges[i - 1].uLast);
470
471	/*
472	* Adding an entirely new entry?
473	*/
474	if ( i >= cMsrRanges
475	\|\| pNewRange->uLast < paMsrRanges[i].uFirst)
476	{
477	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
478	if (!paMsrRanges)
479	return VERR_NO_MEMORY;
480	if (i < cMsrRanges)
481	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
482	paMsrRanges[i] = *pNewRange;
483	*pcMsrRanges += 1;
484	}
485	/*
486	* Replace existing entry?
487	*/
488	else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
489	&& pNewRange->uLast == paMsrRanges[i].uLast)
490	paMsrRanges[i] = *pNewRange;
491	/*
492	* Splitting an existing entry?
493	*/
494	else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
495	&& pNewRange->uLast < paMsrRanges[i].uLast)
496	{
497	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 2);
498	if (!paMsrRanges)
499	return VERR_NO_MEMORY;
500	if (i < cMsrRanges)
501	memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
502	paMsrRanges[i + 1] = *pNewRange;
503	paMsrRanges[i + 2] = paMsrRanges[i];
504	paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
505	paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
506	*pcMsrRanges += 2;
507	}
508	/*
509	* Complicated scenarios that can affect more than one range.
510	*
511	* The current code does not optimize memmove calls when replacing
512	* one or more existing ranges, because it's tedious to deal with and
513	* not expected to be a frequent usage scenario.
514	*/
515	else
516	{
517	/* Adjust start of first match? */
518	if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
519	&& pNewRange->uLast < paMsrRanges[i].uLast)
520	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
521	else
522	{
523	/* Adjust end of first match? */
524	if (pNewRange->uFirst > paMsrRanges[i].uFirst)
525	{
526	Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
527	paMsrRanges[i].uLast = pNewRange->uFirst - 1;
528	i++;
529	}
530	/* Replace the whole first match (lazy bird). */
531	else
532	{
533	if (i + 1 < cMsrRanges)
534	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
535	cMsrRanges = *pcMsrRanges -= 1;
536	}
537
538	/* Do the new range affect more ranges? */
539	while ( i < cMsrRanges
540	&& pNewRange->uLast >= paMsrRanges[i].uFirst)
541	{
542	if (pNewRange->uLast < paMsrRanges[i].uLast)
543	{
544	/* Adjust the start of it, then we're done. */
545	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
546	break;
547	}
548
549	/* Remove it entirely. */
550	if (i + 1 < cMsrRanges)
551	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
552	cMsrRanges = *pcMsrRanges -= 1;
553	}
554	}
555
556	/* Now, perform a normal insertion. */
557	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
558	if (!paMsrRanges)
559	return VERR_NO_MEMORY;
560	if (i < cMsrRanges)
561	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
562	paMsrRanges[i] = *pNewRange;
563	*pcMsrRanges += 1;
564	}
565	}
566
567	return VINF_SUCCESS;
568	}
569
570
571	/**
572	* Worker for cpumR3MsrApplyFudge that applies one table.
573	*
574	* @returns VBox status code.
575	* @param pVM The cross context VM structure.
576	* @param paRanges Array of MSRs to fudge.
577	* @param cRanges Number of MSRs in the array.
578	*/
579	static int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
580	{
581	for (uint32_t i = 0; i < cRanges; i++)
582	if (!cpumLookupMsrRange(pVM, paRanges[i].uFirst))
583	{
584	LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
585	int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
586	&paRanges[i]);
587	if (RT_FAILURE(rc))
588	return rc;
589	}
590	return VINF_SUCCESS;
591	}
592
593
594	/**
595	* Fudges the MSRs that guest are known to access in some odd cases.
596	*
597	* A typical example is a VM that has been moved between different hosts where
598	* for instance the cpu vendor differs.
599	*
600	* Another example is older CPU profiles (e.g. Atom Bonnet) for newer CPUs (e.g.
601	* Atom Silvermont), where features reported thru CPUID aren't present in the
602	* MSRs (e.g. AMD64_TSC_AUX).
603	*
604	*
605	* @returns VBox status code.
606	* @param pVM The cross context VM structure.
607	*/
608	int cpumR3MsrApplyFudge(PVM pVM)
609	{
610	/*
611	* Basic.
612	*/
613	static CPUMMSRRANGE const s_aFudgeMsrs[] =
614	{
615	MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
616	MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
617	MVO(0x00000017, "IA32_PLATFORM_ID", 0),
618	MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
619	MVI(0x0000008b, "BIOS_SIGN", 0),
620	MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
621	MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
622	MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
623	MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
624	MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
625	MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
626	MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
627	MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
628	MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
629	MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
630	MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
631	MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
632	};
633	int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
634	AssertLogRelRCReturn(rc, rc);
635
636	/*
637	* XP might mistake opterons and other newer CPUs for P4s.
638	*/
639	if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
640	{
641	static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
642	{
643	MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
644	};
645	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
646	AssertLogRelRCReturn(rc, rc);
647	}
648
649	if (pVM->cpum.s.GuestFeatures.fRdTscP)
650	{
651	static CPUMMSRRANGE const s_aRdTscPFudgeMsrs[] =
652	{
653	MFX(0xc0000103, "AMD64_TSC_AUX", Amd64TscAux, Amd64TscAux, 0, 0, ~(uint64_t)UINT32_MAX),
654	};
655	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aRdTscPFudgeMsrs[0], RT_ELEMENTS(s_aRdTscPFudgeMsrs));
656	AssertLogRelRCReturn(rc, rc);
657	}
658
659	return rc;
660	}
661
662
663	/**
664	* Do we consider @a enmConsider a better match for @a enmTarget than
665	* @a enmFound?
666	*
667	* Only called when @a enmConsider isn't exactly what we're looking for.
668	*
669	* @returns true/false.
670	* @param enmConsider The new microarch to consider.
671	* @param enmTarget The target microarch.
672	* @param enmFound The best microarch match we've found thus far.
673	*/
674	DECLINLINE(bool) cpumR3DbIsBetterMarchMatch(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
675	{
676	Assert(enmConsider != enmTarget);
677
678	/*
679	* If we've got an march match, don't bother with enmConsider.
680	*/
681	if (enmFound == enmTarget)
682	return false;
683
684	/*
685	* Found is below: Pick 'consider' if it's closer to the target or above it.
686	*/
687	if (enmFound < enmTarget)
688	return enmConsider > enmFound;
689
690	/*
691	* Found is above: Pick 'consider' if it's also above (paranoia: or equal)
692	* and but closer to the target.
693	*/
694	return enmConsider >= enmTarget && enmConsider < enmFound;
695	}
696
697
698	/**
699	* Do we consider @a enmConsider a better match for @a enmTarget than
700	* @a enmFound?
701	*
702	* Only called for intel family 06h CPUs.
703	*
704	* @returns true/false.
705	* @param enmConsider The new microarch to consider.
706	* @param enmTarget The target microarch.
707	* @param enmFound The best microarch match we've found thus far.
708	*/
709	static bool cpumR3DbIsBetterIntelFam06Match(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
710	{
711	/* Check intel family 06h claims. */
712	AssertReturn(enmConsider >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmConsider <= kCpumMicroarch_Intel_P6_Core_Atom_End,
713	false);
714	AssertReturn(enmTarget >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmTarget <= kCpumMicroarch_Intel_P6_Core_Atom_End,
715	false);
716
717	/* Put matches out of the way. */
718	if (enmConsider == enmTarget)
719	return true;
720	if (enmFound == enmTarget)
721	return false;
722
723	/* If found isn't a family 06h march, whatever we're considering must be a better choice. */
724	if ( enmFound < kCpumMicroarch_Intel_P6_Core_Atom_First
725	\|\| enmFound > kCpumMicroarch_Intel_P6_Core_Atom_End)
726	return true;
727
728	/*
729	* The family 06h stuff is split into three categories:
730	* - Common P6 heritage
731	* - Core
732	* - Atom
733	*
734	* Determin which of the three arguments are Atom marchs, because that's
735	* all we need to make the right choice.
736	*/
737	bool const fConsiderAtom = enmConsider >= kCpumMicroarch_Intel_Atom_First;
738	bool const fTargetAtom = enmTarget >= kCpumMicroarch_Intel_Atom_First;
739	bool const fFoundAtom = enmFound >= kCpumMicroarch_Intel_Atom_First;
740
741	/*
742	* Want atom:
743	*/
744	if (fTargetAtom)
745	{
746	/* Pick the atom if we've got one of each.*/
747	if (fConsiderAtom != fFoundAtom)
748	return fConsiderAtom;
749	/* If we haven't got any atoms under consideration, pick a P6 or the earlier core.
750	Note! Not entirely sure Dothan is the best choice, but it'll do for now. */
751	if (!fConsiderAtom)
752	{
753	if (enmConsider > enmFound)
754	return enmConsider <= kCpumMicroarch_Intel_P6_M_Dothan;
755	return enmFound > kCpumMicroarch_Intel_P6_M_Dothan;
756	}
757	/* else: same category, default comparison rules. */
758	Assert(fConsiderAtom && fFoundAtom);
759	}
760	/*
761	* Want non-atom:
762	*/
763	/* Pick the non-atom if we've got one of each. */
764	else if (fConsiderAtom != fFoundAtom)
765	return fFoundAtom;
766	/* If we've only got atoms under consideration, pick the older one just to pick something. */
767	else if (fConsiderAtom)
768	return enmConsider < enmFound;
769	else
770	Assert(!fConsiderAtom && !fFoundAtom);
771
772	/*
773	* Same basic category. Do same compare as caller.
774	*/
775	return cpumR3DbIsBetterMarchMatch(enmConsider, enmTarget, enmFound);
776	}
777
778
779	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
780	{
781	CPUMDBENTRY const *pEntry = NULL;
782	int rc;
783
784	if (!strcmp(pszName, "host"))
785	{
786	/*
787	* Create a CPU database entry for the host CPU. This means getting
788	* the CPUID bits from the real CPU and grabbing the closest matching
789	* database entry for MSRs.
790	*/
791	rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
792	if (RT_FAILURE(rc))
793	return rc;
794	rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
795	if (RT_FAILURE(rc))
796	return rc;
797
798	/* Lookup database entry for MSRs. */
799	CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
800	pInfo->paCpuIdLeavesR3[0].uEbx,
801	pInfo->paCpuIdLeavesR3[0].uEcx,
802	pInfo->paCpuIdLeavesR3[0].uEdx);
803	uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
804	uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
805	uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
806	uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
807	CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
808
809	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
810	{
811	CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
812	if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
813	{
814	/* Match against Family, Microarch, model and stepping. Except
815	for family, always match the closer with preference given to
816	the later/older ones. */
817	if (pCur->uFamily == uFamily)
818	{
819	if (pCur->enmMicroarch == enmMicroarch)
820	{
821	if (pCur->uModel == uModel)
822	{
823	if (pCur->uStepping == uStepping)
824	{
825	/* Perfect match. */
826	pEntry = pCur;
827	break;
828	}
829
830	if ( !pEntry
831	\|\| pEntry->uModel != uModel
832	\|\| pEntry->enmMicroarch != enmMicroarch
833	\|\| pEntry->uFamily != uFamily)
834	pEntry = pCur;
835	else if ( pCur->uStepping >= uStepping
836	? pCur->uStepping < pEntry->uStepping \|\| pEntry->uStepping < uStepping
837	: pCur->uStepping > pEntry->uStepping)
838	pEntry = pCur;
839	}
840	else if ( !pEntry
841	\|\| pEntry->enmMicroarch != enmMicroarch
842	\|\| pEntry->uFamily != uFamily)
843	pEntry = pCur;
844	else if ( pCur->uModel >= uModel
845	? pCur->uModel < pEntry->uModel \|\| pEntry->uModel < uModel
846	: pCur->uModel > pEntry->uModel)
847	pEntry = pCur;
848	}
849	else if ( !pEntry
850	\|\| pEntry->uFamily != uFamily)
851	pEntry = pCur;
852	/* Special march matching rules applies to intel family 06h. */
853	else if ( enmVendor == CPUMCPUVENDOR_INTEL
854	&& uFamily == 6
855	? cpumR3DbIsBetterIntelFam06Match(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch)
856	: cpumR3DbIsBetterMarchMatch(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch))
857	pEntry = pCur;
858	}
859	/* We don't do closeness matching on family, we use the first
860	entry for the CPU vendor instead. (P4 workaround.) */
861	else if (!pEntry)
862	pEntry = pCur;
863	}
864	}
865
866	if (pEntry)
867	LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
868	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
869	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
870	pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
871	else
872	{
873	pEntry = g_apCpumDbEntries[0];
874	LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'\n",
875	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
876	pEntry->pszName));
877	}
878	}
879	else
880	{
881	/*
882	* We're supposed to be emulating a specific CPU that is included in
883	* our CPU database. The CPUID tables needs to be copied onto the
884	* heap so the caller can modify them and so they can be freed like
885	* in the host case above.
886	*/
887	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
888	if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
889	{
890	pEntry = g_apCpumDbEntries[i];
891	break;
892	}
893	if (!pEntry)
894	{
895	LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
896	return VERR_CPUM_DB_CPU_NOT_FOUND;
897	}
898
899	pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
900	if (pEntry->cCpuIdLeaves)
901	{
902	/* Must allocate a multiple of 16 here, matching cpumR3CpuIdEnsureSpace. */
903	size_t cbExtra = sizeof(pEntry->paCpuIdLeaves[0]) * (RT_ALIGN(pEntry->cCpuIdLeaves, 16) - pEntry->cCpuIdLeaves);
904	pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDupEx(pEntry->paCpuIdLeaves,
905	sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves,
906	cbExtra);
907	if (!pInfo->paCpuIdLeavesR3)
908	return VERR_NO_MEMORY;
909	}
910	else
911	pInfo->paCpuIdLeavesR3 = NULL;
912
913	pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
914	pInfo->DefCpuId = pEntry->DefUnknownCpuId;
915
916	LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
917	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
918	pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
919	}
920
921	pInfo->fMsrMask = pEntry->fMsrMask;
922	pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
923	pInfo->uPadding = 0;
924	pInfo->uScalableBusFreq = pEntry->uScalableBusFreq;
925	pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
926	pInfo->paMsrRangesR0 = NIL_RTR0PTR;
927	pInfo->paCpuIdLeavesRC = NIL_RTRCPTR;
928	pInfo->paMsrRangesRC = NIL_RTRCPTR;
929
930	/*
931	* Copy the MSR range.
932	*/
933	uint32_t cMsrs = 0;
934	PCPUMMSRRANGE paMsrs = NULL;
935
936	PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
937	uint32_t cLeft = pEntry->cMsrRanges;
938	while (cLeft-- > 0)
939	{
940	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &paMsrs, &cMsrs, pCurMsr);
941	if (RT_FAILURE(rc))
942	{
943	Assert(!paMsrs); /* The above function frees this. */
944	RTMemFree(pInfo->paCpuIdLeavesR3);
945	pInfo->paCpuIdLeavesR3 = NULL;
946	return rc;
947	}
948	pCurMsr++;
949	}
950
951	pInfo->paMsrRangesR3 = paMsrs;
952	pInfo->cMsrRanges = cMsrs;
953	return VINF_SUCCESS;
954	}
955
956
957	/**
958	* Insert an MSR range into the VM.
959	*
960	* If the new MSR range overlaps existing ranges, the existing ones will be
961	* adjusted/removed to fit in the new one.
962	*
963	* @returns VBox status code.
964	* @param pVM The cross context VM structure.
965	* @param pNewRange Pointer to the MSR range being inserted.
966	*/
967	VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange)
968	{
969	AssertReturn(pVM, VERR_INVALID_PARAMETER);
970	AssertReturn(pNewRange, VERR_INVALID_PARAMETER);
971
972	return cpumR3MsrRangesInsert(pVM, NULL /* ppaMsrRanges /, NULL / pcMsrRanges */, pNewRange);
973	}
974
975
976	/**
977	* Register statistics for the MSRs.
978	*
979	* This must not be called before the MSRs have been finalized and moved to the
980	* hyper heap.
981	*
982	* @returns VBox status code.
983	* @param pVM The cross context VM structure.
984	*/
985	int cpumR3MsrRegStats(PVM pVM)
986	{
987	/*
988	* Global statistics.
989	*/
990	PCPUM pCpum = &pVM->cpum.s;
991	STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
992	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
993	STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
994	STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
995	STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
996	STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
997	STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
998	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
999	STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
1000	STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
1001	STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
1002	STAMUNIT_OCCURENCES, "Writing of ignored bits.");
1003	STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
1004	STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
1005
1006
1007	# ifdef VBOX_WITH_STATISTICS
1008	/*
1009	* Per range.
1010	*/
1011	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
1012	uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
1013	for (uint32_t i = 0; i < cRanges; i++)
1014	{
1015	char szName[160];
1016	ssize_t cchName;
1017
1018	if (paRanges[i].uFirst == paRanges[i].uLast)
1019	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
1020	paRanges[i].uFirst, paRanges[i].szName);
1021	else
1022	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
1023	paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
1024
1025	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
1026	STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
1027
1028	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
1029	STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
1030
1031	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
1032	STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
1033
1034	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
1035	STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
1036	}
1037	# endif /* VBOX_WITH_STATISTICS */
1038
1039	return VINF_SUCCESS;
1040	}
1041
1042	#endif /* !CPUM_DB_STANDALONE */
1043

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 62639

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