CPUMR3CpuId.cpp@ 94961

Last change on this file since 94961 was 94931, checked in by vboxsync, 3 years ago
VMM/CPUM: Introduced a global variable g_CpumHostFeatures for keeping the host CPU features. This is safer than keeping this info in the shared part of the VM structure. bugref:10093
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File size: 271.6 KB

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1	/* $Id: CPUMR3CpuId.cpp 94931 2022-05-09 08:24:47Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vmcc.h>
30	#include <VBox/sup.h>
31
32	#include <VBox/err.h>
33	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
34	# include <iprt/asm-amd64-x86.h>
35	#endif
36	#include <iprt/ctype.h>
37	#include <iprt/mem.h>
38	#include <iprt/string.h>
39	#include <iprt/x86-helpers.h>
40
41
42	/*********************************************************************************************************************************
43	* Defined Constants And Macros *
44	*********************************************************************************************************************************/
45	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
46	#define CPUM_CPUID_MAX_LEAVES 2048
47
48
49	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
50	/**
51	* Determins the host CPU MXCSR mask.
52	*
53	* @returns MXCSR mask.
54	*/
55	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
56	{
57	if ( ASMHasCpuId()
58	&& RTX86IsValidStdRange(ASMCpuId_EAX(0))
59	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
60	{
61	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
62	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
63	RT_ZERO(*pState);
64	ASMFxSave(pState);
65	if (pState->MXCSR_MASK == 0)
66	return 0xffbf;
67	return pState->MXCSR_MASK;
68	}
69	return 0;
70	}
71	#endif
72
73
74
75	#ifndef IN_VBOX_CPU_REPORT
76	/**
77	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
78	*
79	* @returns true if found, false it not.
80	* @param paLeaves The CPUID leaves to search. This is sorted.
81	* @param cLeaves The number of leaves in the array.
82	* @param uLeaf The leaf to locate.
83	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
84	* @param pLegacy The legacy output leaf.
85	*/
86	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
87	PCPUMCPUID pLegacy)
88	{
89	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, uLeaf, uSubLeaf);
90	if (pLeaf)
91	{
92	pLegacy->uEax = pLeaf->uEax;
93	pLegacy->uEbx = pLeaf->uEbx;
94	pLegacy->uEcx = pLeaf->uEcx;
95	pLegacy->uEdx = pLeaf->uEdx;
96	return true;
97	}
98	return false;
99	}
100	#endif /* IN_VBOX_CPU_REPORT */
101
102
103	/**
104	* Inserts a CPU ID leaf, replacing any existing ones.
105	*
106	* When inserting a simple leaf where we already got a series of sub-leaves with
107	* the same leaf number (eax), the simple leaf will replace the whole series.
108	*
109	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
110	* host-context heap and has only been allocated/reallocated by the
111	* cpumCpuIdEnsureSpace function.
112	*
113	* @returns VBox status code.
114	* @param pVM The cross context VM structure. If NULL, use
115	* the process heap, otherwise the VM's hyper heap.
116	* @param ppaLeaves Pointer to the pointer to the array of sorted
117	* CPUID leaves and sub-leaves. Must be NULL if using
118	* the hyper heap.
119	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
120	* be NULL if using the hyper heap.
121	* @param pNewLeaf Pointer to the data of the new leaf we're about to
122	* insert.
123	*/
124	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
125	{
126	/*
127	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
128	*/
129	if (pVM)
130	{
131	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
132	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
133	AssertReturn(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 == pVM->cpum.s.GuestInfo.aCpuIdLeaves, VERR_INVALID_PARAMETER);
134
135	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
136	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
137	}
138
139	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
140	uint32_t cLeaves = *pcLeaves;
141
142	/*
143	* Validate the new leaf a little.
144	*/
145	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
146	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
147	VERR_INVALID_FLAGS);
148	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
149	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
150	VERR_INVALID_PARAMETER);
151	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
152	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
153	VERR_INVALID_PARAMETER);
154	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
155	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
156	VERR_INVALID_PARAMETER);
157
158	/*
159	* Find insertion point. The lazy bird uses the same excuse as in
160	* cpumCpuIdGetLeaf(), but optimizes for linear insertion (saved state).
161	*/
162	uint32_t i;
163	if ( cLeaves > 0
164	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
165	{
166	/* Add at end. */
167	i = cLeaves;
168	}
169	else if ( cLeaves > 0
170	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
171	{
172	/* Either replacing the last leaf or dealing with sub-leaves. Spool
173	back to the first sub-leaf to pretend we did the linear search. */
174	i = cLeaves - 1;
175	while ( i > 0
176	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
177	i--;
178	}
179	else
180	{
181	/* Linear search from the start. */
182	i = 0;
183	while ( i < cLeaves
184	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
185	i++;
186	}
187	if ( i < cLeaves
188	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
189	{
190	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
191	{
192	/*
193	* The sub-leaf mask differs, replace all existing leaves with the
194	* same leaf number.
195	*/
196	uint32_t c = 1;
197	while ( i + c < cLeaves
198	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
199	c++;
200	if (c > 1 && i + c < cLeaves)
201	{
202	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
203	*pcLeaves = cLeaves -= c - 1;
204	}
205
206	paLeaves[i] = *pNewLeaf;
207	#ifdef VBOX_STRICT
208	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
209	#endif
210	return VINF_SUCCESS;
211	}
212
213	/* Find sub-leaf insertion point. */
214	while ( i < cLeaves
215	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
216	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
217	i++;
218
219	/*
220	* If we've got an exactly matching leaf, replace it.
221	*/
222	if ( i < cLeaves
223	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
224	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
225	{
226	paLeaves[i] = *pNewLeaf;
227	#ifdef VBOX_STRICT
228	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
229	#endif
230	return VINF_SUCCESS;
231	}
232	}
233
234	/*
235	* Adding a new leaf at 'i'.
236	*/
237	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
238	paLeaves = cpumCpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
239	if (!paLeaves)
240	return VERR_NO_MEMORY;
241
242	if (i < cLeaves)
243	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
244	*pcLeaves += 1;
245	paLeaves[i] = *pNewLeaf;
246
247	#ifdef VBOX_STRICT
248	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
249	#endif
250	return VINF_SUCCESS;
251	}
252
253
254	#ifndef IN_VBOX_CPU_REPORT
255	/**
256	* Removes a range of CPUID leaves.
257	*
258	* This will not reallocate the array.
259	*
260	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
261	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
262	* @param uFirst The first leaf.
263	* @param uLast The last leaf.
264	*/
265	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
266	{
267	uint32_t cLeaves = *pcLeaves;
268
269	Assert(uFirst <= uLast);
270
271	/*
272	* Find the first one.
273	*/
274	uint32_t iFirst = 0;
275	while ( iFirst < cLeaves
276	&& paLeaves[iFirst].uLeaf < uFirst)
277	iFirst++;
278
279	/*
280	* Find the end (last + 1).
281	*/
282	uint32_t iEnd = iFirst;
283	while ( iEnd < cLeaves
284	&& paLeaves[iEnd].uLeaf <= uLast)
285	iEnd++;
286
287	/*
288	* Adjust the array if anything needs removing.
289	*/
290	if (iFirst < iEnd)
291	{
292	if (iEnd < cLeaves)
293	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
294	*pcLeaves = cLeaves -= (iEnd - iFirst);
295	}
296
297	# ifdef VBOX_STRICT
298	cpumCpuIdAssertOrder(paLeaves, *pcLeaves);
299	# endif
300	}
301	#endif /* IN_VBOX_CPU_REPORT */
302
303
304	/**
305	* Gets a CPU ID leaf.
306	*
307	* @returns VBox status code.
308	* @param pVM The cross context VM structure.
309	* @param pLeaf Where to store the found leaf.
310	* @param uLeaf The leaf to locate.
311	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
312	*/
313	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
314	{
315	PCPUMCPUIDLEAF pcLeaf = cpumCpuIdGetLeafInt(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
316	uLeaf, uSubLeaf);
317	if (pcLeaf)
318	{
319	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
320	return VINF_SUCCESS;
321	}
322
323	return VERR_NOT_FOUND;
324	}
325
326
327	/**
328	* Gets all the leaves.
329	*
330	* This only works after the CPUID leaves have been initialized. The interface
331	* is intended for NEM and configuring CPUID leaves for the native hypervisor.
332	*
333	* @returns Pointer to the array of leaves. NULL on failure.
334	* @param pVM The cross context VM structure.
335	* @param pcLeaves Where to return the number of leaves.
336	*/
337	VMMR3_INT_DECL(PCCPUMCPUIDLEAF) CPUMR3CpuIdGetPtr(PVM pVM, uint32_t *pcLeaves)
338	{
339	*pcLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
340	return pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
341	}
342
343
344	/**
345	* Inserts a CPU ID leaf, replacing any existing ones.
346	*
347	* @returns VBox status code.
348	* @param pVM The cross context VM structure.
349	* @param pNewLeaf Pointer to the leaf being inserted.
350	*/
351	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
352	{
353	/*
354	* Validate parameters.
355	*/
356	AssertReturn(pVM, VERR_INVALID_PARAMETER);
357	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
358
359	/*
360	* Disallow replacing CPU ID leaves that this API currently cannot manage.
361	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
362	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
363	*/
364	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
365	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
366	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
367	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
368	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
369	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
370	{
371	return VERR_NOT_SUPPORTED;
372	}
373
374	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
375	}
376
377
378	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
379	/**
380	* Determines the method the CPU uses to handle unknown CPUID leaves.
381	*
382	* @returns VBox status code.
383	* @param penmUnknownMethod Where to return the method.
384	* @param pDefUnknown Where to return default unknown values. This
385	* will be set, even if the resulting method
386	* doesn't actually needs it.
387	*/
388	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
389	{
390	uint32_t uLastStd = ASMCpuId_EAX(0);
391	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
392	if (!RTX86IsValidExtRange(uLastExt))
393	uLastExt = 0x80000000;
394
395	uint32_t auChecks[] =
396	{
397	uLastStd + 1,
398	uLastStd + 5,
399	uLastStd + 8,
400	uLastStd + 32,
401	uLastStd + 251,
402	uLastExt + 1,
403	uLastExt + 8,
404	uLastExt + 15,
405	uLastExt + 63,
406	uLastExt + 255,
407	0x7fbbffcc,
408	0x833f7872,
409	0xefff2353,
410	0x35779456,
411	0x1ef6d33e,
412	};
413
414	static const uint32_t s_auValues[] =
415	{
416	0xa95d2156,
417	0x00000001,
418	0x00000002,
419	0x00000008,
420	0x00000000,
421	0x55773399,
422	0x93401769,
423	0x12039587,
424	};
425
426	/*
427	* Simple method, all zeros.
428	*/
429	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
430	pDefUnknown->uEax = 0;
431	pDefUnknown->uEbx = 0;
432	pDefUnknown->uEcx = 0;
433	pDefUnknown->uEdx = 0;
434
435	/*
436	* Intel has been observed returning the last standard leaf.
437	*/
438	uint32_t auLast[4];
439	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
440
441	uint32_t cChecks = RT_ELEMENTS(auChecks);
442	while (cChecks > 0)
443	{
444	uint32_t auCur[4];
445	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
446	if (memcmp(auCur, auLast, sizeof(auCur)))
447	break;
448	cChecks--;
449	}
450	if (cChecks == 0)
451	{
452	/* Now, what happens when the input changes? Esp. ECX. */
453	uint32_t cTotal = 0;
454	uint32_t cSame = 0;
455	uint32_t cLastWithEcx = 0;
456	uint32_t cNeither = 0;
457	uint32_t cValues = RT_ELEMENTS(s_auValues);
458	while (cValues > 0)
459	{
460	uint32_t uValue = s_auValues[cValues - 1];
461	uint32_t auLastWithEcx[4];
462	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
463	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
464
465	cChecks = RT_ELEMENTS(auChecks);
466	while (cChecks > 0)
467	{
468	uint32_t auCur[4];
469	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
470	if (!memcmp(auCur, auLast, sizeof(auCur)))
471	{
472	cSame++;
473	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
474	cLastWithEcx++;
475	}
476	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
477	cLastWithEcx++;
478	else
479	cNeither++;
480	cTotal++;
481	cChecks--;
482	}
483	cValues--;
484	}
485
486	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
487	if (cSame == cTotal)
488	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
489	else if (cLastWithEcx == cTotal)
490	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
491	else
492	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
493	pDefUnknown->uEax = auLast[0];
494	pDefUnknown->uEbx = auLast[1];
495	pDefUnknown->uEcx = auLast[2];
496	pDefUnknown->uEdx = auLast[3];
497	return VINF_SUCCESS;
498	}
499
500	/*
501	* Unchanged register values?
502	*/
503	cChecks = RT_ELEMENTS(auChecks);
504	while (cChecks > 0)
505	{
506	uint32_t const uLeaf = auChecks[cChecks - 1];
507	uint32_t cValues = RT_ELEMENTS(s_auValues);
508	while (cValues > 0)
509	{
510	uint32_t uValue = s_auValues[cValues - 1];
511	uint32_t auCur[4];
512	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
513	if ( auCur[0] != uLeaf
514	\|\| auCur[1] != uValue
515	\|\| auCur[2] != uValue
516	\|\| auCur[3] != uValue)
517	break;
518	cValues--;
519	}
520	if (cValues != 0)
521	break;
522	cChecks--;
523	}
524	if (cChecks == 0)
525	{
526	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
527	return VINF_SUCCESS;
528	}
529
530	/*
531	* Just go with the simple method.
532	*/
533	return VINF_SUCCESS;
534	}
535	#endif /* RT_ARCH_X86 \|\| RT_ARCH_AMD64 */
536
537
538	/**
539	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
540	*
541	* @returns Read only name string.
542	* @param enmUnknownMethod The method to translate.
543	*/
544	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
545	{
546	switch (enmUnknownMethod)
547	{
548	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
549	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
550	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
551	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
552
553	case CPUMUNKNOWNCPUID_INVALID:
554	case CPUMUNKNOWNCPUID_END:
555	case CPUMUNKNOWNCPUID_32BIT_HACK:
556	break;
557	}
558	return "Invalid-unknown-CPUID-method";
559	}
560
561
562	/*
563	*
564	* Init related code.
565	* Init related code.
566	* Init related code.
567	*
568	*
569	*/
570	#ifndef IN_VBOX_CPU_REPORT
571
572
573	/**
574	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
575	*
576	* This ignores the fSubLeafMask.
577	*
578	* @returns Pointer to the matching leaf, or NULL if not found.
579	* @param pCpum The CPUM instance data.
580	* @param uLeaf The leaf to locate.
581	* @param uSubLeaf The subleaf to locate.
582	*/
583	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
584	{
585	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
586	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
587	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
588	if (iEnd)
589	{
590	uint32_t iBegin = 0;
591	for (;;)
592	{
593	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
594	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
595	if (uNeedle < uCur)
596	{
597	if (i > iBegin)
598	iEnd = i;
599	else
600	break;
601	}
602	else if (uNeedle > uCur)
603	{
604	if (i + 1 < iEnd)
605	iBegin = i + 1;
606	else
607	break;
608	}
609	else
610	return &paLeaves[i];
611	}
612	}
613	return NULL;
614	}
615
616
617	/**
618	* Loads MSR range overrides.
619	*
620	* This must be called before the MSR ranges are moved from the normal heap to
621	* the hyper heap!
622	*
623	* @returns VBox status code (VMSetError called).
624	* @param pVM The cross context VM structure.
625	* @param pMsrNode The CFGM node with the MSR overrides.
626	*/
627	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
628	{
629	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
630	{
631	/*
632	* Assemble a valid MSR range.
633	*/
634	CPUMMSRRANGE MsrRange;
635	MsrRange.offCpumCpu = 0;
636	MsrRange.fReserved = 0;
637
638	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
639	if (RT_FAILURE(rc))
640	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
641
642	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
643	if (RT_FAILURE(rc))
644	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
645	MsrRange.szName, rc);
646
647	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
648	if (RT_FAILURE(rc))
649	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
650	MsrRange.szName, rc);
651
652	char szType[32];
653	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
654	if (RT_FAILURE(rc))
655	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
656	MsrRange.szName, rc);
657	if (!RTStrICmp(szType, "FixedValue"))
658	{
659	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
660	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
661
662	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
663	if (RT_FAILURE(rc))
664	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
665	MsrRange.szName, rc);
666
667	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
668	if (RT_FAILURE(rc))
669	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
670	MsrRange.szName, rc);
671
672	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
673	if (RT_FAILURE(rc))
674	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
675	MsrRange.szName, rc);
676	}
677	else
678	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
679	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
680
681	/*
682	* Insert the range into the table (replaces/splits/shrinks existing
683	* MSR ranges).
684	*/
685	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
686	&MsrRange);
687	if (RT_FAILURE(rc))
688	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
689	}
690
691	return VINF_SUCCESS;
692	}
693
694
695	/**
696	* Loads CPUID leaf overrides.
697	*
698	* This must be called before the CPUID leaves are moved from the normal
699	* heap to the hyper heap!
700	*
701	* @returns VBox status code (VMSetError called).
702	* @param pVM The cross context VM structure.
703	* @param pParentNode The CFGM node with the CPUID leaves.
704	* @param pszLabel How to label the overrides we're loading.
705	*/
706	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
707	{
708	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
709	{
710	/*
711	* Get the leaf and subleaf numbers.
712	*/
713	char szName[128];
714	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
715	if (RT_FAILURE(rc))
716	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
717
718	/* The leaf number is either specified directly or thru the node name. */
719	uint32_t uLeaf;
720	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
721	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
722	{
723	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
724	if (rc != VINF_SUCCESS)
725	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
726	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
727	}
728	else if (RT_FAILURE(rc))
729	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
730	pszLabel, szName, rc);
731
732	uint32_t uSubLeaf;
733	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
734	if (RT_FAILURE(rc))
735	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
736	pszLabel, szName, rc);
737
738	uint32_t fSubLeafMask;
739	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
740	if (RT_FAILURE(rc))
741	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
742	pszLabel, szName, rc);
743
744	/*
745	* Look up the specified leaf, since the output register values
746	* defaults to any existing values. This allows overriding a single
747	* register, without needing to know the other values.
748	*/
749	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
750	CPUMCPUIDLEAF Leaf;
751	if (pLeaf)
752	Leaf = *pLeaf;
753	else
754	RT_ZERO(Leaf);
755	Leaf.uLeaf = uLeaf;
756	Leaf.uSubLeaf = uSubLeaf;
757	Leaf.fSubLeafMask = fSubLeafMask;
758
759	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
760	if (RT_FAILURE(rc))
761	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
762	pszLabel, szName, rc);
763	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
764	if (RT_FAILURE(rc))
765	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
766	pszLabel, szName, rc);
767	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
768	if (RT_FAILURE(rc))
769	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
770	pszLabel, szName, rc);
771	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
772	if (RT_FAILURE(rc))
773	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
774	pszLabel, szName, rc);
775
776	/*
777	* Insert the leaf into the table (replaces existing ones).
778	*/
779	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
780	&Leaf);
781	if (RT_FAILURE(rc))
782	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
783	}
784
785	return VINF_SUCCESS;
786	}
787
788
789
790	/**
791	* Fetches overrides for a CPUID leaf.
792	*
793	* @returns VBox status code.
794	* @param pLeaf The leaf to load the overrides into.
795	* @param pCfgNode The CFGM node containing the overrides
796	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
797	* @param iLeaf The CPUID leaf number.
798	*/
799	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
800	{
801	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
802	if (pLeafNode)
803	{
804	uint32_t u32;
805	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
806	if (RT_SUCCESS(rc))
807	pLeaf->uEax = u32;
808	else
809	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
810
811	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
812	if (RT_SUCCESS(rc))
813	pLeaf->uEbx = u32;
814	else
815	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
816
817	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
818	if (RT_SUCCESS(rc))
819	pLeaf->uEcx = u32;
820	else
821	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
822
823	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
824	if (RT_SUCCESS(rc))
825	pLeaf->uEdx = u32;
826	else
827	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
828
829	}
830	return VINF_SUCCESS;
831	}
832
833
834	/**
835	* Load the overrides for a set of CPUID leaves.
836	*
837	* @returns VBox status code.
838	* @param paLeaves The leaf array.
839	* @param cLeaves The number of leaves.
840	* @param uStart The start leaf number.
841	* @param pCfgNode The CFGM node containing the overrides
842	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
843	*/
844	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
845	{
846	for (uint32_t i = 0; i < cLeaves; i++)
847	{
848	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
849	if (RT_FAILURE(rc))
850	return rc;
851	}
852
853	return VINF_SUCCESS;
854	}
855
856
857	/**
858	* Installs the CPUID leaves and explods the data into structures like
859	* GuestFeatures and CPUMCTX::aoffXState.
860	*
861	* @returns VBox status code.
862	* @param pVM The cross context VM structure.
863	* @param pCpum The CPUM part of @a VM.
864	* @param paLeaves The leaves. These will be copied (but not freed).
865	* @param cLeaves The number of leaves.
866	* @param pMsrs The MSRs.
867	*/
868	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
869	{
870	# ifdef VBOX_STRICT
871	cpumCpuIdAssertOrder(paLeaves, cLeaves);
872	# endif
873
874	/*
875	* Install the CPUID information.
876	*/
877	AssertLogRelMsgReturn(cLeaves <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves),
878	("cLeaves=%u - max %u\n", cLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves)),
879	VERR_CPUM_IPE_1); /** @todo better status! */
880	if (paLeaves != pCpum->GuestInfo.aCpuIdLeaves)
881	memcpy(pCpum->GuestInfo.aCpuIdLeaves, paLeaves, cLeaves * sizeof(paLeaves[0]));
882	pCpum->GuestInfo.paCpuIdLeavesR3 = pCpum->GuestInfo.aCpuIdLeaves;
883	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
884
885	/*
886	* Update the default CPUID leaf if necessary.
887	*/
888	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
889	{
890	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
891	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
892	{
893	/* We don't use CPUID(0).eax here because of the NT hack that only
894	changes that value without actually removing any leaves. */
895	uint32_t i = 0;
896	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
897	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
898	{
899	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
900	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
901	i++;
902	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
903	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
904	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
905	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
906	}
907	break;
908	}
909	default:
910	break;
911	}
912
913	/*
914	* Explode the guest CPU features.
915	*/
916	int rc = cpumCpuIdExplodeFeaturesX86(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
917	&pCpum->GuestFeatures);
918	AssertLogRelRCReturn(rc, rc);
919
920	/*
921	* Adjust the scalable bus frequency according to the CPUID information
922	* we're now using.
923	*/
924	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
925	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
926	? UINT64_C(100000000) /* 100MHz */
927	: UINT64_C(133333333); /* 133MHz */
928
929	/*
930	* Populate the legacy arrays. Currently used for everything, later only
931	* for patch manager.
932	*/
933	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
934	{
935	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
936	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
937	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
938	};
939	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
940	{
941	uint32_t cLeft = aOldRanges[i].cCpuIds;
942	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
943	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
944	while (cLeft-- > 0)
945	{
946	uLeaf--;
947	pLegacyLeaf--;
948
949	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
950	if (pLeaf)
951	{
952	pLegacyLeaf->uEax = pLeaf->uEax;
953	pLegacyLeaf->uEbx = pLeaf->uEbx;
954	pLegacyLeaf->uEcx = pLeaf->uEcx;
955	pLegacyLeaf->uEdx = pLeaf->uEdx;
956	}
957	else
958	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
959	}
960	}
961
962	/*
963	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
964	*/
965	PVMCPU pVCpu0 = pVM->apCpusR3[0];
966	AssertCompile(sizeof(pVCpu0->cpum.s.Guest.abXState) == CPUM_MAX_XSAVE_AREA_SIZE);
967	memset(&pVCpu0->cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVCpu0->cpum.s.Guest.aoffXState));
968	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
969	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
970	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
971	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
972	{
973	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
974	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
975	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
976	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
977	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
978	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
979	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
980	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
981	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
982	pCpum->GuestFeatures.cbMaxExtendedState),
983	VERR_CPUM_IPE_1);
984	pVCpu0->cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
985	}
986
987	/* Copy the CPU #0 data to the other CPUs. */
988	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
989	{
990	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
991	memcpy(&pVCpu->cpum.s.Guest.aoffXState[0], &pVCpu0->cpum.s.Guest.aoffXState[0], sizeof(pVCpu0->cpum.s.Guest.aoffXState));
992	}
993
994	return VINF_SUCCESS;
995	}
996
997
998	/** @name Instruction Set Extension Options
999	* @{ */
1000	/** Configuration option type (extended boolean, really). */
1001	typedef uint8_t CPUMISAEXTCFG;
1002	/** Always disable the extension. */
1003	#define CPUMISAEXTCFG_DISABLED false
1004	/** Enable the extension if it's supported by the host CPU. */
1005	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
1006	/** Enable the extension if it's supported by the host CPU, but don't let
1007	* the portable CPUID feature disable it. */
1008	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
1009	/** Always enable the extension. */
1010	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
1011	/** @} */
1012
1013	/**
1014	* CPUID Configuration (from CFGM).
1015	*
1016	* @remarks The members aren't document since we would only be duplicating the
1017	* \@cfgm entries in cpumR3CpuIdReadConfig.
1018	*/
1019	typedef struct CPUMCPUIDCONFIG
1020	{
1021	bool fNt4LeafLimit;
1022	bool fInvariantTsc;
1023	bool fForceVme;
1024	bool fNestedHWVirt;
1025
1026	CPUMISAEXTCFG enmCmpXchg16b;
1027	CPUMISAEXTCFG enmMonitor;
1028	CPUMISAEXTCFG enmMWaitExtensions;
1029	CPUMISAEXTCFG enmSse41;
1030	CPUMISAEXTCFG enmSse42;
1031	CPUMISAEXTCFG enmAvx;
1032	CPUMISAEXTCFG enmAvx2;
1033	CPUMISAEXTCFG enmXSave;
1034	CPUMISAEXTCFG enmAesNi;
1035	CPUMISAEXTCFG enmPClMul;
1036	CPUMISAEXTCFG enmPopCnt;
1037	CPUMISAEXTCFG enmMovBe;
1038	CPUMISAEXTCFG enmRdRand;
1039	CPUMISAEXTCFG enmRdSeed;
1040	CPUMISAEXTCFG enmCLFlushOpt;
1041	CPUMISAEXTCFG enmFsGsBase;
1042	CPUMISAEXTCFG enmPcid;
1043	CPUMISAEXTCFG enmInvpcid;
1044	CPUMISAEXTCFG enmFlushCmdMsr;
1045	CPUMISAEXTCFG enmMdsClear;
1046	CPUMISAEXTCFG enmArchCapMsr;
1047
1048	CPUMISAEXTCFG enmAbm;
1049	CPUMISAEXTCFG enmSse4A;
1050	CPUMISAEXTCFG enmMisAlnSse;
1051	CPUMISAEXTCFG enm3dNowPrf;
1052	CPUMISAEXTCFG enmAmdExtMmx;
1053
1054	uint32_t uMaxStdLeaf;
1055	uint32_t uMaxExtLeaf;
1056	uint32_t uMaxCentaurLeaf;
1057	uint32_t uMaxIntelFamilyModelStep;
1058	char szCpuName[128];
1059	} CPUMCPUIDCONFIG;
1060	/** Pointer to CPUID config (from CFGM). */
1061	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
1062
1063
1064	/**
1065	* Mini CPU selection support for making Mac OS X happy.
1066	*
1067	* Executes the /CPUM/MaxIntelFamilyModelStep config.
1068	*
1069	* @param pCpum The CPUM instance data.
1070	* @param pConfig The CPUID configuration we've read from CFGM.
1071	*/
1072	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1073	{
1074	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1075	{
1076	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1077	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(RTX86GetCpuStepping(pStdFeatureLeaf->uEax),
1078	RTX86GetCpuModelIntel(pStdFeatureLeaf->uEax),
1079	RTX86GetCpuFamily(pStdFeatureLeaf->uEax),
1080	0);
1081	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
1082	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
1083	{
1084	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
1085	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
1086	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
1087	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
1088	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
1089	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
1090	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
1091	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
1092	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
1093	pStdFeatureLeaf->uEax = uNew;
1094	}
1095	}
1096	}
1097
1098
1099
1100	/**
1101	* Limit it the number of entries, zapping the remainder.
1102	*
1103	* The limits are masking off stuff about power saving and similar, this
1104	* is perhaps a bit crudely done as there is probably some relatively harmless
1105	* info too in these leaves (like words about having a constant TSC).
1106	*
1107	* @param pCpum The CPUM instance data.
1108	* @param pConfig The CPUID configuration we've read from CFGM.
1109	*/
1110	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1111	{
1112	/*
1113	* Standard leaves.
1114	*/
1115	uint32_t uSubLeaf = 0;
1116	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
1117	if (pCurLeaf)
1118	{
1119	uint32_t uLimit = pCurLeaf->uEax;
1120	if (uLimit <= UINT32_C(0x000fffff))
1121	{
1122	if (uLimit > pConfig->uMaxStdLeaf)
1123	{
1124	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
1125	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1126	uLimit + 1, UINT32_C(0x000fffff));
1127	}
1128
1129	/* NT4 hack, no zapping of extra leaves here. */
1130	if (pConfig->fNt4LeafLimit && uLimit > 3)
1131	pCurLeaf->uEax = uLimit = 3;
1132
1133	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
1134	pCurLeaf->uEax = uLimit;
1135	}
1136	else
1137	{
1138	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
1139	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1140	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
1141	}
1142	}
1143
1144	/*
1145	* Extended leaves.
1146	*/
1147	uSubLeaf = 0;
1148	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
1149	if (pCurLeaf)
1150	{
1151	uint32_t uLimit = pCurLeaf->uEax;
1152	if ( uLimit >= UINT32_C(0x80000000)
1153	&& uLimit <= UINT32_C(0x800fffff))
1154	{
1155	if (uLimit > pConfig->uMaxExtLeaf)
1156	{
1157	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
1158	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1159	uLimit + 1, UINT32_C(0x800fffff));
1160	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
1161	pCurLeaf->uEax = uLimit;
1162	}
1163	}
1164	else
1165	{
1166	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
1167	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1168	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
1169	}
1170	}
1171
1172	/*
1173	* Centaur leaves (VIA).
1174	*/
1175	uSubLeaf = 0;
1176	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
1177	if (pCurLeaf)
1178	{
1179	uint32_t uLimit = pCurLeaf->uEax;
1180	if ( uLimit >= UINT32_C(0xc0000000)
1181	&& uLimit <= UINT32_C(0xc00fffff))
1182	{
1183	if (uLimit > pConfig->uMaxCentaurLeaf)
1184	{
1185	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
1186	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1187	uLimit + 1, UINT32_C(0xcfffffff));
1188	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
1189	pCurLeaf->uEax = uLimit;
1190	}
1191	}
1192	else
1193	{
1194	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
1195	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1196	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
1197	}
1198	}
1199	}
1200
1201
1202	/**
1203	* Clears a CPUID leaf and all sub-leaves (to zero).
1204	*
1205	* @param pCpum The CPUM instance data.
1206	* @param uLeaf The leaf to clear.
1207	*/
1208	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
1209	{
1210	uint32_t uSubLeaf = 0;
1211	PCPUMCPUIDLEAF pCurLeaf;
1212	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
1213	{
1214	pCurLeaf->uEax = 0;
1215	pCurLeaf->uEbx = 0;
1216	pCurLeaf->uEcx = 0;
1217	pCurLeaf->uEdx = 0;
1218	uSubLeaf++;
1219	}
1220	}
1221
1222
1223	/**
1224	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
1225	* the given leaf.
1226	*
1227	* @returns pLeaf.
1228	* @param pCpum The CPUM instance data.
1229	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
1230	*/
1231	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
1232	{
1233	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
1234	if (pLeaf->fSubLeafMask != 0)
1235	{
1236	/*
1237	* Figure out how many sub-leaves in need of removal (we'll keep the first).
1238	* Log everything while we're at it.
1239	*/
1240	LogRel(("CPUM:\n"
1241	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
1242	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
1243	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
1244	for (;;)
1245	{
1246	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
1247	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
1248	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
1249	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
1250	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
1251	break;
1252	pSubLeaf++;
1253	}
1254	LogRel(("CPUM:\n"));
1255
1256	/*
1257	* Remove the offending sub-leaves.
1258	*/
1259	if (pSubLeaf != pLeaf)
1260	{
1261	if (pSubLeaf != pLast)
1262	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
1263	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
1264	}
1265
1266	/*
1267	* Convert the first sub-leaf into a single leaf.
1268	*/
1269	pLeaf->uSubLeaf = 0;
1270	pLeaf->fSubLeafMask = 0;
1271	}
1272	return pLeaf;
1273	}
1274
1275
1276	/**
1277	* Sanitizes and adjust the CPUID leaves.
1278	*
1279	* Drop features that aren't virtualized (or virtualizable). Adjust information
1280	* and capabilities to fit the virtualized hardware. Remove information the
1281	* guest shouldn't have (because it's wrong in the virtual world or because it
1282	* gives away host details) or that we don't have documentation for and no idea
1283	* what means.
1284	*
1285	* @returns VBox status code.
1286	* @param pVM The cross context VM structure (for cCpus).
1287	* @param pCpum The CPUM instance data.
1288	* @param pConfig The CPUID configuration we've read from CFGM.
1289	*/
1290	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1291	{
1292	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
1293	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
1294	{ \
1295	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
1296	(a_pLeafReg) &= ~(uint32_t)(fMask); \
1297	}
1298	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
1299	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
1300	{ \
1301	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
1302	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
1303	}
1304	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
1305	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
1306	&& ((a_pLeafReg) & (fBitMask)) \
1307	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
1308	{ \
1309	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
1310	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
1311	}
1312	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
1313
1314	/* The CPUID entries we start with here isn't necessarily the ones of the host, so we
1315	must consult HostFeatures when processing CPUMISAEXTCFG variables. */
1316	PCCPUMFEATURES pHstFeat = &pCpum->HostFeatures;
1317	#define PASSTHRU_FEATURE(enmConfig, fHostFeature, fConst) \
1318	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) ? (fConst) : 0)
1319	#define PASSTHRU_FEATURE_EX(enmConfig, fHostFeature, fAndExpr, fConst) \
1320	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) && (fAndExpr) ? (fConst) : 0)
1321	#define PASSTHRU_FEATURE_TODO(enmConfig, fConst) ((enmConfig) ? (fConst) : 0)
1322
1323	/* Cpuid 1:
1324	* EAX: CPU model, family and stepping.
1325	*
1326	* ECX + EDX: Supported features. Only report features we can support.
1327	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1328	* options may require adjusting (i.e. stripping what was enabled).
1329	*
1330	* EBX: Branding, CLFLUSH line size, logical processors per package and
1331	* initial APIC ID.
1332	*/
1333	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
1334	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
1335	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
1336
1337	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
1338	\| X86_CPUID_FEATURE_EDX_VME
1339	\| X86_CPUID_FEATURE_EDX_DE
1340	\| X86_CPUID_FEATURE_EDX_PSE
1341	\| X86_CPUID_FEATURE_EDX_TSC
1342	\| X86_CPUID_FEATURE_EDX_MSR
1343	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
1344	\| X86_CPUID_FEATURE_EDX_MCE
1345	\| X86_CPUID_FEATURE_EDX_CX8
1346	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
1347	//\| RT_BIT_32(10) - not defined
1348	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
1349	//\| X86_CPUID_FEATURE_EDX_SEP
1350	\| X86_CPUID_FEATURE_EDX_MTRR
1351	\| X86_CPUID_FEATURE_EDX_PGE
1352	\| X86_CPUID_FEATURE_EDX_MCA
1353	\| X86_CPUID_FEATURE_EDX_CMOV
1354	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
1355	\| X86_CPUID_FEATURE_EDX_PSE36
1356	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
1357	\| X86_CPUID_FEATURE_EDX_CLFSH
1358	//\| RT_BIT_32(20) - not defined
1359	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
1360	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
1361	\| X86_CPUID_FEATURE_EDX_MMX
1362	\| X86_CPUID_FEATURE_EDX_FXSR
1363	\| X86_CPUID_FEATURE_EDX_SSE
1364	\| X86_CPUID_FEATURE_EDX_SSE2
1365	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
1366	\| X86_CPUID_FEATURE_EDX_HTT
1367	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
1368	//\| RT_BIT_32(30) - not defined
1369	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
1370	;
1371	pStdFeatureLeaf->uEcx &= X86_CPUID_FEATURE_ECX_SSE3
1372	\| PASSTHRU_FEATURE_TODO(pConfig->enmPClMul, X86_CPUID_FEATURE_ECX_PCLMUL)
1373	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
1374	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
1375	\| PASSTHRU_FEATURE_EX(pConfig->enmMonitor, pHstFeat->fMonitorMWait, pVM->cCpus == 1, X86_CPUID_FEATURE_ECX_MONITOR)
1376	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
1377	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
1378	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
1379	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
1380	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
1381	\| X86_CPUID_FEATURE_ECX_SSSE3
1382	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
1383	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
1384	\| PASSTHRU_FEATURE(pConfig->enmCmpXchg16b, pHstFeat->fMovCmpXchg16b, X86_CPUID_FEATURE_ECX_CX16)
1385	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
1386	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1387	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
1388	\| PASSTHRU_FEATURE(pConfig->enmPcid, pHstFeat->fPcid, X86_CPUID_FEATURE_ECX_PCID)
1389	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
1390	\| PASSTHRU_FEATURE(pConfig->enmSse41, pHstFeat->fSse41, X86_CPUID_FEATURE_ECX_SSE4_1)
1391	\| PASSTHRU_FEATURE(pConfig->enmSse42, pHstFeat->fSse42, X86_CPUID_FEATURE_ECX_SSE4_2)
1392	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
1393	\| PASSTHRU_FEATURE_TODO(pConfig->enmMovBe, X86_CPUID_FEATURE_ECX_MOVBE)
1394	\| PASSTHRU_FEATURE_TODO(pConfig->enmPopCnt, X86_CPUID_FEATURE_ECX_POPCNT)
1395	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
1396	\| PASSTHRU_FEATURE_TODO(pConfig->enmAesNi, X86_CPUID_FEATURE_ECX_AES)
1397	\| PASSTHRU_FEATURE(pConfig->enmXSave, pHstFeat->fXSaveRstor, X86_CPUID_FEATURE_ECX_XSAVE)
1398	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
1399	\| PASSTHRU_FEATURE(pConfig->enmAvx, pHstFeat->fAvx, X86_CPUID_FEATURE_ECX_AVX)
1400	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
1401	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdRand, X86_CPUID_FEATURE_ECX_RDRAND)
1402	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
1403	;
1404
1405	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
1406	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
1407	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
1408	{
1409	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
1410	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
1411	}
1412
1413	if (pCpum->u8PortableCpuIdLevel > 0)
1414	{
1415	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
1416	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
1417	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
1418	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
1419	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
1420	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
1421	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
1422	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
1423	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
1424	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
1425	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
1426	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
1427	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
1428	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
1429	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
1430	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
1431	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
1432	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
1433	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
1434	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
1435
1436	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
1437	\| X86_CPUID_FEATURE_EDX_PSN
1438	\| X86_CPUID_FEATURE_EDX_DS
1439	\| X86_CPUID_FEATURE_EDX_ACPI
1440	\| X86_CPUID_FEATURE_EDX_SS
1441	\| X86_CPUID_FEATURE_EDX_TM
1442	\| X86_CPUID_FEATURE_EDX_PBE
1443	)));
1444	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
1445	\| X86_CPUID_FEATURE_ECX_CPLDS
1446	\| X86_CPUID_FEATURE_ECX_AES
1447	\| X86_CPUID_FEATURE_ECX_VMX
1448	\| X86_CPUID_FEATURE_ECX_SMX
1449	\| X86_CPUID_FEATURE_ECX_EST
1450	\| X86_CPUID_FEATURE_ECX_TM2
1451	\| X86_CPUID_FEATURE_ECX_CNTXID
1452	\| X86_CPUID_FEATURE_ECX_FMA
1453	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1454	\| X86_CPUID_FEATURE_ECX_PDCM
1455	\| X86_CPUID_FEATURE_ECX_DCA
1456	\| X86_CPUID_FEATURE_ECX_OSXSAVE
1457	)));
1458	}
1459
1460	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
1461	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
1462
1463	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
1464	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
1465	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
1466	*/
1467	#ifdef VBOX_WITH_MULTI_CORE
1468	if (pVM->cCpus > 1)
1469	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
1470	#endif
1471	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
1472	{
1473	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
1474	core times the number of CPU cores per processor */
1475	#ifdef VBOX_WITH_MULTI_CORE
1476	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
1477	#else
1478	/* Single logical processor in a package. */
1479	pStdFeatureLeaf->uEbx \|= (1 << 16);
1480	#endif
1481	}
1482
1483	uint32_t uMicrocodeRev;
1484	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
1485	if (RT_SUCCESS(rc))
1486	{
1487	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
1488	}
1489	else
1490	{
1491	uMicrocodeRev = 0;
1492	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
1493	}
1494
1495	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
1496	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
1497	*/
1498	if ( ( pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen
1499	/** @todo The following ASSUMES that Hygon uses the same version numbering
1500	* as AMD and that they shipped buggy firmware. */
1501	\|\| pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Hygon_Dhyana)
1502	&& uMicrocodeRev < 0x8001126
1503	&& !pConfig->fForceVme)
1504	{
1505	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
1506	LogRel(("CPUM: Zen VME workaround engaged\n"));
1507	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
1508	}
1509
1510	/* Force standard feature bits. */
1511	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
1512	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
1513	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
1514	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
1515	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
1516	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
1517	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1518	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
1519	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1520	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
1521	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
1522	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
1523	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
1524	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
1525	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
1526	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
1527	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
1528	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
1529	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1530	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
1531	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
1532	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
1533
1534	pStdFeatureLeaf = NULL; /* Must refetch! */
1535
1536	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
1537	* AMD:
1538	* EAX: CPU model, family and stepping.
1539	*
1540	* ECX + EDX: Supported features. Only report features we can support.
1541	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1542	* options may require adjusting (i.e. stripping what was enabled).
1543	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
1544	*
1545	* EBX: Branding ID and package type (or reserved).
1546	*
1547	* Intel and probably most others:
1548	* EAX: 0
1549	* EBX: 0
1550	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
1551	*/
1552	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
1553	if (pExtFeatureLeaf)
1554	{
1555	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
1556
1557	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
1558	\| X86_CPUID_AMD_FEATURE_EDX_VME
1559	\| X86_CPUID_AMD_FEATURE_EDX_DE
1560	\| X86_CPUID_AMD_FEATURE_EDX_PSE
1561	\| X86_CPUID_AMD_FEATURE_EDX_TSC
1562	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
1563	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
1564	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
1565	\| X86_CPUID_AMD_FEATURE_EDX_CX8
1566	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
1567	//\| RT_BIT_32(10) - reserved
1568	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
1569	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
1570	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1571	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
1572	\| X86_CPUID_AMD_FEATURE_EDX_PGE
1573	\| X86_CPUID_AMD_FEATURE_EDX_MCA
1574	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
1575	\| X86_CPUID_AMD_FEATURE_EDX_PAT
1576	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
1577	//\| RT_BIT_32(18) - reserved
1578	//\| RT_BIT_32(19) - reserved
1579	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
1580	//\| RT_BIT_32(21) - reserved
1581	\| PASSTHRU_FEATURE(pConfig->enmAmdExtMmx, pHstFeat->fAmdMmxExts, X86_CPUID_AMD_FEATURE_EDX_AXMMX)
1582	\| X86_CPUID_AMD_FEATURE_EDX_MMX
1583	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
1584	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
1585	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1586	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
1587	//\| RT_BIT_32(28) - reserved
1588	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
1589	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
1590	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
1591	;
1592	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
1593	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
1594	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
1595	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1596	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
1597	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
1598	\| PASSTHRU_FEATURE_TODO(pConfig->enmAbm, X86_CPUID_AMD_FEATURE_ECX_ABM)
1599	\| PASSTHRU_FEATURE_TODO(pConfig->enmSse4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A)
1600	\| PASSTHRU_FEATURE_TODO(pConfig->enmMisAlnSse, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE)
1601	\| PASSTHRU_FEATURE(pConfig->enm3dNowPrf, pHstFeat->f3DNowPrefetch, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1602	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
1603	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
1604	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
1605	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1606	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
1607	//\| RT_BIT_32(14) - reserved
1608	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
1609	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
1610	//\| RT_BIT_32(17) - reserved
1611	//\| RT_BIT_32(18) - reserved
1612	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
1613	//\| RT_BIT_32(20) - reserved
1614	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
1615	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
1616	//\| RT_BIT_32(23) - reserved
1617	//\| RT_BIT_32(24) - reserved
1618	//\| RT_BIT_32(25) - reserved
1619	//\| RT_BIT_32(26) - reserved
1620	//\| RT_BIT_32(27) - reserved
1621	//\| RT_BIT_32(28) - reserved
1622	//\| RT_BIT_32(29) - reserved
1623	//\| RT_BIT_32(30) - reserved
1624	//\| RT_BIT_32(31) - reserved
1625	;
1626	#ifdef VBOX_WITH_MULTI_CORE
1627	if ( pVM->cCpus > 1
1628	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
1629	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
1630	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
1631	#endif
1632
1633	if (pCpum->u8PortableCpuIdLevel > 0)
1634	{
1635	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1636	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
1637	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
1638	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
1639	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
1640	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
1641	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
1642	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
1643	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
1644	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
1645	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1646	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1647	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1648	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1649	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1650	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1651
1652	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
1653	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1654	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
1655	\| X86_CPUID_AMD_FEATURE_ECX_IBS
1656	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1657	\| X86_CPUID_AMD_FEATURE_ECX_WDT
1658	\| X86_CPUID_AMD_FEATURE_ECX_LWP
1659	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
1660	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
1661	\| UINT32_C(0xff964000)
1662	)));
1663	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
1664	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1665	\| RT_BIT(18)
1666	\| RT_BIT(19)
1667	\| RT_BIT(21)
1668	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
1669	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1670	\| RT_BIT(28)
1671	)));
1672	}
1673
1674	/* Force extended feature bits. */
1675	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
1676	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
1677	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
1678	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
1679	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
1680	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
1681	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
1682	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
1683	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1684	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
1685	}
1686	pExtFeatureLeaf = NULL; /* Must refetch! */
1687
1688
1689	/* Cpuid 2:
1690	* Intel: (Nondeterministic) Cache and TLB information
1691	* AMD: Reserved
1692	* VIA: Reserved
1693	* Safe to expose.
1694	*/
1695	uint32_t uSubLeaf = 0;
1696	PCPUMCPUIDLEAF pCurLeaf;
1697	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
1698	{
1699	if ((pCurLeaf->uEax & 0xff) > 1)
1700	{
1701	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
1702	pCurLeaf->uEax &= UINT32_C(0xffffff01);
1703	}
1704	uSubLeaf++;
1705	}
1706
1707	/* Cpuid 3:
1708	* Intel: EAX, EBX - reserved (transmeta uses these)
1709	* ECX, EDX - Processor Serial Number if available, otherwise reserved
1710	* AMD: Reserved
1711	* VIA: Reserved
1712	* Safe to expose
1713	*/
1714	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1715	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
1716	{
1717	uSubLeaf = 0;
1718	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
1719	{
1720	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1721	if (pCpum->u8PortableCpuIdLevel > 0)
1722	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1723	uSubLeaf++;
1724	}
1725	}
1726
1727	/* Cpuid 4 + ECX:
1728	* Intel: Deterministic Cache Parameters Leaf.
1729	* AMD: Reserved
1730	* VIA: Reserved
1731	* Safe to expose, except for EAX:
1732	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
1733	* Bits 31-26: Maximum number of processor cores in this physical package**
1734	* Note: These SMP values are constant regardless of ECX
1735	*/
1736	uSubLeaf = 0;
1737	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
1738	{
1739	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
1740	#ifdef VBOX_WITH_MULTI_CORE
1741	if ( pVM->cCpus > 1
1742	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1743	{
1744	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
1745	/* One logical processor with possibly multiple cores. */
1746	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
1747	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
1748	}
1749	#endif
1750	uSubLeaf++;
1751	}
1752
1753	/* Cpuid 5: Monitor/mwait Leaf
1754	* Intel: ECX, EDX - reserved
1755	* EAX, EBX - Smallest and largest monitor line size
1756	* AMD: EDX - reserved
1757	* EAX, EBX - Smallest and largest monitor line size
1758	* ECX - extensions (ignored for now)
1759	* VIA: Reserved
1760	* Safe to expose
1761	*/
1762	uSubLeaf = 0;
1763	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
1764	{
1765	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1766	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
1767	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1768
1769	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1770	if (pConfig->enmMWaitExtensions)
1771	{
1772	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
1773	/** @todo for now we just expose host's MWAIT C-states, although conceptually
1774	it shall be part of our power management virtualization model */
1775	#if 0
1776	/* MWAIT sub C-states */
1777	pCurLeaf->uEdx =
1778	(0 << 0) /* 0 in C0 */ \|
1779	(2 << 4) /* 2 in C1 */ \|
1780	(2 << 8) /* 2 in C2 */ \|
1781	(2 << 12) /* 2 in C3 */ \|
1782	(0 << 16) /* 0 in C4 */
1783	;
1784	#endif
1785	}
1786	else
1787	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1788	uSubLeaf++;
1789	}
1790
1791	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
1792	* Intel: Various stuff.
1793	* AMD: EAX, EBX, EDX - reserved.
1794	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
1795	* present. Same as intel.
1796	* VIA: ??
1797	*
1798	* We clear everything here for now.
1799	*/
1800	cpumR3CpuIdZeroLeaf(pCpum, 6);
1801
1802	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
1803	* EAX: Number of sub leaves.
1804	* EBX+ECX+EDX: Feature flags
1805	*
1806	* We only have documentation for one sub-leaf, so clear all other (no need
1807	* to remove them as such, just set them to zero).
1808	*
1809	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1810	* options may require adjusting (i.e. stripping what was enabled).
1811	*/
1812	uSubLeaf = 0;
1813	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
1814	{
1815	switch (uSubLeaf)
1816	{
1817	case 0:
1818	{
1819	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
1820	pCurLeaf->uEbx &= 0
1821	\| PASSTHRU_FEATURE(pConfig->enmFsGsBase, pHstFeat->fFsGsBase, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE)
1822	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
1823	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
1824	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
1825	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
1826	\| PASSTHRU_FEATURE(pConfig->enmAvx2, pHstFeat->fAvx2, X86_CPUID_STEXT_FEATURE_EBX_AVX2)
1827	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
1828	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
1829	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
1830	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
1831	\| PASSTHRU_FEATURE(pConfig->enmInvpcid, pHstFeat->fInvpcid, X86_CPUID_STEXT_FEATURE_EBX_INVPCID)
1832	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
1833	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
1834	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
1835	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
1836	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
1837	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
1838	//\| RT_BIT(17) - reserved
1839	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdSeed, X86_CPUID_STEXT_FEATURE_EBX_RDSEED)
1840	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
1841	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
1842	//\| RT_BIT(21) - reserved
1843	//\| RT_BIT(22) - reserved
1844	\| PASSTHRU_FEATURE(pConfig->enmCLFlushOpt, pHstFeat->fClFlushOpt, X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT)
1845	//\| RT_BIT(24) - reserved
1846	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
1847	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
1848	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
1849	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
1850	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
1851	//\| RT_BIT(30) - reserved
1852	//\| RT_BIT(31) - reserved
1853	;
1854	pCurLeaf->uEcx &= 0
1855	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
1856	;
1857	pCurLeaf->uEdx &= 0
1858	\| PASSTHRU_FEATURE(pConfig->enmMdsClear, pHstFeat->fMdsClear, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR)
1859	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
1860	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
1861	\| PASSTHRU_FEATURE(pConfig->enmFlushCmdMsr, pHstFeat->fFlushCmd, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD)
1862	\| PASSTHRU_FEATURE(pConfig->enmArchCapMsr, pHstFeat->fArchCap, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
1863	;
1864
1865	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
1866	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
1867	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
1868	{
1869	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
1870	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
1871	}
1872
1873	if (pCpum->u8PortableCpuIdLevel > 0)
1874	{
1875	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
1876	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
1877	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
1878	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
1879	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
1880	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
1881	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1882	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
1883	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
1884	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
1885	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
1886	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
1887	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
1888	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
1889	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
1890	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
1891	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
1892	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
1893	}
1894
1895	/* Dependencies. */
1896	if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
1897	pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
1898
1899	/* Force standard feature bits. */
1900	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
1901	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
1902	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1903	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
1904	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
1905	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
1906	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
1907	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
1908	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
1909	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
1910	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
1911	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
1912	if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
1913	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
1914	if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
1915	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
1916	break;
1917	}
1918
1919	default:
1920	/* Invalid index, all values are zero. */
1921	pCurLeaf->uEax = 0;
1922	pCurLeaf->uEbx = 0;
1923	pCurLeaf->uEcx = 0;
1924	pCurLeaf->uEdx = 0;
1925	break;
1926	}
1927	uSubLeaf++;
1928	}
1929
1930	/* Cpuid 8: Marked as reserved by Intel and AMD.
1931	* We zero this since we don't know what it may have been used for.
1932	*/
1933	cpumR3CpuIdZeroLeaf(pCpum, 8);
1934
1935	/* Cpuid 9: Direct Cache Access (DCA) Parameters
1936	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
1937	* EBX, ECX, EDX - reserved.
1938	* AMD: Reserved
1939	* VIA: ??
1940	*
1941	* We zero this.
1942	*/
1943	cpumR3CpuIdZeroLeaf(pCpum, 9);
1944
1945	/* Cpuid 0xa: Architectural Performance Monitor Features
1946	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
1947	* EBX, ECX, EDX - reserved.
1948	* AMD: Reserved
1949	* VIA: ??
1950	*
1951	* We zero this, for now at least.
1952	*/
1953	cpumR3CpuIdZeroLeaf(pCpum, 10);
1954
1955	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
1956	* Intel: EAX - APCI ID shift right for next level.
1957	* EBX - Factory configured cores/threads at this level.
1958	* ECX - Level number (same as input) and level type (1,2,0).
1959	* EDX - Extended initial APIC ID.
1960	* AMD: Reserved
1961	* VIA: ??
1962	*/
1963	uSubLeaf = 0;
1964	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
1965	{
1966	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
1967	{
1968	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
1969	if (bLevelType == 1)
1970	{
1971	/* Thread level - we don't do threads at the moment. */
1972	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
1973	pCurLeaf->uEbx = 1;
1974	}
1975	else if (bLevelType == 2)
1976	{
1977	/* Core level. */
1978	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
1979	#ifdef VBOX_WITH_MULTI_CORE
1980	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
1981	pCurLeaf->uEax++;
1982	#endif
1983	pCurLeaf->uEbx = pVM->cCpus;
1984	}
1985	else
1986	{
1987	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
1988	pCurLeaf->uEax = 0;
1989	pCurLeaf->uEbx = 0;
1990	pCurLeaf->uEcx = 0;
1991	}
1992	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
1993	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
1994	}
1995	else
1996	{
1997	pCurLeaf->uEax = 0;
1998	pCurLeaf->uEbx = 0;
1999	pCurLeaf->uEcx = 0;
2000	pCurLeaf->uEdx = 0;
2001	}
2002	uSubLeaf++;
2003	}
2004
2005	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
2006	* We zero this since we don't know what it may have been used for.
2007	*/
2008	cpumR3CpuIdZeroLeaf(pCpum, 12);
2009
2010	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
2011	* ECX=0: EAX - Valid bits in XCR0[31:0].
2012	* EBX - Maximum state size as per current XCR0 value.
2013	* ECX - Maximum state size for all supported features.
2014	* EDX - Valid bits in XCR0[63:32].
2015	* ECX=1: EAX - Various X-features.
2016	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
2017	* ECX - Valid bits in IA32_XSS[31:0].
2018	* EDX - Valid bits in IA32_XSS[63:32].
2019	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
2020	* if the bit invalid all four registers are set to zero.
2021	* EAX - The state size for this feature.
2022	* EBX - The state byte offset of this feature.
2023	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
2024	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
2025	*
2026	* Clear them all as we don't currently implement extended CPU state.
2027	*/
2028	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
2029	uint64_t fGuestXcr0Mask = 0;
2030	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2031	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
2032	{
2033	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
2034	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
2035	fGuestXcr0Mask \|= XSAVE_C_YMM;
2036	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
2037	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
2038	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
2039	fGuestXcr0Mask &= pCpum->fXStateHostMask;
2040
2041	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
2042	}
2043	pStdFeatureLeaf = NULL;
2044	pCpum->fXStateGuestMask = fGuestXcr0Mask;
2045
2046	/* Work the sub-leaves. */
2047	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
2048	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
2049	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
2050	{
2051	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
2052	if (pCurLeaf)
2053	{
2054	if (fGuestXcr0Mask)
2055	{
2056	switch (uSubLeaf)
2057	{
2058	case 0:
2059	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
2060	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
2061	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2062	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
2063	VERR_CPUM_IPE_1);
2064	cbXSaveMaxActual = pCurLeaf->uEcx;
2065	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
2066	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
2067	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
2068	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
2069	VERR_CPUM_IPE_2);
2070	continue;
2071	case 1:
2072	pCurLeaf->uEax &= 0;
2073	pCurLeaf->uEcx &= 0;
2074	pCurLeaf->uEdx &= 0;
2075	/** @todo what about checking ebx? */
2076	continue;
2077	default:
2078	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
2079	{
2080	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
2081	&& pCurLeaf->uEax > 0
2082	&& pCurLeaf->uEbx < cbXSaveMaxActual
2083	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2084	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
2085	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
2086	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
2087	VERR_CPUM_IPE_2);
2088	AssertLogRel(!(pCurLeaf->uEcx & 1));
2089	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
2090	pCurLeaf->uEdx = 0; /* it's reserved... */
2091	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
2092	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
2093	continue;
2094	}
2095	break;
2096	}
2097	}
2098
2099	/* Clear the leaf. */
2100	pCurLeaf->uEax = 0;
2101	pCurLeaf->uEbx = 0;
2102	pCurLeaf->uEcx = 0;
2103	pCurLeaf->uEdx = 0;
2104	}
2105	}
2106
2107	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
2108	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
2109	{
2110	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
2111	if (pCurLeaf)
2112	{
2113	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
2114	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
2115	pCurLeaf->uEbx = cbXSaveMaxReport;
2116	pCurLeaf->uEcx = cbXSaveMaxReport;
2117	}
2118	}
2119
2120	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
2121	* We zero this since we don't know what it may have been used for.
2122	*/
2123	cpumR3CpuIdZeroLeaf(pCpum, 14);
2124
2125	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
2126	* also known as Intel Resource Director Technology (RDT) Monitoring
2127	* We zero this as we don't currently virtualize PQM.
2128	*/
2129	cpumR3CpuIdZeroLeaf(pCpum, 15);
2130
2131	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
2132	* also known as Intel Resource Director Technology (RDT) Allocation
2133	* We zero this as we don't currently virtualize PQE.
2134	*/
2135	cpumR3CpuIdZeroLeaf(pCpum, 16);
2136
2137	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
2138	* We zero this since we don't know what it may have been used for.
2139	*/
2140	cpumR3CpuIdZeroLeaf(pCpum, 17);
2141
2142	/* Cpuid 0x12 + ECX: SGX resource enumeration.
2143	* We zero this as we don't currently virtualize this.
2144	*/
2145	cpumR3CpuIdZeroLeaf(pCpum, 18);
2146
2147	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
2148	* We zero this since we don't know what it may have been used for.
2149	*/
2150	cpumR3CpuIdZeroLeaf(pCpum, 19);
2151
2152	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
2153	* We zero this as we don't currently virtualize this.
2154	*/
2155	cpumR3CpuIdZeroLeaf(pCpum, 20);
2156
2157	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
2158	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
2159	* EAX - denominator (unsigned).
2160	* EBX - numerator (unsigned).
2161	* ECX, EDX - reserved.
2162	* AMD: Reserved / undefined / not implemented.
2163	* VIA: Reserved / undefined / not implemented.
2164	* We zero this as we don't currently virtualize this.
2165	*/
2166	cpumR3CpuIdZeroLeaf(pCpum, 21);
2167
2168	/* Cpuid 0x16: Processor frequency info
2169	* Intel: EAX - Core base frequency in MHz.
2170	* EBX - Core maximum frequency in MHz.
2171	* ECX - Bus (reference) frequency in MHz.
2172	* EDX - Reserved.
2173	* AMD: Reserved / undefined / not implemented.
2174	* VIA: Reserved / undefined / not implemented.
2175	* We zero this as we don't currently virtualize this.
2176	*/
2177	cpumR3CpuIdZeroLeaf(pCpum, 22);
2178
2179	/* Cpuid 0x17..0x10000000: Unknown.
2180	* We don't know these and what they mean, so remove them. */
2181	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2182	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
2183
2184
2185	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
2186	* We remove all these as we're a hypervisor and must provide our own.
2187	*/
2188	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2189	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
2190
2191
2192	/* Cpuid 0x80000000 is harmless. */
2193
2194	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
2195
2196	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
2197
2198	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
2199	* Safe to pass on to the guest.
2200	*
2201	* AMD: 0x800000005 L1 cache information
2202	* 0x800000006 L2/L3 cache information
2203	* Intel: 0x800000005 reserved
2204	* 0x800000006 L2 cache information
2205	* VIA: 0x800000005 TLB and L1 cache information
2206	* 0x800000006 L2 cache information
2207	*/
2208
2209	/* Cpuid 0x800000007: Advanced Power Management Information.
2210	* AMD: EAX: Processor feedback capabilities.
2211	* EBX: RAS capabilites.
2212	* ECX: Advanced power monitoring interface.
2213	* EDX: Enhanced power management capabilities.
2214	* Intel: EAX, EBX, ECX - reserved.
2215	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
2216	* VIA: Reserved
2217	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
2218	*/
2219	uSubLeaf = 0;
2220	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
2221	{
2222	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
2223	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2224	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2225	{
2226	/*
2227	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
2228	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
2229	* bit is now configurable.
2230	*/
2231	pCurLeaf->uEdx &= 0
2232	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
2233	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
2234	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
2235	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
2236	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
2237	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
2238	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
2239	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
2240	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
2241	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
2242	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
2243	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
2244	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
2245	\| 0;
2246	}
2247	else
2248	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
2249	if (!pConfig->fInvariantTsc)
2250	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
2251	uSubLeaf++;
2252	}
2253
2254	/* Cpuid 0x80000008:
2255	* AMD: EBX, EDX - reserved
2256	* EAX: Virtual/Physical/Guest address Size
2257	* ECX: Number of cores + APICIdCoreIdSize
2258	* Intel: EAX: Virtual/Physical address Size
2259	* EBX, ECX, EDX - reserved
2260	* VIA: EAX: Virtual/Physical address Size
2261	* EBX, ECX, EDX - reserved
2262	*
2263	* We only expose the virtual+pysical address size to the guest atm.
2264	* On AMD we set the core count, but not the apic id stuff as we're
2265	* currently not doing the apic id assignments in a complatible manner.
2266	*/
2267	uSubLeaf = 0;
2268	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
2269	{
2270	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
2271	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
2272	pCurLeaf->uEdx = 0; /* reserved */
2273
2274	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
2275	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
2276	pCurLeaf->uEcx = 0;
2277	#ifdef VBOX_WITH_MULTI_CORE
2278	if ( pVM->cCpus > 1
2279	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2280	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
2281	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
2282	#endif
2283	uSubLeaf++;
2284	}
2285
2286	/* Cpuid 0x80000009: Reserved
2287	* We zero this since we don't know what it may have been used for.
2288	*/
2289	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
2290
2291	/* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
2292	* AMD: EAX - SVM revision.
2293	* EBX - Number of ASIDs.
2294	* ECX - Reserved.
2295	* EDX - SVM Feature identification.
2296	*/
2297	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2298	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2299	{
2300	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2301	if ( pExtFeatureLeaf
2302	&& (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM))
2303	{
2304	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
2305	if (pSvmFeatureLeaf)
2306	{
2307	pSvmFeatureLeaf->uEax = 0x1;
2308	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
2309	pSvmFeatureLeaf->uEcx = 0;
2310	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
2311	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
2312	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
2313	}
2314	else
2315	{
2316	/* Should never happen. */
2317	LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
2318	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2319	}
2320	}
2321	else
2322	{
2323	/* If SVM is not supported, this is reserved, zero out. */
2324	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2325	}
2326	}
2327	else
2328	{
2329	/* Cpuid 0x8000000a: Reserved on Intel.
2330	* We zero this since we don't know what it may have been used for.
2331	*/
2332	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2333	}
2334
2335	/* Cpuid 0x8000000b thru 0x80000018: Reserved
2336	* We clear these as we don't know what purpose they might have. */
2337	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
2338	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
2339
2340	/* Cpuid 0x80000019: TLB configuration
2341	* Seems to be harmless, pass them thru as is. */
2342
2343	/* Cpuid 0x8000001a: Peformance optimization identifiers.
2344	* Strip anything we don't know what is or addresses feature we don't implement. */
2345	uSubLeaf = 0;
2346	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
2347	{
2348	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
2349	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
2350	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
2351	;
2352	pCurLeaf->uEbx = 0; /* reserved */
2353	pCurLeaf->uEcx = 0; /* reserved */
2354	pCurLeaf->uEdx = 0; /* reserved */
2355	uSubLeaf++;
2356	}
2357
2358	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
2359	* Clear this as we don't currently virtualize this feature. */
2360	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
2361
2362	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
2363	* Clear this as we don't currently virtualize this feature. */
2364	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
2365
2366	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
2367	* We need to sanitize the cores per cache (EAX[25:14]).
2368	*
2369	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
2370	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
2371	* slightly different meaning.
2372	*/
2373	uSubLeaf = 0;
2374	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
2375	{
2376	#ifdef VBOX_WITH_MULTI_CORE
2377	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
2378	if (cCores > pVM->cCpus)
2379	cCores = pVM->cCpus;
2380	pCurLeaf->uEax &= UINT32_C(0x00003fff);
2381	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
2382	#else
2383	pCurLeaf->uEax &= UINT32_C(0x00003fff);
2384	#endif
2385	uSubLeaf++;
2386	}
2387
2388	/* Cpuid 0x8000001e: Get APIC / unit / node information.
2389	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
2390	* setup, we have one compute unit with all the cores in it. Single node.
2391	*/
2392	uSubLeaf = 0;
2393	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
2394	{
2395	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
2396	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
2397	{
2398	#ifdef VBOX_WITH_MULTI_CORE
2399	pCurLeaf->uEbx = pVM->cCpus < 0x100
2400	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
2401	#else
2402	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
2403	#endif
2404	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
2405	}
2406	else
2407	{
2408	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
2409	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_HYGON);
2410	pCurLeaf->uEbx = 0; /* Reserved. */
2411	pCurLeaf->uEcx = 0; /* Reserved. */
2412	}
2413	pCurLeaf->uEdx = 0; /* Reserved. */
2414	uSubLeaf++;
2415	}
2416
2417	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
2418	* We don't know these and what they mean, so remove them. */
2419	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2420	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
2421
2422	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
2423	* Just pass it thru for now. */
2424
2425	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
2426	* Just pass it thru for now. */
2427
2428	/* Cpuid 0xc0000000: Centaur stuff.
2429	* Harmless, pass it thru. */
2430
2431	/* Cpuid 0xc0000001: Centaur features.
2432	* VIA: EAX - Family, model, stepping.
2433	* EDX - Centaur extended feature flags. Nothing interesting, except may
2434	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
2435	* EBX, ECX - reserved.
2436	* We keep EAX but strips the rest.
2437	*/
2438	uSubLeaf = 0;
2439	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
2440	{
2441	pCurLeaf->uEbx = 0;
2442	pCurLeaf->uEcx = 0;
2443	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
2444	uSubLeaf++;
2445	}
2446
2447	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
2448	* We only have fixed stale values, but should be harmless. */
2449
2450	/* Cpuid 0xc0000003: Reserved.
2451	* We zero this since we don't know what it may have been used for.
2452	*/
2453	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
2454
2455	/* Cpuid 0xc0000004: Centaur Performance Info.
2456	* We only have fixed stale values, but should be harmless. */
2457
2458
2459	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
2460	* We don't know these and what they mean, so remove them. */
2461	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2462	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
2463
2464	return VINF_SUCCESS;
2465	#undef PORTABLE_DISABLE_FEATURE_BIT
2466	#undef PORTABLE_CLEAR_BITS_WHEN
2467	}
2468
2469
2470	/**
2471	* Reads a value in /CPUM/IsaExts/ node.
2472	*
2473	* @returns VBox status code (error message raised).
2474	* @param pVM The cross context VM structure. (For errors.)
2475	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2476	* @param pszValueName The value / extension name.
2477	* @param penmValue Where to return the choice.
2478	* @param enmDefault The default choice.
2479	*/
2480	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
2481	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
2482	{
2483	/*
2484	* Try integer encoding first.
2485	*/
2486	uint64_t uValue;
2487	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
2488	if (RT_SUCCESS(rc))
2489	switch (uValue)
2490	{
2491	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
2492	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
2493	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
2494	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
2495	default:
2496	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
2497	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
2498	pszValueName, uValue);
2499	}
2500	/*
2501	* If missing, use default.
2502	*/
2503	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
2504	*penmValue = enmDefault;
2505	else
2506	{
2507	if (rc == VERR_CFGM_NOT_INTEGER)
2508	{
2509	/*
2510	* Not an integer, try read it as a string.
2511	*/
2512	char szValue[32];
2513	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
2514	if (RT_SUCCESS(rc))
2515	{
2516	RTStrToLower(szValue);
2517	size_t cchValue = strlen(szValue);
2518	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
2519	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
2520	*penmValue = CPUMISAEXTCFG_DISABLED;
2521	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
2522	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
2523	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
2524	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
2525	else if (EQ("portable"))
2526	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
2527	else if (EQ("default") \|\| EQ("def"))
2528	*penmValue = enmDefault;
2529	else
2530	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
2531	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
2532	pszValueName, uValue);
2533	#undef EQ
2534	}
2535	}
2536	if (RT_FAILURE(rc))
2537	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
2538	}
2539	return VINF_SUCCESS;
2540	}
2541
2542
2543	/**
2544	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
2545	*
2546	* @returns VBox status code (error message raised).
2547	* @param pVM The cross context VM structure. (For errors.)
2548	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2549	* @param pszValueName The value / extension name.
2550	* @param penmValue Where to return the choice.
2551	* @param enmDefault The default choice.
2552	* @param fAllowed Allowed choice. Applied both to the result and to
2553	* the default value.
2554	*/
2555	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
2556	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
2557	{
2558	int rc;
2559	if (fAllowed)
2560	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
2561	else
2562	{
2563	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
2564	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
2565	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
2566	*penmValue = CPUMISAEXTCFG_DISABLED;
2567	}
2568	return rc;
2569	}
2570
2571
2572	/**
2573	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
2574	*
2575	* @returns VBox status code (error message raised).
2576	* @param pVM The cross context VM structure. (For errors.)
2577	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2578	* @param pCpumCfg The /CPUM node (can be NULL).
2579	* @param pszValueName The value / extension name.
2580	* @param penmValue Where to return the choice.
2581	* @param enmDefault The default choice.
2582	*/
2583	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
2584	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
2585	{
2586	if (CFGMR3Exists(pCpumCfg, pszValueName))
2587	{
2588	if (!CFGMR3Exists(pIsaExts, pszValueName))
2589	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
2590	else
2591	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
2592	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
2593	pszValueName, pszValueName);
2594
2595	bool fLegacy;
2596	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
2597	if (RT_SUCCESS(rc))
2598	{
2599	*penmValue = fLegacy;
2600	return VINF_SUCCESS;
2601	}
2602	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
2603	}
2604
2605	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
2606	}
2607
2608
2609	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
2610	{
2611	int rc;
2612
2613	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
2614	* When non-zero CPUID features that could cause portability issues will be
2615	* stripped. The higher the value the more features gets stripped. Higher
2616	* values should only be used when older CPUs are involved since it may
2617	* harm performance and maybe also cause problems with specific guests. */
2618	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
2619	AssertLogRelRCReturn(rc, rc);
2620
2621	/** @cfgm{/CPUM/GuestCpuName, string}
2622	* The name of the CPU we're to emulate. The default is the host CPU.
2623	* Note! CPUs other than "host" one is currently unsupported. */
2624	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
2625	AssertLogRelRCReturn(rc, rc);
2626
2627	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
2628	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
2629	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
2630	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
2631	*/
2632	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
2633	AssertLogRelRCReturn(rc, rc);
2634
2635	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
2636	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
2637	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
2638	* 64-bit linux guests which assume the presence of AMD performance counters
2639	* that we do not virtualize.
2640	*/
2641	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
2642	AssertLogRelRCReturn(rc, rc);
2643
2644	/** @cfgm{/CPUM/ForceVme, boolean, false}
2645	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
2646	* By default the flag is passed thru as is from the host CPU, except
2647	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
2648	* guests and DOS boxes in general.
2649	*/
2650	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
2651	AssertLogRelRCReturn(rc, rc);
2652
2653	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
2654	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
2655	* probably going to be a temporary hack, so don't depend on this.
2656	* The 1st byte of the value is the stepping, the 2nd byte value is the model
2657	* number and the 3rd byte value is the family, and the 4th value must be zero.
2658	*/
2659	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
2660	AssertLogRelRCReturn(rc, rc);
2661
2662	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
2663	* The last standard leaf to keep. The actual last value that is stored in EAX
2664	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
2665	* removed. (This works independently of and differently from NT4LeafLimit.)
2666	* The default is usually set to what we're able to reasonably sanitize.
2667	*/
2668	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
2669	AssertLogRelRCReturn(rc, rc);
2670
2671	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
2672	* The last extended leaf to keep. The actual last value that is stored in EAX
2673	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
2674	* leaf are removed. The default is set to what we're able to sanitize.
2675	*/
2676	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
2677	AssertLogRelRCReturn(rc, rc);
2678
2679	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
2680	* The last extended leaf to keep. The actual last value that is stored in EAX
2681	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
2682	* leaf are removed. The default is set to what we're able to sanitize.
2683	*/
2684	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
2685	AssertLogRelRCReturn(rc, rc);
2686
2687	bool fQueryNestedHwvirt = false
2688	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2689	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2690	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON
2691	#endif
2692	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2693	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
2694	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA
2695	#endif
2696	;
2697	if (fQueryNestedHwvirt)
2698	{
2699	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
2700	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
2701	* The default is false, and when enabled requires a 64-bit CPU with support for
2702	* nested-paging and AMD-V or unrestricted guest mode.
2703	*/
2704	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
2705	AssertLogRelRCReturn(rc, rc);
2706	if (pConfig->fNestedHWVirt)
2707	{
2708	/** @todo Think about enabling this later with NEM/KVM. */
2709	if (VM_IS_NEM_ENABLED(pVM))
2710	{
2711	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used! (later)\n"));
2712	pConfig->fNestedHWVirt = false;
2713	}
2714	else if (!fNestedPagingAndFullGuestExec)
2715	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
2716	"Cannot enable nested VT-x/AMD-V without nested-paging and unrestricted guest execution!\n");
2717	}
2718
2719	if (pConfig->fNestedHWVirt)
2720	{
2721	/** @cfgm{/CPUM/NestedVmxPreemptTimer, bool, true}
2722	* Whether to expose the VMX-preemption timer feature to the guest (if also
2723	* supported by the host hardware). When disabled will prevent exposing the
2724	* VMX-preemption timer feature to the guest even if the host supports it.
2725	*
2726	* @todo Currently disabled, see @bugref{9180#c108}.
2727	*/
2728	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxPreemptTimer", &pVM->cpum.s.fNestedVmxPreemptTimer, false);
2729	AssertLogRelRCReturn(rc, rc);
2730
2731	/** @cfgm{/CPUM/NestedVmxEpt, bool, true}
2732	* Whether to expose the EPT feature to the guest. The default is false. When
2733	* disabled will automatically prevent exposing features that rely on
2734	*/
2735	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxEpt", &pVM->cpum.s.fNestedVmxEpt, false);
2736	AssertLogRelRCReturn(rc, rc);
2737
2738	/** @cfgm{/CPUM/NestedVmxUnrestrictedGuest, bool, true}
2739	* Whether to expose the Unrestricted Guest feature to the guest. The default is
2740	* false. When disabled will automatically prevent exposing features that rely on
2741	* it.
2742	*/
2743	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxUnrestrictedGuest", &pVM->cpum.s.fNestedVmxUnrestrictedGuest, false);
2744	AssertLogRelRCReturn(rc, rc);
2745
2746	if ( pVM->cpum.s.fNestedVmxUnrestrictedGuest
2747	&& !pVM->cpum.s.fNestedVmxEpt)
2748	{
2749	LogRel(("CPUM: WARNING! Can't expose \"Unrestricted Guest\" to the guest when EPT is not exposed!\n"));
2750	pVM->cpum.s.fNestedVmxUnrestrictedGuest = false;
2751	}
2752	}
2753	}
2754
2755	/*
2756	* Instruction Set Architecture (ISA) Extensions.
2757	*/
2758	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
2759	if (pIsaExts)
2760	{
2761	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
2762	"CMPXCHG16B"
2763	"\|MONITOR"
2764	"\|MWaitExtensions"
2765	"\|SSE4.1"
2766	"\|SSE4.2"
2767	"\|XSAVE"
2768	"\|AVX"
2769	"\|AVX2"
2770	"\|AESNI"
2771	"\|PCLMUL"
2772	"\|POPCNT"
2773	"\|MOVBE"
2774	"\|RDRAND"
2775	"\|RDSEED"
2776	"\|CLFLUSHOPT"
2777	"\|FSGSBASE"
2778	"\|PCID"
2779	"\|INVPCID"
2780	"\|FlushCmdMsr"
2781	"\|ABM"
2782	"\|SSE4A"
2783	"\|MISALNSSE"
2784	"\|3DNOWPRF"
2785	"\|AXMMX"
2786	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
2787	if (RT_FAILURE(rc))
2788	return rc;
2789	}
2790
2791	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, true}
2792	* Expose CMPXCHG16B to the guest if available. All host CPUs which support
2793	* hardware virtualization have it.
2794	*/
2795	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, true);
2796	AssertLogRelRCReturn(rc, rc);
2797
2798	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
2799	* Expose MONITOR/MWAIT instructions to the guest.
2800	*/
2801	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
2802	AssertLogRelRCReturn(rc, rc);
2803
2804	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
2805	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
2806	* break on interrupt feature (bit 1).
2807	*/
2808	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
2809	AssertLogRelRCReturn(rc, rc);
2810
2811	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
2812	* Expose SSE4.1 to the guest if available.
2813	*/
2814	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
2815	AssertLogRelRCReturn(rc, rc);
2816
2817	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
2818	* Expose SSE4.2 to the guest if available.
2819	*/
2820	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
2821	AssertLogRelRCReturn(rc, rc);
2822
2823	bool const fMayHaveXSave = pVM->cpum.s.HostFeatures.fXSaveRstor
2824	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
2825	&& ( VM_IS_NEM_ENABLED(pVM)
2826	? NEMHCGetFeatures(pVM) & NEM_FEAT_F_XSAVE_XRSTOR
2827	: VM_IS_EXEC_ENGINE_IEM(pVM)
2828	? false /** @todo IEM and XSAVE @bugref{9898} */
2829	: fNestedPagingAndFullGuestExec);
2830	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
2831
2832	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
2833	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
2834	* default is to only expose this to VMs with nested paging and AMD-V or
2835	* unrestricted guest execution mode. Not possible to force this one without
2836	* host support at the moment.
2837	*/
2838	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
2839	fMayHaveXSave /fAllowed/);
2840	AssertLogRelRCReturn(rc, rc);
2841
2842	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
2843	* Expose the AVX instruction set extensions to the guest if available and
2844	* XSAVE is exposed too. For the time being the default is to only expose this
2845	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
2846	*/
2847	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
2848	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
2849	AssertLogRelRCReturn(rc, rc);
2850
2851	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
2852	* Expose the AVX2 instruction set extensions to the guest if available and
2853	* XSAVE is exposed too. For the time being the default is to only expose this
2854	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
2855	*/
2856	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
2857	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
2858	AssertLogRelRCReturn(rc, rc);
2859
2860	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
2861	* Whether to expose the AES instructions to the guest. For the time being the
2862	* default is to only do this for VMs with nested paging and AMD-V or
2863	* unrestricted guest mode.
2864	*/
2865	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
2866	AssertLogRelRCReturn(rc, rc);
2867
2868	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
2869	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
2870	* being the default is to only do this for VMs with nested paging and AMD-V or
2871	* unrestricted guest mode.
2872	*/
2873	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
2874	AssertLogRelRCReturn(rc, rc);
2875
2876	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
2877	* Whether to expose the POPCNT instructions to the guest. For the time
2878	* being the default is to only do this for VMs with nested paging and AMD-V or
2879	* unrestricted guest mode.
2880	*/
2881	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
2882	AssertLogRelRCReturn(rc, rc);
2883
2884	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
2885	* Whether to expose the MOVBE instructions to the guest. For the time
2886	* being the default is to only do this for VMs with nested paging and AMD-V or
2887	* unrestricted guest mode.
2888	*/
2889	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
2890	AssertLogRelRCReturn(rc, rc);
2891
2892	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
2893	* Whether to expose the RDRAND instructions to the guest. For the time being
2894	* the default is to only do this for VMs with nested paging and AMD-V or
2895	* unrestricted guest mode.
2896	*/
2897	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
2898	AssertLogRelRCReturn(rc, rc);
2899
2900	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
2901	* Whether to expose the RDSEED instructions to the guest. For the time being
2902	* the default is to only do this for VMs with nested paging and AMD-V or
2903	* unrestricted guest mode.
2904	*/
2905	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
2906	AssertLogRelRCReturn(rc, rc);
2907
2908	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
2909	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
2910	* being the default is to only do this for VMs with nested paging and AMD-V or
2911	* unrestricted guest mode.
2912	*/
2913	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
2914	AssertLogRelRCReturn(rc, rc);
2915
2916	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
2917	* Whether to expose the read/write FSGSBASE instructions to the guest.
2918	*/
2919	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
2920	AssertLogRelRCReturn(rc, rc);
2921
2922	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
2923	* Whether to expose the PCID feature to the guest.
2924	*/
2925	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
2926	AssertLogRelRCReturn(rc, rc);
2927
2928	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
2929	* Whether to expose the INVPCID instruction to the guest.
2930	*/
2931	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
2932	AssertLogRelRCReturn(rc, rc);
2933
2934	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
2935	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
2936	*/
2937	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
2938	AssertLogRelRCReturn(rc, rc);
2939
2940	/** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
2941	* Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
2942	* the guest. Requires FlushCmdMsr to be present too.
2943	*/
2944	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
2945	AssertLogRelRCReturn(rc, rc);
2946
2947	/** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
2948	* Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
2949	*/
2950	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
2951	AssertLogRelRCReturn(rc, rc);
2952
2953
2954	/* AMD: */
2955
2956	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
2957	* Whether to expose the AMD ABM instructions to the guest. For the time
2958	* being the default is to only do this for VMs with nested paging and AMD-V or
2959	* unrestricted guest mode.
2960	*/
2961	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
2962	AssertLogRelRCReturn(rc, rc);
2963
2964	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
2965	* Whether to expose the AMD SSE4A instructions to the guest. For the time
2966	* being the default is to only do this for VMs with nested paging and AMD-V or
2967	* unrestricted guest mode.
2968	*/
2969	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
2970	AssertLogRelRCReturn(rc, rc);
2971
2972	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
2973	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
2974	* the time being the default is to only do this for VMs with nested paging and
2975	* AMD-V or unrestricted guest mode.
2976	*/
2977	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
2978	AssertLogRelRCReturn(rc, rc);
2979
2980	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
2981	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
2982	* For the time being the default is to only do this for VMs with nested paging
2983	* and AMD-V or unrestricted guest mode.
2984	*/
2985	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
2986	AssertLogRelRCReturn(rc, rc);
2987
2988	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
2989	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
2990	* the default is to only do this for VMs with nested paging and AMD-V or
2991	* unrestricted guest mode.
2992	*/
2993	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
2994	AssertLogRelRCReturn(rc, rc);
2995
2996	return VINF_SUCCESS;
2997	}
2998
2999
3000	/**
3001	* Initializes the emulated CPU's CPUID & MSR information.
3002	*
3003	* @returns VBox status code.
3004	* @param pVM The cross context VM structure.
3005	* @param pHostMsrs Pointer to the host MSRs.
3006	*/
3007	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
3008	{
3009	Assert(pHostMsrs);
3010
3011	PCPUM pCpum = &pVM->cpum.s;
3012	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
3013
3014	/*
3015	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
3016	* on construction and manage everything from here on.
3017	*/
3018	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3019	{
3020	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3021	pVCpu->cpum.s.fCpuIdApicFeatureVisible = true;
3022	}
3023
3024	/*
3025	* Read the configuration.
3026	*/
3027	CPUMCPUIDCONFIG Config;
3028	RT_ZERO(Config);
3029
3030	bool const fNestedPagingAndFullGuestExec = VM_IS_NEM_ENABLED(pVM)
3031	\|\| HMAreNestedPagingAndFullGuestExecEnabled(pVM);
3032	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, fNestedPagingAndFullGuestExec);
3033	AssertRCReturn(rc, rc);
3034
3035	/*
3036	* Get the guest CPU data from the database and/or the host.
3037	*
3038	* The CPUID and MSRs are currently living on the regular heap to avoid
3039	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
3040	* API for the hyper heap). This means special cleanup considerations.
3041	*/
3042	/** @todo The hyper heap will be removed ASAP, so the final destination is
3043	* now a fixed sized arrays in the VM structure. Maybe we can simplify
3044	* this allocation fun a little now? Or maybe it's too convenient for
3045	* the CPU reporter code... No time to figure that out now. */
3046	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
3047	if (RT_FAILURE(rc))
3048	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
3049	? VMSetError(pVM, rc, RT_SRC_POS,
3050	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
3051	: rc;
3052
3053	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
3054	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
3055	{
3056	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
3057	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
3058	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
3059	}
3060	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
3061	#else
3062	LogRel(("CPUM: MXCSR_MASK=%#x\n", pCpum->GuestInfo.fMxCsrMask));
3063	#endif
3064
3065	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
3066	* Overrides the guest MSRs.
3067	*/
3068	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
3069
3070	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
3071	* Overrides the CPUID leaf values (from the host CPU usually) used for
3072	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
3073	* values when moving a VM to a different machine. Another use is restricting
3074	* (or extending) the feature set exposed to the guest. */
3075	if (RT_SUCCESS(rc))
3076	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
3077
3078	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
3079	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
3080	"Found unsupported configuration node '/CPUM/CPUID/'. "
3081	"Please use IMachine::setCPUIDLeaf() instead.");
3082
3083	CPUMMSRS GuestMsrs;
3084	RT_ZERO(GuestMsrs);
3085
3086	/*
3087	* Pre-explode the CPUID info.
3088	*/
3089	if (RT_SUCCESS(rc))
3090	rc = cpumCpuIdExplodeFeaturesX86(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
3091	&pCpum->GuestFeatures);
3092
3093	/*
3094	* Sanitize the cpuid information passed on to the guest.
3095	*/
3096	if (RT_SUCCESS(rc))
3097	{
3098	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
3099	if (RT_SUCCESS(rc))
3100	{
3101	cpumR3CpuIdLimitLeaves(pCpum, &Config);
3102	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
3103	}
3104	}
3105
3106	/*
3107	* Setup MSRs introduced in microcode updates or that are otherwise not in
3108	* the CPU profile, but are advertised in the CPUID info we just sanitized.
3109	*/
3110	if (RT_SUCCESS(rc))
3111	rc = cpumR3MsrReconcileWithCpuId(pVM);
3112	/*
3113	* MSR fudging.
3114	*/
3115	if (RT_SUCCESS(rc))
3116	{
3117	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
3118	* Fudges some common MSRs if not present in the selected CPU database entry.
3119	* This is for trying to keep VMs running when moved between different hosts
3120	* and different CPU vendors. */
3121	bool fEnable;
3122	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
3123	if (RT_SUCCESS(rc) && fEnable)
3124	{
3125	rc = cpumR3MsrApplyFudge(pVM);
3126	AssertLogRelRC(rc);
3127	}
3128	}
3129	if (RT_SUCCESS(rc))
3130	{
3131	/*
3132	* Move the MSR and CPUID arrays over to the static VM structure allocations
3133	* and explode guest CPU features again.
3134	*/
3135	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
3136	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
3137	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
3138	RTMemFree(pvFree);
3139
3140	AssertFatalMsg(pCpum->GuestInfo.cMsrRanges <= RT_ELEMENTS(pCpum->GuestInfo.aMsrRanges),
3141	("%u\n", pCpum->GuestInfo.cMsrRanges));
3142	memcpy(pCpum->GuestInfo.aMsrRanges, pCpum->GuestInfo.paMsrRangesR3,
3143	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges);
3144	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
3145	pCpum->GuestInfo.paMsrRangesR3 = pCpum->GuestInfo.aMsrRanges;
3146
3147	AssertLogRelRCReturn(rc, rc);
3148
3149	/*
3150	* Finally, initialize guest VMX MSRs.
3151	*
3152	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
3153	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
3154	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
3155	*/
3156	if (pVM->cpum.s.GuestFeatures.fVmx)
3157	{
3158	Assert(Config.fNestedHWVirt);
3159	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
3160
3161	/* Copy MSRs to all VCPUs */
3162	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
3163	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3164	{
3165	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3166	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
3167	}
3168	}
3169
3170	/*
3171	* Some more configuration that we're applying at the end of everything
3172	* via the CPUMR3SetGuestCpuIdFeature API.
3173	*/
3174
3175	/* Check if PAE was explicitely enabled by the user. */
3176	bool fEnable;
3177	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
3178	AssertRCReturn(rc, rc);
3179	if (fEnable)
3180	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
3181
3182	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
3183	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
3184	AssertRCReturn(rc, rc);
3185	if (fEnable)
3186	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
3187
3188	/* Check if speculation control is enabled. */
3189	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
3190	AssertRCReturn(rc, rc);
3191	if (fEnable)
3192	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
3193	else
3194	{
3195	/*
3196	* Set the "SSBD-not-needed" flag to work around a bug in some Linux kernels when the VIRT_SPEC_CTL
3197	* feature is not exposed on AMD CPUs and there is only 1 vCPU configured.
3198	* This was observed with kernel "4.15.0-29-generic #31~16.04.1-Ubuntu" but more versions are likely affected.
3199	*
3200	* The kernel doesn't initialize a lock and causes a NULL pointer exception later on when configuring SSBD:
3201	* EIP: _raw_spin_lock+0x14/0x30
3202	* EFLAGS: 00010046 CPU: 0
3203	* EAX: 00000000 EBX: 00000001 ECX: 00000004 EDX: 00000000
3204	* ESI: 00000000 EDI: 00000000 EBP: ee023f1c ESP: ee023f18
3205	* DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
3206	* CR0: 80050033 CR2: 00000004 CR3: 3671c180 CR4: 000006f0
3207	* Call Trace:
3208	* speculative_store_bypass_update+0x8e/0x180
3209	* ssb_prctl_set+0xc0/0xe0
3210	* arch_seccomp_spec_mitigate+0x1d/0x20
3211	* do_seccomp+0x3cb/0x610
3212	* SyS_seccomp+0x16/0x20
3213	* do_fast_syscall_32+0x7f/0x1d0
3214	* entry_SYSENTER_32+0x4e/0x7c
3215	*
3216	* The lock would've been initialized in process.c:speculative_store_bypass_ht_init() called from two places in smpboot.c.
3217	* First when a secondary CPU is started and second in native_smp_prepare_cpus() which is not called in a single vCPU environment.
3218	*
3219	* As spectre control features are completely disabled anyway when we arrived here there is no harm done in informing the
3220	* guest to not even try.
3221	*/
3222	if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3223	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3224	{
3225	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x80000008), 0);
3226	if (pLeaf)
3227	{
3228	pLeaf->uEbx \|= X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED;
3229	LogRel(("CPUM: Set SSBD not required flag for AMD to work around some buggy Linux kernels!\n"));
3230	}
3231	}
3232	}
3233
3234	return VINF_SUCCESS;
3235	}
3236
3237	/*
3238	* Failed before switching to hyper heap.
3239	*/
3240	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
3241	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
3242	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
3243	pCpum->GuestInfo.paMsrRangesR3 = NULL;
3244	return rc;
3245	}
3246
3247
3248	/**
3249	* Sets a CPUID feature bit during VM initialization.
3250	*
3251	* Since the CPUID feature bits are generally related to CPU features, other
3252	* CPUM configuration like MSRs can also be modified by calls to this API.
3253	*
3254	* @param pVM The cross context VM structure.
3255	* @param enmFeature The feature to set.
3256	*/
3257	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
3258	{
3259	PCPUMCPUIDLEAF pLeaf;
3260	PCPUMMSRRANGE pMsrRange;
3261
3262	switch (enmFeature)
3263	{
3264	/*
3265	* Set the APIC bit in both feature masks.
3266	*/
3267	case CPUMCPUIDFEATURE_APIC:
3268	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3269	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
3270	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
3271
3272	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3273	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
3274	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
3275
3276	pVM->cpum.s.GuestFeatures.fApic = 1;
3277
3278	/* Make sure we've got the APICBASE MSR present. */
3279	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
3280	if (!pMsrRange)
3281	{
3282	static CPUMMSRRANGE const s_ApicBase =
3283	{
3284	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
3285	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
3286	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3287	/.szName = / "IA32_APIC_BASE"
3288	};
3289	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
3290	AssertLogRelRC(rc);
3291	}
3292
3293	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
3294	break;
3295
3296	/*
3297	* Set the x2APIC bit in the standard feature mask.
3298	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
3299	*/
3300	case CPUMCPUIDFEATURE_X2APIC:
3301	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3302	if (pLeaf)
3303	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
3304	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
3305
3306	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
3307	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
3308	if (pMsrRange)
3309	{
3310	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
3311	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
3312	}
3313
3314	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
3315	break;
3316
3317	/*
3318	* Set the sysenter/sysexit bit in the standard feature mask.
3319	* Assumes the caller knows what it's doing! (host must support these)
3320	*/
3321	case CPUMCPUIDFEATURE_SEP:
3322	if (!pVM->cpum.s.HostFeatures.fSysEnter)
3323	{
3324	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
3325	return;
3326	}
3327
3328	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3329	if (pLeaf)
3330	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
3331	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
3332	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
3333	break;
3334
3335	/*
3336	* Set the syscall/sysret bit in the extended feature mask.
3337	* Assumes the caller knows what it's doing! (host must support these)
3338	*/
3339	case CPUMCPUIDFEATURE_SYSCALL:
3340	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3341	if ( !pLeaf
3342	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
3343	{
3344	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
3345	return;
3346	}
3347
3348	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
3349	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
3350	pVM->cpum.s.GuestFeatures.fSysCall = 1;
3351	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
3352	break;
3353
3354	/*
3355	* Set the PAE bit in both feature masks.
3356	* Assumes the caller knows what it's doing! (host must support these)
3357	*/
3358	case CPUMCPUIDFEATURE_PAE:
3359	if (!pVM->cpum.s.HostFeatures.fPae)
3360	{
3361	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
3362	return;
3363	}
3364
3365	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3366	if (pLeaf)
3367	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
3368
3369	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3370	if ( pLeaf
3371	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3372	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3373	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
3374
3375	pVM->cpum.s.GuestFeatures.fPae = 1;
3376	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
3377	break;
3378
3379	/*
3380	* Set the LONG MODE bit in the extended feature mask.
3381	* Assumes the caller knows what it's doing! (host must support these)
3382	*/
3383	case CPUMCPUIDFEATURE_LONG_MODE:
3384	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3385	if ( !pLeaf
3386	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
3387	{
3388	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
3389	return;
3390	}
3391
3392	/* Valid for both Intel and AMD. */
3393	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
3394	pVM->cpum.s.GuestFeatures.fLongMode = 1;
3395	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
3396	if (pVM->cpum.s.GuestFeatures.fVmx)
3397	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3398	{
3399	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3400	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic &= ~VMX_BASIC_PHYSADDR_WIDTH_32BIT;
3401	}
3402	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
3403	break;
3404
3405	/*
3406	* Set the NX/XD bit in the extended feature mask.
3407	* Assumes the caller knows what it's doing! (host must support these)
3408	*/
3409	case CPUMCPUIDFEATURE_NX:
3410	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3411	if ( !pLeaf
3412	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
3413	{
3414	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
3415	return;
3416	}
3417
3418	/* Valid for both Intel and AMD. */
3419	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
3420	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
3421	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
3422	break;
3423
3424
3425	/*
3426	* Set the LAHF/SAHF support in 64-bit mode.
3427	* Assumes the caller knows what it's doing! (host must support this)
3428	*/
3429	case CPUMCPUIDFEATURE_LAHF:
3430	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3431	if ( !pLeaf
3432	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
3433	{
3434	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
3435	return;
3436	}
3437
3438	/* Valid for both Intel and AMD. */
3439	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
3440	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
3441	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
3442	break;
3443
3444	/*
3445	* Set the RDTSCP support bit.
3446	* Assumes the caller knows what it's doing! (host must support this)
3447	*/
3448	case CPUMCPUIDFEATURE_RDTSCP:
3449	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3450	if ( !pLeaf
3451	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
3452	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
3453	{
3454	if (!pVM->cpum.s.u8PortableCpuIdLevel)
3455	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
3456	return;
3457	}
3458
3459	/* Valid for both Intel and AMD. */
3460	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
3461	pVM->cpum.s.HostFeatures.fRdTscP = 1;
3462	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
3463	break;
3464
3465	/*
3466	* Set the Hypervisor Present bit in the standard feature mask.
3467	*/
3468	case CPUMCPUIDFEATURE_HVP:
3469	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3470	if (pLeaf)
3471	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
3472	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
3473	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
3474	break;
3475
3476	/*
3477	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
3478	* on Intel CPUs, and different on AMDs.
3479	*/
3480	case CPUMCPUIDFEATURE_SPEC_CTRL:
3481	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3482	{
3483	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
3484	if ( !pLeaf
3485	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
3486	{
3487	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
3488	return;
3489	}
3490
3491	/* The feature can be enabled. Let's see what we can actually do. */
3492	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
3493
3494	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
3495	if (pVM->cpum.s.HostFeatures.fIbrs)
3496	{
3497	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
3498	pVM->cpum.s.GuestFeatures.fIbrs = 1;
3499	if (pVM->cpum.s.HostFeatures.fStibp)
3500	{
3501	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
3502	pVM->cpum.s.GuestFeatures.fStibp = 1;
3503	}
3504
3505	/* Make sure we have the speculation control MSR... */
3506	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
3507	if (!pMsrRange)
3508	{
3509	static CPUMMSRRANGE const s_SpecCtrl =
3510	{
3511	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
3512	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
3513	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3514	/.szName = / "IA32_SPEC_CTRL"
3515	};
3516	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
3517	AssertLogRelRC(rc);
3518	}
3519
3520	/* ... and the predictor command MSR. */
3521	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
3522	if (!pMsrRange)
3523	{
3524	/** @todo incorrect fWrGpMask. */
3525	static CPUMMSRRANGE const s_SpecCtrl =
3526	{
3527	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
3528	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
3529	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3530	/.szName = / "IA32_PRED_CMD"
3531	};
3532	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
3533	AssertLogRelRC(rc);
3534	}
3535
3536	}
3537
3538	if (pVM->cpum.s.HostFeatures.fArchCap)
3539	{
3540	/* Install the architectural capabilities MSR. */
3541	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
3542	if (!pMsrRange)
3543	{
3544	static CPUMMSRRANGE const s_ArchCaps =
3545	{
3546	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
3547	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
3548	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
3549	/.szName = / "IA32_ARCH_CAPABILITIES"
3550	};
3551	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
3552	AssertLogRelRC(rc);
3553	}
3554
3555	/* Advertise IBRS_ALL if present at this point... */
3556	if (pVM->cpum.s.HostFeatures.fArchCap & MSR_IA32_ARCH_CAP_F_IBRS_ALL)
3557	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps \|= MSR_IA32_ARCH_CAP_F_IBRS_ALL);
3558	}
3559
3560	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
3561	}
3562	else if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3563	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3564	{
3565	/* The precise details of AMD's implementation are not yet clear. */
3566	}
3567	break;
3568
3569	default:
3570	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
3571	break;
3572	}
3573
3574	/** @todo can probably kill this as this API is now init time only... */
3575	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3576	{
3577	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3578	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
3579	}
3580	}
3581
3582
3583	/**
3584	* Queries a CPUID feature bit.
3585	*
3586	* @returns boolean for feature presence
3587	* @param pVM The cross context VM structure.
3588	* @param enmFeature The feature to query.
3589	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
3590	*/
3591	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
3592	{
3593	switch (enmFeature)
3594	{
3595	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
3596	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
3597	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
3598	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
3599	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
3600	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
3601	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
3602	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
3603	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
3604	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
3605	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
3606	case CPUMCPUIDFEATURE_INVALID:
3607	case CPUMCPUIDFEATURE_32BIT_HACK:
3608	break;
3609	}
3610	AssertFailed();
3611	return false;
3612	}
3613
3614
3615	/**
3616	* Clears a CPUID feature bit.
3617	*
3618	* @param pVM The cross context VM structure.
3619	* @param enmFeature The feature to clear.
3620	*
3621	* @deprecated Probably better to default the feature to disabled and only allow
3622	* setting (enabling) it during construction.
3623	*/
3624	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
3625	{
3626	PCPUMCPUIDLEAF pLeaf;
3627	switch (enmFeature)
3628	{
3629	case CPUMCPUIDFEATURE_APIC:
3630	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
3631	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3632	if (pLeaf)
3633	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
3634
3635	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3636	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
3637	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
3638
3639	pVM->cpum.s.GuestFeatures.fApic = 0;
3640	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
3641	break;
3642
3643	case CPUMCPUIDFEATURE_X2APIC:
3644	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
3645	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3646	if (pLeaf)
3647	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
3648	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
3649	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
3650	break;
3651
3652	case CPUMCPUIDFEATURE_PAE:
3653	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3654	if (pLeaf)
3655	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
3656
3657	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3658	if ( pLeaf
3659	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3660	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3661	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
3662
3663	pVM->cpum.s.GuestFeatures.fPae = 0;
3664	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
3665	break;
3666
3667	case CPUMCPUIDFEATURE_LONG_MODE:
3668	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3669	if (pLeaf)
3670	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
3671	pVM->cpum.s.GuestFeatures.fLongMode = 0;
3672	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = 32;
3673	if (pVM->cpum.s.GuestFeatures.fVmx)
3674	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3675	{
3676	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3677	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic \|= VMX_BASIC_PHYSADDR_WIDTH_32BIT;
3678	}
3679	break;
3680
3681	case CPUMCPUIDFEATURE_LAHF:
3682	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3683	if (pLeaf)
3684	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
3685	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
3686	break;
3687
3688	case CPUMCPUIDFEATURE_RDTSCP:
3689	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3690	if (pLeaf)
3691	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
3692	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
3693	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
3694	break;
3695
3696	case CPUMCPUIDFEATURE_HVP:
3697	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3698	if (pLeaf)
3699	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
3700	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
3701	break;
3702
3703	case CPUMCPUIDFEATURE_SPEC_CTRL:
3704	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
3705	if (pLeaf)
3706	pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP);
3707	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL);
3708	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
3709	break;
3710
3711	default:
3712	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
3713	break;
3714	}
3715
3716	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3717	{
3718	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3719	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
3720	}
3721	}
3722
3723
3724
3725	/*
3726	*
3727	*
3728	* Saved state related code.
3729	* Saved state related code.
3730	* Saved state related code.
3731	*
3732	*
3733	*/
3734
3735	/**
3736	* Called both in pass 0 and the final pass.
3737	*
3738	* @param pVM The cross context VM structure.
3739	* @param pSSM The saved state handle.
3740	*/
3741	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
3742	{
3743	/*
3744	* Save all the CPU ID leaves.
3745	*/
3746	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
3747	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
3748	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
3749	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
3750
3751	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
3752
3753	/*
3754	* Save a good portion of the raw CPU IDs as well as they may come in
3755	* handy when validating features for raw mode.
3756	*/
3757	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
3758	CPUMCPUID aRawStd[16];
3759	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
3760	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
3761	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
3762	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
3763
3764	CPUMCPUID aRawExt[32];
3765	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
3766	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
3767	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
3768	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
3769
3770	#else
3771	/* Two zero counts on non-x86 hosts. */
3772	SSMR3PutU32(pSSM, 0);
3773	SSMR3PutU32(pSSM, 0);
3774	#endif
3775	}
3776
3777
3778	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
3779	{
3780	uint32_t cCpuIds;
3781	int rc = SSMR3GetU32(pSSM, &cCpuIds);
3782	if (RT_SUCCESS(rc))
3783	{
3784	if (cCpuIds < 64)
3785	{
3786	for (uint32_t i = 0; i < cCpuIds; i++)
3787	{
3788	CPUMCPUID CpuId;
3789	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
3790	if (RT_FAILURE(rc))
3791	break;
3792
3793	CPUMCPUIDLEAF NewLeaf;
3794	NewLeaf.uLeaf = uBase + i;
3795	NewLeaf.uSubLeaf = 0;
3796	NewLeaf.fSubLeafMask = 0;
3797	NewLeaf.uEax = CpuId.uEax;
3798	NewLeaf.uEbx = CpuId.uEbx;
3799	NewLeaf.uEcx = CpuId.uEcx;
3800	NewLeaf.uEdx = CpuId.uEdx;
3801	NewLeaf.fFlags = 0;
3802	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
3803	}
3804	}
3805	else
3806	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3807	}
3808	if (RT_FAILURE(rc))
3809	{
3810	RTMemFree(*ppaLeaves);
3811	*ppaLeaves = NULL;
3812	*pcLeaves = 0;
3813	}
3814	return rc;
3815	}
3816
3817
3818	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
3819	{
3820	*ppaLeaves = NULL;
3821	*pcLeaves = 0;
3822
3823	int rc;
3824	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
3825	{
3826	/*
3827	* The new format. Starts by declaring the leave size and count.
3828	*/
3829	uint32_t cbLeaf;
3830	SSMR3GetU32(pSSM, &cbLeaf);
3831	uint32_t cLeaves;
3832	rc = SSMR3GetU32(pSSM, &cLeaves);
3833	if (RT_SUCCESS(rc))
3834	{
3835	if (cbLeaf == sizeof(**ppaLeaves))
3836	{
3837	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
3838	{
3839	/*
3840	* Load the leaves one by one.
3841	*
3842	* The uPrev stuff is a kludge for working around a week worth of bad saved
3843	* states during the CPUID revamp in March 2015. We saved too many leaves
3844	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
3845	* garbage entires at the end of the array when restoring. We also had
3846	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
3847	* this kludge doesn't deal correctly with that, but who cares...
3848	*/
3849	uint32_t uPrev = 0;
3850	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
3851	{
3852	CPUMCPUIDLEAF Leaf;
3853	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
3854	if (RT_SUCCESS(rc))
3855	{
3856	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
3857	\|\| Leaf.uLeaf >= uPrev)
3858	{
3859	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3860	uPrev = Leaf.uLeaf;
3861	}
3862	else
3863	uPrev = UINT32_MAX;
3864	}
3865	}
3866	}
3867	else
3868	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
3869	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
3870	}
3871	else
3872	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
3873	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
3874	}
3875	}
3876	else
3877	{
3878	/*
3879	* The old format with its three inflexible arrays.
3880	*/
3881	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
3882	if (RT_SUCCESS(rc))
3883	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
3884	if (RT_SUCCESS(rc))
3885	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
3886	if (RT_SUCCESS(rc))
3887	{
3888	/*
3889	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
3890	*/
3891	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(ppaLeaves, pcLeaves, 0, 0);
3892	if ( pLeaf
3893	&& RTX86IsIntelCpu(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
3894	{
3895	CPUMCPUIDLEAF Leaf;
3896	Leaf.uLeaf = 4;
3897	Leaf.fSubLeafMask = UINT32_MAX;
3898	Leaf.uSubLeaf = 0;
3899	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
3900	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
3901	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
3902	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
3903	\| UINT32_C(63); /* system coherency line size - 1 */
3904	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
3905	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
3906	\| (UINT32_C(1) << 5) /* cache level */
3907	\| UINT32_C(1); /* cache type (data) */
3908	Leaf.fFlags = 0;
3909	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3910	if (RT_SUCCESS(rc))
3911	{
3912	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
3913	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3914	}
3915	if (RT_SUCCESS(rc))
3916	{
3917	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
3918	Leaf.uEcx = 4095; /* sets - 1 */
3919	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
3920	Leaf.uEbx \|= UINT32_C(23) << 22;
3921	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
3922	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
3923	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
3924	Leaf.uEax \|= UINT32_C(2) << 5;
3925	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3926	}
3927	}
3928	}
3929	}
3930	return rc;
3931	}
3932
3933
3934	/**
3935	* Loads the CPU ID leaves saved by pass 0, inner worker.
3936	*
3937	* @returns VBox status code.
3938	* @param pVM The cross context VM structure.
3939	* @param pSSM The saved state handle.
3940	* @param uVersion The format version.
3941	* @param paLeaves Guest CPUID leaves loaded from the state.
3942	* @param cLeaves The number of leaves in @a paLeaves.
3943	* @param pMsrs The guest MSRs.
3944	*/
3945	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
3946	{
3947	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
3948
3949	/*
3950	* Continue loading the state into stack buffers.
3951	*/
3952	CPUMCPUID GuestDefCpuId;
3953	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
3954	AssertRCReturn(rc, rc);
3955
3956	CPUMCPUID aRawStd[16];
3957	uint32_t cRawStd;
3958	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
3959	if (cRawStd > RT_ELEMENTS(aRawStd))
3960	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3961	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
3962	AssertRCReturn(rc, rc);
3963	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
3964	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
3965	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
3966	#else
3967	RT_ZERO(aRawStd[i]);
3968	#endif
3969
3970	CPUMCPUID aRawExt[32];
3971	uint32_t cRawExt;
3972	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
3973	if (cRawExt > RT_ELEMENTS(aRawExt))
3974	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3975	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
3976	AssertRCReturn(rc, rc);
3977	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
3978	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
3979	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
3980	#else
3981	RT_ZERO(aRawExt[i]);
3982	#endif
3983
3984	/*
3985	* Get the raw CPU IDs for the current host.
3986	*/
3987	CPUMCPUID aHostRawStd[16];
3988	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
3989	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
3990	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
3991	#else
3992	RT_ZERO(aHostRawStd);
3993	#endif
3994
3995	CPUMCPUID aHostRawExt[32];
3996	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
3997	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
3998	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
3999	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
4000	#else
4001	RT_ZERO(aHostRawExt);
4002	#endif
4003
4004	/*
4005	* Get the host and guest overrides so we don't reject the state because
4006	* some feature was enabled thru these interfaces.
4007	* Note! We currently only need the feature leaves, so skip rest.
4008	*/
4009	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
4010	CPUMCPUID aHostOverrideStd[2];
4011	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
4012	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
4013
4014	CPUMCPUID aHostOverrideExt[2];
4015	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
4016	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
4017
4018	/*
4019	* This can be skipped.
4020	*/
4021	bool fStrictCpuIdChecks;
4022	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
4023
4024	/*
4025	* Define a bunch of macros for simplifying the santizing/checking code below.
4026	*/
4027	/* Generic expression + failure message. */
4028	#define CPUID_CHECK_RET(expr, fmt) \
4029	do { \
4030	if (!(expr)) \
4031	{ \
4032	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
4033	if (fStrictCpuIdChecks) \
4034	{ \
4035	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
4036	RTStrFree(pszMsg); \
4037	return rcCpuid; \
4038	} \
4039	LogRel(("CPUM: %s\n", pszMsg)); \
4040	RTStrFree(pszMsg); \
4041	} \
4042	} while (0)
4043	#define CPUID_CHECK_WRN(expr, fmt) \
4044	do { \
4045	if (!(expr)) \
4046	LogRel(fmt); \
4047	} while (0)
4048
4049	/* For comparing two values and bitch if they differs. */
4050	#define CPUID_CHECK2_RET(what, host, saved) \
4051	do { \
4052	if ((host) != (saved)) \
4053	{ \
4054	if (fStrictCpuIdChecks) \
4055	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4056	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
4057	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4058	} \
4059	} while (0)
4060	#define CPUID_CHECK2_WRN(what, host, saved) \
4061	do { \
4062	if ((host) != (saved)) \
4063	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4064	} while (0)
4065
4066	/* For checking raw cpu features (raw mode). */
4067	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
4068	do { \
4069	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4070	{ \
4071	if (fStrictCpuIdChecks) \
4072	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4073	N_(#bit " mismatch: host=%d saved=%d"), \
4074	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
4075	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4076	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4077	} \
4078	} while (0)
4079	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
4080	do { \
4081	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4082	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4083	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4084	} while (0)
4085	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
4086
4087	/* For checking guest features. */
4088	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
4089	do { \
4090	if ( (aGuestCpuId##set [1].reg & bit) \
4091	&& !(aHostRaw##set [1].reg & bit) \
4092	&& !(aHostOverride##set [1].reg & bit) \
4093	) \
4094	{ \
4095	if (fStrictCpuIdChecks) \
4096	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4097	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4098	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4099	} \
4100	} while (0)
4101	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
4102	do { \
4103	if ( (aGuestCpuId##set [1].reg & bit) \
4104	&& !(aHostRaw##set [1].reg & bit) \
4105	&& !(aHostOverride##set [1].reg & bit) \
4106	) \
4107	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4108	} while (0)
4109	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
4110	do { \
4111	if ( (aGuestCpuId##set [1].reg & bit) \
4112	&& !(aHostRaw##set [1].reg & bit) \
4113	&& !(aHostOverride##set [1].reg & bit) \
4114	) \
4115	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4116	} while (0)
4117	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
4118
4119	/* For checking guest features if AMD guest CPU. */
4120	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
4121	do { \
4122	if ( (aGuestCpuId##set [1].reg & bit) \
4123	&& fGuestAmd \
4124	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4125	&& !(aHostOverride##set [1].reg & bit) \
4126	) \
4127	{ \
4128	if (fStrictCpuIdChecks) \
4129	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4130	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4131	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4132	} \
4133	} while (0)
4134	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
4135	do { \
4136	if ( (aGuestCpuId##set [1].reg & bit) \
4137	&& fGuestAmd \
4138	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4139	&& !(aHostOverride##set [1].reg & bit) \
4140	) \
4141	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4142	} while (0)
4143	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
4144	do { \
4145	if ( (aGuestCpuId##set [1].reg & bit) \
4146	&& fGuestAmd \
4147	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4148	&& !(aHostOverride##set [1].reg & bit) \
4149	) \
4150	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4151	} while (0)
4152	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
4153
4154	/* For checking AMD features which have a corresponding bit in the standard
4155	range. (Intel defines very few bits in the extended feature sets.) */
4156	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
4157	do { \
4158	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4159	&& !(fHostAmd \
4160	? aHostRawExt[1].reg & (ExtBit) \
4161	: aHostRawStd[1].reg & (StdBit)) \
4162	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4163	) \
4164	{ \
4165	if (fStrictCpuIdChecks) \
4166	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4167	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
4168	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4169	} \
4170	} while (0)
4171	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
4172	do { \
4173	if ( (aGuestCpuId[1].reg & (ExtBit)) \
4174	&& !(fHostAmd \
4175	? aHostRawExt[1].reg & (ExtBit) \
4176	: aHostRawStd[1].reg & (StdBit)) \
4177	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4178	) \
4179	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4180	} while (0)
4181	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
4182	do { \
4183	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4184	&& !(fHostAmd \
4185	? aHostRawExt[1].reg & (ExtBit) \
4186	: aHostRawStd[1].reg & (StdBit)) \
4187	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4188	) \
4189	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4190	} while (0)
4191	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
4192
4193
4194	/*
4195	* Verify that we can support the features already exposed to the guest on
4196	* this host.
4197	*
4198	* Most of the features we're emulating requires intercepting instruction
4199	* and doing it the slow way, so there is no need to warn when they aren't
4200	* present in the host CPU. Thus we use IGN instead of EMU on these.
4201	*
4202	* Trailing comments:
4203	* "EMU" - Possible to emulate, could be lots of work and very slow.
4204	* "EMU?" - Can this be emulated?
4205	*/
4206	CPUMCPUID aGuestCpuIdStd[2];
4207	RT_ZERO(aGuestCpuIdStd);
4208	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
4209
4210	/* CPUID(1).ecx */
4211	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
4212	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
4213	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
4214	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4215	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
4216	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
4217	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
4218	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
4219	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
4220	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
4221	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
4222	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
4223	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
4224	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
4225	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
4226	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
4227	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
4228	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4229	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
4230	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
4231	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
4232	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4233	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
4234	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
4235	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4236	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
4237	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
4238	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
4239	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
4240	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4241	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4242	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
4243
4244	/* CPUID(1).edx */
4245	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4246	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4247	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
4248	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4249	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4250	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4251	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4252	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4253	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4254	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4255	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
4256	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4257	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4258	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4259	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4260	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4261	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4262	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4263	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4264	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
4265	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
4266	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
4267	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
4268	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4269	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4270	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
4271	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
4272	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
4273	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
4274	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
4275	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
4276	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
4277
4278	/* CPUID(0x80000000). */
4279	CPUMCPUID aGuestCpuIdExt[2];
4280	RT_ZERO(aGuestCpuIdExt);
4281	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
4282	{
4283	/** @todo deal with no 0x80000001 on the host. */
4284	bool const fHostAmd = RTX86IsAmdCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx)
4285	\|\| RTX86IsHygonCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
4286	bool const fGuestAmd = RTX86IsAmdCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx)
4287	\|\| RTX86IsHygonCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
4288
4289	/* CPUID(0x80000001).ecx */
4290	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
4291	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
4292	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
4293	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
4294	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
4295	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
4296	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
4297	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
4298	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
4299	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
4300	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
4301	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
4302	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
4303	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
4304	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4305	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4306	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4307	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4308	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4309	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4310	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4311	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4312	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4313	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4314	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4315	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4316	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4317	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4318	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4319	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4320	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4321	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4322
4323	/* CPUID(0x80000001).edx */
4324	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
4325	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
4326	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
4327	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
4328	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4329	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4330	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
4331	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
4332	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4333	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
4334	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
4335	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
4336	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
4337	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
4338	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
4339	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4340	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
4341	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
4342	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
4343	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
4344	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4345	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
4346	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4347	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4348	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4349	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4350	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4351	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4352	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
4353	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4354	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4355	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4356	}
4357
4358	/** @todo check leaf 7 */
4359
4360	/* CPUID(d) - XCR0 stuff - takes ECX as input.
4361	* ECX=0: EAX - Valid bits in XCR0[31:0].
4362	* EBX - Maximum state size as per current XCR0 value.
4363	* ECX - Maximum state size for all supported features.
4364	* EDX - Valid bits in XCR0[63:32].
4365	* ECX=1: EAX - Various X-features.
4366	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
4367	* ECX - Valid bits in IA32_XSS[31:0].
4368	* EDX - Valid bits in IA32_XSS[63:32].
4369	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
4370	* if the bit invalid all four registers are set to zero.
4371	* EAX - The state size for this feature.
4372	* EBX - The state byte offset of this feature.
4373	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
4374	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
4375	*/
4376	uint64_t fGuestXcr0Mask = 0;
4377	PCPUMCPUIDLEAF pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
4378	if ( pCurLeaf
4379	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
4380	&& ( pCurLeaf->uEax
4381	\|\| pCurLeaf->uEbx
4382	\|\| pCurLeaf->uEcx
4383	\|\| pCurLeaf->uEdx) )
4384	{
4385	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
4386	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
4387	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4388	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
4389	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
4390	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
4391	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4392	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
4393
4394	/* We don't support any additional features yet. */
4395	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
4396	if (pCurLeaf && pCurLeaf->uEax)
4397	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4398	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
4399	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
4400	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4401	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
4402	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
4403
4404
4405	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4406	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
4407	{
4408	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4409	if (pCurLeaf)
4410	{
4411	/* If advertised, the state component offset and size must match the one used by host. */
4412	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
4413	{
4414	CPUMCPUID RawHost;
4415	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
4416	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
4417	if ( RawHost.uEbx != pCurLeaf->uEbx
4418	\|\| RawHost.uEax != pCurLeaf->uEax)
4419	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4420	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
4421	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
4422	}
4423	}
4424	}
4425	#endif
4426	}
4427	/* Clear leaf 0xd just in case we're loading an old state... */
4428	else if (pCurLeaf)
4429	{
4430	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
4431	{
4432	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4433	if (pCurLeaf)
4434	{
4435	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
4436	\|\| ( pCurLeaf->uEax == 0
4437	&& pCurLeaf->uEbx == 0
4438	&& pCurLeaf->uEcx == 0
4439	&& pCurLeaf->uEdx == 0),
4440	("uVersion=%#x; %#x %#x %#x %#x\n",
4441	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
4442	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
4443	}
4444	}
4445	}
4446
4447	/* Update the fXStateGuestMask value for the VM. */
4448	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
4449	{
4450	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
4451	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
4452	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
4453	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4454	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
4455	}
4456
4457	#undef CPUID_CHECK_RET
4458	#undef CPUID_CHECK_WRN
4459	#undef CPUID_CHECK2_RET
4460	#undef CPUID_CHECK2_WRN
4461	#undef CPUID_RAW_FEATURE_RET
4462	#undef CPUID_RAW_FEATURE_WRN
4463	#undef CPUID_RAW_FEATURE_IGN
4464	#undef CPUID_GST_FEATURE_RET
4465	#undef CPUID_GST_FEATURE_WRN
4466	#undef CPUID_GST_FEATURE_EMU
4467	#undef CPUID_GST_FEATURE_IGN
4468	#undef CPUID_GST_FEATURE2_RET
4469	#undef CPUID_GST_FEATURE2_WRN
4470	#undef CPUID_GST_FEATURE2_EMU
4471	#undef CPUID_GST_FEATURE2_IGN
4472	#undef CPUID_GST_AMD_FEATURE_RET
4473	#undef CPUID_GST_AMD_FEATURE_WRN
4474	#undef CPUID_GST_AMD_FEATURE_EMU
4475	#undef CPUID_GST_AMD_FEATURE_IGN
4476
4477	/*
4478	* We're good, commit the CPU ID leaves.
4479	*/
4480	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
4481	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
4482	AssertLogRelRCReturn(rc, rc);
4483
4484	return VINF_SUCCESS;
4485	}
4486
4487
4488	/**
4489	* Loads the CPU ID leaves saved by pass 0.
4490	*
4491	* @returns VBox status code.
4492	* @param pVM The cross context VM structure.
4493	* @param pSSM The saved state handle.
4494	* @param uVersion The format version.
4495	* @param pMsrs The guest MSRs.
4496	*/
4497	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
4498	{
4499	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4500
4501	/*
4502	* Load the CPUID leaves array first and call worker to do the rest, just so
4503	* we can free the memory when we need to without ending up in column 1000.
4504	*/
4505	PCPUMCPUIDLEAF paLeaves;
4506	uint32_t cLeaves;
4507	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
4508	AssertRC(rc);
4509	if (RT_SUCCESS(rc))
4510	{
4511	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
4512	RTMemFree(paLeaves);
4513	}
4514	return rc;
4515	}
4516
4517
4518
4519	/**
4520	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
4521	*
4522	* @returns VBox status code.
4523	* @param pVM The cross context VM structure.
4524	* @param pSSM The saved state handle.
4525	* @param uVersion The format version.
4526	*/
4527	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
4528	{
4529	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4530
4531	/*
4532	* Restore the CPUID leaves.
4533	*
4534	* Note that we support restoring less than the current amount of standard
4535	* leaves because we've been allowed more is newer version of VBox.
4536	*/
4537	uint32_t cElements;
4538	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
4539	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
4540	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4541	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
4542
4543	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
4544	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
4545	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4546	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
4547
4548	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
4549	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
4550	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4551	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
4552
4553	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4554
4555	/*
4556	* Check that the basic cpuid id information is unchanged.
4557	*/
4558	/** @todo we should check the 64 bits capabilities too! */
4559	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
4560	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4561	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
4562	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
4563	#endif
4564	uint32_t au32CpuIdSaved[8];
4565	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
4566	if (RT_SUCCESS(rc))
4567	{
4568	/* Ignore CPU stepping. */
4569	au32CpuId[4] &= 0xfffffff0;
4570	au32CpuIdSaved[4] &= 0xfffffff0;
4571
4572	/* Ignore APIC ID (AMD specs). */
4573	au32CpuId[5] &= ~0xff000000;
4574	au32CpuIdSaved[5] &= ~0xff000000;
4575
4576	/* Ignore the number of Logical CPUs (AMD specs). */
4577	au32CpuId[5] &= ~0x00ff0000;
4578	au32CpuIdSaved[5] &= ~0x00ff0000;
4579
4580	/* Ignore some advanced capability bits, that we don't expose to the guest. */
4581	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
4582	\| X86_CPUID_FEATURE_ECX_VMX
4583	\| X86_CPUID_FEATURE_ECX_SMX
4584	\| X86_CPUID_FEATURE_ECX_EST
4585	\| X86_CPUID_FEATURE_ECX_TM2
4586	\| X86_CPUID_FEATURE_ECX_CNTXID
4587	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
4588	\| X86_CPUID_FEATURE_ECX_PDCM
4589	\| X86_CPUID_FEATURE_ECX_DCA
4590	\| X86_CPUID_FEATURE_ECX_X2APIC
4591	);
4592	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
4593	\| X86_CPUID_FEATURE_ECX_VMX
4594	\| X86_CPUID_FEATURE_ECX_SMX
4595	\| X86_CPUID_FEATURE_ECX_EST
4596	\| X86_CPUID_FEATURE_ECX_TM2
4597	\| X86_CPUID_FEATURE_ECX_CNTXID
4598	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
4599	\| X86_CPUID_FEATURE_ECX_PDCM
4600	\| X86_CPUID_FEATURE_ECX_DCA
4601	\| X86_CPUID_FEATURE_ECX_X2APIC
4602	);
4603
4604	/* Make sure we don't forget to update the masks when enabling
4605	* features in the future.
4606	*/
4607	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
4608	( X86_CPUID_FEATURE_ECX_DTES64
4609	\| X86_CPUID_FEATURE_ECX_VMX
4610	\| X86_CPUID_FEATURE_ECX_SMX
4611	\| X86_CPUID_FEATURE_ECX_EST
4612	\| X86_CPUID_FEATURE_ECX_TM2
4613	\| X86_CPUID_FEATURE_ECX_CNTXID
4614	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
4615	\| X86_CPUID_FEATURE_ECX_PDCM
4616	\| X86_CPUID_FEATURE_ECX_DCA
4617	\| X86_CPUID_FEATURE_ECX_X2APIC
4618	)));
4619	/* do the compare */
4620	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
4621	{
4622	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
4623	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
4624	"Saved=%.*Rhxs\n"
4625	"Real =%.*Rhxs\n",
4626	sizeof(au32CpuIdSaved), au32CpuIdSaved,
4627	sizeof(au32CpuId), au32CpuId));
4628	else
4629	{
4630	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
4631	"Saved=%.*Rhxs\n"
4632	"Real =%.*Rhxs\n",
4633	sizeof(au32CpuIdSaved), au32CpuIdSaved,
4634	sizeof(au32CpuId), au32CpuId));
4635	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
4636	}
4637	}
4638	}
4639
4640	return rc;
4641	}
4642
4643
4644
4645	/*
4646	*
4647	*
4648	* CPUID Info Handler.
4649	* CPUID Info Handler.
4650	* CPUID Info Handler.
4651	*
4652	*
4653	*/
4654
4655
4656
4657	/**
4658	* Get L1 cache / TLS associativity.
4659	*/
4660	static const char getCacheAss(unsigned u, char pszBuf)
4661	{
4662	if (u == 0)
4663	return "res0 ";
4664	if (u == 1)
4665	return "direct";
4666	if (u == 255)
4667	return "fully";
4668	if (u >= 256)
4669	return "???";
4670
4671	RTStrPrintf(pszBuf, 16, "%d way", u);
4672	return pszBuf;
4673	}
4674
4675
4676	/**
4677	* Get L2 cache associativity.
4678	*/
4679	const char *getL2CacheAss(unsigned u)
4680	{
4681	switch (u)
4682	{
4683	case 0: return "off ";
4684	case 1: return "direct";
4685	case 2: return "2 way ";
4686	case 3: return "res3 ";
4687	case 4: return "4 way ";
4688	case 5: return "res5 ";
4689	case 6: return "8 way ";
4690	case 7: return "res7 ";
4691	case 8: return "16 way";
4692	case 9: return "res9 ";
4693	case 10: return "res10 ";
4694	case 11: return "res11 ";
4695	case 12: return "res12 ";
4696	case 13: return "res13 ";
4697	case 14: return "res14 ";
4698	case 15: return "fully ";
4699	default: return "????";
4700	}
4701	}
4702
4703
4704	/** CPUID(1).EDX field descriptions. */
4705	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
4706	{
4707	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
4708	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
4709	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
4710	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
4711	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
4712	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
4713	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
4714	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
4715	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
4716	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
4717	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
4718	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
4719	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
4720	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
4721	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
4722	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
4723	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
4724	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
4725	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
4726	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
4727	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
4728	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
4729	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
4730	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
4731	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
4732	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
4733	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
4734	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
4735	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
4736	DBGFREGSUBFIELD_TERMINATOR()
4737	};
4738
4739	/** CPUID(1).ECX field descriptions. */
4740	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
4741	{
4742	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
4743	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
4744	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
4745	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
4746	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
4747	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
4748	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
4749	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
4750	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
4751	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
4752	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
4753	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
4754	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
4755	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
4756	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
4757	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
4758	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
4759	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
4760	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
4761	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
4762	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
4763	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
4764	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
4765	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
4766	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
4767	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
4768	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
4769	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
4770	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
4771	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
4772	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
4773	DBGFREGSUBFIELD_TERMINATOR()
4774	};
4775
4776	/** CPUID(7,0).EBX field descriptions. */
4777	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
4778	{
4779	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
4780	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
4781	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
4782	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
4783	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
4784	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
4785	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
4786	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
4787	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
4788	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
4789	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
4790	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
4791	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
4792	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
4793	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
4794	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
4795	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
4796	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
4797	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
4798	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
4799	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
4800	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
4801	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
4802	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
4803	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
4804	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
4805	DBGFREGSUBFIELD_TERMINATOR()
4806	};
4807
4808	/** CPUID(7,0).ECX field descriptions. */
4809	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
4810	{
4811	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
4812	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
4813	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
4814	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
4815	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
4816	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
4817	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
4818	DBGFREGSUBFIELD_TERMINATOR()
4819	};
4820
4821	/** CPUID(7,0).EDX field descriptions. */
4822	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
4823	{
4824	DBGFREGSUBFIELD_RO("MD_CLEAR\0" "Supports MDS related buffer clearing", 10, 1, 0),
4825	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
4826	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
4827	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
4828	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
4829	DBGFREGSUBFIELD_RO("CORECAP\0" "Supports IA32_CORE_CAP", 30, 1, 0),
4830	DBGFREGSUBFIELD_RO("SSBD\0" "Supports IA32_SPEC_CTRL.SSBD", 31, 1, 0),
4831	DBGFREGSUBFIELD_TERMINATOR()
4832	};
4833
4834
4835	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
4836	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
4837	{
4838	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
4839	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
4840	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
4841	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
4842	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
4843	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
4844	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
4845	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
4846	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
4847	DBGFREGSUBFIELD_TERMINATOR()
4848	};
4849
4850	/** CPUID(13,1).EAX field descriptions. */
4851	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
4852	{
4853	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
4854	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
4855	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
4856	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
4857	DBGFREGSUBFIELD_TERMINATOR()
4858	};
4859
4860
4861	/** CPUID(0x80000001,0).EDX field descriptions. */
4862	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
4863	{
4864	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
4865	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
4866	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
4867	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
4868	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
4869	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
4870	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
4871	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
4872	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
4873	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
4874	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
4875	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
4876	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
4877	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
4878	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
4879	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
4880	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
4881	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
4882	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
4883	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
4884	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
4885	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
4886	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
4887	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
4888	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
4889	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
4890	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
4891	DBGFREGSUBFIELD_TERMINATOR()
4892	};
4893
4894	/** CPUID(0x80000001,0).ECX field descriptions. */
4895	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
4896	{
4897	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
4898	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
4899	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
4900	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
4901	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
4902	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
4903	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
4904	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
4905	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
4906	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
4907	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
4908	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
4909	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
4910	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
4911	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
4912	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
4913	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
4914	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
4915	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
4916	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
4917	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
4918	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
4919	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
4920	DBGFREGSUBFIELD_RO("PCX_L2I\0" "L2I/L3 Performance Counter Extensions", 28, 1, 0),
4921	DBGFREGSUBFIELD_RO("MWAITX\0" "MWAITX and MONITORX instructions", 29, 1, 0),
4922	DBGFREGSUBFIELD_TERMINATOR()
4923	};
4924
4925	/** CPUID(0x8000000a,0).EDX field descriptions. */
4926	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
4927	{
4928	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
4929	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
4930	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
4931	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
4932	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
4933	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
4934	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
4935	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
4936	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
4937	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
4938	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
4939	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
4940	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
4941	DBGFREGSUBFIELD_RO("GMET\0" "Guest Mode Execute Trap Extension", 17, 1, 0),
4942	DBGFREGSUBFIELD_TERMINATOR()
4943	};
4944
4945
4946	/** CPUID(0x80000007,0).EDX field descriptions. */
4947	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
4948	{
4949	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
4950	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
4951	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
4952	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
4953	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
4954	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
4955	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
4956	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
4957	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
4958	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
4959	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
4960	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
4961	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
4962	DBGFREGSUBFIELD_TERMINATOR()
4963	};
4964
4965	/** CPUID(0x80000008,0).EBX field descriptions. */
4966	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
4967	{
4968	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
4969	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
4970	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
4971	DBGFREGSUBFIELD_RO("RDPRU\0" "RDPRU instruction", 4, 1, 0),
4972	DBGFREGSUBFIELD_RO("MCOMMIT\0" "MCOMMIT instruction", 8, 1, 0),
4973	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
4974	DBGFREGSUBFIELD_TERMINATOR()
4975	};
4976
4977
4978	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
4979	const char *pszLeadIn, uint32_t cchWidth)
4980	{
4981	if (pszLeadIn)
4982	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
4983
4984	for (uint32_t iBit = 0; iBit < 32; iBit++)
4985	if (RT_BIT_32(iBit) & uVal)
4986	{
4987	while ( pDesc->pszName != NULL
4988	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
4989	pDesc++;
4990	if ( pDesc->pszName != NULL
4991	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
4992	{
4993	if (pDesc->cBits == 1)
4994	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
4995	else
4996	{
4997	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
4998	if (pDesc->cBits < 32)
4999	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5000	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
5001	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5002	}
5003	}
5004	else
5005	pHlp->pfnPrintf(pHlp, " %u", iBit);
5006	}
5007	if (pszLeadIn)
5008	pHlp->pfnPrintf(pHlp, "\n");
5009	}
5010
5011
5012	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5013	const char *pszLeadIn, uint32_t cchWidth)
5014	{
5015	if (pszLeadIn)
5016	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5017
5018	for (uint32_t iBit = 0; iBit < 64; iBit++)
5019	if (RT_BIT_64(iBit) & uVal)
5020	{
5021	while ( pDesc->pszName != NULL
5022	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5023	pDesc++;
5024	if ( pDesc->pszName != NULL
5025	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5026	{
5027	if (pDesc->cBits == 1)
5028	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5029	else
5030	{
5031	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
5032	if (pDesc->cBits < 64)
5033	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
5034	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
5035	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5036	}
5037	}
5038	else
5039	pHlp->pfnPrintf(pHlp, " %u", iBit);
5040	}
5041	if (pszLeadIn)
5042	pHlp->pfnPrintf(pHlp, "\n");
5043	}
5044
5045
5046	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5047	const char *pszLeadIn, uint32_t cchWidth)
5048	{
5049	if (!uVal)
5050	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5051	else
5052	{
5053	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5054	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
5055	pHlp->pfnPrintf(pHlp, " )\n");
5056	}
5057	}
5058
5059
5060	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
5061	uint32_t cchWidth)
5062	{
5063	uint32_t uCombined = uVal1 \| uVal2;
5064	for (uint32_t iBit = 0; iBit < 32; iBit++)
5065	if ( (RT_BIT_32(iBit) & uCombined)
5066	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
5067	{
5068	while ( pDesc->pszName != NULL
5069	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5070	pDesc++;
5071
5072	if ( pDesc->pszName != NULL
5073	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5074	{
5075	size_t cchMnemonic = strlen(pDesc->pszName);
5076	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
5077	size_t cchDesc = strlen(pszDesc);
5078	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
5079	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
5080	if (pDesc->cBits < 32)
5081	{
5082	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5083	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5084	}
5085
5086	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
5087	pDesc->pszName, pszDesc,
5088	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
5089	uFieldValue1, uFieldValue2);
5090
5091	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
5092	pDesc++;
5093	}
5094	else
5095	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
5096	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
5097	}
5098	}
5099
5100
5101	/**
5102	* Produces a detailed summary of standard leaf 0x00000001.
5103	*
5104	* @param pHlp The info helper functions.
5105	* @param pCurLeaf The 0x00000001 leaf.
5106	* @param fVerbose Whether to be very verbose or not.
5107	* @param fIntel Set if intel CPU.
5108	*/
5109	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
5110	{
5111	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
5112	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
5113	uint32_t uEAX = pCurLeaf->uEax;
5114	uint32_t uEBX = pCurLeaf->uEbx;
5115
5116	pHlp->pfnPrintf(pHlp,
5117	"%36s %2d \tExtended: %d \tEffective: %d\n"
5118	"%36s %2d \tExtended: %d \tEffective: %d\n"
5119	"%36s %d\n"
5120	"%36s %d (%s)\n"
5121	"%36s %#04x\n"
5122	"%36s %d\n"
5123	"%36s %d\n"
5124	"%36s %#04x\n"
5125	,
5126	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
5127	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
5128	"Stepping:", RTX86GetCpuStepping(uEAX),
5129	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
5130	"APIC ID:", (uEBX >> 24) & 0xff,
5131	"Logical CPUs:",(uEBX >> 16) & 0xff,
5132	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
5133	"Brand ID:", (uEBX >> 0) & 0xff);
5134	if (fVerbose)
5135	{
5136	CPUMCPUID Host = {0};
5137	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5138	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5139	#endif
5140	pHlp->pfnPrintf(pHlp, "Features\n");
5141	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5142	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
5143	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
5144	}
5145	else
5146	{
5147	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
5148	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
5149	}
5150	}
5151
5152
5153	/**
5154	* Produces a detailed summary of standard leaf 0x00000007.
5155	*
5156	* @param pHlp The info helper functions.
5157	* @param paLeaves The CPUID leaves array.
5158	* @param cLeaves The number of leaves in the array.
5159	* @param pCurLeaf The first 0x00000007 leaf.
5160	* @param fVerbose Whether to be very verbose or not.
5161	*/
5162	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5163	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5164	{
5165	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
5166	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
5167	for (;;)
5168	{
5169	CPUMCPUID Host = {0};
5170	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5171	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5172	#endif
5173
5174	switch (pCurLeaf->uSubLeaf)
5175	{
5176	case 0:
5177	if (fVerbose)
5178	{
5179	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5180	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
5181	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
5182	if (pCurLeaf->uEdx \|\| Host.uEdx)
5183	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
5184	}
5185	else
5186	{
5187	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
5188	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
5189	if (pCurLeaf->uEdx)
5190	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
5191	}
5192	break;
5193
5194	default:
5195	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
5196	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
5197	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
5198	break;
5199
5200	}
5201
5202	/* advance. */
5203	pCurLeaf++;
5204	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5205	\|\| pCurLeaf->uLeaf != 0x7)
5206	break;
5207	}
5208	}
5209
5210
5211	/**
5212	* Produces a detailed summary of standard leaf 0x0000000d.
5213	*
5214	* @param pHlp The info helper functions.
5215	* @param paLeaves The CPUID leaves array.
5216	* @param cLeaves The number of leaves in the array.
5217	* @param pCurLeaf The first 0x00000007 leaf.
5218	* @param fVerbose Whether to be very verbose or not.
5219	*/
5220	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5221	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5222	{
5223	RT_NOREF_PV(fVerbose);
5224	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
5225	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
5226	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5227	{
5228	CPUMCPUID Host = {0};
5229	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5230	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5231	#endif
5232
5233	switch (uSubLeaf)
5234	{
5235	case 0:
5236	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5237	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
5238	pCurLeaf->uEbx, pCurLeaf->uEcx);
5239	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
5240
5241	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5242	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
5243	"Valid XCR0 bits, guest:", 42);
5244	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
5245	"Valid XCR0 bits, host:", 42);
5246	break;
5247
5248	case 1:
5249	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5250	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
5251	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
5252
5253	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5254	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
5255	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
5256
5257	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5258	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
5259	" Valid IA32_XSS bits, guest:", 42);
5260	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
5261	" Valid IA32_XSS bits, host:", 42);
5262	break;
5263
5264	default:
5265	if ( pCurLeaf
5266	&& pCurLeaf->uSubLeaf == uSubLeaf
5267	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
5268	{
5269	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
5270	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5271	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
5272	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
5273	if (pCurLeaf->uEdx)
5274	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
5275	pHlp->pfnPrintf(pHlp, " --");
5276	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5277	pHlp->pfnPrintf(pHlp, "\n");
5278	}
5279	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
5280	{
5281	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
5282	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5283	if (Host.uEcx & ~RT_BIT_32(0))
5284	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
5285	if (Host.uEdx)
5286	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
5287	pHlp->pfnPrintf(pHlp, " --");
5288	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5289	pHlp->pfnPrintf(pHlp, "\n");
5290	}
5291	break;
5292
5293	}
5294
5295	/* advance. */
5296	if (pCurLeaf)
5297	{
5298	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5299	&& pCurLeaf->uSubLeaf <= uSubLeaf
5300	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
5301	pCurLeaf++;
5302	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5303	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
5304	pCurLeaf = NULL;
5305	}
5306	}
5307	}
5308
5309
5310	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5311	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
5312	{
5313	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5314	&& pCurLeaf->uLeaf <= uUpToLeaf)
5315	{
5316	pHlp->pfnPrintf(pHlp,
5317	" %s\n"
5318	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
5319	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5320	&& pCurLeaf->uLeaf <= uUpToLeaf)
5321	{
5322	CPUMCPUID Host = {0};
5323	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5324	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5325	#endif
5326	pHlp->pfnPrintf(pHlp,
5327	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5328	"Hst: %08x %08x %08x %08x\n",
5329	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5330	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5331	pCurLeaf++;
5332	}
5333	}
5334
5335	return pCurLeaf;
5336	}
5337
5338
5339	/**
5340	* Display the guest CpuId leaves.
5341	*
5342	* @param pVM The cross context VM structure.
5343	* @param pHlp The info helper functions.
5344	* @param pszArgs "terse", "default" or "verbose".
5345	*/
5346	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
5347	{
5348	/*
5349	* Parse the argument.
5350	*/
5351	unsigned iVerbosity = 1;
5352	if (pszArgs)
5353	{
5354	pszArgs = RTStrStripL(pszArgs);
5355	if (!strcmp(pszArgs, "terse"))
5356	iVerbosity--;
5357	else if (!strcmp(pszArgs, "verbose"))
5358	iVerbosity++;
5359	}
5360
5361	uint32_t uLeaf;
5362	CPUMCPUID Host = {0};
5363	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
5364	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
5365	PCCPUMCPUIDLEAF pCurLeaf;
5366	PCCPUMCPUIDLEAF pNextLeaf;
5367	bool const fIntel = RTX86IsIntelCpu(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
5368	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
5369	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
5370
5371	/*
5372	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
5373	*/
5374	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5375	uint32_t cHstMax = ASMCpuId_EAX(0);
5376	#else
5377	uint32_t cHstMax = 0;
5378	#endif
5379	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
5380	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
5381	pHlp->pfnPrintf(pHlp,
5382	" Raw Standard CPUID Leaves\n"
5383	" Leaf/sub-leaf eax ebx ecx edx\n");
5384	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
5385	{
5386	uint32_t cMaxSubLeaves = 1;
5387	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
5388	cMaxSubLeaves = 16;
5389	else if (uLeaf == 0xd)
5390	cMaxSubLeaves = 128;
5391
5392	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5393	{
5394	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5395	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5396	#endif
5397	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5398	&& pCurLeaf->uLeaf == uLeaf
5399	&& pCurLeaf->uSubLeaf == uSubLeaf)
5400	{
5401	pHlp->pfnPrintf(pHlp,
5402	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5403	"Hst: %08x %08x %08x %08x\n",
5404	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5405	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5406	pCurLeaf++;
5407	}
5408	else if ( uLeaf != 0xd
5409	\|\| uSubLeaf <= 1
5410	\|\| Host.uEbx != 0 )
5411	pHlp->pfnPrintf(pHlp,
5412	"Hst: %08x/%04x %08x %08x %08x %08x\n",
5413	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5414
5415	/* Done? */
5416	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5417	\|\| pCurLeaf->uLeaf != uLeaf)
5418	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
5419	\|\| (uLeaf == 0x7 && Host.uEax == 0)
5420	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
5421	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
5422	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
5423	)
5424	)
5425	break;
5426	}
5427	}
5428	pNextLeaf = pCurLeaf;
5429
5430	/*
5431	* If verbose, decode it.
5432	*/
5433	if (iVerbosity && paLeaves[0].uLeaf == 0)
5434	pHlp->pfnPrintf(pHlp,
5435	"%36s %.04s%.04s%.04s\n"
5436	"%36s 0x00000000-%#010x\n"
5437	,
5438	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
5439	"Supports:", paLeaves[0].uEax);
5440
5441	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
5442	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
5443
5444	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
5445	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5446
5447	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
5448	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5449
5450	pCurLeaf = pNextLeaf;
5451
5452	/*
5453	* Hypervisor leaves.
5454	*
5455	* Unlike most of the other leaves reported, the guest hypervisor leaves
5456	* aren't a subset of the host CPUID bits.
5457	*/
5458	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
5459
5460	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5461	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5462	#endif
5463	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
5464	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
5465	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
5466	cMax = RT_MAX(cHstMax, cGstMax);
5467	if (cMax >= UINT32_C(0x40000000))
5468	{
5469	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
5470
5471	/** @todo dump these in more detail. */
5472
5473	pCurLeaf = pNextLeaf;
5474	}
5475
5476
5477	/*
5478	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
5479	* Implemented after AMD specs.
5480	*/
5481	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
5482
5483	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5484	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5485	#endif
5486	cHstMax = RTX86IsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
5487	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
5488	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
5489	cMax = RT_MAX(cHstMax, cGstMax);
5490	if (cMax >= UINT32_C(0x80000000))
5491	{
5492
5493	pHlp->pfnPrintf(pHlp,
5494	" Raw Extended CPUID Leaves\n"
5495	" Leaf/sub-leaf eax ebx ecx edx\n");
5496	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
5497	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
5498	{
5499	uint32_t cMaxSubLeaves = 1;
5500	if (uLeaf == UINT32_C(0x8000001d))
5501	cMaxSubLeaves = 16;
5502
5503	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5504	{
5505	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5506	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5507	#endif
5508	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5509	&& pCurLeaf->uLeaf == uLeaf
5510	&& pCurLeaf->uSubLeaf == uSubLeaf)
5511	{
5512	pHlp->pfnPrintf(pHlp,
5513	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5514	"Hst: %08x %08x %08x %08x\n",
5515	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5516	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5517	pCurLeaf++;
5518	}
5519	else if ( uLeaf != 0xd
5520	\|\| uSubLeaf <= 1
5521	\|\| Host.uEbx != 0 )
5522	pHlp->pfnPrintf(pHlp,
5523	"Hst: %08x/%04x %08x %08x %08x %08x\n",
5524	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5525
5526	/* Done? */
5527	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5528	\|\| pCurLeaf->uLeaf != uLeaf)
5529	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
5530	break;
5531	}
5532	}
5533	pNextLeaf = pCurLeaf;
5534
5535	/*
5536	* Understandable output
5537	*/
5538	if (iVerbosity)
5539	pHlp->pfnPrintf(pHlp,
5540	"Ext Name: %.4s%.4s%.4s\n"
5541	"Ext Supports: 0x80000000-%#010x\n",
5542	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
5543
5544	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
5545	if (iVerbosity && pCurLeaf)
5546	{
5547	uint32_t uEAX = pCurLeaf->uEax;
5548	pHlp->pfnPrintf(pHlp,
5549	"Family: %d \tExtended: %d \tEffective: %d\n"
5550	"Model: %d \tExtended: %d \tEffective: %d\n"
5551	"Stepping: %d\n"
5552	"Brand ID: %#05x\n",
5553	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
5554	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
5555	RTX86GetCpuStepping(uEAX),
5556	pCurLeaf->uEbx & 0xfff);
5557
5558	if (iVerbosity == 1)
5559	{
5560	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
5561	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
5562	}
5563	else
5564	{
5565	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5566	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5567	#endif
5568	pHlp->pfnPrintf(pHlp, "Ext Features\n");
5569	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5570	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
5571	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
5572	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
5573	{
5574	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
5575	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5576	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5577	#endif
5578	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
5579	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
5580	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
5581	}
5582	}
5583	}
5584
5585	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
5586	{
5587	char szString[443+1] = {0};
5588	uint32_t pu32 = (uint32_t )szString;
5589	*pu32++ = pCurLeaf->uEax;
5590	*pu32++ = pCurLeaf->uEbx;
5591	*pu32++ = pCurLeaf->uEcx;
5592	*pu32++ = pCurLeaf->uEdx;
5593	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
5594	if (pCurLeaf)
5595	{
5596	*pu32++ = pCurLeaf->uEax;
5597	*pu32++ = pCurLeaf->uEbx;
5598	*pu32++ = pCurLeaf->uEcx;
5599	*pu32++ = pCurLeaf->uEdx;
5600	}
5601	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
5602	if (pCurLeaf)
5603	{
5604	*pu32++ = pCurLeaf->uEax;
5605	*pu32++ = pCurLeaf->uEbx;
5606	*pu32++ = pCurLeaf->uEcx;
5607	*pu32++ = pCurLeaf->uEdx;
5608	}
5609	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
5610	}
5611
5612	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
5613	{
5614	uint32_t uEAX = pCurLeaf->uEax;
5615	uint32_t uEBX = pCurLeaf->uEbx;
5616	uint32_t uECX = pCurLeaf->uEcx;
5617	uint32_t uEDX = pCurLeaf->uEdx;
5618	char sz1[32];
5619	char sz2[32];
5620
5621	pHlp->pfnPrintf(pHlp,
5622	"TLB 2/4M Instr/Uni: %s %3d entries\n"
5623	"TLB 2/4M Data: %s %3d entries\n",
5624	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
5625	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
5626	pHlp->pfnPrintf(pHlp,
5627	"TLB 4K Instr/Uni: %s %3d entries\n"
5628	"TLB 4K Data: %s %3d entries\n",
5629	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
5630	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
5631	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
5632	"L1 Instr Cache Lines Per Tag: %d\n"
5633	"L1 Instr Cache Associativity: %s\n"
5634	"L1 Instr Cache Size: %d KB\n",
5635	(uEDX >> 0) & 0xff,
5636	(uEDX >> 8) & 0xff,
5637	getCacheAss((uEDX >> 16) & 0xff, sz1),
5638	(uEDX >> 24) & 0xff);
5639	pHlp->pfnPrintf(pHlp,
5640	"L1 Data Cache Line Size: %d bytes\n"
5641	"L1 Data Cache Lines Per Tag: %d\n"
5642	"L1 Data Cache Associativity: %s\n"
5643	"L1 Data Cache Size: %d KB\n",
5644	(uECX >> 0) & 0xff,
5645	(uECX >> 8) & 0xff,
5646	getCacheAss((uECX >> 16) & 0xff, sz1),
5647	(uECX >> 24) & 0xff);
5648	}
5649
5650	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
5651	{
5652	uint32_t uEAX = pCurLeaf->uEax;
5653	uint32_t uEBX = pCurLeaf->uEbx;
5654	uint32_t uEDX = pCurLeaf->uEdx;
5655
5656	pHlp->pfnPrintf(pHlp,
5657	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
5658	"L2 TLB 2/4M Data: %s %4d entries\n",
5659	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
5660	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
5661	pHlp->pfnPrintf(pHlp,
5662	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
5663	"L2 TLB 4K Data: %s %4d entries\n",
5664	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
5665	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
5666	pHlp->pfnPrintf(pHlp,
5667	"L2 Cache Line Size: %d bytes\n"
5668	"L2 Cache Lines Per Tag: %d\n"
5669	"L2 Cache Associativity: %s\n"
5670	"L2 Cache Size: %d KB\n",
5671	(uEDX >> 0) & 0xff,
5672	(uEDX >> 8) & 0xf,
5673	getL2CacheAss((uEDX >> 12) & 0xf),
5674	(uEDX >> 16) & 0xffff);
5675	}
5676
5677	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
5678	{
5679	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5680	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5681	#endif
5682	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
5683	{
5684	if (iVerbosity < 1)
5685	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
5686	else
5687	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
5688	}
5689	}
5690
5691	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
5692	if (pCurLeaf != NULL)
5693	{
5694	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5695	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5696	#endif
5697	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
5698	{
5699	if (iVerbosity < 1)
5700	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
5701	else
5702	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
5703	}
5704
5705	if (iVerbosity)
5706	{
5707	uint32_t uEAX = pCurLeaf->uEax;
5708	uint32_t uECX = pCurLeaf->uEcx;
5709
5710	/** @todo 0x80000008:EAX[23:16] is only defined for AMD. We'll get 0 on Intel. On
5711	* AMD if we get 0, the guest physical address width should be taken from
5712	* 0x80000008:EAX[7:0] instead. Guest Physical address width is relevant
5713	* for guests using nested paging. */
5714	pHlp->pfnPrintf(pHlp,
5715	"Physical Address Width: %d bits\n"
5716	"Virtual Address Width: %d bits\n"
5717	"Guest Physical Address Width: %d bits\n",
5718	(uEAX >> 0) & 0xff,
5719	(uEAX >> 8) & 0xff,
5720	(uEAX >> 16) & 0xff);
5721
5722	/** @todo 0x80000008:ECX is reserved on Intel (we'll get incorrect physical core
5723	* count here). */
5724	pHlp->pfnPrintf(pHlp,
5725	"Physical Core Count: %d\n",
5726	((uECX >> 0) & 0xff) + 1);
5727	}
5728	}
5729
5730	pCurLeaf = pNextLeaf;
5731	}
5732
5733
5734
5735	/*
5736	* Centaur.
5737	*/
5738	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
5739
5740	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5741	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5742	#endif
5743	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
5744	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
5745	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
5746	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
5747	cMax = RT_MAX(cHstMax, cGstMax);
5748	if (cMax >= UINT32_C(0xc0000000))
5749	{
5750	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
5751
5752	/*
5753	* Understandable output
5754	*/
5755	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
5756	pHlp->pfnPrintf(pHlp,
5757	"Centaur Supports: 0xc0000000-%#010x\n",
5758	pCurLeaf->uEax);
5759
5760	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
5761	{
5762	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5763	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5764	#endif
5765	uint32_t uEdxGst = pCurLeaf->uEdx;
5766	uint32_t uEdxHst = Host.uEdx;
5767
5768	if (iVerbosity == 1)
5769	{
5770	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
5771	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
5772	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
5773	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
5774	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
5775	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
5776	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
5777	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
5778	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
5779	/* possibly indicating MM/HE and MM/HE-E on older chips... */
5780	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
5781	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
5782	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
5783	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
5784	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
5785	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
5786	for (unsigned iBit = 14; iBit < 32; iBit++)
5787	if (uEdxGst & RT_BIT(iBit))
5788	pHlp->pfnPrintf(pHlp, " %d", iBit);
5789	pHlp->pfnPrintf(pHlp, "\n");
5790	}
5791	else
5792	{
5793	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
5794	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
5795	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
5796	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
5797	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
5798	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
5799	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
5800	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
5801	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
5802	/* possibly indicating MM/HE and MM/HE-E on older chips... */
5803	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
5804	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
5805	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
5806	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
5807	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
5808	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
5809	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
5810	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
5811	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
5812	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
5813	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
5814	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
5815	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
5816	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
5817	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
5818	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
5819	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
5820	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
5821	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
5822	for (unsigned iBit = 27; iBit < 32; iBit++)
5823	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
5824	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
5825	pHlp->pfnPrintf(pHlp, "\n");
5826	}
5827	}
5828
5829	pCurLeaf = pNextLeaf;
5830	}
5831
5832	/*
5833	* The remainder.
5834	*/
5835	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
5836	}
5837
5838	#endif /* !IN_VBOX_CPU_REPORT */
5839

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 94961

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