CPUMR3CpuId.cpp@ 94911

Last change on this file since 94911 was 94911, checked in by vboxsync, 3 years ago
VMM/CPUM: Don't set fNestedPagingAndFullGuestExec when using IEM as main execution engine. duh. bugref:9898
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 345.3 KB

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1	/* $Id: CPUMR3CpuId.cpp 94911 2022-05-08 15:46:51Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vmcc.h>
30	#include <VBox/sup.h>
31
32	#include <VBox/err.h>
33	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
34	# include <iprt/asm-amd64-x86.h>
35	#endif
36	#include <iprt/ctype.h>
37	#include <iprt/mem.h>
38	#include <iprt/string.h>
39	#include <iprt/x86-helpers.h>
40
41
42	/*********************************************************************************************************************************
43	* Defined Constants And Macros *
44	*********************************************************************************************************************************/
45	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
46	#define CPUM_CPUID_MAX_LEAVES 2048
47	/** Max size we accept for the XSAVE area.
48	* @see CPUMCTX::abXSave */
49	#define CPUM_MAX_XSAVE_AREA_SIZE (0x4000 - 0x300)
50	/* Min size we accept for the XSAVE area. */
51	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
52
53
54	/*********************************************************************************************************************************
55	* Global Variables *
56	*********************************************************************************************************************************/
57	/**
58	* The intel pentium family.
59	*/
60	static const CPUMMICROARCH g_aenmIntelFamily06[] =
61	{
62	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
63	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
64	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
65	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
66	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
67	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
68	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
69	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
70	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
71	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
72	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
73	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
74	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
75	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
76	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
77	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
78	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
81	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
82	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
83	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
84	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
85	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
86	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
87	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
88	/* [26(0x1a)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Nehalem-EP */
89	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
90	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
91	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
92	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
93	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
94	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
97	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
98	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
99	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
100	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
101	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
102	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
103	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
104	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
105	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
106	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
107	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
108	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
109	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
110	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
113	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
114	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
115	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
116	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
117	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
118	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
120	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
121	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
122	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
124	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
125	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
126	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
129	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
130	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
131	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
132	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
133	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
134	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
136	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
137	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
138	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
139	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
140	/* [78(0x4e)] = */ kCpumMicroarch_Intel_Core7_Skylake,
141	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Broadwell-E */
142	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
145	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
146	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
147	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu; skylake <= 4, cascade lake > 5 */
148	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
149	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
150	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
151	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
152	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
153	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
154	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
155	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
156	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
157	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
158	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
159	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
160	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
161	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
162	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
163	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
164	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
165	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
166	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
167	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
168	/[106(0x6a)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
169	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
170	/[108(0x6c)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
171	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
172	/[110(0x6e)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
173	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
174	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
175	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
176	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
177	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
178	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
179	/[117(0x75)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
180	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
181	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
182	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
183	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
184	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
185	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
186	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
187	/[125(0x7d)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
188	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
189	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
190	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
191	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
192	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
193	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
194	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
195	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
196	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
197	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
198	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
199	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
200	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
201	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
202	/[140(0x8c)] = / kCpumMicroarch_Intel_Core7_TigerLake, /* 11th Gen Intel(R) Core(TM) i7-1185G7 @ 3.00GHz (bird) */
203	/[141(0x8d)] = / kCpumMicroarch_Intel_Core7_TigerLake, /* unconfirmed */
204	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
205	/[143(0x8f)] = / kCpumMicroarch_Intel_Core7_SapphireRapids,
206	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
207	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
208	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
209	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
210	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
211	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
212	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
213	/[151(0x97)] = / kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
214	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
215	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
216	/[154(0x9a)] = / kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
217	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
218	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
219	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
220	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
221	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
222	/[160(0xa0)] = / kCpumMicroarch_Intel_Unknown,
223	/[161(0xa1)] = / kCpumMicroarch_Intel_Unknown,
224	/[162(0xa2)] = / kCpumMicroarch_Intel_Unknown,
225	/[163(0xa3)] = / kCpumMicroarch_Intel_Unknown,
226	/[164(0xa4)] = / kCpumMicroarch_Intel_Unknown,
227	/[165(0xa5)] = / kCpumMicroarch_Intel_Core7_CometLake, /* unconfirmed */
228	/[166(0xa6)] = / kCpumMicroarch_Intel_Unknown,
229	/[167(0xa7)] = / kCpumMicroarch_Intel_Core7_CypressCove, /* 14nm backport, unconfirmed */
230	};
231	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0xa7+1);
232
233
234	/**
235	* Figures out the (sub-)micro architecture given a bit of CPUID info.
236	*
237	* @returns Micro architecture.
238	* @param enmVendor The CPU vendor.
239	* @param bFamily The CPU family.
240	* @param bModel The CPU model.
241	* @param bStepping The CPU stepping.
242	*/
243	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
244	uint8_t bModel, uint8_t bStepping)
245	{
246	if (enmVendor == CPUMCPUVENDOR_AMD)
247	{
248	switch (bFamily)
249	{
250	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
251	case 0x03: return kCpumMicroarch_AMD_Am386;
252	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
253	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
254	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
255	case 0x06:
256	switch (bModel)
257	{
258	case 0: return kCpumMicroarch_AMD_K7_Palomino;
259	case 1: return kCpumMicroarch_AMD_K7_Palomino;
260	case 2: return kCpumMicroarch_AMD_K7_Palomino;
261	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
262	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
263	case 6: return kCpumMicroarch_AMD_K7_Palomino;
264	case 7: return kCpumMicroarch_AMD_K7_Morgan;
265	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
266	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
267	}
268	return kCpumMicroarch_AMD_K7_Unknown;
269	case 0x0f:
270	/*
271	* This family is a friggin mess. Trying my best to make some
272	* sense out of it. Too much happened in the 0x0f family to
273	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
274	*
275	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
276	* cpu-world.com, and other places:
277	* - 130nm:
278	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
279	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
280	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
281	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
282	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
283	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
284	* - 90nm:
285	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
286	* - Oakville: 10FC0/DH-D0.
287	* - Georgetown: 10FC0/DH-D0.
288	* - Sonora: 10FC0/DH-D0.
289	* - Venus: 20F71/SH-E4
290	* - Troy: 20F51/SH-E4
291	* - Athens: 20F51/SH-E4
292	* - San Diego: 20F71/SH-E4.
293	* - Lancaster: 20F42/SH-E5
294	* - Newark: 20F42/SH-E5.
295	* - Albany: 20FC2/DH-E6.
296	* - Roma: 20FC2/DH-E6.
297	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
298	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
299	* - 90nm introducing Dual core:
300	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
301	* - Italy: 20F10/JH-E1, 20F12/JH-E6
302	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
303	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
304	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
305	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
306	* - Santa Ana: 40F32/JH-F2, /-F3
307	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
308	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
309	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
310	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
311	* - Keene: 40FC2/DH-F2.
312	* - Richmond: 40FC2/DH-F2
313	* - Taylor: 40F82/BH-F2
314	* - Trinidad: 40F82/BH-F2
315	*
316	* - 65nm:
317	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
318	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
319	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
320	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
321	* - Sherman: /-G1, 70FC2/DH-G2.
322	* - Huron: 70FF2/DH-G2.
323	*/
324	if (bModel < 0x10)
325	return kCpumMicroarch_AMD_K8_130nm;
326	if (bModel >= 0x60 && bModel < 0x80)
327	return kCpumMicroarch_AMD_K8_65nm;
328	if (bModel >= 0x40)
329	return kCpumMicroarch_AMD_K8_90nm_AMDV;
330	switch (bModel)
331	{
332	case 0x21:
333	case 0x23:
334	case 0x2b:
335	case 0x2f:
336	case 0x37:
337	case 0x3f:
338	return kCpumMicroarch_AMD_K8_90nm_DualCore;
339	}
340	return kCpumMicroarch_AMD_K8_90nm;
341	case 0x10:
342	return kCpumMicroarch_AMD_K10;
343	case 0x11:
344	return kCpumMicroarch_AMD_K10_Lion;
345	case 0x12:
346	return kCpumMicroarch_AMD_K10_Llano;
347	case 0x14:
348	return kCpumMicroarch_AMD_Bobcat;
349	case 0x15:
350	switch (bModel)
351	{
352	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
353	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
354	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
355	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
356	case 0x11: /* ?? */
357	case 0x12: /* ?? */
358	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
359	}
360	return kCpumMicroarch_AMD_15h_Unknown;
361	case 0x16:
362	return kCpumMicroarch_AMD_Jaguar;
363	case 0x17:
364	return kCpumMicroarch_AMD_Zen_Ryzen;
365	}
366	return kCpumMicroarch_AMD_Unknown;
367	}
368
369	if (enmVendor == CPUMCPUVENDOR_INTEL)
370	{
371	switch (bFamily)
372	{
373	case 3:
374	return kCpumMicroarch_Intel_80386;
375	case 4:
376	return kCpumMicroarch_Intel_80486;
377	case 5:
378	return kCpumMicroarch_Intel_P5;
379	case 6:
380	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
381	{
382	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
383	if (enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake)
384	{
385	if (bStepping >= 0xa && bStepping <= 0xc)
386	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
387	else if (bStepping >= 0xc)
388	enmMicroArch = kCpumMicroarch_Intel_Core7_WhiskeyLake;
389	}
390	else if ( enmMicroArch == kCpumMicroarch_Intel_Core7_Skylake
391	&& bModel == 0x55
392	&& bStepping >= 5)
393	enmMicroArch = kCpumMicroarch_Intel_Core7_CascadeLake;
394	return enmMicroArch;
395	}
396	return kCpumMicroarch_Intel_Atom_Unknown;
397	case 15:
398	switch (bModel)
399	{
400	case 0: return kCpumMicroarch_Intel_NB_Willamette;
401	case 1: return kCpumMicroarch_Intel_NB_Willamette;
402	case 2: return kCpumMicroarch_Intel_NB_Northwood;
403	case 3: return kCpumMicroarch_Intel_NB_Prescott;
404	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
405	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
406	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
407	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
408	default: return kCpumMicroarch_Intel_NB_Unknown;
409	}
410	break;
411	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
412	case 0:
413	return kCpumMicroarch_Intel_8086;
414	case 1:
415	return kCpumMicroarch_Intel_80186;
416	case 2:
417	return kCpumMicroarch_Intel_80286;
418	}
419	return kCpumMicroarch_Intel_Unknown;
420	}
421
422	if (enmVendor == CPUMCPUVENDOR_VIA)
423	{
424	switch (bFamily)
425	{
426	case 5:
427	switch (bModel)
428	{
429	case 1: return kCpumMicroarch_Centaur_C6;
430	case 4: return kCpumMicroarch_Centaur_C6;
431	case 8: return kCpumMicroarch_Centaur_C2;
432	case 9: return kCpumMicroarch_Centaur_C3;
433	}
434	break;
435
436	case 6:
437	switch (bModel)
438	{
439	case 5: return kCpumMicroarch_VIA_C3_M2;
440	case 6: return kCpumMicroarch_VIA_C3_C5A;
441	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
442	case 8: return kCpumMicroarch_VIA_C3_C5N;
443	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
444	case 10: return kCpumMicroarch_VIA_C7_C5J;
445	case 15: return kCpumMicroarch_VIA_Isaiah;
446	}
447	break;
448	}
449	return kCpumMicroarch_VIA_Unknown;
450	}
451
452	if (enmVendor == CPUMCPUVENDOR_SHANGHAI)
453	{
454	switch (bFamily)
455	{
456	case 6:
457	case 7:
458	return kCpumMicroarch_Shanghai_Wudaokou;
459	default:
460	break;
461	}
462	return kCpumMicroarch_Shanghai_Unknown;
463	}
464
465	if (enmVendor == CPUMCPUVENDOR_CYRIX)
466	{
467	switch (bFamily)
468	{
469	case 4:
470	switch (bModel)
471	{
472	case 9: return kCpumMicroarch_Cyrix_5x86;
473	}
474	break;
475
476	case 5:
477	switch (bModel)
478	{
479	case 2: return kCpumMicroarch_Cyrix_M1;
480	case 4: return kCpumMicroarch_Cyrix_MediaGX;
481	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
482	}
483	break;
484
485	case 6:
486	switch (bModel)
487	{
488	case 0: return kCpumMicroarch_Cyrix_M2;
489	}
490	break;
491
492	}
493	return kCpumMicroarch_Cyrix_Unknown;
494	}
495
496	if (enmVendor == CPUMCPUVENDOR_HYGON)
497	{
498	switch (bFamily)
499	{
500	case 0x18:
501	return kCpumMicroarch_Hygon_Dhyana;
502	default:
503	break;
504	}
505	return kCpumMicroarch_Hygon_Unknown;
506	}
507
508	return kCpumMicroarch_Unknown;
509	}
510
511
512	/**
513	* Translates a microarchitecture enum value to the corresponding string
514	* constant.
515	*
516	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
517	* NULL if the value is invalid.
518	*
519	* @param enmMicroarch The enum value to convert.
520	*/
521	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
522	{
523	switch (enmMicroarch)
524	{
525	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
526	CASE_RET_STR(kCpumMicroarch_Intel_8086);
527	CASE_RET_STR(kCpumMicroarch_Intel_80186);
528	CASE_RET_STR(kCpumMicroarch_Intel_80286);
529	CASE_RET_STR(kCpumMicroarch_Intel_80386);
530	CASE_RET_STR(kCpumMicroarch_Intel_80486);
531	CASE_RET_STR(kCpumMicroarch_Intel_P5);
532
533	CASE_RET_STR(kCpumMicroarch_Intel_P6);
534	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
535	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
536
537	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
538	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
539	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
540
541	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
542	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
543
544	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
545	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
546	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
547	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
548	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
549	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
550	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
551	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
552	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
553	CASE_RET_STR(kCpumMicroarch_Intel_Core7_WhiskeyLake);
554	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CascadeLake);
555	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
556	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CometLake);
557	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
558	CASE_RET_STR(kCpumMicroarch_Intel_Core7_RocketLake);
559	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
560	CASE_RET_STR(kCpumMicroarch_Intel_Core7_AlderLake);
561	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SapphireRapids);
562
563	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
564	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
565	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
566	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
567	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
568	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
569	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
570	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
571
572	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
573	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
574	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
575	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
576	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
577
578	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
579	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
580	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
581	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
582	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
583	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
584	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
585
586	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
587
588	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
589	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
590	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
591	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
592	CASE_RET_STR(kCpumMicroarch_AMD_K5);
593	CASE_RET_STR(kCpumMicroarch_AMD_K6);
594
595	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
596	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
597	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
598	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
599	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
600	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
601	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
602
603	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
604	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
605	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
606	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
607	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
608
609	CASE_RET_STR(kCpumMicroarch_AMD_K10);
610	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
611	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
612	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
613	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
614
615	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
616	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
617	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
618	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
619	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
620
621	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
622
623	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
624
625	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
626
627	CASE_RET_STR(kCpumMicroarch_Hygon_Dhyana);
628	CASE_RET_STR(kCpumMicroarch_Hygon_Unknown);
629
630	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
631	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
632	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
633	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
634	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
635	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
636	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
637	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
638	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
639	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
640	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
641	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
642	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
643
644	CASE_RET_STR(kCpumMicroarch_Shanghai_Wudaokou);
645	CASE_RET_STR(kCpumMicroarch_Shanghai_Unknown);
646
647	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
648	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
649	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
650	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
651	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
652	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
653
654	CASE_RET_STR(kCpumMicroarch_NEC_V20);
655	CASE_RET_STR(kCpumMicroarch_NEC_V30);
656
657	CASE_RET_STR(kCpumMicroarch_Unknown);
658
659	#undef CASE_RET_STR
660	case kCpumMicroarch_Invalid:
661	case kCpumMicroarch_Intel_End:
662	case kCpumMicroarch_Intel_Core2_End:
663	case kCpumMicroarch_Intel_Core7_End:
664	case kCpumMicroarch_Intel_Atom_End:
665	case kCpumMicroarch_Intel_P6_Core_Atom_End:
666	case kCpumMicroarch_Intel_Phi_End:
667	case kCpumMicroarch_Intel_NB_End:
668	case kCpumMicroarch_AMD_K7_End:
669	case kCpumMicroarch_AMD_K8_End:
670	case kCpumMicroarch_AMD_15h_End:
671	case kCpumMicroarch_AMD_16h_End:
672	case kCpumMicroarch_AMD_Zen_End:
673	case kCpumMicroarch_AMD_End:
674	case kCpumMicroarch_Hygon_End:
675	case kCpumMicroarch_VIA_End:
676	case kCpumMicroarch_Shanghai_End:
677	case kCpumMicroarch_Cyrix_End:
678	case kCpumMicroarch_NEC_End:
679	case kCpumMicroarch_32BitHack:
680	break;
681	/* no default! */
682	}
683
684	return NULL;
685	}
686
687
688	/**
689	* Determins the host CPU MXCSR mask.
690	*
691	* @returns MXCSR mask.
692	*/
693	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
694	{
695	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
696	if ( ASMHasCpuId()
697	&& RTX86IsValidStdRange(ASMCpuId_EAX(0))
698	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
699	{
700	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
701	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
702	RT_ZERO(*pState);
703	ASMFxSave(pState);
704	if (pState->MXCSR_MASK == 0)
705	return 0xffbf;
706	return pState->MXCSR_MASK;
707	}
708	#endif
709	return 0;
710	}
711
712
713	/**
714	* Gets a matching leaf in the CPUID leaf array.
715	*
716	* @returns Pointer to the matching leaf, or NULL if not found.
717	* @param paLeaves The CPUID leaves to search. This is sorted.
718	* @param cLeaves The number of leaves in the array.
719	* @param uLeaf The leaf to locate.
720	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
721	*/
722	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
723	{
724	/* Lazy bird does linear lookup here since this is only used for the
725	occational CPUID overrides. */
726	for (uint32_t i = 0; i < cLeaves; i++)
727	if ( paLeaves[i].uLeaf == uLeaf
728	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
729	return &paLeaves[i];
730	return NULL;
731	}
732
733
734	#ifndef IN_VBOX_CPU_REPORT
735	/**
736	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
737	*
738	* @returns true if found, false it not.
739	* @param paLeaves The CPUID leaves to search. This is sorted.
740	* @param cLeaves The number of leaves in the array.
741	* @param uLeaf The leaf to locate.
742	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
743	* @param pLegacy The legacy output leaf.
744	*/
745	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
746	PCPUMCPUID pLegacy)
747	{
748	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
749	if (pLeaf)
750	{
751	pLegacy->uEax = pLeaf->uEax;
752	pLegacy->uEbx = pLeaf->uEbx;
753	pLegacy->uEcx = pLeaf->uEcx;
754	pLegacy->uEdx = pLeaf->uEdx;
755	return true;
756	}
757	return false;
758	}
759	#endif /* IN_VBOX_CPU_REPORT */
760
761
762	/**
763	* Ensures that the CPUID leaf array can hold one more leaf.
764	*
765	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
766	* failure.
767	* @param pVM The cross context VM structure. If NULL, use
768	* the process heap, otherwise the VM's hyper heap.
769	* @param ppaLeaves Pointer to the variable holding the array pointer
770	* (input/output).
771	* @param cLeaves The current array size.
772	*
773	* @remarks This function will automatically update the R0 and RC pointers when
774	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
775	* be the corresponding VM's CPUID arrays (which is asserted).
776	*/
777	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
778	{
779	/*
780	* If pVM is not specified, we're on the regular heap and can waste a
781	* little space to speed things up.
782	*/
783	uint32_t cAllocated;
784	if (!pVM)
785	{
786	cAllocated = RT_ALIGN(cLeaves, 16);
787	if (cLeaves + 1 > cAllocated)
788	{
789	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
790	if (pvNew)
791	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
792	else
793	{
794	RTMemFree(*ppaLeaves);
795	*ppaLeaves = NULL;
796	}
797	}
798	}
799	/*
800	* Otherwise, we're on the hyper heap and are probably just inserting
801	* one or two leaves and should conserve space.
802	*/
803	else
804	{
805	#ifdef IN_VBOX_CPU_REPORT
806	AssertReleaseFailed();
807	#else
808	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
809	Assert(*ppaLeaves == pVM->cpum.s.GuestInfo.aCpuIdLeaves);
810	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
811
812	if (cLeaves + 1 <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves))
813	{ }
814	else
815	{
816	*ppaLeaves = NULL;
817	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: Out of CPUID space!\n"));
818	}
819	#endif
820	}
821	return *ppaLeaves;
822	}
823
824
825	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
826	/**
827	* Append a CPUID leaf or sub-leaf.
828	*
829	* ASSUMES linear insertion order, so we'll won't need to do any searching or
830	* replace anything. Use cpumR3CpuIdInsert() for those cases.
831	*
832	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
833	* the caller need do no more work.
834	* @param ppaLeaves Pointer to the pointer to the array of sorted
835	* CPUID leaves and sub-leaves.
836	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
837	* @param uLeaf The leaf we're adding.
838	* @param uSubLeaf The sub-leaf number.
839	* @param fSubLeafMask The sub-leaf mask.
840	* @param uEax The EAX value.
841	* @param uEbx The EBX value.
842	* @param uEcx The ECX value.
843	* @param uEdx The EDX value.
844	* @param fFlags The flags.
845	*/
846	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
847	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
848	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
849	{
850	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
851	return VERR_NO_MEMORY;
852
853	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
854	Assert( *pcLeaves == 0
855	\|\| pNew[-1].uLeaf < uLeaf
856	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
857
858	pNew->uLeaf = uLeaf;
859	pNew->uSubLeaf = uSubLeaf;
860	pNew->fSubLeafMask = fSubLeafMask;
861	pNew->uEax = uEax;
862	pNew->uEbx = uEbx;
863	pNew->uEcx = uEcx;
864	pNew->uEdx = uEdx;
865	pNew->fFlags = fFlags;
866
867	*pcLeaves += 1;
868	return VINF_SUCCESS;
869	}
870	#endif /* RT_ARCH_X86 \|\| RT_ARCH_AMD64 */
871
872
873	/**
874	* Checks that we've updated the CPUID leaves array correctly.
875	*
876	* This is a no-op in non-strict builds.
877	*
878	* @param paLeaves The leaves array.
879	* @param cLeaves The number of leaves.
880	*/
881	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
882	{
883	#ifdef VBOX_STRICT
884	for (uint32_t i = 1; i < cLeaves; i++)
885	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
886	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
887	else
888	{
889	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
890	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
891	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
892	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
893	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
894	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
895	}
896	#else
897	NOREF(paLeaves);
898	NOREF(cLeaves);
899	#endif
900	}
901
902
903	/**
904	* Inserts a CPU ID leaf, replacing any existing ones.
905	*
906	* When inserting a simple leaf where we already got a series of sub-leaves with
907	* the same leaf number (eax), the simple leaf will replace the whole series.
908	*
909	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
910	* host-context heap and has only been allocated/reallocated by the
911	* cpumR3CpuIdEnsureSpace function.
912	*
913	* @returns VBox status code.
914	* @param pVM The cross context VM structure. If NULL, use
915	* the process heap, otherwise the VM's hyper heap.
916	* @param ppaLeaves Pointer to the pointer to the array of sorted
917	* CPUID leaves and sub-leaves. Must be NULL if using
918	* the hyper heap.
919	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
920	* be NULL if using the hyper heap.
921	* @param pNewLeaf Pointer to the data of the new leaf we're about to
922	* insert.
923	*/
924	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
925	{
926	/*
927	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
928	*/
929	if (pVM)
930	{
931	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
932	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
933	AssertReturn(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 == pVM->cpum.s.GuestInfo.aCpuIdLeaves, VERR_INVALID_PARAMETER);
934
935	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
936	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
937	}
938
939	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
940	uint32_t cLeaves = *pcLeaves;
941
942	/*
943	* Validate the new leaf a little.
944	*/
945	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
946	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
947	VERR_INVALID_FLAGS);
948	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
949	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
950	VERR_INVALID_PARAMETER);
951	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
952	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
953	VERR_INVALID_PARAMETER);
954	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
955	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
956	VERR_INVALID_PARAMETER);
957
958	/*
959	* Find insertion point. The lazy bird uses the same excuse as in
960	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
961	*/
962	uint32_t i;
963	if ( cLeaves > 0
964	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
965	{
966	/* Add at end. */
967	i = cLeaves;
968	}
969	else if ( cLeaves > 0
970	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
971	{
972	/* Either replacing the last leaf or dealing with sub-leaves. Spool
973	back to the first sub-leaf to pretend we did the linear search. */
974	i = cLeaves - 1;
975	while ( i > 0
976	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
977	i--;
978	}
979	else
980	{
981	/* Linear search from the start. */
982	i = 0;
983	while ( i < cLeaves
984	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
985	i++;
986	}
987	if ( i < cLeaves
988	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
989	{
990	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
991	{
992	/*
993	* The sub-leaf mask differs, replace all existing leaves with the
994	* same leaf number.
995	*/
996	uint32_t c = 1;
997	while ( i + c < cLeaves
998	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
999	c++;
1000	if (c > 1 && i + c < cLeaves)
1001	{
1002	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
1003	*pcLeaves = cLeaves -= c - 1;
1004	}
1005
1006	paLeaves[i] = *pNewLeaf;
1007	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1008	return VINF_SUCCESS;
1009	}
1010
1011	/* Find sub-leaf insertion point. */
1012	while ( i < cLeaves
1013	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
1014	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
1015	i++;
1016
1017	/*
1018	* If we've got an exactly matching leaf, replace it.
1019	*/
1020	if ( i < cLeaves
1021	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
1022	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
1023	{
1024	paLeaves[i] = *pNewLeaf;
1025	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1026	return VINF_SUCCESS;
1027	}
1028	}
1029
1030	/*
1031	* Adding a new leaf at 'i'.
1032	*/
1033	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
1034	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
1035	if (!paLeaves)
1036	return VERR_NO_MEMORY;
1037
1038	if (i < cLeaves)
1039	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
1040	*pcLeaves += 1;
1041	paLeaves[i] = *pNewLeaf;
1042
1043	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1044	return VINF_SUCCESS;
1045	}
1046
1047
1048	#ifndef IN_VBOX_CPU_REPORT
1049	/**
1050	* Removes a range of CPUID leaves.
1051	*
1052	* This will not reallocate the array.
1053	*
1054	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1055	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1056	* @param uFirst The first leaf.
1057	* @param uLast The last leaf.
1058	*/
1059	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1060	{
1061	uint32_t cLeaves = *pcLeaves;
1062
1063	Assert(uFirst <= uLast);
1064
1065	/*
1066	* Find the first one.
1067	*/
1068	uint32_t iFirst = 0;
1069	while ( iFirst < cLeaves
1070	&& paLeaves[iFirst].uLeaf < uFirst)
1071	iFirst++;
1072
1073	/*
1074	* Find the end (last + 1).
1075	*/
1076	uint32_t iEnd = iFirst;
1077	while ( iEnd < cLeaves
1078	&& paLeaves[iEnd].uLeaf <= uLast)
1079	iEnd++;
1080
1081	/*
1082	* Adjust the array if anything needs removing.
1083	*/
1084	if (iFirst < iEnd)
1085	{
1086	if (iEnd < cLeaves)
1087	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1088	*pcLeaves = cLeaves -= (iEnd - iFirst);
1089	}
1090
1091	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1092	}
1093	#endif /* IN_VBOX_CPU_REPORT */
1094
1095
1096	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
1097	/**
1098	* Checks if ECX make a difference when reading a given CPUID leaf.
1099	*
1100	* @returns @c true if it does, @c false if it doesn't.
1101	* @param uLeaf The leaf we're reading.
1102	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1103	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1104	* final sub-leaf (for leaf 0xb only).
1105	*/
1106	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1107	{
1108	*pfFinalEcxUnchanged = false;
1109
1110	uint32_t auCur[4];
1111	uint32_t auPrev[4];
1112	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1113
1114	/* Look for sub-leaves. */
1115	uint32_t uSubLeaf = 1;
1116	for (;;)
1117	{
1118	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1119	if (memcmp(auCur, auPrev, sizeof(auCur)))
1120	break;
1121
1122	/* Advance / give up. */
1123	uSubLeaf++;
1124	if (uSubLeaf >= 64)
1125	{
1126	*pcSubLeaves = 1;
1127	return false;
1128	}
1129	}
1130
1131	/* Count sub-leaves. */
1132	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1133	uint32_t cRepeats = 0;
1134	uSubLeaf = 0;
1135	for (;;)
1136	{
1137	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1138
1139	/* Figuring out when to stop isn't entirely straight forward as we need
1140	to cover undocumented behavior up to a point and implementation shortcuts. */
1141
1142	/* 1. Look for more than 4 repeating value sets. */
1143	if ( auCur[0] == auPrev[0]
1144	&& auCur[1] == auPrev[1]
1145	&& ( auCur[2] == auPrev[2]
1146	\|\| ( auCur[2] == uSubLeaf
1147	&& auPrev[2] == uSubLeaf - 1) )
1148	&& auCur[3] == auPrev[3])
1149	{
1150	if ( uLeaf != 0xd
1151	\|\| uSubLeaf >= 64
1152	\|\| ( auCur[0] == 0
1153	&& auCur[1] == 0
1154	&& auCur[2] == 0
1155	&& auCur[3] == 0
1156	&& auPrev[2] == 0) )
1157	cRepeats++;
1158	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1159	break;
1160	}
1161	else
1162	cRepeats = 0;
1163
1164	/* 2. Look for zero values. */
1165	if ( auCur[0] == 0
1166	&& auCur[1] == 0
1167	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1168	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1169	&& uSubLeaf >= cMinLeaves)
1170	{
1171	cRepeats = 0;
1172	break;
1173	}
1174
1175	/* 3. Leaf 0xb level type 0 check. */
1176	if ( uLeaf == 0xb
1177	&& (auCur[2] & 0xff00) == 0
1178	&& (auPrev[2] & 0xff00) == 0)
1179	{
1180	cRepeats = 0;
1181	break;
1182	}
1183
1184	/* 99. Give up. */
1185	if (uSubLeaf >= 128)
1186	{
1187	# ifndef IN_VBOX_CPU_REPORT
1188	/* Ok, limit it according to the documentation if possible just to
1189	avoid annoying users with these detection issues. */
1190	uint32_t cDocLimit = UINT32_MAX;
1191	if (uLeaf == 0x4)
1192	cDocLimit = 4;
1193	else if (uLeaf == 0x7)
1194	cDocLimit = 1;
1195	else if (uLeaf == 0xd)
1196	cDocLimit = 63;
1197	else if (uLeaf == 0xf)
1198	cDocLimit = 2;
1199	if (cDocLimit != UINT32_MAX)
1200	{
1201	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1202	*pcSubLeaves = cDocLimit + 3;
1203	return true;
1204	}
1205	# endif
1206	*pcSubLeaves = UINT32_MAX;
1207	return true;
1208	}
1209
1210	/* Advance. */
1211	uSubLeaf++;
1212	memcpy(auPrev, auCur, sizeof(auCur));
1213	}
1214
1215	/* Standard exit. */
1216	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1217	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1218	if (*pcSubLeaves == 0)
1219	*pcSubLeaves = 1;
1220	return true;
1221	}
1222	#endif /* RT_ARCH_X86 \|\| RT_ARCH_AMD64 */
1223
1224
1225	/**
1226	* Gets a CPU ID leaf.
1227	*
1228	* @returns VBox status code.
1229	* @param pVM The cross context VM structure.
1230	* @param pLeaf Where to store the found leaf.
1231	* @param uLeaf The leaf to locate.
1232	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1233	*/
1234	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1235	{
1236	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1237	uLeaf, uSubLeaf);
1238	if (pcLeaf)
1239	{
1240	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1241	return VINF_SUCCESS;
1242	}
1243
1244	return VERR_NOT_FOUND;
1245	}
1246
1247
1248	/**
1249	* Gets all the leaves.
1250	*
1251	* This only works after the CPUID leaves have been initialized. The interface
1252	* is intended for NEM and configuring CPUID leaves for the native hypervisor.
1253	*
1254	* @returns Pointer to the array of leaves. NULL on failure.
1255	* @param pVM The cross context VM structure.
1256	* @param pcLeaves Where to return the number of leaves.
1257	*/
1258	VMMR3_INT_DECL(PCCPUMCPUIDLEAF) CPUMR3CpuIdGetPtr(PVM pVM, uint32_t *pcLeaves)
1259	{
1260	*pcLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
1261	return pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
1262	}
1263
1264
1265	/**
1266	* Inserts a CPU ID leaf, replacing any existing ones.
1267	*
1268	* @returns VBox status code.
1269	* @param pVM The cross context VM structure.
1270	* @param pNewLeaf Pointer to the leaf being inserted.
1271	*/
1272	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1273	{
1274	/*
1275	* Validate parameters.
1276	*/
1277	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1278	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1279
1280	/*
1281	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1282	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1283	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1284	*/
1285	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1286	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1287	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1288	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1289	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1290	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1291	{
1292	return VERR_NOT_SUPPORTED;
1293	}
1294
1295	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1296	}
1297
1298	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
1299
1300	/**
1301	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1302	*
1303	* @returns VBox status code.
1304	* @param ppaLeaves Where to return the array pointer on success.
1305	* Use RTMemFree to release.
1306	* @param pcLeaves Where to return the size of the array on
1307	* success.
1308	*/
1309	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1310	{
1311	*ppaLeaves = NULL;
1312	*pcLeaves = 0;
1313
1314	/*
1315	* Try out various candidates. This must be sorted!
1316	*/
1317	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1318	{
1319	{ UINT32_C(0x00000000), false },
1320	{ UINT32_C(0x10000000), false },
1321	{ UINT32_C(0x20000000), false },
1322	{ UINT32_C(0x30000000), false },
1323	{ UINT32_C(0x40000000), false },
1324	{ UINT32_C(0x50000000), false },
1325	{ UINT32_C(0x60000000), false },
1326	{ UINT32_C(0x70000000), false },
1327	{ UINT32_C(0x80000000), false },
1328	{ UINT32_C(0x80860000), false },
1329	{ UINT32_C(0x8ffffffe), true },
1330	{ UINT32_C(0x8fffffff), true },
1331	{ UINT32_C(0x90000000), false },
1332	{ UINT32_C(0xa0000000), false },
1333	{ UINT32_C(0xb0000000), false },
1334	{ UINT32_C(0xc0000000), false },
1335	{ UINT32_C(0xd0000000), false },
1336	{ UINT32_C(0xe0000000), false },
1337	{ UINT32_C(0xf0000000), false },
1338	};
1339
1340	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1341	{
1342	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1343	uint32_t uEax, uEbx, uEcx, uEdx;
1344	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1345
1346	/*
1347	* Does EAX look like a typical leaf count value?
1348	*/
1349	if ( uEax > uLeaf
1350	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1351	{
1352	/* Yes, dump them. */
1353	uint32_t cLeaves = uEax - uLeaf + 1;
1354	while (cLeaves-- > 0)
1355	{
1356	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1357
1358	uint32_t fFlags = 0;
1359
1360	/* There are currently three known leaves containing an APIC ID
1361	that needs EMT specific attention */
1362	if (uLeaf == 1)
1363	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1364	else if (uLeaf == 0xb && uEcx != 0)
1365	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1366	else if ( uLeaf == UINT32_C(0x8000001e)
1367	&& ( uEax
1368	\|\| uEbx
1369	\|\| uEdx
1370	\|\| RTX86IsAmdCpu((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1371	\|\| RTX86IsHygonCpu((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1372	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1373
1374	/* The APIC bit is per-VCpu and needs flagging. */
1375	if (uLeaf == 1)
1376	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1377	else if ( uLeaf == UINT32_C(0x80000001)
1378	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1379	\|\| RTX86IsAmdCpu((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1380	\|\| RTX86IsHygonCpu((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1381	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1382
1383	/* Check three times here to reduce the chance of CPU migration
1384	resulting in false positives with things like the APIC ID. */
1385	uint32_t cSubLeaves;
1386	bool fFinalEcxUnchanged;
1387	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1388	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1389	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1390	{
1391	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1392	{
1393	/* This shouldn't happen. But in case it does, file all
1394	relevant details in the release log. */
1395	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1396	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1397	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1398	{
1399	uint32_t auTmp[4];
1400	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1401	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1402	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1403	}
1404	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1405	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1406	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1407	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1408	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1409	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1410	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1411	}
1412
1413	if (fFinalEcxUnchanged)
1414	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1415
1416	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1417	{
1418	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1419	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1420	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1421	if (RT_FAILURE(rc))
1422	return rc;
1423	}
1424	}
1425	else
1426	{
1427	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1428	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1429	if (RT_FAILURE(rc))
1430	return rc;
1431	}
1432
1433	/* next */
1434	uLeaf++;
1435	}
1436	}
1437	/*
1438	* Special CPUIDs needs special handling as they don't follow the
1439	* leaf count principle used above.
1440	*/
1441	else if (s_aCandidates[iOuter].fSpecial)
1442	{
1443	bool fKeep = false;
1444	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1445	fKeep = true;
1446	else if ( uLeaf == 0x8fffffff
1447	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1448	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1449	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1450	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1451	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1452	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1453	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1454	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1455	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1456	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1457	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1458	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1459	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1460	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1461	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1462	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1463	fKeep = true;
1464	if (fKeep)
1465	{
1466	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1467	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1468	if (RT_FAILURE(rc))
1469	return rc;
1470	}
1471	}
1472	}
1473
1474	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1475	return VINF_SUCCESS;
1476	}
1477
1478
1479	/**
1480	* Determines the method the CPU uses to handle unknown CPUID leaves.
1481	*
1482	* @returns VBox status code.
1483	* @param penmUnknownMethod Where to return the method.
1484	* @param pDefUnknown Where to return default unknown values. This
1485	* will be set, even if the resulting method
1486	* doesn't actually needs it.
1487	*/
1488	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1489	{
1490	uint32_t uLastStd = ASMCpuId_EAX(0);
1491	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1492	if (!RTX86IsValidExtRange(uLastExt))
1493	uLastExt = 0x80000000;
1494
1495	uint32_t auChecks[] =
1496	{
1497	uLastStd + 1,
1498	uLastStd + 5,
1499	uLastStd + 8,
1500	uLastStd + 32,
1501	uLastStd + 251,
1502	uLastExt + 1,
1503	uLastExt + 8,
1504	uLastExt + 15,
1505	uLastExt + 63,
1506	uLastExt + 255,
1507	0x7fbbffcc,
1508	0x833f7872,
1509	0xefff2353,
1510	0x35779456,
1511	0x1ef6d33e,
1512	};
1513
1514	static const uint32_t s_auValues[] =
1515	{
1516	0xa95d2156,
1517	0x00000001,
1518	0x00000002,
1519	0x00000008,
1520	0x00000000,
1521	0x55773399,
1522	0x93401769,
1523	0x12039587,
1524	};
1525
1526	/*
1527	* Simple method, all zeros.
1528	*/
1529	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1530	pDefUnknown->uEax = 0;
1531	pDefUnknown->uEbx = 0;
1532	pDefUnknown->uEcx = 0;
1533	pDefUnknown->uEdx = 0;
1534
1535	/*
1536	* Intel has been observed returning the last standard leaf.
1537	*/
1538	uint32_t auLast[4];
1539	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1540
1541	uint32_t cChecks = RT_ELEMENTS(auChecks);
1542	while (cChecks > 0)
1543	{
1544	uint32_t auCur[4];
1545	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1546	if (memcmp(auCur, auLast, sizeof(auCur)))
1547	break;
1548	cChecks--;
1549	}
1550	if (cChecks == 0)
1551	{
1552	/* Now, what happens when the input changes? Esp. ECX. */
1553	uint32_t cTotal = 0;
1554	uint32_t cSame = 0;
1555	uint32_t cLastWithEcx = 0;
1556	uint32_t cNeither = 0;
1557	uint32_t cValues = RT_ELEMENTS(s_auValues);
1558	while (cValues > 0)
1559	{
1560	uint32_t uValue = s_auValues[cValues - 1];
1561	uint32_t auLastWithEcx[4];
1562	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1563	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1564
1565	cChecks = RT_ELEMENTS(auChecks);
1566	while (cChecks > 0)
1567	{
1568	uint32_t auCur[4];
1569	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1570	if (!memcmp(auCur, auLast, sizeof(auCur)))
1571	{
1572	cSame++;
1573	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1574	cLastWithEcx++;
1575	}
1576	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1577	cLastWithEcx++;
1578	else
1579	cNeither++;
1580	cTotal++;
1581	cChecks--;
1582	}
1583	cValues--;
1584	}
1585
1586	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1587	if (cSame == cTotal)
1588	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1589	else if (cLastWithEcx == cTotal)
1590	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1591	else
1592	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1593	pDefUnknown->uEax = auLast[0];
1594	pDefUnknown->uEbx = auLast[1];
1595	pDefUnknown->uEcx = auLast[2];
1596	pDefUnknown->uEdx = auLast[3];
1597	return VINF_SUCCESS;
1598	}
1599
1600	/*
1601	* Unchanged register values?
1602	*/
1603	cChecks = RT_ELEMENTS(auChecks);
1604	while (cChecks > 0)
1605	{
1606	uint32_t const uLeaf = auChecks[cChecks - 1];
1607	uint32_t cValues = RT_ELEMENTS(s_auValues);
1608	while (cValues > 0)
1609	{
1610	uint32_t uValue = s_auValues[cValues - 1];
1611	uint32_t auCur[4];
1612	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1613	if ( auCur[0] != uLeaf
1614	\|\| auCur[1] != uValue
1615	\|\| auCur[2] != uValue
1616	\|\| auCur[3] != uValue)
1617	break;
1618	cValues--;
1619	}
1620	if (cValues != 0)
1621	break;
1622	cChecks--;
1623	}
1624	if (cChecks == 0)
1625	{
1626	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1627	return VINF_SUCCESS;
1628	}
1629
1630	/*
1631	* Just go with the simple method.
1632	*/
1633	return VINF_SUCCESS;
1634	}
1635
1636	#endif /* RT_ARCH_X86 \|\| RT_ARCH_AMD64 */
1637
1638	/**
1639	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1640	*
1641	* @returns Read only name string.
1642	* @param enmUnknownMethod The method to translate.
1643	*/
1644	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1645	{
1646	switch (enmUnknownMethod)
1647	{
1648	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1649	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1650	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1651	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1652
1653	case CPUMUNKNOWNCPUID_INVALID:
1654	case CPUMUNKNOWNCPUID_END:
1655	case CPUMUNKNOWNCPUID_32BIT_HACK:
1656	break;
1657	}
1658	return "Invalid-unknown-CPUID-method";
1659	}
1660
1661
1662	/**
1663	* Detect the CPU vendor give n the
1664	*
1665	* @returns The vendor.
1666	* @param uEAX EAX from CPUID(0).
1667	* @param uEBX EBX from CPUID(0).
1668	* @param uECX ECX from CPUID(0).
1669	* @param uEDX EDX from CPUID(0).
1670	*/
1671	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1672	{
1673	if (RTX86IsValidStdRange(uEAX))
1674	{
1675	if (RTX86IsAmdCpu(uEBX, uECX, uEDX))
1676	return CPUMCPUVENDOR_AMD;
1677
1678	if (RTX86IsIntelCpu(uEBX, uECX, uEDX))
1679	return CPUMCPUVENDOR_INTEL;
1680
1681	if (RTX86IsViaCentaurCpu(uEBX, uECX, uEDX))
1682	return CPUMCPUVENDOR_VIA;
1683
1684	if (RTX86IsShanghaiCpu(uEBX, uECX, uEDX))
1685	return CPUMCPUVENDOR_SHANGHAI;
1686
1687	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1688	&& uECX == UINT32_C(0x64616574)
1689	&& uEDX == UINT32_C(0x736E4978))
1690	return CPUMCPUVENDOR_CYRIX;
1691
1692	if (RTX86IsHygonCpu(uEBX, uECX, uEDX))
1693	return CPUMCPUVENDOR_HYGON;
1694
1695	/* "Geode by NSC", example: family 5, model 9. */
1696
1697	/** @todo detect the other buggers... */
1698	}
1699
1700	return CPUMCPUVENDOR_UNKNOWN;
1701	}
1702
1703
1704	/**
1705	* Translates a CPU vendor enum value into the corresponding string constant.
1706	*
1707	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1708	* value name. This can be useful when generating code.
1709	*
1710	* @returns Read only name string.
1711	* @param enmVendor The CPU vendor value.
1712	*/
1713	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1714	{
1715	switch (enmVendor)
1716	{
1717	case CPUMCPUVENDOR_INTEL: return "INTEL";
1718	case CPUMCPUVENDOR_AMD: return "AMD";
1719	case CPUMCPUVENDOR_VIA: return "VIA";
1720	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1721	case CPUMCPUVENDOR_SHANGHAI: return "SHANGHAI";
1722	case CPUMCPUVENDOR_HYGON: return "HYGON";
1723	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1724
1725	case CPUMCPUVENDOR_INVALID:
1726	case CPUMCPUVENDOR_32BIT_HACK:
1727	break;
1728	}
1729	return "Invalid-cpu-vendor";
1730	}
1731
1732
1733	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1734	{
1735	/* Could do binary search, doing linear now because I'm lazy. */
1736	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1737	while (cLeaves-- > 0)
1738	{
1739	if (pLeaf->uLeaf == uLeaf)
1740	return pLeaf;
1741	pLeaf++;
1742	}
1743	return NULL;
1744	}
1745
1746
1747	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1748	{
1749	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1750	if ( !pLeaf
1751	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1752	return pLeaf;
1753
1754	/* Linear sub-leaf search. Lazy as usual. */
1755	cLeaves -= pLeaf - paLeaves;
1756	while ( cLeaves-- > 0
1757	&& pLeaf->uLeaf == uLeaf)
1758	{
1759	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1760	return pLeaf;
1761	pLeaf++;
1762	}
1763
1764	return NULL;
1765	}
1766
1767
1768	static void cpumR3ExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, PCPUMFEATURES pFeatures)
1769	{
1770	Assert(pVmxMsrs);
1771	Assert(pFeatures);
1772	Assert(pFeatures->fVmx);
1773
1774	/* Basic information. */
1775	bool const fVmxTrueMsrs = RT_BOOL(pVmxMsrs->u64Basic & VMX_BF_BASIC_TRUE_CTLS_MASK);
1776	{
1777	uint64_t const u64Basic = pVmxMsrs->u64Basic;
1778	pFeatures->fVmxInsOutInfo = RT_BF_GET(u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1779	}
1780
1781	/* Pin-based VM-execution controls. */
1782	{
1783	uint32_t const fPinCtls = fVmxTrueMsrs ? pVmxMsrs->TruePinCtls.n.allowed1 : pVmxMsrs->PinCtls.n.allowed1;
1784	pFeatures->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1785	pFeatures->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1786	pFeatures->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1787	pFeatures->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1788	pFeatures->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1789	}
1790
1791	/* Processor-based VM-execution controls. */
1792	{
1793	uint32_t const fProcCtls = fVmxTrueMsrs ? pVmxMsrs->TrueProcCtls.n.allowed1 : pVmxMsrs->ProcCtls.n.allowed1;
1794	pFeatures->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1795	pFeatures->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1796	pFeatures->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1797	pFeatures->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1798	pFeatures->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1799	pFeatures->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1800	pFeatures->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1801	pFeatures->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1802	pFeatures->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1803	pFeatures->fVmxTertiaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TERTIARY_CTLS);
1804	pFeatures->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1805	pFeatures->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1806	pFeatures->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1807	pFeatures->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1808	pFeatures->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1809	pFeatures->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1810	pFeatures->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1811	pFeatures->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1812	pFeatures->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1813	pFeatures->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1814	pFeatures->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1815	pFeatures->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1816	}
1817
1818	/* Secondary processor-based VM-execution controls. */
1819	{
1820	uint32_t const fProcCtls2 = pFeatures->fVmxSecondaryExecCtls ? pVmxMsrs->ProcCtls2.n.allowed1 : 0;
1821	pFeatures->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1822	pFeatures->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1823	pFeatures->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1824	pFeatures->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1825	pFeatures->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1826	pFeatures->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1827	pFeatures->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1828	pFeatures->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1829	pFeatures->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1830	pFeatures->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1831	pFeatures->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1832	pFeatures->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1833	pFeatures->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1834	pFeatures->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1835	pFeatures->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1836	pFeatures->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1837	pFeatures->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1838	pFeatures->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE);
1839	pFeatures->fVmxConcealVmxFromPt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1840	pFeatures->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1841	pFeatures->fVmxModeBasedExecuteEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1842	pFeatures->fVmxSppEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_SPP_EPT);
1843	pFeatures->fVmxPtEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PT_EPT);
1844	pFeatures->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1845	pFeatures->fVmxUserWaitPause = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1846	pFeatures->fVmxEnclvExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_ENCLV_EXIT);
1847	}
1848
1849	/* Tertiary processor-based VM-execution controls. */
1850	{
1851	uint64_t const fProcCtls3 = pFeatures->fVmxTertiaryExecCtls ? pVmxMsrs->u64ProcCtls3 : 0;
1852	pFeatures->fVmxLoadIwKeyExit = RT_BOOL(fProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT);
1853	}
1854
1855	/* VM-exit controls. */
1856	{
1857	uint32_t const fExitCtls = fVmxTrueMsrs ? pVmxMsrs->TrueExitCtls.n.allowed1 : pVmxMsrs->ExitCtls.n.allowed1;
1858	pFeatures->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1859	pFeatures->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1860	pFeatures->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1861	pFeatures->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1862	pFeatures->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1863	pFeatures->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1864	pFeatures->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1865	pFeatures->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1866	}
1867
1868	/* VM-entry controls. */
1869	{
1870	uint32_t const fEntryCtls = fVmxTrueMsrs ? pVmxMsrs->TrueEntryCtls.n.allowed1 : pVmxMsrs->EntryCtls.n.allowed1;
1871	pFeatures->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1872	pFeatures->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1873	pFeatures->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1874	pFeatures->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1875	}
1876
1877	/* Miscellaneous data. */
1878	{
1879	uint32_t const fMiscData = pVmxMsrs->u64Misc;
1880	pFeatures->fVmxExitSaveEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_SAVE_EFER_LMA);
1881	pFeatures->fVmxPt = RT_BOOL(fMiscData & VMX_MISC_INTEL_PT);
1882	pFeatures->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1883	pFeatures->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1884	}
1885	}
1886
1887
1888	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures)
1889	{
1890	Assert(pMsrs);
1891	RT_ZERO(*pFeatures);
1892	if (cLeaves >= 2)
1893	{
1894	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1895	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1896	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1897	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1898	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1899	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1900
1901	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1902	pStd0Leaf->uEbx,
1903	pStd0Leaf->uEcx,
1904	pStd0Leaf->uEdx);
1905	pFeatures->uFamily = RTX86GetCpuFamily(pStd1Leaf->uEax);
1906	pFeatures->uModel = RTX86GetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1907	pFeatures->uStepping = RTX86GetCpuStepping(pStd1Leaf->uEax);
1908	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1909	pFeatures->uFamily,
1910	pFeatures->uModel,
1911	pFeatures->uStepping);
1912
1913	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1914	if (pExtLeaf8)
1915	{
1916	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1917	pFeatures->cMaxLinearAddrWidth = (pExtLeaf8->uEax >> 8) & 0xff;
1918	}
1919	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1920	{
1921	pFeatures->cMaxPhysAddrWidth = 36;
1922	pFeatures->cMaxLinearAddrWidth = 36;
1923	}
1924	else
1925	{
1926	pFeatures->cMaxPhysAddrWidth = 32;
1927	pFeatures->cMaxLinearAddrWidth = 32;
1928	}
1929
1930	/* Standard features. */
1931	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1932	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1933	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1934	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1935	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1936	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1937	pFeatures->fPge = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PGE);
1938	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1939	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1940	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1941	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1942	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1943	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1944	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1945	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1946	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1947	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1948	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1949	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1950	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1951	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1952	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1953	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1954	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1955	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1956	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1957	pFeatures->fRdRand = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_RDRAND);
1958	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1959	if (pFeatures->fVmx)
1960	cpumR3ExplodeVmxFeatures(&pMsrs->hwvirt.vmx, pFeatures);
1961
1962	/* Structured extended features. */
1963	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1964	if (pSxfLeaf0)
1965	{
1966	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1967	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1968	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1969	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1970	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1971	pFeatures->fBmi1 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_BMI1);
1972	pFeatures->fBmi2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_BMI2);
1973	pFeatures->fRdSeed = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_RDSEED);
1974
1975	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1976	pFeatures->fIbrs = pFeatures->fIbpb;
1977	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1978	pFeatures->fFlushCmd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
1979	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1980	pFeatures->fMdsClear = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR);
1981	}
1982
1983	/* MWAIT/MONITOR leaf. */
1984	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1985	if (pMWaitLeaf)
1986	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1987	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1988
1989	/* Extended features. */
1990	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1991	if (pExtLeaf)
1992	{
1993	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1994	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1995	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1996	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1997	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1998	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1999	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2000	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
2001	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
2002	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
2003	}
2004
2005	/* VMX (VMXON, VMCS region and related data structures) physical address width (depends on long-mode). */
2006	pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
2007
2008	if ( pExtLeaf
2009	&& ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
2010	\|\| pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON))
2011	{
2012	/* AMD features. */
2013	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
2014	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
2015	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
2016	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
2017	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
2018	pFeatures->fPge \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PGE);
2019	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
2020	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
2021	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
2022	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
2023	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
2024	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2025	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
2026	pFeatures->fAbm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_ABM);
2027	pFeatures->fTbm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_TBM);
2028	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
2029	if (pFeatures->fSvm)
2030	{
2031	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
2032	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
2033	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
2034	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
2035	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
2036	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
2037	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
2038	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
2039	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
2040	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
2041	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
2042	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
2043	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
2044	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
2045	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
2046	pFeatures->fSvmGmet = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_GMET);
2047	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
2048	}
2049	}
2050
2051	/*
2052	* Quirks.
2053	*/
2054	pFeatures->fLeakyFxSR = pExtLeaf
2055	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
2056	&& ( ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
2057	&& pFeatures->uFamily >= 6 /* K7 and up */)
2058	\|\| pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON);
2059
2060	/*
2061	* Max extended (/FPU) state.
2062	*/
2063	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
2064	if (pFeatures->fXSaveRstor)
2065	{
2066	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
2067	if (pXStateLeaf0)
2068	{
2069	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
2070	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
2071	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
2072	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
2073	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
2074	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
2075	{
2076	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
2077
2078	/* (paranoia:) */
2079	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
2080	if ( pXStateLeaf1
2081	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
2082	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
2083	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
2084	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
2085	}
2086	else
2087	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
2088	pFeatures->fXSaveRstor = 0);
2089	}
2090	else
2091	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
2092	pFeatures->fXSaveRstor = 0);
2093	}
2094	}
2095	else
2096	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
2097	return VINF_SUCCESS;
2098	}
2099
2100
2101	/*
2102	*
2103	* Init related code.
2104	* Init related code.
2105	* Init related code.
2106	*
2107	*
2108	*/
2109	#ifndef IN_VBOX_CPU_REPORT
2110
2111
2112	/**
2113	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
2114	*
2115	* This ignores the fSubLeafMask.
2116	*
2117	* @returns Pointer to the matching leaf, or NULL if not found.
2118	* @param pCpum The CPUM instance data.
2119	* @param uLeaf The leaf to locate.
2120	* @param uSubLeaf The subleaf to locate.
2121	*/
2122	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
2123	{
2124	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
2125	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
2126	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
2127	if (iEnd)
2128	{
2129	uint32_t iBegin = 0;
2130	for (;;)
2131	{
2132	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
2133	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
2134	if (uNeedle < uCur)
2135	{
2136	if (i > iBegin)
2137	iEnd = i;
2138	else
2139	break;
2140	}
2141	else if (uNeedle > uCur)
2142	{
2143	if (i + 1 < iEnd)
2144	iBegin = i + 1;
2145	else
2146	break;
2147	}
2148	else
2149	return &paLeaves[i];
2150	}
2151	}
2152	return NULL;
2153	}
2154
2155
2156	/**
2157	* Loads MSR range overrides.
2158	*
2159	* This must be called before the MSR ranges are moved from the normal heap to
2160	* the hyper heap!
2161	*
2162	* @returns VBox status code (VMSetError called).
2163	* @param pVM The cross context VM structure.
2164	* @param pMsrNode The CFGM node with the MSR overrides.
2165	*/
2166	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
2167	{
2168	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2169	{
2170	/*
2171	* Assemble a valid MSR range.
2172	*/
2173	CPUMMSRRANGE MsrRange;
2174	MsrRange.offCpumCpu = 0;
2175	MsrRange.fReserved = 0;
2176
2177	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
2178	if (RT_FAILURE(rc))
2179	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
2180
2181	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
2182	if (RT_FAILURE(rc))
2183	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
2184	MsrRange.szName, rc);
2185
2186	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
2187	if (RT_FAILURE(rc))
2188	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
2189	MsrRange.szName, rc);
2190
2191	char szType[32];
2192	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
2193	if (RT_FAILURE(rc))
2194	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
2195	MsrRange.szName, rc);
2196	if (!RTStrICmp(szType, "FixedValue"))
2197	{
2198	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
2199	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
2200
2201	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
2202	if (RT_FAILURE(rc))
2203	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
2204	MsrRange.szName, rc);
2205
2206	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
2207	if (RT_FAILURE(rc))
2208	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
2209	MsrRange.szName, rc);
2210
2211	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
2212	if (RT_FAILURE(rc))
2213	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
2214	MsrRange.szName, rc);
2215	}
2216	else
2217	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
2218	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
2219
2220	/*
2221	* Insert the range into the table (replaces/splits/shrinks existing
2222	* MSR ranges).
2223	*/
2224	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
2225	&MsrRange);
2226	if (RT_FAILURE(rc))
2227	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
2228	}
2229
2230	return VINF_SUCCESS;
2231	}
2232
2233
2234	/**
2235	* Loads CPUID leaf overrides.
2236	*
2237	* This must be called before the CPUID leaves are moved from the normal
2238	* heap to the hyper heap!
2239	*
2240	* @returns VBox status code (VMSetError called).
2241	* @param pVM The cross context VM structure.
2242	* @param pParentNode The CFGM node with the CPUID leaves.
2243	* @param pszLabel How to label the overrides we're loading.
2244	*/
2245	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2246	{
2247	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2248	{
2249	/*
2250	* Get the leaf and subleaf numbers.
2251	*/
2252	char szName[128];
2253	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2254	if (RT_FAILURE(rc))
2255	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2256
2257	/* The leaf number is either specified directly or thru the node name. */
2258	uint32_t uLeaf;
2259	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2260	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2261	{
2262	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2263	if (rc != VINF_SUCCESS)
2264	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2265	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2266	}
2267	else if (RT_FAILURE(rc))
2268	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2269	pszLabel, szName, rc);
2270
2271	uint32_t uSubLeaf;
2272	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2273	if (RT_FAILURE(rc))
2274	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2275	pszLabel, szName, rc);
2276
2277	uint32_t fSubLeafMask;
2278	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2279	if (RT_FAILURE(rc))
2280	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2281	pszLabel, szName, rc);
2282
2283	/*
2284	* Look up the specified leaf, since the output register values
2285	* defaults to any existing values. This allows overriding a single
2286	* register, without needing to know the other values.
2287	*/
2288	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2289	CPUMCPUIDLEAF Leaf;
2290	if (pLeaf)
2291	Leaf = *pLeaf;
2292	else
2293	RT_ZERO(Leaf);
2294	Leaf.uLeaf = uLeaf;
2295	Leaf.uSubLeaf = uSubLeaf;
2296	Leaf.fSubLeafMask = fSubLeafMask;
2297
2298	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2299	if (RT_FAILURE(rc))
2300	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2301	pszLabel, szName, rc);
2302	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2303	if (RT_FAILURE(rc))
2304	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2305	pszLabel, szName, rc);
2306	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2307	if (RT_FAILURE(rc))
2308	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2309	pszLabel, szName, rc);
2310	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2311	if (RT_FAILURE(rc))
2312	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2313	pszLabel, szName, rc);
2314
2315	/*
2316	* Insert the leaf into the table (replaces existing ones).
2317	*/
2318	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2319	&Leaf);
2320	if (RT_FAILURE(rc))
2321	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2322	}
2323
2324	return VINF_SUCCESS;
2325	}
2326
2327
2328
2329	/**
2330	* Fetches overrides for a CPUID leaf.
2331	*
2332	* @returns VBox status code.
2333	* @param pLeaf The leaf to load the overrides into.
2334	* @param pCfgNode The CFGM node containing the overrides
2335	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2336	* @param iLeaf The CPUID leaf number.
2337	*/
2338	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2339	{
2340	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2341	if (pLeafNode)
2342	{
2343	uint32_t u32;
2344	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2345	if (RT_SUCCESS(rc))
2346	pLeaf->uEax = u32;
2347	else
2348	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2349
2350	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2351	if (RT_SUCCESS(rc))
2352	pLeaf->uEbx = u32;
2353	else
2354	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2355
2356	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2357	if (RT_SUCCESS(rc))
2358	pLeaf->uEcx = u32;
2359	else
2360	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2361
2362	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2363	if (RT_SUCCESS(rc))
2364	pLeaf->uEdx = u32;
2365	else
2366	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2367
2368	}
2369	return VINF_SUCCESS;
2370	}
2371
2372
2373	/**
2374	* Load the overrides for a set of CPUID leaves.
2375	*
2376	* @returns VBox status code.
2377	* @param paLeaves The leaf array.
2378	* @param cLeaves The number of leaves.
2379	* @param uStart The start leaf number.
2380	* @param pCfgNode The CFGM node containing the overrides
2381	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2382	*/
2383	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2384	{
2385	for (uint32_t i = 0; i < cLeaves; i++)
2386	{
2387	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2388	if (RT_FAILURE(rc))
2389	return rc;
2390	}
2391
2392	return VINF_SUCCESS;
2393	}
2394
2395
2396	/**
2397	* Installs the CPUID leaves and explods the data into structures like
2398	* GuestFeatures and CPUMCTX::aoffXState.
2399	*
2400	* @returns VBox status code.
2401	* @param pVM The cross context VM structure.
2402	* @param pCpum The CPUM part of @a VM.
2403	* @param paLeaves The leaves. These will be copied (but not freed).
2404	* @param cLeaves The number of leaves.
2405	* @param pMsrs The MSRs.
2406	*/
2407	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
2408	{
2409	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2410
2411	/*
2412	* Install the CPUID information.
2413	*/
2414	AssertLogRelMsgReturn(cLeaves <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves),
2415	("cLeaves=%u - max %u\n", cLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves)),
2416	VERR_CPUM_IPE_1); /** @todo better status! */
2417	if (paLeaves != pCpum->GuestInfo.aCpuIdLeaves)
2418	memcpy(pCpum->GuestInfo.aCpuIdLeaves, paLeaves, cLeaves * sizeof(paLeaves[0]));
2419	pCpum->GuestInfo.paCpuIdLeavesR3 = pCpum->GuestInfo.aCpuIdLeaves;
2420	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2421
2422	/*
2423	* Update the default CPUID leaf if necessary.
2424	*/
2425	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2426	{
2427	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2428	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2429	{
2430	/* We don't use CPUID(0).eax here because of the NT hack that only
2431	changes that value without actually removing any leaves. */
2432	uint32_t i = 0;
2433	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2434	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2435	{
2436	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2437	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2438	i++;
2439	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2440	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2441	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2442	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2443	}
2444	break;
2445	}
2446	default:
2447	break;
2448	}
2449
2450	/*
2451	* Explode the guest CPU features.
2452	*/
2453	int rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
2454	&pCpum->GuestFeatures);
2455	AssertLogRelRCReturn(rc, rc);
2456
2457	/*
2458	* Adjust the scalable bus frequency according to the CPUID information
2459	* we're now using.
2460	*/
2461	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2462	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2463	? UINT64_C(100000000) /* 100MHz */
2464	: UINT64_C(133333333); /* 133MHz */
2465
2466	/*
2467	* Populate the legacy arrays. Currently used for everything, later only
2468	* for patch manager.
2469	*/
2470	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2471	{
2472	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2473	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2474	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2475	};
2476	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2477	{
2478	uint32_t cLeft = aOldRanges[i].cCpuIds;
2479	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2480	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2481	while (cLeft-- > 0)
2482	{
2483	uLeaf--;
2484	pLegacyLeaf--;
2485
2486	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2487	if (pLeaf)
2488	{
2489	pLegacyLeaf->uEax = pLeaf->uEax;
2490	pLegacyLeaf->uEbx = pLeaf->uEbx;
2491	pLegacyLeaf->uEcx = pLeaf->uEcx;
2492	pLegacyLeaf->uEdx = pLeaf->uEdx;
2493	}
2494	else
2495	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2496	}
2497	}
2498
2499	/*
2500	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2501	*/
2502	PVMCPU pVCpu0 = pVM->apCpusR3[0];
2503	AssertCompile(sizeof(pVCpu0->cpum.s.Guest.abXState) == CPUM_MAX_XSAVE_AREA_SIZE);
2504	memset(&pVCpu0->cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2505	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2506	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2507	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2508	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2509	{
2510	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2511	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2512	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2513	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2514	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2515	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2516	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2517	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2518	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2519	pCpum->GuestFeatures.cbMaxExtendedState),
2520	VERR_CPUM_IPE_1);
2521	pVCpu0->cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2522	}
2523
2524	/* Copy the CPU #0 data to the other CPUs. */
2525	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
2526	{
2527	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2528	memcpy(&pVCpu->cpum.s.Guest.aoffXState[0], &pVCpu0->cpum.s.Guest.aoffXState[0], sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2529	}
2530
2531	return VINF_SUCCESS;
2532	}
2533
2534
2535	/** @name Instruction Set Extension Options
2536	* @{ */
2537	/** Configuration option type (extended boolean, really). */
2538	typedef uint8_t CPUMISAEXTCFG;
2539	/** Always disable the extension. */
2540	#define CPUMISAEXTCFG_DISABLED false
2541	/** Enable the extension if it's supported by the host CPU. */
2542	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2543	/** Enable the extension if it's supported by the host CPU, but don't let
2544	* the portable CPUID feature disable it. */
2545	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2546	/** Always enable the extension. */
2547	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2548	/** @} */
2549
2550	/**
2551	* CPUID Configuration (from CFGM).
2552	*
2553	* @remarks The members aren't document since we would only be duplicating the
2554	* \@cfgm entries in cpumR3CpuIdReadConfig.
2555	*/
2556	typedef struct CPUMCPUIDCONFIG
2557	{
2558	bool fNt4LeafLimit;
2559	bool fInvariantTsc;
2560	bool fForceVme;
2561	bool fNestedHWVirt;
2562
2563	CPUMISAEXTCFG enmCmpXchg16b;
2564	CPUMISAEXTCFG enmMonitor;
2565	CPUMISAEXTCFG enmMWaitExtensions;
2566	CPUMISAEXTCFG enmSse41;
2567	CPUMISAEXTCFG enmSse42;
2568	CPUMISAEXTCFG enmAvx;
2569	CPUMISAEXTCFG enmAvx2;
2570	CPUMISAEXTCFG enmXSave;
2571	CPUMISAEXTCFG enmAesNi;
2572	CPUMISAEXTCFG enmPClMul;
2573	CPUMISAEXTCFG enmPopCnt;
2574	CPUMISAEXTCFG enmMovBe;
2575	CPUMISAEXTCFG enmRdRand;
2576	CPUMISAEXTCFG enmRdSeed;
2577	CPUMISAEXTCFG enmCLFlushOpt;
2578	CPUMISAEXTCFG enmFsGsBase;
2579	CPUMISAEXTCFG enmPcid;
2580	CPUMISAEXTCFG enmInvpcid;
2581	CPUMISAEXTCFG enmFlushCmdMsr;
2582	CPUMISAEXTCFG enmMdsClear;
2583	CPUMISAEXTCFG enmArchCapMsr;
2584
2585	CPUMISAEXTCFG enmAbm;
2586	CPUMISAEXTCFG enmSse4A;
2587	CPUMISAEXTCFG enmMisAlnSse;
2588	CPUMISAEXTCFG enm3dNowPrf;
2589	CPUMISAEXTCFG enmAmdExtMmx;
2590
2591	uint32_t uMaxStdLeaf;
2592	uint32_t uMaxExtLeaf;
2593	uint32_t uMaxCentaurLeaf;
2594	uint32_t uMaxIntelFamilyModelStep;
2595	char szCpuName[128];
2596	} CPUMCPUIDCONFIG;
2597	/** Pointer to CPUID config (from CFGM). */
2598	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2599
2600
2601	/**
2602	* Mini CPU selection support for making Mac OS X happy.
2603	*
2604	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2605	*
2606	* @param pCpum The CPUM instance data.
2607	* @param pConfig The CPUID configuration we've read from CFGM.
2608	*/
2609	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2610	{
2611	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2612	{
2613	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2614	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(RTX86GetCpuStepping(pStdFeatureLeaf->uEax),
2615	RTX86GetCpuModelIntel(pStdFeatureLeaf->uEax),
2616	RTX86GetCpuFamily(pStdFeatureLeaf->uEax),
2617	0);
2618	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2619	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2620	{
2621	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2622	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2623	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2624	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2625	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2626	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2627	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2628	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2629	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2630	pStdFeatureLeaf->uEax = uNew;
2631	}
2632	}
2633	}
2634
2635
2636
2637	/**
2638	* Limit it the number of entries, zapping the remainder.
2639	*
2640	* The limits are masking off stuff about power saving and similar, this
2641	* is perhaps a bit crudely done as there is probably some relatively harmless
2642	* info too in these leaves (like words about having a constant TSC).
2643	*
2644	* @param pCpum The CPUM instance data.
2645	* @param pConfig The CPUID configuration we've read from CFGM.
2646	*/
2647	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2648	{
2649	/*
2650	* Standard leaves.
2651	*/
2652	uint32_t uSubLeaf = 0;
2653	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2654	if (pCurLeaf)
2655	{
2656	uint32_t uLimit = pCurLeaf->uEax;
2657	if (uLimit <= UINT32_C(0x000fffff))
2658	{
2659	if (uLimit > pConfig->uMaxStdLeaf)
2660	{
2661	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2662	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2663	uLimit + 1, UINT32_C(0x000fffff));
2664	}
2665
2666	/* NT4 hack, no zapping of extra leaves here. */
2667	if (pConfig->fNt4LeafLimit && uLimit > 3)
2668	pCurLeaf->uEax = uLimit = 3;
2669
2670	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2671	pCurLeaf->uEax = uLimit;
2672	}
2673	else
2674	{
2675	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2676	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2677	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2678	}
2679	}
2680
2681	/*
2682	* Extended leaves.
2683	*/
2684	uSubLeaf = 0;
2685	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2686	if (pCurLeaf)
2687	{
2688	uint32_t uLimit = pCurLeaf->uEax;
2689	if ( uLimit >= UINT32_C(0x80000000)
2690	&& uLimit <= UINT32_C(0x800fffff))
2691	{
2692	if (uLimit > pConfig->uMaxExtLeaf)
2693	{
2694	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2695	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2696	uLimit + 1, UINT32_C(0x800fffff));
2697	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2698	pCurLeaf->uEax = uLimit;
2699	}
2700	}
2701	else
2702	{
2703	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2704	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2705	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2706	}
2707	}
2708
2709	/*
2710	* Centaur leaves (VIA).
2711	*/
2712	uSubLeaf = 0;
2713	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2714	if (pCurLeaf)
2715	{
2716	uint32_t uLimit = pCurLeaf->uEax;
2717	if ( uLimit >= UINT32_C(0xc0000000)
2718	&& uLimit <= UINT32_C(0xc00fffff))
2719	{
2720	if (uLimit > pConfig->uMaxCentaurLeaf)
2721	{
2722	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2723	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2724	uLimit + 1, UINT32_C(0xcfffffff));
2725	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2726	pCurLeaf->uEax = uLimit;
2727	}
2728	}
2729	else
2730	{
2731	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2732	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2733	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2734	}
2735	}
2736	}
2737
2738
2739	/**
2740	* Clears a CPUID leaf and all sub-leaves (to zero).
2741	*
2742	* @param pCpum The CPUM instance data.
2743	* @param uLeaf The leaf to clear.
2744	*/
2745	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2746	{
2747	uint32_t uSubLeaf = 0;
2748	PCPUMCPUIDLEAF pCurLeaf;
2749	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2750	{
2751	pCurLeaf->uEax = 0;
2752	pCurLeaf->uEbx = 0;
2753	pCurLeaf->uEcx = 0;
2754	pCurLeaf->uEdx = 0;
2755	uSubLeaf++;
2756	}
2757	}
2758
2759
2760	/**
2761	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2762	* the given leaf.
2763	*
2764	* @returns pLeaf.
2765	* @param pCpum The CPUM instance data.
2766	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2767	*/
2768	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2769	{
2770	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2771	if (pLeaf->fSubLeafMask != 0)
2772	{
2773	/*
2774	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2775	* Log everything while we're at it.
2776	*/
2777	LogRel(("CPUM:\n"
2778	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2779	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2780	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2781	for (;;)
2782	{
2783	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2784	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2785	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2786	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2787	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2788	break;
2789	pSubLeaf++;
2790	}
2791	LogRel(("CPUM:\n"));
2792
2793	/*
2794	* Remove the offending sub-leaves.
2795	*/
2796	if (pSubLeaf != pLeaf)
2797	{
2798	if (pSubLeaf != pLast)
2799	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2800	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2801	}
2802
2803	/*
2804	* Convert the first sub-leaf into a single leaf.
2805	*/
2806	pLeaf->uSubLeaf = 0;
2807	pLeaf->fSubLeafMask = 0;
2808	}
2809	return pLeaf;
2810	}
2811
2812
2813	/**
2814	* Sanitizes and adjust the CPUID leaves.
2815	*
2816	* Drop features that aren't virtualized (or virtualizable). Adjust information
2817	* and capabilities to fit the virtualized hardware. Remove information the
2818	* guest shouldn't have (because it's wrong in the virtual world or because it
2819	* gives away host details) or that we don't have documentation for and no idea
2820	* what means.
2821	*
2822	* @returns VBox status code.
2823	* @param pVM The cross context VM structure (for cCpus).
2824	* @param pCpum The CPUM instance data.
2825	* @param pConfig The CPUID configuration we've read from CFGM.
2826	*/
2827	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2828	{
2829	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2830	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2831	{ \
2832	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2833	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2834	}
2835	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2836	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2837	{ \
2838	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2839	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2840	}
2841	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2842	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2843	&& ((a_pLeafReg) & (fBitMask)) \
2844	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2845	{ \
2846	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2847	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2848	}
2849	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2850
2851	/* The CPUID entries we start with here isn't necessarily the ones of the host, so we
2852	must consult HostFeatures when processing CPUMISAEXTCFG variables. */
2853	PCCPUMFEATURES pHstFeat = &pCpum->HostFeatures;
2854	#define PASSTHRU_FEATURE(enmConfig, fHostFeature, fConst) \
2855	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) ? (fConst) : 0)
2856	#define PASSTHRU_FEATURE_EX(enmConfig, fHostFeature, fAndExpr, fConst) \
2857	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) && (fAndExpr) ? (fConst) : 0)
2858	#define PASSTHRU_FEATURE_TODO(enmConfig, fConst) ((enmConfig) ? (fConst) : 0)
2859
2860	/* Cpuid 1:
2861	* EAX: CPU model, family and stepping.
2862	*
2863	* ECX + EDX: Supported features. Only report features we can support.
2864	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2865	* options may require adjusting (i.e. stripping what was enabled).
2866	*
2867	* EBX: Branding, CLFLUSH line size, logical processors per package and
2868	* initial APIC ID.
2869	*/
2870	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2871	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2872	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2873
2874	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2875	\| X86_CPUID_FEATURE_EDX_VME
2876	\| X86_CPUID_FEATURE_EDX_DE
2877	\| X86_CPUID_FEATURE_EDX_PSE
2878	\| X86_CPUID_FEATURE_EDX_TSC
2879	\| X86_CPUID_FEATURE_EDX_MSR
2880	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2881	\| X86_CPUID_FEATURE_EDX_MCE
2882	\| X86_CPUID_FEATURE_EDX_CX8
2883	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2884	//\| RT_BIT_32(10) - not defined
2885	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2886	//\| X86_CPUID_FEATURE_EDX_SEP
2887	\| X86_CPUID_FEATURE_EDX_MTRR
2888	\| X86_CPUID_FEATURE_EDX_PGE
2889	\| X86_CPUID_FEATURE_EDX_MCA
2890	\| X86_CPUID_FEATURE_EDX_CMOV
2891	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2892	\| X86_CPUID_FEATURE_EDX_PSE36
2893	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2894	\| X86_CPUID_FEATURE_EDX_CLFSH
2895	//\| RT_BIT_32(20) - not defined
2896	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2897	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2898	\| X86_CPUID_FEATURE_EDX_MMX
2899	\| X86_CPUID_FEATURE_EDX_FXSR
2900	\| X86_CPUID_FEATURE_EDX_SSE
2901	\| X86_CPUID_FEATURE_EDX_SSE2
2902	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2903	\| X86_CPUID_FEATURE_EDX_HTT
2904	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2905	//\| RT_BIT_32(30) - not defined
2906	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2907	;
2908	pStdFeatureLeaf->uEcx &= X86_CPUID_FEATURE_ECX_SSE3
2909	\| PASSTHRU_FEATURE_TODO(pConfig->enmPClMul, X86_CPUID_FEATURE_ECX_PCLMUL)
2910	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2911	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2912	\| PASSTHRU_FEATURE_EX(pConfig->enmMonitor, pHstFeat->fMonitorMWait, pVM->cCpus == 1, X86_CPUID_FEATURE_ECX_MONITOR)
2913	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2914	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
2915	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2916	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2917	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2918	\| X86_CPUID_FEATURE_ECX_SSSE3
2919	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2920	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2921	\| PASSTHRU_FEATURE(pConfig->enmCmpXchg16b, pHstFeat->fMovCmpXchg16b, X86_CPUID_FEATURE_ECX_CX16)
2922	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2923	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2924	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2925	\| PASSTHRU_FEATURE(pConfig->enmPcid, pHstFeat->fPcid, X86_CPUID_FEATURE_ECX_PCID)
2926	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2927	\| PASSTHRU_FEATURE(pConfig->enmSse41, pHstFeat->fSse41, X86_CPUID_FEATURE_ECX_SSE4_1)
2928	\| PASSTHRU_FEATURE(pConfig->enmSse42, pHstFeat->fSse42, X86_CPUID_FEATURE_ECX_SSE4_2)
2929	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2930	\| PASSTHRU_FEATURE_TODO(pConfig->enmMovBe, X86_CPUID_FEATURE_ECX_MOVBE)
2931	\| PASSTHRU_FEATURE_TODO(pConfig->enmPopCnt, X86_CPUID_FEATURE_ECX_POPCNT)
2932	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2933	\| PASSTHRU_FEATURE_TODO(pConfig->enmAesNi, X86_CPUID_FEATURE_ECX_AES)
2934	\| PASSTHRU_FEATURE(pConfig->enmXSave, pHstFeat->fXSaveRstor, X86_CPUID_FEATURE_ECX_XSAVE)
2935	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2936	\| PASSTHRU_FEATURE(pConfig->enmAvx, pHstFeat->fAvx, X86_CPUID_FEATURE_ECX_AVX)
2937	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2938	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdRand, X86_CPUID_FEATURE_ECX_RDRAND)
2939	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2940	;
2941
2942	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2943	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2944	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2945	{
2946	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2947	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2948	}
2949
2950	if (pCpum->u8PortableCpuIdLevel > 0)
2951	{
2952	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2953	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2954	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2955	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2956	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2957	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2958	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2959	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
2960	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2961	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2962	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2963	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2964	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2965	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2966	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2967	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2968	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2969	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2970	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2971	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2972
2973	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2974	\| X86_CPUID_FEATURE_EDX_PSN
2975	\| X86_CPUID_FEATURE_EDX_DS
2976	\| X86_CPUID_FEATURE_EDX_ACPI
2977	\| X86_CPUID_FEATURE_EDX_SS
2978	\| X86_CPUID_FEATURE_EDX_TM
2979	\| X86_CPUID_FEATURE_EDX_PBE
2980	)));
2981	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2982	\| X86_CPUID_FEATURE_ECX_CPLDS
2983	\| X86_CPUID_FEATURE_ECX_AES
2984	\| X86_CPUID_FEATURE_ECX_VMX
2985	\| X86_CPUID_FEATURE_ECX_SMX
2986	\| X86_CPUID_FEATURE_ECX_EST
2987	\| X86_CPUID_FEATURE_ECX_TM2
2988	\| X86_CPUID_FEATURE_ECX_CNTXID
2989	\| X86_CPUID_FEATURE_ECX_FMA
2990	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2991	\| X86_CPUID_FEATURE_ECX_PDCM
2992	\| X86_CPUID_FEATURE_ECX_DCA
2993	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2994	)));
2995	}
2996
2997	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2998	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2999
3000	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
3001	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
3002	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
3003	*/
3004	#ifdef VBOX_WITH_MULTI_CORE
3005	if (pVM->cCpus > 1)
3006	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
3007	#endif
3008	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
3009	{
3010	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
3011	core times the number of CPU cores per processor */
3012	#ifdef VBOX_WITH_MULTI_CORE
3013	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
3014	#else
3015	/* Single logical processor in a package. */
3016	pStdFeatureLeaf->uEbx \|= (1 << 16);
3017	#endif
3018	}
3019
3020	uint32_t uMicrocodeRev;
3021	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
3022	if (RT_SUCCESS(rc))
3023	{
3024	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
3025	}
3026	else
3027	{
3028	uMicrocodeRev = 0;
3029	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
3030	}
3031
3032	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
3033	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
3034	*/
3035	if ( ( pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen
3036	/** @todo The following ASSUMES that Hygon uses the same version numbering
3037	* as AMD and that they shipped buggy firmware. */
3038	\|\| pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Hygon_Dhyana)
3039	&& uMicrocodeRev < 0x8001126
3040	&& !pConfig->fForceVme)
3041	{
3042	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
3043	LogRel(("CPUM: Zen VME workaround engaged\n"));
3044	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
3045	}
3046
3047	/* Force standard feature bits. */
3048	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
3049	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
3050	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
3051	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
3052	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
3053	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
3054	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3055	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
3056	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3057	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
3058	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
3059	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
3060	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3061	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
3062	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
3063	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
3064	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
3065	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
3066	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3067	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
3068	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
3069	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
3070
3071	pStdFeatureLeaf = NULL; /* Must refetch! */
3072
3073	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
3074	* AMD:
3075	* EAX: CPU model, family and stepping.
3076	*
3077	* ECX + EDX: Supported features. Only report features we can support.
3078	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3079	* options may require adjusting (i.e. stripping what was enabled).
3080	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
3081	*
3082	* EBX: Branding ID and package type (or reserved).
3083	*
3084	* Intel and probably most others:
3085	* EAX: 0
3086	* EBX: 0
3087	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
3088	*/
3089	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3090	if (pExtFeatureLeaf)
3091	{
3092	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
3093
3094	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
3095	\| X86_CPUID_AMD_FEATURE_EDX_VME
3096	\| X86_CPUID_AMD_FEATURE_EDX_DE
3097	\| X86_CPUID_AMD_FEATURE_EDX_PSE
3098	\| X86_CPUID_AMD_FEATURE_EDX_TSC
3099	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
3100	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
3101	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
3102	\| X86_CPUID_AMD_FEATURE_EDX_CX8
3103	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
3104	//\| RT_BIT_32(10) - reserved
3105	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
3106	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
3107	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3108	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
3109	\| X86_CPUID_AMD_FEATURE_EDX_PGE
3110	\| X86_CPUID_AMD_FEATURE_EDX_MCA
3111	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
3112	\| X86_CPUID_AMD_FEATURE_EDX_PAT
3113	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
3114	//\| RT_BIT_32(18) - reserved
3115	//\| RT_BIT_32(19) - reserved
3116	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
3117	//\| RT_BIT_32(21) - reserved
3118	\| PASSTHRU_FEATURE(pConfig->enmAmdExtMmx, pHstFeat->fAmdMmxExts, X86_CPUID_AMD_FEATURE_EDX_AXMMX)
3119	\| X86_CPUID_AMD_FEATURE_EDX_MMX
3120	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
3121	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
3122	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3123	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
3124	//\| RT_BIT_32(28) - reserved
3125	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
3126	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
3127	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
3128	;
3129	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
3130	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
3131	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
3132	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3133	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
3134	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
3135	\| PASSTHRU_FEATURE_TODO(pConfig->enmAbm, X86_CPUID_AMD_FEATURE_ECX_ABM)
3136	\| PASSTHRU_FEATURE_TODO(pConfig->enmSse4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A)
3137	\| PASSTHRU_FEATURE_TODO(pConfig->enmMisAlnSse, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE)
3138	\| PASSTHRU_FEATURE(pConfig->enm3dNowPrf, pHstFeat->f3DNowPrefetch, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
3139	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3140	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
3141	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
3142	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3143	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
3144	//\| RT_BIT_32(14) - reserved
3145	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
3146	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
3147	//\| RT_BIT_32(17) - reserved
3148	//\| RT_BIT_32(18) - reserved
3149	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
3150	//\| RT_BIT_32(20) - reserved
3151	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
3152	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
3153	//\| RT_BIT_32(23) - reserved
3154	//\| RT_BIT_32(24) - reserved
3155	//\| RT_BIT_32(25) - reserved
3156	//\| RT_BIT_32(26) - reserved
3157	//\| RT_BIT_32(27) - reserved
3158	//\| RT_BIT_32(28) - reserved
3159	//\| RT_BIT_32(29) - reserved
3160	//\| RT_BIT_32(30) - reserved
3161	//\| RT_BIT_32(31) - reserved
3162	;
3163	#ifdef VBOX_WITH_MULTI_CORE
3164	if ( pVM->cCpus > 1
3165	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3166	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3167	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
3168	#endif
3169
3170	if (pCpum->u8PortableCpuIdLevel > 0)
3171	{
3172	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
3173	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
3174	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
3175	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
3176	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
3177	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
3178	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
3179	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
3180	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
3181	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
3182	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
3183	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
3184	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
3185	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
3186	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
3187	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
3188
3189	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
3190	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3191	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3192	\| X86_CPUID_AMD_FEATURE_ECX_IBS
3193	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3194	\| X86_CPUID_AMD_FEATURE_ECX_WDT
3195	\| X86_CPUID_AMD_FEATURE_ECX_LWP
3196	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
3197	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
3198	\| UINT32_C(0xff964000)
3199	)));
3200	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
3201	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3202	\| RT_BIT(18)
3203	\| RT_BIT(19)
3204	\| RT_BIT(21)
3205	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
3206	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3207	\| RT_BIT(28)
3208	)));
3209	}
3210
3211	/* Force extended feature bits. */
3212	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
3213	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
3214	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
3215	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
3216	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
3217	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
3218	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
3219	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
3220	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3221	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
3222	}
3223	pExtFeatureLeaf = NULL; /* Must refetch! */
3224
3225
3226	/* Cpuid 2:
3227	* Intel: (Nondeterministic) Cache and TLB information
3228	* AMD: Reserved
3229	* VIA: Reserved
3230	* Safe to expose.
3231	*/
3232	uint32_t uSubLeaf = 0;
3233	PCPUMCPUIDLEAF pCurLeaf;
3234	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
3235	{
3236	if ((pCurLeaf->uEax & 0xff) > 1)
3237	{
3238	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
3239	pCurLeaf->uEax &= UINT32_C(0xffffff01);
3240	}
3241	uSubLeaf++;
3242	}
3243
3244	/* Cpuid 3:
3245	* Intel: EAX, EBX - reserved (transmeta uses these)
3246	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3247	* AMD: Reserved
3248	* VIA: Reserved
3249	* Safe to expose
3250	*/
3251	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3252	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3253	{
3254	uSubLeaf = 0;
3255	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3256	{
3257	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3258	if (pCpum->u8PortableCpuIdLevel > 0)
3259	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3260	uSubLeaf++;
3261	}
3262	}
3263
3264	/* Cpuid 4 + ECX:
3265	* Intel: Deterministic Cache Parameters Leaf.
3266	* AMD: Reserved
3267	* VIA: Reserved
3268	* Safe to expose, except for EAX:
3269	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3270	* Bits 31-26: Maximum number of processor cores in this physical package**
3271	* Note: These SMP values are constant regardless of ECX
3272	*/
3273	uSubLeaf = 0;
3274	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3275	{
3276	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3277	#ifdef VBOX_WITH_MULTI_CORE
3278	if ( pVM->cCpus > 1
3279	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3280	{
3281	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3282	/* One logical processor with possibly multiple cores. */
3283	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3284	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3285	}
3286	#endif
3287	uSubLeaf++;
3288	}
3289
3290	/* Cpuid 5: Monitor/mwait Leaf
3291	* Intel: ECX, EDX - reserved
3292	* EAX, EBX - Smallest and largest monitor line size
3293	* AMD: EDX - reserved
3294	* EAX, EBX - Smallest and largest monitor line size
3295	* ECX - extensions (ignored for now)
3296	* VIA: Reserved
3297	* Safe to expose
3298	*/
3299	uSubLeaf = 0;
3300	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3301	{
3302	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3303	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3304	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3305
3306	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3307	if (pConfig->enmMWaitExtensions)
3308	{
3309	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3310	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3311	it shall be part of our power management virtualization model */
3312	#if 0
3313	/* MWAIT sub C-states */
3314	pCurLeaf->uEdx =
3315	(0 << 0) /* 0 in C0 */ \|
3316	(2 << 4) /* 2 in C1 */ \|
3317	(2 << 8) /* 2 in C2 */ \|
3318	(2 << 12) /* 2 in C3 */ \|
3319	(0 << 16) /* 0 in C4 */
3320	;
3321	#endif
3322	}
3323	else
3324	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3325	uSubLeaf++;
3326	}
3327
3328	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3329	* Intel: Various stuff.
3330	* AMD: EAX, EBX, EDX - reserved.
3331	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3332	* present. Same as intel.
3333	* VIA: ??
3334	*
3335	* We clear everything here for now.
3336	*/
3337	cpumR3CpuIdZeroLeaf(pCpum, 6);
3338
3339	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3340	* EAX: Number of sub leaves.
3341	* EBX+ECX+EDX: Feature flags
3342	*
3343	* We only have documentation for one sub-leaf, so clear all other (no need
3344	* to remove them as such, just set them to zero).
3345	*
3346	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3347	* options may require adjusting (i.e. stripping what was enabled).
3348	*/
3349	uSubLeaf = 0;
3350	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3351	{
3352	switch (uSubLeaf)
3353	{
3354	case 0:
3355	{
3356	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3357	pCurLeaf->uEbx &= 0
3358	\| PASSTHRU_FEATURE(pConfig->enmFsGsBase, pHstFeat->fFsGsBase, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE)
3359	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3360	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3361	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3362	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3363	\| PASSTHRU_FEATURE(pConfig->enmAvx2, pHstFeat->fAvx2, X86_CPUID_STEXT_FEATURE_EBX_AVX2)
3364	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3365	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3366	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3367	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3368	\| PASSTHRU_FEATURE(pConfig->enmInvpcid, pHstFeat->fInvpcid, X86_CPUID_STEXT_FEATURE_EBX_INVPCID)
3369	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3370	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3371	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3372	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3373	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3374	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3375	//\| RT_BIT(17) - reserved
3376	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdSeed, X86_CPUID_STEXT_FEATURE_EBX_RDSEED)
3377	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3378	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3379	//\| RT_BIT(21) - reserved
3380	//\| RT_BIT(22) - reserved
3381	\| PASSTHRU_FEATURE(pConfig->enmCLFlushOpt, pHstFeat->fClFlushOpt, X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT)
3382	//\| RT_BIT(24) - reserved
3383	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3384	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3385	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3386	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3387	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3388	//\| RT_BIT(30) - reserved
3389	//\| RT_BIT(31) - reserved
3390	;
3391	pCurLeaf->uEcx &= 0
3392	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3393	;
3394	pCurLeaf->uEdx &= 0
3395	\| PASSTHRU_FEATURE(pConfig->enmMdsClear, pHstFeat->fMdsClear, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR)
3396	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3397	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3398	\| PASSTHRU_FEATURE(pConfig->enmFlushCmdMsr, pHstFeat->fFlushCmd, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD)
3399	\| PASSTHRU_FEATURE(pConfig->enmArchCapMsr, pHstFeat->fArchCap, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
3400	;
3401
3402	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3403	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3404	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3405	{
3406	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3407	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3408	}
3409
3410	if (pCpum->u8PortableCpuIdLevel > 0)
3411	{
3412	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3413	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3414	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3415	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3416	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3417	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3418	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3419	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3420	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3421	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3422	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3423	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3424	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3425	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3426	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3427	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
3428	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
3429	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
3430	}
3431
3432	/* Dependencies. */
3433	if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
3434	pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3435
3436	/* Force standard feature bits. */
3437	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3438	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3439	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3440	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3441	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3442	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3443	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3444	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3445	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3446	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3447	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3448	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
3449	if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
3450	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3451	if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3452	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
3453	break;
3454	}
3455
3456	default:
3457	/* Invalid index, all values are zero. */
3458	pCurLeaf->uEax = 0;
3459	pCurLeaf->uEbx = 0;
3460	pCurLeaf->uEcx = 0;
3461	pCurLeaf->uEdx = 0;
3462	break;
3463	}
3464	uSubLeaf++;
3465	}
3466
3467	/* Cpuid 8: Marked as reserved by Intel and AMD.
3468	* We zero this since we don't know what it may have been used for.
3469	*/
3470	cpumR3CpuIdZeroLeaf(pCpum, 8);
3471
3472	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3473	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3474	* EBX, ECX, EDX - reserved.
3475	* AMD: Reserved
3476	* VIA: ??
3477	*
3478	* We zero this.
3479	*/
3480	cpumR3CpuIdZeroLeaf(pCpum, 9);
3481
3482	/* Cpuid 0xa: Architectural Performance Monitor Features
3483	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3484	* EBX, ECX, EDX - reserved.
3485	* AMD: Reserved
3486	* VIA: ??
3487	*
3488	* We zero this, for now at least.
3489	*/
3490	cpumR3CpuIdZeroLeaf(pCpum, 10);
3491
3492	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3493	* Intel: EAX - APCI ID shift right for next level.
3494	* EBX - Factory configured cores/threads at this level.
3495	* ECX - Level number (same as input) and level type (1,2,0).
3496	* EDX - Extended initial APIC ID.
3497	* AMD: Reserved
3498	* VIA: ??
3499	*/
3500	uSubLeaf = 0;
3501	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3502	{
3503	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3504	{
3505	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3506	if (bLevelType == 1)
3507	{
3508	/* Thread level - we don't do threads at the moment. */
3509	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3510	pCurLeaf->uEbx = 1;
3511	}
3512	else if (bLevelType == 2)
3513	{
3514	/* Core level. */
3515	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3516	#ifdef VBOX_WITH_MULTI_CORE
3517	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3518	pCurLeaf->uEax++;
3519	#endif
3520	pCurLeaf->uEbx = pVM->cCpus;
3521	}
3522	else
3523	{
3524	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3525	pCurLeaf->uEax = 0;
3526	pCurLeaf->uEbx = 0;
3527	pCurLeaf->uEcx = 0;
3528	}
3529	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3530	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3531	}
3532	else
3533	{
3534	pCurLeaf->uEax = 0;
3535	pCurLeaf->uEbx = 0;
3536	pCurLeaf->uEcx = 0;
3537	pCurLeaf->uEdx = 0;
3538	}
3539	uSubLeaf++;
3540	}
3541
3542	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3543	* We zero this since we don't know what it may have been used for.
3544	*/
3545	cpumR3CpuIdZeroLeaf(pCpum, 12);
3546
3547	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3548	* ECX=0: EAX - Valid bits in XCR0[31:0].
3549	* EBX - Maximum state size as per current XCR0 value.
3550	* ECX - Maximum state size for all supported features.
3551	* EDX - Valid bits in XCR0[63:32].
3552	* ECX=1: EAX - Various X-features.
3553	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3554	* ECX - Valid bits in IA32_XSS[31:0].
3555	* EDX - Valid bits in IA32_XSS[63:32].
3556	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3557	* if the bit invalid all four registers are set to zero.
3558	* EAX - The state size for this feature.
3559	* EBX - The state byte offset of this feature.
3560	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3561	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3562	*
3563	* Clear them all as we don't currently implement extended CPU state.
3564	*/
3565	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3566	uint64_t fGuestXcr0Mask = 0;
3567	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3568	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3569	{
3570	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3571	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3572	fGuestXcr0Mask \|= XSAVE_C_YMM;
3573	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3574	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3575	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3576	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3577
3578	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3579	}
3580	pStdFeatureLeaf = NULL;
3581	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3582
3583	/* Work the sub-leaves. */
3584	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3585	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3586	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3587	{
3588	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3589	if (pCurLeaf)
3590	{
3591	if (fGuestXcr0Mask)
3592	{
3593	switch (uSubLeaf)
3594	{
3595	case 0:
3596	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3597	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3598	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3599	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3600	VERR_CPUM_IPE_1);
3601	cbXSaveMaxActual = pCurLeaf->uEcx;
3602	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3603	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3604	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3605	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3606	VERR_CPUM_IPE_2);
3607	continue;
3608	case 1:
3609	pCurLeaf->uEax &= 0;
3610	pCurLeaf->uEcx &= 0;
3611	pCurLeaf->uEdx &= 0;
3612	/** @todo what about checking ebx? */
3613	continue;
3614	default:
3615	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3616	{
3617	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3618	&& pCurLeaf->uEax > 0
3619	&& pCurLeaf->uEbx < cbXSaveMaxActual
3620	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3621	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3622	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3623	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3624	VERR_CPUM_IPE_2);
3625	AssertLogRel(!(pCurLeaf->uEcx & 1));
3626	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3627	pCurLeaf->uEdx = 0; /* it's reserved... */
3628	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3629	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3630	continue;
3631	}
3632	break;
3633	}
3634	}
3635
3636	/* Clear the leaf. */
3637	pCurLeaf->uEax = 0;
3638	pCurLeaf->uEbx = 0;
3639	pCurLeaf->uEcx = 0;
3640	pCurLeaf->uEdx = 0;
3641	}
3642	}
3643
3644	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3645	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3646	{
3647	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3648	if (pCurLeaf)
3649	{
3650	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3651	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3652	pCurLeaf->uEbx = cbXSaveMaxReport;
3653	pCurLeaf->uEcx = cbXSaveMaxReport;
3654	}
3655	}
3656
3657	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3658	* We zero this since we don't know what it may have been used for.
3659	*/
3660	cpumR3CpuIdZeroLeaf(pCpum, 14);
3661
3662	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3663	* also known as Intel Resource Director Technology (RDT) Monitoring
3664	* We zero this as we don't currently virtualize PQM.
3665	*/
3666	cpumR3CpuIdZeroLeaf(pCpum, 15);
3667
3668	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3669	* also known as Intel Resource Director Technology (RDT) Allocation
3670	* We zero this as we don't currently virtualize PQE.
3671	*/
3672	cpumR3CpuIdZeroLeaf(pCpum, 16);
3673
3674	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3675	* We zero this since we don't know what it may have been used for.
3676	*/
3677	cpumR3CpuIdZeroLeaf(pCpum, 17);
3678
3679	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3680	* We zero this as we don't currently virtualize this.
3681	*/
3682	cpumR3CpuIdZeroLeaf(pCpum, 18);
3683
3684	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3685	* We zero this since we don't know what it may have been used for.
3686	*/
3687	cpumR3CpuIdZeroLeaf(pCpum, 19);
3688
3689	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3690	* We zero this as we don't currently virtualize this.
3691	*/
3692	cpumR3CpuIdZeroLeaf(pCpum, 20);
3693
3694	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3695	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3696	* EAX - denominator (unsigned).
3697	* EBX - numerator (unsigned).
3698	* ECX, EDX - reserved.
3699	* AMD: Reserved / undefined / not implemented.
3700	* VIA: Reserved / undefined / not implemented.
3701	* We zero this as we don't currently virtualize this.
3702	*/
3703	cpumR3CpuIdZeroLeaf(pCpum, 21);
3704
3705	/* Cpuid 0x16: Processor frequency info
3706	* Intel: EAX - Core base frequency in MHz.
3707	* EBX - Core maximum frequency in MHz.
3708	* ECX - Bus (reference) frequency in MHz.
3709	* EDX - Reserved.
3710	* AMD: Reserved / undefined / not implemented.
3711	* VIA: Reserved / undefined / not implemented.
3712	* We zero this as we don't currently virtualize this.
3713	*/
3714	cpumR3CpuIdZeroLeaf(pCpum, 22);
3715
3716	/* Cpuid 0x17..0x10000000: Unknown.
3717	* We don't know these and what they mean, so remove them. */
3718	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3719	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3720
3721
3722	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3723	* We remove all these as we're a hypervisor and must provide our own.
3724	*/
3725	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3726	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3727
3728
3729	/* Cpuid 0x80000000 is harmless. */
3730
3731	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3732
3733	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3734
3735	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3736	* Safe to pass on to the guest.
3737	*
3738	* AMD: 0x800000005 L1 cache information
3739	* 0x800000006 L2/L3 cache information
3740	* Intel: 0x800000005 reserved
3741	* 0x800000006 L2 cache information
3742	* VIA: 0x800000005 TLB and L1 cache information
3743	* 0x800000006 L2 cache information
3744	*/
3745
3746	/* Cpuid 0x800000007: Advanced Power Management Information.
3747	* AMD: EAX: Processor feedback capabilities.
3748	* EBX: RAS capabilites.
3749	* ECX: Advanced power monitoring interface.
3750	* EDX: Enhanced power management capabilities.
3751	* Intel: EAX, EBX, ECX - reserved.
3752	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3753	* VIA: Reserved
3754	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3755	*/
3756	uSubLeaf = 0;
3757	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3758	{
3759	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3760	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3761	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3762	{
3763	/*
3764	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3765	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3766	* bit is now configurable.
3767	*/
3768	pCurLeaf->uEdx &= 0
3769	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3770	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3771	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3772	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3773	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3774	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3775	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3776	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3777	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3778	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3779	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3780	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3781	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3782	\| 0;
3783	}
3784	else
3785	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3786	if (!pConfig->fInvariantTsc)
3787	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3788	uSubLeaf++;
3789	}
3790
3791	/* Cpuid 0x80000008:
3792	* AMD: EBX, EDX - reserved
3793	* EAX: Virtual/Physical/Guest address Size
3794	* ECX: Number of cores + APICIdCoreIdSize
3795	* Intel: EAX: Virtual/Physical address Size
3796	* EBX, ECX, EDX - reserved
3797	* VIA: EAX: Virtual/Physical address Size
3798	* EBX, ECX, EDX - reserved
3799	*
3800	* We only expose the virtual+pysical address size to the guest atm.
3801	* On AMD we set the core count, but not the apic id stuff as we're
3802	* currently not doing the apic id assignments in a complatible manner.
3803	*/
3804	uSubLeaf = 0;
3805	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3806	{
3807	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3808	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3809	pCurLeaf->uEdx = 0; /* reserved */
3810
3811	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3812	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3813	pCurLeaf->uEcx = 0;
3814	#ifdef VBOX_WITH_MULTI_CORE
3815	if ( pVM->cCpus > 1
3816	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3817	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3818	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3819	#endif
3820	uSubLeaf++;
3821	}
3822
3823	/* Cpuid 0x80000009: Reserved
3824	* We zero this since we don't know what it may have been used for.
3825	*/
3826	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3827
3828	/* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
3829	* AMD: EAX - SVM revision.
3830	* EBX - Number of ASIDs.
3831	* ECX - Reserved.
3832	* EDX - SVM Feature identification.
3833	*/
3834	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3835	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3836	{
3837	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3838	if ( pExtFeatureLeaf
3839	&& (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM))
3840	{
3841	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3842	if (pSvmFeatureLeaf)
3843	{
3844	pSvmFeatureLeaf->uEax = 0x1;
3845	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3846	pSvmFeatureLeaf->uEcx = 0;
3847	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3848	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3849	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3850	}
3851	else
3852	{
3853	/* Should never happen. */
3854	LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
3855	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3856	}
3857	}
3858	else
3859	{
3860	/* If SVM is not supported, this is reserved, zero out. */
3861	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3862	}
3863	}
3864	else
3865	{
3866	/* Cpuid 0x8000000a: Reserved on Intel.
3867	* We zero this since we don't know what it may have been used for.
3868	*/
3869	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3870	}
3871
3872	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3873	* We clear these as we don't know what purpose they might have. */
3874	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3875	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3876
3877	/* Cpuid 0x80000019: TLB configuration
3878	* Seems to be harmless, pass them thru as is. */
3879
3880	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3881	* Strip anything we don't know what is or addresses feature we don't implement. */
3882	uSubLeaf = 0;
3883	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3884	{
3885	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3886	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3887	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3888	;
3889	pCurLeaf->uEbx = 0; /* reserved */
3890	pCurLeaf->uEcx = 0; /* reserved */
3891	pCurLeaf->uEdx = 0; /* reserved */
3892	uSubLeaf++;
3893	}
3894
3895	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3896	* Clear this as we don't currently virtualize this feature. */
3897	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3898
3899	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3900	* Clear this as we don't currently virtualize this feature. */
3901	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3902
3903	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3904	* We need to sanitize the cores per cache (EAX[25:14]).
3905	*
3906	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3907	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3908	* slightly different meaning.
3909	*/
3910	uSubLeaf = 0;
3911	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3912	{
3913	#ifdef VBOX_WITH_MULTI_CORE
3914	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3915	if (cCores > pVM->cCpus)
3916	cCores = pVM->cCpus;
3917	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3918	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3919	#else
3920	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3921	#endif
3922	uSubLeaf++;
3923	}
3924
3925	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3926	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3927	* setup, we have one compute unit with all the cores in it. Single node.
3928	*/
3929	uSubLeaf = 0;
3930	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3931	{
3932	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3933	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3934	{
3935	#ifdef VBOX_WITH_MULTI_CORE
3936	pCurLeaf->uEbx = pVM->cCpus < 0x100
3937	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3938	#else
3939	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3940	#endif
3941	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3942	}
3943	else
3944	{
3945	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3946	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_HYGON);
3947	pCurLeaf->uEbx = 0; /* Reserved. */
3948	pCurLeaf->uEcx = 0; /* Reserved. */
3949	}
3950	pCurLeaf->uEdx = 0; /* Reserved. */
3951	uSubLeaf++;
3952	}
3953
3954	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3955	* We don't know these and what they mean, so remove them. */
3956	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3957	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3958
3959	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3960	* Just pass it thru for now. */
3961
3962	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3963	* Just pass it thru for now. */
3964
3965	/* Cpuid 0xc0000000: Centaur stuff.
3966	* Harmless, pass it thru. */
3967
3968	/* Cpuid 0xc0000001: Centaur features.
3969	* VIA: EAX - Family, model, stepping.
3970	* EDX - Centaur extended feature flags. Nothing interesting, except may
3971	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3972	* EBX, ECX - reserved.
3973	* We keep EAX but strips the rest.
3974	*/
3975	uSubLeaf = 0;
3976	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3977	{
3978	pCurLeaf->uEbx = 0;
3979	pCurLeaf->uEcx = 0;
3980	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3981	uSubLeaf++;
3982	}
3983
3984	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3985	* We only have fixed stale values, but should be harmless. */
3986
3987	/* Cpuid 0xc0000003: Reserved.
3988	* We zero this since we don't know what it may have been used for.
3989	*/
3990	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3991
3992	/* Cpuid 0xc0000004: Centaur Performance Info.
3993	* We only have fixed stale values, but should be harmless. */
3994
3995
3996	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3997	* We don't know these and what they mean, so remove them. */
3998	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3999	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
4000
4001	return VINF_SUCCESS;
4002	#undef PORTABLE_DISABLE_FEATURE_BIT
4003	#undef PORTABLE_CLEAR_BITS_WHEN
4004	}
4005
4006
4007	/**
4008	* Reads a value in /CPUM/IsaExts/ node.
4009	*
4010	* @returns VBox status code (error message raised).
4011	* @param pVM The cross context VM structure. (For errors.)
4012	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4013	* @param pszValueName The value / extension name.
4014	* @param penmValue Where to return the choice.
4015	* @param enmDefault The default choice.
4016	*/
4017	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
4018	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
4019	{
4020	/*
4021	* Try integer encoding first.
4022	*/
4023	uint64_t uValue;
4024	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
4025	if (RT_SUCCESS(rc))
4026	switch (uValue)
4027	{
4028	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
4029	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
4030	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
4031	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
4032	default:
4033	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
4034	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
4035	pszValueName, uValue);
4036	}
4037	/*
4038	* If missing, use default.
4039	*/
4040	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
4041	*penmValue = enmDefault;
4042	else
4043	{
4044	if (rc == VERR_CFGM_NOT_INTEGER)
4045	{
4046	/*
4047	* Not an integer, try read it as a string.
4048	*/
4049	char szValue[32];
4050	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
4051	if (RT_SUCCESS(rc))
4052	{
4053	RTStrToLower(szValue);
4054	size_t cchValue = strlen(szValue);
4055	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
4056	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
4057	*penmValue = CPUMISAEXTCFG_DISABLED;
4058	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
4059	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
4060	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
4061	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
4062	else if (EQ("portable"))
4063	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
4064	else if (EQ("default") \|\| EQ("def"))
4065	*penmValue = enmDefault;
4066	else
4067	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
4068	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
4069	pszValueName, uValue);
4070	#undef EQ
4071	}
4072	}
4073	if (RT_FAILURE(rc))
4074	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
4075	}
4076	return VINF_SUCCESS;
4077	}
4078
4079
4080	/**
4081	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
4082	*
4083	* @returns VBox status code (error message raised).
4084	* @param pVM The cross context VM structure. (For errors.)
4085	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4086	* @param pszValueName The value / extension name.
4087	* @param penmValue Where to return the choice.
4088	* @param enmDefault The default choice.
4089	* @param fAllowed Allowed choice. Applied both to the result and to
4090	* the default value.
4091	*/
4092	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
4093	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
4094	{
4095	int rc;
4096	if (fAllowed)
4097	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4098	else
4099	{
4100	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
4101	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
4102	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
4103	*penmValue = CPUMISAEXTCFG_DISABLED;
4104	}
4105	return rc;
4106	}
4107
4108
4109	/**
4110	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
4111	*
4112	* @returns VBox status code (error message raised).
4113	* @param pVM The cross context VM structure. (For errors.)
4114	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4115	* @param pCpumCfg The /CPUM node (can be NULL).
4116	* @param pszValueName The value / extension name.
4117	* @param penmValue Where to return the choice.
4118	* @param enmDefault The default choice.
4119	*/
4120	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
4121	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
4122	{
4123	if (CFGMR3Exists(pCpumCfg, pszValueName))
4124	{
4125	if (!CFGMR3Exists(pIsaExts, pszValueName))
4126	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
4127	else
4128	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
4129	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
4130	pszValueName, pszValueName);
4131
4132	bool fLegacy;
4133	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
4134	if (RT_SUCCESS(rc))
4135	{
4136	*penmValue = fLegacy;
4137	return VINF_SUCCESS;
4138	}
4139	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
4140	}
4141
4142	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4143	}
4144
4145
4146	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
4147	{
4148	int rc;
4149
4150	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
4151	* When non-zero CPUID features that could cause portability issues will be
4152	* stripped. The higher the value the more features gets stripped. Higher
4153	* values should only be used when older CPUs are involved since it may
4154	* harm performance and maybe also cause problems with specific guests. */
4155	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
4156	AssertLogRelRCReturn(rc, rc);
4157
4158	/** @cfgm{/CPUM/GuestCpuName, string}
4159	* The name of the CPU we're to emulate. The default is the host CPU.
4160	* Note! CPUs other than "host" one is currently unsupported. */
4161	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
4162	AssertLogRelRCReturn(rc, rc);
4163
4164	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
4165	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
4166	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
4167	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
4168	*/
4169	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
4170	AssertLogRelRCReturn(rc, rc);
4171
4172	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
4173	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
4174	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
4175	* 64-bit linux guests which assume the presence of AMD performance counters
4176	* that we do not virtualize.
4177	*/
4178	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
4179	AssertLogRelRCReturn(rc, rc);
4180
4181	/** @cfgm{/CPUM/ForceVme, boolean, false}
4182	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
4183	* By default the flag is passed thru as is from the host CPU, except
4184	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
4185	* guests and DOS boxes in general.
4186	*/
4187	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
4188	AssertLogRelRCReturn(rc, rc);
4189
4190	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
4191	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
4192	* probably going to be a temporary hack, so don't depend on this.
4193	* The 1st byte of the value is the stepping, the 2nd byte value is the model
4194	* number and the 3rd byte value is the family, and the 4th value must be zero.
4195	*/
4196	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
4197	AssertLogRelRCReturn(rc, rc);
4198
4199	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
4200	* The last standard leaf to keep. The actual last value that is stored in EAX
4201	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
4202	* removed. (This works independently of and differently from NT4LeafLimit.)
4203	* The default is usually set to what we're able to reasonably sanitize.
4204	*/
4205	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
4206	AssertLogRelRCReturn(rc, rc);
4207
4208	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
4209	* The last extended leaf to keep. The actual last value that is stored in EAX
4210	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
4211	* leaf are removed. The default is set to what we're able to sanitize.
4212	*/
4213	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
4214	AssertLogRelRCReturn(rc, rc);
4215
4216	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
4217	* The last extended leaf to keep. The actual last value that is stored in EAX
4218	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
4219	* leaf are removed. The default is set to what we're able to sanitize.
4220	*/
4221	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
4222	AssertLogRelRCReturn(rc, rc);
4223
4224	bool fQueryNestedHwvirt = false
4225	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4226	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4227	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON
4228	#endif
4229	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4230	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
4231	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA
4232	#endif
4233	;
4234	if (fQueryNestedHwvirt)
4235	{
4236	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
4237	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
4238	* The default is false, and when enabled requires a 64-bit CPU with support for
4239	* nested-paging and AMD-V or unrestricted guest mode.
4240	*/
4241	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
4242	AssertLogRelRCReturn(rc, rc);
4243	if (pConfig->fNestedHWVirt)
4244	{
4245	/** @todo Think about enabling this later with NEM/KVM. */
4246	if (VM_IS_NEM_ENABLED(pVM))
4247	{
4248	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used! (later)\n"));
4249	pConfig->fNestedHWVirt = false;
4250	}
4251	else if (!fNestedPagingAndFullGuestExec)
4252	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
4253	"Cannot enable nested VT-x/AMD-V without nested-paging and unrestricted guest execution!\n");
4254	}
4255
4256	if (pConfig->fNestedHWVirt)
4257	{
4258	/** @cfgm{/CPUM/NestedVmxPreemptTimer, bool, true}
4259	* Whether to expose the VMX-preemption timer feature to the guest (if also
4260	* supported by the host hardware). When disabled will prevent exposing the
4261	* VMX-preemption timer feature to the guest even if the host supports it.
4262	*
4263	* @todo Currently disabled, see @bugref{9180#c108}.
4264	*/
4265	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxPreemptTimer", &pVM->cpum.s.fNestedVmxPreemptTimer, false);
4266	AssertLogRelRCReturn(rc, rc);
4267
4268	/** @cfgm{/CPUM/NestedVmxEpt, bool, true}
4269	* Whether to expose the EPT feature to the guest. The default is false. When
4270	* disabled will automatically prevent exposing features that rely on
4271	*/
4272	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxEpt", &pVM->cpum.s.fNestedVmxEpt, false);
4273	AssertLogRelRCReturn(rc, rc);
4274
4275	/** @cfgm{/CPUM/NestedVmxUnrestrictedGuest, bool, true}
4276	* Whether to expose the Unrestricted Guest feature to the guest. The default is
4277	* false. When disabled will automatically prevent exposing features that rely on
4278	* it.
4279	*/
4280	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxUnrestrictedGuest", &pVM->cpum.s.fNestedVmxUnrestrictedGuest, false);
4281	AssertLogRelRCReturn(rc, rc);
4282
4283	if ( pVM->cpum.s.fNestedVmxUnrestrictedGuest
4284	&& !pVM->cpum.s.fNestedVmxEpt)
4285	{
4286	LogRel(("CPUM: WARNING! Can't expose \"Unrestricted Guest\" to the guest when EPT is not exposed!\n"));
4287	pVM->cpum.s.fNestedVmxUnrestrictedGuest = false;
4288	}
4289	}
4290	}
4291
4292	/*
4293	* Instruction Set Architecture (ISA) Extensions.
4294	*/
4295	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
4296	if (pIsaExts)
4297	{
4298	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
4299	"CMPXCHG16B"
4300	"\|MONITOR"
4301	"\|MWaitExtensions"
4302	"\|SSE4.1"
4303	"\|SSE4.2"
4304	"\|XSAVE"
4305	"\|AVX"
4306	"\|AVX2"
4307	"\|AESNI"
4308	"\|PCLMUL"
4309	"\|POPCNT"
4310	"\|MOVBE"
4311	"\|RDRAND"
4312	"\|RDSEED"
4313	"\|CLFLUSHOPT"
4314	"\|FSGSBASE"
4315	"\|PCID"
4316	"\|INVPCID"
4317	"\|FlushCmdMsr"
4318	"\|ABM"
4319	"\|SSE4A"
4320	"\|MISALNSSE"
4321	"\|3DNOWPRF"
4322	"\|AXMMX"
4323	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
4324	if (RT_FAILURE(rc))
4325	return rc;
4326	}
4327
4328	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, true}
4329	* Expose CMPXCHG16B to the guest if available. All host CPUs which support
4330	* hardware virtualization have it.
4331	*/
4332	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, true);
4333	AssertLogRelRCReturn(rc, rc);
4334
4335	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
4336	* Expose MONITOR/MWAIT instructions to the guest.
4337	*/
4338	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
4339	AssertLogRelRCReturn(rc, rc);
4340
4341	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4342	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4343	* break on interrupt feature (bit 1).
4344	*/
4345	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4346	AssertLogRelRCReturn(rc, rc);
4347
4348	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4349	* Expose SSE4.1 to the guest if available.
4350	*/
4351	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4352	AssertLogRelRCReturn(rc, rc);
4353
4354	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4355	* Expose SSE4.2 to the guest if available.
4356	*/
4357	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4358	AssertLogRelRCReturn(rc, rc);
4359
4360	bool const fMayHaveXSave = pVM->cpum.s.HostFeatures.fXSaveRstor
4361	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
4362	&& ( VM_IS_NEM_ENABLED(pVM)
4363	? NEMHCGetFeatures(pVM) & NEM_FEAT_F_XSAVE_XRSTOR
4364	: VM_IS_EXEC_ENGINE_IEM(pVM)
4365	? false /** @todo IEM and XSAVE @bugref{9898} */
4366	: fNestedPagingAndFullGuestExec);
4367	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4368
4369	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4370	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4371	* default is to only expose this to VMs with nested paging and AMD-V or
4372	* unrestricted guest execution mode. Not possible to force this one without
4373	* host support at the moment.
4374	*/
4375	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4376	fMayHaveXSave /fAllowed/);
4377	AssertLogRelRCReturn(rc, rc);
4378
4379	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4380	* Expose the AVX instruction set extensions to the guest if available and
4381	* XSAVE is exposed too. For the time being the default is to only expose this
4382	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4383	*/
4384	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4385	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4386	AssertLogRelRCReturn(rc, rc);
4387
4388	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4389	* Expose the AVX2 instruction set extensions to the guest if available and
4390	* XSAVE is exposed too. For the time being the default is to only expose this
4391	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4392	*/
4393	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4394	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4395	AssertLogRelRCReturn(rc, rc);
4396
4397	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4398	* Whether to expose the AES instructions to the guest. For the time being the
4399	* default is to only do this for VMs with nested paging and AMD-V or
4400	* unrestricted guest mode.
4401	*/
4402	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4403	AssertLogRelRCReturn(rc, rc);
4404
4405	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4406	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4407	* being the default is to only do this for VMs with nested paging and AMD-V or
4408	* unrestricted guest mode.
4409	*/
4410	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4411	AssertLogRelRCReturn(rc, rc);
4412
4413	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4414	* Whether to expose the POPCNT instructions to the guest. For the time
4415	* being the default is to only do this for VMs with nested paging and AMD-V or
4416	* unrestricted guest mode.
4417	*/
4418	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4419	AssertLogRelRCReturn(rc, rc);
4420
4421	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4422	* Whether to expose the MOVBE instructions to the guest. For the time
4423	* being the default is to only do this for VMs with nested paging and AMD-V or
4424	* unrestricted guest mode.
4425	*/
4426	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4427	AssertLogRelRCReturn(rc, rc);
4428
4429	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4430	* Whether to expose the RDRAND instructions to the guest. For the time being
4431	* the default is to only do this for VMs with nested paging and AMD-V or
4432	* unrestricted guest mode.
4433	*/
4434	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4435	AssertLogRelRCReturn(rc, rc);
4436
4437	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4438	* Whether to expose the RDSEED instructions to the guest. For the time being
4439	* the default is to only do this for VMs with nested paging and AMD-V or
4440	* unrestricted guest mode.
4441	*/
4442	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4443	AssertLogRelRCReturn(rc, rc);
4444
4445	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4446	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4447	* being the default is to only do this for VMs with nested paging and AMD-V or
4448	* unrestricted guest mode.
4449	*/
4450	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4451	AssertLogRelRCReturn(rc, rc);
4452
4453	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4454	* Whether to expose the read/write FSGSBASE instructions to the guest.
4455	*/
4456	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4457	AssertLogRelRCReturn(rc, rc);
4458
4459	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4460	* Whether to expose the PCID feature to the guest.
4461	*/
4462	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4463	AssertLogRelRCReturn(rc, rc);
4464
4465	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4466	* Whether to expose the INVPCID instruction to the guest.
4467	*/
4468	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4469	AssertLogRelRCReturn(rc, rc);
4470
4471	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
4472	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
4473	*/
4474	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4475	AssertLogRelRCReturn(rc, rc);
4476
4477	/** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
4478	* Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
4479	* the guest. Requires FlushCmdMsr to be present too.
4480	*/
4481	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4482	AssertLogRelRCReturn(rc, rc);
4483
4484	/** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
4485	* Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
4486	*/
4487	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4488	AssertLogRelRCReturn(rc, rc);
4489
4490
4491	/* AMD: */
4492
4493	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4494	* Whether to expose the AMD ABM instructions to the guest. For the time
4495	* being the default is to only do this for VMs with nested paging and AMD-V or
4496	* unrestricted guest mode.
4497	*/
4498	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4499	AssertLogRelRCReturn(rc, rc);
4500
4501	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4502	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4503	* being the default is to only do this for VMs with nested paging and AMD-V or
4504	* unrestricted guest mode.
4505	*/
4506	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4507	AssertLogRelRCReturn(rc, rc);
4508
4509	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4510	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4511	* the time being the default is to only do this for VMs with nested paging and
4512	* AMD-V or unrestricted guest mode.
4513	*/
4514	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4515	AssertLogRelRCReturn(rc, rc);
4516
4517	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4518	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4519	* For the time being the default is to only do this for VMs with nested paging
4520	* and AMD-V or unrestricted guest mode.
4521	*/
4522	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4523	AssertLogRelRCReturn(rc, rc);
4524
4525	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4526	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4527	* the default is to only do this for VMs with nested paging and AMD-V or
4528	* unrestricted guest mode.
4529	*/
4530	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4531	AssertLogRelRCReturn(rc, rc);
4532
4533	return VINF_SUCCESS;
4534	}
4535
4536
4537	/**
4538	* Initializes the emulated CPU's CPUID & MSR information.
4539	*
4540	* @returns VBox status code.
4541	* @param pVM The cross context VM structure.
4542	* @param pHostMsrs Pointer to the host MSRs.
4543	*/
4544	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
4545	{
4546	Assert(pHostMsrs);
4547
4548	PCPUM pCpum = &pVM->cpum.s;
4549	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4550
4551	/*
4552	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4553	* on construction and manage everything from here on.
4554	*/
4555	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4556	{
4557	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4558	pVCpu->cpum.s.fCpuIdApicFeatureVisible = true;
4559	}
4560
4561	/*
4562	* Read the configuration.
4563	*/
4564	CPUMCPUIDCONFIG Config;
4565	RT_ZERO(Config);
4566
4567	bool const fNestedPagingAndFullGuestExec = VM_IS_NEM_ENABLED(pVM)
4568	\|\| HMAreNestedPagingAndFullGuestExecEnabled(pVM);
4569	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, fNestedPagingAndFullGuestExec);
4570	AssertRCReturn(rc, rc);
4571
4572	/*
4573	* Get the guest CPU data from the database and/or the host.
4574	*
4575	* The CPUID and MSRs are currently living on the regular heap to avoid
4576	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4577	* API for the hyper heap). This means special cleanup considerations.
4578	*/
4579	/** @todo The hyper heap will be removed ASAP, so the final destination is
4580	* now a fixed sized arrays in the VM structure. Maybe we can simplify
4581	* this allocation fun a little now? Or maybe it's too convenient for
4582	* the CPU reporter code... No time to figure that out now. */
4583	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4584	if (RT_FAILURE(rc))
4585	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4586	? VMSetError(pVM, rc, RT_SRC_POS,
4587	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4588	: rc;
4589
4590	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
4591	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4592	{
4593	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4594	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4595	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4596	}
4597	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4598	#else
4599	LogRel(("CPUM: MXCSR_MASK=%#x\n", pCpum->GuestInfo.fMxCsrMask));
4600	#endif
4601
4602	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4603	* Overrides the guest MSRs.
4604	*/
4605	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4606
4607	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4608	* Overrides the CPUID leaf values (from the host CPU usually) used for
4609	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4610	* values when moving a VM to a different machine. Another use is restricting
4611	* (or extending) the feature set exposed to the guest. */
4612	if (RT_SUCCESS(rc))
4613	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4614
4615	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4616	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4617	"Found unsupported configuration node '/CPUM/CPUID/'. "
4618	"Please use IMachine::setCPUIDLeaf() instead.");
4619
4620	CPUMMSRS GuestMsrs;
4621	RT_ZERO(GuestMsrs);
4622
4623	/*
4624	* Pre-explode the CPUID info.
4625	*/
4626	if (RT_SUCCESS(rc))
4627	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
4628	&pCpum->GuestFeatures);
4629
4630	/*
4631	* Sanitize the cpuid information passed on to the guest.
4632	*/
4633	if (RT_SUCCESS(rc))
4634	{
4635	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4636	if (RT_SUCCESS(rc))
4637	{
4638	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4639	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4640	}
4641	}
4642
4643	/*
4644	* Setup MSRs introduced in microcode updates or that are otherwise not in
4645	* the CPU profile, but are advertised in the CPUID info we just sanitized.
4646	*/
4647	if (RT_SUCCESS(rc))
4648	rc = cpumR3MsrReconcileWithCpuId(pVM);
4649	/*
4650	* MSR fudging.
4651	*/
4652	if (RT_SUCCESS(rc))
4653	{
4654	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4655	* Fudges some common MSRs if not present in the selected CPU database entry.
4656	* This is for trying to keep VMs running when moved between different hosts
4657	* and different CPU vendors. */
4658	bool fEnable;
4659	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4660	if (RT_SUCCESS(rc) && fEnable)
4661	{
4662	rc = cpumR3MsrApplyFudge(pVM);
4663	AssertLogRelRC(rc);
4664	}
4665	}
4666	if (RT_SUCCESS(rc))
4667	{
4668	/*
4669	* Move the MSR and CPUID arrays over to the static VM structure allocations
4670	* and explode guest CPU features again.
4671	*/
4672	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4673	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4674	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
4675	RTMemFree(pvFree);
4676
4677	AssertFatalMsg(pCpum->GuestInfo.cMsrRanges <= RT_ELEMENTS(pCpum->GuestInfo.aMsrRanges),
4678	("%u\n", pCpum->GuestInfo.cMsrRanges));
4679	memcpy(pCpum->GuestInfo.aMsrRanges, pCpum->GuestInfo.paMsrRangesR3,
4680	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges);
4681	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4682	pCpum->GuestInfo.paMsrRangesR3 = pCpum->GuestInfo.aMsrRanges;
4683
4684	AssertLogRelRCReturn(rc, rc);
4685
4686	/*
4687	* Finally, initialize guest VMX MSRs.
4688	*
4689	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
4690	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
4691	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
4692	*/
4693	if (pVM->cpum.s.GuestFeatures.fVmx)
4694	{
4695	Assert(Config.fNestedHWVirt);
4696	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
4697
4698	/* Copy MSRs to all VCPUs */
4699	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
4700	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4701	{
4702	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4703	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
4704	}
4705	}
4706
4707	/*
4708	* Some more configuration that we're applying at the end of everything
4709	* via the CPUMR3SetGuestCpuIdFeature API.
4710	*/
4711
4712	/* Check if PAE was explicitely enabled by the user. */
4713	bool fEnable;
4714	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4715	AssertRCReturn(rc, rc);
4716	if (fEnable)
4717	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4718
4719	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4720	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4721	AssertRCReturn(rc, rc);
4722	if (fEnable)
4723	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4724
4725	/* Check if speculation control is enabled. */
4726	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4727	AssertRCReturn(rc, rc);
4728	if (fEnable)
4729	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4730	else
4731	{
4732	/*
4733	* Set the "SSBD-not-needed" flag to work around a bug in some Linux kernels when the VIRT_SPEC_CTL
4734	* feature is not exposed on AMD CPUs and there is only 1 vCPU configured.
4735	* This was observed with kernel "4.15.0-29-generic #31~16.04.1-Ubuntu" but more versions are likely affected.
4736	*
4737	* The kernel doesn't initialize a lock and causes a NULL pointer exception later on when configuring SSBD:
4738	* EIP: _raw_spin_lock+0x14/0x30
4739	* EFLAGS: 00010046 CPU: 0
4740	* EAX: 00000000 EBX: 00000001 ECX: 00000004 EDX: 00000000
4741	* ESI: 00000000 EDI: 00000000 EBP: ee023f1c ESP: ee023f18
4742	* DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
4743	* CR0: 80050033 CR2: 00000004 CR3: 3671c180 CR4: 000006f0
4744	* Call Trace:
4745	* speculative_store_bypass_update+0x8e/0x180
4746	* ssb_prctl_set+0xc0/0xe0
4747	* arch_seccomp_spec_mitigate+0x1d/0x20
4748	* do_seccomp+0x3cb/0x610
4749	* SyS_seccomp+0x16/0x20
4750	* do_fast_syscall_32+0x7f/0x1d0
4751	* entry_SYSENTER_32+0x4e/0x7c
4752	*
4753	* The lock would've been initialized in process.c:speculative_store_bypass_ht_init() called from two places in smpboot.c.
4754	* First when a secondary CPU is started and second in native_smp_prepare_cpus() which is not called in a single vCPU environment.
4755	*
4756	* As spectre control features are completely disabled anyway when we arrived here there is no harm done in informing the
4757	* guest to not even try.
4758	*/
4759	if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4760	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
4761	{
4762	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x80000008), 0);
4763	if (pLeaf)
4764	{
4765	pLeaf->uEbx \|= X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED;
4766	LogRel(("CPUM: Set SSBD not required flag for AMD to work around some buggy Linux kernels!\n"));
4767	}
4768	}
4769	}
4770
4771	return VINF_SUCCESS;
4772	}
4773
4774	/*
4775	* Failed before switching to hyper heap.
4776	*/
4777	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4778	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4779	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4780	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4781	return rc;
4782	}
4783
4784
4785	/**
4786	* Sets a CPUID feature bit during VM initialization.
4787	*
4788	* Since the CPUID feature bits are generally related to CPU features, other
4789	* CPUM configuration like MSRs can also be modified by calls to this API.
4790	*
4791	* @param pVM The cross context VM structure.
4792	* @param enmFeature The feature to set.
4793	*/
4794	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4795	{
4796	PCPUMCPUIDLEAF pLeaf;
4797	PCPUMMSRRANGE pMsrRange;
4798
4799	switch (enmFeature)
4800	{
4801	/*
4802	* Set the APIC bit in both feature masks.
4803	*/
4804	case CPUMCPUIDFEATURE_APIC:
4805	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4806	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4807	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4808
4809	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4810	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4811	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4812
4813	pVM->cpum.s.GuestFeatures.fApic = 1;
4814
4815	/* Make sure we've got the APICBASE MSR present. */
4816	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4817	if (!pMsrRange)
4818	{
4819	static CPUMMSRRANGE const s_ApicBase =
4820	{
4821	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4822	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4823	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4824	/.szName = / "IA32_APIC_BASE"
4825	};
4826	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4827	AssertLogRelRC(rc);
4828	}
4829
4830	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4831	break;
4832
4833	/*
4834	* Set the x2APIC bit in the standard feature mask.
4835	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4836	*/
4837	case CPUMCPUIDFEATURE_X2APIC:
4838	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4839	if (pLeaf)
4840	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4841	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4842
4843	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4844	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4845	if (pMsrRange)
4846	{
4847	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4848	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4849	}
4850
4851	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4852	break;
4853
4854	/*
4855	* Set the sysenter/sysexit bit in the standard feature mask.
4856	* Assumes the caller knows what it's doing! (host must support these)
4857	*/
4858	case CPUMCPUIDFEATURE_SEP:
4859	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4860	{
4861	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4862	return;
4863	}
4864
4865	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4866	if (pLeaf)
4867	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4868	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4869	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4870	break;
4871
4872	/*
4873	* Set the syscall/sysret bit in the extended feature mask.
4874	* Assumes the caller knows what it's doing! (host must support these)
4875	*/
4876	case CPUMCPUIDFEATURE_SYSCALL:
4877	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4878	if ( !pLeaf
4879	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4880	{
4881	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4882	return;
4883	}
4884
4885	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4886	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4887	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4888	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4889	break;
4890
4891	/*
4892	* Set the PAE bit in both feature masks.
4893	* Assumes the caller knows what it's doing! (host must support these)
4894	*/
4895	case CPUMCPUIDFEATURE_PAE:
4896	if (!pVM->cpum.s.HostFeatures.fPae)
4897	{
4898	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4899	return;
4900	}
4901
4902	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4903	if (pLeaf)
4904	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4905
4906	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4907	if ( pLeaf
4908	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4909	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
4910	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4911
4912	pVM->cpum.s.GuestFeatures.fPae = 1;
4913	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4914	break;
4915
4916	/*
4917	* Set the LONG MODE bit in the extended feature mask.
4918	* Assumes the caller knows what it's doing! (host must support these)
4919	*/
4920	case CPUMCPUIDFEATURE_LONG_MODE:
4921	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4922	if ( !pLeaf
4923	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4924	{
4925	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4926	return;
4927	}
4928
4929	/* Valid for both Intel and AMD. */
4930	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4931	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4932	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
4933	if (pVM->cpum.s.GuestFeatures.fVmx)
4934	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4935	{
4936	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4937	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic &= ~VMX_BASIC_PHYSADDR_WIDTH_32BIT;
4938	}
4939	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4940	break;
4941
4942	/*
4943	* Set the NX/XD bit in the extended feature mask.
4944	* Assumes the caller knows what it's doing! (host must support these)
4945	*/
4946	case CPUMCPUIDFEATURE_NX:
4947	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4948	if ( !pLeaf
4949	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4950	{
4951	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4952	return;
4953	}
4954
4955	/* Valid for both Intel and AMD. */
4956	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4957	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4958	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4959	break;
4960
4961
4962	/*
4963	* Set the LAHF/SAHF support in 64-bit mode.
4964	* Assumes the caller knows what it's doing! (host must support this)
4965	*/
4966	case CPUMCPUIDFEATURE_LAHF:
4967	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4968	if ( !pLeaf
4969	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4970	{
4971	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4972	return;
4973	}
4974
4975	/* Valid for both Intel and AMD. */
4976	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4977	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4978	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4979	break;
4980
4981	/*
4982	* Set the RDTSCP support bit.
4983	* Assumes the caller knows what it's doing! (host must support this)
4984	*/
4985	case CPUMCPUIDFEATURE_RDTSCP:
4986	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4987	if ( !pLeaf
4988	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4989	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4990	{
4991	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4992	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4993	return;
4994	}
4995
4996	/* Valid for both Intel and AMD. */
4997	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4998	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4999	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
5000	break;
5001
5002	/*
5003	* Set the Hypervisor Present bit in the standard feature mask.
5004	*/
5005	case CPUMCPUIDFEATURE_HVP:
5006	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5007	if (pLeaf)
5008	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
5009	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
5010	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
5011	break;
5012
5013	/*
5014	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
5015	* on Intel CPUs, and different on AMDs.
5016	*/
5017	case CPUMCPUIDFEATURE_SPEC_CTRL:
5018	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
5019	{
5020	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
5021	if ( !pLeaf
5022	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
5023	{
5024	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
5025	return;
5026	}
5027
5028	/* The feature can be enabled. Let's see what we can actually do. */
5029	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
5030
5031	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
5032	if (pVM->cpum.s.HostFeatures.fIbrs)
5033	{
5034	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
5035	pVM->cpum.s.GuestFeatures.fIbrs = 1;
5036	if (pVM->cpum.s.HostFeatures.fStibp)
5037	{
5038	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
5039	pVM->cpum.s.GuestFeatures.fStibp = 1;
5040	}
5041
5042	/* Make sure we have the speculation control MSR... */
5043	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
5044	if (!pMsrRange)
5045	{
5046	static CPUMMSRRANGE const s_SpecCtrl =
5047	{
5048	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
5049	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
5050	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
5051	/.szName = / "IA32_SPEC_CTRL"
5052	};
5053	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
5054	AssertLogRelRC(rc);
5055	}
5056
5057	/* ... and the predictor command MSR. */
5058	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
5059	if (!pMsrRange)
5060	{
5061	/** @todo incorrect fWrGpMask. */
5062	static CPUMMSRRANGE const s_SpecCtrl =
5063	{
5064	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
5065	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
5066	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
5067	/.szName = / "IA32_PRED_CMD"
5068	};
5069	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
5070	AssertLogRelRC(rc);
5071	}
5072
5073	}
5074
5075	if (pVM->cpum.s.HostFeatures.fArchCap)
5076	{
5077	/* Install the architectural capabilities MSR. */
5078	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
5079	if (!pMsrRange)
5080	{
5081	static CPUMMSRRANGE const s_ArchCaps =
5082	{
5083	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
5084	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
5085	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
5086	/.szName = / "IA32_ARCH_CAPABILITIES"
5087	};
5088	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
5089	AssertLogRelRC(rc);
5090	}
5091
5092	/* Advertise IBRS_ALL if present at this point... */
5093	if (pVM->cpum.s.HostFeatures.fArchCap & MSR_IA32_ARCH_CAP_F_IBRS_ALL)
5094	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps \|= MSR_IA32_ARCH_CAP_F_IBRS_ALL);
5095	}
5096
5097	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
5098	}
5099	else if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
5100	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
5101	{
5102	/* The precise details of AMD's implementation are not yet clear. */
5103	}
5104	break;
5105
5106	default:
5107	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5108	break;
5109	}
5110
5111	/** @todo can probably kill this as this API is now init time only... */
5112	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5113	{
5114	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5115	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5116	}
5117	}
5118
5119
5120	/**
5121	* Queries a CPUID feature bit.
5122	*
5123	* @returns boolean for feature presence
5124	* @param pVM The cross context VM structure.
5125	* @param enmFeature The feature to query.
5126	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
5127	*/
5128	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
5129	{
5130	switch (enmFeature)
5131	{
5132	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
5133	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
5134	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
5135	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
5136	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
5137	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
5138	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
5139	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
5140	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
5141	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
5142	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
5143	case CPUMCPUIDFEATURE_INVALID:
5144	case CPUMCPUIDFEATURE_32BIT_HACK:
5145	break;
5146	}
5147	AssertFailed();
5148	return false;
5149	}
5150
5151
5152	/**
5153	* Clears a CPUID feature bit.
5154	*
5155	* @param pVM The cross context VM structure.
5156	* @param enmFeature The feature to clear.
5157	*
5158	* @deprecated Probably better to default the feature to disabled and only allow
5159	* setting (enabling) it during construction.
5160	*/
5161	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
5162	{
5163	PCPUMCPUIDLEAF pLeaf;
5164	switch (enmFeature)
5165	{
5166	case CPUMCPUIDFEATURE_APIC:
5167	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
5168	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5169	if (pLeaf)
5170	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
5171
5172	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5173	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
5174	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
5175
5176	pVM->cpum.s.GuestFeatures.fApic = 0;
5177	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
5178	break;
5179
5180	case CPUMCPUIDFEATURE_X2APIC:
5181	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
5182	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5183	if (pLeaf)
5184	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
5185	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
5186	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
5187	break;
5188
5189	case CPUMCPUIDFEATURE_PAE:
5190	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5191	if (pLeaf)
5192	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
5193
5194	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5195	if ( pLeaf
5196	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
5197	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
5198	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
5199
5200	pVM->cpum.s.GuestFeatures.fPae = 0;
5201	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
5202	break;
5203
5204	case CPUMCPUIDFEATURE_LONG_MODE:
5205	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5206	if (pLeaf)
5207	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
5208	pVM->cpum.s.GuestFeatures.fLongMode = 0;
5209	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = 32;
5210	if (pVM->cpum.s.GuestFeatures.fVmx)
5211	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5212	{
5213	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5214	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic \|= VMX_BASIC_PHYSADDR_WIDTH_32BIT;
5215	}
5216	break;
5217
5218	case CPUMCPUIDFEATURE_LAHF:
5219	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5220	if (pLeaf)
5221	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
5222	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
5223	break;
5224
5225	case CPUMCPUIDFEATURE_RDTSCP:
5226	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5227	if (pLeaf)
5228	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
5229	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
5230	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
5231	break;
5232
5233	case CPUMCPUIDFEATURE_HVP:
5234	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5235	if (pLeaf)
5236	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
5237	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
5238	break;
5239
5240	case CPUMCPUIDFEATURE_SPEC_CTRL:
5241	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
5242	if (pLeaf)
5243	pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP);
5244	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL);
5245	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
5246	break;
5247
5248	default:
5249	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5250	break;
5251	}
5252
5253	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5254	{
5255	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5256	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5257	}
5258	}
5259
5260
5261
5262	/*
5263	*
5264	*
5265	* Saved state related code.
5266	* Saved state related code.
5267	* Saved state related code.
5268	*
5269	*
5270	*/
5271
5272	/**
5273	* Called both in pass 0 and the final pass.
5274	*
5275	* @param pVM The cross context VM structure.
5276	* @param pSSM The saved state handle.
5277	*/
5278	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
5279	{
5280	/*
5281	* Save all the CPU ID leaves.
5282	*/
5283	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
5284	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5285	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
5286	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5287
5288	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5289
5290	/*
5291	* Save a good portion of the raw CPU IDs as well as they may come in
5292	* handy when validating features for raw mode.
5293	*/
5294	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5295	CPUMCPUID aRawStd[16];
5296	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
5297	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5298	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
5299	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
5300
5301	CPUMCPUID aRawExt[32];
5302	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
5303	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5304	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
5305	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
5306
5307	#else
5308	/* Two zero counts on non-x86 hosts. */
5309	SSMR3PutU32(pSSM, 0);
5310	SSMR3PutU32(pSSM, 0);
5311	#endif
5312	}
5313
5314
5315	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5316	{
5317	uint32_t cCpuIds;
5318	int rc = SSMR3GetU32(pSSM, &cCpuIds);
5319	if (RT_SUCCESS(rc))
5320	{
5321	if (cCpuIds < 64)
5322	{
5323	for (uint32_t i = 0; i < cCpuIds; i++)
5324	{
5325	CPUMCPUID CpuId;
5326	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
5327	if (RT_FAILURE(rc))
5328	break;
5329
5330	CPUMCPUIDLEAF NewLeaf;
5331	NewLeaf.uLeaf = uBase + i;
5332	NewLeaf.uSubLeaf = 0;
5333	NewLeaf.fSubLeafMask = 0;
5334	NewLeaf.uEax = CpuId.uEax;
5335	NewLeaf.uEbx = CpuId.uEbx;
5336	NewLeaf.uEcx = CpuId.uEcx;
5337	NewLeaf.uEdx = CpuId.uEdx;
5338	NewLeaf.fFlags = 0;
5339	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
5340	}
5341	}
5342	else
5343	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5344	}
5345	if (RT_FAILURE(rc))
5346	{
5347	RTMemFree(*ppaLeaves);
5348	*ppaLeaves = NULL;
5349	*pcLeaves = 0;
5350	}
5351	return rc;
5352	}
5353
5354
5355	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5356	{
5357	*ppaLeaves = NULL;
5358	*pcLeaves = 0;
5359
5360	int rc;
5361	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
5362	{
5363	/*
5364	* The new format. Starts by declaring the leave size and count.
5365	*/
5366	uint32_t cbLeaf;
5367	SSMR3GetU32(pSSM, &cbLeaf);
5368	uint32_t cLeaves;
5369	rc = SSMR3GetU32(pSSM, &cLeaves);
5370	if (RT_SUCCESS(rc))
5371	{
5372	if (cbLeaf == sizeof(**ppaLeaves))
5373	{
5374	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
5375	{
5376	/*
5377	* Load the leaves one by one.
5378	*
5379	* The uPrev stuff is a kludge for working around a week worth of bad saved
5380	* states during the CPUID revamp in March 2015. We saved too many leaves
5381	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
5382	* garbage entires at the end of the array when restoring. We also had
5383	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
5384	* this kludge doesn't deal correctly with that, but who cares...
5385	*/
5386	uint32_t uPrev = 0;
5387	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
5388	{
5389	CPUMCPUIDLEAF Leaf;
5390	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
5391	if (RT_SUCCESS(rc))
5392	{
5393	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
5394	\|\| Leaf.uLeaf >= uPrev)
5395	{
5396	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5397	uPrev = Leaf.uLeaf;
5398	}
5399	else
5400	uPrev = UINT32_MAX;
5401	}
5402	}
5403	}
5404	else
5405	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5406	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5407	}
5408	else
5409	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5410	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5411	}
5412	}
5413	else
5414	{
5415	/*
5416	* The old format with its three inflexible arrays.
5417	*/
5418	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5419	if (RT_SUCCESS(rc))
5420	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5421	if (RT_SUCCESS(rc))
5422	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5423	if (RT_SUCCESS(rc))
5424	{
5425	/*
5426	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5427	*/
5428	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5429	if ( pLeaf
5430	&& RTX86IsIntelCpu(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5431	{
5432	CPUMCPUIDLEAF Leaf;
5433	Leaf.uLeaf = 4;
5434	Leaf.fSubLeafMask = UINT32_MAX;
5435	Leaf.uSubLeaf = 0;
5436	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5437	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5438	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5439	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5440	\| UINT32_C(63); /* system coherency line size - 1 */
5441	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5442	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5443	\| (UINT32_C(1) << 5) /* cache level */
5444	\| UINT32_C(1); /* cache type (data) */
5445	Leaf.fFlags = 0;
5446	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5447	if (RT_SUCCESS(rc))
5448	{
5449	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5450	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5451	}
5452	if (RT_SUCCESS(rc))
5453	{
5454	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5455	Leaf.uEcx = 4095; /* sets - 1 */
5456	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5457	Leaf.uEbx \|= UINT32_C(23) << 22;
5458	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5459	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5460	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5461	Leaf.uEax \|= UINT32_C(2) << 5;
5462	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5463	}
5464	}
5465	}
5466	}
5467	return rc;
5468	}
5469
5470
5471	/**
5472	* Loads the CPU ID leaves saved by pass 0, inner worker.
5473	*
5474	* @returns VBox status code.
5475	* @param pVM The cross context VM structure.
5476	* @param pSSM The saved state handle.
5477	* @param uVersion The format version.
5478	* @param paLeaves Guest CPUID leaves loaded from the state.
5479	* @param cLeaves The number of leaves in @a paLeaves.
5480	* @param pMsrs The guest MSRs.
5481	*/
5482	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
5483	{
5484	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5485
5486	/*
5487	* Continue loading the state into stack buffers.
5488	*/
5489	CPUMCPUID GuestDefCpuId;
5490	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5491	AssertRCReturn(rc, rc);
5492
5493	CPUMCPUID aRawStd[16];
5494	uint32_t cRawStd;
5495	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5496	if (cRawStd > RT_ELEMENTS(aRawStd))
5497	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5498	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5499	AssertRCReturn(rc, rc);
5500	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5501	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5502	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5503	#else
5504	RT_ZERO(aRawStd[i]);
5505	#endif
5506
5507	CPUMCPUID aRawExt[32];
5508	uint32_t cRawExt;
5509	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5510	if (cRawExt > RT_ELEMENTS(aRawExt))
5511	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5512	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5513	AssertRCReturn(rc, rc);
5514	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5515	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5516	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5517	#else
5518	RT_ZERO(aRawExt[i]);
5519	#endif
5520
5521	/*
5522	* Get the raw CPU IDs for the current host.
5523	*/
5524	CPUMCPUID aHostRawStd[16];
5525	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5526	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5527	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5528	#else
5529	RT_ZERO(aHostRawStd);
5530	#endif
5531
5532	CPUMCPUID aHostRawExt[32];
5533	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5534	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5535	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5536	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5537	#else
5538	RT_ZERO(aHostRawExt);
5539	#endif
5540
5541	/*
5542	* Get the host and guest overrides so we don't reject the state because
5543	* some feature was enabled thru these interfaces.
5544	* Note! We currently only need the feature leaves, so skip rest.
5545	*/
5546	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5547	CPUMCPUID aHostOverrideStd[2];
5548	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5549	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5550
5551	CPUMCPUID aHostOverrideExt[2];
5552	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5553	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5554
5555	/*
5556	* This can be skipped.
5557	*/
5558	bool fStrictCpuIdChecks;
5559	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5560
5561	/*
5562	* Define a bunch of macros for simplifying the santizing/checking code below.
5563	*/
5564	/* Generic expression + failure message. */
5565	#define CPUID_CHECK_RET(expr, fmt) \
5566	do { \
5567	if (!(expr)) \
5568	{ \
5569	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5570	if (fStrictCpuIdChecks) \
5571	{ \
5572	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5573	RTStrFree(pszMsg); \
5574	return rcCpuid; \
5575	} \
5576	LogRel(("CPUM: %s\n", pszMsg)); \
5577	RTStrFree(pszMsg); \
5578	} \
5579	} while (0)
5580	#define CPUID_CHECK_WRN(expr, fmt) \
5581	do { \
5582	if (!(expr)) \
5583	LogRel(fmt); \
5584	} while (0)
5585
5586	/* For comparing two values and bitch if they differs. */
5587	#define CPUID_CHECK2_RET(what, host, saved) \
5588	do { \
5589	if ((host) != (saved)) \
5590	{ \
5591	if (fStrictCpuIdChecks) \
5592	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5593	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5594	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5595	} \
5596	} while (0)
5597	#define CPUID_CHECK2_WRN(what, host, saved) \
5598	do { \
5599	if ((host) != (saved)) \
5600	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5601	} while (0)
5602
5603	/* For checking raw cpu features (raw mode). */
5604	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5605	do { \
5606	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5607	{ \
5608	if (fStrictCpuIdChecks) \
5609	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5610	N_(#bit " mismatch: host=%d saved=%d"), \
5611	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5612	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5613	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5614	} \
5615	} while (0)
5616	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5617	do { \
5618	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5619	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5620	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5621	} while (0)
5622	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5623
5624	/* For checking guest features. */
5625	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5626	do { \
5627	if ( (aGuestCpuId##set [1].reg & bit) \
5628	&& !(aHostRaw##set [1].reg & bit) \
5629	&& !(aHostOverride##set [1].reg & bit) \
5630	) \
5631	{ \
5632	if (fStrictCpuIdChecks) \
5633	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5634	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5635	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5636	} \
5637	} while (0)
5638	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5639	do { \
5640	if ( (aGuestCpuId##set [1].reg & bit) \
5641	&& !(aHostRaw##set [1].reg & bit) \
5642	&& !(aHostOverride##set [1].reg & bit) \
5643	) \
5644	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5645	} while (0)
5646	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5647	do { \
5648	if ( (aGuestCpuId##set [1].reg & bit) \
5649	&& !(aHostRaw##set [1].reg & bit) \
5650	&& !(aHostOverride##set [1].reg & bit) \
5651	) \
5652	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5653	} while (0)
5654	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5655
5656	/* For checking guest features if AMD guest CPU. */
5657	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5658	do { \
5659	if ( (aGuestCpuId##set [1].reg & bit) \
5660	&& fGuestAmd \
5661	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5662	&& !(aHostOverride##set [1].reg & bit) \
5663	) \
5664	{ \
5665	if (fStrictCpuIdChecks) \
5666	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5667	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5668	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5669	} \
5670	} while (0)
5671	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5672	do { \
5673	if ( (aGuestCpuId##set [1].reg & bit) \
5674	&& fGuestAmd \
5675	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5676	&& !(aHostOverride##set [1].reg & bit) \
5677	) \
5678	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5679	} while (0)
5680	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5681	do { \
5682	if ( (aGuestCpuId##set [1].reg & bit) \
5683	&& fGuestAmd \
5684	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5685	&& !(aHostOverride##set [1].reg & bit) \
5686	) \
5687	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5688	} while (0)
5689	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5690
5691	/* For checking AMD features which have a corresponding bit in the standard
5692	range. (Intel defines very few bits in the extended feature sets.) */
5693	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5694	do { \
5695	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5696	&& !(fHostAmd \
5697	? aHostRawExt[1].reg & (ExtBit) \
5698	: aHostRawStd[1].reg & (StdBit)) \
5699	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5700	) \
5701	{ \
5702	if (fStrictCpuIdChecks) \
5703	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5704	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5705	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5706	} \
5707	} while (0)
5708	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5709	do { \
5710	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5711	&& !(fHostAmd \
5712	? aHostRawExt[1].reg & (ExtBit) \
5713	: aHostRawStd[1].reg & (StdBit)) \
5714	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5715	) \
5716	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5717	} while (0)
5718	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5719	do { \
5720	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5721	&& !(fHostAmd \
5722	? aHostRawExt[1].reg & (ExtBit) \
5723	: aHostRawStd[1].reg & (StdBit)) \
5724	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5725	) \
5726	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5727	} while (0)
5728	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5729
5730
5731	/*
5732	* Verify that we can support the features already exposed to the guest on
5733	* this host.
5734	*
5735	* Most of the features we're emulating requires intercepting instruction
5736	* and doing it the slow way, so there is no need to warn when they aren't
5737	* present in the host CPU. Thus we use IGN instead of EMU on these.
5738	*
5739	* Trailing comments:
5740	* "EMU" - Possible to emulate, could be lots of work and very slow.
5741	* "EMU?" - Can this be emulated?
5742	*/
5743	CPUMCPUID aGuestCpuIdStd[2];
5744	RT_ZERO(aGuestCpuIdStd);
5745	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5746
5747	/* CPUID(1).ecx */
5748	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5749	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5750	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5751	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5752	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5753	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5754	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5755	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5756	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5757	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5758	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5759	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5760	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5761	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5762	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5763	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5764	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5765	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5766	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5767	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5768	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5769	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5770	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5771	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5772	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5773	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5774	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5775	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5776	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5777	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5778	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5779	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5780
5781	/* CPUID(1).edx */
5782	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5783	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5784	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5785	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5786	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5787	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5788	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5789	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5790	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5791	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5792	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5793	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5794	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5795	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5796	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5797	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5798	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5799	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5800	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5801	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5802	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5803	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5804	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5805	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5806	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5807	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5808	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5809	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5810	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5811	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5812	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5813	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5814
5815	/* CPUID(0x80000000). */
5816	CPUMCPUID aGuestCpuIdExt[2];
5817	RT_ZERO(aGuestCpuIdExt);
5818	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5819	{
5820	/** @todo deal with no 0x80000001 on the host. */
5821	bool const fHostAmd = RTX86IsAmdCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx)
5822	\|\| RTX86IsHygonCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5823	bool const fGuestAmd = RTX86IsAmdCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx)
5824	\|\| RTX86IsHygonCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5825
5826	/* CPUID(0x80000001).ecx */
5827	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5828	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5829	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5830	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5831	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5832	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5833	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5834	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5835	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5836	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5837	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5838	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5839	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5840	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5841	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5842	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5843	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5844	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5845	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5846	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5847	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5848	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5849	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5850	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5851	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5852	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5853	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5854	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5855	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5856	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5857	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5858	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5859
5860	/* CPUID(0x80000001).edx */
5861	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5862	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5863	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5864	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5865	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5866	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5867	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5868	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5869	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5870	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5871	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5872	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5873	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5874	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5875	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5876	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5877	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5878	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5879	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5880	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5881	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5882	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5883	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5884	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5885	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5886	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5887	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5888	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5889	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5890	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5891	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5892	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5893	}
5894
5895	/** @todo check leaf 7 */
5896
5897	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5898	* ECX=0: EAX - Valid bits in XCR0[31:0].
5899	* EBX - Maximum state size as per current XCR0 value.
5900	* ECX - Maximum state size for all supported features.
5901	* EDX - Valid bits in XCR0[63:32].
5902	* ECX=1: EAX - Various X-features.
5903	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5904	* ECX - Valid bits in IA32_XSS[31:0].
5905	* EDX - Valid bits in IA32_XSS[63:32].
5906	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5907	* if the bit invalid all four registers are set to zero.
5908	* EAX - The state size for this feature.
5909	* EBX - The state byte offset of this feature.
5910	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5911	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5912	*/
5913	uint64_t fGuestXcr0Mask = 0;
5914	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5915	if ( pCurLeaf
5916	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5917	&& ( pCurLeaf->uEax
5918	\|\| pCurLeaf->uEbx
5919	\|\| pCurLeaf->uEcx
5920	\|\| pCurLeaf->uEdx) )
5921	{
5922	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5923	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5924	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5925	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5926	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5927	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5928	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5929	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5930
5931	/* We don't support any additional features yet. */
5932	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5933	if (pCurLeaf && pCurLeaf->uEax)
5934	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5935	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5936	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5937	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5938	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5939	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5940
5941
5942	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5943	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5944	{
5945	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5946	if (pCurLeaf)
5947	{
5948	/* If advertised, the state component offset and size must match the one used by host. */
5949	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5950	{
5951	CPUMCPUID RawHost;
5952	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5953	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5954	if ( RawHost.uEbx != pCurLeaf->uEbx
5955	\|\| RawHost.uEax != pCurLeaf->uEax)
5956	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5957	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5958	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5959	}
5960	}
5961	}
5962	#endif
5963	}
5964	/* Clear leaf 0xd just in case we're loading an old state... */
5965	else if (pCurLeaf)
5966	{
5967	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5968	{
5969	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5970	if (pCurLeaf)
5971	{
5972	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5973	\|\| ( pCurLeaf->uEax == 0
5974	&& pCurLeaf->uEbx == 0
5975	&& pCurLeaf->uEcx == 0
5976	&& pCurLeaf->uEdx == 0),
5977	("uVersion=%#x; %#x %#x %#x %#x\n",
5978	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5979	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5980	}
5981	}
5982	}
5983
5984	/* Update the fXStateGuestMask value for the VM. */
5985	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5986	{
5987	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5988	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5989	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5990	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5991	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5992	}
5993
5994	#undef CPUID_CHECK_RET
5995	#undef CPUID_CHECK_WRN
5996	#undef CPUID_CHECK2_RET
5997	#undef CPUID_CHECK2_WRN
5998	#undef CPUID_RAW_FEATURE_RET
5999	#undef CPUID_RAW_FEATURE_WRN
6000	#undef CPUID_RAW_FEATURE_IGN
6001	#undef CPUID_GST_FEATURE_RET
6002	#undef CPUID_GST_FEATURE_WRN
6003	#undef CPUID_GST_FEATURE_EMU
6004	#undef CPUID_GST_FEATURE_IGN
6005	#undef CPUID_GST_FEATURE2_RET
6006	#undef CPUID_GST_FEATURE2_WRN
6007	#undef CPUID_GST_FEATURE2_EMU
6008	#undef CPUID_GST_FEATURE2_IGN
6009	#undef CPUID_GST_AMD_FEATURE_RET
6010	#undef CPUID_GST_AMD_FEATURE_WRN
6011	#undef CPUID_GST_AMD_FEATURE_EMU
6012	#undef CPUID_GST_AMD_FEATURE_IGN
6013
6014	/*
6015	* We're good, commit the CPU ID leaves.
6016	*/
6017	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
6018	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
6019	AssertLogRelRCReturn(rc, rc);
6020
6021	return VINF_SUCCESS;
6022	}
6023
6024
6025	/**
6026	* Loads the CPU ID leaves saved by pass 0.
6027	*
6028	* @returns VBox status code.
6029	* @param pVM The cross context VM structure.
6030	* @param pSSM The saved state handle.
6031	* @param uVersion The format version.
6032	* @param pMsrs The guest MSRs.
6033	*/
6034	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
6035	{
6036	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
6037
6038	/*
6039	* Load the CPUID leaves array first and call worker to do the rest, just so
6040	* we can free the memory when we need to without ending up in column 1000.
6041	*/
6042	PCPUMCPUIDLEAF paLeaves;
6043	uint32_t cLeaves;
6044	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
6045	AssertRC(rc);
6046	if (RT_SUCCESS(rc))
6047	{
6048	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
6049	RTMemFree(paLeaves);
6050	}
6051	return rc;
6052	}
6053
6054
6055
6056	/**
6057	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
6058	*
6059	* @returns VBox status code.
6060	* @param pVM The cross context VM structure.
6061	* @param pSSM The saved state handle.
6062	* @param uVersion The format version.
6063	*/
6064	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
6065	{
6066	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
6067
6068	/*
6069	* Restore the CPUID leaves.
6070	*
6071	* Note that we support restoring less than the current amount of standard
6072	* leaves because we've been allowed more is newer version of VBox.
6073	*/
6074	uint32_t cElements;
6075	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6076	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
6077	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6078	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
6079
6080	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6081	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
6082	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6083	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
6084
6085	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6086	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
6087	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6088	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
6089
6090	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
6091
6092	/*
6093	* Check that the basic cpuid id information is unchanged.
6094	*/
6095	/** @todo we should check the 64 bits capabilities too! */
6096	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
6097	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6098	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
6099	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
6100	#endif
6101	uint32_t au32CpuIdSaved[8];
6102	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
6103	if (RT_SUCCESS(rc))
6104	{
6105	/* Ignore CPU stepping. */
6106	au32CpuId[4] &= 0xfffffff0;
6107	au32CpuIdSaved[4] &= 0xfffffff0;
6108
6109	/* Ignore APIC ID (AMD specs). */
6110	au32CpuId[5] &= ~0xff000000;
6111	au32CpuIdSaved[5] &= ~0xff000000;
6112
6113	/* Ignore the number of Logical CPUs (AMD specs). */
6114	au32CpuId[5] &= ~0x00ff0000;
6115	au32CpuIdSaved[5] &= ~0x00ff0000;
6116
6117	/* Ignore some advanced capability bits, that we don't expose to the guest. */
6118	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6119	\| X86_CPUID_FEATURE_ECX_VMX
6120	\| X86_CPUID_FEATURE_ECX_SMX
6121	\| X86_CPUID_FEATURE_ECX_EST
6122	\| X86_CPUID_FEATURE_ECX_TM2
6123	\| X86_CPUID_FEATURE_ECX_CNTXID
6124	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6125	\| X86_CPUID_FEATURE_ECX_PDCM
6126	\| X86_CPUID_FEATURE_ECX_DCA
6127	\| X86_CPUID_FEATURE_ECX_X2APIC
6128	);
6129	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6130	\| X86_CPUID_FEATURE_ECX_VMX
6131	\| X86_CPUID_FEATURE_ECX_SMX
6132	\| X86_CPUID_FEATURE_ECX_EST
6133	\| X86_CPUID_FEATURE_ECX_TM2
6134	\| X86_CPUID_FEATURE_ECX_CNTXID
6135	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6136	\| X86_CPUID_FEATURE_ECX_PDCM
6137	\| X86_CPUID_FEATURE_ECX_DCA
6138	\| X86_CPUID_FEATURE_ECX_X2APIC
6139	);
6140
6141	/* Make sure we don't forget to update the masks when enabling
6142	* features in the future.
6143	*/
6144	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
6145	( X86_CPUID_FEATURE_ECX_DTES64
6146	\| X86_CPUID_FEATURE_ECX_VMX
6147	\| X86_CPUID_FEATURE_ECX_SMX
6148	\| X86_CPUID_FEATURE_ECX_EST
6149	\| X86_CPUID_FEATURE_ECX_TM2
6150	\| X86_CPUID_FEATURE_ECX_CNTXID
6151	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6152	\| X86_CPUID_FEATURE_ECX_PDCM
6153	\| X86_CPUID_FEATURE_ECX_DCA
6154	\| X86_CPUID_FEATURE_ECX_X2APIC
6155	)));
6156	/* do the compare */
6157	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
6158	{
6159	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
6160	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
6161	"Saved=%.*Rhxs\n"
6162	"Real =%.*Rhxs\n",
6163	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6164	sizeof(au32CpuId), au32CpuId));
6165	else
6166	{
6167	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
6168	"Saved=%.*Rhxs\n"
6169	"Real =%.*Rhxs\n",
6170	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6171	sizeof(au32CpuId), au32CpuId));
6172	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
6173	}
6174	}
6175	}
6176
6177	return rc;
6178	}
6179
6180
6181
6182	/*
6183	*
6184	*
6185	* CPUID Info Handler.
6186	* CPUID Info Handler.
6187	* CPUID Info Handler.
6188	*
6189	*
6190	*/
6191
6192
6193
6194	/**
6195	* Get L1 cache / TLS associativity.
6196	*/
6197	static const char getCacheAss(unsigned u, char pszBuf)
6198	{
6199	if (u == 0)
6200	return "res0 ";
6201	if (u == 1)
6202	return "direct";
6203	if (u == 255)
6204	return "fully";
6205	if (u >= 256)
6206	return "???";
6207
6208	RTStrPrintf(pszBuf, 16, "%d way", u);
6209	return pszBuf;
6210	}
6211
6212
6213	/**
6214	* Get L2 cache associativity.
6215	*/
6216	const char *getL2CacheAss(unsigned u)
6217	{
6218	switch (u)
6219	{
6220	case 0: return "off ";
6221	case 1: return "direct";
6222	case 2: return "2 way ";
6223	case 3: return "res3 ";
6224	case 4: return "4 way ";
6225	case 5: return "res5 ";
6226	case 6: return "8 way ";
6227	case 7: return "res7 ";
6228	case 8: return "16 way";
6229	case 9: return "res9 ";
6230	case 10: return "res10 ";
6231	case 11: return "res11 ";
6232	case 12: return "res12 ";
6233	case 13: return "res13 ";
6234	case 14: return "res14 ";
6235	case 15: return "fully ";
6236	default: return "????";
6237	}
6238	}
6239
6240
6241	/** CPUID(1).EDX field descriptions. */
6242	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6243	{
6244	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6245	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6246	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6247	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6248	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6249	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6250	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6251	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6252	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6253	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6254	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6255	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6256	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6257	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6258	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6259	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6260	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6261	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6262	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6263	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6264	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6265	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6266	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6267	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6268	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6269	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6270	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6271	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6272	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6273	DBGFREGSUBFIELD_TERMINATOR()
6274	};
6275
6276	/** CPUID(1).ECX field descriptions. */
6277	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6278	{
6279	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6280	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6281	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6282	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6283	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6284	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6285	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6286	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6287	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6288	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6289	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6290	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6291	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6292	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6293	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6294	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6295	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6296	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6297	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6298	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6299	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6300	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6301	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6302	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6303	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6304	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6305	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6306	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6307	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6308	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6309	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6310	DBGFREGSUBFIELD_TERMINATOR()
6311	};
6312
6313	/** CPUID(7,0).EBX field descriptions. */
6314	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6315	{
6316	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6317	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6318	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6319	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6320	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6321	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6322	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6323	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6324	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6325	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6326	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6327	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6328	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6329	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6330	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6331	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6332	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6333	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6334	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6335	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6336	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6337	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6338	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6339	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6340	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6341	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6342	DBGFREGSUBFIELD_TERMINATOR()
6343	};
6344
6345	/** CPUID(7,0).ECX field descriptions. */
6346	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6347	{
6348	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6349	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6350	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6351	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6352	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6353	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6354	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6355	DBGFREGSUBFIELD_TERMINATOR()
6356	};
6357
6358	/** CPUID(7,0).EDX field descriptions. */
6359	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6360	{
6361	DBGFREGSUBFIELD_RO("MD_CLEAR\0" "Supports MDS related buffer clearing", 10, 1, 0),
6362	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6363	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6364	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
6365	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6366	DBGFREGSUBFIELD_RO("CORECAP\0" "Supports IA32_CORE_CAP", 30, 1, 0),
6367	DBGFREGSUBFIELD_RO("SSBD\0" "Supports IA32_SPEC_CTRL.SSBD", 31, 1, 0),
6368	DBGFREGSUBFIELD_TERMINATOR()
6369	};
6370
6371
6372	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6373	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6374	{
6375	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6376	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6377	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6378	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6379	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6380	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6381	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6382	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6383	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6384	DBGFREGSUBFIELD_TERMINATOR()
6385	};
6386
6387	/** CPUID(13,1).EAX field descriptions. */
6388	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6389	{
6390	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6391	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6392	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6393	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6394	DBGFREGSUBFIELD_TERMINATOR()
6395	};
6396
6397
6398	/** CPUID(0x80000001,0).EDX field descriptions. */
6399	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6400	{
6401	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6402	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6403	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6404	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6405	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6406	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6407	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6408	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6409	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6410	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6411	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6412	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6413	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6414	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6415	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6416	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6417	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6418	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6419	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6420	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6421	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6422	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6423	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6424	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6425	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6426	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6427	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6428	DBGFREGSUBFIELD_TERMINATOR()
6429	};
6430
6431	/** CPUID(0x80000001,0).ECX field descriptions. */
6432	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6433	{
6434	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6435	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6436	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6437	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6438	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6439	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6440	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6441	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6442	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6443	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6444	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6445	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6446	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6447	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6448	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6449	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6450	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6451	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6452	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6453	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6454	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6455	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6456	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6457	DBGFREGSUBFIELD_RO("PCX_L2I\0" "L2I/L3 Performance Counter Extensions", 28, 1, 0),
6458	DBGFREGSUBFIELD_RO("MWAITX\0" "MWAITX and MONITORX instructions", 29, 1, 0),
6459	DBGFREGSUBFIELD_TERMINATOR()
6460	};
6461
6462	/** CPUID(0x8000000a,0).EDX field descriptions. */
6463	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
6464	{
6465	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
6466	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
6467	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
6468	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
6469	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
6470	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
6471	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
6472	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
6473	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
6474	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
6475	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
6476	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
6477	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
6478	DBGFREGSUBFIELD_RO("GMET\0" "Guest Mode Execute Trap Extension", 17, 1, 0),
6479	DBGFREGSUBFIELD_TERMINATOR()
6480	};
6481
6482
6483	/** CPUID(0x80000007,0).EDX field descriptions. */
6484	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6485	{
6486	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6487	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6488	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6489	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6490	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6491	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6492	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6493	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6494	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6495	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6496	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6497	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6498	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6499	DBGFREGSUBFIELD_TERMINATOR()
6500	};
6501
6502	/** CPUID(0x80000008,0).EBX field descriptions. */
6503	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6504	{
6505	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6506	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6507	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6508	DBGFREGSUBFIELD_RO("RDPRU\0" "RDPRU instruction", 4, 1, 0),
6509	DBGFREGSUBFIELD_RO("MCOMMIT\0" "MCOMMIT instruction", 8, 1, 0),
6510	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6511	DBGFREGSUBFIELD_TERMINATOR()
6512	};
6513
6514
6515	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6516	const char *pszLeadIn, uint32_t cchWidth)
6517	{
6518	if (pszLeadIn)
6519	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6520
6521	for (uint32_t iBit = 0; iBit < 32; iBit++)
6522	if (RT_BIT_32(iBit) & uVal)
6523	{
6524	while ( pDesc->pszName != NULL
6525	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6526	pDesc++;
6527	if ( pDesc->pszName != NULL
6528	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6529	{
6530	if (pDesc->cBits == 1)
6531	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6532	else
6533	{
6534	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6535	if (pDesc->cBits < 32)
6536	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6537	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6538	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6539	}
6540	}
6541	else
6542	pHlp->pfnPrintf(pHlp, " %u", iBit);
6543	}
6544	if (pszLeadIn)
6545	pHlp->pfnPrintf(pHlp, "\n");
6546	}
6547
6548
6549	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6550	const char *pszLeadIn, uint32_t cchWidth)
6551	{
6552	if (pszLeadIn)
6553	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6554
6555	for (uint32_t iBit = 0; iBit < 64; iBit++)
6556	if (RT_BIT_64(iBit) & uVal)
6557	{
6558	while ( pDesc->pszName != NULL
6559	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6560	pDesc++;
6561	if ( pDesc->pszName != NULL
6562	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6563	{
6564	if (pDesc->cBits == 1)
6565	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6566	else
6567	{
6568	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6569	if (pDesc->cBits < 64)
6570	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6571	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6572	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6573	}
6574	}
6575	else
6576	pHlp->pfnPrintf(pHlp, " %u", iBit);
6577	}
6578	if (pszLeadIn)
6579	pHlp->pfnPrintf(pHlp, "\n");
6580	}
6581
6582
6583	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6584	const char *pszLeadIn, uint32_t cchWidth)
6585	{
6586	if (!uVal)
6587	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6588	else
6589	{
6590	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6591	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6592	pHlp->pfnPrintf(pHlp, " )\n");
6593	}
6594	}
6595
6596
6597	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6598	uint32_t cchWidth)
6599	{
6600	uint32_t uCombined = uVal1 \| uVal2;
6601	for (uint32_t iBit = 0; iBit < 32; iBit++)
6602	if ( (RT_BIT_32(iBit) & uCombined)
6603	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6604	{
6605	while ( pDesc->pszName != NULL
6606	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6607	pDesc++;
6608
6609	if ( pDesc->pszName != NULL
6610	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6611	{
6612	size_t cchMnemonic = strlen(pDesc->pszName);
6613	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6614	size_t cchDesc = strlen(pszDesc);
6615	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6616	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6617	if (pDesc->cBits < 32)
6618	{
6619	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6620	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6621	}
6622
6623	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6624	pDesc->pszName, pszDesc,
6625	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6626	uFieldValue1, uFieldValue2);
6627
6628	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6629	pDesc++;
6630	}
6631	else
6632	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6633	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6634	}
6635	}
6636
6637
6638	/**
6639	* Produces a detailed summary of standard leaf 0x00000001.
6640	*
6641	* @param pHlp The info helper functions.
6642	* @param pCurLeaf The 0x00000001 leaf.
6643	* @param fVerbose Whether to be very verbose or not.
6644	* @param fIntel Set if intel CPU.
6645	*/
6646	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6647	{
6648	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6649	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6650	uint32_t uEAX = pCurLeaf->uEax;
6651	uint32_t uEBX = pCurLeaf->uEbx;
6652
6653	pHlp->pfnPrintf(pHlp,
6654	"%36s %2d \tExtended: %d \tEffective: %d\n"
6655	"%36s %2d \tExtended: %d \tEffective: %d\n"
6656	"%36s %d\n"
6657	"%36s %d (%s)\n"
6658	"%36s %#04x\n"
6659	"%36s %d\n"
6660	"%36s %d\n"
6661	"%36s %#04x\n"
6662	,
6663	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
6664	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
6665	"Stepping:", RTX86GetCpuStepping(uEAX),
6666	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6667	"APIC ID:", (uEBX >> 24) & 0xff,
6668	"Logical CPUs:",(uEBX >> 16) & 0xff,
6669	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6670	"Brand ID:", (uEBX >> 0) & 0xff);
6671	if (fVerbose)
6672	{
6673	CPUMCPUID Host = {0};
6674	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6675	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6676	#endif
6677	pHlp->pfnPrintf(pHlp, "Features\n");
6678	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6679	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6680	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6681	}
6682	else
6683	{
6684	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6685	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6686	}
6687	}
6688
6689
6690	/**
6691	* Produces a detailed summary of standard leaf 0x00000007.
6692	*
6693	* @param pHlp The info helper functions.
6694	* @param paLeaves The CPUID leaves array.
6695	* @param cLeaves The number of leaves in the array.
6696	* @param pCurLeaf The first 0x00000007 leaf.
6697	* @param fVerbose Whether to be very verbose or not.
6698	*/
6699	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6700	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6701	{
6702	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6703	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6704	for (;;)
6705	{
6706	CPUMCPUID Host = {0};
6707	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6708	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6709	#endif
6710
6711	switch (pCurLeaf->uSubLeaf)
6712	{
6713	case 0:
6714	if (fVerbose)
6715	{
6716	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6717	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6718	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6719	if (pCurLeaf->uEdx \|\| Host.uEdx)
6720	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6721	}
6722	else
6723	{
6724	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6725	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6726	if (pCurLeaf->uEdx)
6727	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6728	}
6729	break;
6730
6731	default:
6732	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6733	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6734	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6735	break;
6736
6737	}
6738
6739	/* advance. */
6740	pCurLeaf++;
6741	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6742	\|\| pCurLeaf->uLeaf != 0x7)
6743	break;
6744	}
6745	}
6746
6747
6748	/**
6749	* Produces a detailed summary of standard leaf 0x0000000d.
6750	*
6751	* @param pHlp The info helper functions.
6752	* @param paLeaves The CPUID leaves array.
6753	* @param cLeaves The number of leaves in the array.
6754	* @param pCurLeaf The first 0x00000007 leaf.
6755	* @param fVerbose Whether to be very verbose or not.
6756	*/
6757	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6758	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6759	{
6760	RT_NOREF_PV(fVerbose);
6761	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6762	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6763	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6764	{
6765	CPUMCPUID Host = {0};
6766	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6767	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6768	#endif
6769
6770	switch (uSubLeaf)
6771	{
6772	case 0:
6773	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6774	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6775	pCurLeaf->uEbx, pCurLeaf->uEcx);
6776	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6777
6778	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6779	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6780	"Valid XCR0 bits, guest:", 42);
6781	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6782	"Valid XCR0 bits, host:", 42);
6783	break;
6784
6785	case 1:
6786	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6787	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6788	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6789
6790	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6791	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6792	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6793
6794	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6795	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6796	" Valid IA32_XSS bits, guest:", 42);
6797	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6798	" Valid IA32_XSS bits, host:", 42);
6799	break;
6800
6801	default:
6802	if ( pCurLeaf
6803	&& pCurLeaf->uSubLeaf == uSubLeaf
6804	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6805	{
6806	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6807	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6808	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6809	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6810	if (pCurLeaf->uEdx)
6811	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6812	pHlp->pfnPrintf(pHlp, " --");
6813	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6814	pHlp->pfnPrintf(pHlp, "\n");
6815	}
6816	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6817	{
6818	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6819	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6820	if (Host.uEcx & ~RT_BIT_32(0))
6821	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6822	if (Host.uEdx)
6823	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6824	pHlp->pfnPrintf(pHlp, " --");
6825	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6826	pHlp->pfnPrintf(pHlp, "\n");
6827	}
6828	break;
6829
6830	}
6831
6832	/* advance. */
6833	if (pCurLeaf)
6834	{
6835	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6836	&& pCurLeaf->uSubLeaf <= uSubLeaf
6837	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6838	pCurLeaf++;
6839	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6840	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6841	pCurLeaf = NULL;
6842	}
6843	}
6844	}
6845
6846
6847	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6848	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6849	{
6850	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6851	&& pCurLeaf->uLeaf <= uUpToLeaf)
6852	{
6853	pHlp->pfnPrintf(pHlp,
6854	" %s\n"
6855	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6856	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6857	&& pCurLeaf->uLeaf <= uUpToLeaf)
6858	{
6859	CPUMCPUID Host = {0};
6860	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6861	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6862	#endif
6863	pHlp->pfnPrintf(pHlp,
6864	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6865	"Hst: %08x %08x %08x %08x\n",
6866	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6867	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6868	pCurLeaf++;
6869	}
6870	}
6871
6872	return pCurLeaf;
6873	}
6874
6875
6876	/**
6877	* Display the guest CpuId leaves.
6878	*
6879	* @param pVM The cross context VM structure.
6880	* @param pHlp The info helper functions.
6881	* @param pszArgs "terse", "default" or "verbose".
6882	*/
6883	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6884	{
6885	/*
6886	* Parse the argument.
6887	*/
6888	unsigned iVerbosity = 1;
6889	if (pszArgs)
6890	{
6891	pszArgs = RTStrStripL(pszArgs);
6892	if (!strcmp(pszArgs, "terse"))
6893	iVerbosity--;
6894	else if (!strcmp(pszArgs, "verbose"))
6895	iVerbosity++;
6896	}
6897
6898	uint32_t uLeaf;
6899	CPUMCPUID Host = {0};
6900	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6901	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6902	PCCPUMCPUIDLEAF pCurLeaf;
6903	PCCPUMCPUIDLEAF pNextLeaf;
6904	bool const fIntel = RTX86IsIntelCpu(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6905	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6906	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6907
6908	/*
6909	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6910	*/
6911	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6912	uint32_t cHstMax = ASMCpuId_EAX(0);
6913	#else
6914	uint32_t cHstMax = 0;
6915	#endif
6916	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6917	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6918	pHlp->pfnPrintf(pHlp,
6919	" Raw Standard CPUID Leaves\n"
6920	" Leaf/sub-leaf eax ebx ecx edx\n");
6921	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6922	{
6923	uint32_t cMaxSubLeaves = 1;
6924	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6925	cMaxSubLeaves = 16;
6926	else if (uLeaf == 0xd)
6927	cMaxSubLeaves = 128;
6928
6929	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6930	{
6931	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6932	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6933	#endif
6934	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6935	&& pCurLeaf->uLeaf == uLeaf
6936	&& pCurLeaf->uSubLeaf == uSubLeaf)
6937	{
6938	pHlp->pfnPrintf(pHlp,
6939	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6940	"Hst: %08x %08x %08x %08x\n",
6941	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6942	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6943	pCurLeaf++;
6944	}
6945	else if ( uLeaf != 0xd
6946	\|\| uSubLeaf <= 1
6947	\|\| Host.uEbx != 0 )
6948	pHlp->pfnPrintf(pHlp,
6949	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6950	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6951
6952	/* Done? */
6953	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6954	\|\| pCurLeaf->uLeaf != uLeaf)
6955	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6956	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6957	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6958	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6959	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6960	)
6961	)
6962	break;
6963	}
6964	}
6965	pNextLeaf = pCurLeaf;
6966
6967	/*
6968	* If verbose, decode it.
6969	*/
6970	if (iVerbosity && paLeaves[0].uLeaf == 0)
6971	pHlp->pfnPrintf(pHlp,
6972	"%36s %.04s%.04s%.04s\n"
6973	"%36s 0x00000000-%#010x\n"
6974	,
6975	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6976	"Supports:", paLeaves[0].uEax);
6977
6978	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6979	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6980
6981	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6982	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6983
6984	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6985	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6986
6987	pCurLeaf = pNextLeaf;
6988
6989	/*
6990	* Hypervisor leaves.
6991	*
6992	* Unlike most of the other leaves reported, the guest hypervisor leaves
6993	* aren't a subset of the host CPUID bits.
6994	*/
6995	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6996
6997	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6998	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6999	#endif
7000	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
7001	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
7002	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
7003	cMax = RT_MAX(cHstMax, cGstMax);
7004	if (cMax >= UINT32_C(0x40000000))
7005	{
7006	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
7007
7008	/** @todo dump these in more detail. */
7009
7010	pCurLeaf = pNextLeaf;
7011	}
7012
7013
7014	/*
7015	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
7016	* Implemented after AMD specs.
7017	*/
7018	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
7019
7020	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7021	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7022	#endif
7023	cHstMax = RTX86IsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
7024	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
7025	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
7026	cMax = RT_MAX(cHstMax, cGstMax);
7027	if (cMax >= UINT32_C(0x80000000))
7028	{
7029
7030	pHlp->pfnPrintf(pHlp,
7031	" Raw Extended CPUID Leaves\n"
7032	" Leaf/sub-leaf eax ebx ecx edx\n");
7033	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
7034	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
7035	{
7036	uint32_t cMaxSubLeaves = 1;
7037	if (uLeaf == UINT32_C(0x8000001d))
7038	cMaxSubLeaves = 16;
7039
7040	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
7041	{
7042	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7043	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7044	#endif
7045	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
7046	&& pCurLeaf->uLeaf == uLeaf
7047	&& pCurLeaf->uSubLeaf == uSubLeaf)
7048	{
7049	pHlp->pfnPrintf(pHlp,
7050	"Gst: %08x/%04x %08x %08x %08x %08x\n"
7051	"Hst: %08x %08x %08x %08x\n",
7052	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
7053	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
7054	pCurLeaf++;
7055	}
7056	else if ( uLeaf != 0xd
7057	\|\| uSubLeaf <= 1
7058	\|\| Host.uEbx != 0 )
7059	pHlp->pfnPrintf(pHlp,
7060	"Hst: %08x/%04x %08x %08x %08x %08x\n",
7061	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
7062
7063	/* Done? */
7064	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
7065	\|\| pCurLeaf->uLeaf != uLeaf)
7066	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
7067	break;
7068	}
7069	}
7070	pNextLeaf = pCurLeaf;
7071
7072	/*
7073	* Understandable output
7074	*/
7075	if (iVerbosity)
7076	pHlp->pfnPrintf(pHlp,
7077	"Ext Name: %.4s%.4s%.4s\n"
7078	"Ext Supports: 0x80000000-%#010x\n",
7079	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
7080
7081	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
7082	if (iVerbosity && pCurLeaf)
7083	{
7084	uint32_t uEAX = pCurLeaf->uEax;
7085	pHlp->pfnPrintf(pHlp,
7086	"Family: %d \tExtended: %d \tEffective: %d\n"
7087	"Model: %d \tExtended: %d \tEffective: %d\n"
7088	"Stepping: %d\n"
7089	"Brand ID: %#05x\n",
7090	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
7091	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
7092	RTX86GetCpuStepping(uEAX),
7093	pCurLeaf->uEbx & 0xfff);
7094
7095	if (iVerbosity == 1)
7096	{
7097	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
7098	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
7099	}
7100	else
7101	{
7102	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7103	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7104	#endif
7105	pHlp->pfnPrintf(pHlp, "Ext Features\n");
7106	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
7107	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
7108	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
7109	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
7110	{
7111	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
7112	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7113	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7114	#endif
7115	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
7116	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
7117	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
7118	}
7119	}
7120	}
7121
7122	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
7123	{
7124	char szString[443+1] = {0};
7125	uint32_t pu32 = (uint32_t )szString;
7126	*pu32++ = pCurLeaf->uEax;
7127	*pu32++ = pCurLeaf->uEbx;
7128	*pu32++ = pCurLeaf->uEcx;
7129	*pu32++ = pCurLeaf->uEdx;
7130	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
7131	if (pCurLeaf)
7132	{
7133	*pu32++ = pCurLeaf->uEax;
7134	*pu32++ = pCurLeaf->uEbx;
7135	*pu32++ = pCurLeaf->uEcx;
7136	*pu32++ = pCurLeaf->uEdx;
7137	}
7138	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
7139	if (pCurLeaf)
7140	{
7141	*pu32++ = pCurLeaf->uEax;
7142	*pu32++ = pCurLeaf->uEbx;
7143	*pu32++ = pCurLeaf->uEcx;
7144	*pu32++ = pCurLeaf->uEdx;
7145	}
7146	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
7147	}
7148
7149	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
7150	{
7151	uint32_t uEAX = pCurLeaf->uEax;
7152	uint32_t uEBX = pCurLeaf->uEbx;
7153	uint32_t uECX = pCurLeaf->uEcx;
7154	uint32_t uEDX = pCurLeaf->uEdx;
7155	char sz1[32];
7156	char sz2[32];
7157
7158	pHlp->pfnPrintf(pHlp,
7159	"TLB 2/4M Instr/Uni: %s %3d entries\n"
7160	"TLB 2/4M Data: %s %3d entries\n",
7161	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
7162	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
7163	pHlp->pfnPrintf(pHlp,
7164	"TLB 4K Instr/Uni: %s %3d entries\n"
7165	"TLB 4K Data: %s %3d entries\n",
7166	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
7167	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
7168	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
7169	"L1 Instr Cache Lines Per Tag: %d\n"
7170	"L1 Instr Cache Associativity: %s\n"
7171	"L1 Instr Cache Size: %d KB\n",
7172	(uEDX >> 0) & 0xff,
7173	(uEDX >> 8) & 0xff,
7174	getCacheAss((uEDX >> 16) & 0xff, sz1),
7175	(uEDX >> 24) & 0xff);
7176	pHlp->pfnPrintf(pHlp,
7177	"L1 Data Cache Line Size: %d bytes\n"
7178	"L1 Data Cache Lines Per Tag: %d\n"
7179	"L1 Data Cache Associativity: %s\n"
7180	"L1 Data Cache Size: %d KB\n",
7181	(uECX >> 0) & 0xff,
7182	(uECX >> 8) & 0xff,
7183	getCacheAss((uECX >> 16) & 0xff, sz1),
7184	(uECX >> 24) & 0xff);
7185	}
7186
7187	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
7188	{
7189	uint32_t uEAX = pCurLeaf->uEax;
7190	uint32_t uEBX = pCurLeaf->uEbx;
7191	uint32_t uEDX = pCurLeaf->uEdx;
7192
7193	pHlp->pfnPrintf(pHlp,
7194	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
7195	"L2 TLB 2/4M Data: %s %4d entries\n",
7196	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
7197	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
7198	pHlp->pfnPrintf(pHlp,
7199	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
7200	"L2 TLB 4K Data: %s %4d entries\n",
7201	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
7202	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
7203	pHlp->pfnPrintf(pHlp,
7204	"L2 Cache Line Size: %d bytes\n"
7205	"L2 Cache Lines Per Tag: %d\n"
7206	"L2 Cache Associativity: %s\n"
7207	"L2 Cache Size: %d KB\n",
7208	(uEDX >> 0) & 0xff,
7209	(uEDX >> 8) & 0xf,
7210	getL2CacheAss((uEDX >> 12) & 0xf),
7211	(uEDX >> 16) & 0xffff);
7212	}
7213
7214	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
7215	{
7216	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7217	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7218	#endif
7219	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
7220	{
7221	if (iVerbosity < 1)
7222	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
7223	else
7224	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
7225	}
7226	}
7227
7228	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
7229	if (pCurLeaf != NULL)
7230	{
7231	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7232	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7233	#endif
7234	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
7235	{
7236	if (iVerbosity < 1)
7237	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
7238	else
7239	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
7240	}
7241
7242	if (iVerbosity)
7243	{
7244	uint32_t uEAX = pCurLeaf->uEax;
7245	uint32_t uECX = pCurLeaf->uEcx;
7246
7247	/** @todo 0x80000008:EAX[23:16] is only defined for AMD. We'll get 0 on Intel. On
7248	* AMD if we get 0, the guest physical address width should be taken from
7249	* 0x80000008:EAX[7:0] instead. Guest Physical address width is relevant
7250	* for guests using nested paging. */
7251	pHlp->pfnPrintf(pHlp,
7252	"Physical Address Width: %d bits\n"
7253	"Virtual Address Width: %d bits\n"
7254	"Guest Physical Address Width: %d bits\n",
7255	(uEAX >> 0) & 0xff,
7256	(uEAX >> 8) & 0xff,
7257	(uEAX >> 16) & 0xff);
7258
7259	/** @todo 0x80000008:ECX is reserved on Intel (we'll get incorrect physical core
7260	* count here). */
7261	pHlp->pfnPrintf(pHlp,
7262	"Physical Core Count: %d\n",
7263	((uECX >> 0) & 0xff) + 1);
7264	}
7265	}
7266
7267	pCurLeaf = pNextLeaf;
7268	}
7269
7270
7271
7272	/*
7273	* Centaur.
7274	*/
7275	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7276
7277	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7278	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7279	#endif
7280	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7281	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7282	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7283	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7284	cMax = RT_MAX(cHstMax, cGstMax);
7285	if (cMax >= UINT32_C(0xc0000000))
7286	{
7287	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7288
7289	/*
7290	* Understandable output
7291	*/
7292	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7293	pHlp->pfnPrintf(pHlp,
7294	"Centaur Supports: 0xc0000000-%#010x\n",
7295	pCurLeaf->uEax);
7296
7297	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7298	{
7299	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7300	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7301	#endif
7302	uint32_t uEdxGst = pCurLeaf->uEdx;
7303	uint32_t uEdxHst = Host.uEdx;
7304
7305	if (iVerbosity == 1)
7306	{
7307	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7308	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7309	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7310	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7311	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7312	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7313	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7314	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7315	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7316	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7317	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7318	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7319	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7320	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7321	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7322	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7323	for (unsigned iBit = 14; iBit < 32; iBit++)
7324	if (uEdxGst & RT_BIT(iBit))
7325	pHlp->pfnPrintf(pHlp, " %d", iBit);
7326	pHlp->pfnPrintf(pHlp, "\n");
7327	}
7328	else
7329	{
7330	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7331	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7332	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7333	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7334	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7335	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7336	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7337	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7338	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7339	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7340	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7341	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7342	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7343	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7344	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7345	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7346	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7347	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7348	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7349	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7350	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7351	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7352	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7353	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7354	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7355	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7356	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7357	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7358	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7359	for (unsigned iBit = 27; iBit < 32; iBit++)
7360	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7361	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7362	pHlp->pfnPrintf(pHlp, "\n");
7363	}
7364	}
7365
7366	pCurLeaf = pNextLeaf;
7367	}
7368
7369	/*
7370	* The remainder.
7371	*/
7372	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7373	}
7374
7375	#endif /* !IN_VBOX_CPU_REPORT */
7376

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 94911

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