CPUMR3CpuId.cpp@ 93609

Last change on this file since 93609 was 93519, checked in by vboxsync, 3 years ago
VMM/CPUM: Quick arm64 build adjustments. bugref:9898
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 344.4 KB

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1	/* $Id: CPUMR3CpuId.cpp 93519 2022-01-31 22:45:35Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vmcc.h>
30	#include <VBox/sup.h>
31
32	#include <VBox/err.h>
33	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
34	# include <iprt/asm-amd64-x86.h>
35	#endif
36	#include <iprt/ctype.h>
37	#include <iprt/mem.h>
38	#include <iprt/string.h>
39	#include <iprt/x86-helpers.h>
40
41
42	/*********************************************************************************************************************************
43	* Defined Constants And Macros *
44	*********************************************************************************************************************************/
45	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
46	#define CPUM_CPUID_MAX_LEAVES 2048
47	/** Max size we accept for the XSAVE area.
48	* @see CPUMCTX::abXSave */
49	#define CPUM_MAX_XSAVE_AREA_SIZE (0x4000 - 0x300)
50	/* Min size we accept for the XSAVE area. */
51	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
52
53
54	/*********************************************************************************************************************************
55	* Global Variables *
56	*********************************************************************************************************************************/
57	/**
58	* The intel pentium family.
59	*/
60	static const CPUMMICROARCH g_aenmIntelFamily06[] =
61	{
62	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
63	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
64	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
65	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
66	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
67	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
68	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
69	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
70	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
71	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
72	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
73	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
74	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
75	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
76	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
77	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
78	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
81	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
82	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
83	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
84	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
85	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
86	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
87	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
88	/* [26(0x1a)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Nehalem-EP */
89	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
90	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
91	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
92	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
93	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
94	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
97	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
98	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
99	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
100	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
101	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
102	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
103	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
104	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
105	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
106	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
107	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
108	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
109	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
110	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
113	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
114	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
115	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
116	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
117	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
118	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
120	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
121	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
122	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
124	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
125	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
126	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
129	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
130	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
131	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
132	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
133	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
134	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
136	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
137	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
138	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
139	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
140	/* [78(0x4e)] = */ kCpumMicroarch_Intel_Core7_Skylake,
141	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Broadwell-E */
142	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
145	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
146	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
147	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu; skylake <= 4, cascade lake > 5 */
148	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
149	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
150	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
151	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
152	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
153	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
154	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
155	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
156	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
157	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
158	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
159	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
160	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
161	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
162	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
163	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
164	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
165	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
166	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
167	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
168	/[106(0x6a)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
169	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
170	/[108(0x6c)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
171	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
172	/[110(0x6e)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
173	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
174	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
175	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
176	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
177	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
178	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
179	/[117(0x75)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
180	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
181	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
182	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
183	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
184	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
185	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
186	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
187	/[125(0x7d)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
188	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
189	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
190	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
191	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
192	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
193	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
194	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
195	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
196	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
197	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
198	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
199	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
200	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
201	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
202	/[140(0x8c)] = / kCpumMicroarch_Intel_Core7_TigerLake, /* 11th Gen Intel(R) Core(TM) i7-1185G7 @ 3.00GHz (bird) */
203	/[141(0x8d)] = / kCpumMicroarch_Intel_Core7_TigerLake, /* unconfirmed */
204	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
205	/[143(0x8f)] = / kCpumMicroarch_Intel_Core7_SapphireRapids,
206	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
207	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
208	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
209	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
210	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
211	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
212	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
213	/[151(0x97)] = / kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
214	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
215	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
216	/[154(0x9a)] = / kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
217	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
218	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
219	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
220	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
221	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
222	/[160(0xa0)] = / kCpumMicroarch_Intel_Unknown,
223	/[161(0xa1)] = / kCpumMicroarch_Intel_Unknown,
224	/[162(0xa2)] = / kCpumMicroarch_Intel_Unknown,
225	/[163(0xa3)] = / kCpumMicroarch_Intel_Unknown,
226	/[164(0xa4)] = / kCpumMicroarch_Intel_Unknown,
227	/[165(0xa5)] = / kCpumMicroarch_Intel_Core7_CometLake, /* unconfirmed */
228	/[166(0xa6)] = / kCpumMicroarch_Intel_Unknown,
229	/[167(0xa7)] = / kCpumMicroarch_Intel_Core7_CypressCove, /* 14nm backport, unconfirmed */
230	};
231	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0xa7+1);
232
233
234	/**
235	* Figures out the (sub-)micro architecture given a bit of CPUID info.
236	*
237	* @returns Micro architecture.
238	* @param enmVendor The CPU vendor.
239	* @param bFamily The CPU family.
240	* @param bModel The CPU model.
241	* @param bStepping The CPU stepping.
242	*/
243	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
244	uint8_t bModel, uint8_t bStepping)
245	{
246	if (enmVendor == CPUMCPUVENDOR_AMD)
247	{
248	switch (bFamily)
249	{
250	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
251	case 0x03: return kCpumMicroarch_AMD_Am386;
252	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
253	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
254	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
255	case 0x06:
256	switch (bModel)
257	{
258	case 0: return kCpumMicroarch_AMD_K7_Palomino;
259	case 1: return kCpumMicroarch_AMD_K7_Palomino;
260	case 2: return kCpumMicroarch_AMD_K7_Palomino;
261	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
262	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
263	case 6: return kCpumMicroarch_AMD_K7_Palomino;
264	case 7: return kCpumMicroarch_AMD_K7_Morgan;
265	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
266	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
267	}
268	return kCpumMicroarch_AMD_K7_Unknown;
269	case 0x0f:
270	/*
271	* This family is a friggin mess. Trying my best to make some
272	* sense out of it. Too much happened in the 0x0f family to
273	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
274	*
275	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
276	* cpu-world.com, and other places:
277	* - 130nm:
278	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
279	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
280	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
281	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
282	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
283	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
284	* - 90nm:
285	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
286	* - Oakville: 10FC0/DH-D0.
287	* - Georgetown: 10FC0/DH-D0.
288	* - Sonora: 10FC0/DH-D0.
289	* - Venus: 20F71/SH-E4
290	* - Troy: 20F51/SH-E4
291	* - Athens: 20F51/SH-E4
292	* - San Diego: 20F71/SH-E4.
293	* - Lancaster: 20F42/SH-E5
294	* - Newark: 20F42/SH-E5.
295	* - Albany: 20FC2/DH-E6.
296	* - Roma: 20FC2/DH-E6.
297	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
298	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
299	* - 90nm introducing Dual core:
300	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
301	* - Italy: 20F10/JH-E1, 20F12/JH-E6
302	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
303	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
304	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
305	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
306	* - Santa Ana: 40F32/JH-F2, /-F3
307	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
308	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
309	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
310	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
311	* - Keene: 40FC2/DH-F2.
312	* - Richmond: 40FC2/DH-F2
313	* - Taylor: 40F82/BH-F2
314	* - Trinidad: 40F82/BH-F2
315	*
316	* - 65nm:
317	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
318	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
319	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
320	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
321	* - Sherman: /-G1, 70FC2/DH-G2.
322	* - Huron: 70FF2/DH-G2.
323	*/
324	if (bModel < 0x10)
325	return kCpumMicroarch_AMD_K8_130nm;
326	if (bModel >= 0x60 && bModel < 0x80)
327	return kCpumMicroarch_AMD_K8_65nm;
328	if (bModel >= 0x40)
329	return kCpumMicroarch_AMD_K8_90nm_AMDV;
330	switch (bModel)
331	{
332	case 0x21:
333	case 0x23:
334	case 0x2b:
335	case 0x2f:
336	case 0x37:
337	case 0x3f:
338	return kCpumMicroarch_AMD_K8_90nm_DualCore;
339	}
340	return kCpumMicroarch_AMD_K8_90nm;
341	case 0x10:
342	return kCpumMicroarch_AMD_K10;
343	case 0x11:
344	return kCpumMicroarch_AMD_K10_Lion;
345	case 0x12:
346	return kCpumMicroarch_AMD_K10_Llano;
347	case 0x14:
348	return kCpumMicroarch_AMD_Bobcat;
349	case 0x15:
350	switch (bModel)
351	{
352	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
353	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
354	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
355	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
356	case 0x11: /* ?? */
357	case 0x12: /* ?? */
358	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
359	}
360	return kCpumMicroarch_AMD_15h_Unknown;
361	case 0x16:
362	return kCpumMicroarch_AMD_Jaguar;
363	case 0x17:
364	return kCpumMicroarch_AMD_Zen_Ryzen;
365	}
366	return kCpumMicroarch_AMD_Unknown;
367	}
368
369	if (enmVendor == CPUMCPUVENDOR_INTEL)
370	{
371	switch (bFamily)
372	{
373	case 3:
374	return kCpumMicroarch_Intel_80386;
375	case 4:
376	return kCpumMicroarch_Intel_80486;
377	case 5:
378	return kCpumMicroarch_Intel_P5;
379	case 6:
380	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
381	{
382	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
383	if (enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake)
384	{
385	if (bStepping >= 0xa && bStepping <= 0xc)
386	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
387	else if (bStepping >= 0xc)
388	enmMicroArch = kCpumMicroarch_Intel_Core7_WhiskeyLake;
389	}
390	else if ( enmMicroArch == kCpumMicroarch_Intel_Core7_Skylake
391	&& bModel == 0x55
392	&& bStepping >= 5)
393	enmMicroArch = kCpumMicroarch_Intel_Core7_CascadeLake;
394	return enmMicroArch;
395	}
396	return kCpumMicroarch_Intel_Atom_Unknown;
397	case 15:
398	switch (bModel)
399	{
400	case 0: return kCpumMicroarch_Intel_NB_Willamette;
401	case 1: return kCpumMicroarch_Intel_NB_Willamette;
402	case 2: return kCpumMicroarch_Intel_NB_Northwood;
403	case 3: return kCpumMicroarch_Intel_NB_Prescott;
404	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
405	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
406	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
407	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
408	default: return kCpumMicroarch_Intel_NB_Unknown;
409	}
410	break;
411	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
412	case 0:
413	return kCpumMicroarch_Intel_8086;
414	case 1:
415	return kCpumMicroarch_Intel_80186;
416	case 2:
417	return kCpumMicroarch_Intel_80286;
418	}
419	return kCpumMicroarch_Intel_Unknown;
420	}
421
422	if (enmVendor == CPUMCPUVENDOR_VIA)
423	{
424	switch (bFamily)
425	{
426	case 5:
427	switch (bModel)
428	{
429	case 1: return kCpumMicroarch_Centaur_C6;
430	case 4: return kCpumMicroarch_Centaur_C6;
431	case 8: return kCpumMicroarch_Centaur_C2;
432	case 9: return kCpumMicroarch_Centaur_C3;
433	}
434	break;
435
436	case 6:
437	switch (bModel)
438	{
439	case 5: return kCpumMicroarch_VIA_C3_M2;
440	case 6: return kCpumMicroarch_VIA_C3_C5A;
441	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
442	case 8: return kCpumMicroarch_VIA_C3_C5N;
443	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
444	case 10: return kCpumMicroarch_VIA_C7_C5J;
445	case 15: return kCpumMicroarch_VIA_Isaiah;
446	}
447	break;
448	}
449	return kCpumMicroarch_VIA_Unknown;
450	}
451
452	if (enmVendor == CPUMCPUVENDOR_SHANGHAI)
453	{
454	switch (bFamily)
455	{
456	case 6:
457	case 7:
458	return kCpumMicroarch_Shanghai_Wudaokou;
459	default:
460	break;
461	}
462	return kCpumMicroarch_Shanghai_Unknown;
463	}
464
465	if (enmVendor == CPUMCPUVENDOR_CYRIX)
466	{
467	switch (bFamily)
468	{
469	case 4:
470	switch (bModel)
471	{
472	case 9: return kCpumMicroarch_Cyrix_5x86;
473	}
474	break;
475
476	case 5:
477	switch (bModel)
478	{
479	case 2: return kCpumMicroarch_Cyrix_M1;
480	case 4: return kCpumMicroarch_Cyrix_MediaGX;
481	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
482	}
483	break;
484
485	case 6:
486	switch (bModel)
487	{
488	case 0: return kCpumMicroarch_Cyrix_M2;
489	}
490	break;
491
492	}
493	return kCpumMicroarch_Cyrix_Unknown;
494	}
495
496	if (enmVendor == CPUMCPUVENDOR_HYGON)
497	{
498	switch (bFamily)
499	{
500	case 0x18:
501	return kCpumMicroarch_Hygon_Dhyana;
502	default:
503	break;
504	}
505	return kCpumMicroarch_Hygon_Unknown;
506	}
507
508	return kCpumMicroarch_Unknown;
509	}
510
511
512	/**
513	* Translates a microarchitecture enum value to the corresponding string
514	* constant.
515	*
516	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
517	* NULL if the value is invalid.
518	*
519	* @param enmMicroarch The enum value to convert.
520	*/
521	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
522	{
523	switch (enmMicroarch)
524	{
525	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
526	CASE_RET_STR(kCpumMicroarch_Intel_8086);
527	CASE_RET_STR(kCpumMicroarch_Intel_80186);
528	CASE_RET_STR(kCpumMicroarch_Intel_80286);
529	CASE_RET_STR(kCpumMicroarch_Intel_80386);
530	CASE_RET_STR(kCpumMicroarch_Intel_80486);
531	CASE_RET_STR(kCpumMicroarch_Intel_P5);
532
533	CASE_RET_STR(kCpumMicroarch_Intel_P6);
534	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
535	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
536
537	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
538	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
539	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
540
541	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
542	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
543
544	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
545	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
546	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
547	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
548	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
549	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
550	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
551	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
552	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
553	CASE_RET_STR(kCpumMicroarch_Intel_Core7_WhiskeyLake);
554	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CascadeLake);
555	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
556	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CometLake);
557	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
558	CASE_RET_STR(kCpumMicroarch_Intel_Core7_RocketLake);
559	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
560	CASE_RET_STR(kCpumMicroarch_Intel_Core7_AlderLake);
561	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SapphireRapids);
562
563	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
564	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
565	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
566	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
567	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
568	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
569	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
570	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
571
572	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
573	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
574	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
575	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
576	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
577
578	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
579	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
580	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
581	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
582	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
583	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
584	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
585
586	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
587
588	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
589	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
590	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
591	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
592	CASE_RET_STR(kCpumMicroarch_AMD_K5);
593	CASE_RET_STR(kCpumMicroarch_AMD_K6);
594
595	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
596	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
597	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
598	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
599	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
600	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
601	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
602
603	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
604	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
605	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
606	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
607	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
608
609	CASE_RET_STR(kCpumMicroarch_AMD_K10);
610	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
611	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
612	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
613	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
614
615	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
616	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
617	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
618	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
619	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
620
621	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
622
623	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
624
625	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
626
627	CASE_RET_STR(kCpumMicroarch_Hygon_Dhyana);
628	CASE_RET_STR(kCpumMicroarch_Hygon_Unknown);
629
630	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
631	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
632	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
633	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
634	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
635	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
636	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
637	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
638	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
639	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
640	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
641	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
642	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
643
644	CASE_RET_STR(kCpumMicroarch_Shanghai_Wudaokou);
645	CASE_RET_STR(kCpumMicroarch_Shanghai_Unknown);
646
647	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
648	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
649	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
650	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
651	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
652	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
653
654	CASE_RET_STR(kCpumMicroarch_NEC_V20);
655	CASE_RET_STR(kCpumMicroarch_NEC_V30);
656
657	CASE_RET_STR(kCpumMicroarch_Unknown);
658
659	#undef CASE_RET_STR
660	case kCpumMicroarch_Invalid:
661	case kCpumMicroarch_Intel_End:
662	case kCpumMicroarch_Intel_Core2_End:
663	case kCpumMicroarch_Intel_Core7_End:
664	case kCpumMicroarch_Intel_Atom_End:
665	case kCpumMicroarch_Intel_P6_Core_Atom_End:
666	case kCpumMicroarch_Intel_Phi_End:
667	case kCpumMicroarch_Intel_NB_End:
668	case kCpumMicroarch_AMD_K7_End:
669	case kCpumMicroarch_AMD_K8_End:
670	case kCpumMicroarch_AMD_15h_End:
671	case kCpumMicroarch_AMD_16h_End:
672	case kCpumMicroarch_AMD_Zen_End:
673	case kCpumMicroarch_AMD_End:
674	case kCpumMicroarch_Hygon_End:
675	case kCpumMicroarch_VIA_End:
676	case kCpumMicroarch_Shanghai_End:
677	case kCpumMicroarch_Cyrix_End:
678	case kCpumMicroarch_NEC_End:
679	case kCpumMicroarch_32BitHack:
680	break;
681	/* no default! */
682	}
683
684	return NULL;
685	}
686
687
688	/**
689	* Determins the host CPU MXCSR mask.
690	*
691	* @returns MXCSR mask.
692	*/
693	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
694	{
695	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
696	if ( ASMHasCpuId()
697	&& RTX86IsValidStdRange(ASMCpuId_EAX(0))
698	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
699	{
700	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
701	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
702	RT_ZERO(*pState);
703	ASMFxSave(pState);
704	if (pState->MXCSR_MASK == 0)
705	return 0xffbf;
706	return pState->MXCSR_MASK;
707	}
708	#endif
709	return 0;
710	}
711
712
713	/**
714	* Gets a matching leaf in the CPUID leaf array.
715	*
716	* @returns Pointer to the matching leaf, or NULL if not found.
717	* @param paLeaves The CPUID leaves to search. This is sorted.
718	* @param cLeaves The number of leaves in the array.
719	* @param uLeaf The leaf to locate.
720	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
721	*/
722	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
723	{
724	/* Lazy bird does linear lookup here since this is only used for the
725	occational CPUID overrides. */
726	for (uint32_t i = 0; i < cLeaves; i++)
727	if ( paLeaves[i].uLeaf == uLeaf
728	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
729	return &paLeaves[i];
730	return NULL;
731	}
732
733
734	#ifndef IN_VBOX_CPU_REPORT
735	/**
736	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
737	*
738	* @returns true if found, false it not.
739	* @param paLeaves The CPUID leaves to search. This is sorted.
740	* @param cLeaves The number of leaves in the array.
741	* @param uLeaf The leaf to locate.
742	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
743	* @param pLegacy The legacy output leaf.
744	*/
745	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
746	PCPUMCPUID pLegacy)
747	{
748	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
749	if (pLeaf)
750	{
751	pLegacy->uEax = pLeaf->uEax;
752	pLegacy->uEbx = pLeaf->uEbx;
753	pLegacy->uEcx = pLeaf->uEcx;
754	pLegacy->uEdx = pLeaf->uEdx;
755	return true;
756	}
757	return false;
758	}
759	#endif /* IN_VBOX_CPU_REPORT */
760
761
762	/**
763	* Ensures that the CPUID leaf array can hold one more leaf.
764	*
765	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
766	* failure.
767	* @param pVM The cross context VM structure. If NULL, use
768	* the process heap, otherwise the VM's hyper heap.
769	* @param ppaLeaves Pointer to the variable holding the array pointer
770	* (input/output).
771	* @param cLeaves The current array size.
772	*
773	* @remarks This function will automatically update the R0 and RC pointers when
774	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
775	* be the corresponding VM's CPUID arrays (which is asserted).
776	*/
777	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
778	{
779	/*
780	* If pVM is not specified, we're on the regular heap and can waste a
781	* little space to speed things up.
782	*/
783	uint32_t cAllocated;
784	if (!pVM)
785	{
786	cAllocated = RT_ALIGN(cLeaves, 16);
787	if (cLeaves + 1 > cAllocated)
788	{
789	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
790	if (pvNew)
791	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
792	else
793	{
794	RTMemFree(*ppaLeaves);
795	*ppaLeaves = NULL;
796	}
797	}
798	}
799	/*
800	* Otherwise, we're on the hyper heap and are probably just inserting
801	* one or two leaves and should conserve space.
802	*/
803	else
804	{
805	#ifdef IN_VBOX_CPU_REPORT
806	AssertReleaseFailed();
807	#else
808	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
809	Assert(*ppaLeaves == pVM->cpum.s.GuestInfo.aCpuIdLeaves);
810	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
811
812	if (cLeaves + 1 <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves))
813	{ }
814	else
815	{
816	*ppaLeaves = NULL;
817	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: Out of CPUID space!\n"));
818	}
819	#endif
820	}
821	return *ppaLeaves;
822	}
823
824
825	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
826	/**
827	* Append a CPUID leaf or sub-leaf.
828	*
829	* ASSUMES linear insertion order, so we'll won't need to do any searching or
830	* replace anything. Use cpumR3CpuIdInsert() for those cases.
831	*
832	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
833	* the caller need do no more work.
834	* @param ppaLeaves Pointer to the pointer to the array of sorted
835	* CPUID leaves and sub-leaves.
836	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
837	* @param uLeaf The leaf we're adding.
838	* @param uSubLeaf The sub-leaf number.
839	* @param fSubLeafMask The sub-leaf mask.
840	* @param uEax The EAX value.
841	* @param uEbx The EBX value.
842	* @param uEcx The ECX value.
843	* @param uEdx The EDX value.
844	* @param fFlags The flags.
845	*/
846	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
847	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
848	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
849	{
850	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
851	return VERR_NO_MEMORY;
852
853	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
854	Assert( *pcLeaves == 0
855	\|\| pNew[-1].uLeaf < uLeaf
856	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
857
858	pNew->uLeaf = uLeaf;
859	pNew->uSubLeaf = uSubLeaf;
860	pNew->fSubLeafMask = fSubLeafMask;
861	pNew->uEax = uEax;
862	pNew->uEbx = uEbx;
863	pNew->uEcx = uEcx;
864	pNew->uEdx = uEdx;
865	pNew->fFlags = fFlags;
866
867	*pcLeaves += 1;
868	return VINF_SUCCESS;
869	}
870	#endif /* RT_ARCH_X86 \|\| RT_ARCH_AMD64 */
871
872
873	/**
874	* Checks that we've updated the CPUID leaves array correctly.
875	*
876	* This is a no-op in non-strict builds.
877	*
878	* @param paLeaves The leaves array.
879	* @param cLeaves The number of leaves.
880	*/
881	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
882	{
883	#ifdef VBOX_STRICT
884	for (uint32_t i = 1; i < cLeaves; i++)
885	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
886	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
887	else
888	{
889	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
890	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
891	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
892	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
893	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
894	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
895	}
896	#else
897	NOREF(paLeaves);
898	NOREF(cLeaves);
899	#endif
900	}
901
902
903	/**
904	* Inserts a CPU ID leaf, replacing any existing ones.
905	*
906	* When inserting a simple leaf where we already got a series of sub-leaves with
907	* the same leaf number (eax), the simple leaf will replace the whole series.
908	*
909	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
910	* host-context heap and has only been allocated/reallocated by the
911	* cpumR3CpuIdEnsureSpace function.
912	*
913	* @returns VBox status code.
914	* @param pVM The cross context VM structure. If NULL, use
915	* the process heap, otherwise the VM's hyper heap.
916	* @param ppaLeaves Pointer to the pointer to the array of sorted
917	* CPUID leaves and sub-leaves. Must be NULL if using
918	* the hyper heap.
919	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
920	* be NULL if using the hyper heap.
921	* @param pNewLeaf Pointer to the data of the new leaf we're about to
922	* insert.
923	*/
924	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
925	{
926	/*
927	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
928	*/
929	if (pVM)
930	{
931	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
932	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
933	AssertReturn(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 == pVM->cpum.s.GuestInfo.aCpuIdLeaves, VERR_INVALID_PARAMETER);
934
935	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
936	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
937	}
938
939	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
940	uint32_t cLeaves = *pcLeaves;
941
942	/*
943	* Validate the new leaf a little.
944	*/
945	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
946	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
947	VERR_INVALID_FLAGS);
948	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
949	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
950	VERR_INVALID_PARAMETER);
951	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
952	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
953	VERR_INVALID_PARAMETER);
954	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
955	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
956	VERR_INVALID_PARAMETER);
957
958	/*
959	* Find insertion point. The lazy bird uses the same excuse as in
960	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
961	*/
962	uint32_t i;
963	if ( cLeaves > 0
964	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
965	{
966	/* Add at end. */
967	i = cLeaves;
968	}
969	else if ( cLeaves > 0
970	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
971	{
972	/* Either replacing the last leaf or dealing with sub-leaves. Spool
973	back to the first sub-leaf to pretend we did the linear search. */
974	i = cLeaves - 1;
975	while ( i > 0
976	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
977	i--;
978	}
979	else
980	{
981	/* Linear search from the start. */
982	i = 0;
983	while ( i < cLeaves
984	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
985	i++;
986	}
987	if ( i < cLeaves
988	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
989	{
990	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
991	{
992	/*
993	* The sub-leaf mask differs, replace all existing leaves with the
994	* same leaf number.
995	*/
996	uint32_t c = 1;
997	while ( i + c < cLeaves
998	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
999	c++;
1000	if (c > 1 && i + c < cLeaves)
1001	{
1002	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
1003	*pcLeaves = cLeaves -= c - 1;
1004	}
1005
1006	paLeaves[i] = *pNewLeaf;
1007	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1008	return VINF_SUCCESS;
1009	}
1010
1011	/* Find sub-leaf insertion point. */
1012	while ( i < cLeaves
1013	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
1014	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
1015	i++;
1016
1017	/*
1018	* If we've got an exactly matching leaf, replace it.
1019	*/
1020	if ( i < cLeaves
1021	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
1022	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
1023	{
1024	paLeaves[i] = *pNewLeaf;
1025	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1026	return VINF_SUCCESS;
1027	}
1028	}
1029
1030	/*
1031	* Adding a new leaf at 'i'.
1032	*/
1033	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
1034	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
1035	if (!paLeaves)
1036	return VERR_NO_MEMORY;
1037
1038	if (i < cLeaves)
1039	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
1040	*pcLeaves += 1;
1041	paLeaves[i] = *pNewLeaf;
1042
1043	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1044	return VINF_SUCCESS;
1045	}
1046
1047
1048	#ifndef IN_VBOX_CPU_REPORT
1049	/**
1050	* Removes a range of CPUID leaves.
1051	*
1052	* This will not reallocate the array.
1053	*
1054	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1055	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1056	* @param uFirst The first leaf.
1057	* @param uLast The last leaf.
1058	*/
1059	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1060	{
1061	uint32_t cLeaves = *pcLeaves;
1062
1063	Assert(uFirst <= uLast);
1064
1065	/*
1066	* Find the first one.
1067	*/
1068	uint32_t iFirst = 0;
1069	while ( iFirst < cLeaves
1070	&& paLeaves[iFirst].uLeaf < uFirst)
1071	iFirst++;
1072
1073	/*
1074	* Find the end (last + 1).
1075	*/
1076	uint32_t iEnd = iFirst;
1077	while ( iEnd < cLeaves
1078	&& paLeaves[iEnd].uLeaf <= uLast)
1079	iEnd++;
1080
1081	/*
1082	* Adjust the array if anything needs removing.
1083	*/
1084	if (iFirst < iEnd)
1085	{
1086	if (iEnd < cLeaves)
1087	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1088	*pcLeaves = cLeaves -= (iEnd - iFirst);
1089	}
1090
1091	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1092	}
1093	#endif /* IN_VBOX_CPU_REPORT */
1094
1095
1096	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
1097	/**
1098	* Checks if ECX make a difference when reading a given CPUID leaf.
1099	*
1100	* @returns @c true if it does, @c false if it doesn't.
1101	* @param uLeaf The leaf we're reading.
1102	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1103	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1104	* final sub-leaf (for leaf 0xb only).
1105	*/
1106	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1107	{
1108	*pfFinalEcxUnchanged = false;
1109
1110	uint32_t auCur[4];
1111	uint32_t auPrev[4];
1112	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1113
1114	/* Look for sub-leaves. */
1115	uint32_t uSubLeaf = 1;
1116	for (;;)
1117	{
1118	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1119	if (memcmp(auCur, auPrev, sizeof(auCur)))
1120	break;
1121
1122	/* Advance / give up. */
1123	uSubLeaf++;
1124	if (uSubLeaf >= 64)
1125	{
1126	*pcSubLeaves = 1;
1127	return false;
1128	}
1129	}
1130
1131	/* Count sub-leaves. */
1132	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1133	uint32_t cRepeats = 0;
1134	uSubLeaf = 0;
1135	for (;;)
1136	{
1137	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1138
1139	/* Figuring out when to stop isn't entirely straight forward as we need
1140	to cover undocumented behavior up to a point and implementation shortcuts. */
1141
1142	/* 1. Look for more than 4 repeating value sets. */
1143	if ( auCur[0] == auPrev[0]
1144	&& auCur[1] == auPrev[1]
1145	&& ( auCur[2] == auPrev[2]
1146	\|\| ( auCur[2] == uSubLeaf
1147	&& auPrev[2] == uSubLeaf - 1) )
1148	&& auCur[3] == auPrev[3])
1149	{
1150	if ( uLeaf != 0xd
1151	\|\| uSubLeaf >= 64
1152	\|\| ( auCur[0] == 0
1153	&& auCur[1] == 0
1154	&& auCur[2] == 0
1155	&& auCur[3] == 0
1156	&& auPrev[2] == 0) )
1157	cRepeats++;
1158	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1159	break;
1160	}
1161	else
1162	cRepeats = 0;
1163
1164	/* 2. Look for zero values. */
1165	if ( auCur[0] == 0
1166	&& auCur[1] == 0
1167	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1168	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1169	&& uSubLeaf >= cMinLeaves)
1170	{
1171	cRepeats = 0;
1172	break;
1173	}
1174
1175	/* 3. Leaf 0xb level type 0 check. */
1176	if ( uLeaf == 0xb
1177	&& (auCur[2] & 0xff00) == 0
1178	&& (auPrev[2] & 0xff00) == 0)
1179	{
1180	cRepeats = 0;
1181	break;
1182	}
1183
1184	/* 99. Give up. */
1185	if (uSubLeaf >= 128)
1186	{
1187	# ifndef IN_VBOX_CPU_REPORT
1188	/* Ok, limit it according to the documentation if possible just to
1189	avoid annoying users with these detection issues. */
1190	uint32_t cDocLimit = UINT32_MAX;
1191	if (uLeaf == 0x4)
1192	cDocLimit = 4;
1193	else if (uLeaf == 0x7)
1194	cDocLimit = 1;
1195	else if (uLeaf == 0xd)
1196	cDocLimit = 63;
1197	else if (uLeaf == 0xf)
1198	cDocLimit = 2;
1199	if (cDocLimit != UINT32_MAX)
1200	{
1201	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1202	*pcSubLeaves = cDocLimit + 3;
1203	return true;
1204	}
1205	# endif
1206	*pcSubLeaves = UINT32_MAX;
1207	return true;
1208	}
1209
1210	/* Advance. */
1211	uSubLeaf++;
1212	memcpy(auPrev, auCur, sizeof(auCur));
1213	}
1214
1215	/* Standard exit. */
1216	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1217	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1218	if (*pcSubLeaves == 0)
1219	*pcSubLeaves = 1;
1220	return true;
1221	}
1222	#endif /* RT_ARCH_X86 \|\| RT_ARCH_AMD64 */
1223
1224
1225	/**
1226	* Gets a CPU ID leaf.
1227	*
1228	* @returns VBox status code.
1229	* @param pVM The cross context VM structure.
1230	* @param pLeaf Where to store the found leaf.
1231	* @param uLeaf The leaf to locate.
1232	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1233	*/
1234	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1235	{
1236	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1237	uLeaf, uSubLeaf);
1238	if (pcLeaf)
1239	{
1240	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1241	return VINF_SUCCESS;
1242	}
1243
1244	return VERR_NOT_FOUND;
1245	}
1246
1247
1248	/**
1249	* Gets all the leaves.
1250	*
1251	* This only works after the CPUID leaves have been initialized. The interface
1252	* is intended for NEM and configuring CPUID leaves for the native hypervisor.
1253	*
1254	* @returns Pointer to the array of leaves. NULL on failure.
1255	* @param pVM The cross context VM structure.
1256	* @param pcLeaves Where to return the number of leaves.
1257	*/
1258	VMMR3_INT_DECL(PCCPUMCPUIDLEAF) CPUMR3CpuIdGetPtr(PVM pVM, uint32_t *pcLeaves)
1259	{
1260	*pcLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
1261	return pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
1262	}
1263
1264
1265	/**
1266	* Inserts a CPU ID leaf, replacing any existing ones.
1267	*
1268	* @returns VBox status code.
1269	* @param pVM The cross context VM structure.
1270	* @param pNewLeaf Pointer to the leaf being inserted.
1271	*/
1272	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1273	{
1274	/*
1275	* Validate parameters.
1276	*/
1277	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1278	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1279
1280	/*
1281	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1282	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1283	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1284	*/
1285	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1286	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1287	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1288	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1289	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1290	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1291	{
1292	return VERR_NOT_SUPPORTED;
1293	}
1294
1295	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1296	}
1297
1298	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
1299
1300	/**
1301	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1302	*
1303	* @returns VBox status code.
1304	* @param ppaLeaves Where to return the array pointer on success.
1305	* Use RTMemFree to release.
1306	* @param pcLeaves Where to return the size of the array on
1307	* success.
1308	*/
1309	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1310	{
1311	*ppaLeaves = NULL;
1312	*pcLeaves = 0;
1313
1314	/*
1315	* Try out various candidates. This must be sorted!
1316	*/
1317	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1318	{
1319	{ UINT32_C(0x00000000), false },
1320	{ UINT32_C(0x10000000), false },
1321	{ UINT32_C(0x20000000), false },
1322	{ UINT32_C(0x30000000), false },
1323	{ UINT32_C(0x40000000), false },
1324	{ UINT32_C(0x50000000), false },
1325	{ UINT32_C(0x60000000), false },
1326	{ UINT32_C(0x70000000), false },
1327	{ UINT32_C(0x80000000), false },
1328	{ UINT32_C(0x80860000), false },
1329	{ UINT32_C(0x8ffffffe), true },
1330	{ UINT32_C(0x8fffffff), true },
1331	{ UINT32_C(0x90000000), false },
1332	{ UINT32_C(0xa0000000), false },
1333	{ UINT32_C(0xb0000000), false },
1334	{ UINT32_C(0xc0000000), false },
1335	{ UINT32_C(0xd0000000), false },
1336	{ UINT32_C(0xe0000000), false },
1337	{ UINT32_C(0xf0000000), false },
1338	};
1339
1340	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1341	{
1342	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1343	uint32_t uEax, uEbx, uEcx, uEdx;
1344	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1345
1346	/*
1347	* Does EAX look like a typical leaf count value?
1348	*/
1349	if ( uEax > uLeaf
1350	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1351	{
1352	/* Yes, dump them. */
1353	uint32_t cLeaves = uEax - uLeaf + 1;
1354	while (cLeaves-- > 0)
1355	{
1356	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1357
1358	uint32_t fFlags = 0;
1359
1360	/* There are currently three known leaves containing an APIC ID
1361	that needs EMT specific attention */
1362	if (uLeaf == 1)
1363	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1364	else if (uLeaf == 0xb && uEcx != 0)
1365	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1366	else if ( uLeaf == UINT32_C(0x8000001e)
1367	&& ( uEax
1368	\|\| uEbx
1369	\|\| uEdx
1370	\|\| RTX86IsAmdCpu((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1371	\|\| RTX86IsHygonCpu((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1372	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1373
1374	/* The APIC bit is per-VCpu and needs flagging. */
1375	if (uLeaf == 1)
1376	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1377	else if ( uLeaf == UINT32_C(0x80000001)
1378	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1379	\|\| RTX86IsAmdCpu((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1380	\|\| RTX86IsHygonCpu((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1381	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1382
1383	/* Check three times here to reduce the chance of CPU migration
1384	resulting in false positives with things like the APIC ID. */
1385	uint32_t cSubLeaves;
1386	bool fFinalEcxUnchanged;
1387	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1388	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1389	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1390	{
1391	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1392	{
1393	/* This shouldn't happen. But in case it does, file all
1394	relevant details in the release log. */
1395	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1396	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1397	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1398	{
1399	uint32_t auTmp[4];
1400	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1401	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1402	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1403	}
1404	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1405	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1406	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1407	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1408	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1409	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1410	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1411	}
1412
1413	if (fFinalEcxUnchanged)
1414	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1415
1416	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1417	{
1418	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1419	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1420	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1421	if (RT_FAILURE(rc))
1422	return rc;
1423	}
1424	}
1425	else
1426	{
1427	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1428	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1429	if (RT_FAILURE(rc))
1430	return rc;
1431	}
1432
1433	/* next */
1434	uLeaf++;
1435	}
1436	}
1437	/*
1438	* Special CPUIDs needs special handling as they don't follow the
1439	* leaf count principle used above.
1440	*/
1441	else if (s_aCandidates[iOuter].fSpecial)
1442	{
1443	bool fKeep = false;
1444	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1445	fKeep = true;
1446	else if ( uLeaf == 0x8fffffff
1447	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1448	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1449	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1450	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1451	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1452	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1453	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1454	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1455	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1456	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1457	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1458	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1459	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1460	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1461	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1462	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1463	fKeep = true;
1464	if (fKeep)
1465	{
1466	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1467	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1468	if (RT_FAILURE(rc))
1469	return rc;
1470	}
1471	}
1472	}
1473
1474	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1475	return VINF_SUCCESS;
1476	}
1477
1478
1479	/**
1480	* Determines the method the CPU uses to handle unknown CPUID leaves.
1481	*
1482	* @returns VBox status code.
1483	* @param penmUnknownMethod Where to return the method.
1484	* @param pDefUnknown Where to return default unknown values. This
1485	* will be set, even if the resulting method
1486	* doesn't actually needs it.
1487	*/
1488	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1489	{
1490	uint32_t uLastStd = ASMCpuId_EAX(0);
1491	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1492	if (!RTX86IsValidExtRange(uLastExt))
1493	uLastExt = 0x80000000;
1494
1495	uint32_t auChecks[] =
1496	{
1497	uLastStd + 1,
1498	uLastStd + 5,
1499	uLastStd + 8,
1500	uLastStd + 32,
1501	uLastStd + 251,
1502	uLastExt + 1,
1503	uLastExt + 8,
1504	uLastExt + 15,
1505	uLastExt + 63,
1506	uLastExt + 255,
1507	0x7fbbffcc,
1508	0x833f7872,
1509	0xefff2353,
1510	0x35779456,
1511	0x1ef6d33e,
1512	};
1513
1514	static const uint32_t s_auValues[] =
1515	{
1516	0xa95d2156,
1517	0x00000001,
1518	0x00000002,
1519	0x00000008,
1520	0x00000000,
1521	0x55773399,
1522	0x93401769,
1523	0x12039587,
1524	};
1525
1526	/*
1527	* Simple method, all zeros.
1528	*/
1529	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1530	pDefUnknown->uEax = 0;
1531	pDefUnknown->uEbx = 0;
1532	pDefUnknown->uEcx = 0;
1533	pDefUnknown->uEdx = 0;
1534
1535	/*
1536	* Intel has been observed returning the last standard leaf.
1537	*/
1538	uint32_t auLast[4];
1539	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1540
1541	uint32_t cChecks = RT_ELEMENTS(auChecks);
1542	while (cChecks > 0)
1543	{
1544	uint32_t auCur[4];
1545	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1546	if (memcmp(auCur, auLast, sizeof(auCur)))
1547	break;
1548	cChecks--;
1549	}
1550	if (cChecks == 0)
1551	{
1552	/* Now, what happens when the input changes? Esp. ECX. */
1553	uint32_t cTotal = 0;
1554	uint32_t cSame = 0;
1555	uint32_t cLastWithEcx = 0;
1556	uint32_t cNeither = 0;
1557	uint32_t cValues = RT_ELEMENTS(s_auValues);
1558	while (cValues > 0)
1559	{
1560	uint32_t uValue = s_auValues[cValues - 1];
1561	uint32_t auLastWithEcx[4];
1562	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1563	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1564
1565	cChecks = RT_ELEMENTS(auChecks);
1566	while (cChecks > 0)
1567	{
1568	uint32_t auCur[4];
1569	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1570	if (!memcmp(auCur, auLast, sizeof(auCur)))
1571	{
1572	cSame++;
1573	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1574	cLastWithEcx++;
1575	}
1576	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1577	cLastWithEcx++;
1578	else
1579	cNeither++;
1580	cTotal++;
1581	cChecks--;
1582	}
1583	cValues--;
1584	}
1585
1586	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1587	if (cSame == cTotal)
1588	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1589	else if (cLastWithEcx == cTotal)
1590	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1591	else
1592	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1593	pDefUnknown->uEax = auLast[0];
1594	pDefUnknown->uEbx = auLast[1];
1595	pDefUnknown->uEcx = auLast[2];
1596	pDefUnknown->uEdx = auLast[3];
1597	return VINF_SUCCESS;
1598	}
1599
1600	/*
1601	* Unchanged register values?
1602	*/
1603	cChecks = RT_ELEMENTS(auChecks);
1604	while (cChecks > 0)
1605	{
1606	uint32_t const uLeaf = auChecks[cChecks - 1];
1607	uint32_t cValues = RT_ELEMENTS(s_auValues);
1608	while (cValues > 0)
1609	{
1610	uint32_t uValue = s_auValues[cValues - 1];
1611	uint32_t auCur[4];
1612	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1613	if ( auCur[0] != uLeaf
1614	\|\| auCur[1] != uValue
1615	\|\| auCur[2] != uValue
1616	\|\| auCur[3] != uValue)
1617	break;
1618	cValues--;
1619	}
1620	if (cValues != 0)
1621	break;
1622	cChecks--;
1623	}
1624	if (cChecks == 0)
1625	{
1626	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1627	return VINF_SUCCESS;
1628	}
1629
1630	/*
1631	* Just go with the simple method.
1632	*/
1633	return VINF_SUCCESS;
1634	}
1635
1636	#endif /* RT_ARCH_X86 \|\| RT_ARCH_AMD64 */
1637
1638	/**
1639	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1640	*
1641	* @returns Read only name string.
1642	* @param enmUnknownMethod The method to translate.
1643	*/
1644	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1645	{
1646	switch (enmUnknownMethod)
1647	{
1648	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1649	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1650	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1651	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1652
1653	case CPUMUNKNOWNCPUID_INVALID:
1654	case CPUMUNKNOWNCPUID_END:
1655	case CPUMUNKNOWNCPUID_32BIT_HACK:
1656	break;
1657	}
1658	return "Invalid-unknown-CPUID-method";
1659	}
1660
1661
1662	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
1663	/**
1664	* Detect the CPU vendor give n the
1665	*
1666	* @returns The vendor.
1667	* @param uEAX EAX from CPUID(0).
1668	* @param uEBX EBX from CPUID(0).
1669	* @param uECX ECX from CPUID(0).
1670	* @param uEDX EDX from CPUID(0).
1671	*/
1672	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1673	{
1674	if (RTX86IsValidStdRange(uEAX))
1675	{
1676	if (RTX86IsAmdCpu(uEBX, uECX, uEDX))
1677	return CPUMCPUVENDOR_AMD;
1678
1679	if (RTX86IsIntelCpu(uEBX, uECX, uEDX))
1680	return CPUMCPUVENDOR_INTEL;
1681
1682	if (RTX86IsViaCentaurCpu(uEBX, uECX, uEDX))
1683	return CPUMCPUVENDOR_VIA;
1684
1685	if (RTX86IsShanghaiCpu(uEBX, uECX, uEDX))
1686	return CPUMCPUVENDOR_SHANGHAI;
1687
1688	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1689	&& uECX == UINT32_C(0x64616574)
1690	&& uEDX == UINT32_C(0x736E4978))
1691	return CPUMCPUVENDOR_CYRIX;
1692
1693	if (RTX86IsHygonCpu(uEBX, uECX, uEDX))
1694	return CPUMCPUVENDOR_HYGON;
1695
1696	/* "Geode by NSC", example: family 5, model 9. */
1697
1698	/** @todo detect the other buggers... */
1699	}
1700
1701	return CPUMCPUVENDOR_UNKNOWN;
1702	}
1703	#endif /* RT_ARCH_X86 \|\| RT_ARCH_AMD64 */
1704
1705
1706	/**
1707	* Translates a CPU vendor enum value into the corresponding string constant.
1708	*
1709	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1710	* value name. This can be useful when generating code.
1711	*
1712	* @returns Read only name string.
1713	* @param enmVendor The CPU vendor value.
1714	*/
1715	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1716	{
1717	switch (enmVendor)
1718	{
1719	case CPUMCPUVENDOR_INTEL: return "INTEL";
1720	case CPUMCPUVENDOR_AMD: return "AMD";
1721	case CPUMCPUVENDOR_VIA: return "VIA";
1722	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1723	case CPUMCPUVENDOR_SHANGHAI: return "SHANGHAI";
1724	case CPUMCPUVENDOR_HYGON: return "HYGON";
1725	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1726
1727	case CPUMCPUVENDOR_INVALID:
1728	case CPUMCPUVENDOR_32BIT_HACK:
1729	break;
1730	}
1731	return "Invalid-cpu-vendor";
1732	}
1733
1734
1735	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1736	{
1737	/* Could do binary search, doing linear now because I'm lazy. */
1738	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1739	while (cLeaves-- > 0)
1740	{
1741	if (pLeaf->uLeaf == uLeaf)
1742	return pLeaf;
1743	pLeaf++;
1744	}
1745	return NULL;
1746	}
1747
1748
1749	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1750	{
1751	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1752	if ( !pLeaf
1753	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1754	return pLeaf;
1755
1756	/* Linear sub-leaf search. Lazy as usual. */
1757	cLeaves -= pLeaf - paLeaves;
1758	while ( cLeaves-- > 0
1759	&& pLeaf->uLeaf == uLeaf)
1760	{
1761	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1762	return pLeaf;
1763	pLeaf++;
1764	}
1765
1766	return NULL;
1767	}
1768
1769
1770	static void cpumR3ExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, PCPUMFEATURES pFeatures)
1771	{
1772	Assert(pVmxMsrs);
1773	Assert(pFeatures);
1774	Assert(pFeatures->fVmx);
1775
1776	/* Basic information. */
1777	bool const fVmxTrueMsrs = RT_BOOL(pVmxMsrs->u64Basic & VMX_BF_BASIC_TRUE_CTLS_MASK);
1778	{
1779	uint64_t const u64Basic = pVmxMsrs->u64Basic;
1780	pFeatures->fVmxInsOutInfo = RT_BF_GET(u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1781	}
1782
1783	/* Pin-based VM-execution controls. */
1784	{
1785	uint32_t const fPinCtls = fVmxTrueMsrs ? pVmxMsrs->TruePinCtls.n.allowed1 : pVmxMsrs->PinCtls.n.allowed1;
1786	pFeatures->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1787	pFeatures->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1788	pFeatures->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1789	pFeatures->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1790	pFeatures->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1791	}
1792
1793	/* Processor-based VM-execution controls. */
1794	{
1795	uint32_t const fProcCtls = fVmxTrueMsrs ? pVmxMsrs->TrueProcCtls.n.allowed1 : pVmxMsrs->ProcCtls.n.allowed1;
1796	pFeatures->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1797	pFeatures->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1798	pFeatures->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1799	pFeatures->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1800	pFeatures->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1801	pFeatures->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1802	pFeatures->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1803	pFeatures->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1804	pFeatures->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1805	pFeatures->fVmxTertiaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TERTIARY_CTLS);
1806	pFeatures->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1807	pFeatures->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1808	pFeatures->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1809	pFeatures->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1810	pFeatures->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1811	pFeatures->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1812	pFeatures->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1813	pFeatures->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1814	pFeatures->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1815	pFeatures->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1816	pFeatures->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1817	pFeatures->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1818	}
1819
1820	/* Secondary processor-based VM-execution controls. */
1821	{
1822	uint32_t const fProcCtls2 = pFeatures->fVmxSecondaryExecCtls ? pVmxMsrs->ProcCtls2.n.allowed1 : 0;
1823	pFeatures->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1824	pFeatures->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1825	pFeatures->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1826	pFeatures->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1827	pFeatures->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1828	pFeatures->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1829	pFeatures->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1830	pFeatures->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1831	pFeatures->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1832	pFeatures->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1833	pFeatures->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1834	pFeatures->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1835	pFeatures->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1836	pFeatures->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1837	pFeatures->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1838	pFeatures->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1839	pFeatures->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1840	pFeatures->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE);
1841	pFeatures->fVmxConcealVmxFromPt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1842	pFeatures->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1843	pFeatures->fVmxModeBasedExecuteEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1844	pFeatures->fVmxSppEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_SPP_EPT);
1845	pFeatures->fVmxPtEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PT_EPT);
1846	pFeatures->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1847	pFeatures->fVmxUserWaitPause = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1848	pFeatures->fVmxEnclvExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_ENCLV_EXIT);
1849	}
1850
1851	/* Tertiary processor-based VM-execution controls. */
1852	{
1853	uint64_t const fProcCtls3 = pFeatures->fVmxTertiaryExecCtls ? pVmxMsrs->u64ProcCtls3 : 0;
1854	pFeatures->fVmxLoadIwKeyExit = RT_BOOL(fProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT);
1855	}
1856
1857	/* VM-exit controls. */
1858	{
1859	uint32_t const fExitCtls = fVmxTrueMsrs ? pVmxMsrs->TrueExitCtls.n.allowed1 : pVmxMsrs->ExitCtls.n.allowed1;
1860	pFeatures->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1861	pFeatures->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1862	pFeatures->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1863	pFeatures->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1864	pFeatures->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1865	pFeatures->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1866	pFeatures->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1867	pFeatures->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1868	}
1869
1870	/* VM-entry controls. */
1871	{
1872	uint32_t const fEntryCtls = fVmxTrueMsrs ? pVmxMsrs->TrueEntryCtls.n.allowed1 : pVmxMsrs->EntryCtls.n.allowed1;
1873	pFeatures->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1874	pFeatures->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1875	pFeatures->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1876	pFeatures->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1877	}
1878
1879	/* Miscellaneous data. */
1880	{
1881	uint32_t const fMiscData = pVmxMsrs->u64Misc;
1882	pFeatures->fVmxExitSaveEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_SAVE_EFER_LMA);
1883	pFeatures->fVmxPt = RT_BOOL(fMiscData & VMX_MISC_INTEL_PT);
1884	pFeatures->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1885	pFeatures->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1886	}
1887	}
1888
1889
1890	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures)
1891	{
1892	Assert(pMsrs);
1893	RT_ZERO(*pFeatures);
1894	if (cLeaves >= 2)
1895	{
1896	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1897	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1898	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1899	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1900	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1901	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1902
1903	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1904	pStd0Leaf->uEbx,
1905	pStd0Leaf->uEcx,
1906	pStd0Leaf->uEdx);
1907	pFeatures->uFamily = RTX86GetCpuFamily(pStd1Leaf->uEax);
1908	pFeatures->uModel = RTX86GetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1909	pFeatures->uStepping = RTX86GetCpuStepping(pStd1Leaf->uEax);
1910	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1911	pFeatures->uFamily,
1912	pFeatures->uModel,
1913	pFeatures->uStepping);
1914
1915	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1916	if (pExtLeaf8)
1917	{
1918	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1919	pFeatures->cMaxLinearAddrWidth = (pExtLeaf8->uEax >> 8) & 0xff;
1920	}
1921	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1922	{
1923	pFeatures->cMaxPhysAddrWidth = 36;
1924	pFeatures->cMaxLinearAddrWidth = 36;
1925	}
1926	else
1927	{
1928	pFeatures->cMaxPhysAddrWidth = 32;
1929	pFeatures->cMaxLinearAddrWidth = 32;
1930	}
1931
1932	/* Standard features. */
1933	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1934	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1935	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1936	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1937	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1938	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1939	pFeatures->fPge = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PGE);
1940	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1941	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1942	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1943	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1944	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1945	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1946	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1947	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1948	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1949	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1950	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1951	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1952	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1953	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1954	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1955	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1956	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1957	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1958	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1959	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1960	if (pFeatures->fVmx)
1961	cpumR3ExplodeVmxFeatures(&pMsrs->hwvirt.vmx, pFeatures);
1962
1963	/* Structured extended features. */
1964	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1965	if (pSxfLeaf0)
1966	{
1967	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1968	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1969	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1970	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1971	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1972
1973	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1974	pFeatures->fIbrs = pFeatures->fIbpb;
1975	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1976	pFeatures->fFlushCmd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
1977	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1978	pFeatures->fMdsClear = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR);
1979	}
1980
1981	/* MWAIT/MONITOR leaf. */
1982	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1983	if (pMWaitLeaf)
1984	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1985	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1986
1987	/* Extended features. */
1988	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1989	if (pExtLeaf)
1990	{
1991	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1992	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1993	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1994	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1995	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1996	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1997	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1998	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1999	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
2000	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
2001	}
2002
2003	/* VMX (VMXON, VMCS region and related data structures) physical address width (depends on long-mode). */
2004	pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
2005
2006	if ( pExtLeaf
2007	&& ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
2008	\|\| pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON))
2009	{
2010	/* AMD features. */
2011	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
2012	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
2013	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
2014	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
2015	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
2016	pFeatures->fPge \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PGE);
2017	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
2018	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
2019	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
2020	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
2021	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
2022	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2023	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
2024	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
2025	if (pFeatures->fSvm)
2026	{
2027	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
2028	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
2029	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
2030	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
2031	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
2032	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
2033	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
2034	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
2035	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
2036	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
2037	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
2038	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
2039	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
2040	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
2041	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
2042	pFeatures->fSvmGmet = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_GMET);
2043	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
2044	}
2045	}
2046
2047	/*
2048	* Quirks.
2049	*/
2050	pFeatures->fLeakyFxSR = pExtLeaf
2051	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
2052	&& ( ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
2053	&& pFeatures->uFamily >= 6 /* K7 and up */)
2054	\|\| pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON);
2055
2056	/*
2057	* Max extended (/FPU) state.
2058	*/
2059	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
2060	if (pFeatures->fXSaveRstor)
2061	{
2062	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
2063	if (pXStateLeaf0)
2064	{
2065	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
2066	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
2067	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
2068	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
2069	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
2070	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
2071	{
2072	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
2073
2074	/* (paranoia:) */
2075	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
2076	if ( pXStateLeaf1
2077	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
2078	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
2079	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
2080	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
2081	}
2082	else
2083	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
2084	pFeatures->fXSaveRstor = 0);
2085	}
2086	else
2087	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
2088	pFeatures->fXSaveRstor = 0);
2089	}
2090	}
2091	else
2092	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
2093	return VINF_SUCCESS;
2094	}
2095
2096
2097	/*
2098	*
2099	* Init related code.
2100	* Init related code.
2101	* Init related code.
2102	*
2103	*
2104	*/
2105	#ifndef IN_VBOX_CPU_REPORT
2106
2107
2108	/**
2109	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
2110	*
2111	* This ignores the fSubLeafMask.
2112	*
2113	* @returns Pointer to the matching leaf, or NULL if not found.
2114	* @param pCpum The CPUM instance data.
2115	* @param uLeaf The leaf to locate.
2116	* @param uSubLeaf The subleaf to locate.
2117	*/
2118	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
2119	{
2120	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
2121	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
2122	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
2123	if (iEnd)
2124	{
2125	uint32_t iBegin = 0;
2126	for (;;)
2127	{
2128	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
2129	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
2130	if (uNeedle < uCur)
2131	{
2132	if (i > iBegin)
2133	iEnd = i;
2134	else
2135	break;
2136	}
2137	else if (uNeedle > uCur)
2138	{
2139	if (i + 1 < iEnd)
2140	iBegin = i + 1;
2141	else
2142	break;
2143	}
2144	else
2145	return &paLeaves[i];
2146	}
2147	}
2148	return NULL;
2149	}
2150
2151
2152	/**
2153	* Loads MSR range overrides.
2154	*
2155	* This must be called before the MSR ranges are moved from the normal heap to
2156	* the hyper heap!
2157	*
2158	* @returns VBox status code (VMSetError called).
2159	* @param pVM The cross context VM structure.
2160	* @param pMsrNode The CFGM node with the MSR overrides.
2161	*/
2162	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
2163	{
2164	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2165	{
2166	/*
2167	* Assemble a valid MSR range.
2168	*/
2169	CPUMMSRRANGE MsrRange;
2170	MsrRange.offCpumCpu = 0;
2171	MsrRange.fReserved = 0;
2172
2173	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
2174	if (RT_FAILURE(rc))
2175	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
2176
2177	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
2178	if (RT_FAILURE(rc))
2179	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
2180	MsrRange.szName, rc);
2181
2182	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
2183	if (RT_FAILURE(rc))
2184	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
2185	MsrRange.szName, rc);
2186
2187	char szType[32];
2188	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
2189	if (RT_FAILURE(rc))
2190	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
2191	MsrRange.szName, rc);
2192	if (!RTStrICmp(szType, "FixedValue"))
2193	{
2194	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
2195	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
2196
2197	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
2198	if (RT_FAILURE(rc))
2199	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
2200	MsrRange.szName, rc);
2201
2202	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
2203	if (RT_FAILURE(rc))
2204	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
2205	MsrRange.szName, rc);
2206
2207	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
2208	if (RT_FAILURE(rc))
2209	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
2210	MsrRange.szName, rc);
2211	}
2212	else
2213	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
2214	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
2215
2216	/*
2217	* Insert the range into the table (replaces/splits/shrinks existing
2218	* MSR ranges).
2219	*/
2220	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
2221	&MsrRange);
2222	if (RT_FAILURE(rc))
2223	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
2224	}
2225
2226	return VINF_SUCCESS;
2227	}
2228
2229
2230	/**
2231	* Loads CPUID leaf overrides.
2232	*
2233	* This must be called before the CPUID leaves are moved from the normal
2234	* heap to the hyper heap!
2235	*
2236	* @returns VBox status code (VMSetError called).
2237	* @param pVM The cross context VM structure.
2238	* @param pParentNode The CFGM node with the CPUID leaves.
2239	* @param pszLabel How to label the overrides we're loading.
2240	*/
2241	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2242	{
2243	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2244	{
2245	/*
2246	* Get the leaf and subleaf numbers.
2247	*/
2248	char szName[128];
2249	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2250	if (RT_FAILURE(rc))
2251	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2252
2253	/* The leaf number is either specified directly or thru the node name. */
2254	uint32_t uLeaf;
2255	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2256	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2257	{
2258	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2259	if (rc != VINF_SUCCESS)
2260	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2261	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2262	}
2263	else if (RT_FAILURE(rc))
2264	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2265	pszLabel, szName, rc);
2266
2267	uint32_t uSubLeaf;
2268	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2269	if (RT_FAILURE(rc))
2270	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2271	pszLabel, szName, rc);
2272
2273	uint32_t fSubLeafMask;
2274	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2275	if (RT_FAILURE(rc))
2276	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2277	pszLabel, szName, rc);
2278
2279	/*
2280	* Look up the specified leaf, since the output register values
2281	* defaults to any existing values. This allows overriding a single
2282	* register, without needing to know the other values.
2283	*/
2284	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2285	CPUMCPUIDLEAF Leaf;
2286	if (pLeaf)
2287	Leaf = *pLeaf;
2288	else
2289	RT_ZERO(Leaf);
2290	Leaf.uLeaf = uLeaf;
2291	Leaf.uSubLeaf = uSubLeaf;
2292	Leaf.fSubLeafMask = fSubLeafMask;
2293
2294	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2295	if (RT_FAILURE(rc))
2296	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2297	pszLabel, szName, rc);
2298	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2299	if (RT_FAILURE(rc))
2300	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2301	pszLabel, szName, rc);
2302	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2303	if (RT_FAILURE(rc))
2304	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2305	pszLabel, szName, rc);
2306	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2307	if (RT_FAILURE(rc))
2308	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2309	pszLabel, szName, rc);
2310
2311	/*
2312	* Insert the leaf into the table (replaces existing ones).
2313	*/
2314	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2315	&Leaf);
2316	if (RT_FAILURE(rc))
2317	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2318	}
2319
2320	return VINF_SUCCESS;
2321	}
2322
2323
2324
2325	/**
2326	* Fetches overrides for a CPUID leaf.
2327	*
2328	* @returns VBox status code.
2329	* @param pLeaf The leaf to load the overrides into.
2330	* @param pCfgNode The CFGM node containing the overrides
2331	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2332	* @param iLeaf The CPUID leaf number.
2333	*/
2334	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2335	{
2336	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2337	if (pLeafNode)
2338	{
2339	uint32_t u32;
2340	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2341	if (RT_SUCCESS(rc))
2342	pLeaf->uEax = u32;
2343	else
2344	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2345
2346	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2347	if (RT_SUCCESS(rc))
2348	pLeaf->uEbx = u32;
2349	else
2350	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2351
2352	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2353	if (RT_SUCCESS(rc))
2354	pLeaf->uEcx = u32;
2355	else
2356	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2357
2358	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2359	if (RT_SUCCESS(rc))
2360	pLeaf->uEdx = u32;
2361	else
2362	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2363
2364	}
2365	return VINF_SUCCESS;
2366	}
2367
2368
2369	/**
2370	* Load the overrides for a set of CPUID leaves.
2371	*
2372	* @returns VBox status code.
2373	* @param paLeaves The leaf array.
2374	* @param cLeaves The number of leaves.
2375	* @param uStart The start leaf number.
2376	* @param pCfgNode The CFGM node containing the overrides
2377	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2378	*/
2379	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2380	{
2381	for (uint32_t i = 0; i < cLeaves; i++)
2382	{
2383	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2384	if (RT_FAILURE(rc))
2385	return rc;
2386	}
2387
2388	return VINF_SUCCESS;
2389	}
2390
2391
2392	/**
2393	* Installs the CPUID leaves and explods the data into structures like
2394	* GuestFeatures and CPUMCTX::aoffXState.
2395	*
2396	* @returns VBox status code.
2397	* @param pVM The cross context VM structure.
2398	* @param pCpum The CPUM part of @a VM.
2399	* @param paLeaves The leaves. These will be copied (but not freed).
2400	* @param cLeaves The number of leaves.
2401	* @param pMsrs The MSRs.
2402	*/
2403	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
2404	{
2405	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2406
2407	/*
2408	* Install the CPUID information.
2409	*/
2410	AssertLogRelMsgReturn(cLeaves <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves),
2411	("cLeaves=%u - max %u\n", cLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves)),
2412	VERR_CPUM_IPE_1); /** @todo better status! */
2413	if (paLeaves != pCpum->GuestInfo.aCpuIdLeaves)
2414	memcpy(pCpum->GuestInfo.aCpuIdLeaves, paLeaves, cLeaves * sizeof(paLeaves[0]));
2415	pCpum->GuestInfo.paCpuIdLeavesR3 = pCpum->GuestInfo.aCpuIdLeaves;
2416	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2417
2418	/*
2419	* Update the default CPUID leaf if necessary.
2420	*/
2421	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2422	{
2423	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2424	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2425	{
2426	/* We don't use CPUID(0).eax here because of the NT hack that only
2427	changes that value without actually removing any leaves. */
2428	uint32_t i = 0;
2429	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2430	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2431	{
2432	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2433	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2434	i++;
2435	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2436	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2437	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2438	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2439	}
2440	break;
2441	}
2442	default:
2443	break;
2444	}
2445
2446	/*
2447	* Explode the guest CPU features.
2448	*/
2449	int rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
2450	&pCpum->GuestFeatures);
2451	AssertLogRelRCReturn(rc, rc);
2452
2453	/*
2454	* Adjust the scalable bus frequency according to the CPUID information
2455	* we're now using.
2456	*/
2457	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2458	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2459	? UINT64_C(100000000) /* 100MHz */
2460	: UINT64_C(133333333); /* 133MHz */
2461
2462	/*
2463	* Populate the legacy arrays. Currently used for everything, later only
2464	* for patch manager.
2465	*/
2466	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2467	{
2468	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2469	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2470	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2471	};
2472	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2473	{
2474	uint32_t cLeft = aOldRanges[i].cCpuIds;
2475	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2476	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2477	while (cLeft-- > 0)
2478	{
2479	uLeaf--;
2480	pLegacyLeaf--;
2481
2482	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2483	if (pLeaf)
2484	{
2485	pLegacyLeaf->uEax = pLeaf->uEax;
2486	pLegacyLeaf->uEbx = pLeaf->uEbx;
2487	pLegacyLeaf->uEcx = pLeaf->uEcx;
2488	pLegacyLeaf->uEdx = pLeaf->uEdx;
2489	}
2490	else
2491	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2492	}
2493	}
2494
2495	/*
2496	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2497	*/
2498	PVMCPU pVCpu0 = pVM->apCpusR3[0];
2499	AssertCompile(sizeof(pVCpu0->cpum.s.Guest.abXState) == CPUM_MAX_XSAVE_AREA_SIZE);
2500	memset(&pVCpu0->cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2501	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2502	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2503	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2504	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2505	{
2506	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2507	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2508	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2509	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2510	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2511	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2512	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2513	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2514	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2515	pCpum->GuestFeatures.cbMaxExtendedState),
2516	VERR_CPUM_IPE_1);
2517	pVCpu0->cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2518	}
2519
2520	/* Copy the CPU #0 data to the other CPUs. */
2521	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
2522	{
2523	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2524	memcpy(&pVCpu->cpum.s.Guest.aoffXState[0], &pVCpu0->cpum.s.Guest.aoffXState[0], sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2525	}
2526
2527	return VINF_SUCCESS;
2528	}
2529
2530
2531	/** @name Instruction Set Extension Options
2532	* @{ */
2533	/** Configuration option type (extended boolean, really). */
2534	typedef uint8_t CPUMISAEXTCFG;
2535	/** Always disable the extension. */
2536	#define CPUMISAEXTCFG_DISABLED false
2537	/** Enable the extension if it's supported by the host CPU. */
2538	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2539	/** Enable the extension if it's supported by the host CPU, but don't let
2540	* the portable CPUID feature disable it. */
2541	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2542	/** Always enable the extension. */
2543	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2544	/** @} */
2545
2546	/**
2547	* CPUID Configuration (from CFGM).
2548	*
2549	* @remarks The members aren't document since we would only be duplicating the
2550	* \@cfgm entries in cpumR3CpuIdReadConfig.
2551	*/
2552	typedef struct CPUMCPUIDCONFIG
2553	{
2554	bool fNt4LeafLimit;
2555	bool fInvariantTsc;
2556	bool fForceVme;
2557	bool fNestedHWVirt;
2558
2559	CPUMISAEXTCFG enmCmpXchg16b;
2560	CPUMISAEXTCFG enmMonitor;
2561	CPUMISAEXTCFG enmMWaitExtensions;
2562	CPUMISAEXTCFG enmSse41;
2563	CPUMISAEXTCFG enmSse42;
2564	CPUMISAEXTCFG enmAvx;
2565	CPUMISAEXTCFG enmAvx2;
2566	CPUMISAEXTCFG enmXSave;
2567	CPUMISAEXTCFG enmAesNi;
2568	CPUMISAEXTCFG enmPClMul;
2569	CPUMISAEXTCFG enmPopCnt;
2570	CPUMISAEXTCFG enmMovBe;
2571	CPUMISAEXTCFG enmRdRand;
2572	CPUMISAEXTCFG enmRdSeed;
2573	CPUMISAEXTCFG enmCLFlushOpt;
2574	CPUMISAEXTCFG enmFsGsBase;
2575	CPUMISAEXTCFG enmPcid;
2576	CPUMISAEXTCFG enmInvpcid;
2577	CPUMISAEXTCFG enmFlushCmdMsr;
2578	CPUMISAEXTCFG enmMdsClear;
2579	CPUMISAEXTCFG enmArchCapMsr;
2580
2581	CPUMISAEXTCFG enmAbm;
2582	CPUMISAEXTCFG enmSse4A;
2583	CPUMISAEXTCFG enmMisAlnSse;
2584	CPUMISAEXTCFG enm3dNowPrf;
2585	CPUMISAEXTCFG enmAmdExtMmx;
2586
2587	uint32_t uMaxStdLeaf;
2588	uint32_t uMaxExtLeaf;
2589	uint32_t uMaxCentaurLeaf;
2590	uint32_t uMaxIntelFamilyModelStep;
2591	char szCpuName[128];
2592	} CPUMCPUIDCONFIG;
2593	/** Pointer to CPUID config (from CFGM). */
2594	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2595
2596
2597	/**
2598	* Mini CPU selection support for making Mac OS X happy.
2599	*
2600	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2601	*
2602	* @param pCpum The CPUM instance data.
2603	* @param pConfig The CPUID configuration we've read from CFGM.
2604	*/
2605	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2606	{
2607	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2608	{
2609	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2610	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(RTX86GetCpuStepping(pStdFeatureLeaf->uEax),
2611	RTX86GetCpuModelIntel(pStdFeatureLeaf->uEax),
2612	RTX86GetCpuFamily(pStdFeatureLeaf->uEax),
2613	0);
2614	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2615	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2616	{
2617	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2618	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2619	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2620	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2621	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2622	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2623	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2624	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2625	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2626	pStdFeatureLeaf->uEax = uNew;
2627	}
2628	}
2629	}
2630
2631
2632
2633	/**
2634	* Limit it the number of entries, zapping the remainder.
2635	*
2636	* The limits are masking off stuff about power saving and similar, this
2637	* is perhaps a bit crudely done as there is probably some relatively harmless
2638	* info too in these leaves (like words about having a constant TSC).
2639	*
2640	* @param pCpum The CPUM instance data.
2641	* @param pConfig The CPUID configuration we've read from CFGM.
2642	*/
2643	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2644	{
2645	/*
2646	* Standard leaves.
2647	*/
2648	uint32_t uSubLeaf = 0;
2649	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2650	if (pCurLeaf)
2651	{
2652	uint32_t uLimit = pCurLeaf->uEax;
2653	if (uLimit <= UINT32_C(0x000fffff))
2654	{
2655	if (uLimit > pConfig->uMaxStdLeaf)
2656	{
2657	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2658	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2659	uLimit + 1, UINT32_C(0x000fffff));
2660	}
2661
2662	/* NT4 hack, no zapping of extra leaves here. */
2663	if (pConfig->fNt4LeafLimit && uLimit > 3)
2664	pCurLeaf->uEax = uLimit = 3;
2665
2666	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2667	pCurLeaf->uEax = uLimit;
2668	}
2669	else
2670	{
2671	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2672	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2673	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2674	}
2675	}
2676
2677	/*
2678	* Extended leaves.
2679	*/
2680	uSubLeaf = 0;
2681	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2682	if (pCurLeaf)
2683	{
2684	uint32_t uLimit = pCurLeaf->uEax;
2685	if ( uLimit >= UINT32_C(0x80000000)
2686	&& uLimit <= UINT32_C(0x800fffff))
2687	{
2688	if (uLimit > pConfig->uMaxExtLeaf)
2689	{
2690	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2691	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2692	uLimit + 1, UINT32_C(0x800fffff));
2693	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2694	pCurLeaf->uEax = uLimit;
2695	}
2696	}
2697	else
2698	{
2699	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2700	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2701	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2702	}
2703	}
2704
2705	/*
2706	* Centaur leaves (VIA).
2707	*/
2708	uSubLeaf = 0;
2709	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2710	if (pCurLeaf)
2711	{
2712	uint32_t uLimit = pCurLeaf->uEax;
2713	if ( uLimit >= UINT32_C(0xc0000000)
2714	&& uLimit <= UINT32_C(0xc00fffff))
2715	{
2716	if (uLimit > pConfig->uMaxCentaurLeaf)
2717	{
2718	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2719	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2720	uLimit + 1, UINT32_C(0xcfffffff));
2721	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2722	pCurLeaf->uEax = uLimit;
2723	}
2724	}
2725	else
2726	{
2727	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2728	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2729	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2730	}
2731	}
2732	}
2733
2734
2735	/**
2736	* Clears a CPUID leaf and all sub-leaves (to zero).
2737	*
2738	* @param pCpum The CPUM instance data.
2739	* @param uLeaf The leaf to clear.
2740	*/
2741	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2742	{
2743	uint32_t uSubLeaf = 0;
2744	PCPUMCPUIDLEAF pCurLeaf;
2745	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2746	{
2747	pCurLeaf->uEax = 0;
2748	pCurLeaf->uEbx = 0;
2749	pCurLeaf->uEcx = 0;
2750	pCurLeaf->uEdx = 0;
2751	uSubLeaf++;
2752	}
2753	}
2754
2755
2756	/**
2757	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2758	* the given leaf.
2759	*
2760	* @returns pLeaf.
2761	* @param pCpum The CPUM instance data.
2762	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2763	*/
2764	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2765	{
2766	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2767	if (pLeaf->fSubLeafMask != 0)
2768	{
2769	/*
2770	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2771	* Log everything while we're at it.
2772	*/
2773	LogRel(("CPUM:\n"
2774	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2775	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2776	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2777	for (;;)
2778	{
2779	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2780	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2781	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2782	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2783	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2784	break;
2785	pSubLeaf++;
2786	}
2787	LogRel(("CPUM:\n"));
2788
2789	/*
2790	* Remove the offending sub-leaves.
2791	*/
2792	if (pSubLeaf != pLeaf)
2793	{
2794	if (pSubLeaf != pLast)
2795	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2796	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2797	}
2798
2799	/*
2800	* Convert the first sub-leaf into a single leaf.
2801	*/
2802	pLeaf->uSubLeaf = 0;
2803	pLeaf->fSubLeafMask = 0;
2804	}
2805	return pLeaf;
2806	}
2807
2808
2809	/**
2810	* Sanitizes and adjust the CPUID leaves.
2811	*
2812	* Drop features that aren't virtualized (or virtualizable). Adjust information
2813	* and capabilities to fit the virtualized hardware. Remove information the
2814	* guest shouldn't have (because it's wrong in the virtual world or because it
2815	* gives away host details) or that we don't have documentation for and no idea
2816	* what means.
2817	*
2818	* @returns VBox status code.
2819	* @param pVM The cross context VM structure (for cCpus).
2820	* @param pCpum The CPUM instance data.
2821	* @param pConfig The CPUID configuration we've read from CFGM.
2822	*/
2823	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2824	{
2825	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2826	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2827	{ \
2828	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2829	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2830	}
2831	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2832	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2833	{ \
2834	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2835	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2836	}
2837	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2838	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2839	&& ((a_pLeafReg) & (fBitMask)) \
2840	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2841	{ \
2842	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2843	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2844	}
2845	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2846
2847	/* The CPUID entries we start with here isn't necessarily the ones of the host, so we
2848	must consult HostFeatures when processing CPUMISAEXTCFG variables. */
2849	PCCPUMFEATURES pHstFeat = &pCpum->HostFeatures;
2850	#define PASSTHRU_FEATURE(enmConfig, fHostFeature, fConst) \
2851	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) ? (fConst) : 0)
2852	#define PASSTHRU_FEATURE_EX(enmConfig, fHostFeature, fAndExpr, fConst) \
2853	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) && (fAndExpr) ? (fConst) : 0)
2854	#define PASSTHRU_FEATURE_TODO(enmConfig, fConst) ((enmConfig) ? (fConst) : 0)
2855
2856	/* Cpuid 1:
2857	* EAX: CPU model, family and stepping.
2858	*
2859	* ECX + EDX: Supported features. Only report features we can support.
2860	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2861	* options may require adjusting (i.e. stripping what was enabled).
2862	*
2863	* EBX: Branding, CLFLUSH line size, logical processors per package and
2864	* initial APIC ID.
2865	*/
2866	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2867	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2868	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2869
2870	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2871	\| X86_CPUID_FEATURE_EDX_VME
2872	\| X86_CPUID_FEATURE_EDX_DE
2873	\| X86_CPUID_FEATURE_EDX_PSE
2874	\| X86_CPUID_FEATURE_EDX_TSC
2875	\| X86_CPUID_FEATURE_EDX_MSR
2876	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2877	\| X86_CPUID_FEATURE_EDX_MCE
2878	\| X86_CPUID_FEATURE_EDX_CX8
2879	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2880	//\| RT_BIT_32(10) - not defined
2881	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2882	//\| X86_CPUID_FEATURE_EDX_SEP
2883	\| X86_CPUID_FEATURE_EDX_MTRR
2884	\| X86_CPUID_FEATURE_EDX_PGE
2885	\| X86_CPUID_FEATURE_EDX_MCA
2886	\| X86_CPUID_FEATURE_EDX_CMOV
2887	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2888	\| X86_CPUID_FEATURE_EDX_PSE36
2889	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2890	\| X86_CPUID_FEATURE_EDX_CLFSH
2891	//\| RT_BIT_32(20) - not defined
2892	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2893	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2894	\| X86_CPUID_FEATURE_EDX_MMX
2895	\| X86_CPUID_FEATURE_EDX_FXSR
2896	\| X86_CPUID_FEATURE_EDX_SSE
2897	\| X86_CPUID_FEATURE_EDX_SSE2
2898	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2899	\| X86_CPUID_FEATURE_EDX_HTT
2900	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2901	//\| RT_BIT_32(30) - not defined
2902	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2903	;
2904	pStdFeatureLeaf->uEcx &= X86_CPUID_FEATURE_ECX_SSE3
2905	\| PASSTHRU_FEATURE_TODO(pConfig->enmPClMul, X86_CPUID_FEATURE_ECX_PCLMUL)
2906	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2907	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2908	\| PASSTHRU_FEATURE_EX(pConfig->enmMonitor, pHstFeat->fMonitorMWait, pVM->cCpus == 1, X86_CPUID_FEATURE_ECX_MONITOR)
2909	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2910	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
2911	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2912	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2913	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2914	\| X86_CPUID_FEATURE_ECX_SSSE3
2915	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2916	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2917	\| PASSTHRU_FEATURE(pConfig->enmCmpXchg16b, pHstFeat->fMovCmpXchg16b, X86_CPUID_FEATURE_ECX_CX16)
2918	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2919	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2920	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2921	\| PASSTHRU_FEATURE(pConfig->enmPcid, pHstFeat->fPcid, X86_CPUID_FEATURE_ECX_PCID)
2922	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2923	\| PASSTHRU_FEATURE(pConfig->enmSse41, pHstFeat->fSse41, X86_CPUID_FEATURE_ECX_SSE4_1)
2924	\| PASSTHRU_FEATURE(pConfig->enmSse42, pHstFeat->fSse42, X86_CPUID_FEATURE_ECX_SSE4_2)
2925	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2926	\| PASSTHRU_FEATURE_TODO(pConfig->enmMovBe, X86_CPUID_FEATURE_ECX_MOVBE)
2927	\| PASSTHRU_FEATURE_TODO(pConfig->enmPopCnt, X86_CPUID_FEATURE_ECX_POPCNT)
2928	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2929	\| PASSTHRU_FEATURE_TODO(pConfig->enmAesNi, X86_CPUID_FEATURE_ECX_AES)
2930	\| PASSTHRU_FEATURE(pConfig->enmXSave, pHstFeat->fXSaveRstor, X86_CPUID_FEATURE_ECX_XSAVE)
2931	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2932	\| PASSTHRU_FEATURE(pConfig->enmAvx, pHstFeat->fAvx, X86_CPUID_FEATURE_ECX_AVX)
2933	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2934	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdRand, X86_CPUID_FEATURE_ECX_RDRAND)
2935	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2936	;
2937
2938	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2939	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2940	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2941	{
2942	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2943	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2944	}
2945
2946	if (pCpum->u8PortableCpuIdLevel > 0)
2947	{
2948	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2949	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2950	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2951	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2952	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2953	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2954	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2955	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
2956	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2957	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2958	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2959	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2960	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2961	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2962	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2963	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2964	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2965	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2966	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2967	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2968
2969	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2970	\| X86_CPUID_FEATURE_EDX_PSN
2971	\| X86_CPUID_FEATURE_EDX_DS
2972	\| X86_CPUID_FEATURE_EDX_ACPI
2973	\| X86_CPUID_FEATURE_EDX_SS
2974	\| X86_CPUID_FEATURE_EDX_TM
2975	\| X86_CPUID_FEATURE_EDX_PBE
2976	)));
2977	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2978	\| X86_CPUID_FEATURE_ECX_CPLDS
2979	\| X86_CPUID_FEATURE_ECX_AES
2980	\| X86_CPUID_FEATURE_ECX_VMX
2981	\| X86_CPUID_FEATURE_ECX_SMX
2982	\| X86_CPUID_FEATURE_ECX_EST
2983	\| X86_CPUID_FEATURE_ECX_TM2
2984	\| X86_CPUID_FEATURE_ECX_CNTXID
2985	\| X86_CPUID_FEATURE_ECX_FMA
2986	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2987	\| X86_CPUID_FEATURE_ECX_PDCM
2988	\| X86_CPUID_FEATURE_ECX_DCA
2989	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2990	)));
2991	}
2992
2993	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2994	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2995
2996	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2997	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2998	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2999	*/
3000	#ifdef VBOX_WITH_MULTI_CORE
3001	if (pVM->cCpus > 1)
3002	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
3003	#endif
3004	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
3005	{
3006	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
3007	core times the number of CPU cores per processor */
3008	#ifdef VBOX_WITH_MULTI_CORE
3009	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
3010	#else
3011	/* Single logical processor in a package. */
3012	pStdFeatureLeaf->uEbx \|= (1 << 16);
3013	#endif
3014	}
3015
3016	uint32_t uMicrocodeRev;
3017	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
3018	if (RT_SUCCESS(rc))
3019	{
3020	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
3021	}
3022	else
3023	{
3024	uMicrocodeRev = 0;
3025	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
3026	}
3027
3028	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
3029	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
3030	*/
3031	if ( ( pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen
3032	/** @todo The following ASSUMES that Hygon uses the same version numbering
3033	* as AMD and that they shipped buggy firmware. */
3034	\|\| pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Hygon_Dhyana)
3035	&& uMicrocodeRev < 0x8001126
3036	&& !pConfig->fForceVme)
3037	{
3038	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
3039	LogRel(("CPUM: Zen VME workaround engaged\n"));
3040	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
3041	}
3042
3043	/* Force standard feature bits. */
3044	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
3045	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
3046	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
3047	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
3048	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
3049	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
3050	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3051	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
3052	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3053	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
3054	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
3055	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
3056	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3057	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
3058	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
3059	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
3060	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
3061	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
3062	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3063	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
3064	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
3065	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
3066
3067	pStdFeatureLeaf = NULL; /* Must refetch! */
3068
3069	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
3070	* AMD:
3071	* EAX: CPU model, family and stepping.
3072	*
3073	* ECX + EDX: Supported features. Only report features we can support.
3074	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3075	* options may require adjusting (i.e. stripping what was enabled).
3076	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
3077	*
3078	* EBX: Branding ID and package type (or reserved).
3079	*
3080	* Intel and probably most others:
3081	* EAX: 0
3082	* EBX: 0
3083	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
3084	*/
3085	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3086	if (pExtFeatureLeaf)
3087	{
3088	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
3089
3090	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
3091	\| X86_CPUID_AMD_FEATURE_EDX_VME
3092	\| X86_CPUID_AMD_FEATURE_EDX_DE
3093	\| X86_CPUID_AMD_FEATURE_EDX_PSE
3094	\| X86_CPUID_AMD_FEATURE_EDX_TSC
3095	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
3096	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
3097	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
3098	\| X86_CPUID_AMD_FEATURE_EDX_CX8
3099	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
3100	//\| RT_BIT_32(10) - reserved
3101	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
3102	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
3103	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3104	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
3105	\| X86_CPUID_AMD_FEATURE_EDX_PGE
3106	\| X86_CPUID_AMD_FEATURE_EDX_MCA
3107	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
3108	\| X86_CPUID_AMD_FEATURE_EDX_PAT
3109	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
3110	//\| RT_BIT_32(18) - reserved
3111	//\| RT_BIT_32(19) - reserved
3112	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
3113	//\| RT_BIT_32(21) - reserved
3114	\| PASSTHRU_FEATURE(pConfig->enmAmdExtMmx, pHstFeat->fAmdMmxExts, X86_CPUID_AMD_FEATURE_EDX_AXMMX)
3115	\| X86_CPUID_AMD_FEATURE_EDX_MMX
3116	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
3117	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
3118	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3119	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
3120	//\| RT_BIT_32(28) - reserved
3121	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
3122	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
3123	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
3124	;
3125	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
3126	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
3127	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
3128	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3129	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
3130	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
3131	\| PASSTHRU_FEATURE_TODO(pConfig->enmAbm, X86_CPUID_AMD_FEATURE_ECX_ABM)
3132	\| PASSTHRU_FEATURE_TODO(pConfig->enmSse4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A)
3133	\| PASSTHRU_FEATURE_TODO(pConfig->enmMisAlnSse, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE)
3134	\| PASSTHRU_FEATURE(pConfig->enm3dNowPrf, pHstFeat->f3DNowPrefetch, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
3135	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3136	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
3137	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
3138	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3139	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
3140	//\| RT_BIT_32(14) - reserved
3141	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
3142	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
3143	//\| RT_BIT_32(17) - reserved
3144	//\| RT_BIT_32(18) - reserved
3145	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
3146	//\| RT_BIT_32(20) - reserved
3147	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
3148	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
3149	//\| RT_BIT_32(23) - reserved
3150	//\| RT_BIT_32(24) - reserved
3151	//\| RT_BIT_32(25) - reserved
3152	//\| RT_BIT_32(26) - reserved
3153	//\| RT_BIT_32(27) - reserved
3154	//\| RT_BIT_32(28) - reserved
3155	//\| RT_BIT_32(29) - reserved
3156	//\| RT_BIT_32(30) - reserved
3157	//\| RT_BIT_32(31) - reserved
3158	;
3159	#ifdef VBOX_WITH_MULTI_CORE
3160	if ( pVM->cCpus > 1
3161	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3162	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3163	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
3164	#endif
3165
3166	if (pCpum->u8PortableCpuIdLevel > 0)
3167	{
3168	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
3169	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
3170	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
3171	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
3172	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
3173	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
3174	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
3175	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
3176	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
3177	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
3178	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
3179	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
3180	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
3181	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
3182	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
3183	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
3184
3185	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
3186	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3187	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3188	\| X86_CPUID_AMD_FEATURE_ECX_IBS
3189	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3190	\| X86_CPUID_AMD_FEATURE_ECX_WDT
3191	\| X86_CPUID_AMD_FEATURE_ECX_LWP
3192	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
3193	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
3194	\| UINT32_C(0xff964000)
3195	)));
3196	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
3197	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3198	\| RT_BIT(18)
3199	\| RT_BIT(19)
3200	\| RT_BIT(21)
3201	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
3202	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3203	\| RT_BIT(28)
3204	)));
3205	}
3206
3207	/* Force extended feature bits. */
3208	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
3209	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
3210	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
3211	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
3212	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
3213	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
3214	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
3215	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
3216	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3217	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
3218	}
3219	pExtFeatureLeaf = NULL; /* Must refetch! */
3220
3221
3222	/* Cpuid 2:
3223	* Intel: (Nondeterministic) Cache and TLB information
3224	* AMD: Reserved
3225	* VIA: Reserved
3226	* Safe to expose.
3227	*/
3228	uint32_t uSubLeaf = 0;
3229	PCPUMCPUIDLEAF pCurLeaf;
3230	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
3231	{
3232	if ((pCurLeaf->uEax & 0xff) > 1)
3233	{
3234	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
3235	pCurLeaf->uEax &= UINT32_C(0xffffff01);
3236	}
3237	uSubLeaf++;
3238	}
3239
3240	/* Cpuid 3:
3241	* Intel: EAX, EBX - reserved (transmeta uses these)
3242	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3243	* AMD: Reserved
3244	* VIA: Reserved
3245	* Safe to expose
3246	*/
3247	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3248	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3249	{
3250	uSubLeaf = 0;
3251	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3252	{
3253	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3254	if (pCpum->u8PortableCpuIdLevel > 0)
3255	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3256	uSubLeaf++;
3257	}
3258	}
3259
3260	/* Cpuid 4 + ECX:
3261	* Intel: Deterministic Cache Parameters Leaf.
3262	* AMD: Reserved
3263	* VIA: Reserved
3264	* Safe to expose, except for EAX:
3265	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3266	* Bits 31-26: Maximum number of processor cores in this physical package**
3267	* Note: These SMP values are constant regardless of ECX
3268	*/
3269	uSubLeaf = 0;
3270	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3271	{
3272	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3273	#ifdef VBOX_WITH_MULTI_CORE
3274	if ( pVM->cCpus > 1
3275	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3276	{
3277	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3278	/* One logical processor with possibly multiple cores. */
3279	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3280	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3281	}
3282	#endif
3283	uSubLeaf++;
3284	}
3285
3286	/* Cpuid 5: Monitor/mwait Leaf
3287	* Intel: ECX, EDX - reserved
3288	* EAX, EBX - Smallest and largest monitor line size
3289	* AMD: EDX - reserved
3290	* EAX, EBX - Smallest and largest monitor line size
3291	* ECX - extensions (ignored for now)
3292	* VIA: Reserved
3293	* Safe to expose
3294	*/
3295	uSubLeaf = 0;
3296	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3297	{
3298	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3299	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3300	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3301
3302	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3303	if (pConfig->enmMWaitExtensions)
3304	{
3305	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3306	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3307	it shall be part of our power management virtualization model */
3308	#if 0
3309	/* MWAIT sub C-states */
3310	pCurLeaf->uEdx =
3311	(0 << 0) /* 0 in C0 */ \|
3312	(2 << 4) /* 2 in C1 */ \|
3313	(2 << 8) /* 2 in C2 */ \|
3314	(2 << 12) /* 2 in C3 */ \|
3315	(0 << 16) /* 0 in C4 */
3316	;
3317	#endif
3318	}
3319	else
3320	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3321	uSubLeaf++;
3322	}
3323
3324	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3325	* Intel: Various stuff.
3326	* AMD: EAX, EBX, EDX - reserved.
3327	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3328	* present. Same as intel.
3329	* VIA: ??
3330	*
3331	* We clear everything here for now.
3332	*/
3333	cpumR3CpuIdZeroLeaf(pCpum, 6);
3334
3335	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3336	* EAX: Number of sub leaves.
3337	* EBX+ECX+EDX: Feature flags
3338	*
3339	* We only have documentation for one sub-leaf, so clear all other (no need
3340	* to remove them as such, just set them to zero).
3341	*
3342	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3343	* options may require adjusting (i.e. stripping what was enabled).
3344	*/
3345	uSubLeaf = 0;
3346	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3347	{
3348	switch (uSubLeaf)
3349	{
3350	case 0:
3351	{
3352	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3353	pCurLeaf->uEbx &= 0
3354	\| PASSTHRU_FEATURE(pConfig->enmFsGsBase, pHstFeat->fFsGsBase, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE)
3355	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3356	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3357	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3358	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3359	\| PASSTHRU_FEATURE(pConfig->enmAvx2, pHstFeat->fAvx2, X86_CPUID_STEXT_FEATURE_EBX_AVX2)
3360	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3361	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3362	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3363	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3364	\| PASSTHRU_FEATURE(pConfig->enmInvpcid, pHstFeat->fInvpcid, X86_CPUID_STEXT_FEATURE_EBX_INVPCID)
3365	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3366	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3367	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3368	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3369	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3370	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3371	//\| RT_BIT(17) - reserved
3372	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdSeed, X86_CPUID_STEXT_FEATURE_EBX_RDSEED)
3373	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3374	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3375	//\| RT_BIT(21) - reserved
3376	//\| RT_BIT(22) - reserved
3377	\| PASSTHRU_FEATURE(pConfig->enmCLFlushOpt, pHstFeat->fClFlushOpt, X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT)
3378	//\| RT_BIT(24) - reserved
3379	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3380	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3381	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3382	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3383	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3384	//\| RT_BIT(30) - reserved
3385	//\| RT_BIT(31) - reserved
3386	;
3387	pCurLeaf->uEcx &= 0
3388	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3389	;
3390	pCurLeaf->uEdx &= 0
3391	\| PASSTHRU_FEATURE(pConfig->enmMdsClear, pHstFeat->fMdsClear, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR)
3392	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3393	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3394	\| PASSTHRU_FEATURE(pConfig->enmFlushCmdMsr, pHstFeat->fFlushCmd, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD)
3395	\| PASSTHRU_FEATURE(pConfig->enmArchCapMsr, pHstFeat->fArchCap, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
3396	;
3397
3398	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3399	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3400	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3401	{
3402	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3403	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3404	}
3405
3406	if (pCpum->u8PortableCpuIdLevel > 0)
3407	{
3408	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3409	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3410	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3411	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3412	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3413	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3414	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3415	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3416	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3417	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3418	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3419	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3420	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3421	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3422	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3423	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
3424	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
3425	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
3426	}
3427
3428	/* Dependencies. */
3429	if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
3430	pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3431
3432	/* Force standard feature bits. */
3433	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3434	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3435	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3436	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3437	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3438	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3439	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3440	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3441	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3442	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3443	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3444	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
3445	if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
3446	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3447	if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3448	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
3449	break;
3450	}
3451
3452	default:
3453	/* Invalid index, all values are zero. */
3454	pCurLeaf->uEax = 0;
3455	pCurLeaf->uEbx = 0;
3456	pCurLeaf->uEcx = 0;
3457	pCurLeaf->uEdx = 0;
3458	break;
3459	}
3460	uSubLeaf++;
3461	}
3462
3463	/* Cpuid 8: Marked as reserved by Intel and AMD.
3464	* We zero this since we don't know what it may have been used for.
3465	*/
3466	cpumR3CpuIdZeroLeaf(pCpum, 8);
3467
3468	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3469	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3470	* EBX, ECX, EDX - reserved.
3471	* AMD: Reserved
3472	* VIA: ??
3473	*
3474	* We zero this.
3475	*/
3476	cpumR3CpuIdZeroLeaf(pCpum, 9);
3477
3478	/* Cpuid 0xa: Architectural Performance Monitor Features
3479	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3480	* EBX, ECX, EDX - reserved.
3481	* AMD: Reserved
3482	* VIA: ??
3483	*
3484	* We zero this, for now at least.
3485	*/
3486	cpumR3CpuIdZeroLeaf(pCpum, 10);
3487
3488	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3489	* Intel: EAX - APCI ID shift right for next level.
3490	* EBX - Factory configured cores/threads at this level.
3491	* ECX - Level number (same as input) and level type (1,2,0).
3492	* EDX - Extended initial APIC ID.
3493	* AMD: Reserved
3494	* VIA: ??
3495	*/
3496	uSubLeaf = 0;
3497	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3498	{
3499	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3500	{
3501	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3502	if (bLevelType == 1)
3503	{
3504	/* Thread level - we don't do threads at the moment. */
3505	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3506	pCurLeaf->uEbx = 1;
3507	}
3508	else if (bLevelType == 2)
3509	{
3510	/* Core level. */
3511	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3512	#ifdef VBOX_WITH_MULTI_CORE
3513	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3514	pCurLeaf->uEax++;
3515	#endif
3516	pCurLeaf->uEbx = pVM->cCpus;
3517	}
3518	else
3519	{
3520	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3521	pCurLeaf->uEax = 0;
3522	pCurLeaf->uEbx = 0;
3523	pCurLeaf->uEcx = 0;
3524	}
3525	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3526	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3527	}
3528	else
3529	{
3530	pCurLeaf->uEax = 0;
3531	pCurLeaf->uEbx = 0;
3532	pCurLeaf->uEcx = 0;
3533	pCurLeaf->uEdx = 0;
3534	}
3535	uSubLeaf++;
3536	}
3537
3538	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3539	* We zero this since we don't know what it may have been used for.
3540	*/
3541	cpumR3CpuIdZeroLeaf(pCpum, 12);
3542
3543	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3544	* ECX=0: EAX - Valid bits in XCR0[31:0].
3545	* EBX - Maximum state size as per current XCR0 value.
3546	* ECX - Maximum state size for all supported features.
3547	* EDX - Valid bits in XCR0[63:32].
3548	* ECX=1: EAX - Various X-features.
3549	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3550	* ECX - Valid bits in IA32_XSS[31:0].
3551	* EDX - Valid bits in IA32_XSS[63:32].
3552	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3553	* if the bit invalid all four registers are set to zero.
3554	* EAX - The state size for this feature.
3555	* EBX - The state byte offset of this feature.
3556	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3557	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3558	*
3559	* Clear them all as we don't currently implement extended CPU state.
3560	*/
3561	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3562	uint64_t fGuestXcr0Mask = 0;
3563	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3564	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3565	{
3566	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3567	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3568	fGuestXcr0Mask \|= XSAVE_C_YMM;
3569	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3570	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3571	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3572	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3573
3574	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3575	}
3576	pStdFeatureLeaf = NULL;
3577	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3578
3579	/* Work the sub-leaves. */
3580	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3581	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3582	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3583	{
3584	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3585	if (pCurLeaf)
3586	{
3587	if (fGuestXcr0Mask)
3588	{
3589	switch (uSubLeaf)
3590	{
3591	case 0:
3592	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3593	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3594	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3595	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3596	VERR_CPUM_IPE_1);
3597	cbXSaveMaxActual = pCurLeaf->uEcx;
3598	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3599	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3600	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3601	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3602	VERR_CPUM_IPE_2);
3603	continue;
3604	case 1:
3605	pCurLeaf->uEax &= 0;
3606	pCurLeaf->uEcx &= 0;
3607	pCurLeaf->uEdx &= 0;
3608	/** @todo what about checking ebx? */
3609	continue;
3610	default:
3611	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3612	{
3613	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3614	&& pCurLeaf->uEax > 0
3615	&& pCurLeaf->uEbx < cbXSaveMaxActual
3616	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3617	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3618	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3619	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3620	VERR_CPUM_IPE_2);
3621	AssertLogRel(!(pCurLeaf->uEcx & 1));
3622	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3623	pCurLeaf->uEdx = 0; /* it's reserved... */
3624	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3625	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3626	continue;
3627	}
3628	break;
3629	}
3630	}
3631
3632	/* Clear the leaf. */
3633	pCurLeaf->uEax = 0;
3634	pCurLeaf->uEbx = 0;
3635	pCurLeaf->uEcx = 0;
3636	pCurLeaf->uEdx = 0;
3637	}
3638	}
3639
3640	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3641	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3642	{
3643	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3644	if (pCurLeaf)
3645	{
3646	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3647	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3648	pCurLeaf->uEbx = cbXSaveMaxReport;
3649	pCurLeaf->uEcx = cbXSaveMaxReport;
3650	}
3651	}
3652
3653	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3654	* We zero this since we don't know what it may have been used for.
3655	*/
3656	cpumR3CpuIdZeroLeaf(pCpum, 14);
3657
3658	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3659	* also known as Intel Resource Director Technology (RDT) Monitoring
3660	* We zero this as we don't currently virtualize PQM.
3661	*/
3662	cpumR3CpuIdZeroLeaf(pCpum, 15);
3663
3664	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3665	* also known as Intel Resource Director Technology (RDT) Allocation
3666	* We zero this as we don't currently virtualize PQE.
3667	*/
3668	cpumR3CpuIdZeroLeaf(pCpum, 16);
3669
3670	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3671	* We zero this since we don't know what it may have been used for.
3672	*/
3673	cpumR3CpuIdZeroLeaf(pCpum, 17);
3674
3675	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3676	* We zero this as we don't currently virtualize this.
3677	*/
3678	cpumR3CpuIdZeroLeaf(pCpum, 18);
3679
3680	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3681	* We zero this since we don't know what it may have been used for.
3682	*/
3683	cpumR3CpuIdZeroLeaf(pCpum, 19);
3684
3685	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3686	* We zero this as we don't currently virtualize this.
3687	*/
3688	cpumR3CpuIdZeroLeaf(pCpum, 20);
3689
3690	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3691	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3692	* EAX - denominator (unsigned).
3693	* EBX - numerator (unsigned).
3694	* ECX, EDX - reserved.
3695	* AMD: Reserved / undefined / not implemented.
3696	* VIA: Reserved / undefined / not implemented.
3697	* We zero this as we don't currently virtualize this.
3698	*/
3699	cpumR3CpuIdZeroLeaf(pCpum, 21);
3700
3701	/* Cpuid 0x16: Processor frequency info
3702	* Intel: EAX - Core base frequency in MHz.
3703	* EBX - Core maximum frequency in MHz.
3704	* ECX - Bus (reference) frequency in MHz.
3705	* EDX - Reserved.
3706	* AMD: Reserved / undefined / not implemented.
3707	* VIA: Reserved / undefined / not implemented.
3708	* We zero this as we don't currently virtualize this.
3709	*/
3710	cpumR3CpuIdZeroLeaf(pCpum, 22);
3711
3712	/* Cpuid 0x17..0x10000000: Unknown.
3713	* We don't know these and what they mean, so remove them. */
3714	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3715	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3716
3717
3718	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3719	* We remove all these as we're a hypervisor and must provide our own.
3720	*/
3721	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3722	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3723
3724
3725	/* Cpuid 0x80000000 is harmless. */
3726
3727	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3728
3729	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3730
3731	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3732	* Safe to pass on to the guest.
3733	*
3734	* AMD: 0x800000005 L1 cache information
3735	* 0x800000006 L2/L3 cache information
3736	* Intel: 0x800000005 reserved
3737	* 0x800000006 L2 cache information
3738	* VIA: 0x800000005 TLB and L1 cache information
3739	* 0x800000006 L2 cache information
3740	*/
3741
3742	/* Cpuid 0x800000007: Advanced Power Management Information.
3743	* AMD: EAX: Processor feedback capabilities.
3744	* EBX: RAS capabilites.
3745	* ECX: Advanced power monitoring interface.
3746	* EDX: Enhanced power management capabilities.
3747	* Intel: EAX, EBX, ECX - reserved.
3748	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3749	* VIA: Reserved
3750	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3751	*/
3752	uSubLeaf = 0;
3753	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3754	{
3755	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3756	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3757	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3758	{
3759	/*
3760	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3761	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3762	* bit is now configurable.
3763	*/
3764	pCurLeaf->uEdx &= 0
3765	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3766	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3767	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3768	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3769	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3770	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3771	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3772	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3773	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3774	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3775	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3776	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3777	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3778	\| 0;
3779	}
3780	else
3781	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3782	if (!pConfig->fInvariantTsc)
3783	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3784	uSubLeaf++;
3785	}
3786
3787	/* Cpuid 0x80000008:
3788	* AMD: EBX, EDX - reserved
3789	* EAX: Virtual/Physical/Guest address Size
3790	* ECX: Number of cores + APICIdCoreIdSize
3791	* Intel: EAX: Virtual/Physical address Size
3792	* EBX, ECX, EDX - reserved
3793	* VIA: EAX: Virtual/Physical address Size
3794	* EBX, ECX, EDX - reserved
3795	*
3796	* We only expose the virtual+pysical address size to the guest atm.
3797	* On AMD we set the core count, but not the apic id stuff as we're
3798	* currently not doing the apic id assignments in a complatible manner.
3799	*/
3800	uSubLeaf = 0;
3801	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3802	{
3803	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3804	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3805	pCurLeaf->uEdx = 0; /* reserved */
3806
3807	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3808	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3809	pCurLeaf->uEcx = 0;
3810	#ifdef VBOX_WITH_MULTI_CORE
3811	if ( pVM->cCpus > 1
3812	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3813	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3814	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3815	#endif
3816	uSubLeaf++;
3817	}
3818
3819	/* Cpuid 0x80000009: Reserved
3820	* We zero this since we don't know what it may have been used for.
3821	*/
3822	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3823
3824	/* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
3825	* AMD: EAX - SVM revision.
3826	* EBX - Number of ASIDs.
3827	* ECX - Reserved.
3828	* EDX - SVM Feature identification.
3829	*/
3830	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3831	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3832	{
3833	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3834	if ( pExtFeatureLeaf
3835	&& (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM))
3836	{
3837	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3838	if (pSvmFeatureLeaf)
3839	{
3840	pSvmFeatureLeaf->uEax = 0x1;
3841	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3842	pSvmFeatureLeaf->uEcx = 0;
3843	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3844	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3845	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3846	}
3847	else
3848	{
3849	/* Should never happen. */
3850	LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
3851	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3852	}
3853	}
3854	else
3855	{
3856	/* If SVM is not supported, this is reserved, zero out. */
3857	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3858	}
3859	}
3860	else
3861	{
3862	/* Cpuid 0x8000000a: Reserved on Intel.
3863	* We zero this since we don't know what it may have been used for.
3864	*/
3865	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3866	}
3867
3868	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3869	* We clear these as we don't know what purpose they might have. */
3870	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3871	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3872
3873	/* Cpuid 0x80000019: TLB configuration
3874	* Seems to be harmless, pass them thru as is. */
3875
3876	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3877	* Strip anything we don't know what is or addresses feature we don't implement. */
3878	uSubLeaf = 0;
3879	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3880	{
3881	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3882	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3883	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3884	;
3885	pCurLeaf->uEbx = 0; /* reserved */
3886	pCurLeaf->uEcx = 0; /* reserved */
3887	pCurLeaf->uEdx = 0; /* reserved */
3888	uSubLeaf++;
3889	}
3890
3891	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3892	* Clear this as we don't currently virtualize this feature. */
3893	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3894
3895	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3896	* Clear this as we don't currently virtualize this feature. */
3897	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3898
3899	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3900	* We need to sanitize the cores per cache (EAX[25:14]).
3901	*
3902	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3903	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3904	* slightly different meaning.
3905	*/
3906	uSubLeaf = 0;
3907	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3908	{
3909	#ifdef VBOX_WITH_MULTI_CORE
3910	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3911	if (cCores > pVM->cCpus)
3912	cCores = pVM->cCpus;
3913	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3914	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3915	#else
3916	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3917	#endif
3918	uSubLeaf++;
3919	}
3920
3921	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3922	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3923	* setup, we have one compute unit with all the cores in it. Single node.
3924	*/
3925	uSubLeaf = 0;
3926	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3927	{
3928	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3929	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3930	{
3931	#ifdef VBOX_WITH_MULTI_CORE
3932	pCurLeaf->uEbx = pVM->cCpus < 0x100
3933	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3934	#else
3935	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3936	#endif
3937	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3938	}
3939	else
3940	{
3941	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3942	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_HYGON);
3943	pCurLeaf->uEbx = 0; /* Reserved. */
3944	pCurLeaf->uEcx = 0; /* Reserved. */
3945	}
3946	pCurLeaf->uEdx = 0; /* Reserved. */
3947	uSubLeaf++;
3948	}
3949
3950	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3951	* We don't know these and what they mean, so remove them. */
3952	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3953	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3954
3955	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3956	* Just pass it thru for now. */
3957
3958	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3959	* Just pass it thru for now. */
3960
3961	/* Cpuid 0xc0000000: Centaur stuff.
3962	* Harmless, pass it thru. */
3963
3964	/* Cpuid 0xc0000001: Centaur features.
3965	* VIA: EAX - Family, model, stepping.
3966	* EDX - Centaur extended feature flags. Nothing interesting, except may
3967	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3968	* EBX, ECX - reserved.
3969	* We keep EAX but strips the rest.
3970	*/
3971	uSubLeaf = 0;
3972	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3973	{
3974	pCurLeaf->uEbx = 0;
3975	pCurLeaf->uEcx = 0;
3976	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3977	uSubLeaf++;
3978	}
3979
3980	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3981	* We only have fixed stale values, but should be harmless. */
3982
3983	/* Cpuid 0xc0000003: Reserved.
3984	* We zero this since we don't know what it may have been used for.
3985	*/
3986	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3987
3988	/* Cpuid 0xc0000004: Centaur Performance Info.
3989	* We only have fixed stale values, but should be harmless. */
3990
3991
3992	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3993	* We don't know these and what they mean, so remove them. */
3994	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3995	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3996
3997	return VINF_SUCCESS;
3998	#undef PORTABLE_DISABLE_FEATURE_BIT
3999	#undef PORTABLE_CLEAR_BITS_WHEN
4000	}
4001
4002
4003	/**
4004	* Reads a value in /CPUM/IsaExts/ node.
4005	*
4006	* @returns VBox status code (error message raised).
4007	* @param pVM The cross context VM structure. (For errors.)
4008	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4009	* @param pszValueName The value / extension name.
4010	* @param penmValue Where to return the choice.
4011	* @param enmDefault The default choice.
4012	*/
4013	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
4014	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
4015	{
4016	/*
4017	* Try integer encoding first.
4018	*/
4019	uint64_t uValue;
4020	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
4021	if (RT_SUCCESS(rc))
4022	switch (uValue)
4023	{
4024	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
4025	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
4026	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
4027	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
4028	default:
4029	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
4030	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
4031	pszValueName, uValue);
4032	}
4033	/*
4034	* If missing, use default.
4035	*/
4036	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
4037	*penmValue = enmDefault;
4038	else
4039	{
4040	if (rc == VERR_CFGM_NOT_INTEGER)
4041	{
4042	/*
4043	* Not an integer, try read it as a string.
4044	*/
4045	char szValue[32];
4046	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
4047	if (RT_SUCCESS(rc))
4048	{
4049	RTStrToLower(szValue);
4050	size_t cchValue = strlen(szValue);
4051	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
4052	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
4053	*penmValue = CPUMISAEXTCFG_DISABLED;
4054	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
4055	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
4056	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
4057	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
4058	else if (EQ("portable"))
4059	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
4060	else if (EQ("default") \|\| EQ("def"))
4061	*penmValue = enmDefault;
4062	else
4063	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
4064	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
4065	pszValueName, uValue);
4066	#undef EQ
4067	}
4068	}
4069	if (RT_FAILURE(rc))
4070	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
4071	}
4072	return VINF_SUCCESS;
4073	}
4074
4075
4076	/**
4077	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
4078	*
4079	* @returns VBox status code (error message raised).
4080	* @param pVM The cross context VM structure. (For errors.)
4081	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4082	* @param pszValueName The value / extension name.
4083	* @param penmValue Where to return the choice.
4084	* @param enmDefault The default choice.
4085	* @param fAllowed Allowed choice. Applied both to the result and to
4086	* the default value.
4087	*/
4088	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
4089	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
4090	{
4091	int rc;
4092	if (fAllowed)
4093	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4094	else
4095	{
4096	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
4097	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
4098	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
4099	*penmValue = CPUMISAEXTCFG_DISABLED;
4100	}
4101	return rc;
4102	}
4103
4104
4105	/**
4106	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
4107	*
4108	* @returns VBox status code (error message raised).
4109	* @param pVM The cross context VM structure. (For errors.)
4110	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4111	* @param pCpumCfg The /CPUM node (can be NULL).
4112	* @param pszValueName The value / extension name.
4113	* @param penmValue Where to return the choice.
4114	* @param enmDefault The default choice.
4115	*/
4116	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
4117	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
4118	{
4119	if (CFGMR3Exists(pCpumCfg, pszValueName))
4120	{
4121	if (!CFGMR3Exists(pIsaExts, pszValueName))
4122	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
4123	else
4124	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
4125	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
4126	pszValueName, pszValueName);
4127
4128	bool fLegacy;
4129	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
4130	if (RT_SUCCESS(rc))
4131	{
4132	*penmValue = fLegacy;
4133	return VINF_SUCCESS;
4134	}
4135	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
4136	}
4137
4138	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4139	}
4140
4141
4142	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
4143	{
4144	int rc;
4145
4146	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
4147	* When non-zero CPUID features that could cause portability issues will be
4148	* stripped. The higher the value the more features gets stripped. Higher
4149	* values should only be used when older CPUs are involved since it may
4150	* harm performance and maybe also cause problems with specific guests. */
4151	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
4152	AssertLogRelRCReturn(rc, rc);
4153
4154	/** @cfgm{/CPUM/GuestCpuName, string}
4155	* The name of the CPU we're to emulate. The default is the host CPU.
4156	* Note! CPUs other than "host" one is currently unsupported. */
4157	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
4158	AssertLogRelRCReturn(rc, rc);
4159
4160	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
4161	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
4162	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
4163	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
4164	*/
4165	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
4166	AssertLogRelRCReturn(rc, rc);
4167
4168	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
4169	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
4170	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
4171	* 64-bit linux guests which assume the presence of AMD performance counters
4172	* that we do not virtualize.
4173	*/
4174	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
4175	AssertLogRelRCReturn(rc, rc);
4176
4177	/** @cfgm{/CPUM/ForceVme, boolean, false}
4178	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
4179	* By default the flag is passed thru as is from the host CPU, except
4180	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
4181	* guests and DOS boxes in general.
4182	*/
4183	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
4184	AssertLogRelRCReturn(rc, rc);
4185
4186	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
4187	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
4188	* probably going to be a temporary hack, so don't depend on this.
4189	* The 1st byte of the value is the stepping, the 2nd byte value is the model
4190	* number and the 3rd byte value is the family, and the 4th value must be zero.
4191	*/
4192	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
4193	AssertLogRelRCReturn(rc, rc);
4194
4195	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
4196	* The last standard leaf to keep. The actual last value that is stored in EAX
4197	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
4198	* removed. (This works independently of and differently from NT4LeafLimit.)
4199	* The default is usually set to what we're able to reasonably sanitize.
4200	*/
4201	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
4202	AssertLogRelRCReturn(rc, rc);
4203
4204	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
4205	* The last extended leaf to keep. The actual last value that is stored in EAX
4206	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
4207	* leaf are removed. The default is set to what we're able to sanitize.
4208	*/
4209	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
4210	AssertLogRelRCReturn(rc, rc);
4211
4212	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
4213	* The last extended leaf to keep. The actual last value that is stored in EAX
4214	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
4215	* leaf are removed. The default is set to what we're able to sanitize.
4216	*/
4217	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
4218	AssertLogRelRCReturn(rc, rc);
4219
4220	bool fQueryNestedHwvirt = false
4221	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4222	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4223	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON
4224	#endif
4225	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4226	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
4227	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA
4228	#endif
4229	;
4230	if (fQueryNestedHwvirt)
4231	{
4232	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
4233	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
4234	* The default is false, and when enabled requires a 64-bit CPU with support for
4235	* nested-paging and AMD-V or unrestricted guest mode.
4236	*/
4237	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
4238	AssertLogRelRCReturn(rc, rc);
4239	if (pConfig->fNestedHWVirt)
4240	{
4241	/** @todo Think about enabling this later with NEM/KVM. */
4242	if (VM_IS_NEM_ENABLED(pVM))
4243	{
4244	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used! (later)\n"));
4245	pConfig->fNestedHWVirt = false;
4246	}
4247	else if (!fNestedPagingAndFullGuestExec)
4248	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
4249	"Cannot enable nested VT-x/AMD-V without nested-paging and unrestricted guest execution!\n");
4250	}
4251
4252	if (pConfig->fNestedHWVirt)
4253	{
4254	/** @cfgm{/CPUM/NestedVmxPreemptTimer, bool, true}
4255	* Whether to expose the VMX-preemption timer feature to the guest (if also
4256	* supported by the host hardware). When disabled will prevent exposing the
4257	* VMX-preemption timer feature to the guest even if the host supports it.
4258	*
4259	* @todo Currently disabled, see @bugref{9180#c108}.
4260	*/
4261	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxPreemptTimer", &pVM->cpum.s.fNestedVmxPreemptTimer, false);
4262	AssertLogRelRCReturn(rc, rc);
4263
4264	/** @cfgm{/CPUM/NestedVmxEpt, bool, true}
4265	* Whether to expose the EPT feature to the guest. The default is false. When
4266	* disabled will automatically prevent exposing features that rely on
4267	*/
4268	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxEpt", &pVM->cpum.s.fNestedVmxEpt, false);
4269	AssertLogRelRCReturn(rc, rc);
4270
4271	/** @cfgm{/CPUM/NestedVmxUnrestrictedGuest, bool, true}
4272	* Whether to expose the Unrestricted Guest feature to the guest. The default is
4273	* false. When disabled will automatically prevent exposing features that rely on
4274	* it.
4275	*/
4276	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxUnrestrictedGuest", &pVM->cpum.s.fNestedVmxUnrestrictedGuest, false);
4277	AssertLogRelRCReturn(rc, rc);
4278
4279	if ( pVM->cpum.s.fNestedVmxUnrestrictedGuest
4280	&& !pVM->cpum.s.fNestedVmxEpt)
4281	{
4282	LogRel(("CPUM: WARNING! Can't expose \"Unrestricted Guest\" to the guest when EPT is not exposed!\n"));
4283	pVM->cpum.s.fNestedVmxUnrestrictedGuest = false;
4284	}
4285	}
4286	}
4287
4288	/*
4289	* Instruction Set Architecture (ISA) Extensions.
4290	*/
4291	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
4292	if (pIsaExts)
4293	{
4294	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
4295	"CMPXCHG16B"
4296	"\|MONITOR"
4297	"\|MWaitExtensions"
4298	"\|SSE4.1"
4299	"\|SSE4.2"
4300	"\|XSAVE"
4301	"\|AVX"
4302	"\|AVX2"
4303	"\|AESNI"
4304	"\|PCLMUL"
4305	"\|POPCNT"
4306	"\|MOVBE"
4307	"\|RDRAND"
4308	"\|RDSEED"
4309	"\|CLFLUSHOPT"
4310	"\|FSGSBASE"
4311	"\|PCID"
4312	"\|INVPCID"
4313	"\|FlushCmdMsr"
4314	"\|ABM"
4315	"\|SSE4A"
4316	"\|MISALNSSE"
4317	"\|3DNOWPRF"
4318	"\|AXMMX"
4319	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
4320	if (RT_FAILURE(rc))
4321	return rc;
4322	}
4323
4324	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, true}
4325	* Expose CMPXCHG16B to the guest if available. All host CPUs which support
4326	* hardware virtualization have it.
4327	*/
4328	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, true);
4329	AssertLogRelRCReturn(rc, rc);
4330
4331	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
4332	* Expose MONITOR/MWAIT instructions to the guest.
4333	*/
4334	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
4335	AssertLogRelRCReturn(rc, rc);
4336
4337	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4338	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4339	* break on interrupt feature (bit 1).
4340	*/
4341	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4342	AssertLogRelRCReturn(rc, rc);
4343
4344	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4345	* Expose SSE4.1 to the guest if available.
4346	*/
4347	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4348	AssertLogRelRCReturn(rc, rc);
4349
4350	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4351	* Expose SSE4.2 to the guest if available.
4352	*/
4353	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4354	AssertLogRelRCReturn(rc, rc);
4355
4356	bool const fMayHaveXSave = pVM->cpum.s.HostFeatures.fXSaveRstor
4357	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
4358	&& ( !VM_IS_NEM_ENABLED(pVM)
4359	? fNestedPagingAndFullGuestExec
4360	: NEMHCGetFeatures(pVM) & NEM_FEAT_F_XSAVE_XRSTOR);
4361	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4362
4363	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4364	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4365	* default is to only expose this to VMs with nested paging and AMD-V or
4366	* unrestricted guest execution mode. Not possible to force this one without
4367	* host support at the moment.
4368	*/
4369	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4370	fMayHaveXSave /fAllowed/);
4371	AssertLogRelRCReturn(rc, rc);
4372
4373	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4374	* Expose the AVX instruction set extensions to the guest if available and
4375	* XSAVE is exposed too. For the time being the default is to only expose this
4376	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4377	*/
4378	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4379	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4380	AssertLogRelRCReturn(rc, rc);
4381
4382	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4383	* Expose the AVX2 instruction set extensions to the guest if available and
4384	* XSAVE is exposed too. For the time being the default is to only expose this
4385	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4386	*/
4387	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4388	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4389	AssertLogRelRCReturn(rc, rc);
4390
4391	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4392	* Whether to expose the AES instructions to the guest. For the time being the
4393	* default is to only do this for VMs with nested paging and AMD-V or
4394	* unrestricted guest mode.
4395	*/
4396	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4397	AssertLogRelRCReturn(rc, rc);
4398
4399	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4400	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4401	* being the default is to only do this for VMs with nested paging and AMD-V or
4402	* unrestricted guest mode.
4403	*/
4404	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4405	AssertLogRelRCReturn(rc, rc);
4406
4407	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4408	* Whether to expose the POPCNT instructions to the guest. For the time
4409	* being the default is to only do this for VMs with nested paging and AMD-V or
4410	* unrestricted guest mode.
4411	*/
4412	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4413	AssertLogRelRCReturn(rc, rc);
4414
4415	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4416	* Whether to expose the MOVBE instructions to the guest. For the time
4417	* being the default is to only do this for VMs with nested paging and AMD-V or
4418	* unrestricted guest mode.
4419	*/
4420	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4421	AssertLogRelRCReturn(rc, rc);
4422
4423	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4424	* Whether to expose the RDRAND instructions to the guest. For the time being
4425	* the default is to only do this for VMs with nested paging and AMD-V or
4426	* unrestricted guest mode.
4427	*/
4428	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4429	AssertLogRelRCReturn(rc, rc);
4430
4431	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4432	* Whether to expose the RDSEED instructions to the guest. For the time being
4433	* the default is to only do this for VMs with nested paging and AMD-V or
4434	* unrestricted guest mode.
4435	*/
4436	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4437	AssertLogRelRCReturn(rc, rc);
4438
4439	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4440	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4441	* being the default is to only do this for VMs with nested paging and AMD-V or
4442	* unrestricted guest mode.
4443	*/
4444	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4445	AssertLogRelRCReturn(rc, rc);
4446
4447	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4448	* Whether to expose the read/write FSGSBASE instructions to the guest.
4449	*/
4450	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4451	AssertLogRelRCReturn(rc, rc);
4452
4453	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4454	* Whether to expose the PCID feature to the guest.
4455	*/
4456	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4457	AssertLogRelRCReturn(rc, rc);
4458
4459	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4460	* Whether to expose the INVPCID instruction to the guest.
4461	*/
4462	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4463	AssertLogRelRCReturn(rc, rc);
4464
4465	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
4466	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
4467	*/
4468	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4469	AssertLogRelRCReturn(rc, rc);
4470
4471	/** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
4472	* Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
4473	* the guest. Requires FlushCmdMsr to be present too.
4474	*/
4475	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4476	AssertLogRelRCReturn(rc, rc);
4477
4478	/** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
4479	* Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
4480	*/
4481	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4482	AssertLogRelRCReturn(rc, rc);
4483
4484
4485	/* AMD: */
4486
4487	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4488	* Whether to expose the AMD ABM instructions to the guest. For the time
4489	* being the default is to only do this for VMs with nested paging and AMD-V or
4490	* unrestricted guest mode.
4491	*/
4492	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4493	AssertLogRelRCReturn(rc, rc);
4494
4495	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4496	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4497	* being the default is to only do this for VMs with nested paging and AMD-V or
4498	* unrestricted guest mode.
4499	*/
4500	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4501	AssertLogRelRCReturn(rc, rc);
4502
4503	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4504	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4505	* the time being the default is to only do this for VMs with nested paging and
4506	* AMD-V or unrestricted guest mode.
4507	*/
4508	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4509	AssertLogRelRCReturn(rc, rc);
4510
4511	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4512	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4513	* For the time being the default is to only do this for VMs with nested paging
4514	* and AMD-V or unrestricted guest mode.
4515	*/
4516	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4517	AssertLogRelRCReturn(rc, rc);
4518
4519	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4520	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4521	* the default is to only do this for VMs with nested paging and AMD-V or
4522	* unrestricted guest mode.
4523	*/
4524	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4525	AssertLogRelRCReturn(rc, rc);
4526
4527	return VINF_SUCCESS;
4528	}
4529
4530
4531	/**
4532	* Initializes the emulated CPU's CPUID & MSR information.
4533	*
4534	* @returns VBox status code.
4535	* @param pVM The cross context VM structure.
4536	* @param pHostMsrs Pointer to the host MSRs.
4537	*/
4538	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
4539	{
4540	Assert(pHostMsrs);
4541
4542	PCPUM pCpum = &pVM->cpum.s;
4543	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4544
4545	/*
4546	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4547	* on construction and manage everything from here on.
4548	*/
4549	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4550	{
4551	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4552	pVCpu->cpum.s.fCpuIdApicFeatureVisible = true;
4553	}
4554
4555	/*
4556	* Read the configuration.
4557	*/
4558	CPUMCPUIDCONFIG Config;
4559	RT_ZERO(Config);
4560
4561	bool const fNestedPagingAndFullGuestExec = VM_IS_NEM_ENABLED(pVM) \|\| HMAreNestedPagingAndFullGuestExecEnabled(pVM);
4562	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, fNestedPagingAndFullGuestExec);
4563	AssertRCReturn(rc, rc);
4564
4565	/*
4566	* Get the guest CPU data from the database and/or the host.
4567	*
4568	* The CPUID and MSRs are currently living on the regular heap to avoid
4569	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4570	* API for the hyper heap). This means special cleanup considerations.
4571	*/
4572	/** @todo The hyper heap will be removed ASAP, so the final destination is
4573	* now a fixed sized arrays in the VM structure. Maybe we can simplify
4574	* this allocation fun a little now? Or maybe it's too convenient for
4575	* the CPU reporter code... No time to figure that out now. */
4576	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4577	if (RT_FAILURE(rc))
4578	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4579	? VMSetError(pVM, rc, RT_SRC_POS,
4580	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4581	: rc;
4582
4583	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4584	{
4585	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4586	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4587	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4588	}
4589	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4590
4591	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4592	* Overrides the guest MSRs.
4593	*/
4594	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4595
4596	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4597	* Overrides the CPUID leaf values (from the host CPU usually) used for
4598	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4599	* values when moving a VM to a different machine. Another use is restricting
4600	* (or extending) the feature set exposed to the guest. */
4601	if (RT_SUCCESS(rc))
4602	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4603
4604	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4605	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4606	"Found unsupported configuration node '/CPUM/CPUID/'. "
4607	"Please use IMachine::setCPUIDLeaf() instead.");
4608
4609	CPUMMSRS GuestMsrs;
4610	RT_ZERO(GuestMsrs);
4611
4612	/*
4613	* Pre-explode the CPUID info.
4614	*/
4615	if (RT_SUCCESS(rc))
4616	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
4617	&pCpum->GuestFeatures);
4618
4619	/*
4620	* Sanitize the cpuid information passed on to the guest.
4621	*/
4622	if (RT_SUCCESS(rc))
4623	{
4624	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4625	if (RT_SUCCESS(rc))
4626	{
4627	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4628	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4629	}
4630	}
4631
4632	/*
4633	* Setup MSRs introduced in microcode updates or that are otherwise not in
4634	* the CPU profile, but are advertised in the CPUID info we just sanitized.
4635	*/
4636	if (RT_SUCCESS(rc))
4637	rc = cpumR3MsrReconcileWithCpuId(pVM);
4638	/*
4639	* MSR fudging.
4640	*/
4641	if (RT_SUCCESS(rc))
4642	{
4643	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4644	* Fudges some common MSRs if not present in the selected CPU database entry.
4645	* This is for trying to keep VMs running when moved between different hosts
4646	* and different CPU vendors. */
4647	bool fEnable;
4648	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4649	if (RT_SUCCESS(rc) && fEnable)
4650	{
4651	rc = cpumR3MsrApplyFudge(pVM);
4652	AssertLogRelRC(rc);
4653	}
4654	}
4655	if (RT_SUCCESS(rc))
4656	{
4657	/*
4658	* Move the MSR and CPUID arrays over to the static VM structure allocations
4659	* and explode guest CPU features again.
4660	*/
4661	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4662	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4663	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
4664	RTMemFree(pvFree);
4665
4666	AssertFatalMsg(pCpum->GuestInfo.cMsrRanges <= RT_ELEMENTS(pCpum->GuestInfo.aMsrRanges),
4667	("%u\n", pCpum->GuestInfo.cMsrRanges));
4668	memcpy(pCpum->GuestInfo.aMsrRanges, pCpum->GuestInfo.paMsrRangesR3,
4669	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges);
4670	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4671	pCpum->GuestInfo.paMsrRangesR3 = pCpum->GuestInfo.aMsrRanges;
4672
4673	AssertLogRelRCReturn(rc, rc);
4674
4675	/*
4676	* Finally, initialize guest VMX MSRs.
4677	*
4678	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
4679	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
4680	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
4681	*/
4682	if (pVM->cpum.s.GuestFeatures.fVmx)
4683	{
4684	Assert(Config.fNestedHWVirt);
4685	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
4686
4687	/* Copy MSRs to all VCPUs */
4688	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
4689	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4690	{
4691	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4692	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
4693	}
4694	}
4695
4696	/*
4697	* Some more configuration that we're applying at the end of everything
4698	* via the CPUMR3SetGuestCpuIdFeature API.
4699	*/
4700
4701	/* Check if PAE was explicitely enabled by the user. */
4702	bool fEnable;
4703	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4704	AssertRCReturn(rc, rc);
4705	if (fEnable)
4706	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4707
4708	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4709	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4710	AssertRCReturn(rc, rc);
4711	if (fEnable)
4712	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4713
4714	/* Check if speculation control is enabled. */
4715	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4716	AssertRCReturn(rc, rc);
4717	if (fEnable)
4718	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4719	else
4720	{
4721	/*
4722	* Set the "SSBD-not-needed" flag to work around a bug in some Linux kernels when the VIRT_SPEC_CTL
4723	* feature is not exposed on AMD CPUs and there is only 1 vCPU configured.
4724	* This was observed with kernel "4.15.0-29-generic #31~16.04.1-Ubuntu" but more versions are likely affected.
4725	*
4726	* The kernel doesn't initialize a lock and causes a NULL pointer exception later on when configuring SSBD:
4727	* EIP: _raw_spin_lock+0x14/0x30
4728	* EFLAGS: 00010046 CPU: 0
4729	* EAX: 00000000 EBX: 00000001 ECX: 00000004 EDX: 00000000
4730	* ESI: 00000000 EDI: 00000000 EBP: ee023f1c ESP: ee023f18
4731	* DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
4732	* CR0: 80050033 CR2: 00000004 CR3: 3671c180 CR4: 000006f0
4733	* Call Trace:
4734	* speculative_store_bypass_update+0x8e/0x180
4735	* ssb_prctl_set+0xc0/0xe0
4736	* arch_seccomp_spec_mitigate+0x1d/0x20
4737	* do_seccomp+0x3cb/0x610
4738	* SyS_seccomp+0x16/0x20
4739	* do_fast_syscall_32+0x7f/0x1d0
4740	* entry_SYSENTER_32+0x4e/0x7c
4741	*
4742	* The lock would've been initialized in process.c:speculative_store_bypass_ht_init() called from two places in smpboot.c.
4743	* First when a secondary CPU is started and second in native_smp_prepare_cpus() which is not called in a single vCPU environment.
4744	*
4745	* As spectre control features are completely disabled anyway when we arrived here there is no harm done in informing the
4746	* guest to not even try.
4747	*/
4748	if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4749	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
4750	{
4751	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x80000008), 0);
4752	if (pLeaf)
4753	{
4754	pLeaf->uEbx \|= X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED;
4755	LogRel(("CPUM: Set SSBD not required flag for AMD to work around some buggy Linux kernels!\n"));
4756	}
4757	}
4758	}
4759
4760	return VINF_SUCCESS;
4761	}
4762
4763	/*
4764	* Failed before switching to hyper heap.
4765	*/
4766	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4767	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4768	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4769	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4770	return rc;
4771	}
4772
4773
4774	/**
4775	* Sets a CPUID feature bit during VM initialization.
4776	*
4777	* Since the CPUID feature bits are generally related to CPU features, other
4778	* CPUM configuration like MSRs can also be modified by calls to this API.
4779	*
4780	* @param pVM The cross context VM structure.
4781	* @param enmFeature The feature to set.
4782	*/
4783	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4784	{
4785	PCPUMCPUIDLEAF pLeaf;
4786	PCPUMMSRRANGE pMsrRange;
4787
4788	switch (enmFeature)
4789	{
4790	/*
4791	* Set the APIC bit in both feature masks.
4792	*/
4793	case CPUMCPUIDFEATURE_APIC:
4794	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4795	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4796	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4797
4798	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4799	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4800	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4801
4802	pVM->cpum.s.GuestFeatures.fApic = 1;
4803
4804	/* Make sure we've got the APICBASE MSR present. */
4805	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4806	if (!pMsrRange)
4807	{
4808	static CPUMMSRRANGE const s_ApicBase =
4809	{
4810	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4811	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4812	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4813	/.szName = / "IA32_APIC_BASE"
4814	};
4815	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4816	AssertLogRelRC(rc);
4817	}
4818
4819	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4820	break;
4821
4822	/*
4823	* Set the x2APIC bit in the standard feature mask.
4824	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4825	*/
4826	case CPUMCPUIDFEATURE_X2APIC:
4827	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4828	if (pLeaf)
4829	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4830	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4831
4832	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4833	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4834	if (pMsrRange)
4835	{
4836	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4837	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4838	}
4839
4840	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4841	break;
4842
4843	/*
4844	* Set the sysenter/sysexit bit in the standard feature mask.
4845	* Assumes the caller knows what it's doing! (host must support these)
4846	*/
4847	case CPUMCPUIDFEATURE_SEP:
4848	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4849	{
4850	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4851	return;
4852	}
4853
4854	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4855	if (pLeaf)
4856	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4857	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4858	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4859	break;
4860
4861	/*
4862	* Set the syscall/sysret bit in the extended feature mask.
4863	* Assumes the caller knows what it's doing! (host must support these)
4864	*/
4865	case CPUMCPUIDFEATURE_SYSCALL:
4866	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4867	if ( !pLeaf
4868	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4869	{
4870	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4871	return;
4872	}
4873
4874	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4875	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4876	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4877	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4878	break;
4879
4880	/*
4881	* Set the PAE bit in both feature masks.
4882	* Assumes the caller knows what it's doing! (host must support these)
4883	*/
4884	case CPUMCPUIDFEATURE_PAE:
4885	if (!pVM->cpum.s.HostFeatures.fPae)
4886	{
4887	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4888	return;
4889	}
4890
4891	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4892	if (pLeaf)
4893	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4894
4895	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4896	if ( pLeaf
4897	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4898	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
4899	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4900
4901	pVM->cpum.s.GuestFeatures.fPae = 1;
4902	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4903	break;
4904
4905	/*
4906	* Set the LONG MODE bit in the extended feature mask.
4907	* Assumes the caller knows what it's doing! (host must support these)
4908	*/
4909	case CPUMCPUIDFEATURE_LONG_MODE:
4910	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4911	if ( !pLeaf
4912	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4913	{
4914	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4915	return;
4916	}
4917
4918	/* Valid for both Intel and AMD. */
4919	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4920	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4921	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
4922	if (pVM->cpum.s.GuestFeatures.fVmx)
4923	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4924	{
4925	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4926	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic &= ~VMX_BASIC_PHYSADDR_WIDTH_32BIT;
4927	}
4928	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4929	break;
4930
4931	/*
4932	* Set the NX/XD bit in the extended feature mask.
4933	* Assumes the caller knows what it's doing! (host must support these)
4934	*/
4935	case CPUMCPUIDFEATURE_NX:
4936	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4937	if ( !pLeaf
4938	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4939	{
4940	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4941	return;
4942	}
4943
4944	/* Valid for both Intel and AMD. */
4945	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4946	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4947	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4948	break;
4949
4950
4951	/*
4952	* Set the LAHF/SAHF support in 64-bit mode.
4953	* Assumes the caller knows what it's doing! (host must support this)
4954	*/
4955	case CPUMCPUIDFEATURE_LAHF:
4956	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4957	if ( !pLeaf
4958	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4959	{
4960	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4961	return;
4962	}
4963
4964	/* Valid for both Intel and AMD. */
4965	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4966	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4967	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4968	break;
4969
4970	/*
4971	* Set the RDTSCP support bit.
4972	* Assumes the caller knows what it's doing! (host must support this)
4973	*/
4974	case CPUMCPUIDFEATURE_RDTSCP:
4975	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4976	if ( !pLeaf
4977	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4978	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4979	{
4980	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4981	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4982	return;
4983	}
4984
4985	/* Valid for both Intel and AMD. */
4986	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4987	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4988	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4989	break;
4990
4991	/*
4992	* Set the Hypervisor Present bit in the standard feature mask.
4993	*/
4994	case CPUMCPUIDFEATURE_HVP:
4995	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4996	if (pLeaf)
4997	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4998	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4999	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
5000	break;
5001
5002	/*
5003	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
5004	* on Intel CPUs, and different on AMDs.
5005	*/
5006	case CPUMCPUIDFEATURE_SPEC_CTRL:
5007	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
5008	{
5009	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
5010	if ( !pLeaf
5011	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
5012	{
5013	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
5014	return;
5015	}
5016
5017	/* The feature can be enabled. Let's see what we can actually do. */
5018	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
5019
5020	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
5021	if (pVM->cpum.s.HostFeatures.fIbrs)
5022	{
5023	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
5024	pVM->cpum.s.GuestFeatures.fIbrs = 1;
5025	if (pVM->cpum.s.HostFeatures.fStibp)
5026	{
5027	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
5028	pVM->cpum.s.GuestFeatures.fStibp = 1;
5029	}
5030
5031	/* Make sure we have the speculation control MSR... */
5032	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
5033	if (!pMsrRange)
5034	{
5035	static CPUMMSRRANGE const s_SpecCtrl =
5036	{
5037	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
5038	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
5039	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
5040	/.szName = / "IA32_SPEC_CTRL"
5041	};
5042	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
5043	AssertLogRelRC(rc);
5044	}
5045
5046	/* ... and the predictor command MSR. */
5047	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
5048	if (!pMsrRange)
5049	{
5050	/** @todo incorrect fWrGpMask. */
5051	static CPUMMSRRANGE const s_SpecCtrl =
5052	{
5053	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
5054	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
5055	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
5056	/.szName = / "IA32_PRED_CMD"
5057	};
5058	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
5059	AssertLogRelRC(rc);
5060	}
5061
5062	}
5063
5064	if (pVM->cpum.s.HostFeatures.fArchCap)
5065	{
5066	/* Install the architectural capabilities MSR. */
5067	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
5068	if (!pMsrRange)
5069	{
5070	static CPUMMSRRANGE const s_ArchCaps =
5071	{
5072	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
5073	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
5074	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
5075	/.szName = / "IA32_ARCH_CAPABILITIES"
5076	};
5077	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
5078	AssertLogRelRC(rc);
5079	}
5080
5081	/* Advertise IBRS_ALL if present at this point... */
5082	if (pVM->cpum.s.HostFeatures.fArchCap & MSR_IA32_ARCH_CAP_F_IBRS_ALL)
5083	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps \|= MSR_IA32_ARCH_CAP_F_IBRS_ALL);
5084	}
5085
5086	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
5087	}
5088	else if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
5089	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
5090	{
5091	/* The precise details of AMD's implementation are not yet clear. */
5092	}
5093	break;
5094
5095	default:
5096	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5097	break;
5098	}
5099
5100	/** @todo can probably kill this as this API is now init time only... */
5101	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5102	{
5103	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5104	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5105	}
5106	}
5107
5108
5109	/**
5110	* Queries a CPUID feature bit.
5111	*
5112	* @returns boolean for feature presence
5113	* @param pVM The cross context VM structure.
5114	* @param enmFeature The feature to query.
5115	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
5116	*/
5117	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
5118	{
5119	switch (enmFeature)
5120	{
5121	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
5122	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
5123	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
5124	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
5125	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
5126	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
5127	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
5128	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
5129	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
5130	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
5131	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
5132	case CPUMCPUIDFEATURE_INVALID:
5133	case CPUMCPUIDFEATURE_32BIT_HACK:
5134	break;
5135	}
5136	AssertFailed();
5137	return false;
5138	}
5139
5140
5141	/**
5142	* Clears a CPUID feature bit.
5143	*
5144	* @param pVM The cross context VM structure.
5145	* @param enmFeature The feature to clear.
5146	*
5147	* @deprecated Probably better to default the feature to disabled and only allow
5148	* setting (enabling) it during construction.
5149	*/
5150	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
5151	{
5152	PCPUMCPUIDLEAF pLeaf;
5153	switch (enmFeature)
5154	{
5155	case CPUMCPUIDFEATURE_APIC:
5156	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
5157	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5158	if (pLeaf)
5159	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
5160
5161	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5162	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
5163	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
5164
5165	pVM->cpum.s.GuestFeatures.fApic = 0;
5166	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
5167	break;
5168
5169	case CPUMCPUIDFEATURE_X2APIC:
5170	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
5171	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5172	if (pLeaf)
5173	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
5174	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
5175	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
5176	break;
5177
5178	case CPUMCPUIDFEATURE_PAE:
5179	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5180	if (pLeaf)
5181	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
5182
5183	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5184	if ( pLeaf
5185	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
5186	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
5187	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
5188
5189	pVM->cpum.s.GuestFeatures.fPae = 0;
5190	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
5191	break;
5192
5193	case CPUMCPUIDFEATURE_LONG_MODE:
5194	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5195	if (pLeaf)
5196	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
5197	pVM->cpum.s.GuestFeatures.fLongMode = 0;
5198	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = 32;
5199	if (pVM->cpum.s.GuestFeatures.fVmx)
5200	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5201	{
5202	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5203	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic \|= VMX_BASIC_PHYSADDR_WIDTH_32BIT;
5204	}
5205	break;
5206
5207	case CPUMCPUIDFEATURE_LAHF:
5208	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5209	if (pLeaf)
5210	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
5211	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
5212	break;
5213
5214	case CPUMCPUIDFEATURE_RDTSCP:
5215	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5216	if (pLeaf)
5217	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
5218	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
5219	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
5220	break;
5221
5222	case CPUMCPUIDFEATURE_HVP:
5223	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5224	if (pLeaf)
5225	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
5226	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
5227	break;
5228
5229	case CPUMCPUIDFEATURE_SPEC_CTRL:
5230	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
5231	if (pLeaf)
5232	pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP);
5233	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL);
5234	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
5235	break;
5236
5237	default:
5238	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5239	break;
5240	}
5241
5242	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5243	{
5244	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5245	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5246	}
5247	}
5248
5249
5250
5251	/*
5252	*
5253	*
5254	* Saved state related code.
5255	* Saved state related code.
5256	* Saved state related code.
5257	*
5258	*
5259	*/
5260
5261	/**
5262	* Called both in pass 0 and the final pass.
5263	*
5264	* @param pVM The cross context VM structure.
5265	* @param pSSM The saved state handle.
5266	*/
5267	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
5268	{
5269	/*
5270	* Save all the CPU ID leaves.
5271	*/
5272	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
5273	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5274	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
5275	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5276
5277	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5278
5279	/*
5280	* Save a good portion of the raw CPU IDs as well as they may come in
5281	* handy when validating features for raw mode.
5282	*/
5283	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5284	CPUMCPUID aRawStd[16];
5285	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
5286	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5287	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
5288	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
5289
5290	CPUMCPUID aRawExt[32];
5291	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
5292	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5293	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
5294	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
5295
5296	#else
5297	/* Two zero counts on non-x86 hosts. */
5298	SSMR3PutU32(pSSM, 0);
5299	SSMR3PutU32(pSSM, 0);
5300	#endif
5301	}
5302
5303
5304	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5305	{
5306	uint32_t cCpuIds;
5307	int rc = SSMR3GetU32(pSSM, &cCpuIds);
5308	if (RT_SUCCESS(rc))
5309	{
5310	if (cCpuIds < 64)
5311	{
5312	for (uint32_t i = 0; i < cCpuIds; i++)
5313	{
5314	CPUMCPUID CpuId;
5315	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
5316	if (RT_FAILURE(rc))
5317	break;
5318
5319	CPUMCPUIDLEAF NewLeaf;
5320	NewLeaf.uLeaf = uBase + i;
5321	NewLeaf.uSubLeaf = 0;
5322	NewLeaf.fSubLeafMask = 0;
5323	NewLeaf.uEax = CpuId.uEax;
5324	NewLeaf.uEbx = CpuId.uEbx;
5325	NewLeaf.uEcx = CpuId.uEcx;
5326	NewLeaf.uEdx = CpuId.uEdx;
5327	NewLeaf.fFlags = 0;
5328	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
5329	}
5330	}
5331	else
5332	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5333	}
5334	if (RT_FAILURE(rc))
5335	{
5336	RTMemFree(*ppaLeaves);
5337	*ppaLeaves = NULL;
5338	*pcLeaves = 0;
5339	}
5340	return rc;
5341	}
5342
5343
5344	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5345	{
5346	*ppaLeaves = NULL;
5347	*pcLeaves = 0;
5348
5349	int rc;
5350	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
5351	{
5352	/*
5353	* The new format. Starts by declaring the leave size and count.
5354	*/
5355	uint32_t cbLeaf;
5356	SSMR3GetU32(pSSM, &cbLeaf);
5357	uint32_t cLeaves;
5358	rc = SSMR3GetU32(pSSM, &cLeaves);
5359	if (RT_SUCCESS(rc))
5360	{
5361	if (cbLeaf == sizeof(**ppaLeaves))
5362	{
5363	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
5364	{
5365	/*
5366	* Load the leaves one by one.
5367	*
5368	* The uPrev stuff is a kludge for working around a week worth of bad saved
5369	* states during the CPUID revamp in March 2015. We saved too many leaves
5370	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
5371	* garbage entires at the end of the array when restoring. We also had
5372	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
5373	* this kludge doesn't deal correctly with that, but who cares...
5374	*/
5375	uint32_t uPrev = 0;
5376	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
5377	{
5378	CPUMCPUIDLEAF Leaf;
5379	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
5380	if (RT_SUCCESS(rc))
5381	{
5382	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
5383	\|\| Leaf.uLeaf >= uPrev)
5384	{
5385	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5386	uPrev = Leaf.uLeaf;
5387	}
5388	else
5389	uPrev = UINT32_MAX;
5390	}
5391	}
5392	}
5393	else
5394	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5395	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5396	}
5397	else
5398	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5399	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5400	}
5401	}
5402	else
5403	{
5404	/*
5405	* The old format with its three inflexible arrays.
5406	*/
5407	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5408	if (RT_SUCCESS(rc))
5409	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5410	if (RT_SUCCESS(rc))
5411	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5412	if (RT_SUCCESS(rc))
5413	{
5414	/*
5415	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5416	*/
5417	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5418	if ( pLeaf
5419	&& RTX86IsIntelCpu(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5420	{
5421	CPUMCPUIDLEAF Leaf;
5422	Leaf.uLeaf = 4;
5423	Leaf.fSubLeafMask = UINT32_MAX;
5424	Leaf.uSubLeaf = 0;
5425	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5426	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5427	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5428	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5429	\| UINT32_C(63); /* system coherency line size - 1 */
5430	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5431	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5432	\| (UINT32_C(1) << 5) /* cache level */
5433	\| UINT32_C(1); /* cache type (data) */
5434	Leaf.fFlags = 0;
5435	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5436	if (RT_SUCCESS(rc))
5437	{
5438	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5439	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5440	}
5441	if (RT_SUCCESS(rc))
5442	{
5443	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5444	Leaf.uEcx = 4095; /* sets - 1 */
5445	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5446	Leaf.uEbx \|= UINT32_C(23) << 22;
5447	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5448	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5449	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5450	Leaf.uEax \|= UINT32_C(2) << 5;
5451	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5452	}
5453	}
5454	}
5455	}
5456	return rc;
5457	}
5458
5459
5460	/**
5461	* Loads the CPU ID leaves saved by pass 0, inner worker.
5462	*
5463	* @returns VBox status code.
5464	* @param pVM The cross context VM structure.
5465	* @param pSSM The saved state handle.
5466	* @param uVersion The format version.
5467	* @param paLeaves Guest CPUID leaves loaded from the state.
5468	* @param cLeaves The number of leaves in @a paLeaves.
5469	* @param pMsrs The guest MSRs.
5470	*/
5471	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
5472	{
5473	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5474
5475	/*
5476	* Continue loading the state into stack buffers.
5477	*/
5478	CPUMCPUID GuestDefCpuId;
5479	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5480	AssertRCReturn(rc, rc);
5481
5482	CPUMCPUID aRawStd[16];
5483	uint32_t cRawStd;
5484	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5485	if (cRawStd > RT_ELEMENTS(aRawStd))
5486	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5487	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5488	AssertRCReturn(rc, rc);
5489	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5490	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5491	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5492	#else
5493	RT_ZERO(aRawStd[i]);
5494	#endif
5495
5496	CPUMCPUID aRawExt[32];
5497	uint32_t cRawExt;
5498	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5499	if (cRawExt > RT_ELEMENTS(aRawExt))
5500	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5501	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5502	AssertRCReturn(rc, rc);
5503	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5504	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5505	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5506	#else
5507	RT_ZERO(aRawExt[i]);
5508	#endif
5509
5510	/*
5511	* Get the raw CPU IDs for the current host.
5512	*/
5513	CPUMCPUID aHostRawStd[16];
5514	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5515	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5516	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5517	#else
5518	RT_ZERO(aHostRawStd);
5519	#endif
5520
5521	CPUMCPUID aHostRawExt[32];
5522	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5523	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5524	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5525	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5526	#else
5527	RT_ZERO(aHostRawExt);
5528	#endif
5529
5530	/*
5531	* Get the host and guest overrides so we don't reject the state because
5532	* some feature was enabled thru these interfaces.
5533	* Note! We currently only need the feature leaves, so skip rest.
5534	*/
5535	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5536	CPUMCPUID aHostOverrideStd[2];
5537	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5538	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5539
5540	CPUMCPUID aHostOverrideExt[2];
5541	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5542	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5543
5544	/*
5545	* This can be skipped.
5546	*/
5547	bool fStrictCpuIdChecks;
5548	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5549
5550	/*
5551	* Define a bunch of macros for simplifying the santizing/checking code below.
5552	*/
5553	/* Generic expression + failure message. */
5554	#define CPUID_CHECK_RET(expr, fmt) \
5555	do { \
5556	if (!(expr)) \
5557	{ \
5558	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5559	if (fStrictCpuIdChecks) \
5560	{ \
5561	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5562	RTStrFree(pszMsg); \
5563	return rcCpuid; \
5564	} \
5565	LogRel(("CPUM: %s\n", pszMsg)); \
5566	RTStrFree(pszMsg); \
5567	} \
5568	} while (0)
5569	#define CPUID_CHECK_WRN(expr, fmt) \
5570	do { \
5571	if (!(expr)) \
5572	LogRel(fmt); \
5573	} while (0)
5574
5575	/* For comparing two values and bitch if they differs. */
5576	#define CPUID_CHECK2_RET(what, host, saved) \
5577	do { \
5578	if ((host) != (saved)) \
5579	{ \
5580	if (fStrictCpuIdChecks) \
5581	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5582	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5583	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5584	} \
5585	} while (0)
5586	#define CPUID_CHECK2_WRN(what, host, saved) \
5587	do { \
5588	if ((host) != (saved)) \
5589	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5590	} while (0)
5591
5592	/* For checking raw cpu features (raw mode). */
5593	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5594	do { \
5595	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5596	{ \
5597	if (fStrictCpuIdChecks) \
5598	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5599	N_(#bit " mismatch: host=%d saved=%d"), \
5600	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5601	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5602	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5603	} \
5604	} while (0)
5605	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5606	do { \
5607	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5608	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5609	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5610	} while (0)
5611	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5612
5613	/* For checking guest features. */
5614	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5615	do { \
5616	if ( (aGuestCpuId##set [1].reg & bit) \
5617	&& !(aHostRaw##set [1].reg & bit) \
5618	&& !(aHostOverride##set [1].reg & bit) \
5619	) \
5620	{ \
5621	if (fStrictCpuIdChecks) \
5622	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5623	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5624	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5625	} \
5626	} while (0)
5627	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5628	do { \
5629	if ( (aGuestCpuId##set [1].reg & bit) \
5630	&& !(aHostRaw##set [1].reg & bit) \
5631	&& !(aHostOverride##set [1].reg & bit) \
5632	) \
5633	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5634	} while (0)
5635	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5636	do { \
5637	if ( (aGuestCpuId##set [1].reg & bit) \
5638	&& !(aHostRaw##set [1].reg & bit) \
5639	&& !(aHostOverride##set [1].reg & bit) \
5640	) \
5641	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5642	} while (0)
5643	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5644
5645	/* For checking guest features if AMD guest CPU. */
5646	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5647	do { \
5648	if ( (aGuestCpuId##set [1].reg & bit) \
5649	&& fGuestAmd \
5650	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5651	&& !(aHostOverride##set [1].reg & bit) \
5652	) \
5653	{ \
5654	if (fStrictCpuIdChecks) \
5655	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5656	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5657	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5658	} \
5659	} while (0)
5660	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5661	do { \
5662	if ( (aGuestCpuId##set [1].reg & bit) \
5663	&& fGuestAmd \
5664	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5665	&& !(aHostOverride##set [1].reg & bit) \
5666	) \
5667	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5668	} while (0)
5669	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5670	do { \
5671	if ( (aGuestCpuId##set [1].reg & bit) \
5672	&& fGuestAmd \
5673	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5674	&& !(aHostOverride##set [1].reg & bit) \
5675	) \
5676	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5677	} while (0)
5678	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5679
5680	/* For checking AMD features which have a corresponding bit in the standard
5681	range. (Intel defines very few bits in the extended feature sets.) */
5682	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5683	do { \
5684	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5685	&& !(fHostAmd \
5686	? aHostRawExt[1].reg & (ExtBit) \
5687	: aHostRawStd[1].reg & (StdBit)) \
5688	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5689	) \
5690	{ \
5691	if (fStrictCpuIdChecks) \
5692	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5693	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5694	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5695	} \
5696	} while (0)
5697	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5698	do { \
5699	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5700	&& !(fHostAmd \
5701	? aHostRawExt[1].reg & (ExtBit) \
5702	: aHostRawStd[1].reg & (StdBit)) \
5703	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5704	) \
5705	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5706	} while (0)
5707	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5708	do { \
5709	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5710	&& !(fHostAmd \
5711	? aHostRawExt[1].reg & (ExtBit) \
5712	: aHostRawStd[1].reg & (StdBit)) \
5713	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5714	) \
5715	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5716	} while (0)
5717	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5718
5719
5720	/*
5721	* Verify that we can support the features already exposed to the guest on
5722	* this host.
5723	*
5724	* Most of the features we're emulating requires intercepting instruction
5725	* and doing it the slow way, so there is no need to warn when they aren't
5726	* present in the host CPU. Thus we use IGN instead of EMU on these.
5727	*
5728	* Trailing comments:
5729	* "EMU" - Possible to emulate, could be lots of work and very slow.
5730	* "EMU?" - Can this be emulated?
5731	*/
5732	CPUMCPUID aGuestCpuIdStd[2];
5733	RT_ZERO(aGuestCpuIdStd);
5734	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5735
5736	/* CPUID(1).ecx */
5737	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5738	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5739	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5740	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5741	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5742	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5743	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5744	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5745	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5746	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5747	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5748	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5749	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5750	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5751	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5752	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5753	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5754	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5755	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5756	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5757	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5758	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5759	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5760	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5761	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5762	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5763	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5764	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5765	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5766	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5767	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5768	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5769
5770	/* CPUID(1).edx */
5771	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5772	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5773	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5774	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5775	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5776	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5777	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5778	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5779	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5780	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5781	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5782	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5783	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5784	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5785	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5786	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5787	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5788	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5789	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5790	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5791	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5792	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5793	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5794	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5795	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5796	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5797	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5798	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5799	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5800	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5801	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5802	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5803
5804	/* CPUID(0x80000000). */
5805	CPUMCPUID aGuestCpuIdExt[2];
5806	RT_ZERO(aGuestCpuIdExt);
5807	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5808	{
5809	/** @todo deal with no 0x80000001 on the host. */
5810	bool const fHostAmd = RTX86IsAmdCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx)
5811	\|\| RTX86IsHygonCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5812	bool const fGuestAmd = RTX86IsAmdCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx)
5813	\|\| RTX86IsHygonCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5814
5815	/* CPUID(0x80000001).ecx */
5816	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5817	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5818	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5819	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5820	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5821	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5822	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5823	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5824	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5825	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5826	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5827	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5828	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5829	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5830	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5831	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5832	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5833	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5834	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5835	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5836	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5837	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5838	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5839	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5840	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5841	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5842	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5843	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5844	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5845	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5846	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5847	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5848
5849	/* CPUID(0x80000001).edx */
5850	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5851	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5852	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5853	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5854	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5855	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5856	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5857	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5858	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5859	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5860	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5861	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5862	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5863	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5864	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5865	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5866	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5867	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5868	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5869	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5870	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5871	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5872	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5873	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5874	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5875	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5876	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5877	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5878	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5879	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5880	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5881	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5882	}
5883
5884	/** @todo check leaf 7 */
5885
5886	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5887	* ECX=0: EAX - Valid bits in XCR0[31:0].
5888	* EBX - Maximum state size as per current XCR0 value.
5889	* ECX - Maximum state size for all supported features.
5890	* EDX - Valid bits in XCR0[63:32].
5891	* ECX=1: EAX - Various X-features.
5892	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5893	* ECX - Valid bits in IA32_XSS[31:0].
5894	* EDX - Valid bits in IA32_XSS[63:32].
5895	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5896	* if the bit invalid all four registers are set to zero.
5897	* EAX - The state size for this feature.
5898	* EBX - The state byte offset of this feature.
5899	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5900	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5901	*/
5902	uint64_t fGuestXcr0Mask = 0;
5903	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5904	if ( pCurLeaf
5905	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5906	&& ( pCurLeaf->uEax
5907	\|\| pCurLeaf->uEbx
5908	\|\| pCurLeaf->uEcx
5909	\|\| pCurLeaf->uEdx) )
5910	{
5911	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5912	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5913	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5914	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5915	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5916	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5917	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5918	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5919
5920	/* We don't support any additional features yet. */
5921	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5922	if (pCurLeaf && pCurLeaf->uEax)
5923	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5924	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5925	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5926	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5927	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5928	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5929
5930
5931	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5932	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5933	{
5934	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5935	if (pCurLeaf)
5936	{
5937	/* If advertised, the state component offset and size must match the one used by host. */
5938	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5939	{
5940	CPUMCPUID RawHost;
5941	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5942	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5943	if ( RawHost.uEbx != pCurLeaf->uEbx
5944	\|\| RawHost.uEax != pCurLeaf->uEax)
5945	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5946	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5947	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5948	}
5949	}
5950	}
5951	#endif
5952	}
5953	/* Clear leaf 0xd just in case we're loading an old state... */
5954	else if (pCurLeaf)
5955	{
5956	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5957	{
5958	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5959	if (pCurLeaf)
5960	{
5961	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5962	\|\| ( pCurLeaf->uEax == 0
5963	&& pCurLeaf->uEbx == 0
5964	&& pCurLeaf->uEcx == 0
5965	&& pCurLeaf->uEdx == 0),
5966	("uVersion=%#x; %#x %#x %#x %#x\n",
5967	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5968	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5969	}
5970	}
5971	}
5972
5973	/* Update the fXStateGuestMask value for the VM. */
5974	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5975	{
5976	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5977	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5978	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5979	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5980	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5981	}
5982
5983	#undef CPUID_CHECK_RET
5984	#undef CPUID_CHECK_WRN
5985	#undef CPUID_CHECK2_RET
5986	#undef CPUID_CHECK2_WRN
5987	#undef CPUID_RAW_FEATURE_RET
5988	#undef CPUID_RAW_FEATURE_WRN
5989	#undef CPUID_RAW_FEATURE_IGN
5990	#undef CPUID_GST_FEATURE_RET
5991	#undef CPUID_GST_FEATURE_WRN
5992	#undef CPUID_GST_FEATURE_EMU
5993	#undef CPUID_GST_FEATURE_IGN
5994	#undef CPUID_GST_FEATURE2_RET
5995	#undef CPUID_GST_FEATURE2_WRN
5996	#undef CPUID_GST_FEATURE2_EMU
5997	#undef CPUID_GST_FEATURE2_IGN
5998	#undef CPUID_GST_AMD_FEATURE_RET
5999	#undef CPUID_GST_AMD_FEATURE_WRN
6000	#undef CPUID_GST_AMD_FEATURE_EMU
6001	#undef CPUID_GST_AMD_FEATURE_IGN
6002
6003	/*
6004	* We're good, commit the CPU ID leaves.
6005	*/
6006	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
6007	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
6008	AssertLogRelRCReturn(rc, rc);
6009
6010	return VINF_SUCCESS;
6011	}
6012
6013
6014	/**
6015	* Loads the CPU ID leaves saved by pass 0.
6016	*
6017	* @returns VBox status code.
6018	* @param pVM The cross context VM structure.
6019	* @param pSSM The saved state handle.
6020	* @param uVersion The format version.
6021	* @param pMsrs The guest MSRs.
6022	*/
6023	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
6024	{
6025	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
6026
6027	/*
6028	* Load the CPUID leaves array first and call worker to do the rest, just so
6029	* we can free the memory when we need to without ending up in column 1000.
6030	*/
6031	PCPUMCPUIDLEAF paLeaves;
6032	uint32_t cLeaves;
6033	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
6034	AssertRC(rc);
6035	if (RT_SUCCESS(rc))
6036	{
6037	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
6038	RTMemFree(paLeaves);
6039	}
6040	return rc;
6041	}
6042
6043
6044
6045	/**
6046	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
6047	*
6048	* @returns VBox status code.
6049	* @param pVM The cross context VM structure.
6050	* @param pSSM The saved state handle.
6051	* @param uVersion The format version.
6052	*/
6053	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
6054	{
6055	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
6056
6057	/*
6058	* Restore the CPUID leaves.
6059	*
6060	* Note that we support restoring less than the current amount of standard
6061	* leaves because we've been allowed more is newer version of VBox.
6062	*/
6063	uint32_t cElements;
6064	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6065	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
6066	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6067	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
6068
6069	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6070	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
6071	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6072	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
6073
6074	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6075	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
6076	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6077	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
6078
6079	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
6080
6081	/*
6082	* Check that the basic cpuid id information is unchanged.
6083	*/
6084	/** @todo we should check the 64 bits capabilities too! */
6085	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
6086	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6087	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
6088	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
6089	#endif
6090	uint32_t au32CpuIdSaved[8];
6091	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
6092	if (RT_SUCCESS(rc))
6093	{
6094	/* Ignore CPU stepping. */
6095	au32CpuId[4] &= 0xfffffff0;
6096	au32CpuIdSaved[4] &= 0xfffffff0;
6097
6098	/* Ignore APIC ID (AMD specs). */
6099	au32CpuId[5] &= ~0xff000000;
6100	au32CpuIdSaved[5] &= ~0xff000000;
6101
6102	/* Ignore the number of Logical CPUs (AMD specs). */
6103	au32CpuId[5] &= ~0x00ff0000;
6104	au32CpuIdSaved[5] &= ~0x00ff0000;
6105
6106	/* Ignore some advanced capability bits, that we don't expose to the guest. */
6107	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6108	\| X86_CPUID_FEATURE_ECX_VMX
6109	\| X86_CPUID_FEATURE_ECX_SMX
6110	\| X86_CPUID_FEATURE_ECX_EST
6111	\| X86_CPUID_FEATURE_ECX_TM2
6112	\| X86_CPUID_FEATURE_ECX_CNTXID
6113	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6114	\| X86_CPUID_FEATURE_ECX_PDCM
6115	\| X86_CPUID_FEATURE_ECX_DCA
6116	\| X86_CPUID_FEATURE_ECX_X2APIC
6117	);
6118	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6119	\| X86_CPUID_FEATURE_ECX_VMX
6120	\| X86_CPUID_FEATURE_ECX_SMX
6121	\| X86_CPUID_FEATURE_ECX_EST
6122	\| X86_CPUID_FEATURE_ECX_TM2
6123	\| X86_CPUID_FEATURE_ECX_CNTXID
6124	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6125	\| X86_CPUID_FEATURE_ECX_PDCM
6126	\| X86_CPUID_FEATURE_ECX_DCA
6127	\| X86_CPUID_FEATURE_ECX_X2APIC
6128	);
6129
6130	/* Make sure we don't forget to update the masks when enabling
6131	* features in the future.
6132	*/
6133	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
6134	( X86_CPUID_FEATURE_ECX_DTES64
6135	\| X86_CPUID_FEATURE_ECX_VMX
6136	\| X86_CPUID_FEATURE_ECX_SMX
6137	\| X86_CPUID_FEATURE_ECX_EST
6138	\| X86_CPUID_FEATURE_ECX_TM2
6139	\| X86_CPUID_FEATURE_ECX_CNTXID
6140	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6141	\| X86_CPUID_FEATURE_ECX_PDCM
6142	\| X86_CPUID_FEATURE_ECX_DCA
6143	\| X86_CPUID_FEATURE_ECX_X2APIC
6144	)));
6145	/* do the compare */
6146	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
6147	{
6148	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
6149	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
6150	"Saved=%.*Rhxs\n"
6151	"Real =%.*Rhxs\n",
6152	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6153	sizeof(au32CpuId), au32CpuId));
6154	else
6155	{
6156	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
6157	"Saved=%.*Rhxs\n"
6158	"Real =%.*Rhxs\n",
6159	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6160	sizeof(au32CpuId), au32CpuId));
6161	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
6162	}
6163	}
6164	}
6165
6166	return rc;
6167	}
6168
6169
6170
6171	/*
6172	*
6173	*
6174	* CPUID Info Handler.
6175	* CPUID Info Handler.
6176	* CPUID Info Handler.
6177	*
6178	*
6179	*/
6180
6181
6182
6183	/**
6184	* Get L1 cache / TLS associativity.
6185	*/
6186	static const char getCacheAss(unsigned u, char pszBuf)
6187	{
6188	if (u == 0)
6189	return "res0 ";
6190	if (u == 1)
6191	return "direct";
6192	if (u == 255)
6193	return "fully";
6194	if (u >= 256)
6195	return "???";
6196
6197	RTStrPrintf(pszBuf, 16, "%d way", u);
6198	return pszBuf;
6199	}
6200
6201
6202	/**
6203	* Get L2 cache associativity.
6204	*/
6205	const char *getL2CacheAss(unsigned u)
6206	{
6207	switch (u)
6208	{
6209	case 0: return "off ";
6210	case 1: return "direct";
6211	case 2: return "2 way ";
6212	case 3: return "res3 ";
6213	case 4: return "4 way ";
6214	case 5: return "res5 ";
6215	case 6: return "8 way ";
6216	case 7: return "res7 ";
6217	case 8: return "16 way";
6218	case 9: return "res9 ";
6219	case 10: return "res10 ";
6220	case 11: return "res11 ";
6221	case 12: return "res12 ";
6222	case 13: return "res13 ";
6223	case 14: return "res14 ";
6224	case 15: return "fully ";
6225	default: return "????";
6226	}
6227	}
6228
6229
6230	/** CPUID(1).EDX field descriptions. */
6231	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6232	{
6233	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6234	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6235	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6236	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6237	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6238	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6239	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6240	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6241	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6242	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6243	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6244	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6245	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6246	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6247	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6248	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6249	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6250	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6251	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6252	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6253	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6254	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6255	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6256	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6257	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6258	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6259	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6260	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6261	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6262	DBGFREGSUBFIELD_TERMINATOR()
6263	};
6264
6265	/** CPUID(1).ECX field descriptions. */
6266	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6267	{
6268	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6269	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6270	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6271	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6272	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6273	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6274	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6275	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6276	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6277	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6278	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6279	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6280	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6281	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6282	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6283	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6284	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6285	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6286	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6287	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6288	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6289	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6290	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6291	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6292	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6293	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6294	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6295	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6296	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6297	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6298	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6299	DBGFREGSUBFIELD_TERMINATOR()
6300	};
6301
6302	/** CPUID(7,0).EBX field descriptions. */
6303	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6304	{
6305	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6306	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6307	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6308	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6309	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6310	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6311	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6312	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6313	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6314	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6315	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6316	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6317	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6318	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6319	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6320	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6321	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6322	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6323	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6324	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6325	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6326	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6327	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6328	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6329	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6330	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6331	DBGFREGSUBFIELD_TERMINATOR()
6332	};
6333
6334	/** CPUID(7,0).ECX field descriptions. */
6335	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6336	{
6337	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6338	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6339	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6340	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6341	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6342	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6343	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6344	DBGFREGSUBFIELD_TERMINATOR()
6345	};
6346
6347	/** CPUID(7,0).EDX field descriptions. */
6348	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6349	{
6350	DBGFREGSUBFIELD_RO("MD_CLEAR\0" "Supports MDS related buffer clearing", 10, 1, 0),
6351	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6352	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6353	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
6354	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6355	DBGFREGSUBFIELD_RO("CORECAP\0" "Supports IA32_CORE_CAP", 30, 1, 0),
6356	DBGFREGSUBFIELD_RO("SSBD\0" "Supports IA32_SPEC_CTRL.SSBD", 31, 1, 0),
6357	DBGFREGSUBFIELD_TERMINATOR()
6358	};
6359
6360
6361	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6362	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6363	{
6364	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6365	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6366	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6367	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6368	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6369	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6370	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6371	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6372	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6373	DBGFREGSUBFIELD_TERMINATOR()
6374	};
6375
6376	/** CPUID(13,1).EAX field descriptions. */
6377	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6378	{
6379	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6380	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6381	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6382	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6383	DBGFREGSUBFIELD_TERMINATOR()
6384	};
6385
6386
6387	/** CPUID(0x80000001,0).EDX field descriptions. */
6388	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6389	{
6390	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6391	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6392	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6393	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6394	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6395	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6396	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6397	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6398	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6399	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6400	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6401	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6402	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6403	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6404	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6405	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6406	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6407	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6408	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6409	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6410	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6411	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6412	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6413	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6414	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6415	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6416	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6417	DBGFREGSUBFIELD_TERMINATOR()
6418	};
6419
6420	/** CPUID(0x80000001,0).ECX field descriptions. */
6421	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6422	{
6423	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6424	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6425	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6426	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6427	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6428	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6429	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6430	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6431	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6432	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6433	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6434	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6435	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6436	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6437	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6438	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6439	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6440	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6441	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6442	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6443	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6444	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6445	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6446	DBGFREGSUBFIELD_RO("PCX_L2I\0" "L2I/L3 Performance Counter Extensions", 28, 1, 0),
6447	DBGFREGSUBFIELD_RO("MWAITX\0" "MWAITX and MONITORX instructions", 29, 1, 0),
6448	DBGFREGSUBFIELD_TERMINATOR()
6449	};
6450
6451	/** CPUID(0x8000000a,0).EDX field descriptions. */
6452	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
6453	{
6454	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
6455	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
6456	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
6457	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
6458	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
6459	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
6460	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
6461	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
6462	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
6463	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
6464	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
6465	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
6466	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
6467	DBGFREGSUBFIELD_RO("GMET\0" "Guest Mode Execute Trap Extension", 17, 1, 0),
6468	DBGFREGSUBFIELD_TERMINATOR()
6469	};
6470
6471
6472	/** CPUID(0x80000007,0).EDX field descriptions. */
6473	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6474	{
6475	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6476	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6477	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6478	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6479	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6480	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6481	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6482	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6483	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6484	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6485	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6486	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6487	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6488	DBGFREGSUBFIELD_TERMINATOR()
6489	};
6490
6491	/** CPUID(0x80000008,0).EBX field descriptions. */
6492	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6493	{
6494	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6495	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6496	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6497	DBGFREGSUBFIELD_RO("RDPRU\0" "RDPRU instruction", 4, 1, 0),
6498	DBGFREGSUBFIELD_RO("MCOMMIT\0" "MCOMMIT instruction", 8, 1, 0),
6499	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6500	DBGFREGSUBFIELD_TERMINATOR()
6501	};
6502
6503
6504	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6505	const char *pszLeadIn, uint32_t cchWidth)
6506	{
6507	if (pszLeadIn)
6508	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6509
6510	for (uint32_t iBit = 0; iBit < 32; iBit++)
6511	if (RT_BIT_32(iBit) & uVal)
6512	{
6513	while ( pDesc->pszName != NULL
6514	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6515	pDesc++;
6516	if ( pDesc->pszName != NULL
6517	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6518	{
6519	if (pDesc->cBits == 1)
6520	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6521	else
6522	{
6523	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6524	if (pDesc->cBits < 32)
6525	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6526	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6527	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6528	}
6529	}
6530	else
6531	pHlp->pfnPrintf(pHlp, " %u", iBit);
6532	}
6533	if (pszLeadIn)
6534	pHlp->pfnPrintf(pHlp, "\n");
6535	}
6536
6537
6538	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6539	const char *pszLeadIn, uint32_t cchWidth)
6540	{
6541	if (pszLeadIn)
6542	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6543
6544	for (uint32_t iBit = 0; iBit < 64; iBit++)
6545	if (RT_BIT_64(iBit) & uVal)
6546	{
6547	while ( pDesc->pszName != NULL
6548	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6549	pDesc++;
6550	if ( pDesc->pszName != NULL
6551	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6552	{
6553	if (pDesc->cBits == 1)
6554	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6555	else
6556	{
6557	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6558	if (pDesc->cBits < 64)
6559	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6560	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6561	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6562	}
6563	}
6564	else
6565	pHlp->pfnPrintf(pHlp, " %u", iBit);
6566	}
6567	if (pszLeadIn)
6568	pHlp->pfnPrintf(pHlp, "\n");
6569	}
6570
6571
6572	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6573	const char *pszLeadIn, uint32_t cchWidth)
6574	{
6575	if (!uVal)
6576	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6577	else
6578	{
6579	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6580	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6581	pHlp->pfnPrintf(pHlp, " )\n");
6582	}
6583	}
6584
6585
6586	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6587	uint32_t cchWidth)
6588	{
6589	uint32_t uCombined = uVal1 \| uVal2;
6590	for (uint32_t iBit = 0; iBit < 32; iBit++)
6591	if ( (RT_BIT_32(iBit) & uCombined)
6592	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6593	{
6594	while ( pDesc->pszName != NULL
6595	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6596	pDesc++;
6597
6598	if ( pDesc->pszName != NULL
6599	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6600	{
6601	size_t cchMnemonic = strlen(pDesc->pszName);
6602	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6603	size_t cchDesc = strlen(pszDesc);
6604	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6605	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6606	if (pDesc->cBits < 32)
6607	{
6608	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6609	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6610	}
6611
6612	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6613	pDesc->pszName, pszDesc,
6614	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6615	uFieldValue1, uFieldValue2);
6616
6617	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6618	pDesc++;
6619	}
6620	else
6621	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6622	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6623	}
6624	}
6625
6626
6627	/**
6628	* Produces a detailed summary of standard leaf 0x00000001.
6629	*
6630	* @param pHlp The info helper functions.
6631	* @param pCurLeaf The 0x00000001 leaf.
6632	* @param fVerbose Whether to be very verbose or not.
6633	* @param fIntel Set if intel CPU.
6634	*/
6635	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6636	{
6637	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6638	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6639	uint32_t uEAX = pCurLeaf->uEax;
6640	uint32_t uEBX = pCurLeaf->uEbx;
6641
6642	pHlp->pfnPrintf(pHlp,
6643	"%36s %2d \tExtended: %d \tEffective: %d\n"
6644	"%36s %2d \tExtended: %d \tEffective: %d\n"
6645	"%36s %d\n"
6646	"%36s %d (%s)\n"
6647	"%36s %#04x\n"
6648	"%36s %d\n"
6649	"%36s %d\n"
6650	"%36s %#04x\n"
6651	,
6652	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
6653	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
6654	"Stepping:", RTX86GetCpuStepping(uEAX),
6655	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6656	"APIC ID:", (uEBX >> 24) & 0xff,
6657	"Logical CPUs:",(uEBX >> 16) & 0xff,
6658	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6659	"Brand ID:", (uEBX >> 0) & 0xff);
6660	if (fVerbose)
6661	{
6662	CPUMCPUID Host = {0};
6663	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6664	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6665	#endif
6666	pHlp->pfnPrintf(pHlp, "Features\n");
6667	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6668	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6669	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6670	}
6671	else
6672	{
6673	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6674	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6675	}
6676	}
6677
6678
6679	/**
6680	* Produces a detailed summary of standard leaf 0x00000007.
6681	*
6682	* @param pHlp The info helper functions.
6683	* @param paLeaves The CPUID leaves array.
6684	* @param cLeaves The number of leaves in the array.
6685	* @param pCurLeaf The first 0x00000007 leaf.
6686	* @param fVerbose Whether to be very verbose or not.
6687	*/
6688	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6689	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6690	{
6691	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6692	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6693	for (;;)
6694	{
6695	CPUMCPUID Host = {0};
6696	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6697	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6698	#endif
6699
6700	switch (pCurLeaf->uSubLeaf)
6701	{
6702	case 0:
6703	if (fVerbose)
6704	{
6705	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6706	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6707	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6708	if (pCurLeaf->uEdx \|\| Host.uEdx)
6709	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6710	}
6711	else
6712	{
6713	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6714	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6715	if (pCurLeaf->uEdx)
6716	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6717	}
6718	break;
6719
6720	default:
6721	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6722	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6723	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6724	break;
6725
6726	}
6727
6728	/* advance. */
6729	pCurLeaf++;
6730	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6731	\|\| pCurLeaf->uLeaf != 0x7)
6732	break;
6733	}
6734	}
6735
6736
6737	/**
6738	* Produces a detailed summary of standard leaf 0x0000000d.
6739	*
6740	* @param pHlp The info helper functions.
6741	* @param paLeaves The CPUID leaves array.
6742	* @param cLeaves The number of leaves in the array.
6743	* @param pCurLeaf The first 0x00000007 leaf.
6744	* @param fVerbose Whether to be very verbose or not.
6745	*/
6746	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6747	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6748	{
6749	RT_NOREF_PV(fVerbose);
6750	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6751	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6752	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6753	{
6754	CPUMCPUID Host = {0};
6755	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6756	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6757	#endif
6758
6759	switch (uSubLeaf)
6760	{
6761	case 0:
6762	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6763	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6764	pCurLeaf->uEbx, pCurLeaf->uEcx);
6765	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6766
6767	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6768	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6769	"Valid XCR0 bits, guest:", 42);
6770	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6771	"Valid XCR0 bits, host:", 42);
6772	break;
6773
6774	case 1:
6775	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6776	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6777	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6778
6779	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6780	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6781	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6782
6783	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6784	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6785	" Valid IA32_XSS bits, guest:", 42);
6786	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6787	" Valid IA32_XSS bits, host:", 42);
6788	break;
6789
6790	default:
6791	if ( pCurLeaf
6792	&& pCurLeaf->uSubLeaf == uSubLeaf
6793	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6794	{
6795	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6796	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6797	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6798	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6799	if (pCurLeaf->uEdx)
6800	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6801	pHlp->pfnPrintf(pHlp, " --");
6802	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6803	pHlp->pfnPrintf(pHlp, "\n");
6804	}
6805	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6806	{
6807	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6808	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6809	if (Host.uEcx & ~RT_BIT_32(0))
6810	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6811	if (Host.uEdx)
6812	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6813	pHlp->pfnPrintf(pHlp, " --");
6814	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6815	pHlp->pfnPrintf(pHlp, "\n");
6816	}
6817	break;
6818
6819	}
6820
6821	/* advance. */
6822	if (pCurLeaf)
6823	{
6824	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6825	&& pCurLeaf->uSubLeaf <= uSubLeaf
6826	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6827	pCurLeaf++;
6828	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6829	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6830	pCurLeaf = NULL;
6831	}
6832	}
6833	}
6834
6835
6836	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6837	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6838	{
6839	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6840	&& pCurLeaf->uLeaf <= uUpToLeaf)
6841	{
6842	pHlp->pfnPrintf(pHlp,
6843	" %s\n"
6844	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6845	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6846	&& pCurLeaf->uLeaf <= uUpToLeaf)
6847	{
6848	CPUMCPUID Host = {0};
6849	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6850	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6851	#endif
6852	pHlp->pfnPrintf(pHlp,
6853	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6854	"Hst: %08x %08x %08x %08x\n",
6855	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6856	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6857	pCurLeaf++;
6858	}
6859	}
6860
6861	return pCurLeaf;
6862	}
6863
6864
6865	/**
6866	* Display the guest CpuId leaves.
6867	*
6868	* @param pVM The cross context VM structure.
6869	* @param pHlp The info helper functions.
6870	* @param pszArgs "terse", "default" or "verbose".
6871	*/
6872	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6873	{
6874	/*
6875	* Parse the argument.
6876	*/
6877	unsigned iVerbosity = 1;
6878	if (pszArgs)
6879	{
6880	pszArgs = RTStrStripL(pszArgs);
6881	if (!strcmp(pszArgs, "terse"))
6882	iVerbosity--;
6883	else if (!strcmp(pszArgs, "verbose"))
6884	iVerbosity++;
6885	}
6886
6887	uint32_t uLeaf;
6888	CPUMCPUID Host = {0};
6889	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6890	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6891	PCCPUMCPUIDLEAF pCurLeaf;
6892	PCCPUMCPUIDLEAF pNextLeaf;
6893	bool const fIntel = RTX86IsIntelCpu(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6894	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6895	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6896
6897	/*
6898	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6899	*/
6900	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6901	uint32_t cHstMax = ASMCpuId_EAX(0);
6902	#else
6903	uint32_t cHstMax = 0;
6904	#endif
6905	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6906	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6907	pHlp->pfnPrintf(pHlp,
6908	" Raw Standard CPUID Leaves\n"
6909	" Leaf/sub-leaf eax ebx ecx edx\n");
6910	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6911	{
6912	uint32_t cMaxSubLeaves = 1;
6913	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6914	cMaxSubLeaves = 16;
6915	else if (uLeaf == 0xd)
6916	cMaxSubLeaves = 128;
6917
6918	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6919	{
6920	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6921	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6922	#endif
6923	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6924	&& pCurLeaf->uLeaf == uLeaf
6925	&& pCurLeaf->uSubLeaf == uSubLeaf)
6926	{
6927	pHlp->pfnPrintf(pHlp,
6928	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6929	"Hst: %08x %08x %08x %08x\n",
6930	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6931	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6932	pCurLeaf++;
6933	}
6934	else if ( uLeaf != 0xd
6935	\|\| uSubLeaf <= 1
6936	\|\| Host.uEbx != 0 )
6937	pHlp->pfnPrintf(pHlp,
6938	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6939	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6940
6941	/* Done? */
6942	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6943	\|\| pCurLeaf->uLeaf != uLeaf)
6944	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6945	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6946	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6947	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6948	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6949	)
6950	)
6951	break;
6952	}
6953	}
6954	pNextLeaf = pCurLeaf;
6955
6956	/*
6957	* If verbose, decode it.
6958	*/
6959	if (iVerbosity && paLeaves[0].uLeaf == 0)
6960	pHlp->pfnPrintf(pHlp,
6961	"%36s %.04s%.04s%.04s\n"
6962	"%36s 0x00000000-%#010x\n"
6963	,
6964	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6965	"Supports:", paLeaves[0].uEax);
6966
6967	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6968	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6969
6970	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6971	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6972
6973	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6974	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6975
6976	pCurLeaf = pNextLeaf;
6977
6978	/*
6979	* Hypervisor leaves.
6980	*
6981	* Unlike most of the other leaves reported, the guest hypervisor leaves
6982	* aren't a subset of the host CPUID bits.
6983	*/
6984	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6985
6986	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6987	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6988	#endif
6989	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6990	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6991	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6992	cMax = RT_MAX(cHstMax, cGstMax);
6993	if (cMax >= UINT32_C(0x40000000))
6994	{
6995	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6996
6997	/** @todo dump these in more detail. */
6998
6999	pCurLeaf = pNextLeaf;
7000	}
7001
7002
7003	/*
7004	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
7005	* Implemented after AMD specs.
7006	*/
7007	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
7008
7009	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7010	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7011	#endif
7012	cHstMax = RTX86IsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
7013	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
7014	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
7015	cMax = RT_MAX(cHstMax, cGstMax);
7016	if (cMax >= UINT32_C(0x80000000))
7017	{
7018
7019	pHlp->pfnPrintf(pHlp,
7020	" Raw Extended CPUID Leaves\n"
7021	" Leaf/sub-leaf eax ebx ecx edx\n");
7022	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
7023	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
7024	{
7025	uint32_t cMaxSubLeaves = 1;
7026	if (uLeaf == UINT32_C(0x8000001d))
7027	cMaxSubLeaves = 16;
7028
7029	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
7030	{
7031	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7032	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7033	#endif
7034	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
7035	&& pCurLeaf->uLeaf == uLeaf
7036	&& pCurLeaf->uSubLeaf == uSubLeaf)
7037	{
7038	pHlp->pfnPrintf(pHlp,
7039	"Gst: %08x/%04x %08x %08x %08x %08x\n"
7040	"Hst: %08x %08x %08x %08x\n",
7041	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
7042	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
7043	pCurLeaf++;
7044	}
7045	else if ( uLeaf != 0xd
7046	\|\| uSubLeaf <= 1
7047	\|\| Host.uEbx != 0 )
7048	pHlp->pfnPrintf(pHlp,
7049	"Hst: %08x/%04x %08x %08x %08x %08x\n",
7050	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
7051
7052	/* Done? */
7053	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
7054	\|\| pCurLeaf->uLeaf != uLeaf)
7055	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
7056	break;
7057	}
7058	}
7059	pNextLeaf = pCurLeaf;
7060
7061	/*
7062	* Understandable output
7063	*/
7064	if (iVerbosity)
7065	pHlp->pfnPrintf(pHlp,
7066	"Ext Name: %.4s%.4s%.4s\n"
7067	"Ext Supports: 0x80000000-%#010x\n",
7068	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
7069
7070	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
7071	if (iVerbosity && pCurLeaf)
7072	{
7073	uint32_t uEAX = pCurLeaf->uEax;
7074	pHlp->pfnPrintf(pHlp,
7075	"Family: %d \tExtended: %d \tEffective: %d\n"
7076	"Model: %d \tExtended: %d \tEffective: %d\n"
7077	"Stepping: %d\n"
7078	"Brand ID: %#05x\n",
7079	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
7080	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
7081	RTX86GetCpuStepping(uEAX),
7082	pCurLeaf->uEbx & 0xfff);
7083
7084	if (iVerbosity == 1)
7085	{
7086	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
7087	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
7088	}
7089	else
7090	{
7091	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7092	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7093	#endif
7094	pHlp->pfnPrintf(pHlp, "Ext Features\n");
7095	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
7096	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
7097	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
7098	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
7099	{
7100	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
7101	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7102	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7103	#endif
7104	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
7105	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
7106	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
7107	}
7108	}
7109	}
7110
7111	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
7112	{
7113	char szString[443+1] = {0};
7114	uint32_t pu32 = (uint32_t )szString;
7115	*pu32++ = pCurLeaf->uEax;
7116	*pu32++ = pCurLeaf->uEbx;
7117	*pu32++ = pCurLeaf->uEcx;
7118	*pu32++ = pCurLeaf->uEdx;
7119	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
7120	if (pCurLeaf)
7121	{
7122	*pu32++ = pCurLeaf->uEax;
7123	*pu32++ = pCurLeaf->uEbx;
7124	*pu32++ = pCurLeaf->uEcx;
7125	*pu32++ = pCurLeaf->uEdx;
7126	}
7127	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
7128	if (pCurLeaf)
7129	{
7130	*pu32++ = pCurLeaf->uEax;
7131	*pu32++ = pCurLeaf->uEbx;
7132	*pu32++ = pCurLeaf->uEcx;
7133	*pu32++ = pCurLeaf->uEdx;
7134	}
7135	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
7136	}
7137
7138	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
7139	{
7140	uint32_t uEAX = pCurLeaf->uEax;
7141	uint32_t uEBX = pCurLeaf->uEbx;
7142	uint32_t uECX = pCurLeaf->uEcx;
7143	uint32_t uEDX = pCurLeaf->uEdx;
7144	char sz1[32];
7145	char sz2[32];
7146
7147	pHlp->pfnPrintf(pHlp,
7148	"TLB 2/4M Instr/Uni: %s %3d entries\n"
7149	"TLB 2/4M Data: %s %3d entries\n",
7150	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
7151	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
7152	pHlp->pfnPrintf(pHlp,
7153	"TLB 4K Instr/Uni: %s %3d entries\n"
7154	"TLB 4K Data: %s %3d entries\n",
7155	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
7156	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
7157	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
7158	"L1 Instr Cache Lines Per Tag: %d\n"
7159	"L1 Instr Cache Associativity: %s\n"
7160	"L1 Instr Cache Size: %d KB\n",
7161	(uEDX >> 0) & 0xff,
7162	(uEDX >> 8) & 0xff,
7163	getCacheAss((uEDX >> 16) & 0xff, sz1),
7164	(uEDX >> 24) & 0xff);
7165	pHlp->pfnPrintf(pHlp,
7166	"L1 Data Cache Line Size: %d bytes\n"
7167	"L1 Data Cache Lines Per Tag: %d\n"
7168	"L1 Data Cache Associativity: %s\n"
7169	"L1 Data Cache Size: %d KB\n",
7170	(uECX >> 0) & 0xff,
7171	(uECX >> 8) & 0xff,
7172	getCacheAss((uECX >> 16) & 0xff, sz1),
7173	(uECX >> 24) & 0xff);
7174	}
7175
7176	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
7177	{
7178	uint32_t uEAX = pCurLeaf->uEax;
7179	uint32_t uEBX = pCurLeaf->uEbx;
7180	uint32_t uEDX = pCurLeaf->uEdx;
7181
7182	pHlp->pfnPrintf(pHlp,
7183	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
7184	"L2 TLB 2/4M Data: %s %4d entries\n",
7185	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
7186	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
7187	pHlp->pfnPrintf(pHlp,
7188	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
7189	"L2 TLB 4K Data: %s %4d entries\n",
7190	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
7191	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
7192	pHlp->pfnPrintf(pHlp,
7193	"L2 Cache Line Size: %d bytes\n"
7194	"L2 Cache Lines Per Tag: %d\n"
7195	"L2 Cache Associativity: %s\n"
7196	"L2 Cache Size: %d KB\n",
7197	(uEDX >> 0) & 0xff,
7198	(uEDX >> 8) & 0xf,
7199	getL2CacheAss((uEDX >> 12) & 0xf),
7200	(uEDX >> 16) & 0xffff);
7201	}
7202
7203	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
7204	{
7205	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7206	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7207	#endif
7208	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
7209	{
7210	if (iVerbosity < 1)
7211	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
7212	else
7213	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
7214	}
7215	}
7216
7217	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
7218	if (pCurLeaf != NULL)
7219	{
7220	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7221	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7222	#endif
7223	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
7224	{
7225	if (iVerbosity < 1)
7226	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
7227	else
7228	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
7229	}
7230
7231	if (iVerbosity)
7232	{
7233	uint32_t uEAX = pCurLeaf->uEax;
7234	uint32_t uECX = pCurLeaf->uEcx;
7235
7236	/** @todo 0x80000008:EAX[23:16] is only defined for AMD. We'll get 0 on Intel. On
7237	* AMD if we get 0, the guest physical address width should be taken from
7238	* 0x80000008:EAX[7:0] instead. Guest Physical address width is relevant
7239	* for guests using nested paging. */
7240	pHlp->pfnPrintf(pHlp,
7241	"Physical Address Width: %d bits\n"
7242	"Virtual Address Width: %d bits\n"
7243	"Guest Physical Address Width: %d bits\n",
7244	(uEAX >> 0) & 0xff,
7245	(uEAX >> 8) & 0xff,
7246	(uEAX >> 16) & 0xff);
7247
7248	/** @todo 0x80000008:ECX is reserved on Intel (we'll get incorrect physical core
7249	* count here). */
7250	pHlp->pfnPrintf(pHlp,
7251	"Physical Core Count: %d\n",
7252	((uECX >> 0) & 0xff) + 1);
7253	}
7254	}
7255
7256	pCurLeaf = pNextLeaf;
7257	}
7258
7259
7260
7261	/*
7262	* Centaur.
7263	*/
7264	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7265
7266	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7267	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7268	#endif
7269	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7270	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7271	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7272	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7273	cMax = RT_MAX(cHstMax, cGstMax);
7274	if (cMax >= UINT32_C(0xc0000000))
7275	{
7276	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7277
7278	/*
7279	* Understandable output
7280	*/
7281	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7282	pHlp->pfnPrintf(pHlp,
7283	"Centaur Supports: 0xc0000000-%#010x\n",
7284	pCurLeaf->uEax);
7285
7286	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7287	{
7288	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7289	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7290	#endif
7291	uint32_t uEdxGst = pCurLeaf->uEdx;
7292	uint32_t uEdxHst = Host.uEdx;
7293
7294	if (iVerbosity == 1)
7295	{
7296	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7297	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7298	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7299	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7300	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7301	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7302	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7303	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7304	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7305	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7306	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7307	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7308	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7309	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7310	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7311	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7312	for (unsigned iBit = 14; iBit < 32; iBit++)
7313	if (uEdxGst & RT_BIT(iBit))
7314	pHlp->pfnPrintf(pHlp, " %d", iBit);
7315	pHlp->pfnPrintf(pHlp, "\n");
7316	}
7317	else
7318	{
7319	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7320	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7321	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7322	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7323	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7324	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7325	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7326	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7327	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7328	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7329	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7330	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7331	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7332	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7333	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7334	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7335	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7336	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7337	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7338	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7339	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7340	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7341	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7342	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7343	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7344	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7345	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7346	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7347	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7348	for (unsigned iBit = 27; iBit < 32; iBit++)
7349	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7350	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7351	pHlp->pfnPrintf(pHlp, "\n");
7352	}
7353	}
7354
7355	pCurLeaf = pNextLeaf;
7356	}
7357
7358	/*
7359	* The remainder.
7360	*/
7361	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7362	}
7363
7364	#endif /* !IN_VBOX_CPU_REPORT */
7365

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 93609

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