CPUMR3CpuId.cpp@ 91276

Last change on this file since 91276 was 91276, checked in by vboxsync, 3 years ago
VMM: Added missing features checks while constructing mask of valid CR4 bits. (missed line)
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 340.5 KB

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1	/* $Id: CPUMR3CpuId.cpp 91276 2021-09-16 11:14:18Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vmcc.h>
30	#include <VBox/sup.h>
31
32	#include <VBox/err.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/ctype.h>
35	#include <iprt/mem.h>
36	#include <iprt/string.h>
37
38
39	/*********************************************************************************************************************************
40	* Defined Constants And Macros *
41	*********************************************************************************************************************************/
42	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
43	#define CPUM_CPUID_MAX_LEAVES 2048
44	/* Max size we accept for the XSAVE area. */
45	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
46	/* Min size we accept for the XSAVE area. */
47	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
48
49
50	/*********************************************************************************************************************************
51	* Global Variables *
52	*********************************************************************************************************************************/
53	/**
54	* The intel pentium family.
55	*/
56	static const CPUMMICROARCH g_aenmIntelFamily06[] =
57	{
58	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
59	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
60	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
61	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
62	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
63	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
64	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
65	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
66	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
67	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
68	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
69	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
70	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
71	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
72	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
73	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
74	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
75	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
80	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
81	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
82	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
83	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [26(0x1a)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Nehalem-EP */
85	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
86	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
87	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
88	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
89	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
90	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
91	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
96	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
97	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
98	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
99	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
101	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
102	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
103	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
104	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
105	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
106	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
107	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
112	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
113	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
114	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
115	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
117	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
118	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
119	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
120	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
121	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
122	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
123	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
128	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
130	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
131	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
133	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
134	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
135	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
136	/* [78(0x4e)] = */ kCpumMicroarch_Intel_Core7_Skylake,
137	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Broadwell-E */
138	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
139	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu; skylake <= 4, cascade lake > 5 */
144	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
145	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
146	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
147	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
149	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
150	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
151	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
152	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
153	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
154	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
155	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
158	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
159	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
160	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
161	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
162	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
163	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
164	/[106(0x6a)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
165	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
166	/[108(0x6c)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
167	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
168	/[110(0x6e)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
169	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
170	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
171	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
172	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
173	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
174	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
175	/[117(0x75)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
176	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
177	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
178	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
179	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
180	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
181	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
182	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
183	/[125(0x7d)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
184	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
185	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
186	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
187	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
188	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
189	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
190	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
191	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
192	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
193	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
194	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
195	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
196	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
197	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
198	/[140(0x8c)] = / kCpumMicroarch_Intel_Core7_TigerLake, /* 11th Gen Intel(R) Core(TM) i7-1185G7 @ 3.00GHz (bird) */
199	/[141(0x8d)] = / kCpumMicroarch_Intel_Core7_TigerLake, /* unconfirmed */
200	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
201	/[143(0x8f)] = / kCpumMicroarch_Intel_Core7_SapphireRapids,
202	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
203	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
204	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
205	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
206	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
207	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
208	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
209	/[151(0x97)] = / kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
210	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
211	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
212	/[154(0x9a)] = / kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
213	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
214	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
215	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
216	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
217	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
218	/[160(0xa0)] = / kCpumMicroarch_Intel_Unknown,
219	/[161(0xa1)] = / kCpumMicroarch_Intel_Unknown,
220	/[162(0xa2)] = / kCpumMicroarch_Intel_Unknown,
221	/[163(0xa3)] = / kCpumMicroarch_Intel_Unknown,
222	/[164(0xa4)] = / kCpumMicroarch_Intel_Unknown,
223	/[165(0xa5)] = / kCpumMicroarch_Intel_Core7_CometLake, /* unconfirmed */
224	/[166(0xa6)] = / kCpumMicroarch_Intel_Unknown,
225	/[167(0xa7)] = / kCpumMicroarch_Intel_Core7_CypressCove, /* 14nm backport, unconfirmed */
226	};
227	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0xa7+1);
228
229
230	/**
231	* Figures out the (sub-)micro architecture given a bit of CPUID info.
232	*
233	* @returns Micro architecture.
234	* @param enmVendor The CPU vendor.
235	* @param bFamily The CPU family.
236	* @param bModel The CPU model.
237	* @param bStepping The CPU stepping.
238	*/
239	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
240	uint8_t bModel, uint8_t bStepping)
241	{
242	if (enmVendor == CPUMCPUVENDOR_AMD)
243	{
244	switch (bFamily)
245	{
246	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
247	case 0x03: return kCpumMicroarch_AMD_Am386;
248	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
249	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
250	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
251	case 0x06:
252	switch (bModel)
253	{
254	case 0: return kCpumMicroarch_AMD_K7_Palomino;
255	case 1: return kCpumMicroarch_AMD_K7_Palomino;
256	case 2: return kCpumMicroarch_AMD_K7_Palomino;
257	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
258	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
259	case 6: return kCpumMicroarch_AMD_K7_Palomino;
260	case 7: return kCpumMicroarch_AMD_K7_Morgan;
261	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
262	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
263	}
264	return kCpumMicroarch_AMD_K7_Unknown;
265	case 0x0f:
266	/*
267	* This family is a friggin mess. Trying my best to make some
268	* sense out of it. Too much happened in the 0x0f family to
269	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
270	*
271	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
272	* cpu-world.com, and other places:
273	* - 130nm:
274	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
275	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
276	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
277	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
278	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
279	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
280	* - 90nm:
281	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
282	* - Oakville: 10FC0/DH-D0.
283	* - Georgetown: 10FC0/DH-D0.
284	* - Sonora: 10FC0/DH-D0.
285	* - Venus: 20F71/SH-E4
286	* - Troy: 20F51/SH-E4
287	* - Athens: 20F51/SH-E4
288	* - San Diego: 20F71/SH-E4.
289	* - Lancaster: 20F42/SH-E5
290	* - Newark: 20F42/SH-E5.
291	* - Albany: 20FC2/DH-E6.
292	* - Roma: 20FC2/DH-E6.
293	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
294	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
295	* - 90nm introducing Dual core:
296	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
297	* - Italy: 20F10/JH-E1, 20F12/JH-E6
298	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
299	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
300	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
301	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
302	* - Santa Ana: 40F32/JH-F2, /-F3
303	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
304	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
305	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
306	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
307	* - Keene: 40FC2/DH-F2.
308	* - Richmond: 40FC2/DH-F2
309	* - Taylor: 40F82/BH-F2
310	* - Trinidad: 40F82/BH-F2
311	*
312	* - 65nm:
313	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
314	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
315	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
316	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
317	* - Sherman: /-G1, 70FC2/DH-G2.
318	* - Huron: 70FF2/DH-G2.
319	*/
320	if (bModel < 0x10)
321	return kCpumMicroarch_AMD_K8_130nm;
322	if (bModel >= 0x60 && bModel < 0x80)
323	return kCpumMicroarch_AMD_K8_65nm;
324	if (bModel >= 0x40)
325	return kCpumMicroarch_AMD_K8_90nm_AMDV;
326	switch (bModel)
327	{
328	case 0x21:
329	case 0x23:
330	case 0x2b:
331	case 0x2f:
332	case 0x37:
333	case 0x3f:
334	return kCpumMicroarch_AMD_K8_90nm_DualCore;
335	}
336	return kCpumMicroarch_AMD_K8_90nm;
337	case 0x10:
338	return kCpumMicroarch_AMD_K10;
339	case 0x11:
340	return kCpumMicroarch_AMD_K10_Lion;
341	case 0x12:
342	return kCpumMicroarch_AMD_K10_Llano;
343	case 0x14:
344	return kCpumMicroarch_AMD_Bobcat;
345	case 0x15:
346	switch (bModel)
347	{
348	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
349	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
350	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
351	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
352	case 0x11: /* ?? */
353	case 0x12: /* ?? */
354	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
355	}
356	return kCpumMicroarch_AMD_15h_Unknown;
357	case 0x16:
358	return kCpumMicroarch_AMD_Jaguar;
359	case 0x17:
360	return kCpumMicroarch_AMD_Zen_Ryzen;
361	}
362	return kCpumMicroarch_AMD_Unknown;
363	}
364
365	if (enmVendor == CPUMCPUVENDOR_INTEL)
366	{
367	switch (bFamily)
368	{
369	case 3:
370	return kCpumMicroarch_Intel_80386;
371	case 4:
372	return kCpumMicroarch_Intel_80486;
373	case 5:
374	return kCpumMicroarch_Intel_P5;
375	case 6:
376	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
377	{
378	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
379	if (enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake)
380	{
381	if (bStepping >= 0xa && bStepping <= 0xc)
382	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
383	else if (bStepping >= 0xc)
384	enmMicroArch = kCpumMicroarch_Intel_Core7_WhiskeyLake;
385	}
386	else if ( enmMicroArch == kCpumMicroarch_Intel_Core7_Skylake
387	&& bModel == 0x55
388	&& bStepping >= 5)
389	enmMicroArch = kCpumMicroarch_Intel_Core7_CascadeLake;
390	return enmMicroArch;
391	}
392	return kCpumMicroarch_Intel_Atom_Unknown;
393	case 15:
394	switch (bModel)
395	{
396	case 0: return kCpumMicroarch_Intel_NB_Willamette;
397	case 1: return kCpumMicroarch_Intel_NB_Willamette;
398	case 2: return kCpumMicroarch_Intel_NB_Northwood;
399	case 3: return kCpumMicroarch_Intel_NB_Prescott;
400	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
401	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
402	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
403	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
404	default: return kCpumMicroarch_Intel_NB_Unknown;
405	}
406	break;
407	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
408	case 0:
409	return kCpumMicroarch_Intel_8086;
410	case 1:
411	return kCpumMicroarch_Intel_80186;
412	case 2:
413	return kCpumMicroarch_Intel_80286;
414	}
415	return kCpumMicroarch_Intel_Unknown;
416	}
417
418	if (enmVendor == CPUMCPUVENDOR_VIA)
419	{
420	switch (bFamily)
421	{
422	case 5:
423	switch (bModel)
424	{
425	case 1: return kCpumMicroarch_Centaur_C6;
426	case 4: return kCpumMicroarch_Centaur_C6;
427	case 8: return kCpumMicroarch_Centaur_C2;
428	case 9: return kCpumMicroarch_Centaur_C3;
429	}
430	break;
431
432	case 6:
433	switch (bModel)
434	{
435	case 5: return kCpumMicroarch_VIA_C3_M2;
436	case 6: return kCpumMicroarch_VIA_C3_C5A;
437	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
438	case 8: return kCpumMicroarch_VIA_C3_C5N;
439	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
440	case 10: return kCpumMicroarch_VIA_C7_C5J;
441	case 15: return kCpumMicroarch_VIA_Isaiah;
442	}
443	break;
444	}
445	return kCpumMicroarch_VIA_Unknown;
446	}
447
448	if (enmVendor == CPUMCPUVENDOR_SHANGHAI)
449	{
450	switch (bFamily)
451	{
452	case 6:
453	case 7:
454	return kCpumMicroarch_Shanghai_Wudaokou;
455	default:
456	break;
457	}
458	return kCpumMicroarch_Shanghai_Unknown;
459	}
460
461	if (enmVendor == CPUMCPUVENDOR_CYRIX)
462	{
463	switch (bFamily)
464	{
465	case 4:
466	switch (bModel)
467	{
468	case 9: return kCpumMicroarch_Cyrix_5x86;
469	}
470	break;
471
472	case 5:
473	switch (bModel)
474	{
475	case 2: return kCpumMicroarch_Cyrix_M1;
476	case 4: return kCpumMicroarch_Cyrix_MediaGX;
477	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
478	}
479	break;
480
481	case 6:
482	switch (bModel)
483	{
484	case 0: return kCpumMicroarch_Cyrix_M2;
485	}
486	break;
487
488	}
489	return kCpumMicroarch_Cyrix_Unknown;
490	}
491
492	if (enmVendor == CPUMCPUVENDOR_HYGON)
493	{
494	switch (bFamily)
495	{
496	case 0x18:
497	return kCpumMicroarch_Hygon_Dhyana;
498	default:
499	break;
500	}
501	return kCpumMicroarch_Hygon_Unknown;
502	}
503
504	return kCpumMicroarch_Unknown;
505	}
506
507
508	/**
509	* Translates a microarchitecture enum value to the corresponding string
510	* constant.
511	*
512	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
513	* NULL if the value is invalid.
514	*
515	* @param enmMicroarch The enum value to convert.
516	*/
517	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
518	{
519	switch (enmMicroarch)
520	{
521	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
522	CASE_RET_STR(kCpumMicroarch_Intel_8086);
523	CASE_RET_STR(kCpumMicroarch_Intel_80186);
524	CASE_RET_STR(kCpumMicroarch_Intel_80286);
525	CASE_RET_STR(kCpumMicroarch_Intel_80386);
526	CASE_RET_STR(kCpumMicroarch_Intel_80486);
527	CASE_RET_STR(kCpumMicroarch_Intel_P5);
528
529	CASE_RET_STR(kCpumMicroarch_Intel_P6);
530	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
531	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
532
533	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
534	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
535	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
536
537	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
538	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
539
540	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
541	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
542	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
543	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
544	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
545	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
546	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
547	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
548	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
549	CASE_RET_STR(kCpumMicroarch_Intel_Core7_WhiskeyLake);
550	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CascadeLake);
551	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
552	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CometLake);
553	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
554	CASE_RET_STR(kCpumMicroarch_Intel_Core7_RocketLake);
555	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
556	CASE_RET_STR(kCpumMicroarch_Intel_Core7_AlderLake);
557	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SapphireRapids);
558
559	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
560	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
561	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
562	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
563	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
564	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
565	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
566	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
567
568	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
569	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
570	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
571	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
572	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
573
574	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
575	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
576	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
577	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
578	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
579	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
580	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
581
582	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
583
584	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
585	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
586	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
587	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
588	CASE_RET_STR(kCpumMicroarch_AMD_K5);
589	CASE_RET_STR(kCpumMicroarch_AMD_K6);
590
591	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
592	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
593	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
594	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
595	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
596	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
597	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
598
599	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
600	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
601	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
602	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
603	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
604
605	CASE_RET_STR(kCpumMicroarch_AMD_K10);
606	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
607	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
608	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
609	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
610
611	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
612	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
613	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
614	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
615	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
616
617	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
618
619	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
620
621	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
622
623	CASE_RET_STR(kCpumMicroarch_Hygon_Dhyana);
624	CASE_RET_STR(kCpumMicroarch_Hygon_Unknown);
625
626	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
627	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
628	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
629	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
630	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
631	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
632	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
633	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
634	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
635	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
636	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
637	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
638	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
639
640	CASE_RET_STR(kCpumMicroarch_Shanghai_Wudaokou);
641	CASE_RET_STR(kCpumMicroarch_Shanghai_Unknown);
642
643	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
644	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
645	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
646	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
647	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
648	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
649
650	CASE_RET_STR(kCpumMicroarch_NEC_V20);
651	CASE_RET_STR(kCpumMicroarch_NEC_V30);
652
653	CASE_RET_STR(kCpumMicroarch_Unknown);
654
655	#undef CASE_RET_STR
656	case kCpumMicroarch_Invalid:
657	case kCpumMicroarch_Intel_End:
658	case kCpumMicroarch_Intel_Core2_End:
659	case kCpumMicroarch_Intel_Core7_End:
660	case kCpumMicroarch_Intel_Atom_End:
661	case kCpumMicroarch_Intel_P6_Core_Atom_End:
662	case kCpumMicroarch_Intel_Phi_End:
663	case kCpumMicroarch_Intel_NB_End:
664	case kCpumMicroarch_AMD_K7_End:
665	case kCpumMicroarch_AMD_K8_End:
666	case kCpumMicroarch_AMD_15h_End:
667	case kCpumMicroarch_AMD_16h_End:
668	case kCpumMicroarch_AMD_Zen_End:
669	case kCpumMicroarch_AMD_End:
670	case kCpumMicroarch_Hygon_End:
671	case kCpumMicroarch_VIA_End:
672	case kCpumMicroarch_Shanghai_End:
673	case kCpumMicroarch_Cyrix_End:
674	case kCpumMicroarch_NEC_End:
675	case kCpumMicroarch_32BitHack:
676	break;
677	/* no default! */
678	}
679
680	return NULL;
681	}
682
683
684	/**
685	* Determins the host CPU MXCSR mask.
686	*
687	* @returns MXCSR mask.
688	*/
689	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
690	{
691	if ( ASMHasCpuId()
692	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
693	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
694	{
695	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
696	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
697	RT_ZERO(*pState);
698	ASMFxSave(pState);
699	if (pState->MXCSR_MASK == 0)
700	return 0xffbf;
701	return pState->MXCSR_MASK;
702	}
703	return 0;
704	}
705
706
707	/**
708	* Gets a matching leaf in the CPUID leaf array.
709	*
710	* @returns Pointer to the matching leaf, or NULL if not found.
711	* @param paLeaves The CPUID leaves to search. This is sorted.
712	* @param cLeaves The number of leaves in the array.
713	* @param uLeaf The leaf to locate.
714	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
715	*/
716	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
717	{
718	/* Lazy bird does linear lookup here since this is only used for the
719	occational CPUID overrides. */
720	for (uint32_t i = 0; i < cLeaves; i++)
721	if ( paLeaves[i].uLeaf == uLeaf
722	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
723	return &paLeaves[i];
724	return NULL;
725	}
726
727
728	#ifndef IN_VBOX_CPU_REPORT
729	/**
730	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
731	*
732	* @returns true if found, false it not.
733	* @param paLeaves The CPUID leaves to search. This is sorted.
734	* @param cLeaves The number of leaves in the array.
735	* @param uLeaf The leaf to locate.
736	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
737	* @param pLegacy The legacy output leaf.
738	*/
739	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
740	PCPUMCPUID pLegacy)
741	{
742	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
743	if (pLeaf)
744	{
745	pLegacy->uEax = pLeaf->uEax;
746	pLegacy->uEbx = pLeaf->uEbx;
747	pLegacy->uEcx = pLeaf->uEcx;
748	pLegacy->uEdx = pLeaf->uEdx;
749	return true;
750	}
751	return false;
752	}
753	#endif /* IN_VBOX_CPU_REPORT */
754
755
756	/**
757	* Ensures that the CPUID leaf array can hold one more leaf.
758	*
759	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
760	* failure.
761	* @param pVM The cross context VM structure. If NULL, use
762	* the process heap, otherwise the VM's hyper heap.
763	* @param ppaLeaves Pointer to the variable holding the array pointer
764	* (input/output).
765	* @param cLeaves The current array size.
766	*
767	* @remarks This function will automatically update the R0 and RC pointers when
768	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
769	* be the corresponding VM's CPUID arrays (which is asserted).
770	*/
771	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
772	{
773	/*
774	* If pVM is not specified, we're on the regular heap and can waste a
775	* little space to speed things up.
776	*/
777	uint32_t cAllocated;
778	if (!pVM)
779	{
780	cAllocated = RT_ALIGN(cLeaves, 16);
781	if (cLeaves + 1 > cAllocated)
782	{
783	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
784	if (pvNew)
785	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
786	else
787	{
788	RTMemFree(*ppaLeaves);
789	*ppaLeaves = NULL;
790	}
791	}
792	}
793	/*
794	* Otherwise, we're on the hyper heap and are probably just inserting
795	* one or two leaves and should conserve space.
796	*/
797	else
798	{
799	#ifdef IN_VBOX_CPU_REPORT
800	AssertReleaseFailed();
801	#else
802	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
803	Assert(*ppaLeaves == pVM->cpum.s.GuestInfo.aCpuIdLeaves);
804	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
805
806	if (cLeaves + 1 <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves))
807	{ }
808	else
809	{
810	*ppaLeaves = NULL;
811	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: Out of CPUID space!\n"));
812	}
813	#endif
814	}
815	return *ppaLeaves;
816	}
817
818
819	/**
820	* Append a CPUID leaf or sub-leaf.
821	*
822	* ASSUMES linear insertion order, so we'll won't need to do any searching or
823	* replace anything. Use cpumR3CpuIdInsert() for those cases.
824	*
825	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
826	* the caller need do no more work.
827	* @param ppaLeaves Pointer to the pointer to the array of sorted
828	* CPUID leaves and sub-leaves.
829	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
830	* @param uLeaf The leaf we're adding.
831	* @param uSubLeaf The sub-leaf number.
832	* @param fSubLeafMask The sub-leaf mask.
833	* @param uEax The EAX value.
834	* @param uEbx The EBX value.
835	* @param uEcx The ECX value.
836	* @param uEdx The EDX value.
837	* @param fFlags The flags.
838	*/
839	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
840	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
841	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
842	{
843	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
844	return VERR_NO_MEMORY;
845
846	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
847	Assert( *pcLeaves == 0
848	\|\| pNew[-1].uLeaf < uLeaf
849	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
850
851	pNew->uLeaf = uLeaf;
852	pNew->uSubLeaf = uSubLeaf;
853	pNew->fSubLeafMask = fSubLeafMask;
854	pNew->uEax = uEax;
855	pNew->uEbx = uEbx;
856	pNew->uEcx = uEcx;
857	pNew->uEdx = uEdx;
858	pNew->fFlags = fFlags;
859
860	*pcLeaves += 1;
861	return VINF_SUCCESS;
862	}
863
864
865	/**
866	* Checks that we've updated the CPUID leaves array correctly.
867	*
868	* This is a no-op in non-strict builds.
869	*
870	* @param paLeaves The leaves array.
871	* @param cLeaves The number of leaves.
872	*/
873	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
874	{
875	#ifdef VBOX_STRICT
876	for (uint32_t i = 1; i < cLeaves; i++)
877	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
878	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
879	else
880	{
881	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
882	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
883	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
884	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
885	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
886	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
887	}
888	#else
889	NOREF(paLeaves);
890	NOREF(cLeaves);
891	#endif
892	}
893
894
895	/**
896	* Inserts a CPU ID leaf, replacing any existing ones.
897	*
898	* When inserting a simple leaf where we already got a series of sub-leaves with
899	* the same leaf number (eax), the simple leaf will replace the whole series.
900	*
901	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
902	* host-context heap and has only been allocated/reallocated by the
903	* cpumR3CpuIdEnsureSpace function.
904	*
905	* @returns VBox status code.
906	* @param pVM The cross context VM structure. If NULL, use
907	* the process heap, otherwise the VM's hyper heap.
908	* @param ppaLeaves Pointer to the pointer to the array of sorted
909	* CPUID leaves and sub-leaves. Must be NULL if using
910	* the hyper heap.
911	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
912	* be NULL if using the hyper heap.
913	* @param pNewLeaf Pointer to the data of the new leaf we're about to
914	* insert.
915	*/
916	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
917	{
918	/*
919	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
920	*/
921	if (pVM)
922	{
923	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
924	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
925	AssertReturn(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 == pVM->cpum.s.GuestInfo.aCpuIdLeaves, VERR_INVALID_PARAMETER);
926
927	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
928	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
929	}
930
931	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
932	uint32_t cLeaves = *pcLeaves;
933
934	/*
935	* Validate the new leaf a little.
936	*/
937	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
938	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
939	VERR_INVALID_FLAGS);
940	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
941	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
942	VERR_INVALID_PARAMETER);
943	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
944	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
945	VERR_INVALID_PARAMETER);
946	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
947	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
948	VERR_INVALID_PARAMETER);
949
950	/*
951	* Find insertion point. The lazy bird uses the same excuse as in
952	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
953	*/
954	uint32_t i;
955	if ( cLeaves > 0
956	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
957	{
958	/* Add at end. */
959	i = cLeaves;
960	}
961	else if ( cLeaves > 0
962	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
963	{
964	/* Either replacing the last leaf or dealing with sub-leaves. Spool
965	back to the first sub-leaf to pretend we did the linear search. */
966	i = cLeaves - 1;
967	while ( i > 0
968	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
969	i--;
970	}
971	else
972	{
973	/* Linear search from the start. */
974	i = 0;
975	while ( i < cLeaves
976	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
977	i++;
978	}
979	if ( i < cLeaves
980	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
981	{
982	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
983	{
984	/*
985	* The sub-leaf mask differs, replace all existing leaves with the
986	* same leaf number.
987	*/
988	uint32_t c = 1;
989	while ( i + c < cLeaves
990	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
991	c++;
992	if (c > 1 && i + c < cLeaves)
993	{
994	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
995	*pcLeaves = cLeaves -= c - 1;
996	}
997
998	paLeaves[i] = *pNewLeaf;
999	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1000	return VINF_SUCCESS;
1001	}
1002
1003	/* Find sub-leaf insertion point. */
1004	while ( i < cLeaves
1005	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
1006	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
1007	i++;
1008
1009	/*
1010	* If we've got an exactly matching leaf, replace it.
1011	*/
1012	if ( i < cLeaves
1013	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
1014	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
1015	{
1016	paLeaves[i] = *pNewLeaf;
1017	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1018	return VINF_SUCCESS;
1019	}
1020	}
1021
1022	/*
1023	* Adding a new leaf at 'i'.
1024	*/
1025	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
1026	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
1027	if (!paLeaves)
1028	return VERR_NO_MEMORY;
1029
1030	if (i < cLeaves)
1031	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
1032	*pcLeaves += 1;
1033	paLeaves[i] = *pNewLeaf;
1034
1035	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1036	return VINF_SUCCESS;
1037	}
1038
1039
1040	#ifndef IN_VBOX_CPU_REPORT
1041	/**
1042	* Removes a range of CPUID leaves.
1043	*
1044	* This will not reallocate the array.
1045	*
1046	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1047	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1048	* @param uFirst The first leaf.
1049	* @param uLast The last leaf.
1050	*/
1051	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1052	{
1053	uint32_t cLeaves = *pcLeaves;
1054
1055	Assert(uFirst <= uLast);
1056
1057	/*
1058	* Find the first one.
1059	*/
1060	uint32_t iFirst = 0;
1061	while ( iFirst < cLeaves
1062	&& paLeaves[iFirst].uLeaf < uFirst)
1063	iFirst++;
1064
1065	/*
1066	* Find the end (last + 1).
1067	*/
1068	uint32_t iEnd = iFirst;
1069	while ( iEnd < cLeaves
1070	&& paLeaves[iEnd].uLeaf <= uLast)
1071	iEnd++;
1072
1073	/*
1074	* Adjust the array if anything needs removing.
1075	*/
1076	if (iFirst < iEnd)
1077	{
1078	if (iEnd < cLeaves)
1079	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1080	*pcLeaves = cLeaves -= (iEnd - iFirst);
1081	}
1082
1083	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1084	}
1085	#endif /* IN_VBOX_CPU_REPORT */
1086
1087
1088	/**
1089	* Checks if ECX make a difference when reading a given CPUID leaf.
1090	*
1091	* @returns @c true if it does, @c false if it doesn't.
1092	* @param uLeaf The leaf we're reading.
1093	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1094	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1095	* final sub-leaf (for leaf 0xb only).
1096	*/
1097	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1098	{
1099	*pfFinalEcxUnchanged = false;
1100
1101	uint32_t auCur[4];
1102	uint32_t auPrev[4];
1103	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1104
1105	/* Look for sub-leaves. */
1106	uint32_t uSubLeaf = 1;
1107	for (;;)
1108	{
1109	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1110	if (memcmp(auCur, auPrev, sizeof(auCur)))
1111	break;
1112
1113	/* Advance / give up. */
1114	uSubLeaf++;
1115	if (uSubLeaf >= 64)
1116	{
1117	*pcSubLeaves = 1;
1118	return false;
1119	}
1120	}
1121
1122	/* Count sub-leaves. */
1123	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1124	uint32_t cRepeats = 0;
1125	uSubLeaf = 0;
1126	for (;;)
1127	{
1128	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1129
1130	/* Figuring out when to stop isn't entirely straight forward as we need
1131	to cover undocumented behavior up to a point and implementation shortcuts. */
1132
1133	/* 1. Look for more than 4 repeating value sets. */
1134	if ( auCur[0] == auPrev[0]
1135	&& auCur[1] == auPrev[1]
1136	&& ( auCur[2] == auPrev[2]
1137	\|\| ( auCur[2] == uSubLeaf
1138	&& auPrev[2] == uSubLeaf - 1) )
1139	&& auCur[3] == auPrev[3])
1140	{
1141	if ( uLeaf != 0xd
1142	\|\| uSubLeaf >= 64
1143	\|\| ( auCur[0] == 0
1144	&& auCur[1] == 0
1145	&& auCur[2] == 0
1146	&& auCur[3] == 0
1147	&& auPrev[2] == 0) )
1148	cRepeats++;
1149	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1150	break;
1151	}
1152	else
1153	cRepeats = 0;
1154
1155	/* 2. Look for zero values. */
1156	if ( auCur[0] == 0
1157	&& auCur[1] == 0
1158	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1159	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1160	&& uSubLeaf >= cMinLeaves)
1161	{
1162	cRepeats = 0;
1163	break;
1164	}
1165
1166	/* 3. Leaf 0xb level type 0 check. */
1167	if ( uLeaf == 0xb
1168	&& (auCur[2] & 0xff00) == 0
1169	&& (auPrev[2] & 0xff00) == 0)
1170	{
1171	cRepeats = 0;
1172	break;
1173	}
1174
1175	/* 99. Give up. */
1176	if (uSubLeaf >= 128)
1177	{
1178	#ifndef IN_VBOX_CPU_REPORT
1179	/* Ok, limit it according to the documentation if possible just to
1180	avoid annoying users with these detection issues. */
1181	uint32_t cDocLimit = UINT32_MAX;
1182	if (uLeaf == 0x4)
1183	cDocLimit = 4;
1184	else if (uLeaf == 0x7)
1185	cDocLimit = 1;
1186	else if (uLeaf == 0xd)
1187	cDocLimit = 63;
1188	else if (uLeaf == 0xf)
1189	cDocLimit = 2;
1190	if (cDocLimit != UINT32_MAX)
1191	{
1192	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1193	*pcSubLeaves = cDocLimit + 3;
1194	return true;
1195	}
1196	#endif
1197	*pcSubLeaves = UINT32_MAX;
1198	return true;
1199	}
1200
1201	/* Advance. */
1202	uSubLeaf++;
1203	memcpy(auPrev, auCur, sizeof(auCur));
1204	}
1205
1206	/* Standard exit. */
1207	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1208	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1209	if (*pcSubLeaves == 0)
1210	*pcSubLeaves = 1;
1211	return true;
1212	}
1213
1214
1215	/**
1216	* Gets a CPU ID leaf.
1217	*
1218	* @returns VBox status code.
1219	* @param pVM The cross context VM structure.
1220	* @param pLeaf Where to store the found leaf.
1221	* @param uLeaf The leaf to locate.
1222	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1223	*/
1224	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1225	{
1226	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1227	uLeaf, uSubLeaf);
1228	if (pcLeaf)
1229	{
1230	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1231	return VINF_SUCCESS;
1232	}
1233
1234	return VERR_NOT_FOUND;
1235	}
1236
1237
1238	/**
1239	* Inserts a CPU ID leaf, replacing any existing ones.
1240	*
1241	* @returns VBox status code.
1242	* @param pVM The cross context VM structure.
1243	* @param pNewLeaf Pointer to the leaf being inserted.
1244	*/
1245	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1246	{
1247	/*
1248	* Validate parameters.
1249	*/
1250	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1251	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1252
1253	/*
1254	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1255	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1256	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1257	*/
1258	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1259	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1260	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1261	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1262	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1263	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1264	{
1265	return VERR_NOT_SUPPORTED;
1266	}
1267
1268	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1269	}
1270
1271	/**
1272	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1273	*
1274	* @returns VBox status code.
1275	* @param ppaLeaves Where to return the array pointer on success.
1276	* Use RTMemFree to release.
1277	* @param pcLeaves Where to return the size of the array on
1278	* success.
1279	*/
1280	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1281	{
1282	*ppaLeaves = NULL;
1283	*pcLeaves = 0;
1284
1285	/*
1286	* Try out various candidates. This must be sorted!
1287	*/
1288	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1289	{
1290	{ UINT32_C(0x00000000), false },
1291	{ UINT32_C(0x10000000), false },
1292	{ UINT32_C(0x20000000), false },
1293	{ UINT32_C(0x30000000), false },
1294	{ UINT32_C(0x40000000), false },
1295	{ UINT32_C(0x50000000), false },
1296	{ UINT32_C(0x60000000), false },
1297	{ UINT32_C(0x70000000), false },
1298	{ UINT32_C(0x80000000), false },
1299	{ UINT32_C(0x80860000), false },
1300	{ UINT32_C(0x8ffffffe), true },
1301	{ UINT32_C(0x8fffffff), true },
1302	{ UINT32_C(0x90000000), false },
1303	{ UINT32_C(0xa0000000), false },
1304	{ UINT32_C(0xb0000000), false },
1305	{ UINT32_C(0xc0000000), false },
1306	{ UINT32_C(0xd0000000), false },
1307	{ UINT32_C(0xe0000000), false },
1308	{ UINT32_C(0xf0000000), false },
1309	};
1310
1311	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1312	{
1313	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1314	uint32_t uEax, uEbx, uEcx, uEdx;
1315	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1316
1317	/*
1318	* Does EAX look like a typical leaf count value?
1319	*/
1320	if ( uEax > uLeaf
1321	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1322	{
1323	/* Yes, dump them. */
1324	uint32_t cLeaves = uEax - uLeaf + 1;
1325	while (cLeaves-- > 0)
1326	{
1327	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1328
1329	uint32_t fFlags = 0;
1330
1331	/* There are currently three known leaves containing an APIC ID
1332	that needs EMT specific attention */
1333	if (uLeaf == 1)
1334	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1335	else if (uLeaf == 0xb && uEcx != 0)
1336	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1337	else if ( uLeaf == UINT32_C(0x8000001e)
1338	&& ( uEax
1339	\|\| uEbx
1340	\|\| uEdx
1341	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1342	\|\| ASMIsHygonCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1343	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1344
1345	/* The APIC bit is per-VCpu and needs flagging. */
1346	if (uLeaf == 1)
1347	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1348	else if ( uLeaf == UINT32_C(0x80000001)
1349	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1350	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1351	\|\| ASMIsHygonCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1352	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1353
1354	/* Check three times here to reduce the chance of CPU migration
1355	resulting in false positives with things like the APIC ID. */
1356	uint32_t cSubLeaves;
1357	bool fFinalEcxUnchanged;
1358	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1359	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1360	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1361	{
1362	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1363	{
1364	/* This shouldn't happen. But in case it does, file all
1365	relevant details in the release log. */
1366	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1367	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1368	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1369	{
1370	uint32_t auTmp[4];
1371	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1372	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1373	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1374	}
1375	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1376	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1377	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1378	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1379	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1380	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1381	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1382	}
1383
1384	if (fFinalEcxUnchanged)
1385	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1386
1387	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1388	{
1389	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1390	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1391	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1392	if (RT_FAILURE(rc))
1393	return rc;
1394	}
1395	}
1396	else
1397	{
1398	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1399	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1400	if (RT_FAILURE(rc))
1401	return rc;
1402	}
1403
1404	/* next */
1405	uLeaf++;
1406	}
1407	}
1408	/*
1409	* Special CPUIDs needs special handling as they don't follow the
1410	* leaf count principle used above.
1411	*/
1412	else if (s_aCandidates[iOuter].fSpecial)
1413	{
1414	bool fKeep = false;
1415	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1416	fKeep = true;
1417	else if ( uLeaf == 0x8fffffff
1418	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1419	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1420	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1421	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1422	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1423	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1424	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1425	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1426	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1427	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1428	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1429	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1430	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1431	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1432	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1433	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1434	fKeep = true;
1435	if (fKeep)
1436	{
1437	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1438	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1439	if (RT_FAILURE(rc))
1440	return rc;
1441	}
1442	}
1443	}
1444
1445	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1446	return VINF_SUCCESS;
1447	}
1448
1449
1450	/**
1451	* Determines the method the CPU uses to handle unknown CPUID leaves.
1452	*
1453	* @returns VBox status code.
1454	* @param penmUnknownMethod Where to return the method.
1455	* @param pDefUnknown Where to return default unknown values. This
1456	* will be set, even if the resulting method
1457	* doesn't actually needs it.
1458	*/
1459	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1460	{
1461	uint32_t uLastStd = ASMCpuId_EAX(0);
1462	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1463	if (!ASMIsValidExtRange(uLastExt))
1464	uLastExt = 0x80000000;
1465
1466	uint32_t auChecks[] =
1467	{
1468	uLastStd + 1,
1469	uLastStd + 5,
1470	uLastStd + 8,
1471	uLastStd + 32,
1472	uLastStd + 251,
1473	uLastExt + 1,
1474	uLastExt + 8,
1475	uLastExt + 15,
1476	uLastExt + 63,
1477	uLastExt + 255,
1478	0x7fbbffcc,
1479	0x833f7872,
1480	0xefff2353,
1481	0x35779456,
1482	0x1ef6d33e,
1483	};
1484
1485	static const uint32_t s_auValues[] =
1486	{
1487	0xa95d2156,
1488	0x00000001,
1489	0x00000002,
1490	0x00000008,
1491	0x00000000,
1492	0x55773399,
1493	0x93401769,
1494	0x12039587,
1495	};
1496
1497	/*
1498	* Simple method, all zeros.
1499	*/
1500	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1501	pDefUnknown->uEax = 0;
1502	pDefUnknown->uEbx = 0;
1503	pDefUnknown->uEcx = 0;
1504	pDefUnknown->uEdx = 0;
1505
1506	/*
1507	* Intel has been observed returning the last standard leaf.
1508	*/
1509	uint32_t auLast[4];
1510	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1511
1512	uint32_t cChecks = RT_ELEMENTS(auChecks);
1513	while (cChecks > 0)
1514	{
1515	uint32_t auCur[4];
1516	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1517	if (memcmp(auCur, auLast, sizeof(auCur)))
1518	break;
1519	cChecks--;
1520	}
1521	if (cChecks == 0)
1522	{
1523	/* Now, what happens when the input changes? Esp. ECX. */
1524	uint32_t cTotal = 0;
1525	uint32_t cSame = 0;
1526	uint32_t cLastWithEcx = 0;
1527	uint32_t cNeither = 0;
1528	uint32_t cValues = RT_ELEMENTS(s_auValues);
1529	while (cValues > 0)
1530	{
1531	uint32_t uValue = s_auValues[cValues - 1];
1532	uint32_t auLastWithEcx[4];
1533	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1534	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1535
1536	cChecks = RT_ELEMENTS(auChecks);
1537	while (cChecks > 0)
1538	{
1539	uint32_t auCur[4];
1540	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1541	if (!memcmp(auCur, auLast, sizeof(auCur)))
1542	{
1543	cSame++;
1544	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1545	cLastWithEcx++;
1546	}
1547	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1548	cLastWithEcx++;
1549	else
1550	cNeither++;
1551	cTotal++;
1552	cChecks--;
1553	}
1554	cValues--;
1555	}
1556
1557	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1558	if (cSame == cTotal)
1559	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1560	else if (cLastWithEcx == cTotal)
1561	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1562	else
1563	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1564	pDefUnknown->uEax = auLast[0];
1565	pDefUnknown->uEbx = auLast[1];
1566	pDefUnknown->uEcx = auLast[2];
1567	pDefUnknown->uEdx = auLast[3];
1568	return VINF_SUCCESS;
1569	}
1570
1571	/*
1572	* Unchanged register values?
1573	*/
1574	cChecks = RT_ELEMENTS(auChecks);
1575	while (cChecks > 0)
1576	{
1577	uint32_t const uLeaf = auChecks[cChecks - 1];
1578	uint32_t cValues = RT_ELEMENTS(s_auValues);
1579	while (cValues > 0)
1580	{
1581	uint32_t uValue = s_auValues[cValues - 1];
1582	uint32_t auCur[4];
1583	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1584	if ( auCur[0] != uLeaf
1585	\|\| auCur[1] != uValue
1586	\|\| auCur[2] != uValue
1587	\|\| auCur[3] != uValue)
1588	break;
1589	cValues--;
1590	}
1591	if (cValues != 0)
1592	break;
1593	cChecks--;
1594	}
1595	if (cChecks == 0)
1596	{
1597	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1598	return VINF_SUCCESS;
1599	}
1600
1601	/*
1602	* Just go with the simple method.
1603	*/
1604	return VINF_SUCCESS;
1605	}
1606
1607
1608	/**
1609	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1610	*
1611	* @returns Read only name string.
1612	* @param enmUnknownMethod The method to translate.
1613	*/
1614	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1615	{
1616	switch (enmUnknownMethod)
1617	{
1618	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1619	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1620	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1621	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1622
1623	case CPUMUNKNOWNCPUID_INVALID:
1624	case CPUMUNKNOWNCPUID_END:
1625	case CPUMUNKNOWNCPUID_32BIT_HACK:
1626	break;
1627	}
1628	return "Invalid-unknown-CPUID-method";
1629	}
1630
1631
1632	/**
1633	* Detect the CPU vendor give n the
1634	*
1635	* @returns The vendor.
1636	* @param uEAX EAX from CPUID(0).
1637	* @param uEBX EBX from CPUID(0).
1638	* @param uECX ECX from CPUID(0).
1639	* @param uEDX EDX from CPUID(0).
1640	*/
1641	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1642	{
1643	if (ASMIsValidStdRange(uEAX))
1644	{
1645	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1646	return CPUMCPUVENDOR_AMD;
1647
1648	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1649	return CPUMCPUVENDOR_INTEL;
1650
1651	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1652	return CPUMCPUVENDOR_VIA;
1653
1654	if (ASMIsShanghaiCpuEx(uEBX, uECX, uEDX))
1655	return CPUMCPUVENDOR_SHANGHAI;
1656
1657	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1658	&& uECX == UINT32_C(0x64616574)
1659	&& uEDX == UINT32_C(0x736E4978))
1660	return CPUMCPUVENDOR_CYRIX;
1661
1662	if (ASMIsHygonCpuEx(uEBX, uECX, uEDX))
1663	return CPUMCPUVENDOR_HYGON;
1664
1665	/* "Geode by NSC", example: family 5, model 9. */
1666
1667	/** @todo detect the other buggers... */
1668	}
1669
1670	return CPUMCPUVENDOR_UNKNOWN;
1671	}
1672
1673
1674	/**
1675	* Translates a CPU vendor enum value into the corresponding string constant.
1676	*
1677	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1678	* value name. This can be useful when generating code.
1679	*
1680	* @returns Read only name string.
1681	* @param enmVendor The CPU vendor value.
1682	*/
1683	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1684	{
1685	switch (enmVendor)
1686	{
1687	case CPUMCPUVENDOR_INTEL: return "INTEL";
1688	case CPUMCPUVENDOR_AMD: return "AMD";
1689	case CPUMCPUVENDOR_VIA: return "VIA";
1690	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1691	case CPUMCPUVENDOR_SHANGHAI: return "SHANGHAI";
1692	case CPUMCPUVENDOR_HYGON: return "HYGON";
1693	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1694
1695	case CPUMCPUVENDOR_INVALID:
1696	case CPUMCPUVENDOR_32BIT_HACK:
1697	break;
1698	}
1699	return "Invalid-cpu-vendor";
1700	}
1701
1702
1703	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1704	{
1705	/* Could do binary search, doing linear now because I'm lazy. */
1706	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1707	while (cLeaves-- > 0)
1708	{
1709	if (pLeaf->uLeaf == uLeaf)
1710	return pLeaf;
1711	pLeaf++;
1712	}
1713	return NULL;
1714	}
1715
1716
1717	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1718	{
1719	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1720	if ( !pLeaf
1721	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1722	return pLeaf;
1723
1724	/* Linear sub-leaf search. Lazy as usual. */
1725	cLeaves -= pLeaf - paLeaves;
1726	while ( cLeaves-- > 0
1727	&& pLeaf->uLeaf == uLeaf)
1728	{
1729	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1730	return pLeaf;
1731	pLeaf++;
1732	}
1733
1734	return NULL;
1735	}
1736
1737
1738	static void cpumR3ExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, PCPUMFEATURES pFeatures)
1739	{
1740	Assert(pVmxMsrs);
1741	Assert(pFeatures);
1742	Assert(pFeatures->fVmx);
1743
1744	/* Basic information. */
1745	{
1746	uint64_t const u64Basic = pVmxMsrs->u64Basic;
1747	pFeatures->fVmxInsOutInfo = RT_BF_GET(u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1748	}
1749
1750	/* Pin-based VM-execution controls. */
1751	{
1752	uint32_t const fPinCtls = pVmxMsrs->PinCtls.n.allowed1;
1753	pFeatures->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1754	pFeatures->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1755	pFeatures->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1756	pFeatures->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1757	pFeatures->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1758	}
1759
1760	/* Processor-based VM-execution controls. */
1761	{
1762	uint32_t const fProcCtls = pVmxMsrs->ProcCtls.n.allowed1;
1763	pFeatures->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1764	pFeatures->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1765	pFeatures->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1766	pFeatures->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1767	pFeatures->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1768	pFeatures->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1769	pFeatures->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1770	pFeatures->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1771	pFeatures->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1772	pFeatures->fVmxTertiaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TERTIARY_CTLS);
1773	pFeatures->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1774	pFeatures->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1775	pFeatures->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1776	pFeatures->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1777	pFeatures->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1778	pFeatures->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1779	pFeatures->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1780	pFeatures->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1781	pFeatures->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1782	pFeatures->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1783	pFeatures->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1784	pFeatures->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1785	}
1786
1787	/* Secondary processor-based VM-execution controls. */
1788	{
1789	uint32_t const fProcCtls2 = pFeatures->fVmxSecondaryExecCtls ? pVmxMsrs->ProcCtls2.n.allowed1 : 0;
1790	pFeatures->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1791	pFeatures->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1792	pFeatures->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1793	pFeatures->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1794	pFeatures->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1795	pFeatures->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1796	pFeatures->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1797	pFeatures->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1798	pFeatures->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1799	pFeatures->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1800	pFeatures->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1801	pFeatures->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1802	pFeatures->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1803	pFeatures->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1804	pFeatures->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1805	pFeatures->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1806	pFeatures->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1807	pFeatures->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE);
1808	pFeatures->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1809	pFeatures->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1810	}
1811
1812	/* Tertiary processor-based VM-execution controls. */
1813	{
1814	uint64_t const fProcCtls3 = pFeatures->fVmxTertiaryExecCtls ? pVmxMsrs->u64ProcCtls3 : 0;
1815	pFeatures->fVmxLoadIwKeyExit = RT_BOOL(fProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT);
1816	}
1817
1818	/* VM-exit controls. */
1819	{
1820	uint32_t const fExitCtls = pVmxMsrs->ExitCtls.n.allowed1;
1821	pFeatures->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1822	pFeatures->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1823	pFeatures->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1824	pFeatures->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1825	pFeatures->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1826	pFeatures->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1827	pFeatures->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1828	pFeatures->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1829	}
1830
1831	/* VM-entry controls. */
1832	{
1833	uint32_t const fEntryCtls = pVmxMsrs->EntryCtls.n.allowed1;
1834	pFeatures->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1835	pFeatures->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1836	pFeatures->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1837	pFeatures->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1838	}
1839
1840	/* Miscellaneous data. */
1841	{
1842	uint32_t const fMiscData = pVmxMsrs->u64Misc;
1843	pFeatures->fVmxExitSaveEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_SAVE_EFER_LMA);
1844	pFeatures->fVmxIntelPt = RT_BOOL(fMiscData & VMX_MISC_INTEL_PT);
1845	pFeatures->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1846	pFeatures->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1847	}
1848	}
1849
1850
1851	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures)
1852	{
1853	Assert(pMsrs);
1854	RT_ZERO(*pFeatures);
1855	if (cLeaves >= 2)
1856	{
1857	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1858	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1859	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1860	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1861	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1862	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1863
1864	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1865	pStd0Leaf->uEbx,
1866	pStd0Leaf->uEcx,
1867	pStd0Leaf->uEdx);
1868	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1869	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1870	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1871	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1872	pFeatures->uFamily,
1873	pFeatures->uModel,
1874	pFeatures->uStepping);
1875
1876	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1877	if (pExtLeaf8)
1878	{
1879	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1880	pFeatures->cMaxLinearAddrWidth = (pExtLeaf8->uEax >> 8) & 0xff;
1881	}
1882	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1883	{
1884	pFeatures->cMaxPhysAddrWidth = 36;
1885	pFeatures->cMaxLinearAddrWidth = 36;
1886	}
1887	else
1888	{
1889	pFeatures->cMaxPhysAddrWidth = 32;
1890	pFeatures->cMaxLinearAddrWidth = 32;
1891	}
1892
1893	/* Standard features. */
1894	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1895	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1896	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1897	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1898	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1899	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1900	pFeatures->fPge = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PGE);
1901	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1902	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1903	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1904	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1905	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1906	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1907	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1908	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1909	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1910	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1911	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1912	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1913	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1914	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1915	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1916	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1917	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1918	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1919	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1920	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1921	if (pFeatures->fVmx)
1922	cpumR3ExplodeVmxFeatures(&pMsrs->hwvirt.vmx, pFeatures);
1923
1924	/* Structured extended features. */
1925	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1926	if (pSxfLeaf0)
1927	{
1928	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1929	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1930	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1931	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1932	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1933
1934	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1935	pFeatures->fIbrs = pFeatures->fIbpb;
1936	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1937	pFeatures->fFlushCmd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
1938	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1939	pFeatures->fMdsClear = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR);
1940	}
1941
1942	/* MWAIT/MONITOR leaf. */
1943	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1944	if (pMWaitLeaf)
1945	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1946	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1947
1948	/* Extended features. */
1949	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1950	if (pExtLeaf)
1951	{
1952	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1953	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1954	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1955	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1956	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1957	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1958	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1959	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1960	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1961	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1962	}
1963
1964	/* VMX (VMXON, VMCS region and related data structures) physical address width (depends on long-mode). */
1965	pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
1966
1967	if ( pExtLeaf
1968	&& ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1969	\|\| pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON))
1970	{
1971	/* AMD features. */
1972	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1973	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1974	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1975	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1976	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1977	pFeatures->fPge \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PGE);
1978	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1979	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1980	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1981	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1982	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1983	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1984	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1985	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1986	if (pFeatures->fSvm)
1987	{
1988	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1989	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1990	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1991	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1992	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1993	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1994	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1995	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1996	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1997	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1998	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1999	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
2000	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
2001	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
2002	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
2003	pFeatures->fSvmGmet = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_GMET);
2004	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
2005	}
2006	}
2007
2008	/*
2009	* Quirks.
2010	*/
2011	pFeatures->fLeakyFxSR = pExtLeaf
2012	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
2013	&& ( ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
2014	&& pFeatures->uFamily >= 6 /* K7 and up */)
2015	\|\| pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON);
2016
2017	/*
2018	* Max extended (/FPU) state.
2019	*/
2020	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
2021	if (pFeatures->fXSaveRstor)
2022	{
2023	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
2024	if (pXStateLeaf0)
2025	{
2026	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
2027	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
2028	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
2029	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
2030	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
2031	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
2032	{
2033	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
2034
2035	/* (paranoia:) */
2036	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
2037	if ( pXStateLeaf1
2038	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
2039	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
2040	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
2041	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
2042	}
2043	else
2044	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
2045	pFeatures->fXSaveRstor = 0);
2046	}
2047	else
2048	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
2049	pFeatures->fXSaveRstor = 0);
2050	}
2051	}
2052	else
2053	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
2054	return VINF_SUCCESS;
2055	}
2056
2057
2058	/*
2059	*
2060	* Init related code.
2061	* Init related code.
2062	* Init related code.
2063	*
2064	*
2065	*/
2066	#ifndef IN_VBOX_CPU_REPORT
2067
2068
2069	/**
2070	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
2071	*
2072	* This ignores the fSubLeafMask.
2073	*
2074	* @returns Pointer to the matching leaf, or NULL if not found.
2075	* @param pCpum The CPUM instance data.
2076	* @param uLeaf The leaf to locate.
2077	* @param uSubLeaf The subleaf to locate.
2078	*/
2079	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
2080	{
2081	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
2082	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
2083	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
2084	if (iEnd)
2085	{
2086	uint32_t iBegin = 0;
2087	for (;;)
2088	{
2089	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
2090	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
2091	if (uNeedle < uCur)
2092	{
2093	if (i > iBegin)
2094	iEnd = i;
2095	else
2096	break;
2097	}
2098	else if (uNeedle > uCur)
2099	{
2100	if (i + 1 < iEnd)
2101	iBegin = i + 1;
2102	else
2103	break;
2104	}
2105	else
2106	return &paLeaves[i];
2107	}
2108	}
2109	return NULL;
2110	}
2111
2112
2113	/**
2114	* Loads MSR range overrides.
2115	*
2116	* This must be called before the MSR ranges are moved from the normal heap to
2117	* the hyper heap!
2118	*
2119	* @returns VBox status code (VMSetError called).
2120	* @param pVM The cross context VM structure.
2121	* @param pMsrNode The CFGM node with the MSR overrides.
2122	*/
2123	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
2124	{
2125	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2126	{
2127	/*
2128	* Assemble a valid MSR range.
2129	*/
2130	CPUMMSRRANGE MsrRange;
2131	MsrRange.offCpumCpu = 0;
2132	MsrRange.fReserved = 0;
2133
2134	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
2135	if (RT_FAILURE(rc))
2136	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
2137
2138	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
2139	if (RT_FAILURE(rc))
2140	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
2141	MsrRange.szName, rc);
2142
2143	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
2144	if (RT_FAILURE(rc))
2145	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
2146	MsrRange.szName, rc);
2147
2148	char szType[32];
2149	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
2150	if (RT_FAILURE(rc))
2151	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
2152	MsrRange.szName, rc);
2153	if (!RTStrICmp(szType, "FixedValue"))
2154	{
2155	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
2156	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
2157
2158	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
2159	if (RT_FAILURE(rc))
2160	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
2161	MsrRange.szName, rc);
2162
2163	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
2164	if (RT_FAILURE(rc))
2165	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
2166	MsrRange.szName, rc);
2167
2168	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
2169	if (RT_FAILURE(rc))
2170	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
2171	MsrRange.szName, rc);
2172	}
2173	else
2174	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
2175	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
2176
2177	/*
2178	* Insert the range into the table (replaces/splits/shrinks existing
2179	* MSR ranges).
2180	*/
2181	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
2182	&MsrRange);
2183	if (RT_FAILURE(rc))
2184	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
2185	}
2186
2187	return VINF_SUCCESS;
2188	}
2189
2190
2191	/**
2192	* Loads CPUID leaf overrides.
2193	*
2194	* This must be called before the CPUID leaves are moved from the normal
2195	* heap to the hyper heap!
2196	*
2197	* @returns VBox status code (VMSetError called).
2198	* @param pVM The cross context VM structure.
2199	* @param pParentNode The CFGM node with the CPUID leaves.
2200	* @param pszLabel How to label the overrides we're loading.
2201	*/
2202	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2203	{
2204	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2205	{
2206	/*
2207	* Get the leaf and subleaf numbers.
2208	*/
2209	char szName[128];
2210	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2211	if (RT_FAILURE(rc))
2212	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2213
2214	/* The leaf number is either specified directly or thru the node name. */
2215	uint32_t uLeaf;
2216	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2217	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2218	{
2219	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2220	if (rc != VINF_SUCCESS)
2221	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2222	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2223	}
2224	else if (RT_FAILURE(rc))
2225	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2226	pszLabel, szName, rc);
2227
2228	uint32_t uSubLeaf;
2229	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2230	if (RT_FAILURE(rc))
2231	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2232	pszLabel, szName, rc);
2233
2234	uint32_t fSubLeafMask;
2235	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2236	if (RT_FAILURE(rc))
2237	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2238	pszLabel, szName, rc);
2239
2240	/*
2241	* Look up the specified leaf, since the output register values
2242	* defaults to any existing values. This allows overriding a single
2243	* register, without needing to know the other values.
2244	*/
2245	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2246	CPUMCPUIDLEAF Leaf;
2247	if (pLeaf)
2248	Leaf = *pLeaf;
2249	else
2250	RT_ZERO(Leaf);
2251	Leaf.uLeaf = uLeaf;
2252	Leaf.uSubLeaf = uSubLeaf;
2253	Leaf.fSubLeafMask = fSubLeafMask;
2254
2255	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2256	if (RT_FAILURE(rc))
2257	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2258	pszLabel, szName, rc);
2259	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2260	if (RT_FAILURE(rc))
2261	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2262	pszLabel, szName, rc);
2263	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2264	if (RT_FAILURE(rc))
2265	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2266	pszLabel, szName, rc);
2267	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2268	if (RT_FAILURE(rc))
2269	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2270	pszLabel, szName, rc);
2271
2272	/*
2273	* Insert the leaf into the table (replaces existing ones).
2274	*/
2275	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2276	&Leaf);
2277	if (RT_FAILURE(rc))
2278	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2279	}
2280
2281	return VINF_SUCCESS;
2282	}
2283
2284
2285
2286	/**
2287	* Fetches overrides for a CPUID leaf.
2288	*
2289	* @returns VBox status code.
2290	* @param pLeaf The leaf to load the overrides into.
2291	* @param pCfgNode The CFGM node containing the overrides
2292	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2293	* @param iLeaf The CPUID leaf number.
2294	*/
2295	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2296	{
2297	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2298	if (pLeafNode)
2299	{
2300	uint32_t u32;
2301	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2302	if (RT_SUCCESS(rc))
2303	pLeaf->uEax = u32;
2304	else
2305	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2306
2307	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2308	if (RT_SUCCESS(rc))
2309	pLeaf->uEbx = u32;
2310	else
2311	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2312
2313	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2314	if (RT_SUCCESS(rc))
2315	pLeaf->uEcx = u32;
2316	else
2317	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2318
2319	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2320	if (RT_SUCCESS(rc))
2321	pLeaf->uEdx = u32;
2322	else
2323	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2324
2325	}
2326	return VINF_SUCCESS;
2327	}
2328
2329
2330	/**
2331	* Load the overrides for a set of CPUID leaves.
2332	*
2333	* @returns VBox status code.
2334	* @param paLeaves The leaf array.
2335	* @param cLeaves The number of leaves.
2336	* @param uStart The start leaf number.
2337	* @param pCfgNode The CFGM node containing the overrides
2338	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2339	*/
2340	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2341	{
2342	for (uint32_t i = 0; i < cLeaves; i++)
2343	{
2344	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2345	if (RT_FAILURE(rc))
2346	return rc;
2347	}
2348
2349	return VINF_SUCCESS;
2350	}
2351
2352
2353	/**
2354	* Installs the CPUID leaves and explods the data into structures like
2355	* GuestFeatures and CPUMCTX::aoffXState.
2356	*
2357	* @returns VBox status code.
2358	* @param pVM The cross context VM structure.
2359	* @param pCpum The CPUM part of @a VM.
2360	* @param paLeaves The leaves. These will be copied (but not freed).
2361	* @param cLeaves The number of leaves.
2362	* @param pMsrs The MSRs.
2363	*/
2364	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
2365	{
2366	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2367
2368	/*
2369	* Install the CPUID information.
2370	*/
2371	AssertLogRelMsgReturn(cLeaves <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves),
2372	("cLeaves=%u - max %u\n", cLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves)),
2373	VERR_CPUM_IPE_1); /** @todo better status! */
2374	if (paLeaves != pCpum->GuestInfo.aCpuIdLeaves)
2375	memcpy(pCpum->GuestInfo.aCpuIdLeaves, paLeaves, cLeaves * sizeof(paLeaves[0]));
2376	pCpum->GuestInfo.paCpuIdLeavesR3 = pCpum->GuestInfo.aCpuIdLeaves;
2377	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2378
2379	/*
2380	* Update the default CPUID leaf if necessary.
2381	*/
2382	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2383	{
2384	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2385	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2386	{
2387	/* We don't use CPUID(0).eax here because of the NT hack that only
2388	changes that value without actually removing any leaves. */
2389	uint32_t i = 0;
2390	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2391	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2392	{
2393	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2394	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2395	i++;
2396	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2397	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2398	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2399	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2400	}
2401	break;
2402	}
2403	default:
2404	break;
2405	}
2406
2407	/*
2408	* Explode the guest CPU features.
2409	*/
2410	int rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
2411	&pCpum->GuestFeatures);
2412	AssertLogRelRCReturn(rc, rc);
2413
2414	/*
2415	* Adjust the scalable bus frequency according to the CPUID information
2416	* we're now using.
2417	*/
2418	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2419	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2420	? UINT64_C(100000000) /* 100MHz */
2421	: UINT64_C(133333333); /* 133MHz */
2422
2423	/*
2424	* Populate the legacy arrays. Currently used for everything, later only
2425	* for patch manager.
2426	*/
2427	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2428	{
2429	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2430	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2431	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2432	};
2433	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2434	{
2435	uint32_t cLeft = aOldRanges[i].cCpuIds;
2436	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2437	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2438	while (cLeft-- > 0)
2439	{
2440	uLeaf--;
2441	pLegacyLeaf--;
2442
2443	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2444	if (pLeaf)
2445	{
2446	pLegacyLeaf->uEax = pLeaf->uEax;
2447	pLegacyLeaf->uEbx = pLeaf->uEbx;
2448	pLegacyLeaf->uEcx = pLeaf->uEcx;
2449	pLegacyLeaf->uEdx = pLeaf->uEdx;
2450	}
2451	else
2452	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2453	}
2454	}
2455
2456	/*
2457	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2458	*/
2459	PVMCPU pVCpu0 = pVM->apCpusR3[0];
2460	memset(&pVCpu0->cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2461	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2462	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2463	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2464	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2465	{
2466	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2467	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2468	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2469	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2470	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2471	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2472	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2473	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2474	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2475	pCpum->GuestFeatures.cbMaxExtendedState),
2476	VERR_CPUM_IPE_1);
2477	pVCpu0->cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2478	}
2479
2480	/* Copy the CPU #0 data to the other CPUs. */
2481	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
2482	{
2483	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2484	memcpy(&pVCpu->cpum.s.Guest.aoffXState[0], &pVCpu0->cpum.s.Guest.aoffXState[0], sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2485	}
2486
2487	return VINF_SUCCESS;
2488	}
2489
2490
2491	/** @name Instruction Set Extension Options
2492	* @{ */
2493	/** Configuration option type (extended boolean, really). */
2494	typedef uint8_t CPUMISAEXTCFG;
2495	/** Always disable the extension. */
2496	#define CPUMISAEXTCFG_DISABLED false
2497	/** Enable the extension if it's supported by the host CPU. */
2498	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2499	/** Enable the extension if it's supported by the host CPU, but don't let
2500	* the portable CPUID feature disable it. */
2501	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2502	/** Always enable the extension. */
2503	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2504	/** @} */
2505
2506	/**
2507	* CPUID Configuration (from CFGM).
2508	*
2509	* @remarks The members aren't document since we would only be duplicating the
2510	* \@cfgm entries in cpumR3CpuIdReadConfig.
2511	*/
2512	typedef struct CPUMCPUIDCONFIG
2513	{
2514	bool fNt4LeafLimit;
2515	bool fInvariantTsc;
2516	bool fForceVme;
2517	bool fNestedHWVirt;
2518
2519	CPUMISAEXTCFG enmCmpXchg16b;
2520	CPUMISAEXTCFG enmMonitor;
2521	CPUMISAEXTCFG enmMWaitExtensions;
2522	CPUMISAEXTCFG enmSse41;
2523	CPUMISAEXTCFG enmSse42;
2524	CPUMISAEXTCFG enmAvx;
2525	CPUMISAEXTCFG enmAvx2;
2526	CPUMISAEXTCFG enmXSave;
2527	CPUMISAEXTCFG enmAesNi;
2528	CPUMISAEXTCFG enmPClMul;
2529	CPUMISAEXTCFG enmPopCnt;
2530	CPUMISAEXTCFG enmMovBe;
2531	CPUMISAEXTCFG enmRdRand;
2532	CPUMISAEXTCFG enmRdSeed;
2533	CPUMISAEXTCFG enmCLFlushOpt;
2534	CPUMISAEXTCFG enmFsGsBase;
2535	CPUMISAEXTCFG enmPcid;
2536	CPUMISAEXTCFG enmInvpcid;
2537	CPUMISAEXTCFG enmFlushCmdMsr;
2538	CPUMISAEXTCFG enmMdsClear;
2539	CPUMISAEXTCFG enmArchCapMsr;
2540
2541	CPUMISAEXTCFG enmAbm;
2542	CPUMISAEXTCFG enmSse4A;
2543	CPUMISAEXTCFG enmMisAlnSse;
2544	CPUMISAEXTCFG enm3dNowPrf;
2545	CPUMISAEXTCFG enmAmdExtMmx;
2546
2547	uint32_t uMaxStdLeaf;
2548	uint32_t uMaxExtLeaf;
2549	uint32_t uMaxCentaurLeaf;
2550	uint32_t uMaxIntelFamilyModelStep;
2551	char szCpuName[128];
2552	} CPUMCPUIDCONFIG;
2553	/** Pointer to CPUID config (from CFGM). */
2554	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2555
2556
2557	/**
2558	* Mini CPU selection support for making Mac OS X happy.
2559	*
2560	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2561	*
2562	* @param pCpum The CPUM instance data.
2563	* @param pConfig The CPUID configuration we've read from CFGM.
2564	*/
2565	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2566	{
2567	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2568	{
2569	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2570	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2571	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2572	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2573	0);
2574	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2575	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2576	{
2577	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2578	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2579	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2580	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2581	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2582	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2583	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2584	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2585	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2586	pStdFeatureLeaf->uEax = uNew;
2587	}
2588	}
2589	}
2590
2591
2592
2593	/**
2594	* Limit it the number of entries, zapping the remainder.
2595	*
2596	* The limits are masking off stuff about power saving and similar, this
2597	* is perhaps a bit crudely done as there is probably some relatively harmless
2598	* info too in these leaves (like words about having a constant TSC).
2599	*
2600	* @param pCpum The CPUM instance data.
2601	* @param pConfig The CPUID configuration we've read from CFGM.
2602	*/
2603	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2604	{
2605	/*
2606	* Standard leaves.
2607	*/
2608	uint32_t uSubLeaf = 0;
2609	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2610	if (pCurLeaf)
2611	{
2612	uint32_t uLimit = pCurLeaf->uEax;
2613	if (uLimit <= UINT32_C(0x000fffff))
2614	{
2615	if (uLimit > pConfig->uMaxStdLeaf)
2616	{
2617	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2618	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2619	uLimit + 1, UINT32_C(0x000fffff));
2620	}
2621
2622	/* NT4 hack, no zapping of extra leaves here. */
2623	if (pConfig->fNt4LeafLimit && uLimit > 3)
2624	pCurLeaf->uEax = uLimit = 3;
2625
2626	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2627	pCurLeaf->uEax = uLimit;
2628	}
2629	else
2630	{
2631	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2632	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2633	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2634	}
2635	}
2636
2637	/*
2638	* Extended leaves.
2639	*/
2640	uSubLeaf = 0;
2641	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2642	if (pCurLeaf)
2643	{
2644	uint32_t uLimit = pCurLeaf->uEax;
2645	if ( uLimit >= UINT32_C(0x80000000)
2646	&& uLimit <= UINT32_C(0x800fffff))
2647	{
2648	if (uLimit > pConfig->uMaxExtLeaf)
2649	{
2650	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2651	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2652	uLimit + 1, UINT32_C(0x800fffff));
2653	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2654	pCurLeaf->uEax = uLimit;
2655	}
2656	}
2657	else
2658	{
2659	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2660	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2661	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2662	}
2663	}
2664
2665	/*
2666	* Centaur leaves (VIA).
2667	*/
2668	uSubLeaf = 0;
2669	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2670	if (pCurLeaf)
2671	{
2672	uint32_t uLimit = pCurLeaf->uEax;
2673	if ( uLimit >= UINT32_C(0xc0000000)
2674	&& uLimit <= UINT32_C(0xc00fffff))
2675	{
2676	if (uLimit > pConfig->uMaxCentaurLeaf)
2677	{
2678	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2679	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2680	uLimit + 1, UINT32_C(0xcfffffff));
2681	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2682	pCurLeaf->uEax = uLimit;
2683	}
2684	}
2685	else
2686	{
2687	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2688	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2689	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2690	}
2691	}
2692	}
2693
2694
2695	/**
2696	* Clears a CPUID leaf and all sub-leaves (to zero).
2697	*
2698	* @param pCpum The CPUM instance data.
2699	* @param uLeaf The leaf to clear.
2700	*/
2701	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2702	{
2703	uint32_t uSubLeaf = 0;
2704	PCPUMCPUIDLEAF pCurLeaf;
2705	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2706	{
2707	pCurLeaf->uEax = 0;
2708	pCurLeaf->uEbx = 0;
2709	pCurLeaf->uEcx = 0;
2710	pCurLeaf->uEdx = 0;
2711	uSubLeaf++;
2712	}
2713	}
2714
2715
2716	/**
2717	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2718	* the given leaf.
2719	*
2720	* @returns pLeaf.
2721	* @param pCpum The CPUM instance data.
2722	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2723	*/
2724	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2725	{
2726	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2727	if (pLeaf->fSubLeafMask != 0)
2728	{
2729	/*
2730	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2731	* Log everything while we're at it.
2732	*/
2733	LogRel(("CPUM:\n"
2734	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2735	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2736	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2737	for (;;)
2738	{
2739	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2740	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2741	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2742	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2743	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2744	break;
2745	pSubLeaf++;
2746	}
2747	LogRel(("CPUM:\n"));
2748
2749	/*
2750	* Remove the offending sub-leaves.
2751	*/
2752	if (pSubLeaf != pLeaf)
2753	{
2754	if (pSubLeaf != pLast)
2755	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2756	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2757	}
2758
2759	/*
2760	* Convert the first sub-leaf into a single leaf.
2761	*/
2762	pLeaf->uSubLeaf = 0;
2763	pLeaf->fSubLeafMask = 0;
2764	}
2765	return pLeaf;
2766	}
2767
2768
2769	/**
2770	* Sanitizes and adjust the CPUID leaves.
2771	*
2772	* Drop features that aren't virtualized (or virtualizable). Adjust information
2773	* and capabilities to fit the virtualized hardware. Remove information the
2774	* guest shouldn't have (because it's wrong in the virtual world or because it
2775	* gives away host details) or that we don't have documentation for and no idea
2776	* what means.
2777	*
2778	* @returns VBox status code.
2779	* @param pVM The cross context VM structure (for cCpus).
2780	* @param pCpum The CPUM instance data.
2781	* @param pConfig The CPUID configuration we've read from CFGM.
2782	*/
2783	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2784	{
2785	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2786	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2787	{ \
2788	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2789	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2790	}
2791	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2792	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2793	{ \
2794	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2795	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2796	}
2797	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2798	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2799	&& ((a_pLeafReg) & (fBitMask)) \
2800	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2801	{ \
2802	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2803	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2804	}
2805	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2806
2807	/* The CPUID entries we start with here isn't necessarily the ones of the host, so we
2808	must consult HostFeatures when processing CPUMISAEXTCFG variables. */
2809	PCCPUMFEATURES pHstFeat = &pCpum->HostFeatures;
2810	#define PASSTHRU_FEATURE(enmConfig, fHostFeature, fConst) \
2811	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) ? (fConst) : 0)
2812	#define PASSTHRU_FEATURE_EX(enmConfig, fHostFeature, fAndExpr, fConst) \
2813	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) && (fAndExpr) ? (fConst) : 0)
2814	#define PASSTHRU_FEATURE_TODO(enmConfig, fConst) ((enmConfig) ? (fConst) : 0)
2815
2816	/* Cpuid 1:
2817	* EAX: CPU model, family and stepping.
2818	*
2819	* ECX + EDX: Supported features. Only report features we can support.
2820	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2821	* options may require adjusting (i.e. stripping what was enabled).
2822	*
2823	* EBX: Branding, CLFLUSH line size, logical processors per package and
2824	* initial APIC ID.
2825	*/
2826	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2827	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2828	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2829
2830	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2831	\| X86_CPUID_FEATURE_EDX_VME
2832	\| X86_CPUID_FEATURE_EDX_DE
2833	\| X86_CPUID_FEATURE_EDX_PSE
2834	\| X86_CPUID_FEATURE_EDX_TSC
2835	\| X86_CPUID_FEATURE_EDX_MSR
2836	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2837	\| X86_CPUID_FEATURE_EDX_MCE
2838	\| X86_CPUID_FEATURE_EDX_CX8
2839	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2840	//\| RT_BIT_32(10) - not defined
2841	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2842	//\| X86_CPUID_FEATURE_EDX_SEP
2843	\| X86_CPUID_FEATURE_EDX_MTRR
2844	\| X86_CPUID_FEATURE_EDX_PGE
2845	\| X86_CPUID_FEATURE_EDX_MCA
2846	\| X86_CPUID_FEATURE_EDX_CMOV
2847	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2848	\| X86_CPUID_FEATURE_EDX_PSE36
2849	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2850	\| X86_CPUID_FEATURE_EDX_CLFSH
2851	//\| RT_BIT_32(20) - not defined
2852	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2853	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2854	\| X86_CPUID_FEATURE_EDX_MMX
2855	\| X86_CPUID_FEATURE_EDX_FXSR
2856	\| X86_CPUID_FEATURE_EDX_SSE
2857	\| X86_CPUID_FEATURE_EDX_SSE2
2858	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2859	\| X86_CPUID_FEATURE_EDX_HTT
2860	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2861	//\| RT_BIT_32(30) - not defined
2862	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2863	;
2864	pStdFeatureLeaf->uEcx &= X86_CPUID_FEATURE_ECX_SSE3
2865	\| PASSTHRU_FEATURE_TODO(pConfig->enmPClMul, X86_CPUID_FEATURE_ECX_PCLMUL)
2866	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2867	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2868	\| PASSTHRU_FEATURE_EX(pConfig->enmMonitor, pHstFeat->fMonitorMWait, pVM->cCpus == 1, X86_CPUID_FEATURE_ECX_MONITOR)
2869	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2870	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
2871	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2872	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2873	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2874	\| X86_CPUID_FEATURE_ECX_SSSE3
2875	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2876	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2877	\| PASSTHRU_FEATURE(pConfig->enmCmpXchg16b, pHstFeat->fMovCmpXchg16b, X86_CPUID_FEATURE_ECX_CX16)
2878	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2879	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2880	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2881	\| PASSTHRU_FEATURE(pConfig->enmPcid, pHstFeat->fPcid, X86_CPUID_FEATURE_ECX_PCID)
2882	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2883	\| PASSTHRU_FEATURE(pConfig->enmSse41, pHstFeat->fSse41, X86_CPUID_FEATURE_ECX_SSE4_1)
2884	\| PASSTHRU_FEATURE(pConfig->enmSse42, pHstFeat->fSse42, X86_CPUID_FEATURE_ECX_SSE4_2)
2885	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2886	\| PASSTHRU_FEATURE_TODO(pConfig->enmMovBe, X86_CPUID_FEATURE_ECX_MOVBE)
2887	\| PASSTHRU_FEATURE_TODO(pConfig->enmPopCnt, X86_CPUID_FEATURE_ECX_POPCNT)
2888	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2889	\| PASSTHRU_FEATURE_TODO(pConfig->enmAesNi, X86_CPUID_FEATURE_ECX_AES)
2890	\| PASSTHRU_FEATURE(pConfig->enmXSave, pHstFeat->fXSaveRstor, X86_CPUID_FEATURE_ECX_XSAVE)
2891	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2892	\| PASSTHRU_FEATURE(pConfig->enmAvx, pHstFeat->fAvx, X86_CPUID_FEATURE_ECX_AVX)
2893	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2894	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdRand, X86_CPUID_FEATURE_ECX_RDRAND)
2895	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2896	;
2897
2898	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2899	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2900	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2901	{
2902	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2903	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2904	}
2905
2906	if (pCpum->u8PortableCpuIdLevel > 0)
2907	{
2908	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2909	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2910	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2911	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2912	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2913	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2914	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2915	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
2916	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2917	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2918	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2919	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2920	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2921	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2922	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2923	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2924	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2925	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2926	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2927	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2928
2929	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2930	\| X86_CPUID_FEATURE_EDX_PSN
2931	\| X86_CPUID_FEATURE_EDX_DS
2932	\| X86_CPUID_FEATURE_EDX_ACPI
2933	\| X86_CPUID_FEATURE_EDX_SS
2934	\| X86_CPUID_FEATURE_EDX_TM
2935	\| X86_CPUID_FEATURE_EDX_PBE
2936	)));
2937	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2938	\| X86_CPUID_FEATURE_ECX_CPLDS
2939	\| X86_CPUID_FEATURE_ECX_AES
2940	\| X86_CPUID_FEATURE_ECX_VMX
2941	\| X86_CPUID_FEATURE_ECX_SMX
2942	\| X86_CPUID_FEATURE_ECX_EST
2943	\| X86_CPUID_FEATURE_ECX_TM2
2944	\| X86_CPUID_FEATURE_ECX_CNTXID
2945	\| X86_CPUID_FEATURE_ECX_FMA
2946	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2947	\| X86_CPUID_FEATURE_ECX_PDCM
2948	\| X86_CPUID_FEATURE_ECX_DCA
2949	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2950	)));
2951	}
2952
2953	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2954	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2955
2956	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2957	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2958	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2959	*/
2960	#ifdef VBOX_WITH_MULTI_CORE
2961	if (pVM->cCpus > 1)
2962	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2963	#endif
2964	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2965	{
2966	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2967	core times the number of CPU cores per processor */
2968	#ifdef VBOX_WITH_MULTI_CORE
2969	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2970	#else
2971	/* Single logical processor in a package. */
2972	pStdFeatureLeaf->uEbx \|= (1 << 16);
2973	#endif
2974	}
2975
2976	uint32_t uMicrocodeRev;
2977	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2978	if (RT_SUCCESS(rc))
2979	{
2980	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2981	}
2982	else
2983	{
2984	uMicrocodeRev = 0;
2985	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2986	}
2987
2988	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2989	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2990	*/
2991	if ( ( pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen
2992	/** @todo The following ASSUMES that Hygon uses the same version numbering
2993	* as AMD and that they shipped buggy firmware. */
2994	\|\| pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Hygon_Dhyana)
2995	&& uMicrocodeRev < 0x8001126
2996	&& !pConfig->fForceVme)
2997	{
2998	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2999	LogRel(("CPUM: Zen VME workaround engaged\n"));
3000	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
3001	}
3002
3003	/* Force standard feature bits. */
3004	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
3005	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
3006	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
3007	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
3008	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
3009	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
3010	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3011	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
3012	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3013	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
3014	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
3015	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
3016	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3017	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
3018	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
3019	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
3020	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
3021	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
3022	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3023	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
3024	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
3025	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
3026
3027	pStdFeatureLeaf = NULL; /* Must refetch! */
3028
3029	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
3030	* AMD:
3031	* EAX: CPU model, family and stepping.
3032	*
3033	* ECX + EDX: Supported features. Only report features we can support.
3034	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3035	* options may require adjusting (i.e. stripping what was enabled).
3036	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
3037	*
3038	* EBX: Branding ID and package type (or reserved).
3039	*
3040	* Intel and probably most others:
3041	* EAX: 0
3042	* EBX: 0
3043	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
3044	*/
3045	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3046	if (pExtFeatureLeaf)
3047	{
3048	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
3049
3050	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
3051	\| X86_CPUID_AMD_FEATURE_EDX_VME
3052	\| X86_CPUID_AMD_FEATURE_EDX_DE
3053	\| X86_CPUID_AMD_FEATURE_EDX_PSE
3054	\| X86_CPUID_AMD_FEATURE_EDX_TSC
3055	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
3056	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
3057	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
3058	\| X86_CPUID_AMD_FEATURE_EDX_CX8
3059	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
3060	//\| RT_BIT_32(10) - reserved
3061	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
3062	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
3063	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3064	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
3065	\| X86_CPUID_AMD_FEATURE_EDX_PGE
3066	\| X86_CPUID_AMD_FEATURE_EDX_MCA
3067	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
3068	\| X86_CPUID_AMD_FEATURE_EDX_PAT
3069	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
3070	//\| RT_BIT_32(18) - reserved
3071	//\| RT_BIT_32(19) - reserved
3072	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
3073	//\| RT_BIT_32(21) - reserved
3074	\| PASSTHRU_FEATURE(pConfig->enmAmdExtMmx, pHstFeat->fAmdMmxExts, X86_CPUID_AMD_FEATURE_EDX_AXMMX)
3075	\| X86_CPUID_AMD_FEATURE_EDX_MMX
3076	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
3077	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
3078	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3079	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
3080	//\| RT_BIT_32(28) - reserved
3081	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
3082	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
3083	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
3084	;
3085	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
3086	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
3087	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
3088	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3089	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
3090	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
3091	\| PASSTHRU_FEATURE_TODO(pConfig->enmAbm, X86_CPUID_AMD_FEATURE_ECX_ABM)
3092	\| PASSTHRU_FEATURE_TODO(pConfig->enmSse4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A)
3093	\| PASSTHRU_FEATURE_TODO(pConfig->enmMisAlnSse, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE)
3094	\| PASSTHRU_FEATURE(pConfig->enm3dNowPrf, pHstFeat->f3DNowPrefetch, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
3095	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3096	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
3097	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
3098	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3099	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
3100	//\| RT_BIT_32(14) - reserved
3101	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
3102	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
3103	//\| RT_BIT_32(17) - reserved
3104	//\| RT_BIT_32(18) - reserved
3105	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
3106	//\| RT_BIT_32(20) - reserved
3107	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
3108	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
3109	//\| RT_BIT_32(23) - reserved
3110	//\| RT_BIT_32(24) - reserved
3111	//\| RT_BIT_32(25) - reserved
3112	//\| RT_BIT_32(26) - reserved
3113	//\| RT_BIT_32(27) - reserved
3114	//\| RT_BIT_32(28) - reserved
3115	//\| RT_BIT_32(29) - reserved
3116	//\| RT_BIT_32(30) - reserved
3117	//\| RT_BIT_32(31) - reserved
3118	;
3119	#ifdef VBOX_WITH_MULTI_CORE
3120	if ( pVM->cCpus > 1
3121	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3122	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3123	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
3124	#endif
3125
3126	if (pCpum->u8PortableCpuIdLevel > 0)
3127	{
3128	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
3129	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
3130	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
3131	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
3132	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
3133	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
3134	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
3135	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
3136	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
3137	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
3138	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
3139	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
3140	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
3141	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
3142	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
3143	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
3144
3145	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
3146	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3147	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3148	\| X86_CPUID_AMD_FEATURE_ECX_IBS
3149	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3150	\| X86_CPUID_AMD_FEATURE_ECX_WDT
3151	\| X86_CPUID_AMD_FEATURE_ECX_LWP
3152	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
3153	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
3154	\| UINT32_C(0xff964000)
3155	)));
3156	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
3157	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3158	\| RT_BIT(18)
3159	\| RT_BIT(19)
3160	\| RT_BIT(21)
3161	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
3162	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3163	\| RT_BIT(28)
3164	)));
3165	}
3166
3167	/* Force extended feature bits. */
3168	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
3169	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
3170	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
3171	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
3172	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
3173	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
3174	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
3175	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
3176	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3177	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
3178	}
3179	pExtFeatureLeaf = NULL; /* Must refetch! */
3180
3181
3182	/* Cpuid 2:
3183	* Intel: (Nondeterministic) Cache and TLB information
3184	* AMD: Reserved
3185	* VIA: Reserved
3186	* Safe to expose.
3187	*/
3188	uint32_t uSubLeaf = 0;
3189	PCPUMCPUIDLEAF pCurLeaf;
3190	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
3191	{
3192	if ((pCurLeaf->uEax & 0xff) > 1)
3193	{
3194	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
3195	pCurLeaf->uEax &= UINT32_C(0xffffff01);
3196	}
3197	uSubLeaf++;
3198	}
3199
3200	/* Cpuid 3:
3201	* Intel: EAX, EBX - reserved (transmeta uses these)
3202	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3203	* AMD: Reserved
3204	* VIA: Reserved
3205	* Safe to expose
3206	*/
3207	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3208	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3209	{
3210	uSubLeaf = 0;
3211	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3212	{
3213	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3214	if (pCpum->u8PortableCpuIdLevel > 0)
3215	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3216	uSubLeaf++;
3217	}
3218	}
3219
3220	/* Cpuid 4 + ECX:
3221	* Intel: Deterministic Cache Parameters Leaf.
3222	* AMD: Reserved
3223	* VIA: Reserved
3224	* Safe to expose, except for EAX:
3225	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3226	* Bits 31-26: Maximum number of processor cores in this physical package**
3227	* Note: These SMP values are constant regardless of ECX
3228	*/
3229	uSubLeaf = 0;
3230	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3231	{
3232	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3233	#ifdef VBOX_WITH_MULTI_CORE
3234	if ( pVM->cCpus > 1
3235	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3236	{
3237	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3238	/* One logical processor with possibly multiple cores. */
3239	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3240	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3241	}
3242	#endif
3243	uSubLeaf++;
3244	}
3245
3246	/* Cpuid 5: Monitor/mwait Leaf
3247	* Intel: ECX, EDX - reserved
3248	* EAX, EBX - Smallest and largest monitor line size
3249	* AMD: EDX - reserved
3250	* EAX, EBX - Smallest and largest monitor line size
3251	* ECX - extensions (ignored for now)
3252	* VIA: Reserved
3253	* Safe to expose
3254	*/
3255	uSubLeaf = 0;
3256	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3257	{
3258	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3259	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3260	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3261
3262	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3263	if (pConfig->enmMWaitExtensions)
3264	{
3265	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3266	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3267	it shall be part of our power management virtualization model */
3268	#if 0
3269	/* MWAIT sub C-states */
3270	pCurLeaf->uEdx =
3271	(0 << 0) /* 0 in C0 */ \|
3272	(2 << 4) /* 2 in C1 */ \|
3273	(2 << 8) /* 2 in C2 */ \|
3274	(2 << 12) /* 2 in C3 */ \|
3275	(0 << 16) /* 0 in C4 */
3276	;
3277	#endif
3278	}
3279	else
3280	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3281	uSubLeaf++;
3282	}
3283
3284	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3285	* Intel: Various stuff.
3286	* AMD: EAX, EBX, EDX - reserved.
3287	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3288	* present. Same as intel.
3289	* VIA: ??
3290	*
3291	* We clear everything here for now.
3292	*/
3293	cpumR3CpuIdZeroLeaf(pCpum, 6);
3294
3295	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3296	* EAX: Number of sub leaves.
3297	* EBX+ECX+EDX: Feature flags
3298	*
3299	* We only have documentation for one sub-leaf, so clear all other (no need
3300	* to remove them as such, just set them to zero).
3301	*
3302	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3303	* options may require adjusting (i.e. stripping what was enabled).
3304	*/
3305	uSubLeaf = 0;
3306	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3307	{
3308	switch (uSubLeaf)
3309	{
3310	case 0:
3311	{
3312	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3313	pCurLeaf->uEbx &= 0
3314	\| PASSTHRU_FEATURE(pConfig->enmFsGsBase, pHstFeat->fFsGsBase, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE)
3315	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3316	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3317	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3318	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3319	\| PASSTHRU_FEATURE(pConfig->enmAvx2, pHstFeat->fAvx2, X86_CPUID_STEXT_FEATURE_EBX_AVX2)
3320	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3321	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3322	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3323	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3324	\| PASSTHRU_FEATURE(pConfig->enmInvpcid, pHstFeat->fInvpcid, X86_CPUID_STEXT_FEATURE_EBX_INVPCID)
3325	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3326	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3327	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3328	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3329	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3330	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3331	//\| RT_BIT(17) - reserved
3332	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdSeed, X86_CPUID_STEXT_FEATURE_EBX_RDSEED)
3333	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3334	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3335	//\| RT_BIT(21) - reserved
3336	//\| RT_BIT(22) - reserved
3337	\| PASSTHRU_FEATURE(pConfig->enmCLFlushOpt, pHstFeat->fClFlushOpt, X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT)
3338	//\| RT_BIT(24) - reserved
3339	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3340	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3341	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3342	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3343	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3344	//\| RT_BIT(30) - reserved
3345	//\| RT_BIT(31) - reserved
3346	;
3347	pCurLeaf->uEcx &= 0
3348	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3349	;
3350	pCurLeaf->uEdx &= 0
3351	\| PASSTHRU_FEATURE(pConfig->enmMdsClear, pHstFeat->fMdsClear, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR)
3352	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3353	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3354	\| PASSTHRU_FEATURE(pConfig->enmFlushCmdMsr, pHstFeat->fFlushCmd, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD)
3355	\| PASSTHRU_FEATURE(pConfig->enmArchCapMsr, pHstFeat->fArchCap, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
3356	;
3357
3358	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3359	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3360	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3361	{
3362	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3363	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3364	}
3365
3366	if (pCpum->u8PortableCpuIdLevel > 0)
3367	{
3368	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3369	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3370	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3371	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3372	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3373	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3374	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3375	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3376	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3377	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3378	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3379	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3380	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3381	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3382	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3383	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
3384	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
3385	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
3386	}
3387
3388	/* Dependencies. */
3389	if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
3390	pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3391
3392	/* Force standard feature bits. */
3393	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3394	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3395	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3396	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3397	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3398	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3399	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3400	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3401	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3402	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3403	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3404	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
3405	if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
3406	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3407	if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3408	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
3409	break;
3410	}
3411
3412	default:
3413	/* Invalid index, all values are zero. */
3414	pCurLeaf->uEax = 0;
3415	pCurLeaf->uEbx = 0;
3416	pCurLeaf->uEcx = 0;
3417	pCurLeaf->uEdx = 0;
3418	break;
3419	}
3420	uSubLeaf++;
3421	}
3422
3423	/* Cpuid 8: Marked as reserved by Intel and AMD.
3424	* We zero this since we don't know what it may have been used for.
3425	*/
3426	cpumR3CpuIdZeroLeaf(pCpum, 8);
3427
3428	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3429	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3430	* EBX, ECX, EDX - reserved.
3431	* AMD: Reserved
3432	* VIA: ??
3433	*
3434	* We zero this.
3435	*/
3436	cpumR3CpuIdZeroLeaf(pCpum, 9);
3437
3438	/* Cpuid 0xa: Architectural Performance Monitor Features
3439	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3440	* EBX, ECX, EDX - reserved.
3441	* AMD: Reserved
3442	* VIA: ??
3443	*
3444	* We zero this, for now at least.
3445	*/
3446	cpumR3CpuIdZeroLeaf(pCpum, 10);
3447
3448	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3449	* Intel: EAX - APCI ID shift right for next level.
3450	* EBX - Factory configured cores/threads at this level.
3451	* ECX - Level number (same as input) and level type (1,2,0).
3452	* EDX - Extended initial APIC ID.
3453	* AMD: Reserved
3454	* VIA: ??
3455	*/
3456	uSubLeaf = 0;
3457	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3458	{
3459	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3460	{
3461	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3462	if (bLevelType == 1)
3463	{
3464	/* Thread level - we don't do threads at the moment. */
3465	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3466	pCurLeaf->uEbx = 1;
3467	}
3468	else if (bLevelType == 2)
3469	{
3470	/* Core level. */
3471	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3472	#ifdef VBOX_WITH_MULTI_CORE
3473	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3474	pCurLeaf->uEax++;
3475	#endif
3476	pCurLeaf->uEbx = pVM->cCpus;
3477	}
3478	else
3479	{
3480	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3481	pCurLeaf->uEax = 0;
3482	pCurLeaf->uEbx = 0;
3483	pCurLeaf->uEcx = 0;
3484	}
3485	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3486	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3487	}
3488	else
3489	{
3490	pCurLeaf->uEax = 0;
3491	pCurLeaf->uEbx = 0;
3492	pCurLeaf->uEcx = 0;
3493	pCurLeaf->uEdx = 0;
3494	}
3495	uSubLeaf++;
3496	}
3497
3498	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3499	* We zero this since we don't know what it may have been used for.
3500	*/
3501	cpumR3CpuIdZeroLeaf(pCpum, 12);
3502
3503	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3504	* ECX=0: EAX - Valid bits in XCR0[31:0].
3505	* EBX - Maximum state size as per current XCR0 value.
3506	* ECX - Maximum state size for all supported features.
3507	* EDX - Valid bits in XCR0[63:32].
3508	* ECX=1: EAX - Various X-features.
3509	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3510	* ECX - Valid bits in IA32_XSS[31:0].
3511	* EDX - Valid bits in IA32_XSS[63:32].
3512	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3513	* if the bit invalid all four registers are set to zero.
3514	* EAX - The state size for this feature.
3515	* EBX - The state byte offset of this feature.
3516	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3517	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3518	*
3519	* Clear them all as we don't currently implement extended CPU state.
3520	*/
3521	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3522	uint64_t fGuestXcr0Mask = 0;
3523	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3524	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3525	{
3526	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3527	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3528	fGuestXcr0Mask \|= XSAVE_C_YMM;
3529	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3530	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3531	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3532	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3533
3534	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3535	}
3536	pStdFeatureLeaf = NULL;
3537	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3538
3539	/* Work the sub-leaves. */
3540	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3541	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3542	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3543	{
3544	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3545	if (pCurLeaf)
3546	{
3547	if (fGuestXcr0Mask)
3548	{
3549	switch (uSubLeaf)
3550	{
3551	case 0:
3552	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3553	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3554	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3555	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3556	VERR_CPUM_IPE_1);
3557	cbXSaveMaxActual = pCurLeaf->uEcx;
3558	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3559	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3560	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3561	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3562	VERR_CPUM_IPE_2);
3563	continue;
3564	case 1:
3565	pCurLeaf->uEax &= 0;
3566	pCurLeaf->uEcx &= 0;
3567	pCurLeaf->uEdx &= 0;
3568	/** @todo what about checking ebx? */
3569	continue;
3570	default:
3571	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3572	{
3573	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3574	&& pCurLeaf->uEax > 0
3575	&& pCurLeaf->uEbx < cbXSaveMaxActual
3576	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3577	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3578	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3579	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3580	VERR_CPUM_IPE_2);
3581	AssertLogRel(!(pCurLeaf->uEcx & 1));
3582	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3583	pCurLeaf->uEdx = 0; /* it's reserved... */
3584	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3585	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3586	continue;
3587	}
3588	break;
3589	}
3590	}
3591
3592	/* Clear the leaf. */
3593	pCurLeaf->uEax = 0;
3594	pCurLeaf->uEbx = 0;
3595	pCurLeaf->uEcx = 0;
3596	pCurLeaf->uEdx = 0;
3597	}
3598	}
3599
3600	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3601	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3602	{
3603	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3604	if (pCurLeaf)
3605	{
3606	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3607	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3608	pCurLeaf->uEbx = cbXSaveMaxReport;
3609	pCurLeaf->uEcx = cbXSaveMaxReport;
3610	}
3611	}
3612
3613	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3614	* We zero this since we don't know what it may have been used for.
3615	*/
3616	cpumR3CpuIdZeroLeaf(pCpum, 14);
3617
3618	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3619	* also known as Intel Resource Director Technology (RDT) Monitoring
3620	* We zero this as we don't currently virtualize PQM.
3621	*/
3622	cpumR3CpuIdZeroLeaf(pCpum, 15);
3623
3624	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3625	* also known as Intel Resource Director Technology (RDT) Allocation
3626	* We zero this as we don't currently virtualize PQE.
3627	*/
3628	cpumR3CpuIdZeroLeaf(pCpum, 16);
3629
3630	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3631	* We zero this since we don't know what it may have been used for.
3632	*/
3633	cpumR3CpuIdZeroLeaf(pCpum, 17);
3634
3635	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3636	* We zero this as we don't currently virtualize this.
3637	*/
3638	cpumR3CpuIdZeroLeaf(pCpum, 18);
3639
3640	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3641	* We zero this since we don't know what it may have been used for.
3642	*/
3643	cpumR3CpuIdZeroLeaf(pCpum, 19);
3644
3645	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3646	* We zero this as we don't currently virtualize this.
3647	*/
3648	cpumR3CpuIdZeroLeaf(pCpum, 20);
3649
3650	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3651	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3652	* EAX - denominator (unsigned).
3653	* EBX - numerator (unsigned).
3654	* ECX, EDX - reserved.
3655	* AMD: Reserved / undefined / not implemented.
3656	* VIA: Reserved / undefined / not implemented.
3657	* We zero this as we don't currently virtualize this.
3658	*/
3659	cpumR3CpuIdZeroLeaf(pCpum, 21);
3660
3661	/* Cpuid 0x16: Processor frequency info
3662	* Intel: EAX - Core base frequency in MHz.
3663	* EBX - Core maximum frequency in MHz.
3664	* ECX - Bus (reference) frequency in MHz.
3665	* EDX - Reserved.
3666	* AMD: Reserved / undefined / not implemented.
3667	* VIA: Reserved / undefined / not implemented.
3668	* We zero this as we don't currently virtualize this.
3669	*/
3670	cpumR3CpuIdZeroLeaf(pCpum, 22);
3671
3672	/* Cpuid 0x17..0x10000000: Unknown.
3673	* We don't know these and what they mean, so remove them. */
3674	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3675	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3676
3677
3678	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3679	* We remove all these as we're a hypervisor and must provide our own.
3680	*/
3681	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3682	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3683
3684
3685	/* Cpuid 0x80000000 is harmless. */
3686
3687	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3688
3689	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3690
3691	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3692	* Safe to pass on to the guest.
3693	*
3694	* AMD: 0x800000005 L1 cache information
3695	* 0x800000006 L2/L3 cache information
3696	* Intel: 0x800000005 reserved
3697	* 0x800000006 L2 cache information
3698	* VIA: 0x800000005 TLB and L1 cache information
3699	* 0x800000006 L2 cache information
3700	*/
3701
3702	/* Cpuid 0x800000007: Advanced Power Management Information.
3703	* AMD: EAX: Processor feedback capabilities.
3704	* EBX: RAS capabilites.
3705	* ECX: Advanced power monitoring interface.
3706	* EDX: Enhanced power management capabilities.
3707	* Intel: EAX, EBX, ECX - reserved.
3708	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3709	* VIA: Reserved
3710	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3711	*/
3712	uSubLeaf = 0;
3713	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3714	{
3715	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3716	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3717	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3718	{
3719	/*
3720	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3721	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3722	* bit is now configurable.
3723	*/
3724	pCurLeaf->uEdx &= 0
3725	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3726	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3727	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3728	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3729	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3730	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3731	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3732	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3733	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3734	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3735	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3736	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3737	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3738	\| 0;
3739	}
3740	else
3741	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3742	if (!pConfig->fInvariantTsc)
3743	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3744	uSubLeaf++;
3745	}
3746
3747	/* Cpuid 0x80000008:
3748	* AMD: EBX, EDX - reserved
3749	* EAX: Virtual/Physical/Guest address Size
3750	* ECX: Number of cores + APICIdCoreIdSize
3751	* Intel: EAX: Virtual/Physical address Size
3752	* EBX, ECX, EDX - reserved
3753	* VIA: EAX: Virtual/Physical address Size
3754	* EBX, ECX, EDX - reserved
3755	*
3756	* We only expose the virtual+pysical address size to the guest atm.
3757	* On AMD we set the core count, but not the apic id stuff as we're
3758	* currently not doing the apic id assignments in a complatible manner.
3759	*/
3760	uSubLeaf = 0;
3761	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3762	{
3763	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3764	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3765	pCurLeaf->uEdx = 0; /* reserved */
3766
3767	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3768	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3769	pCurLeaf->uEcx = 0;
3770	#ifdef VBOX_WITH_MULTI_CORE
3771	if ( pVM->cCpus > 1
3772	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3773	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3774	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3775	#endif
3776	uSubLeaf++;
3777	}
3778
3779	/* Cpuid 0x80000009: Reserved
3780	* We zero this since we don't know what it may have been used for.
3781	*/
3782	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3783
3784	/* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
3785	* AMD: EAX - SVM revision.
3786	* EBX - Number of ASIDs.
3787	* ECX - Reserved.
3788	* EDX - SVM Feature identification.
3789	*/
3790	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3791	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3792	{
3793	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3794	if ( pExtFeatureLeaf
3795	&& (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM))
3796	{
3797	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3798	if (pSvmFeatureLeaf)
3799	{
3800	pSvmFeatureLeaf->uEax = 0x1;
3801	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3802	pSvmFeatureLeaf->uEcx = 0;
3803	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3804	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3805	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3806	}
3807	else
3808	{
3809	/* Should never happen. */
3810	LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
3811	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3812	}
3813	}
3814	else
3815	{
3816	/* If SVM is not supported, this is reserved, zero out. */
3817	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3818	}
3819	}
3820	else
3821	{
3822	/* Cpuid 0x8000000a: Reserved on Intel.
3823	* We zero this since we don't know what it may have been used for.
3824	*/
3825	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3826	}
3827
3828	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3829	* We clear these as we don't know what purpose they might have. */
3830	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3831	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3832
3833	/* Cpuid 0x80000019: TLB configuration
3834	* Seems to be harmless, pass them thru as is. */
3835
3836	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3837	* Strip anything we don't know what is or addresses feature we don't implement. */
3838	uSubLeaf = 0;
3839	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3840	{
3841	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3842	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3843	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3844	;
3845	pCurLeaf->uEbx = 0; /* reserved */
3846	pCurLeaf->uEcx = 0; /* reserved */
3847	pCurLeaf->uEdx = 0; /* reserved */
3848	uSubLeaf++;
3849	}
3850
3851	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3852	* Clear this as we don't currently virtualize this feature. */
3853	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3854
3855	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3856	* Clear this as we don't currently virtualize this feature. */
3857	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3858
3859	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3860	* We need to sanitize the cores per cache (EAX[25:14]).
3861	*
3862	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3863	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3864	* slightly different meaning.
3865	*/
3866	uSubLeaf = 0;
3867	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3868	{
3869	#ifdef VBOX_WITH_MULTI_CORE
3870	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3871	if (cCores > pVM->cCpus)
3872	cCores = pVM->cCpus;
3873	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3874	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3875	#else
3876	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3877	#endif
3878	uSubLeaf++;
3879	}
3880
3881	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3882	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3883	* setup, we have one compute unit with all the cores in it. Single node.
3884	*/
3885	uSubLeaf = 0;
3886	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3887	{
3888	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3889	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3890	{
3891	#ifdef VBOX_WITH_MULTI_CORE
3892	pCurLeaf->uEbx = pVM->cCpus < 0x100
3893	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3894	#else
3895	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3896	#endif
3897	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3898	}
3899	else
3900	{
3901	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3902	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_HYGON);
3903	pCurLeaf->uEbx = 0; /* Reserved. */
3904	pCurLeaf->uEcx = 0; /* Reserved. */
3905	}
3906	pCurLeaf->uEdx = 0; /* Reserved. */
3907	uSubLeaf++;
3908	}
3909
3910	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3911	* We don't know these and what they mean, so remove them. */
3912	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3913	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3914
3915	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3916	* Just pass it thru for now. */
3917
3918	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3919	* Just pass it thru for now. */
3920
3921	/* Cpuid 0xc0000000: Centaur stuff.
3922	* Harmless, pass it thru. */
3923
3924	/* Cpuid 0xc0000001: Centaur features.
3925	* VIA: EAX - Family, model, stepping.
3926	* EDX - Centaur extended feature flags. Nothing interesting, except may
3927	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3928	* EBX, ECX - reserved.
3929	* We keep EAX but strips the rest.
3930	*/
3931	uSubLeaf = 0;
3932	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3933	{
3934	pCurLeaf->uEbx = 0;
3935	pCurLeaf->uEcx = 0;
3936	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3937	uSubLeaf++;
3938	}
3939
3940	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3941	* We only have fixed stale values, but should be harmless. */
3942
3943	/* Cpuid 0xc0000003: Reserved.
3944	* We zero this since we don't know what it may have been used for.
3945	*/
3946	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3947
3948	/* Cpuid 0xc0000004: Centaur Performance Info.
3949	* We only have fixed stale values, but should be harmless. */
3950
3951
3952	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3953	* We don't know these and what they mean, so remove them. */
3954	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3955	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3956
3957	return VINF_SUCCESS;
3958	#undef PORTABLE_DISABLE_FEATURE_BIT
3959	#undef PORTABLE_CLEAR_BITS_WHEN
3960	}
3961
3962
3963	/**
3964	* Reads a value in /CPUM/IsaExts/ node.
3965	*
3966	* @returns VBox status code (error message raised).
3967	* @param pVM The cross context VM structure. (For errors.)
3968	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3969	* @param pszValueName The value / extension name.
3970	* @param penmValue Where to return the choice.
3971	* @param enmDefault The default choice.
3972	*/
3973	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3974	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3975	{
3976	/*
3977	* Try integer encoding first.
3978	*/
3979	uint64_t uValue;
3980	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3981	if (RT_SUCCESS(rc))
3982	switch (uValue)
3983	{
3984	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3985	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3986	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3987	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3988	default:
3989	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3990	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3991	pszValueName, uValue);
3992	}
3993	/*
3994	* If missing, use default.
3995	*/
3996	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3997	*penmValue = enmDefault;
3998	else
3999	{
4000	if (rc == VERR_CFGM_NOT_INTEGER)
4001	{
4002	/*
4003	* Not an integer, try read it as a string.
4004	*/
4005	char szValue[32];
4006	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
4007	if (RT_SUCCESS(rc))
4008	{
4009	RTStrToLower(szValue);
4010	size_t cchValue = strlen(szValue);
4011	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
4012	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
4013	*penmValue = CPUMISAEXTCFG_DISABLED;
4014	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
4015	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
4016	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
4017	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
4018	else if (EQ("portable"))
4019	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
4020	else if (EQ("default") \|\| EQ("def"))
4021	*penmValue = enmDefault;
4022	else
4023	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
4024	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
4025	pszValueName, uValue);
4026	#undef EQ
4027	}
4028	}
4029	if (RT_FAILURE(rc))
4030	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
4031	}
4032	return VINF_SUCCESS;
4033	}
4034
4035
4036	/**
4037	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
4038	*
4039	* @returns VBox status code (error message raised).
4040	* @param pVM The cross context VM structure. (For errors.)
4041	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4042	* @param pszValueName The value / extension name.
4043	* @param penmValue Where to return the choice.
4044	* @param enmDefault The default choice.
4045	* @param fAllowed Allowed choice. Applied both to the result and to
4046	* the default value.
4047	*/
4048	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
4049	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
4050	{
4051	int rc;
4052	if (fAllowed)
4053	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4054	else
4055	{
4056	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
4057	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
4058	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
4059	*penmValue = CPUMISAEXTCFG_DISABLED;
4060	}
4061	return rc;
4062	}
4063
4064
4065	/**
4066	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
4067	*
4068	* @returns VBox status code (error message raised).
4069	* @param pVM The cross context VM structure. (For errors.)
4070	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4071	* @param pCpumCfg The /CPUM node (can be NULL).
4072	* @param pszValueName The value / extension name.
4073	* @param penmValue Where to return the choice.
4074	* @param enmDefault The default choice.
4075	*/
4076	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
4077	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
4078	{
4079	if (CFGMR3Exists(pCpumCfg, pszValueName))
4080	{
4081	if (!CFGMR3Exists(pIsaExts, pszValueName))
4082	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
4083	else
4084	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
4085	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
4086	pszValueName, pszValueName);
4087
4088	bool fLegacy;
4089	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
4090	if (RT_SUCCESS(rc))
4091	{
4092	*penmValue = fLegacy;
4093	return VINF_SUCCESS;
4094	}
4095	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
4096	}
4097
4098	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4099	}
4100
4101
4102	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
4103	{
4104	int rc;
4105
4106	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
4107	* When non-zero CPUID features that could cause portability issues will be
4108	* stripped. The higher the value the more features gets stripped. Higher
4109	* values should only be used when older CPUs are involved since it may
4110	* harm performance and maybe also cause problems with specific guests. */
4111	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
4112	AssertLogRelRCReturn(rc, rc);
4113
4114	/** @cfgm{/CPUM/GuestCpuName, string}
4115	* The name of the CPU we're to emulate. The default is the host CPU.
4116	* Note! CPUs other than "host" one is currently unsupported. */
4117	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
4118	AssertLogRelRCReturn(rc, rc);
4119
4120	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
4121	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
4122	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
4123	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
4124	*/
4125	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
4126	AssertLogRelRCReturn(rc, rc);
4127
4128	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
4129	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
4130	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
4131	* 64-bit linux guests which assume the presence of AMD performance counters
4132	* that we do not virtualize.
4133	*/
4134	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
4135	AssertLogRelRCReturn(rc, rc);
4136
4137	/** @cfgm{/CPUM/ForceVme, boolean, false}
4138	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
4139	* By default the flag is passed thru as is from the host CPU, except
4140	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
4141	* guests and DOS boxes in general.
4142	*/
4143	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
4144	AssertLogRelRCReturn(rc, rc);
4145
4146	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
4147	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
4148	* probably going to be a temporary hack, so don't depend on this.
4149	* The 1st byte of the value is the stepping, the 2nd byte value is the model
4150	* number and the 3rd byte value is the family, and the 4th value must be zero.
4151	*/
4152	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
4153	AssertLogRelRCReturn(rc, rc);
4154
4155	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
4156	* The last standard leaf to keep. The actual last value that is stored in EAX
4157	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
4158	* removed. (This works independently of and differently from NT4LeafLimit.)
4159	* The default is usually set to what we're able to reasonably sanitize.
4160	*/
4161	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
4162	AssertLogRelRCReturn(rc, rc);
4163
4164	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
4165	* The last extended leaf to keep. The actual last value that is stored in EAX
4166	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
4167	* leaf are removed. The default is set to what we're able to sanitize.
4168	*/
4169	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
4170	AssertLogRelRCReturn(rc, rc);
4171
4172	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
4173	* The last extended leaf to keep. The actual last value that is stored in EAX
4174	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
4175	* leaf are removed. The default is set to what we're able to sanitize.
4176	*/
4177	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
4178	AssertLogRelRCReturn(rc, rc);
4179
4180	bool fQueryNestedHwvirt = false
4181	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4182	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4183	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON
4184	#endif
4185	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4186	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
4187	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA
4188	#endif
4189	;
4190	if (fQueryNestedHwvirt)
4191	{
4192	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
4193	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
4194	* The default is false, and when enabled requires a 64-bit CPU with support for
4195	* nested-paging and AMD-V or unrestricted guest mode.
4196	*/
4197	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
4198	AssertLogRelRCReturn(rc, rc);
4199	if (pConfig->fNestedHWVirt)
4200	{
4201	if (!fNestedPagingAndFullGuestExec)
4202	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
4203	"Cannot enable nested VT-x/AMD-V without nested-paging and unresricted guest execution!\n");
4204
4205	/** @todo Think about enabling this later with NEM/KVM. */
4206	if (VM_IS_NEM_ENABLED(pVM))
4207	{
4208	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used!\n"));
4209	pConfig->fNestedHWVirt = false;
4210	}
4211	}
4212
4213	if (pConfig->fNestedHWVirt)
4214	{
4215	/** @cfgm{/CPUM/NestedVmxPreemptTimer, bool, true}
4216	* Whether to expose the VMX-preemption timer feature to the guest (if also
4217	* supported by the host hardware). The default is true, and when disabled will
4218	* prevent exposing the VMX-preemption timer feature to the guest even if the host
4219	* supports it.
4220	*/
4221	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxPreemptTimer", &pVM->cpum.s.fNestedVmxPreemptTimer, true);
4222	AssertLogRelRCReturn(rc, rc);
4223
4224	/** @cfgm{/CPUM/NestedVmxEpt, bool, true}
4225	* Whether to expose the EPT feature to the guest. The default is false. When
4226	* disabled will automatically prevent exposing features that rely on
4227	*/
4228	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxEpt", &pVM->cpum.s.fNestedVmxEpt, false);
4229	AssertLogRelRCReturn(rc, rc);
4230
4231	/** @cfgm{/CPUM/NestedVmxUnrestrictedGuest, bool, true}
4232	* Whether to expose the Unrestricted Guest feature to the guest. The default is
4233	* false. When disabled will automatically prevent exposing features that rely on
4234	* it.
4235	*/
4236	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxUnrestrictedGuest", &pVM->cpum.s.fNestedVmxUnrestrictedGuest, false);
4237	AssertLogRelRCReturn(rc, rc);
4238
4239	if ( pVM->cpum.s.fNestedVmxUnrestrictedGuest
4240	&& !pVM->cpum.s.fNestedVmxEpt)
4241	{
4242	LogRel(("CPUM: WARNING! Can't expose \"Unrestricted Guest\" to the guest when EPT is not exposed!\n"));
4243	pVM->cpum.s.fNestedVmxUnrestrictedGuest = false;
4244	}
4245	}
4246	}
4247
4248	/*
4249	* Instruction Set Architecture (ISA) Extensions.
4250	*/
4251	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
4252	if (pIsaExts)
4253	{
4254	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
4255	"CMPXCHG16B"
4256	"\|MONITOR"
4257	"\|MWaitExtensions"
4258	"\|SSE4.1"
4259	"\|SSE4.2"
4260	"\|XSAVE"
4261	"\|AVX"
4262	"\|AVX2"
4263	"\|AESNI"
4264	"\|PCLMUL"
4265	"\|POPCNT"
4266	"\|MOVBE"
4267	"\|RDRAND"
4268	"\|RDSEED"
4269	"\|CLFLUSHOPT"
4270	"\|FSGSBASE"
4271	"\|PCID"
4272	"\|INVPCID"
4273	"\|FlushCmdMsr"
4274	"\|ABM"
4275	"\|SSE4A"
4276	"\|MISALNSSE"
4277	"\|3DNOWPRF"
4278	"\|AXMMX"
4279	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
4280	if (RT_FAILURE(rc))
4281	return rc;
4282	}
4283
4284	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, true}
4285	* Expose CMPXCHG16B to the guest if available. All host CPUs which support
4286	* hardware virtualization have it.
4287	*/
4288	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, true);
4289	AssertLogRelRCReturn(rc, rc);
4290
4291	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
4292	* Expose MONITOR/MWAIT instructions to the guest.
4293	*/
4294	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
4295	AssertLogRelRCReturn(rc, rc);
4296
4297	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4298	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4299	* break on interrupt feature (bit 1).
4300	*/
4301	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4302	AssertLogRelRCReturn(rc, rc);
4303
4304	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4305	* Expose SSE4.1 to the guest if available.
4306	*/
4307	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4308	AssertLogRelRCReturn(rc, rc);
4309
4310	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4311	* Expose SSE4.2 to the guest if available.
4312	*/
4313	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4314	AssertLogRelRCReturn(rc, rc);
4315
4316	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
4317	&& pVM->cpum.s.HostFeatures.fXSaveRstor
4318	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor;
4319	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4320
4321	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4322	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4323	* default is to only expose this to VMs with nested paging and AMD-V or
4324	* unrestricted guest execution mode. Not possible to force this one without
4325	* host support at the moment.
4326	*/
4327	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4328	fMayHaveXSave /fAllowed/);
4329	AssertLogRelRCReturn(rc, rc);
4330
4331	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4332	* Expose the AVX instruction set extensions to the guest if available and
4333	* XSAVE is exposed too. For the time being the default is to only expose this
4334	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4335	*/
4336	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4337	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4338	AssertLogRelRCReturn(rc, rc);
4339
4340	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4341	* Expose the AVX2 instruction set extensions to the guest if available and
4342	* XSAVE is exposed too. For the time being the default is to only expose this
4343	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4344	*/
4345	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4346	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4347	AssertLogRelRCReturn(rc, rc);
4348
4349	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4350	* Whether to expose the AES instructions to the guest. For the time being the
4351	* default is to only do this for VMs with nested paging and AMD-V or
4352	* unrestricted guest mode.
4353	*/
4354	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4355	AssertLogRelRCReturn(rc, rc);
4356
4357	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4358	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4359	* being the default is to only do this for VMs with nested paging and AMD-V or
4360	* unrestricted guest mode.
4361	*/
4362	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4363	AssertLogRelRCReturn(rc, rc);
4364
4365	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4366	* Whether to expose the POPCNT instructions to the guest. For the time
4367	* being the default is to only do this for VMs with nested paging and AMD-V or
4368	* unrestricted guest mode.
4369	*/
4370	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4371	AssertLogRelRCReturn(rc, rc);
4372
4373	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4374	* Whether to expose the MOVBE instructions to the guest. For the time
4375	* being the default is to only do this for VMs with nested paging and AMD-V or
4376	* unrestricted guest mode.
4377	*/
4378	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4379	AssertLogRelRCReturn(rc, rc);
4380
4381	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4382	* Whether to expose the RDRAND instructions to the guest. For the time being
4383	* the default is to only do this for VMs with nested paging and AMD-V or
4384	* unrestricted guest mode.
4385	*/
4386	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4387	AssertLogRelRCReturn(rc, rc);
4388
4389	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4390	* Whether to expose the RDSEED instructions to the guest. For the time being
4391	* the default is to only do this for VMs with nested paging and AMD-V or
4392	* unrestricted guest mode.
4393	*/
4394	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4395	AssertLogRelRCReturn(rc, rc);
4396
4397	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4398	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4399	* being the default is to only do this for VMs with nested paging and AMD-V or
4400	* unrestricted guest mode.
4401	*/
4402	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4403	AssertLogRelRCReturn(rc, rc);
4404
4405	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4406	* Whether to expose the read/write FSGSBASE instructions to the guest.
4407	*/
4408	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4409	AssertLogRelRCReturn(rc, rc);
4410
4411	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4412	* Whether to expose the PCID feature to the guest.
4413	*/
4414	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4415	AssertLogRelRCReturn(rc, rc);
4416
4417	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4418	* Whether to expose the INVPCID instruction to the guest.
4419	*/
4420	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4421	AssertLogRelRCReturn(rc, rc);
4422
4423	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
4424	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
4425	*/
4426	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4427	AssertLogRelRCReturn(rc, rc);
4428
4429	/** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
4430	* Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
4431	* the guest. Requires FlushCmdMsr to be present too.
4432	*/
4433	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4434	AssertLogRelRCReturn(rc, rc);
4435
4436	/** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
4437	* Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
4438	*/
4439	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4440	AssertLogRelRCReturn(rc, rc);
4441
4442
4443	/* AMD: */
4444
4445	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4446	* Whether to expose the AMD ABM instructions to the guest. For the time
4447	* being the default is to only do this for VMs with nested paging and AMD-V or
4448	* unrestricted guest mode.
4449	*/
4450	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4451	AssertLogRelRCReturn(rc, rc);
4452
4453	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4454	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4455	* being the default is to only do this for VMs with nested paging and AMD-V or
4456	* unrestricted guest mode.
4457	*/
4458	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4459	AssertLogRelRCReturn(rc, rc);
4460
4461	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4462	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4463	* the time being the default is to only do this for VMs with nested paging and
4464	* AMD-V or unrestricted guest mode.
4465	*/
4466	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4467	AssertLogRelRCReturn(rc, rc);
4468
4469	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4470	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4471	* For the time being the default is to only do this for VMs with nested paging
4472	* and AMD-V or unrestricted guest mode.
4473	*/
4474	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4475	AssertLogRelRCReturn(rc, rc);
4476
4477	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4478	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4479	* the default is to only do this for VMs with nested paging and AMD-V or
4480	* unrestricted guest mode.
4481	*/
4482	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4483	AssertLogRelRCReturn(rc, rc);
4484
4485	return VINF_SUCCESS;
4486	}
4487
4488
4489	/**
4490	* Initializes the emulated CPU's CPUID & MSR information.
4491	*
4492	* @returns VBox status code.
4493	* @param pVM The cross context VM structure.
4494	* @param pHostMsrs Pointer to the host MSRs.
4495	*/
4496	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
4497	{
4498	Assert(pHostMsrs);
4499
4500	PCPUM pCpum = &pVM->cpum.s;
4501	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4502
4503	/*
4504	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4505	* on construction and manage everything from here on.
4506	*/
4507	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4508	{
4509	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4510	pVCpu->cpum.s.fCpuIdApicFeatureVisible = true;
4511	}
4512
4513	/*
4514	* Read the configuration.
4515	*/
4516	CPUMCPUIDCONFIG Config;
4517	RT_ZERO(Config);
4518
4519	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4520	AssertRCReturn(rc, rc);
4521
4522	/*
4523	* Get the guest CPU data from the database and/or the host.
4524	*
4525	* The CPUID and MSRs are currently living on the regular heap to avoid
4526	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4527	* API for the hyper heap). This means special cleanup considerations.
4528	*/
4529	/** @todo The hyper heap will be removed ASAP, so the final destination is
4530	* now a fixed sized arrays in the VM structure. Maybe we can simplify
4531	* this allocation fun a little now? Or maybe it's too convenient for
4532	* the CPU reporter code... No time to figure that out now. */
4533	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4534	if (RT_FAILURE(rc))
4535	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4536	? VMSetError(pVM, rc, RT_SRC_POS,
4537	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4538	: rc;
4539
4540	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4541	{
4542	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4543	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4544	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4545	}
4546	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4547
4548	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4549	* Overrides the guest MSRs.
4550	*/
4551	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4552
4553	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4554	* Overrides the CPUID leaf values (from the host CPU usually) used for
4555	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4556	* values when moving a VM to a different machine. Another use is restricting
4557	* (or extending) the feature set exposed to the guest. */
4558	if (RT_SUCCESS(rc))
4559	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4560
4561	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4562	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4563	"Found unsupported configuration node '/CPUM/CPUID/'. "
4564	"Please use IMachine::setCPUIDLeaf() instead.");
4565
4566	CPUMMSRS GuestMsrs;
4567	RT_ZERO(GuestMsrs);
4568
4569	/*
4570	* Pre-explode the CPUID info.
4571	*/
4572	if (RT_SUCCESS(rc))
4573	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
4574	&pCpum->GuestFeatures);
4575
4576	/*
4577	* Sanitize the cpuid information passed on to the guest.
4578	*/
4579	if (RT_SUCCESS(rc))
4580	{
4581	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4582	if (RT_SUCCESS(rc))
4583	{
4584	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4585	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4586	}
4587	}
4588
4589	/*
4590	* Setup MSRs introduced in microcode updates or that are otherwise not in
4591	* the CPU profile, but are advertised in the CPUID info we just sanitized.
4592	*/
4593	if (RT_SUCCESS(rc))
4594	rc = cpumR3MsrReconcileWithCpuId(pVM);
4595	/*
4596	* MSR fudging.
4597	*/
4598	if (RT_SUCCESS(rc))
4599	{
4600	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4601	* Fudges some common MSRs if not present in the selected CPU database entry.
4602	* This is for trying to keep VMs running when moved between different hosts
4603	* and different CPU vendors. */
4604	bool fEnable;
4605	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4606	if (RT_SUCCESS(rc) && fEnable)
4607	{
4608	rc = cpumR3MsrApplyFudge(pVM);
4609	AssertLogRelRC(rc);
4610	}
4611	}
4612	if (RT_SUCCESS(rc))
4613	{
4614	/*
4615	* Move the MSR and CPUID arrays over to the static VM structure allocations
4616	* and explode guest CPU features again.
4617	*/
4618	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4619	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4620	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
4621	RTMemFree(pvFree);
4622
4623	AssertFatalMsg(pCpum->GuestInfo.cMsrRanges <= RT_ELEMENTS(pCpum->GuestInfo.aMsrRanges),
4624	("%u\n", pCpum->GuestInfo.cMsrRanges));
4625	memcpy(pCpum->GuestInfo.aMsrRanges, pCpum->GuestInfo.paMsrRangesR3,
4626	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges);
4627	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4628	pCpum->GuestInfo.paMsrRangesR3 = pCpum->GuestInfo.aMsrRanges;
4629
4630	AssertLogRelRCReturn(rc, rc);
4631
4632	/*
4633	* Finally, initialize guest VMX MSRs.
4634	*
4635	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
4636	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
4637	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
4638	*/
4639	if (pVM->cpum.s.GuestFeatures.fVmx)
4640	{
4641	Assert(Config.fNestedHWVirt);
4642	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
4643
4644	/* Copy MSRs to all VCPUs */
4645	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
4646	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4647	{
4648	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4649	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
4650	}
4651	}
4652
4653	/*
4654	* Some more configuration that we're applying at the end of everything
4655	* via the CPUMR3SetGuestCpuIdFeature API.
4656	*/
4657
4658	/* Check if PAE was explicitely enabled by the user. */
4659	bool fEnable;
4660	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4661	AssertRCReturn(rc, rc);
4662	if (fEnable)
4663	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4664
4665	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4666	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4667	AssertRCReturn(rc, rc);
4668	if (fEnable)
4669	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4670
4671	/* Check if speculation control is enabled. */
4672	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4673	AssertRCReturn(rc, rc);
4674	if (fEnable)
4675	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4676	else
4677	{
4678	/*
4679	* Set the "SSBD-not-needed" flag to work around a bug in some Linux kernels when the VIRT_SPEC_CTL
4680	* feature is not exposed on AMD CPUs and there is only 1 vCPU configured.
4681	* This was observed with kernel "4.15.0-29-generic #31~16.04.1-Ubuntu" but more versions are likely affected.
4682	*
4683	* The kernel doesn't initialize a lock and causes a NULL pointer exception later on when configuring SSBD:
4684	* EIP: _raw_spin_lock+0x14/0x30
4685	* EFLAGS: 00010046 CPU: 0
4686	* EAX: 00000000 EBX: 00000001 ECX: 00000004 EDX: 00000000
4687	* ESI: 00000000 EDI: 00000000 EBP: ee023f1c ESP: ee023f18
4688	* DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
4689	* CR0: 80050033 CR2: 00000004 CR3: 3671c180 CR4: 000006f0
4690	* Call Trace:
4691	* speculative_store_bypass_update+0x8e/0x180
4692	* ssb_prctl_set+0xc0/0xe0
4693	* arch_seccomp_spec_mitigate+0x1d/0x20
4694	* do_seccomp+0x3cb/0x610
4695	* SyS_seccomp+0x16/0x20
4696	* do_fast_syscall_32+0x7f/0x1d0
4697	* entry_SYSENTER_32+0x4e/0x7c
4698	*
4699	* The lock would've been initialized in process.c:speculative_store_bypass_ht_init() called from two places in smpboot.c.
4700	* First when a secondary CPU is started and second in native_smp_prepare_cpus() which is not called in a single vCPU environment.
4701	*
4702	* As spectre control features are completely disabled anyway when we arrived here there is no harm done in informing the
4703	* guest to not even try.
4704	*/
4705	if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4706	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
4707	{
4708	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x80000008), 0);
4709	if (pLeaf)
4710	{
4711	pLeaf->uEbx \|= X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED;
4712	LogRel(("CPUM: Set SSBD not required flag for AMD to work around some buggy Linux kernels!\n"));
4713	}
4714	}
4715	}
4716
4717	return VINF_SUCCESS;
4718	}
4719
4720	/*
4721	* Failed before switching to hyper heap.
4722	*/
4723	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4724	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4725	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4726	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4727	return rc;
4728	}
4729
4730
4731	/**
4732	* Sets a CPUID feature bit during VM initialization.
4733	*
4734	* Since the CPUID feature bits are generally related to CPU features, other
4735	* CPUM configuration like MSRs can also be modified by calls to this API.
4736	*
4737	* @param pVM The cross context VM structure.
4738	* @param enmFeature The feature to set.
4739	*/
4740	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4741	{
4742	PCPUMCPUIDLEAF pLeaf;
4743	PCPUMMSRRANGE pMsrRange;
4744
4745	switch (enmFeature)
4746	{
4747	/*
4748	* Set the APIC bit in both feature masks.
4749	*/
4750	case CPUMCPUIDFEATURE_APIC:
4751	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4752	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4753	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4754
4755	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4756	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4757	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4758
4759	pVM->cpum.s.GuestFeatures.fApic = 1;
4760
4761	/* Make sure we've got the APICBASE MSR present. */
4762	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4763	if (!pMsrRange)
4764	{
4765	static CPUMMSRRANGE const s_ApicBase =
4766	{
4767	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4768	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4769	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4770	/.szName = / "IA32_APIC_BASE"
4771	};
4772	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4773	AssertLogRelRC(rc);
4774	}
4775
4776	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4777	break;
4778
4779	/*
4780	* Set the x2APIC bit in the standard feature mask.
4781	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4782	*/
4783	case CPUMCPUIDFEATURE_X2APIC:
4784	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4785	if (pLeaf)
4786	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4787	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4788
4789	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4790	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4791	if (pMsrRange)
4792	{
4793	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4794	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4795	}
4796
4797	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4798	break;
4799
4800	/*
4801	* Set the sysenter/sysexit bit in the standard feature mask.
4802	* Assumes the caller knows what it's doing! (host must support these)
4803	*/
4804	case CPUMCPUIDFEATURE_SEP:
4805	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4806	{
4807	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4808	return;
4809	}
4810
4811	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4812	if (pLeaf)
4813	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4814	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4815	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4816	break;
4817
4818	/*
4819	* Set the syscall/sysret bit in the extended feature mask.
4820	* Assumes the caller knows what it's doing! (host must support these)
4821	*/
4822	case CPUMCPUIDFEATURE_SYSCALL:
4823	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4824	if ( !pLeaf
4825	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4826	{
4827	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4828	return;
4829	}
4830
4831	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4832	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4833	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4834	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4835	break;
4836
4837	/*
4838	* Set the PAE bit in both feature masks.
4839	* Assumes the caller knows what it's doing! (host must support these)
4840	*/
4841	case CPUMCPUIDFEATURE_PAE:
4842	if (!pVM->cpum.s.HostFeatures.fPae)
4843	{
4844	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4845	return;
4846	}
4847
4848	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4849	if (pLeaf)
4850	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4851
4852	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4853	if ( pLeaf
4854	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4855	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
4856	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4857
4858	pVM->cpum.s.GuestFeatures.fPae = 1;
4859	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4860	break;
4861
4862	/*
4863	* Set the LONG MODE bit in the extended feature mask.
4864	* Assumes the caller knows what it's doing! (host must support these)
4865	*/
4866	case CPUMCPUIDFEATURE_LONG_MODE:
4867	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4868	if ( !pLeaf
4869	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4870	{
4871	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4872	return;
4873	}
4874
4875	/* Valid for both Intel and AMD. */
4876	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4877	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4878	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
4879	if (pVM->cpum.s.GuestFeatures.fVmx)
4880	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4881	{
4882	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4883	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic &= ~VMX_BASIC_PHYSADDR_WIDTH_32BIT;
4884	}
4885	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4886	break;
4887
4888	/*
4889	* Set the NX/XD bit in the extended feature mask.
4890	* Assumes the caller knows what it's doing! (host must support these)
4891	*/
4892	case CPUMCPUIDFEATURE_NX:
4893	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4894	if ( !pLeaf
4895	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4896	{
4897	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4898	return;
4899	}
4900
4901	/* Valid for both Intel and AMD. */
4902	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4903	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4904	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4905	break;
4906
4907
4908	/*
4909	* Set the LAHF/SAHF support in 64-bit mode.
4910	* Assumes the caller knows what it's doing! (host must support this)
4911	*/
4912	case CPUMCPUIDFEATURE_LAHF:
4913	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4914	if ( !pLeaf
4915	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4916	{
4917	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4918	return;
4919	}
4920
4921	/* Valid for both Intel and AMD. */
4922	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4923	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4924	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4925	break;
4926
4927	/*
4928	* Set the RDTSCP support bit.
4929	* Assumes the caller knows what it's doing! (host must support this)
4930	*/
4931	case CPUMCPUIDFEATURE_RDTSCP:
4932	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4933	if ( !pLeaf
4934	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4935	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4936	{
4937	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4938	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4939	return;
4940	}
4941
4942	/* Valid for both Intel and AMD. */
4943	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4944	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4945	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4946	break;
4947
4948	/*
4949	* Set the Hypervisor Present bit in the standard feature mask.
4950	*/
4951	case CPUMCPUIDFEATURE_HVP:
4952	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4953	if (pLeaf)
4954	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4955	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4956	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4957	break;
4958
4959	/*
4960	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
4961	* on Intel CPUs, and different on AMDs.
4962	*/
4963	case CPUMCPUIDFEATURE_SPEC_CTRL:
4964	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
4965	{
4966	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4967	if ( !pLeaf
4968	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
4969	{
4970	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
4971	return;
4972	}
4973
4974	/* The feature can be enabled. Let's see what we can actually do. */
4975	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
4976
4977	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
4978	if (pVM->cpum.s.HostFeatures.fIbrs)
4979	{
4980	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
4981	pVM->cpum.s.GuestFeatures.fIbrs = 1;
4982	if (pVM->cpum.s.HostFeatures.fStibp)
4983	{
4984	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
4985	pVM->cpum.s.GuestFeatures.fStibp = 1;
4986	}
4987
4988	/* Make sure we have the speculation control MSR... */
4989	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
4990	if (!pMsrRange)
4991	{
4992	static CPUMMSRRANGE const s_SpecCtrl =
4993	{
4994	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
4995	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
4996	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4997	/.szName = / "IA32_SPEC_CTRL"
4998	};
4999	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
5000	AssertLogRelRC(rc);
5001	}
5002
5003	/* ... and the predictor command MSR. */
5004	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
5005	if (!pMsrRange)
5006	{
5007	/** @todo incorrect fWrGpMask. */
5008	static CPUMMSRRANGE const s_SpecCtrl =
5009	{
5010	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
5011	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
5012	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
5013	/.szName = / "IA32_PRED_CMD"
5014	};
5015	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
5016	AssertLogRelRC(rc);
5017	}
5018
5019	}
5020
5021	if (pVM->cpum.s.HostFeatures.fArchCap)
5022	{
5023	/* Install the architectural capabilities MSR. */
5024	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
5025	if (!pMsrRange)
5026	{
5027	static CPUMMSRRANGE const s_ArchCaps =
5028	{
5029	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
5030	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
5031	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
5032	/.szName = / "IA32_ARCH_CAPABILITIES"
5033	};
5034	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
5035	AssertLogRelRC(rc);
5036	}
5037
5038	/* Advertise IBRS_ALL if present at this point... */
5039	if (pVM->cpum.s.HostFeatures.fArchCap & MSR_IA32_ARCH_CAP_F_IBRS_ALL)
5040	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps \|= MSR_IA32_ARCH_CAP_F_IBRS_ALL);
5041	}
5042
5043	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
5044	}
5045	else if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
5046	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
5047	{
5048	/* The precise details of AMD's implementation are not yet clear. */
5049	}
5050	break;
5051
5052	default:
5053	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5054	break;
5055	}
5056
5057	/** @todo can probably kill this as this API is now init time only... */
5058	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5059	{
5060	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5061	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5062	}
5063	}
5064
5065
5066	/**
5067	* Queries a CPUID feature bit.
5068	*
5069	* @returns boolean for feature presence
5070	* @param pVM The cross context VM structure.
5071	* @param enmFeature The feature to query.
5072	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
5073	*/
5074	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
5075	{
5076	switch (enmFeature)
5077	{
5078	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
5079	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
5080	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
5081	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
5082	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
5083	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
5084	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
5085	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
5086	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
5087	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
5088	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
5089	case CPUMCPUIDFEATURE_INVALID:
5090	case CPUMCPUIDFEATURE_32BIT_HACK:
5091	break;
5092	}
5093	AssertFailed();
5094	return false;
5095	}
5096
5097
5098	/**
5099	* Clears a CPUID feature bit.
5100	*
5101	* @param pVM The cross context VM structure.
5102	* @param enmFeature The feature to clear.
5103	*
5104	* @deprecated Probably better to default the feature to disabled and only allow
5105	* setting (enabling) it during construction.
5106	*/
5107	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
5108	{
5109	PCPUMCPUIDLEAF pLeaf;
5110	switch (enmFeature)
5111	{
5112	case CPUMCPUIDFEATURE_APIC:
5113	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
5114	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5115	if (pLeaf)
5116	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
5117
5118	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5119	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
5120	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
5121
5122	pVM->cpum.s.GuestFeatures.fApic = 0;
5123	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
5124	break;
5125
5126	case CPUMCPUIDFEATURE_X2APIC:
5127	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
5128	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5129	if (pLeaf)
5130	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
5131	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
5132	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
5133	break;
5134
5135	case CPUMCPUIDFEATURE_PAE:
5136	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5137	if (pLeaf)
5138	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
5139
5140	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5141	if ( pLeaf
5142	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
5143	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
5144	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
5145
5146	pVM->cpum.s.GuestFeatures.fPae = 0;
5147	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
5148	break;
5149
5150	case CPUMCPUIDFEATURE_LONG_MODE:
5151	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5152	if (pLeaf)
5153	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
5154	pVM->cpum.s.GuestFeatures.fLongMode = 0;
5155	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = 32;
5156	if (pVM->cpum.s.GuestFeatures.fVmx)
5157	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5158	{
5159	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5160	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic \|= VMX_BASIC_PHYSADDR_WIDTH_32BIT;
5161	}
5162	break;
5163
5164	case CPUMCPUIDFEATURE_LAHF:
5165	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5166	if (pLeaf)
5167	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
5168	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
5169	break;
5170
5171	case CPUMCPUIDFEATURE_RDTSCP:
5172	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5173	if (pLeaf)
5174	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
5175	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
5176	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
5177	break;
5178
5179	case CPUMCPUIDFEATURE_HVP:
5180	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5181	if (pLeaf)
5182	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
5183	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
5184	break;
5185
5186	case CPUMCPUIDFEATURE_SPEC_CTRL:
5187	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
5188	if (pLeaf)
5189	pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP);
5190	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL);
5191	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
5192	break;
5193
5194	default:
5195	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5196	break;
5197	}
5198
5199	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5200	{
5201	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5202	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5203	}
5204	}
5205
5206
5207
5208	/*
5209	*
5210	*
5211	* Saved state related code.
5212	* Saved state related code.
5213	* Saved state related code.
5214	*
5215	*
5216	*/
5217
5218	/**
5219	* Called both in pass 0 and the final pass.
5220	*
5221	* @param pVM The cross context VM structure.
5222	* @param pSSM The saved state handle.
5223	*/
5224	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
5225	{
5226	/*
5227	* Save all the CPU ID leaves.
5228	*/
5229	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
5230	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5231	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
5232	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5233
5234	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5235
5236	/*
5237	* Save a good portion of the raw CPU IDs as well as they may come in
5238	* handy when validating features for raw mode.
5239	*/
5240	CPUMCPUID aRawStd[16];
5241	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
5242	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5243	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
5244	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
5245
5246	CPUMCPUID aRawExt[32];
5247	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
5248	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5249	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
5250	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
5251	}
5252
5253
5254	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5255	{
5256	uint32_t cCpuIds;
5257	int rc = SSMR3GetU32(pSSM, &cCpuIds);
5258	if (RT_SUCCESS(rc))
5259	{
5260	if (cCpuIds < 64)
5261	{
5262	for (uint32_t i = 0; i < cCpuIds; i++)
5263	{
5264	CPUMCPUID CpuId;
5265	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
5266	if (RT_FAILURE(rc))
5267	break;
5268
5269	CPUMCPUIDLEAF NewLeaf;
5270	NewLeaf.uLeaf = uBase + i;
5271	NewLeaf.uSubLeaf = 0;
5272	NewLeaf.fSubLeafMask = 0;
5273	NewLeaf.uEax = CpuId.uEax;
5274	NewLeaf.uEbx = CpuId.uEbx;
5275	NewLeaf.uEcx = CpuId.uEcx;
5276	NewLeaf.uEdx = CpuId.uEdx;
5277	NewLeaf.fFlags = 0;
5278	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
5279	}
5280	}
5281	else
5282	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5283	}
5284	if (RT_FAILURE(rc))
5285	{
5286	RTMemFree(*ppaLeaves);
5287	*ppaLeaves = NULL;
5288	*pcLeaves = 0;
5289	}
5290	return rc;
5291	}
5292
5293
5294	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5295	{
5296	*ppaLeaves = NULL;
5297	*pcLeaves = 0;
5298
5299	int rc;
5300	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
5301	{
5302	/*
5303	* The new format. Starts by declaring the leave size and count.
5304	*/
5305	uint32_t cbLeaf;
5306	SSMR3GetU32(pSSM, &cbLeaf);
5307	uint32_t cLeaves;
5308	rc = SSMR3GetU32(pSSM, &cLeaves);
5309	if (RT_SUCCESS(rc))
5310	{
5311	if (cbLeaf == sizeof(**ppaLeaves))
5312	{
5313	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
5314	{
5315	/*
5316	* Load the leaves one by one.
5317	*
5318	* The uPrev stuff is a kludge for working around a week worth of bad saved
5319	* states during the CPUID revamp in March 2015. We saved too many leaves
5320	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
5321	* garbage entires at the end of the array when restoring. We also had
5322	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
5323	* this kludge doesn't deal correctly with that, but who cares...
5324	*/
5325	uint32_t uPrev = 0;
5326	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
5327	{
5328	CPUMCPUIDLEAF Leaf;
5329	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
5330	if (RT_SUCCESS(rc))
5331	{
5332	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
5333	\|\| Leaf.uLeaf >= uPrev)
5334	{
5335	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5336	uPrev = Leaf.uLeaf;
5337	}
5338	else
5339	uPrev = UINT32_MAX;
5340	}
5341	}
5342	}
5343	else
5344	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5345	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5346	}
5347	else
5348	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5349	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5350	}
5351	}
5352	else
5353	{
5354	/*
5355	* The old format with its three inflexible arrays.
5356	*/
5357	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5358	if (RT_SUCCESS(rc))
5359	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5360	if (RT_SUCCESS(rc))
5361	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5362	if (RT_SUCCESS(rc))
5363	{
5364	/*
5365	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5366	*/
5367	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5368	if ( pLeaf
5369	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5370	{
5371	CPUMCPUIDLEAF Leaf;
5372	Leaf.uLeaf = 4;
5373	Leaf.fSubLeafMask = UINT32_MAX;
5374	Leaf.uSubLeaf = 0;
5375	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5376	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5377	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5378	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5379	\| UINT32_C(63); /* system coherency line size - 1 */
5380	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5381	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5382	\| (UINT32_C(1) << 5) /* cache level */
5383	\| UINT32_C(1); /* cache type (data) */
5384	Leaf.fFlags = 0;
5385	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5386	if (RT_SUCCESS(rc))
5387	{
5388	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5389	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5390	}
5391	if (RT_SUCCESS(rc))
5392	{
5393	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5394	Leaf.uEcx = 4095; /* sets - 1 */
5395	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5396	Leaf.uEbx \|= UINT32_C(23) << 22;
5397	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5398	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5399	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5400	Leaf.uEax \|= UINT32_C(2) << 5;
5401	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5402	}
5403	}
5404	}
5405	}
5406	return rc;
5407	}
5408
5409
5410	/**
5411	* Loads the CPU ID leaves saved by pass 0, inner worker.
5412	*
5413	* @returns VBox status code.
5414	* @param pVM The cross context VM structure.
5415	* @param pSSM The saved state handle.
5416	* @param uVersion The format version.
5417	* @param paLeaves Guest CPUID leaves loaded from the state.
5418	* @param cLeaves The number of leaves in @a paLeaves.
5419	* @param pMsrs The guest MSRs.
5420	*/
5421	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
5422	{
5423	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5424
5425	/*
5426	* Continue loading the state into stack buffers.
5427	*/
5428	CPUMCPUID GuestDefCpuId;
5429	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5430	AssertRCReturn(rc, rc);
5431
5432	CPUMCPUID aRawStd[16];
5433	uint32_t cRawStd;
5434	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5435	if (cRawStd > RT_ELEMENTS(aRawStd))
5436	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5437	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5438	AssertRCReturn(rc, rc);
5439	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5440	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5441
5442	CPUMCPUID aRawExt[32];
5443	uint32_t cRawExt;
5444	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5445	if (cRawExt > RT_ELEMENTS(aRawExt))
5446	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5447	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5448	AssertRCReturn(rc, rc);
5449	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5450	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5451
5452	/*
5453	* Get the raw CPU IDs for the current host.
5454	*/
5455	CPUMCPUID aHostRawStd[16];
5456	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5457	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5458
5459	CPUMCPUID aHostRawExt[32];
5460	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5461	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5462	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5463
5464	/*
5465	* Get the host and guest overrides so we don't reject the state because
5466	* some feature was enabled thru these interfaces.
5467	* Note! We currently only need the feature leaves, so skip rest.
5468	*/
5469	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5470	CPUMCPUID aHostOverrideStd[2];
5471	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5472	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5473
5474	CPUMCPUID aHostOverrideExt[2];
5475	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5476	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5477
5478	/*
5479	* This can be skipped.
5480	*/
5481	bool fStrictCpuIdChecks;
5482	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5483
5484	/*
5485	* Define a bunch of macros for simplifying the santizing/checking code below.
5486	*/
5487	/* Generic expression + failure message. */
5488	#define CPUID_CHECK_RET(expr, fmt) \
5489	do { \
5490	if (!(expr)) \
5491	{ \
5492	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5493	if (fStrictCpuIdChecks) \
5494	{ \
5495	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5496	RTStrFree(pszMsg); \
5497	return rcCpuid; \
5498	} \
5499	LogRel(("CPUM: %s\n", pszMsg)); \
5500	RTStrFree(pszMsg); \
5501	} \
5502	} while (0)
5503	#define CPUID_CHECK_WRN(expr, fmt) \
5504	do { \
5505	if (!(expr)) \
5506	LogRel(fmt); \
5507	} while (0)
5508
5509	/* For comparing two values and bitch if they differs. */
5510	#define CPUID_CHECK2_RET(what, host, saved) \
5511	do { \
5512	if ((host) != (saved)) \
5513	{ \
5514	if (fStrictCpuIdChecks) \
5515	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5516	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5517	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5518	} \
5519	} while (0)
5520	#define CPUID_CHECK2_WRN(what, host, saved) \
5521	do { \
5522	if ((host) != (saved)) \
5523	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5524	} while (0)
5525
5526	/* For checking raw cpu features (raw mode). */
5527	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5528	do { \
5529	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5530	{ \
5531	if (fStrictCpuIdChecks) \
5532	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5533	N_(#bit " mismatch: host=%d saved=%d"), \
5534	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5535	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5536	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5537	} \
5538	} while (0)
5539	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5540	do { \
5541	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5542	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5543	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5544	} while (0)
5545	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5546
5547	/* For checking guest features. */
5548	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5549	do { \
5550	if ( (aGuestCpuId##set [1].reg & bit) \
5551	&& !(aHostRaw##set [1].reg & bit) \
5552	&& !(aHostOverride##set [1].reg & bit) \
5553	) \
5554	{ \
5555	if (fStrictCpuIdChecks) \
5556	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5557	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5558	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5559	} \
5560	} while (0)
5561	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5562	do { \
5563	if ( (aGuestCpuId##set [1].reg & bit) \
5564	&& !(aHostRaw##set [1].reg & bit) \
5565	&& !(aHostOverride##set [1].reg & bit) \
5566	) \
5567	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5568	} while (0)
5569	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5570	do { \
5571	if ( (aGuestCpuId##set [1].reg & bit) \
5572	&& !(aHostRaw##set [1].reg & bit) \
5573	&& !(aHostOverride##set [1].reg & bit) \
5574	) \
5575	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5576	} while (0)
5577	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5578
5579	/* For checking guest features if AMD guest CPU. */
5580	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5581	do { \
5582	if ( (aGuestCpuId##set [1].reg & bit) \
5583	&& fGuestAmd \
5584	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5585	&& !(aHostOverride##set [1].reg & bit) \
5586	) \
5587	{ \
5588	if (fStrictCpuIdChecks) \
5589	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5590	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5591	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5592	} \
5593	} while (0)
5594	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5595	do { \
5596	if ( (aGuestCpuId##set [1].reg & bit) \
5597	&& fGuestAmd \
5598	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5599	&& !(aHostOverride##set [1].reg & bit) \
5600	) \
5601	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5602	} while (0)
5603	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5604	do { \
5605	if ( (aGuestCpuId##set [1].reg & bit) \
5606	&& fGuestAmd \
5607	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5608	&& !(aHostOverride##set [1].reg & bit) \
5609	) \
5610	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5611	} while (0)
5612	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5613
5614	/* For checking AMD features which have a corresponding bit in the standard
5615	range. (Intel defines very few bits in the extended feature sets.) */
5616	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5617	do { \
5618	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5619	&& !(fHostAmd \
5620	? aHostRawExt[1].reg & (ExtBit) \
5621	: aHostRawStd[1].reg & (StdBit)) \
5622	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5623	) \
5624	{ \
5625	if (fStrictCpuIdChecks) \
5626	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5627	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5628	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5629	} \
5630	} while (0)
5631	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5632	do { \
5633	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5634	&& !(fHostAmd \
5635	? aHostRawExt[1].reg & (ExtBit) \
5636	: aHostRawStd[1].reg & (StdBit)) \
5637	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5638	) \
5639	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5640	} while (0)
5641	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5642	do { \
5643	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5644	&& !(fHostAmd \
5645	? aHostRawExt[1].reg & (ExtBit) \
5646	: aHostRawStd[1].reg & (StdBit)) \
5647	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5648	) \
5649	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5650	} while (0)
5651	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5652
5653
5654	/*
5655	* Verify that we can support the features already exposed to the guest on
5656	* this host.
5657	*
5658	* Most of the features we're emulating requires intercepting instruction
5659	* and doing it the slow way, so there is no need to warn when they aren't
5660	* present in the host CPU. Thus we use IGN instead of EMU on these.
5661	*
5662	* Trailing comments:
5663	* "EMU" - Possible to emulate, could be lots of work and very slow.
5664	* "EMU?" - Can this be emulated?
5665	*/
5666	CPUMCPUID aGuestCpuIdStd[2];
5667	RT_ZERO(aGuestCpuIdStd);
5668	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5669
5670	/* CPUID(1).ecx */
5671	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5672	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5673	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5674	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5675	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5676	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5677	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5678	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5679	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5680	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5681	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5682	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5683	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5684	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5685	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5686	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5687	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5688	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5689	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5690	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5691	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5692	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5693	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5694	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5695	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5696	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5697	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5698	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5699	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5700	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5701	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5702	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5703
5704	/* CPUID(1).edx */
5705	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5706	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5707	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5708	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5709	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5710	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5711	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5712	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5713	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5714	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5715	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5716	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5717	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5718	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5719	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5720	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5721	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5722	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5723	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5724	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5725	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5726	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5727	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5728	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5729	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5730	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5731	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5732	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5733	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5734	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5735	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5736	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5737
5738	/* CPUID(0x80000000). */
5739	CPUMCPUID aGuestCpuIdExt[2];
5740	RT_ZERO(aGuestCpuIdExt);
5741	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5742	{
5743	/** @todo deal with no 0x80000001 on the host. */
5744	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx)
5745	\|\| ASMIsHygonCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5746	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx)
5747	\|\| ASMIsHygonCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5748
5749	/* CPUID(0x80000001).ecx */
5750	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5751	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5752	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5753	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5754	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5755	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5756	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5757	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5758	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5759	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5760	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5761	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5762	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5763	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5764	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5765	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5766	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5767	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5768	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5769	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5770	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5771	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5772	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5773	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5774	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5775	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5776	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5777	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5778	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5779	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5780	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5781	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5782
5783	/* CPUID(0x80000001).edx */
5784	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5785	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5786	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5787	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5788	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5789	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5790	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5791	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5792	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5793	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5794	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5795	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5796	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5797	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5798	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5799	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5800	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5801	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5802	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5803	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5804	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5805	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5806	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5807	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5808	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5809	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5810	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5811	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5812	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5813	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5814	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5815	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5816	}
5817
5818	/** @todo check leaf 7 */
5819
5820	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5821	* ECX=0: EAX - Valid bits in XCR0[31:0].
5822	* EBX - Maximum state size as per current XCR0 value.
5823	* ECX - Maximum state size for all supported features.
5824	* EDX - Valid bits in XCR0[63:32].
5825	* ECX=1: EAX - Various X-features.
5826	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5827	* ECX - Valid bits in IA32_XSS[31:0].
5828	* EDX - Valid bits in IA32_XSS[63:32].
5829	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5830	* if the bit invalid all four registers are set to zero.
5831	* EAX - The state size for this feature.
5832	* EBX - The state byte offset of this feature.
5833	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5834	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5835	*/
5836	uint64_t fGuestXcr0Mask = 0;
5837	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5838	if ( pCurLeaf
5839	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5840	&& ( pCurLeaf->uEax
5841	\|\| pCurLeaf->uEbx
5842	\|\| pCurLeaf->uEcx
5843	\|\| pCurLeaf->uEdx) )
5844	{
5845	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5846	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5847	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5848	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5849	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5850	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5851	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5852	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5853
5854	/* We don't support any additional features yet. */
5855	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5856	if (pCurLeaf && pCurLeaf->uEax)
5857	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5858	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5859	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5860	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5861	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5862	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5863
5864
5865	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5866	{
5867	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5868	if (pCurLeaf)
5869	{
5870	/* If advertised, the state component offset and size must match the one used by host. */
5871	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5872	{
5873	CPUMCPUID RawHost;
5874	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5875	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5876	if ( RawHost.uEbx != pCurLeaf->uEbx
5877	\|\| RawHost.uEax != pCurLeaf->uEax)
5878	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5879	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5880	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5881	}
5882	}
5883	}
5884	}
5885	/* Clear leaf 0xd just in case we're loading an old state... */
5886	else if (pCurLeaf)
5887	{
5888	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5889	{
5890	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5891	if (pCurLeaf)
5892	{
5893	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5894	\|\| ( pCurLeaf->uEax == 0
5895	&& pCurLeaf->uEbx == 0
5896	&& pCurLeaf->uEcx == 0
5897	&& pCurLeaf->uEdx == 0),
5898	("uVersion=%#x; %#x %#x %#x %#x\n",
5899	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5900	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5901	}
5902	}
5903	}
5904
5905	/* Update the fXStateGuestMask value for the VM. */
5906	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5907	{
5908	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5909	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5910	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5911	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5912	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5913	}
5914
5915	#undef CPUID_CHECK_RET
5916	#undef CPUID_CHECK_WRN
5917	#undef CPUID_CHECK2_RET
5918	#undef CPUID_CHECK2_WRN
5919	#undef CPUID_RAW_FEATURE_RET
5920	#undef CPUID_RAW_FEATURE_WRN
5921	#undef CPUID_RAW_FEATURE_IGN
5922	#undef CPUID_GST_FEATURE_RET
5923	#undef CPUID_GST_FEATURE_WRN
5924	#undef CPUID_GST_FEATURE_EMU
5925	#undef CPUID_GST_FEATURE_IGN
5926	#undef CPUID_GST_FEATURE2_RET
5927	#undef CPUID_GST_FEATURE2_WRN
5928	#undef CPUID_GST_FEATURE2_EMU
5929	#undef CPUID_GST_FEATURE2_IGN
5930	#undef CPUID_GST_AMD_FEATURE_RET
5931	#undef CPUID_GST_AMD_FEATURE_WRN
5932	#undef CPUID_GST_AMD_FEATURE_EMU
5933	#undef CPUID_GST_AMD_FEATURE_IGN
5934
5935	/*
5936	* We're good, commit the CPU ID leaves.
5937	*/
5938	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5939	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
5940	AssertLogRelRCReturn(rc, rc);
5941
5942	return VINF_SUCCESS;
5943	}
5944
5945
5946	/**
5947	* Loads the CPU ID leaves saved by pass 0.
5948	*
5949	* @returns VBox status code.
5950	* @param pVM The cross context VM structure.
5951	* @param pSSM The saved state handle.
5952	* @param uVersion The format version.
5953	* @param pMsrs The guest MSRs.
5954	*/
5955	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
5956	{
5957	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5958
5959	/*
5960	* Load the CPUID leaves array first and call worker to do the rest, just so
5961	* we can free the memory when we need to without ending up in column 1000.
5962	*/
5963	PCPUMCPUIDLEAF paLeaves;
5964	uint32_t cLeaves;
5965	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5966	AssertRC(rc);
5967	if (RT_SUCCESS(rc))
5968	{
5969	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
5970	RTMemFree(paLeaves);
5971	}
5972	return rc;
5973	}
5974
5975
5976
5977	/**
5978	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5979	*
5980	* @returns VBox status code.
5981	* @param pVM The cross context VM structure.
5982	* @param pSSM The saved state handle.
5983	* @param uVersion The format version.
5984	*/
5985	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5986	{
5987	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5988
5989	/*
5990	* Restore the CPUID leaves.
5991	*
5992	* Note that we support restoring less than the current amount of standard
5993	* leaves because we've been allowed more is newer version of VBox.
5994	*/
5995	uint32_t cElements;
5996	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5997	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5998	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5999	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
6000
6001	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6002	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
6003	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6004	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
6005
6006	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6007	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
6008	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6009	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
6010
6011	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
6012
6013	/*
6014	* Check that the basic cpuid id information is unchanged.
6015	*/
6016	/** @todo we should check the 64 bits capabilities too! */
6017	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
6018	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
6019	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
6020	uint32_t au32CpuIdSaved[8];
6021	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
6022	if (RT_SUCCESS(rc))
6023	{
6024	/* Ignore CPU stepping. */
6025	au32CpuId[4] &= 0xfffffff0;
6026	au32CpuIdSaved[4] &= 0xfffffff0;
6027
6028	/* Ignore APIC ID (AMD specs). */
6029	au32CpuId[5] &= ~0xff000000;
6030	au32CpuIdSaved[5] &= ~0xff000000;
6031
6032	/* Ignore the number of Logical CPUs (AMD specs). */
6033	au32CpuId[5] &= ~0x00ff0000;
6034	au32CpuIdSaved[5] &= ~0x00ff0000;
6035
6036	/* Ignore some advanced capability bits, that we don't expose to the guest. */
6037	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6038	\| X86_CPUID_FEATURE_ECX_VMX
6039	\| X86_CPUID_FEATURE_ECX_SMX
6040	\| X86_CPUID_FEATURE_ECX_EST
6041	\| X86_CPUID_FEATURE_ECX_TM2
6042	\| X86_CPUID_FEATURE_ECX_CNTXID
6043	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6044	\| X86_CPUID_FEATURE_ECX_PDCM
6045	\| X86_CPUID_FEATURE_ECX_DCA
6046	\| X86_CPUID_FEATURE_ECX_X2APIC
6047	);
6048	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6049	\| X86_CPUID_FEATURE_ECX_VMX
6050	\| X86_CPUID_FEATURE_ECX_SMX
6051	\| X86_CPUID_FEATURE_ECX_EST
6052	\| X86_CPUID_FEATURE_ECX_TM2
6053	\| X86_CPUID_FEATURE_ECX_CNTXID
6054	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6055	\| X86_CPUID_FEATURE_ECX_PDCM
6056	\| X86_CPUID_FEATURE_ECX_DCA
6057	\| X86_CPUID_FEATURE_ECX_X2APIC
6058	);
6059
6060	/* Make sure we don't forget to update the masks when enabling
6061	* features in the future.
6062	*/
6063	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
6064	( X86_CPUID_FEATURE_ECX_DTES64
6065	\| X86_CPUID_FEATURE_ECX_VMX
6066	\| X86_CPUID_FEATURE_ECX_SMX
6067	\| X86_CPUID_FEATURE_ECX_EST
6068	\| X86_CPUID_FEATURE_ECX_TM2
6069	\| X86_CPUID_FEATURE_ECX_CNTXID
6070	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6071	\| X86_CPUID_FEATURE_ECX_PDCM
6072	\| X86_CPUID_FEATURE_ECX_DCA
6073	\| X86_CPUID_FEATURE_ECX_X2APIC
6074	)));
6075	/* do the compare */
6076	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
6077	{
6078	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
6079	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
6080	"Saved=%.*Rhxs\n"
6081	"Real =%.*Rhxs\n",
6082	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6083	sizeof(au32CpuId), au32CpuId));
6084	else
6085	{
6086	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
6087	"Saved=%.*Rhxs\n"
6088	"Real =%.*Rhxs\n",
6089	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6090	sizeof(au32CpuId), au32CpuId));
6091	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
6092	}
6093	}
6094	}
6095
6096	return rc;
6097	}
6098
6099
6100
6101	/*
6102	*
6103	*
6104	* CPUID Info Handler.
6105	* CPUID Info Handler.
6106	* CPUID Info Handler.
6107	*
6108	*
6109	*/
6110
6111
6112
6113	/**
6114	* Get L1 cache / TLS associativity.
6115	*/
6116	static const char getCacheAss(unsigned u, char pszBuf)
6117	{
6118	if (u == 0)
6119	return "res0 ";
6120	if (u == 1)
6121	return "direct";
6122	if (u == 255)
6123	return "fully";
6124	if (u >= 256)
6125	return "???";
6126
6127	RTStrPrintf(pszBuf, 16, "%d way", u);
6128	return pszBuf;
6129	}
6130
6131
6132	/**
6133	* Get L2 cache associativity.
6134	*/
6135	const char *getL2CacheAss(unsigned u)
6136	{
6137	switch (u)
6138	{
6139	case 0: return "off ";
6140	case 1: return "direct";
6141	case 2: return "2 way ";
6142	case 3: return "res3 ";
6143	case 4: return "4 way ";
6144	case 5: return "res5 ";
6145	case 6: return "8 way ";
6146	case 7: return "res7 ";
6147	case 8: return "16 way";
6148	case 9: return "res9 ";
6149	case 10: return "res10 ";
6150	case 11: return "res11 ";
6151	case 12: return "res12 ";
6152	case 13: return "res13 ";
6153	case 14: return "res14 ";
6154	case 15: return "fully ";
6155	default: return "????";
6156	}
6157	}
6158
6159
6160	/** CPUID(1).EDX field descriptions. */
6161	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6162	{
6163	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6164	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6165	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6166	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6167	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6168	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6169	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6170	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6171	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6172	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6173	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6174	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6175	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6176	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6177	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6178	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6179	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6180	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6181	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6182	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6183	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6184	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6185	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6186	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6187	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6188	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6189	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6190	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6191	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6192	DBGFREGSUBFIELD_TERMINATOR()
6193	};
6194
6195	/** CPUID(1).ECX field descriptions. */
6196	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6197	{
6198	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6199	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6200	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6201	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6202	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6203	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6204	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6205	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6206	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6207	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6208	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6209	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6210	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6211	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6212	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6213	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6214	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6215	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6216	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6217	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6218	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6219	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6220	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6221	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6222	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6223	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6224	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6225	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6226	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6227	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6228	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6229	DBGFREGSUBFIELD_TERMINATOR()
6230	};
6231
6232	/** CPUID(7,0).EBX field descriptions. */
6233	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6234	{
6235	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6236	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6237	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6238	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6239	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6240	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6241	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6242	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6243	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6244	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6245	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6246	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6247	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6248	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6249	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6250	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6251	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6252	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6253	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6254	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6255	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6256	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6257	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6258	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6259	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6260	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6261	DBGFREGSUBFIELD_TERMINATOR()
6262	};
6263
6264	/** CPUID(7,0).ECX field descriptions. */
6265	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6266	{
6267	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6268	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6269	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6270	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6271	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6272	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6273	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6274	DBGFREGSUBFIELD_TERMINATOR()
6275	};
6276
6277	/** CPUID(7,0).EDX field descriptions. */
6278	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6279	{
6280	DBGFREGSUBFIELD_RO("MD_CLEAR\0" "Supports MDS related buffer clearing", 10, 1, 0),
6281	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6282	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6283	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
6284	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6285	DBGFREGSUBFIELD_RO("CORECAP\0" "Supports IA32_CORE_CAP", 30, 1, 0),
6286	DBGFREGSUBFIELD_RO("SSBD\0" "Supports IA32_SPEC_CTRL.SSBD", 31, 1, 0),
6287	DBGFREGSUBFIELD_TERMINATOR()
6288	};
6289
6290
6291	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6292	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6293	{
6294	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6295	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6296	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6297	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6298	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6299	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6300	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6301	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6302	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6303	DBGFREGSUBFIELD_TERMINATOR()
6304	};
6305
6306	/** CPUID(13,1).EAX field descriptions. */
6307	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6308	{
6309	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6310	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6311	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6312	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6313	DBGFREGSUBFIELD_TERMINATOR()
6314	};
6315
6316
6317	/** CPUID(0x80000001,0).EDX field descriptions. */
6318	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6319	{
6320	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6321	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6322	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6323	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6324	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6325	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6326	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6327	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6328	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6329	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6330	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6331	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6332	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6333	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6334	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6335	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6336	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6337	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6338	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6339	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6340	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6341	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6342	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6343	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6344	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6345	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6346	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6347	DBGFREGSUBFIELD_TERMINATOR()
6348	};
6349
6350	/** CPUID(0x80000001,0).ECX field descriptions. */
6351	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6352	{
6353	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6354	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6355	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6356	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6357	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6358	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6359	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6360	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6361	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6362	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6363	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6364	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6365	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6366	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6367	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6368	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6369	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6370	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6371	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6372	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6373	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6374	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6375	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6376	DBGFREGSUBFIELD_RO("PCX_L2I\0" "L2I/L3 Performance Counter Extensions", 28, 1, 0),
6377	DBGFREGSUBFIELD_RO("MWAITX\0" "MWAITX and MONITORX instructions", 29, 1, 0),
6378	DBGFREGSUBFIELD_TERMINATOR()
6379	};
6380
6381	/** CPUID(0x8000000a,0).EDX field descriptions. */
6382	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
6383	{
6384	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
6385	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
6386	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
6387	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
6388	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
6389	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
6390	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
6391	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
6392	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
6393	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
6394	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
6395	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
6396	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
6397	DBGFREGSUBFIELD_RO("GMET\0" "Guest Mode Execute Trap Extension", 17, 1, 0),
6398	DBGFREGSUBFIELD_TERMINATOR()
6399	};
6400
6401
6402	/** CPUID(0x80000007,0).EDX field descriptions. */
6403	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6404	{
6405	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6406	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6407	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6408	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6409	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6410	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6411	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6412	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6413	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6414	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6415	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6416	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6417	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6418	DBGFREGSUBFIELD_TERMINATOR()
6419	};
6420
6421	/** CPUID(0x80000008,0).EBX field descriptions. */
6422	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6423	{
6424	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6425	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6426	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6427	DBGFREGSUBFIELD_RO("RDPRU\0" "RDPRU instruction", 4, 1, 0),
6428	DBGFREGSUBFIELD_RO("MCOMMIT\0" "MCOMMIT instruction", 8, 1, 0),
6429	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6430	DBGFREGSUBFIELD_TERMINATOR()
6431	};
6432
6433
6434	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6435	const char *pszLeadIn, uint32_t cchWidth)
6436	{
6437	if (pszLeadIn)
6438	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6439
6440	for (uint32_t iBit = 0; iBit < 32; iBit++)
6441	if (RT_BIT_32(iBit) & uVal)
6442	{
6443	while ( pDesc->pszName != NULL
6444	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6445	pDesc++;
6446	if ( pDesc->pszName != NULL
6447	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6448	{
6449	if (pDesc->cBits == 1)
6450	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6451	else
6452	{
6453	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6454	if (pDesc->cBits < 32)
6455	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6456	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6457	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6458	}
6459	}
6460	else
6461	pHlp->pfnPrintf(pHlp, " %u", iBit);
6462	}
6463	if (pszLeadIn)
6464	pHlp->pfnPrintf(pHlp, "\n");
6465	}
6466
6467
6468	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6469	const char *pszLeadIn, uint32_t cchWidth)
6470	{
6471	if (pszLeadIn)
6472	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6473
6474	for (uint32_t iBit = 0; iBit < 64; iBit++)
6475	if (RT_BIT_64(iBit) & uVal)
6476	{
6477	while ( pDesc->pszName != NULL
6478	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6479	pDesc++;
6480	if ( pDesc->pszName != NULL
6481	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6482	{
6483	if (pDesc->cBits == 1)
6484	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6485	else
6486	{
6487	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6488	if (pDesc->cBits < 64)
6489	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6490	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6491	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6492	}
6493	}
6494	else
6495	pHlp->pfnPrintf(pHlp, " %u", iBit);
6496	}
6497	if (pszLeadIn)
6498	pHlp->pfnPrintf(pHlp, "\n");
6499	}
6500
6501
6502	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6503	const char *pszLeadIn, uint32_t cchWidth)
6504	{
6505	if (!uVal)
6506	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6507	else
6508	{
6509	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6510	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6511	pHlp->pfnPrintf(pHlp, " )\n");
6512	}
6513	}
6514
6515
6516	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6517	uint32_t cchWidth)
6518	{
6519	uint32_t uCombined = uVal1 \| uVal2;
6520	for (uint32_t iBit = 0; iBit < 32; iBit++)
6521	if ( (RT_BIT_32(iBit) & uCombined)
6522	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6523	{
6524	while ( pDesc->pszName != NULL
6525	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6526	pDesc++;
6527
6528	if ( pDesc->pszName != NULL
6529	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6530	{
6531	size_t cchMnemonic = strlen(pDesc->pszName);
6532	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6533	size_t cchDesc = strlen(pszDesc);
6534	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6535	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6536	if (pDesc->cBits < 32)
6537	{
6538	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6539	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6540	}
6541
6542	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6543	pDesc->pszName, pszDesc,
6544	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6545	uFieldValue1, uFieldValue2);
6546
6547	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6548	pDesc++;
6549	}
6550	else
6551	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6552	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6553	}
6554	}
6555
6556
6557	/**
6558	* Produces a detailed summary of standard leaf 0x00000001.
6559	*
6560	* @param pHlp The info helper functions.
6561	* @param pCurLeaf The 0x00000001 leaf.
6562	* @param fVerbose Whether to be very verbose or not.
6563	* @param fIntel Set if intel CPU.
6564	*/
6565	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6566	{
6567	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6568	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6569	uint32_t uEAX = pCurLeaf->uEax;
6570	uint32_t uEBX = pCurLeaf->uEbx;
6571
6572	pHlp->pfnPrintf(pHlp,
6573	"%36s %2d \tExtended: %d \tEffective: %d\n"
6574	"%36s %2d \tExtended: %d \tEffective: %d\n"
6575	"%36s %d\n"
6576	"%36s %d (%s)\n"
6577	"%36s %#04x\n"
6578	"%36s %d\n"
6579	"%36s %d\n"
6580	"%36s %#04x\n"
6581	,
6582	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6583	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6584	"Stepping:", ASMGetCpuStepping(uEAX),
6585	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6586	"APIC ID:", (uEBX >> 24) & 0xff,
6587	"Logical CPUs:",(uEBX >> 16) & 0xff,
6588	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6589	"Brand ID:", (uEBX >> 0) & 0xff);
6590	if (fVerbose)
6591	{
6592	CPUMCPUID Host;
6593	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6594	pHlp->pfnPrintf(pHlp, "Features\n");
6595	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6596	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6597	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6598	}
6599	else
6600	{
6601	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6602	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6603	}
6604	}
6605
6606
6607	/**
6608	* Produces a detailed summary of standard leaf 0x00000007.
6609	*
6610	* @param pHlp The info helper functions.
6611	* @param paLeaves The CPUID leaves array.
6612	* @param cLeaves The number of leaves in the array.
6613	* @param pCurLeaf The first 0x00000007 leaf.
6614	* @param fVerbose Whether to be very verbose or not.
6615	*/
6616	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6617	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6618	{
6619	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6620	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6621	for (;;)
6622	{
6623	CPUMCPUID Host;
6624	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6625
6626	switch (pCurLeaf->uSubLeaf)
6627	{
6628	case 0:
6629	if (fVerbose)
6630	{
6631	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6632	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6633	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6634	if (pCurLeaf->uEdx \|\| Host.uEdx)
6635	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6636	}
6637	else
6638	{
6639	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6640	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6641	if (pCurLeaf->uEdx)
6642	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6643	}
6644	break;
6645
6646	default:
6647	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6648	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6649	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6650	break;
6651
6652	}
6653
6654	/* advance. */
6655	pCurLeaf++;
6656	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6657	\|\| pCurLeaf->uLeaf != 0x7)
6658	break;
6659	}
6660	}
6661
6662
6663	/**
6664	* Produces a detailed summary of standard leaf 0x0000000d.
6665	*
6666	* @param pHlp The info helper functions.
6667	* @param paLeaves The CPUID leaves array.
6668	* @param cLeaves The number of leaves in the array.
6669	* @param pCurLeaf The first 0x00000007 leaf.
6670	* @param fVerbose Whether to be very verbose or not.
6671	*/
6672	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6673	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6674	{
6675	RT_NOREF_PV(fVerbose);
6676	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6677	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6678	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6679	{
6680	CPUMCPUID Host;
6681	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6682
6683	switch (uSubLeaf)
6684	{
6685	case 0:
6686	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6687	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6688	pCurLeaf->uEbx, pCurLeaf->uEcx);
6689	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6690
6691	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6692	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6693	"Valid XCR0 bits, guest:", 42);
6694	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6695	"Valid XCR0 bits, host:", 42);
6696	break;
6697
6698	case 1:
6699	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6700	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6701	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6702
6703	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6704	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6705	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6706
6707	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6708	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6709	" Valid IA32_XSS bits, guest:", 42);
6710	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6711	" Valid IA32_XSS bits, host:", 42);
6712	break;
6713
6714	default:
6715	if ( pCurLeaf
6716	&& pCurLeaf->uSubLeaf == uSubLeaf
6717	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6718	{
6719	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6720	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6721	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6722	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6723	if (pCurLeaf->uEdx)
6724	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6725	pHlp->pfnPrintf(pHlp, " --");
6726	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6727	pHlp->pfnPrintf(pHlp, "\n");
6728	}
6729	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6730	{
6731	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6732	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6733	if (Host.uEcx & ~RT_BIT_32(0))
6734	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6735	if (Host.uEdx)
6736	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6737	pHlp->pfnPrintf(pHlp, " --");
6738	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6739	pHlp->pfnPrintf(pHlp, "\n");
6740	}
6741	break;
6742
6743	}
6744
6745	/* advance. */
6746	if (pCurLeaf)
6747	{
6748	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6749	&& pCurLeaf->uSubLeaf <= uSubLeaf
6750	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6751	pCurLeaf++;
6752	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6753	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6754	pCurLeaf = NULL;
6755	}
6756	}
6757	}
6758
6759
6760	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6761	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6762	{
6763	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6764	&& pCurLeaf->uLeaf <= uUpToLeaf)
6765	{
6766	pHlp->pfnPrintf(pHlp,
6767	" %s\n"
6768	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6769	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6770	&& pCurLeaf->uLeaf <= uUpToLeaf)
6771	{
6772	CPUMCPUID Host;
6773	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6774	pHlp->pfnPrintf(pHlp,
6775	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6776	"Hst: %08x %08x %08x %08x\n",
6777	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6778	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6779	pCurLeaf++;
6780	}
6781	}
6782
6783	return pCurLeaf;
6784	}
6785
6786
6787	/**
6788	* Display the guest CpuId leaves.
6789	*
6790	* @param pVM The cross context VM structure.
6791	* @param pHlp The info helper functions.
6792	* @param pszArgs "terse", "default" or "verbose".
6793	*/
6794	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6795	{
6796	/*
6797	* Parse the argument.
6798	*/
6799	unsigned iVerbosity = 1;
6800	if (pszArgs)
6801	{
6802	pszArgs = RTStrStripL(pszArgs);
6803	if (!strcmp(pszArgs, "terse"))
6804	iVerbosity--;
6805	else if (!strcmp(pszArgs, "verbose"))
6806	iVerbosity++;
6807	}
6808
6809	uint32_t uLeaf;
6810	CPUMCPUID Host;
6811	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6812	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6813	PCCPUMCPUIDLEAF pCurLeaf;
6814	PCCPUMCPUIDLEAF pNextLeaf;
6815	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6816	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6817	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6818
6819	/*
6820	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6821	*/
6822	uint32_t cHstMax = ASMCpuId_EAX(0);
6823	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6824	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6825	pHlp->pfnPrintf(pHlp,
6826	" Raw Standard CPUID Leaves\n"
6827	" Leaf/sub-leaf eax ebx ecx edx\n");
6828	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6829	{
6830	uint32_t cMaxSubLeaves = 1;
6831	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6832	cMaxSubLeaves = 16;
6833	else if (uLeaf == 0xd)
6834	cMaxSubLeaves = 128;
6835
6836	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6837	{
6838	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6839	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6840	&& pCurLeaf->uLeaf == uLeaf
6841	&& pCurLeaf->uSubLeaf == uSubLeaf)
6842	{
6843	pHlp->pfnPrintf(pHlp,
6844	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6845	"Hst: %08x %08x %08x %08x\n",
6846	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6847	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6848	pCurLeaf++;
6849	}
6850	else if ( uLeaf != 0xd
6851	\|\| uSubLeaf <= 1
6852	\|\| Host.uEbx != 0 )
6853	pHlp->pfnPrintf(pHlp,
6854	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6855	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6856
6857	/* Done? */
6858	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6859	\|\| pCurLeaf->uLeaf != uLeaf)
6860	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6861	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6862	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6863	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6864	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6865	)
6866	)
6867	break;
6868	}
6869	}
6870	pNextLeaf = pCurLeaf;
6871
6872	/*
6873	* If verbose, decode it.
6874	*/
6875	if (iVerbosity && paLeaves[0].uLeaf == 0)
6876	pHlp->pfnPrintf(pHlp,
6877	"%36s %.04s%.04s%.04s\n"
6878	"%36s 0x00000000-%#010x\n"
6879	,
6880	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6881	"Supports:", paLeaves[0].uEax);
6882
6883	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6884	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6885
6886	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6887	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6888
6889	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6890	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6891
6892	pCurLeaf = pNextLeaf;
6893
6894	/*
6895	* Hypervisor leaves.
6896	*
6897	* Unlike most of the other leaves reported, the guest hypervisor leaves
6898	* aren't a subset of the host CPUID bits.
6899	*/
6900	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6901
6902	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6903	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6904	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6905	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6906	cMax = RT_MAX(cHstMax, cGstMax);
6907	if (cMax >= UINT32_C(0x40000000))
6908	{
6909	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6910
6911	/** @todo dump these in more detail. */
6912
6913	pCurLeaf = pNextLeaf;
6914	}
6915
6916
6917	/*
6918	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6919	* Implemented after AMD specs.
6920	*/
6921	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6922
6923	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6924	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6925	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6926	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6927	cMax = RT_MAX(cHstMax, cGstMax);
6928	if (cMax >= UINT32_C(0x80000000))
6929	{
6930
6931	pHlp->pfnPrintf(pHlp,
6932	" Raw Extended CPUID Leaves\n"
6933	" Leaf/sub-leaf eax ebx ecx edx\n");
6934	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6935	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6936	{
6937	uint32_t cMaxSubLeaves = 1;
6938	if (uLeaf == UINT32_C(0x8000001d))
6939	cMaxSubLeaves = 16;
6940
6941	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6942	{
6943	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6944	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6945	&& pCurLeaf->uLeaf == uLeaf
6946	&& pCurLeaf->uSubLeaf == uSubLeaf)
6947	{
6948	pHlp->pfnPrintf(pHlp,
6949	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6950	"Hst: %08x %08x %08x %08x\n",
6951	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6952	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6953	pCurLeaf++;
6954	}
6955	else if ( uLeaf != 0xd
6956	\|\| uSubLeaf <= 1
6957	\|\| Host.uEbx != 0 )
6958	pHlp->pfnPrintf(pHlp,
6959	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6960	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6961
6962	/* Done? */
6963	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6964	\|\| pCurLeaf->uLeaf != uLeaf)
6965	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6966	break;
6967	}
6968	}
6969	pNextLeaf = pCurLeaf;
6970
6971	/*
6972	* Understandable output
6973	*/
6974	if (iVerbosity)
6975	pHlp->pfnPrintf(pHlp,
6976	"Ext Name: %.4s%.4s%.4s\n"
6977	"Ext Supports: 0x80000000-%#010x\n",
6978	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6979
6980	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6981	if (iVerbosity && pCurLeaf)
6982	{
6983	uint32_t uEAX = pCurLeaf->uEax;
6984	pHlp->pfnPrintf(pHlp,
6985	"Family: %d \tExtended: %d \tEffective: %d\n"
6986	"Model: %d \tExtended: %d \tEffective: %d\n"
6987	"Stepping: %d\n"
6988	"Brand ID: %#05x\n",
6989	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6990	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6991	ASMGetCpuStepping(uEAX),
6992	pCurLeaf->uEbx & 0xfff);
6993
6994	if (iVerbosity == 1)
6995	{
6996	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6997	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6998	}
6999	else
7000	{
7001	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7002	pHlp->pfnPrintf(pHlp, "Ext Features\n");
7003	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
7004	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
7005	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
7006	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
7007	{
7008	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
7009	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7010	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
7011	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
7012	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
7013	}
7014	}
7015	}
7016
7017	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
7018	{
7019	char szString[443+1] = {0};
7020	uint32_t pu32 = (uint32_t )szString;
7021	*pu32++ = pCurLeaf->uEax;
7022	*pu32++ = pCurLeaf->uEbx;
7023	*pu32++ = pCurLeaf->uEcx;
7024	*pu32++ = pCurLeaf->uEdx;
7025	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
7026	if (pCurLeaf)
7027	{
7028	*pu32++ = pCurLeaf->uEax;
7029	*pu32++ = pCurLeaf->uEbx;
7030	*pu32++ = pCurLeaf->uEcx;
7031	*pu32++ = pCurLeaf->uEdx;
7032	}
7033	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
7034	if (pCurLeaf)
7035	{
7036	*pu32++ = pCurLeaf->uEax;
7037	*pu32++ = pCurLeaf->uEbx;
7038	*pu32++ = pCurLeaf->uEcx;
7039	*pu32++ = pCurLeaf->uEdx;
7040	}
7041	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
7042	}
7043
7044	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
7045	{
7046	uint32_t uEAX = pCurLeaf->uEax;
7047	uint32_t uEBX = pCurLeaf->uEbx;
7048	uint32_t uECX = pCurLeaf->uEcx;
7049	uint32_t uEDX = pCurLeaf->uEdx;
7050	char sz1[32];
7051	char sz2[32];
7052
7053	pHlp->pfnPrintf(pHlp,
7054	"TLB 2/4M Instr/Uni: %s %3d entries\n"
7055	"TLB 2/4M Data: %s %3d entries\n",
7056	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
7057	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
7058	pHlp->pfnPrintf(pHlp,
7059	"TLB 4K Instr/Uni: %s %3d entries\n"
7060	"TLB 4K Data: %s %3d entries\n",
7061	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
7062	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
7063	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
7064	"L1 Instr Cache Lines Per Tag: %d\n"
7065	"L1 Instr Cache Associativity: %s\n"
7066	"L1 Instr Cache Size: %d KB\n",
7067	(uEDX >> 0) & 0xff,
7068	(uEDX >> 8) & 0xff,
7069	getCacheAss((uEDX >> 16) & 0xff, sz1),
7070	(uEDX >> 24) & 0xff);
7071	pHlp->pfnPrintf(pHlp,
7072	"L1 Data Cache Line Size: %d bytes\n"
7073	"L1 Data Cache Lines Per Tag: %d\n"
7074	"L1 Data Cache Associativity: %s\n"
7075	"L1 Data Cache Size: %d KB\n",
7076	(uECX >> 0) & 0xff,
7077	(uECX >> 8) & 0xff,
7078	getCacheAss((uECX >> 16) & 0xff, sz1),
7079	(uECX >> 24) & 0xff);
7080	}
7081
7082	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
7083	{
7084	uint32_t uEAX = pCurLeaf->uEax;
7085	uint32_t uEBX = pCurLeaf->uEbx;
7086	uint32_t uEDX = pCurLeaf->uEdx;
7087
7088	pHlp->pfnPrintf(pHlp,
7089	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
7090	"L2 TLB 2/4M Data: %s %4d entries\n",
7091	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
7092	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
7093	pHlp->pfnPrintf(pHlp,
7094	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
7095	"L2 TLB 4K Data: %s %4d entries\n",
7096	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
7097	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
7098	pHlp->pfnPrintf(pHlp,
7099	"L2 Cache Line Size: %d bytes\n"
7100	"L2 Cache Lines Per Tag: %d\n"
7101	"L2 Cache Associativity: %s\n"
7102	"L2 Cache Size: %d KB\n",
7103	(uEDX >> 0) & 0xff,
7104	(uEDX >> 8) & 0xf,
7105	getL2CacheAss((uEDX >> 12) & 0xf),
7106	(uEDX >> 16) & 0xffff);
7107	}
7108
7109	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
7110	{
7111	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7112	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
7113	{
7114	if (iVerbosity < 1)
7115	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
7116	else
7117	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
7118	}
7119	}
7120
7121	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
7122	if (pCurLeaf != NULL)
7123	{
7124	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7125	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
7126	{
7127	if (iVerbosity < 1)
7128	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
7129	else
7130	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
7131	}
7132
7133	if (iVerbosity)
7134	{
7135	uint32_t uEAX = pCurLeaf->uEax;
7136	uint32_t uECX = pCurLeaf->uEcx;
7137
7138	/** @todo 0x80000008:EAX[23:16] is only defined for AMD. We'll get 0 on Intel. On
7139	* AMD if we get 0, the guest physical address width should be taken from
7140	* 0x80000008:EAX[7:0] instead. Guest Physical address width is relevant
7141	* for guests using nested paging. */
7142	pHlp->pfnPrintf(pHlp,
7143	"Physical Address Width: %d bits\n"
7144	"Virtual Address Width: %d bits\n"
7145	"Guest Physical Address Width: %d bits\n",
7146	(uEAX >> 0) & 0xff,
7147	(uEAX >> 8) & 0xff,
7148	(uEAX >> 16) & 0xff);
7149
7150	/** @todo 0x80000008:ECX is reserved on Intel (we'll get incorrect physical core
7151	* count here). */
7152	pHlp->pfnPrintf(pHlp,
7153	"Physical Core Count: %d\n",
7154	((uECX >> 0) & 0xff) + 1);
7155	}
7156	}
7157
7158	pCurLeaf = pNextLeaf;
7159	}
7160
7161
7162
7163	/*
7164	* Centaur.
7165	*/
7166	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7167
7168	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7169	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7170	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7171	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7172	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7173	cMax = RT_MAX(cHstMax, cGstMax);
7174	if (cMax >= UINT32_C(0xc0000000))
7175	{
7176	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7177
7178	/*
7179	* Understandable output
7180	*/
7181	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7182	pHlp->pfnPrintf(pHlp,
7183	"Centaur Supports: 0xc0000000-%#010x\n",
7184	pCurLeaf->uEax);
7185
7186	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7187	{
7188	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7189	uint32_t uEdxGst = pCurLeaf->uEdx;
7190	uint32_t uEdxHst = Host.uEdx;
7191
7192	if (iVerbosity == 1)
7193	{
7194	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7195	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7196	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7197	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7198	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7199	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7200	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7201	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7202	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7203	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7204	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7205	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7206	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7207	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7208	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7209	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7210	for (unsigned iBit = 14; iBit < 32; iBit++)
7211	if (uEdxGst & RT_BIT(iBit))
7212	pHlp->pfnPrintf(pHlp, " %d", iBit);
7213	pHlp->pfnPrintf(pHlp, "\n");
7214	}
7215	else
7216	{
7217	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7218	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7219	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7220	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7221	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7222	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7223	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7224	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7225	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7226	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7227	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7228	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7229	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7230	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7231	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7232	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7233	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7234	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7235	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7236	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7237	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7238	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7239	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7240	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7241	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7242	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7243	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7244	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7245	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7246	for (unsigned iBit = 27; iBit < 32; iBit++)
7247	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7248	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7249	pHlp->pfnPrintf(pHlp, "\n");
7250	}
7251	}
7252
7253	pCurLeaf = pNextLeaf;
7254	}
7255
7256	/*
7257	* The remainder.
7258	*/
7259	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7260	}
7261
7262	#endif /* !IN_VBOX_CPU_REPORT */
7263

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 91276

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