CPUMR3CpuId.cpp@ 82255

Last change on this file since 82255 was 81786, checked in by vboxsync, 5 years ago
VMM: Nested VMX: bugref:9180 Implement VMX-preemption timer for nested-guest. It's still disabled though.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 336.6 KB

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1	/* $Id: CPUMR3CpuId.cpp 81786 2019-11-12 04:20:34Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vm.h>
30	#include <VBox/vmm/mm.h>
31	#include <VBox/sup.h>
32
33	#include <VBox/err.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/ctype.h>
36	#include <iprt/mem.h>
37	#include <iprt/string.h>
38
39
40	/*********************************************************************************************************************************
41	* Defined Constants And Macros *
42	*********************************************************************************************************************************/
43	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
44	#define CPUM_CPUID_MAX_LEAVES 2048
45	/* Max size we accept for the XSAVE area. */
46	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
47	/* Min size we accept for the XSAVE area. */
48	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
49
50
51	/*********************************************************************************************************************************
52	* Global Variables *
53	*********************************************************************************************************************************/
54	/**
55	* The intel pentium family.
56	*/
57	static const CPUMMICROARCH g_aenmIntelFamily06[] =
58	{
59	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
60	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
61	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
63	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
64	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
65	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
66	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
67	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
68	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
69	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
70	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
71	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
72	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
73	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
74	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
75	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
81	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
82	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
83	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [26(0x1a)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Nehalem-EP */
86	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
87	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
88	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
89	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
90	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
91	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
97	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
98	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
99	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
102	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
103	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
104	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
105	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
106	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
107	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
113	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
114	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
115	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
118	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
120	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
121	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
122	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
130	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
131	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
134	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
136	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
137	/* [78(0x4e)] = */ kCpumMicroarch_Intel_Core7_Skylake,
138	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Broadwell-E */
139	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu; skylake <= 4, cascade lake > 5 */
145	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
146	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
147	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
150	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
151	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
152	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
153	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
154	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
155	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
159	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
160	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
161	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
162	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
163	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
164	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
165	/[106(0x6a)] = / kCpumMicroarch_Intel_Unknown,
166	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
167	/[108(0x6c)] = / kCpumMicroarch_Intel_Unknown,
168	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
169	/[110(0x6e)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
170	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
171	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
172	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
173	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
174	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
175	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
176	/[117(0x75)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
177	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
178	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
179	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
180	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
181	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
182	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
183	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
184	/[125(0x7d)] = / kCpumMicroarch_Intel_Unknown,
185	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
186	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
187	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
188	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
189	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
190	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
191	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
192	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
193	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
194	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
195	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
196	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
197	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
198	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
199	/[140(0x8c)] = / kCpumMicroarch_Intel_Unknown,
200	/[141(0x8d)] = / kCpumMicroarch_Intel_Unknown,
201	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
202	/[143(0x8f)] = / kCpumMicroarch_Intel_Unknown,
203	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
204	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
205	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
206	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
207	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
208	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
209	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
210	/[151(0x97)] = / kCpumMicroarch_Intel_Unknown,
211	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
212	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
213	/[154(0x9a)] = / kCpumMicroarch_Intel_Unknown,
214	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
215	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
216	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
217	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
218	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
219	};
220	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0x9f+1);
221
222
223	/**
224	* Figures out the (sub-)micro architecture given a bit of CPUID info.
225	*
226	* @returns Micro architecture.
227	* @param enmVendor The CPU vendor .
228	* @param bFamily The CPU family.
229	* @param bModel The CPU model.
230	* @param bStepping The CPU stepping.
231	*/
232	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
233	uint8_t bModel, uint8_t bStepping)
234	{
235	if (enmVendor == CPUMCPUVENDOR_AMD)
236	{
237	switch (bFamily)
238	{
239	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
240	case 0x03: return kCpumMicroarch_AMD_Am386;
241	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
242	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
243	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
244	case 0x06:
245	switch (bModel)
246	{
247	case 0: return kCpumMicroarch_AMD_K7_Palomino;
248	case 1: return kCpumMicroarch_AMD_K7_Palomino;
249	case 2: return kCpumMicroarch_AMD_K7_Palomino;
250	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
251	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
252	case 6: return kCpumMicroarch_AMD_K7_Palomino;
253	case 7: return kCpumMicroarch_AMD_K7_Morgan;
254	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
255	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
256	}
257	return kCpumMicroarch_AMD_K7_Unknown;
258	case 0x0f:
259	/*
260	* This family is a friggin mess. Trying my best to make some
261	* sense out of it. Too much happened in the 0x0f family to
262	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
263	*
264	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
265	* cpu-world.com, and other places:
266	* - 130nm:
267	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
268	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
269	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
270	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
271	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
272	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
273	* - 90nm:
274	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
275	* - Oakville: 10FC0/DH-D0.
276	* - Georgetown: 10FC0/DH-D0.
277	* - Sonora: 10FC0/DH-D0.
278	* - Venus: 20F71/SH-E4
279	* - Troy: 20F51/SH-E4
280	* - Athens: 20F51/SH-E4
281	* - San Diego: 20F71/SH-E4.
282	* - Lancaster: 20F42/SH-E5
283	* - Newark: 20F42/SH-E5.
284	* - Albany: 20FC2/DH-E6.
285	* - Roma: 20FC2/DH-E6.
286	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
287	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
288	* - 90nm introducing Dual core:
289	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
290	* - Italy: 20F10/JH-E1, 20F12/JH-E6
291	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
292	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
293	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
294	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
295	* - Santa Ana: 40F32/JH-F2, /-F3
296	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
297	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
298	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
299	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
300	* - Keene: 40FC2/DH-F2.
301	* - Richmond: 40FC2/DH-F2
302	* - Taylor: 40F82/BH-F2
303	* - Trinidad: 40F82/BH-F2
304	*
305	* - 65nm:
306	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
307	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
308	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
309	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
310	* - Sherman: /-G1, 70FC2/DH-G2.
311	* - Huron: 70FF2/DH-G2.
312	*/
313	if (bModel < 0x10)
314	return kCpumMicroarch_AMD_K8_130nm;
315	if (bModel >= 0x60 && bModel < 0x80)
316	return kCpumMicroarch_AMD_K8_65nm;
317	if (bModel >= 0x40)
318	return kCpumMicroarch_AMD_K8_90nm_AMDV;
319	switch (bModel)
320	{
321	case 0x21:
322	case 0x23:
323	case 0x2b:
324	case 0x2f:
325	case 0x37:
326	case 0x3f:
327	return kCpumMicroarch_AMD_K8_90nm_DualCore;
328	}
329	return kCpumMicroarch_AMD_K8_90nm;
330	case 0x10:
331	return kCpumMicroarch_AMD_K10;
332	case 0x11:
333	return kCpumMicroarch_AMD_K10_Lion;
334	case 0x12:
335	return kCpumMicroarch_AMD_K10_Llano;
336	case 0x14:
337	return kCpumMicroarch_AMD_Bobcat;
338	case 0x15:
339	switch (bModel)
340	{
341	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
342	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
343	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
344	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
345	case 0x11: /* ?? */
346	case 0x12: /* ?? */
347	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
348	}
349	return kCpumMicroarch_AMD_15h_Unknown;
350	case 0x16:
351	return kCpumMicroarch_AMD_Jaguar;
352	case 0x17:
353	return kCpumMicroarch_AMD_Zen_Ryzen;
354	}
355	return kCpumMicroarch_AMD_Unknown;
356	}
357
358	if (enmVendor == CPUMCPUVENDOR_INTEL)
359	{
360	switch (bFamily)
361	{
362	case 3:
363	return kCpumMicroarch_Intel_80386;
364	case 4:
365	return kCpumMicroarch_Intel_80486;
366	case 5:
367	return kCpumMicroarch_Intel_P5;
368	case 6:
369	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
370	{
371	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
372	if (enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake)
373	{
374	if (bStepping >= 0xa && bStepping <= 0xc)
375	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
376	else if (bStepping >= 0xc)
377	enmMicroArch = kCpumMicroarch_Intel_Core7_WhiskeyLake;
378	}
379	else if ( enmMicroArch == kCpumMicroarch_Intel_Core7_Skylake
380	&& bModel == 0x55
381	&& bStepping >= 5)
382	enmMicroArch = kCpumMicroarch_Intel_Core7_CascadeLake;
383	return enmMicroArch;
384	}
385	return kCpumMicroarch_Intel_Atom_Unknown;
386	case 15:
387	switch (bModel)
388	{
389	case 0: return kCpumMicroarch_Intel_NB_Willamette;
390	case 1: return kCpumMicroarch_Intel_NB_Willamette;
391	case 2: return kCpumMicroarch_Intel_NB_Northwood;
392	case 3: return kCpumMicroarch_Intel_NB_Prescott;
393	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
394	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
395	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
396	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
397	default: return kCpumMicroarch_Intel_NB_Unknown;
398	}
399	break;
400	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
401	case 0:
402	return kCpumMicroarch_Intel_8086;
403	case 1:
404	return kCpumMicroarch_Intel_80186;
405	case 2:
406	return kCpumMicroarch_Intel_80286;
407	}
408	return kCpumMicroarch_Intel_Unknown;
409	}
410
411	if (enmVendor == CPUMCPUVENDOR_VIA)
412	{
413	switch (bFamily)
414	{
415	case 5:
416	switch (bModel)
417	{
418	case 1: return kCpumMicroarch_Centaur_C6;
419	case 4: return kCpumMicroarch_Centaur_C6;
420	case 8: return kCpumMicroarch_Centaur_C2;
421	case 9: return kCpumMicroarch_Centaur_C3;
422	}
423	break;
424
425	case 6:
426	switch (bModel)
427	{
428	case 5: return kCpumMicroarch_VIA_C3_M2;
429	case 6: return kCpumMicroarch_VIA_C3_C5A;
430	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
431	case 8: return kCpumMicroarch_VIA_C3_C5N;
432	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
433	case 10: return kCpumMicroarch_VIA_C7_C5J;
434	case 15: return kCpumMicroarch_VIA_Isaiah;
435	}
436	break;
437	}
438	return kCpumMicroarch_VIA_Unknown;
439	}
440
441	if (enmVendor == CPUMCPUVENDOR_SHANGHAI)
442	{
443	switch (bFamily)
444	{
445	case 6:
446	case 7:
447	return kCpumMicroarch_Shanghai_Wudaokou;
448	default:
449	break;
450	}
451	return kCpumMicroarch_Shanghai_Unknown;
452	}
453
454	if (enmVendor == CPUMCPUVENDOR_CYRIX)
455	{
456	switch (bFamily)
457	{
458	case 4:
459	switch (bModel)
460	{
461	case 9: return kCpumMicroarch_Cyrix_5x86;
462	}
463	break;
464
465	case 5:
466	switch (bModel)
467	{
468	case 2: return kCpumMicroarch_Cyrix_M1;
469	case 4: return kCpumMicroarch_Cyrix_MediaGX;
470	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
471	}
472	break;
473
474	case 6:
475	switch (bModel)
476	{
477	case 0: return kCpumMicroarch_Cyrix_M2;
478	}
479	break;
480
481	}
482	return kCpumMicroarch_Cyrix_Unknown;
483	}
484
485	if (enmVendor == CPUMCPUVENDOR_HYGON)
486	{
487	switch (bFamily)
488	{
489	case 0x18:
490	return kCpumMicroarch_Hygon_Dhyana;
491	default:
492	break;
493	}
494	return kCpumMicroarch_Hygon_Unknown;
495	}
496
497	return kCpumMicroarch_Unknown;
498	}
499
500
501	/**
502	* Translates a microarchitecture enum value to the corresponding string
503	* constant.
504	*
505	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
506	* NULL if the value is invalid.
507	*
508	* @param enmMicroarch The enum value to convert.
509	*/
510	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
511	{
512	switch (enmMicroarch)
513	{
514	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
515	CASE_RET_STR(kCpumMicroarch_Intel_8086);
516	CASE_RET_STR(kCpumMicroarch_Intel_80186);
517	CASE_RET_STR(kCpumMicroarch_Intel_80286);
518	CASE_RET_STR(kCpumMicroarch_Intel_80386);
519	CASE_RET_STR(kCpumMicroarch_Intel_80486);
520	CASE_RET_STR(kCpumMicroarch_Intel_P5);
521
522	CASE_RET_STR(kCpumMicroarch_Intel_P6);
523	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
524	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
525
526	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
527	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
528	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
529
530	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
531	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
532
533	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
534	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
535	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
536	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
537	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
538	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
539	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
540	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
541	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
542	CASE_RET_STR(kCpumMicroarch_Intel_Core7_WhiskeyLake);
543	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CascadeLake);
544	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
545	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
546	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
547
548	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
549	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
550	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
551	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
552	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
553	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
554	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
555	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
556
557	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
558	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
559	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
560	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
561	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
562
563	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
564	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
565	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
566	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
567	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
568	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
569	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
570
571	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
572
573	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
574	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
575	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
576	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
577	CASE_RET_STR(kCpumMicroarch_AMD_K5);
578	CASE_RET_STR(kCpumMicroarch_AMD_K6);
579
580	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
581	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
582	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
583	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
584	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
585	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
586	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
587
588	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
589	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
590	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
591	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
592	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
593
594	CASE_RET_STR(kCpumMicroarch_AMD_K10);
595	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
596	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
597	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
598	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
599
600	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
601	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
602	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
603	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
604	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
605
606	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
607
608	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
609
610	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
611
612	CASE_RET_STR(kCpumMicroarch_Hygon_Dhyana);
613	CASE_RET_STR(kCpumMicroarch_Hygon_Unknown);
614
615	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
616	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
617	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
618	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
619	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
620	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
621	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
622	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
623	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
624	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
625	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
626	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
627	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
628
629	CASE_RET_STR(kCpumMicroarch_Shanghai_Wudaokou);
630	CASE_RET_STR(kCpumMicroarch_Shanghai_Unknown);
631
632	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
633	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
634	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
635	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
636	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
637	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
638
639	CASE_RET_STR(kCpumMicroarch_NEC_V20);
640	CASE_RET_STR(kCpumMicroarch_NEC_V30);
641
642	CASE_RET_STR(kCpumMicroarch_Unknown);
643
644	#undef CASE_RET_STR
645	case kCpumMicroarch_Invalid:
646	case kCpumMicroarch_Intel_End:
647	case kCpumMicroarch_Intel_Core2_End:
648	case kCpumMicroarch_Intel_Core7_End:
649	case kCpumMicroarch_Intel_Atom_End:
650	case kCpumMicroarch_Intel_P6_Core_Atom_End:
651	case kCpumMicroarch_Intel_Phi_End:
652	case kCpumMicroarch_Intel_NB_End:
653	case kCpumMicroarch_AMD_K7_End:
654	case kCpumMicroarch_AMD_K8_End:
655	case kCpumMicroarch_AMD_15h_End:
656	case kCpumMicroarch_AMD_16h_End:
657	case kCpumMicroarch_AMD_Zen_End:
658	case kCpumMicroarch_AMD_End:
659	case kCpumMicroarch_Hygon_End:
660	case kCpumMicroarch_VIA_End:
661	case kCpumMicroarch_Shanghai_End:
662	case kCpumMicroarch_Cyrix_End:
663	case kCpumMicroarch_NEC_End:
664	case kCpumMicroarch_32BitHack:
665	break;
666	/* no default! */
667	}
668
669	return NULL;
670	}
671
672
673	/**
674	* Determins the host CPU MXCSR mask.
675	*
676	* @returns MXCSR mask.
677	*/
678	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
679	{
680	if ( ASMHasCpuId()
681	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
682	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
683	{
684	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
685	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
686	RT_ZERO(*pState);
687	ASMFxSave(pState);
688	if (pState->MXCSR_MASK == 0)
689	return 0xffbf;
690	return pState->MXCSR_MASK;
691	}
692	return 0;
693	}
694
695
696	/**
697	* Gets a matching leaf in the CPUID leaf array.
698	*
699	* @returns Pointer to the matching leaf, or NULL if not found.
700	* @param paLeaves The CPUID leaves to search. This is sorted.
701	* @param cLeaves The number of leaves in the array.
702	* @param uLeaf The leaf to locate.
703	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
704	*/
705	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
706	{
707	/* Lazy bird does linear lookup here since this is only used for the
708	occational CPUID overrides. */
709	for (uint32_t i = 0; i < cLeaves; i++)
710	if ( paLeaves[i].uLeaf == uLeaf
711	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
712	return &paLeaves[i];
713	return NULL;
714	}
715
716
717	#ifndef IN_VBOX_CPU_REPORT
718	/**
719	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
720	*
721	* @returns true if found, false it not.
722	* @param paLeaves The CPUID leaves to search. This is sorted.
723	* @param cLeaves The number of leaves in the array.
724	* @param uLeaf The leaf to locate.
725	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
726	* @param pLegacy The legacy output leaf.
727	*/
728	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
729	PCPUMCPUID pLegacy)
730	{
731	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
732	if (pLeaf)
733	{
734	pLegacy->uEax = pLeaf->uEax;
735	pLegacy->uEbx = pLeaf->uEbx;
736	pLegacy->uEcx = pLeaf->uEcx;
737	pLegacy->uEdx = pLeaf->uEdx;
738	return true;
739	}
740	return false;
741	}
742	#endif /* IN_VBOX_CPU_REPORT */
743
744
745	/**
746	* Ensures that the CPUID leaf array can hold one more leaf.
747	*
748	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
749	* failure.
750	* @param pVM The cross context VM structure. If NULL, use
751	* the process heap, otherwise the VM's hyper heap.
752	* @param ppaLeaves Pointer to the variable holding the array pointer
753	* (input/output).
754	* @param cLeaves The current array size.
755	*
756	* @remarks This function will automatically update the R0 and RC pointers when
757	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
758	* be the corresponding VM's CPUID arrays (which is asserted).
759	*/
760	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
761	{
762	/*
763	* If pVM is not specified, we're on the regular heap and can waste a
764	* little space to speed things up.
765	*/
766	uint32_t cAllocated;
767	if (!pVM)
768	{
769	cAllocated = RT_ALIGN(cLeaves, 16);
770	if (cLeaves + 1 > cAllocated)
771	{
772	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
773	if (pvNew)
774	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
775	else
776	{
777	RTMemFree(*ppaLeaves);
778	*ppaLeaves = NULL;
779	}
780	}
781	}
782	/*
783	* Otherwise, we're on the hyper heap and are probably just inserting
784	* one or two leaves and should conserve space.
785	*/
786	else
787	{
788	#ifdef IN_VBOX_CPU_REPORT
789	AssertReleaseFailed();
790	#else
791	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
792	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
793
794	size_t cb = cLeaves * sizeof(**ppaLeaves);
795	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
796	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
797	if (RT_SUCCESS(rc))
798	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
799	else
800	{
801	*ppaLeaves = NULL;
802	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
803	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
804	}
805	#endif
806	}
807	return *ppaLeaves;
808	}
809
810
811	/**
812	* Append a CPUID leaf or sub-leaf.
813	*
814	* ASSUMES linear insertion order, so we'll won't need to do any searching or
815	* replace anything. Use cpumR3CpuIdInsert() for those cases.
816	*
817	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
818	* the caller need do no more work.
819	* @param ppaLeaves Pointer to the pointer to the array of sorted
820	* CPUID leaves and sub-leaves.
821	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
822	* @param uLeaf The leaf we're adding.
823	* @param uSubLeaf The sub-leaf number.
824	* @param fSubLeafMask The sub-leaf mask.
825	* @param uEax The EAX value.
826	* @param uEbx The EBX value.
827	* @param uEcx The ECX value.
828	* @param uEdx The EDX value.
829	* @param fFlags The flags.
830	*/
831	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
832	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
833	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
834	{
835	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
836	return VERR_NO_MEMORY;
837
838	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
839	Assert( *pcLeaves == 0
840	\|\| pNew[-1].uLeaf < uLeaf
841	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
842
843	pNew->uLeaf = uLeaf;
844	pNew->uSubLeaf = uSubLeaf;
845	pNew->fSubLeafMask = fSubLeafMask;
846	pNew->uEax = uEax;
847	pNew->uEbx = uEbx;
848	pNew->uEcx = uEcx;
849	pNew->uEdx = uEdx;
850	pNew->fFlags = fFlags;
851
852	*pcLeaves += 1;
853	return VINF_SUCCESS;
854	}
855
856
857	/**
858	* Checks that we've updated the CPUID leaves array correctly.
859	*
860	* This is a no-op in non-strict builds.
861	*
862	* @param paLeaves The leaves array.
863	* @param cLeaves The number of leaves.
864	*/
865	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
866	{
867	#ifdef VBOX_STRICT
868	for (uint32_t i = 1; i < cLeaves; i++)
869	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
870	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
871	else
872	{
873	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
874	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
875	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
876	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
877	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
878	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
879	}
880	#else
881	NOREF(paLeaves);
882	NOREF(cLeaves);
883	#endif
884	}
885
886
887	/**
888	* Inserts a CPU ID leaf, replacing any existing ones.
889	*
890	* When inserting a simple leaf where we already got a series of sub-leaves with
891	* the same leaf number (eax), the simple leaf will replace the whole series.
892	*
893	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
894	* host-context heap and has only been allocated/reallocated by the
895	* cpumR3CpuIdEnsureSpace function.
896	*
897	* @returns VBox status code.
898	* @param pVM The cross context VM structure. If NULL, use
899	* the process heap, otherwise the VM's hyper heap.
900	* @param ppaLeaves Pointer to the pointer to the array of sorted
901	* CPUID leaves and sub-leaves. Must be NULL if using
902	* the hyper heap.
903	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
904	* be NULL if using the hyper heap.
905	* @param pNewLeaf Pointer to the data of the new leaf we're about to
906	* insert.
907	*/
908	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
909	{
910	/*
911	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
912	*/
913	if (pVM)
914	{
915	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
916	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
917
918	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
919	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
920	}
921
922	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
923	uint32_t cLeaves = *pcLeaves;
924
925	/*
926	* Validate the new leaf a little.
927	*/
928	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
929	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
930	VERR_INVALID_FLAGS);
931	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
932	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
933	VERR_INVALID_PARAMETER);
934	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
935	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
936	VERR_INVALID_PARAMETER);
937	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
938	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
939	VERR_INVALID_PARAMETER);
940
941	/*
942	* Find insertion point. The lazy bird uses the same excuse as in
943	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
944	*/
945	uint32_t i;
946	if ( cLeaves > 0
947	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
948	{
949	/* Add at end. */
950	i = cLeaves;
951	}
952	else if ( cLeaves > 0
953	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
954	{
955	/* Either replacing the last leaf or dealing with sub-leaves. Spool
956	back to the first sub-leaf to pretend we did the linear search. */
957	i = cLeaves - 1;
958	while ( i > 0
959	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
960	i--;
961	}
962	else
963	{
964	/* Linear search from the start. */
965	i = 0;
966	while ( i < cLeaves
967	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
968	i++;
969	}
970	if ( i < cLeaves
971	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
972	{
973	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
974	{
975	/*
976	* The sub-leaf mask differs, replace all existing leaves with the
977	* same leaf number.
978	*/
979	uint32_t c = 1;
980	while ( i + c < cLeaves
981	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
982	c++;
983	if (c > 1 && i + c < cLeaves)
984	{
985	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
986	*pcLeaves = cLeaves -= c - 1;
987	}
988
989	paLeaves[i] = *pNewLeaf;
990	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
991	return VINF_SUCCESS;
992	}
993
994	/* Find sub-leaf insertion point. */
995	while ( i < cLeaves
996	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
997	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
998	i++;
999
1000	/*
1001	* If we've got an exactly matching leaf, replace it.
1002	*/
1003	if ( i < cLeaves
1004	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
1005	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
1006	{
1007	paLeaves[i] = *pNewLeaf;
1008	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1009	return VINF_SUCCESS;
1010	}
1011	}
1012
1013	/*
1014	* Adding a new leaf at 'i'.
1015	*/
1016	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
1017	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
1018	if (!paLeaves)
1019	return VERR_NO_MEMORY;
1020
1021	if (i < cLeaves)
1022	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
1023	*pcLeaves += 1;
1024	paLeaves[i] = *pNewLeaf;
1025
1026	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1027	return VINF_SUCCESS;
1028	}
1029
1030
1031	#ifndef IN_VBOX_CPU_REPORT
1032	/**
1033	* Removes a range of CPUID leaves.
1034	*
1035	* This will not reallocate the array.
1036	*
1037	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1038	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1039	* @param uFirst The first leaf.
1040	* @param uLast The last leaf.
1041	*/
1042	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1043	{
1044	uint32_t cLeaves = *pcLeaves;
1045
1046	Assert(uFirst <= uLast);
1047
1048	/*
1049	* Find the first one.
1050	*/
1051	uint32_t iFirst = 0;
1052	while ( iFirst < cLeaves
1053	&& paLeaves[iFirst].uLeaf < uFirst)
1054	iFirst++;
1055
1056	/*
1057	* Find the end (last + 1).
1058	*/
1059	uint32_t iEnd = iFirst;
1060	while ( iEnd < cLeaves
1061	&& paLeaves[iEnd].uLeaf <= uLast)
1062	iEnd++;
1063
1064	/*
1065	* Adjust the array if anything needs removing.
1066	*/
1067	if (iFirst < iEnd)
1068	{
1069	if (iEnd < cLeaves)
1070	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1071	*pcLeaves = cLeaves -= (iEnd - iFirst);
1072	}
1073
1074	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1075	}
1076	#endif /* IN_VBOX_CPU_REPORT */
1077
1078
1079	/**
1080	* Checks if ECX make a difference when reading a given CPUID leaf.
1081	*
1082	* @returns @c true if it does, @c false if it doesn't.
1083	* @param uLeaf The leaf we're reading.
1084	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1085	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1086	* final sub-leaf (for leaf 0xb only).
1087	*/
1088	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1089	{
1090	*pfFinalEcxUnchanged = false;
1091
1092	uint32_t auCur[4];
1093	uint32_t auPrev[4];
1094	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1095
1096	/* Look for sub-leaves. */
1097	uint32_t uSubLeaf = 1;
1098	for (;;)
1099	{
1100	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1101	if (memcmp(auCur, auPrev, sizeof(auCur)))
1102	break;
1103
1104	/* Advance / give up. */
1105	uSubLeaf++;
1106	if (uSubLeaf >= 64)
1107	{
1108	*pcSubLeaves = 1;
1109	return false;
1110	}
1111	}
1112
1113	/* Count sub-leaves. */
1114	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1115	uint32_t cRepeats = 0;
1116	uSubLeaf = 0;
1117	for (;;)
1118	{
1119	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1120
1121	/* Figuring out when to stop isn't entirely straight forward as we need
1122	to cover undocumented behavior up to a point and implementation shortcuts. */
1123
1124	/* 1. Look for more than 4 repeating value sets. */
1125	if ( auCur[0] == auPrev[0]
1126	&& auCur[1] == auPrev[1]
1127	&& ( auCur[2] == auPrev[2]
1128	\|\| ( auCur[2] == uSubLeaf
1129	&& auPrev[2] == uSubLeaf - 1) )
1130	&& auCur[3] == auPrev[3])
1131	{
1132	if ( uLeaf != 0xd
1133	\|\| uSubLeaf >= 64
1134	\|\| ( auCur[0] == 0
1135	&& auCur[1] == 0
1136	&& auCur[2] == 0
1137	&& auCur[3] == 0
1138	&& auPrev[2] == 0) )
1139	cRepeats++;
1140	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1141	break;
1142	}
1143	else
1144	cRepeats = 0;
1145
1146	/* 2. Look for zero values. */
1147	if ( auCur[0] == 0
1148	&& auCur[1] == 0
1149	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1150	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1151	&& uSubLeaf >= cMinLeaves)
1152	{
1153	cRepeats = 0;
1154	break;
1155	}
1156
1157	/* 3. Leaf 0xb level type 0 check. */
1158	if ( uLeaf == 0xb
1159	&& (auCur[2] & 0xff00) == 0
1160	&& (auPrev[2] & 0xff00) == 0)
1161	{
1162	cRepeats = 0;
1163	break;
1164	}
1165
1166	/* 99. Give up. */
1167	if (uSubLeaf >= 128)
1168	{
1169	#ifndef IN_VBOX_CPU_REPORT
1170	/* Ok, limit it according to the documentation if possible just to
1171	avoid annoying users with these detection issues. */
1172	uint32_t cDocLimit = UINT32_MAX;
1173	if (uLeaf == 0x4)
1174	cDocLimit = 4;
1175	else if (uLeaf == 0x7)
1176	cDocLimit = 1;
1177	else if (uLeaf == 0xd)
1178	cDocLimit = 63;
1179	else if (uLeaf == 0xf)
1180	cDocLimit = 2;
1181	if (cDocLimit != UINT32_MAX)
1182	{
1183	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1184	*pcSubLeaves = cDocLimit + 3;
1185	return true;
1186	}
1187	#endif
1188	*pcSubLeaves = UINT32_MAX;
1189	return true;
1190	}
1191
1192	/* Advance. */
1193	uSubLeaf++;
1194	memcpy(auPrev, auCur, sizeof(auCur));
1195	}
1196
1197	/* Standard exit. */
1198	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1199	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1200	if (*pcSubLeaves == 0)
1201	*pcSubLeaves = 1;
1202	return true;
1203	}
1204
1205
1206	/**
1207	* Gets a CPU ID leaf.
1208	*
1209	* @returns VBox status code.
1210	* @param pVM The cross context VM structure.
1211	* @param pLeaf Where to store the found leaf.
1212	* @param uLeaf The leaf to locate.
1213	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1214	*/
1215	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1216	{
1217	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1218	uLeaf, uSubLeaf);
1219	if (pcLeaf)
1220	{
1221	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1222	return VINF_SUCCESS;
1223	}
1224
1225	return VERR_NOT_FOUND;
1226	}
1227
1228
1229	/**
1230	* Inserts a CPU ID leaf, replacing any existing ones.
1231	*
1232	* @returns VBox status code.
1233	* @param pVM The cross context VM structure.
1234	* @param pNewLeaf Pointer to the leaf being inserted.
1235	*/
1236	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1237	{
1238	/*
1239	* Validate parameters.
1240	*/
1241	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1242	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1243
1244	/*
1245	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1246	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1247	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1248	*/
1249	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1250	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1251	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1252	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1253	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1254	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1255	{
1256	return VERR_NOT_SUPPORTED;
1257	}
1258
1259	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1260	}
1261
1262	/**
1263	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1264	*
1265	* @returns VBox status code.
1266	* @param ppaLeaves Where to return the array pointer on success.
1267	* Use RTMemFree to release.
1268	* @param pcLeaves Where to return the size of the array on
1269	* success.
1270	*/
1271	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1272	{
1273	*ppaLeaves = NULL;
1274	*pcLeaves = 0;
1275
1276	/*
1277	* Try out various candidates. This must be sorted!
1278	*/
1279	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1280	{
1281	{ UINT32_C(0x00000000), false },
1282	{ UINT32_C(0x10000000), false },
1283	{ UINT32_C(0x20000000), false },
1284	{ UINT32_C(0x30000000), false },
1285	{ UINT32_C(0x40000000), false },
1286	{ UINT32_C(0x50000000), false },
1287	{ UINT32_C(0x60000000), false },
1288	{ UINT32_C(0x70000000), false },
1289	{ UINT32_C(0x80000000), false },
1290	{ UINT32_C(0x80860000), false },
1291	{ UINT32_C(0x8ffffffe), true },
1292	{ UINT32_C(0x8fffffff), true },
1293	{ UINT32_C(0x90000000), false },
1294	{ UINT32_C(0xa0000000), false },
1295	{ UINT32_C(0xb0000000), false },
1296	{ UINT32_C(0xc0000000), false },
1297	{ UINT32_C(0xd0000000), false },
1298	{ UINT32_C(0xe0000000), false },
1299	{ UINT32_C(0xf0000000), false },
1300	};
1301
1302	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1303	{
1304	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1305	uint32_t uEax, uEbx, uEcx, uEdx;
1306	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1307
1308	/*
1309	* Does EAX look like a typical leaf count value?
1310	*/
1311	if ( uEax > uLeaf
1312	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1313	{
1314	/* Yes, dump them. */
1315	uint32_t cLeaves = uEax - uLeaf + 1;
1316	while (cLeaves-- > 0)
1317	{
1318	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1319
1320	uint32_t fFlags = 0;
1321
1322	/* There are currently three known leaves containing an APIC ID
1323	that needs EMT specific attention */
1324	if (uLeaf == 1)
1325	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1326	else if (uLeaf == 0xb && uEcx != 0)
1327	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1328	else if ( uLeaf == UINT32_C(0x8000001e)
1329	&& ( uEax
1330	\|\| uEbx
1331	\|\| uEdx
1332	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1333	\|\| ASMIsHygonCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1334	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1335
1336	/* The APIC bit is per-VCpu and needs flagging. */
1337	if (uLeaf == 1)
1338	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1339	else if ( uLeaf == UINT32_C(0x80000001)
1340	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1341	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1342	\|\| ASMIsHygonCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1343	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1344
1345	/* Check three times here to reduce the chance of CPU migration
1346	resulting in false positives with things like the APIC ID. */
1347	uint32_t cSubLeaves;
1348	bool fFinalEcxUnchanged;
1349	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1350	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1351	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1352	{
1353	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1354	{
1355	/* This shouldn't happen. But in case it does, file all
1356	relevant details in the release log. */
1357	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1358	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1359	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1360	{
1361	uint32_t auTmp[4];
1362	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1363	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1364	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1365	}
1366	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1367	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1368	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1369	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1370	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1371	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1372	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1373	}
1374
1375	if (fFinalEcxUnchanged)
1376	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1377
1378	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1379	{
1380	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1381	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1382	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1383	if (RT_FAILURE(rc))
1384	return rc;
1385	}
1386	}
1387	else
1388	{
1389	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1390	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1391	if (RT_FAILURE(rc))
1392	return rc;
1393	}
1394
1395	/* next */
1396	uLeaf++;
1397	}
1398	}
1399	/*
1400	* Special CPUIDs needs special handling as they don't follow the
1401	* leaf count principle used above.
1402	*/
1403	else if (s_aCandidates[iOuter].fSpecial)
1404	{
1405	bool fKeep = false;
1406	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1407	fKeep = true;
1408	else if ( uLeaf == 0x8fffffff
1409	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1410	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1411	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1412	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1413	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1414	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1415	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1416	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1417	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1418	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1419	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1420	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1421	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1422	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1423	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1424	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1425	fKeep = true;
1426	if (fKeep)
1427	{
1428	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1429	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1430	if (RT_FAILURE(rc))
1431	return rc;
1432	}
1433	}
1434	}
1435
1436	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1437	return VINF_SUCCESS;
1438	}
1439
1440
1441	/**
1442	* Determines the method the CPU uses to handle unknown CPUID leaves.
1443	*
1444	* @returns VBox status code.
1445	* @param penmUnknownMethod Where to return the method.
1446	* @param pDefUnknown Where to return default unknown values. This
1447	* will be set, even if the resulting method
1448	* doesn't actually needs it.
1449	*/
1450	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1451	{
1452	uint32_t uLastStd = ASMCpuId_EAX(0);
1453	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1454	if (!ASMIsValidExtRange(uLastExt))
1455	uLastExt = 0x80000000;
1456
1457	uint32_t auChecks[] =
1458	{
1459	uLastStd + 1,
1460	uLastStd + 5,
1461	uLastStd + 8,
1462	uLastStd + 32,
1463	uLastStd + 251,
1464	uLastExt + 1,
1465	uLastExt + 8,
1466	uLastExt + 15,
1467	uLastExt + 63,
1468	uLastExt + 255,
1469	0x7fbbffcc,
1470	0x833f7872,
1471	0xefff2353,
1472	0x35779456,
1473	0x1ef6d33e,
1474	};
1475
1476	static const uint32_t s_auValues[] =
1477	{
1478	0xa95d2156,
1479	0x00000001,
1480	0x00000002,
1481	0x00000008,
1482	0x00000000,
1483	0x55773399,
1484	0x93401769,
1485	0x12039587,
1486	};
1487
1488	/*
1489	* Simple method, all zeros.
1490	*/
1491	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1492	pDefUnknown->uEax = 0;
1493	pDefUnknown->uEbx = 0;
1494	pDefUnknown->uEcx = 0;
1495	pDefUnknown->uEdx = 0;
1496
1497	/*
1498	* Intel has been observed returning the last standard leaf.
1499	*/
1500	uint32_t auLast[4];
1501	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1502
1503	uint32_t cChecks = RT_ELEMENTS(auChecks);
1504	while (cChecks > 0)
1505	{
1506	uint32_t auCur[4];
1507	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1508	if (memcmp(auCur, auLast, sizeof(auCur)))
1509	break;
1510	cChecks--;
1511	}
1512	if (cChecks == 0)
1513	{
1514	/* Now, what happens when the input changes? Esp. ECX. */
1515	uint32_t cTotal = 0;
1516	uint32_t cSame = 0;
1517	uint32_t cLastWithEcx = 0;
1518	uint32_t cNeither = 0;
1519	uint32_t cValues = RT_ELEMENTS(s_auValues);
1520	while (cValues > 0)
1521	{
1522	uint32_t uValue = s_auValues[cValues - 1];
1523	uint32_t auLastWithEcx[4];
1524	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1525	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1526
1527	cChecks = RT_ELEMENTS(auChecks);
1528	while (cChecks > 0)
1529	{
1530	uint32_t auCur[4];
1531	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1532	if (!memcmp(auCur, auLast, sizeof(auCur)))
1533	{
1534	cSame++;
1535	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1536	cLastWithEcx++;
1537	}
1538	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1539	cLastWithEcx++;
1540	else
1541	cNeither++;
1542	cTotal++;
1543	cChecks--;
1544	}
1545	cValues--;
1546	}
1547
1548	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1549	if (cSame == cTotal)
1550	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1551	else if (cLastWithEcx == cTotal)
1552	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1553	else
1554	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1555	pDefUnknown->uEax = auLast[0];
1556	pDefUnknown->uEbx = auLast[1];
1557	pDefUnknown->uEcx = auLast[2];
1558	pDefUnknown->uEdx = auLast[3];
1559	return VINF_SUCCESS;
1560	}
1561
1562	/*
1563	* Unchanged register values?
1564	*/
1565	cChecks = RT_ELEMENTS(auChecks);
1566	while (cChecks > 0)
1567	{
1568	uint32_t const uLeaf = auChecks[cChecks - 1];
1569	uint32_t cValues = RT_ELEMENTS(s_auValues);
1570	while (cValues > 0)
1571	{
1572	uint32_t uValue = s_auValues[cValues - 1];
1573	uint32_t auCur[4];
1574	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1575	if ( auCur[0] != uLeaf
1576	\|\| auCur[1] != uValue
1577	\|\| auCur[2] != uValue
1578	\|\| auCur[3] != uValue)
1579	break;
1580	cValues--;
1581	}
1582	if (cValues != 0)
1583	break;
1584	cChecks--;
1585	}
1586	if (cChecks == 0)
1587	{
1588	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1589	return VINF_SUCCESS;
1590	}
1591
1592	/*
1593	* Just go with the simple method.
1594	*/
1595	return VINF_SUCCESS;
1596	}
1597
1598
1599	/**
1600	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1601	*
1602	* @returns Read only name string.
1603	* @param enmUnknownMethod The method to translate.
1604	*/
1605	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1606	{
1607	switch (enmUnknownMethod)
1608	{
1609	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1610	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1611	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1612	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1613
1614	case CPUMUNKNOWNCPUID_INVALID:
1615	case CPUMUNKNOWNCPUID_END:
1616	case CPUMUNKNOWNCPUID_32BIT_HACK:
1617	break;
1618	}
1619	return "Invalid-unknown-CPUID-method";
1620	}
1621
1622
1623	/**
1624	* Detect the CPU vendor give n the
1625	*
1626	* @returns The vendor.
1627	* @param uEAX EAX from CPUID(0).
1628	* @param uEBX EBX from CPUID(0).
1629	* @param uECX ECX from CPUID(0).
1630	* @param uEDX EDX from CPUID(0).
1631	*/
1632	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1633	{
1634	if (ASMIsValidStdRange(uEAX))
1635	{
1636	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1637	return CPUMCPUVENDOR_AMD;
1638
1639	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1640	return CPUMCPUVENDOR_INTEL;
1641
1642	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1643	return CPUMCPUVENDOR_VIA;
1644
1645	if (ASMIsShanghaiCpuEx(uEBX, uECX, uEDX))
1646	return CPUMCPUVENDOR_SHANGHAI;
1647
1648	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1649	&& uECX == UINT32_C(0x64616574)
1650	&& uEDX == UINT32_C(0x736E4978))
1651	return CPUMCPUVENDOR_CYRIX;
1652
1653	if (ASMIsHygonCpuEx(uEBX, uECX, uEDX))
1654	return CPUMCPUVENDOR_HYGON;
1655
1656	/* "Geode by NSC", example: family 5, model 9. */
1657
1658	/** @todo detect the other buggers... */
1659	}
1660
1661	return CPUMCPUVENDOR_UNKNOWN;
1662	}
1663
1664
1665	/**
1666	* Translates a CPU vendor enum value into the corresponding string constant.
1667	*
1668	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1669	* value name. This can be useful when generating code.
1670	*
1671	* @returns Read only name string.
1672	* @param enmVendor The CPU vendor value.
1673	*/
1674	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1675	{
1676	switch (enmVendor)
1677	{
1678	case CPUMCPUVENDOR_INTEL: return "INTEL";
1679	case CPUMCPUVENDOR_AMD: return "AMD";
1680	case CPUMCPUVENDOR_VIA: return "VIA";
1681	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1682	case CPUMCPUVENDOR_SHANGHAI: return "SHANGHAI";
1683	case CPUMCPUVENDOR_HYGON: return "HYGON";
1684	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1685
1686	case CPUMCPUVENDOR_INVALID:
1687	case CPUMCPUVENDOR_32BIT_HACK:
1688	break;
1689	}
1690	return "Invalid-cpu-vendor";
1691	}
1692
1693
1694	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1695	{
1696	/* Could do binary search, doing linear now because I'm lazy. */
1697	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1698	while (cLeaves-- > 0)
1699	{
1700	if (pLeaf->uLeaf == uLeaf)
1701	return pLeaf;
1702	pLeaf++;
1703	}
1704	return NULL;
1705	}
1706
1707
1708	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1709	{
1710	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1711	if ( !pLeaf
1712	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1713	return pLeaf;
1714
1715	/* Linear sub-leaf search. Lazy as usual. */
1716	cLeaves -= pLeaf - paLeaves;
1717	while ( cLeaves-- > 0
1718	&& pLeaf->uLeaf == uLeaf)
1719	{
1720	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1721	return pLeaf;
1722	pLeaf++;
1723	}
1724
1725	return NULL;
1726	}
1727
1728
1729	static void cpumR3ExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, PCPUMFEATURES pFeatures)
1730	{
1731	Assert(pVmxMsrs);
1732	Assert(pFeatures);
1733	Assert(pFeatures->fVmx);
1734
1735	/* Basic information. */
1736	{
1737	uint64_t const u64Basic = pVmxMsrs->u64Basic;
1738	pFeatures->fVmxInsOutInfo = RT_BF_GET(u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1739	}
1740
1741	/* Pin-based VM-execution controls. */
1742	{
1743	uint32_t const fPinCtls = pVmxMsrs->PinCtls.n.allowed1;
1744	pFeatures->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1745	pFeatures->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1746	pFeatures->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1747	pFeatures->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1748	pFeatures->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1749	}
1750
1751	/* Processor-based VM-execution controls. */
1752	{
1753	uint32_t const fProcCtls = pVmxMsrs->ProcCtls.n.allowed1;
1754	pFeatures->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1755	pFeatures->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1756	pFeatures->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1757	pFeatures->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1758	pFeatures->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1759	pFeatures->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1760	pFeatures->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1761	pFeatures->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1762	pFeatures->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1763	pFeatures->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1764	pFeatures->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1765	pFeatures->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1766	pFeatures->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1767	pFeatures->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1768	pFeatures->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1769	pFeatures->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1770	pFeatures->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1771	pFeatures->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1772	pFeatures->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1773	pFeatures->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1774	pFeatures->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1775	}
1776
1777	/* Secondary processor-based VM-execution controls. */
1778	{
1779	uint32_t const fProcCtls2 = pFeatures->fVmxSecondaryExecCtls ? pVmxMsrs->ProcCtls2.n.allowed1 : 0;
1780	pFeatures->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1781	pFeatures->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1782	pFeatures->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1783	pFeatures->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1784	pFeatures->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1785	pFeatures->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1786	pFeatures->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1787	pFeatures->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1788	pFeatures->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1789	pFeatures->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1790	pFeatures->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1791	pFeatures->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1792	pFeatures->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1793	pFeatures->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1794	pFeatures->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1795	pFeatures->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1796	pFeatures->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1797	pFeatures->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_VE);
1798	pFeatures->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1799	pFeatures->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1800	}
1801
1802	/* VM-exit controls. */
1803	{
1804	uint32_t const fExitCtls = pVmxMsrs->ExitCtls.n.allowed1;
1805	pFeatures->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1806	pFeatures->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1807	pFeatures->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1808	pFeatures->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1809	pFeatures->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1810	pFeatures->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1811	pFeatures->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1812	pFeatures->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1813	}
1814
1815	/* VM-entry controls. */
1816	{
1817	uint32_t const fEntryCtls = pVmxMsrs->EntryCtls.n.allowed1;
1818	pFeatures->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1819	pFeatures->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1820	pFeatures->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1821	pFeatures->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1822	}
1823
1824	/* Miscellaneous data. */
1825	{
1826	uint32_t const fMiscData = pVmxMsrs->u64Misc;
1827	pFeatures->fVmxExitSaveEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_SAVE_EFER_LMA);
1828	pFeatures->fVmxIntelPt = RT_BOOL(fMiscData & VMX_MISC_INTEL_PT);
1829	pFeatures->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1830	pFeatures->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1831	}
1832	}
1833
1834
1835	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures)
1836	{
1837	Assert(pMsrs);
1838	RT_ZERO(*pFeatures);
1839	if (cLeaves >= 2)
1840	{
1841	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1842	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1843	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1844	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1845	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1846	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1847
1848	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1849	pStd0Leaf->uEbx,
1850	pStd0Leaf->uEcx,
1851	pStd0Leaf->uEdx);
1852	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1853	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1854	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1855	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1856	pFeatures->uFamily,
1857	pFeatures->uModel,
1858	pFeatures->uStepping);
1859
1860	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1861	if (pExtLeaf8)
1862	{
1863	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1864	pFeatures->cMaxLinearAddrWidth = (pExtLeaf8->uEax >> 8) & 0xff;
1865	}
1866	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1867	{
1868	pFeatures->cMaxPhysAddrWidth = 36;
1869	pFeatures->cMaxLinearAddrWidth = 36;
1870	}
1871	else
1872	{
1873	pFeatures->cMaxPhysAddrWidth = 32;
1874	pFeatures->cMaxLinearAddrWidth = 32;
1875	}
1876
1877	/* Standard features. */
1878	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1879	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1880	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1881	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1882	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1883	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1884	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1885	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1886	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1887	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1888	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1889	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1890	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1891	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1892	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1893	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1894	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1895	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1896	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1897	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1898	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1899	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1900	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1901	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1902	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1903	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1904	if (pFeatures->fVmx)
1905	cpumR3ExplodeVmxFeatures(&pMsrs->hwvirt.vmx, pFeatures);
1906
1907	/* Structured extended features. */
1908	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1909	if (pSxfLeaf0)
1910	{
1911	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1912	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1913	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1914	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1915	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1916
1917	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1918	pFeatures->fIbrs = pFeatures->fIbpb;
1919	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1920	pFeatures->fFlushCmd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
1921	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1922	pFeatures->fMdsClear = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR);
1923	}
1924
1925	/* MWAIT/MONITOR leaf. */
1926	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1927	if (pMWaitLeaf)
1928	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1929	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1930
1931	/* Extended features. */
1932	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1933	if (pExtLeaf)
1934	{
1935	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1936	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1937	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1938	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1939	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1940	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1941	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1942	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1943	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1944	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1945	}
1946
1947	/* VMX (VMXON, VMCS region and related data structures) physical address width (depends on long-mode). */
1948	pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
1949
1950	if ( pExtLeaf
1951	&& ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1952	\|\| pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON))
1953	{
1954	/* AMD features. */
1955	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1956	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1957	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1958	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1959	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1960	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1961	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1962	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1963	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1964	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1965	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1966	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1967	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1968	if (pFeatures->fSvm)
1969	{
1970	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1971	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1972	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1973	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1974	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1975	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1976	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1977	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1978	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1979	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1980	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1981	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1982	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1983	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1984	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1985	pFeatures->fSvmGmet = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_GMET);
1986	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1987	}
1988	}
1989
1990	/*
1991	* Quirks.
1992	*/
1993	pFeatures->fLeakyFxSR = pExtLeaf
1994	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1995	&& ( ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1996	&& pFeatures->uFamily >= 6 /* K7 and up */)
1997	\|\| pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON);
1998
1999	/*
2000	* Max extended (/FPU) state.
2001	*/
2002	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
2003	if (pFeatures->fXSaveRstor)
2004	{
2005	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
2006	if (pXStateLeaf0)
2007	{
2008	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
2009	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
2010	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
2011	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
2012	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
2013	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
2014	{
2015	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
2016
2017	/* (paranoia:) */
2018	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
2019	if ( pXStateLeaf1
2020	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
2021	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
2022	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
2023	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
2024	}
2025	else
2026	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
2027	pFeatures->fXSaveRstor = 0);
2028	}
2029	else
2030	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
2031	pFeatures->fXSaveRstor = 0);
2032	}
2033	}
2034	else
2035	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
2036	return VINF_SUCCESS;
2037	}
2038
2039
2040	/*
2041	*
2042	* Init related code.
2043	* Init related code.
2044	* Init related code.
2045	*
2046	*
2047	*/
2048	#ifndef IN_VBOX_CPU_REPORT
2049
2050
2051	/**
2052	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
2053	*
2054	* This ignores the fSubLeafMask.
2055	*
2056	* @returns Pointer to the matching leaf, or NULL if not found.
2057	* @param pCpum The CPUM instance data.
2058	* @param uLeaf The leaf to locate.
2059	* @param uSubLeaf The subleaf to locate.
2060	*/
2061	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
2062	{
2063	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
2064	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
2065	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
2066	if (iEnd)
2067	{
2068	uint32_t iBegin = 0;
2069	for (;;)
2070	{
2071	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
2072	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
2073	if (uNeedle < uCur)
2074	{
2075	if (i > iBegin)
2076	iEnd = i;
2077	else
2078	break;
2079	}
2080	else if (uNeedle > uCur)
2081	{
2082	if (i + 1 < iEnd)
2083	iBegin = i + 1;
2084	else
2085	break;
2086	}
2087	else
2088	return &paLeaves[i];
2089	}
2090	}
2091	return NULL;
2092	}
2093
2094
2095	/**
2096	* Loads MSR range overrides.
2097	*
2098	* This must be called before the MSR ranges are moved from the normal heap to
2099	* the hyper heap!
2100	*
2101	* @returns VBox status code (VMSetError called).
2102	* @param pVM The cross context VM structure.
2103	* @param pMsrNode The CFGM node with the MSR overrides.
2104	*/
2105	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
2106	{
2107	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2108	{
2109	/*
2110	* Assemble a valid MSR range.
2111	*/
2112	CPUMMSRRANGE MsrRange;
2113	MsrRange.offCpumCpu = 0;
2114	MsrRange.fReserved = 0;
2115
2116	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
2117	if (RT_FAILURE(rc))
2118	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
2119
2120	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
2121	if (RT_FAILURE(rc))
2122	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
2123	MsrRange.szName, rc);
2124
2125	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
2126	if (RT_FAILURE(rc))
2127	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
2128	MsrRange.szName, rc);
2129
2130	char szType[32];
2131	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
2132	if (RT_FAILURE(rc))
2133	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
2134	MsrRange.szName, rc);
2135	if (!RTStrICmp(szType, "FixedValue"))
2136	{
2137	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
2138	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
2139
2140	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
2141	if (RT_FAILURE(rc))
2142	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
2143	MsrRange.szName, rc);
2144
2145	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
2146	if (RT_FAILURE(rc))
2147	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
2148	MsrRange.szName, rc);
2149
2150	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
2151	if (RT_FAILURE(rc))
2152	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
2153	MsrRange.szName, rc);
2154	}
2155	else
2156	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
2157	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
2158
2159	/*
2160	* Insert the range into the table (replaces/splits/shrinks existing
2161	* MSR ranges).
2162	*/
2163	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
2164	&MsrRange);
2165	if (RT_FAILURE(rc))
2166	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
2167	}
2168
2169	return VINF_SUCCESS;
2170	}
2171
2172
2173	/**
2174	* Loads CPUID leaf overrides.
2175	*
2176	* This must be called before the CPUID leaves are moved from the normal
2177	* heap to the hyper heap!
2178	*
2179	* @returns VBox status code (VMSetError called).
2180	* @param pVM The cross context VM structure.
2181	* @param pParentNode The CFGM node with the CPUID leaves.
2182	* @param pszLabel How to label the overrides we're loading.
2183	*/
2184	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2185	{
2186	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2187	{
2188	/*
2189	* Get the leaf and subleaf numbers.
2190	*/
2191	char szName[128];
2192	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2193	if (RT_FAILURE(rc))
2194	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2195
2196	/* The leaf number is either specified directly or thru the node name. */
2197	uint32_t uLeaf;
2198	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2199	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2200	{
2201	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2202	if (rc != VINF_SUCCESS)
2203	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2204	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2205	}
2206	else if (RT_FAILURE(rc))
2207	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2208	pszLabel, szName, rc);
2209
2210	uint32_t uSubLeaf;
2211	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2212	if (RT_FAILURE(rc))
2213	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2214	pszLabel, szName, rc);
2215
2216	uint32_t fSubLeafMask;
2217	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2218	if (RT_FAILURE(rc))
2219	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2220	pszLabel, szName, rc);
2221
2222	/*
2223	* Look up the specified leaf, since the output register values
2224	* defaults to any existing values. This allows overriding a single
2225	* register, without needing to know the other values.
2226	*/
2227	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2228	CPUMCPUIDLEAF Leaf;
2229	if (pLeaf)
2230	Leaf = *pLeaf;
2231	else
2232	RT_ZERO(Leaf);
2233	Leaf.uLeaf = uLeaf;
2234	Leaf.uSubLeaf = uSubLeaf;
2235	Leaf.fSubLeafMask = fSubLeafMask;
2236
2237	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2238	if (RT_FAILURE(rc))
2239	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2240	pszLabel, szName, rc);
2241	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2242	if (RT_FAILURE(rc))
2243	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2244	pszLabel, szName, rc);
2245	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2246	if (RT_FAILURE(rc))
2247	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2248	pszLabel, szName, rc);
2249	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2250	if (RT_FAILURE(rc))
2251	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2252	pszLabel, szName, rc);
2253
2254	/*
2255	* Insert the leaf into the table (replaces existing ones).
2256	*/
2257	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2258	&Leaf);
2259	if (RT_FAILURE(rc))
2260	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2261	}
2262
2263	return VINF_SUCCESS;
2264	}
2265
2266
2267
2268	/**
2269	* Fetches overrides for a CPUID leaf.
2270	*
2271	* @returns VBox status code.
2272	* @param pLeaf The leaf to load the overrides into.
2273	* @param pCfgNode The CFGM node containing the overrides
2274	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2275	* @param iLeaf The CPUID leaf number.
2276	*/
2277	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2278	{
2279	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2280	if (pLeafNode)
2281	{
2282	uint32_t u32;
2283	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2284	if (RT_SUCCESS(rc))
2285	pLeaf->uEax = u32;
2286	else
2287	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2288
2289	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2290	if (RT_SUCCESS(rc))
2291	pLeaf->uEbx = u32;
2292	else
2293	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2294
2295	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2296	if (RT_SUCCESS(rc))
2297	pLeaf->uEcx = u32;
2298	else
2299	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2300
2301	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2302	if (RT_SUCCESS(rc))
2303	pLeaf->uEdx = u32;
2304	else
2305	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2306
2307	}
2308	return VINF_SUCCESS;
2309	}
2310
2311
2312	/**
2313	* Load the overrides for a set of CPUID leaves.
2314	*
2315	* @returns VBox status code.
2316	* @param paLeaves The leaf array.
2317	* @param cLeaves The number of leaves.
2318	* @param uStart The start leaf number.
2319	* @param pCfgNode The CFGM node containing the overrides
2320	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2321	*/
2322	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2323	{
2324	for (uint32_t i = 0; i < cLeaves; i++)
2325	{
2326	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2327	if (RT_FAILURE(rc))
2328	return rc;
2329	}
2330
2331	return VINF_SUCCESS;
2332	}
2333
2334
2335	/**
2336	* Installs the CPUID leaves and explods the data into structures like
2337	* GuestFeatures and CPUMCTX::aoffXState.
2338	*
2339	* @returns VBox status code.
2340	* @param pVM The cross context VM structure.
2341	* @param pCpum The CPUM part of @a VM.
2342	* @param paLeaves The leaves. These will be copied (but not freed).
2343	* @param cLeaves The number of leaves.
2344	* @param pMsrs The MSRs.
2345	*/
2346	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
2347	{
2348	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2349
2350	/*
2351	* Install the CPUID information.
2352	*/
2353	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2354	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2355
2356	AssertLogRelRCReturn(rc, rc);
2357	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2358	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2359	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2360
2361	/*
2362	* Update the default CPUID leaf if necessary.
2363	*/
2364	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2365	{
2366	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2367	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2368	{
2369	/* We don't use CPUID(0).eax here because of the NT hack that only
2370	changes that value without actually removing any leaves. */
2371	uint32_t i = 0;
2372	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2373	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2374	{
2375	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2376	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2377	i++;
2378	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2379	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2380	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2381	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2382	}
2383	break;
2384	}
2385	default:
2386	break;
2387	}
2388
2389	/*
2390	* Explode the guest CPU features.
2391	*/
2392	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
2393	&pCpum->GuestFeatures);
2394	AssertLogRelRCReturn(rc, rc);
2395
2396	/*
2397	* Adjust the scalable bus frequency according to the CPUID information
2398	* we're now using.
2399	*/
2400	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2401	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2402	? UINT64_C(100000000) /* 100MHz */
2403	: UINT64_C(133333333); /* 133MHz */
2404
2405	/*
2406	* Populate the legacy arrays. Currently used for everything, later only
2407	* for patch manager.
2408	*/
2409	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2410	{
2411	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2412	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2413	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2414	};
2415	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2416	{
2417	uint32_t cLeft = aOldRanges[i].cCpuIds;
2418	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2419	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2420	while (cLeft-- > 0)
2421	{
2422	uLeaf--;
2423	pLegacyLeaf--;
2424
2425	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2426	if (pLeaf)
2427	{
2428	pLegacyLeaf->uEax = pLeaf->uEax;
2429	pLegacyLeaf->uEbx = pLeaf->uEbx;
2430	pLegacyLeaf->uEcx = pLeaf->uEcx;
2431	pLegacyLeaf->uEdx = pLeaf->uEdx;
2432	}
2433	else
2434	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2435	}
2436	}
2437
2438	/*
2439	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2440	*/
2441	PVMCPU pVCpu0 = pVM->apCpusR3[0];
2442	memset(&pVCpu0->cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2443	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2444	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2445	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2446	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2447	{
2448	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2449	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2450	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2451	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2452	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2453	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2454	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2455	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2456	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2457	pCpum->GuestFeatures.cbMaxExtendedState),
2458	VERR_CPUM_IPE_1);
2459	pVCpu0->cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2460	}
2461
2462	/* Copy the CPU #0 data to the other CPUs. */
2463	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
2464	{
2465	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2466	memcpy(&pVCpu->cpum.s.Guest.aoffXState[0], &pVCpu0->cpum.s.Guest.aoffXState[0], sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2467	}
2468
2469	return VINF_SUCCESS;
2470	}
2471
2472
2473	/** @name Instruction Set Extension Options
2474	* @{ */
2475	/** Configuration option type (extended boolean, really). */
2476	typedef uint8_t CPUMISAEXTCFG;
2477	/** Always disable the extension. */
2478	#define CPUMISAEXTCFG_DISABLED false
2479	/** Enable the extension if it's supported by the host CPU. */
2480	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2481	/** Enable the extension if it's supported by the host CPU, but don't let
2482	* the portable CPUID feature disable it. */
2483	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2484	/** Always enable the extension. */
2485	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2486	/** @} */
2487
2488	/**
2489	* CPUID Configuration (from CFGM).
2490	*
2491	* @remarks The members aren't document since we would only be duplicating the
2492	* \@cfgm entries in cpumR3CpuIdReadConfig.
2493	*/
2494	typedef struct CPUMCPUIDCONFIG
2495	{
2496	bool fNt4LeafLimit;
2497	bool fInvariantTsc;
2498	bool fForceVme;
2499	bool fNestedHWVirt;
2500
2501	CPUMISAEXTCFG enmCmpXchg16b;
2502	CPUMISAEXTCFG enmMonitor;
2503	CPUMISAEXTCFG enmMWaitExtensions;
2504	CPUMISAEXTCFG enmSse41;
2505	CPUMISAEXTCFG enmSse42;
2506	CPUMISAEXTCFG enmAvx;
2507	CPUMISAEXTCFG enmAvx2;
2508	CPUMISAEXTCFG enmXSave;
2509	CPUMISAEXTCFG enmAesNi;
2510	CPUMISAEXTCFG enmPClMul;
2511	CPUMISAEXTCFG enmPopCnt;
2512	CPUMISAEXTCFG enmMovBe;
2513	CPUMISAEXTCFG enmRdRand;
2514	CPUMISAEXTCFG enmRdSeed;
2515	CPUMISAEXTCFG enmCLFlushOpt;
2516	CPUMISAEXTCFG enmFsGsBase;
2517	CPUMISAEXTCFG enmPcid;
2518	CPUMISAEXTCFG enmInvpcid;
2519	CPUMISAEXTCFG enmFlushCmdMsr;
2520	CPUMISAEXTCFG enmMdsClear;
2521	CPUMISAEXTCFG enmArchCapMsr;
2522
2523	CPUMISAEXTCFG enmAbm;
2524	CPUMISAEXTCFG enmSse4A;
2525	CPUMISAEXTCFG enmMisAlnSse;
2526	CPUMISAEXTCFG enm3dNowPrf;
2527	CPUMISAEXTCFG enmAmdExtMmx;
2528
2529	uint32_t uMaxStdLeaf;
2530	uint32_t uMaxExtLeaf;
2531	uint32_t uMaxCentaurLeaf;
2532	uint32_t uMaxIntelFamilyModelStep;
2533	char szCpuName[128];
2534	} CPUMCPUIDCONFIG;
2535	/** Pointer to CPUID config (from CFGM). */
2536	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2537
2538
2539	/**
2540	* Mini CPU selection support for making Mac OS X happy.
2541	*
2542	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2543	*
2544	* @param pCpum The CPUM instance data.
2545	* @param pConfig The CPUID configuration we've read from CFGM.
2546	*/
2547	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2548	{
2549	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2550	{
2551	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2552	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2553	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2554	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2555	0);
2556	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2557	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2558	{
2559	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2560	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2561	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2562	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2563	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2564	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2565	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2566	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2567	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2568	pStdFeatureLeaf->uEax = uNew;
2569	}
2570	}
2571	}
2572
2573
2574
2575	/**
2576	* Limit it the number of entries, zapping the remainder.
2577	*
2578	* The limits are masking off stuff about power saving and similar, this
2579	* is perhaps a bit crudely done as there is probably some relatively harmless
2580	* info too in these leaves (like words about having a constant TSC).
2581	*
2582	* @param pCpum The CPUM instance data.
2583	* @param pConfig The CPUID configuration we've read from CFGM.
2584	*/
2585	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2586	{
2587	/*
2588	* Standard leaves.
2589	*/
2590	uint32_t uSubLeaf = 0;
2591	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2592	if (pCurLeaf)
2593	{
2594	uint32_t uLimit = pCurLeaf->uEax;
2595	if (uLimit <= UINT32_C(0x000fffff))
2596	{
2597	if (uLimit > pConfig->uMaxStdLeaf)
2598	{
2599	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2600	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2601	uLimit + 1, UINT32_C(0x000fffff));
2602	}
2603
2604	/* NT4 hack, no zapping of extra leaves here. */
2605	if (pConfig->fNt4LeafLimit && uLimit > 3)
2606	pCurLeaf->uEax = uLimit = 3;
2607
2608	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2609	pCurLeaf->uEax = uLimit;
2610	}
2611	else
2612	{
2613	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2614	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2615	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2616	}
2617	}
2618
2619	/*
2620	* Extended leaves.
2621	*/
2622	uSubLeaf = 0;
2623	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2624	if (pCurLeaf)
2625	{
2626	uint32_t uLimit = pCurLeaf->uEax;
2627	if ( uLimit >= UINT32_C(0x80000000)
2628	&& uLimit <= UINT32_C(0x800fffff))
2629	{
2630	if (uLimit > pConfig->uMaxExtLeaf)
2631	{
2632	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2633	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2634	uLimit + 1, UINT32_C(0x800fffff));
2635	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2636	pCurLeaf->uEax = uLimit;
2637	}
2638	}
2639	else
2640	{
2641	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2642	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2643	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2644	}
2645	}
2646
2647	/*
2648	* Centaur leaves (VIA).
2649	*/
2650	uSubLeaf = 0;
2651	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2652	if (pCurLeaf)
2653	{
2654	uint32_t uLimit = pCurLeaf->uEax;
2655	if ( uLimit >= UINT32_C(0xc0000000)
2656	&& uLimit <= UINT32_C(0xc00fffff))
2657	{
2658	if (uLimit > pConfig->uMaxCentaurLeaf)
2659	{
2660	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2661	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2662	uLimit + 1, UINT32_C(0xcfffffff));
2663	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2664	pCurLeaf->uEax = uLimit;
2665	}
2666	}
2667	else
2668	{
2669	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2670	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2671	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2672	}
2673	}
2674	}
2675
2676
2677	/**
2678	* Clears a CPUID leaf and all sub-leaves (to zero).
2679	*
2680	* @param pCpum The CPUM instance data.
2681	* @param uLeaf The leaf to clear.
2682	*/
2683	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2684	{
2685	uint32_t uSubLeaf = 0;
2686	PCPUMCPUIDLEAF pCurLeaf;
2687	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2688	{
2689	pCurLeaf->uEax = 0;
2690	pCurLeaf->uEbx = 0;
2691	pCurLeaf->uEcx = 0;
2692	pCurLeaf->uEdx = 0;
2693	uSubLeaf++;
2694	}
2695	}
2696
2697
2698	/**
2699	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2700	* the given leaf.
2701	*
2702	* @returns pLeaf.
2703	* @param pCpum The CPUM instance data.
2704	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2705	*/
2706	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2707	{
2708	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2709	if (pLeaf->fSubLeafMask != 0)
2710	{
2711	/*
2712	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2713	* Log everything while we're at it.
2714	*/
2715	LogRel(("CPUM:\n"
2716	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2717	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2718	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2719	for (;;)
2720	{
2721	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2722	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2723	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2724	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2725	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2726	break;
2727	pSubLeaf++;
2728	}
2729	LogRel(("CPUM:\n"));
2730
2731	/*
2732	* Remove the offending sub-leaves.
2733	*/
2734	if (pSubLeaf != pLeaf)
2735	{
2736	if (pSubLeaf != pLast)
2737	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2738	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2739	}
2740
2741	/*
2742	* Convert the first sub-leaf into a single leaf.
2743	*/
2744	pLeaf->uSubLeaf = 0;
2745	pLeaf->fSubLeafMask = 0;
2746	}
2747	return pLeaf;
2748	}
2749
2750
2751	/**
2752	* Sanitizes and adjust the CPUID leaves.
2753	*
2754	* Drop features that aren't virtualized (or virtualizable). Adjust information
2755	* and capabilities to fit the virtualized hardware. Remove information the
2756	* guest shouldn't have (because it's wrong in the virtual world or because it
2757	* gives away host details) or that we don't have documentation for and no idea
2758	* what means.
2759	*
2760	* @returns VBox status code.
2761	* @param pVM The cross context VM structure (for cCpus).
2762	* @param pCpum The CPUM instance data.
2763	* @param pConfig The CPUID configuration we've read from CFGM.
2764	*/
2765	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2766	{
2767	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2768	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2769	{ \
2770	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2771	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2772	}
2773	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2774	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2775	{ \
2776	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2777	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2778	}
2779	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2780	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2781	&& ((a_pLeafReg) & (fBitMask)) \
2782	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2783	{ \
2784	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2785	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2786	}
2787	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2788
2789	/* Cpuid 1:
2790	* EAX: CPU model, family and stepping.
2791	*
2792	* ECX + EDX: Supported features. Only report features we can support.
2793	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2794	* options may require adjusting (i.e. stripping what was enabled).
2795	*
2796	* EBX: Branding, CLFLUSH line size, logical processors per package and
2797	* initial APIC ID.
2798	*/
2799	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2800	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2801	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2802
2803	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2804	\| X86_CPUID_FEATURE_EDX_VME
2805	\| X86_CPUID_FEATURE_EDX_DE
2806	\| X86_CPUID_FEATURE_EDX_PSE
2807	\| X86_CPUID_FEATURE_EDX_TSC
2808	\| X86_CPUID_FEATURE_EDX_MSR
2809	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2810	\| X86_CPUID_FEATURE_EDX_MCE
2811	\| X86_CPUID_FEATURE_EDX_CX8
2812	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2813	//\| RT_BIT_32(10) - not defined
2814	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2815	//\| X86_CPUID_FEATURE_EDX_SEP
2816	\| X86_CPUID_FEATURE_EDX_MTRR
2817	\| X86_CPUID_FEATURE_EDX_PGE
2818	\| X86_CPUID_FEATURE_EDX_MCA
2819	\| X86_CPUID_FEATURE_EDX_CMOV
2820	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2821	\| X86_CPUID_FEATURE_EDX_PSE36
2822	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2823	\| X86_CPUID_FEATURE_EDX_CLFSH
2824	//\| RT_BIT_32(20) - not defined
2825	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2826	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2827	\| X86_CPUID_FEATURE_EDX_MMX
2828	\| X86_CPUID_FEATURE_EDX_FXSR
2829	\| X86_CPUID_FEATURE_EDX_SSE
2830	\| X86_CPUID_FEATURE_EDX_SSE2
2831	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2832	\| X86_CPUID_FEATURE_EDX_HTT
2833	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2834	//\| RT_BIT_32(30) - not defined
2835	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2836	;
2837	pStdFeatureLeaf->uEcx &= 0
2838	\| X86_CPUID_FEATURE_ECX_SSE3
2839	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2840	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2841	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2842	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2843	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2844	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
2845	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2846	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2847	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2848	\| X86_CPUID_FEATURE_ECX_SSSE3
2849	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2850	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2851	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2852	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2853	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2854	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2855	\| (pConfig->enmPcid ? X86_CPUID_FEATURE_ECX_PCID : 0)
2856	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2857	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2858	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2859	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2860	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2861	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2862	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2863	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2864	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2865	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2866	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2867	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2868	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2869	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2870	;
2871
2872	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2873	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2874	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2875	{
2876	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2877	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2878	}
2879
2880	if (pCpum->u8PortableCpuIdLevel > 0)
2881	{
2882	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2883	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2884	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2885	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2886	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2887	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2888	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2889	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
2890	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2891	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2892	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2893	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2894	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2895	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2896	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2897	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2898	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2899	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2900	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2901	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2902
2903	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2904	\| X86_CPUID_FEATURE_EDX_PSN
2905	\| X86_CPUID_FEATURE_EDX_DS
2906	\| X86_CPUID_FEATURE_EDX_ACPI
2907	\| X86_CPUID_FEATURE_EDX_SS
2908	\| X86_CPUID_FEATURE_EDX_TM
2909	\| X86_CPUID_FEATURE_EDX_PBE
2910	)));
2911	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2912	\| X86_CPUID_FEATURE_ECX_CPLDS
2913	\| X86_CPUID_FEATURE_ECX_AES
2914	\| X86_CPUID_FEATURE_ECX_VMX
2915	\| X86_CPUID_FEATURE_ECX_SMX
2916	\| X86_CPUID_FEATURE_ECX_EST
2917	\| X86_CPUID_FEATURE_ECX_TM2
2918	\| X86_CPUID_FEATURE_ECX_CNTXID
2919	\| X86_CPUID_FEATURE_ECX_FMA
2920	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2921	\| X86_CPUID_FEATURE_ECX_PDCM
2922	\| X86_CPUID_FEATURE_ECX_DCA
2923	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2924	)));
2925	}
2926
2927	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2928	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2929
2930	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2931	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2932	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2933	*/
2934	#ifdef VBOX_WITH_MULTI_CORE
2935	if (pVM->cCpus > 1)
2936	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2937	#endif
2938	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2939	{
2940	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2941	core times the number of CPU cores per processor */
2942	#ifdef VBOX_WITH_MULTI_CORE
2943	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2944	#else
2945	/* Single logical processor in a package. */
2946	pStdFeatureLeaf->uEbx \|= (1 << 16);
2947	#endif
2948	}
2949
2950	uint32_t uMicrocodeRev;
2951	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2952	if (RT_SUCCESS(rc))
2953	{
2954	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2955	}
2956	else
2957	{
2958	uMicrocodeRev = 0;
2959	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2960	}
2961
2962	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2963	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2964	*/
2965	if ( ( pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen
2966	/** @todo The following ASSUMES that Hygon uses the same version numbering
2967	* as AMD and that they shipped buggy firmware. */
2968	\|\| pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Hygon_Dhyana)
2969	&& uMicrocodeRev < 0x8001126
2970	&& !pConfig->fForceVme)
2971	{
2972	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2973	LogRel(("CPUM: Zen VME workaround engaged\n"));
2974	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
2975	}
2976
2977	/* Force standard feature bits. */
2978	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2979	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2980	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2981	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2982	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2983	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2984	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2985	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2986	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2987	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2988	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2989	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2990	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2991	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2992	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2993	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2994	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2995	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2996	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2997	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2998	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2999	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
3000
3001	pStdFeatureLeaf = NULL; /* Must refetch! */
3002
3003	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
3004	* AMD:
3005	* EAX: CPU model, family and stepping.
3006	*
3007	* ECX + EDX: Supported features. Only report features we can support.
3008	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3009	* options may require adjusting (i.e. stripping what was enabled).
3010	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
3011	*
3012	* EBX: Branding ID and package type (or reserved).
3013	*
3014	* Intel and probably most others:
3015	* EAX: 0
3016	* EBX: 0
3017	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
3018	*/
3019	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3020	if (pExtFeatureLeaf)
3021	{
3022	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
3023
3024	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
3025	\| X86_CPUID_AMD_FEATURE_EDX_VME
3026	\| X86_CPUID_AMD_FEATURE_EDX_DE
3027	\| X86_CPUID_AMD_FEATURE_EDX_PSE
3028	\| X86_CPUID_AMD_FEATURE_EDX_TSC
3029	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
3030	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
3031	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
3032	\| X86_CPUID_AMD_FEATURE_EDX_CX8
3033	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
3034	//\| RT_BIT_32(10) - reserved
3035	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
3036	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
3037	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3038	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
3039	\| X86_CPUID_AMD_FEATURE_EDX_PGE
3040	\| X86_CPUID_AMD_FEATURE_EDX_MCA
3041	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
3042	\| X86_CPUID_AMD_FEATURE_EDX_PAT
3043	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
3044	//\| RT_BIT_32(18) - reserved
3045	//\| RT_BIT_32(19) - reserved
3046	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
3047	//\| RT_BIT_32(21) - reserved
3048	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
3049	\| X86_CPUID_AMD_FEATURE_EDX_MMX
3050	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
3051	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
3052	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3053	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
3054	//\| RT_BIT_32(28) - reserved
3055	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
3056	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
3057	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
3058	;
3059	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
3060	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
3061	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
3062	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3063	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
3064	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
3065	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
3066	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
3067	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
3068	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
3069	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3070	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
3071	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
3072	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3073	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
3074	//\| RT_BIT_32(14) - reserved
3075	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
3076	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
3077	//\| RT_BIT_32(17) - reserved
3078	//\| RT_BIT_32(18) - reserved
3079	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
3080	//\| RT_BIT_32(20) - reserved
3081	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
3082	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
3083	//\| RT_BIT_32(23) - reserved
3084	//\| RT_BIT_32(24) - reserved
3085	//\| RT_BIT_32(25) - reserved
3086	//\| RT_BIT_32(26) - reserved
3087	//\| RT_BIT_32(27) - reserved
3088	//\| RT_BIT_32(28) - reserved
3089	//\| RT_BIT_32(29) - reserved
3090	//\| RT_BIT_32(30) - reserved
3091	//\| RT_BIT_32(31) - reserved
3092	;
3093	#ifdef VBOX_WITH_MULTI_CORE
3094	if ( pVM->cCpus > 1
3095	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3096	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3097	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
3098	#endif
3099
3100	if (pCpum->u8PortableCpuIdLevel > 0)
3101	{
3102	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
3103	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
3104	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
3105	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
3106	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
3107	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
3108	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
3109	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
3110	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
3111	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
3112	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
3113	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
3114	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
3115	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
3116	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
3117	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
3118
3119	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
3120	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3121	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3122	\| X86_CPUID_AMD_FEATURE_ECX_IBS
3123	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3124	\| X86_CPUID_AMD_FEATURE_ECX_WDT
3125	\| X86_CPUID_AMD_FEATURE_ECX_LWP
3126	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
3127	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
3128	\| UINT32_C(0xff964000)
3129	)));
3130	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
3131	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3132	\| RT_BIT(18)
3133	\| RT_BIT(19)
3134	\| RT_BIT(21)
3135	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
3136	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3137	\| RT_BIT(28)
3138	)));
3139	}
3140
3141	/* Force extended feature bits. */
3142	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
3143	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
3144	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
3145	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
3146	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
3147	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
3148	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
3149	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
3150	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3151	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
3152	}
3153	pExtFeatureLeaf = NULL; /* Must refetch! */
3154
3155
3156	/* Cpuid 2:
3157	* Intel: (Nondeterministic) Cache and TLB information
3158	* AMD: Reserved
3159	* VIA: Reserved
3160	* Safe to expose.
3161	*/
3162	uint32_t uSubLeaf = 0;
3163	PCPUMCPUIDLEAF pCurLeaf;
3164	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
3165	{
3166	if ((pCurLeaf->uEax & 0xff) > 1)
3167	{
3168	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
3169	pCurLeaf->uEax &= UINT32_C(0xffffff01);
3170	}
3171	uSubLeaf++;
3172	}
3173
3174	/* Cpuid 3:
3175	* Intel: EAX, EBX - reserved (transmeta uses these)
3176	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3177	* AMD: Reserved
3178	* VIA: Reserved
3179	* Safe to expose
3180	*/
3181	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3182	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3183	{
3184	uSubLeaf = 0;
3185	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3186	{
3187	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3188	if (pCpum->u8PortableCpuIdLevel > 0)
3189	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3190	uSubLeaf++;
3191	}
3192	}
3193
3194	/* Cpuid 4 + ECX:
3195	* Intel: Deterministic Cache Parameters Leaf.
3196	* AMD: Reserved
3197	* VIA: Reserved
3198	* Safe to expose, except for EAX:
3199	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3200	* Bits 31-26: Maximum number of processor cores in this physical package**
3201	* Note: These SMP values are constant regardless of ECX
3202	*/
3203	uSubLeaf = 0;
3204	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3205	{
3206	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3207	#ifdef VBOX_WITH_MULTI_CORE
3208	if ( pVM->cCpus > 1
3209	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3210	{
3211	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3212	/* One logical processor with possibly multiple cores. */
3213	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3214	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3215	}
3216	#endif
3217	uSubLeaf++;
3218	}
3219
3220	/* Cpuid 5: Monitor/mwait Leaf
3221	* Intel: ECX, EDX - reserved
3222	* EAX, EBX - Smallest and largest monitor line size
3223	* AMD: EDX - reserved
3224	* EAX, EBX - Smallest and largest monitor line size
3225	* ECX - extensions (ignored for now)
3226	* VIA: Reserved
3227	* Safe to expose
3228	*/
3229	uSubLeaf = 0;
3230	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3231	{
3232	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3233	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3234	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3235
3236	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3237	if (pConfig->enmMWaitExtensions)
3238	{
3239	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3240	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3241	it shall be part of our power management virtualization model */
3242	#if 0
3243	/* MWAIT sub C-states */
3244	pCurLeaf->uEdx =
3245	(0 << 0) /* 0 in C0 */ \|
3246	(2 << 4) /* 2 in C1 */ \|
3247	(2 << 8) /* 2 in C2 */ \|
3248	(2 << 12) /* 2 in C3 */ \|
3249	(0 << 16) /* 0 in C4 */
3250	;
3251	#endif
3252	}
3253	else
3254	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3255	uSubLeaf++;
3256	}
3257
3258	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3259	* Intel: Various stuff.
3260	* AMD: EAX, EBX, EDX - reserved.
3261	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3262	* present. Same as intel.
3263	* VIA: ??
3264	*
3265	* We clear everything here for now.
3266	*/
3267	cpumR3CpuIdZeroLeaf(pCpum, 6);
3268
3269	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3270	* EAX: Number of sub leaves.
3271	* EBX+ECX+EDX: Feature flags
3272	*
3273	* We only have documentation for one sub-leaf, so clear all other (no need
3274	* to remove them as such, just set them to zero).
3275	*
3276	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3277	* options may require adjusting (i.e. stripping what was enabled).
3278	*/
3279	uSubLeaf = 0;
3280	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3281	{
3282	switch (uSubLeaf)
3283	{
3284	case 0:
3285	{
3286	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3287	pCurLeaf->uEbx &= 0
3288	\| (pConfig->enmFsGsBase ? X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE : 0)
3289	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3290	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3291	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3292	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3293	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
3294	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3295	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3296	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3297	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3298	\| (pConfig->enmInvpcid ? X86_CPUID_STEXT_FEATURE_EBX_INVPCID : 0)
3299	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3300	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3301	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3302	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3303	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3304	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3305	//\| RT_BIT(17) - reserved
3306	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
3307	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3308	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3309	//\| RT_BIT(21) - reserved
3310	//\| RT_BIT(22) - reserved
3311	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
3312	//\| RT_BIT(24) - reserved
3313	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3314	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3315	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3316	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3317	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3318	//\| RT_BIT(30) - reserved
3319	//\| RT_BIT(31) - reserved
3320	;
3321	pCurLeaf->uEcx &= 0
3322	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3323	;
3324	pCurLeaf->uEdx &= 0
3325	\| (pConfig->enmMdsClear ? X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR : 0)
3326	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3327	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3328	\| (pConfig->enmFlushCmdMsr ? X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD : 0)
3329	\| (pConfig->enmArchCapMsr ? X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP : 0)
3330	;
3331
3332	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3333	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3334	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3335	{
3336	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3337	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3338	}
3339
3340	if (pCpum->u8PortableCpuIdLevel > 0)
3341	{
3342	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3343	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3344	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3345	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3346	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3347	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3348	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3349	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3350	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3351	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3352	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3353	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3354	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3355	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3356	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3357	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
3358	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
3359	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
3360	}
3361
3362	/* Dependencies. */
3363	if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
3364	pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3365
3366	/* Force standard feature bits. */
3367	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3368	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3369	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3370	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3371	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3372	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3373	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3374	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3375	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3376	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3377	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3378	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
3379	if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
3380	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3381	if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3382	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
3383	break;
3384	}
3385
3386	default:
3387	/* Invalid index, all values are zero. */
3388	pCurLeaf->uEax = 0;
3389	pCurLeaf->uEbx = 0;
3390	pCurLeaf->uEcx = 0;
3391	pCurLeaf->uEdx = 0;
3392	break;
3393	}
3394	uSubLeaf++;
3395	}
3396
3397	/* Cpuid 8: Marked as reserved by Intel and AMD.
3398	* We zero this since we don't know what it may have been used for.
3399	*/
3400	cpumR3CpuIdZeroLeaf(pCpum, 8);
3401
3402	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3403	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3404	* EBX, ECX, EDX - reserved.
3405	* AMD: Reserved
3406	* VIA: ??
3407	*
3408	* We zero this.
3409	*/
3410	cpumR3CpuIdZeroLeaf(pCpum, 9);
3411
3412	/* Cpuid 0xa: Architectural Performance Monitor Features
3413	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3414	* EBX, ECX, EDX - reserved.
3415	* AMD: Reserved
3416	* VIA: ??
3417	*
3418	* We zero this, for now at least.
3419	*/
3420	cpumR3CpuIdZeroLeaf(pCpum, 10);
3421
3422	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3423	* Intel: EAX - APCI ID shift right for next level.
3424	* EBX - Factory configured cores/threads at this level.
3425	* ECX - Level number (same as input) and level type (1,2,0).
3426	* EDX - Extended initial APIC ID.
3427	* AMD: Reserved
3428	* VIA: ??
3429	*/
3430	uSubLeaf = 0;
3431	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3432	{
3433	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3434	{
3435	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3436	if (bLevelType == 1)
3437	{
3438	/* Thread level - we don't do threads at the moment. */
3439	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3440	pCurLeaf->uEbx = 1;
3441	}
3442	else if (bLevelType == 2)
3443	{
3444	/* Core level. */
3445	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3446	#ifdef VBOX_WITH_MULTI_CORE
3447	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3448	pCurLeaf->uEax++;
3449	#endif
3450	pCurLeaf->uEbx = pVM->cCpus;
3451	}
3452	else
3453	{
3454	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3455	pCurLeaf->uEax = 0;
3456	pCurLeaf->uEbx = 0;
3457	pCurLeaf->uEcx = 0;
3458	}
3459	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3460	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3461	}
3462	else
3463	{
3464	pCurLeaf->uEax = 0;
3465	pCurLeaf->uEbx = 0;
3466	pCurLeaf->uEcx = 0;
3467	pCurLeaf->uEdx = 0;
3468	}
3469	uSubLeaf++;
3470	}
3471
3472	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3473	* We zero this since we don't know what it may have been used for.
3474	*/
3475	cpumR3CpuIdZeroLeaf(pCpum, 12);
3476
3477	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3478	* ECX=0: EAX - Valid bits in XCR0[31:0].
3479	* EBX - Maximum state size as per current XCR0 value.
3480	* ECX - Maximum state size for all supported features.
3481	* EDX - Valid bits in XCR0[63:32].
3482	* ECX=1: EAX - Various X-features.
3483	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3484	* ECX - Valid bits in IA32_XSS[31:0].
3485	* EDX - Valid bits in IA32_XSS[63:32].
3486	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3487	* if the bit invalid all four registers are set to zero.
3488	* EAX - The state size for this feature.
3489	* EBX - The state byte offset of this feature.
3490	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3491	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3492	*
3493	* Clear them all as we don't currently implement extended CPU state.
3494	*/
3495	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3496	uint64_t fGuestXcr0Mask = 0;
3497	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3498	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3499	{
3500	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3501	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3502	fGuestXcr0Mask \|= XSAVE_C_YMM;
3503	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3504	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3505	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3506	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3507
3508	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3509	}
3510	pStdFeatureLeaf = NULL;
3511	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3512
3513	/* Work the sub-leaves. */
3514	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3515	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3516	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3517	{
3518	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3519	if (pCurLeaf)
3520	{
3521	if (fGuestXcr0Mask)
3522	{
3523	switch (uSubLeaf)
3524	{
3525	case 0:
3526	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3527	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3528	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3529	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3530	VERR_CPUM_IPE_1);
3531	cbXSaveMaxActual = pCurLeaf->uEcx;
3532	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3533	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3534	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3535	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3536	VERR_CPUM_IPE_2);
3537	continue;
3538	case 1:
3539	pCurLeaf->uEax &= 0;
3540	pCurLeaf->uEcx &= 0;
3541	pCurLeaf->uEdx &= 0;
3542	/** @todo what about checking ebx? */
3543	continue;
3544	default:
3545	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3546	{
3547	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3548	&& pCurLeaf->uEax > 0
3549	&& pCurLeaf->uEbx < cbXSaveMaxActual
3550	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3551	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3552	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3553	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3554	VERR_CPUM_IPE_2);
3555	AssertLogRel(!(pCurLeaf->uEcx & 1));
3556	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3557	pCurLeaf->uEdx = 0; /* it's reserved... */
3558	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3559	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3560	continue;
3561	}
3562	break;
3563	}
3564	}
3565
3566	/* Clear the leaf. */
3567	pCurLeaf->uEax = 0;
3568	pCurLeaf->uEbx = 0;
3569	pCurLeaf->uEcx = 0;
3570	pCurLeaf->uEdx = 0;
3571	}
3572	}
3573
3574	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3575	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3576	{
3577	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3578	if (pCurLeaf)
3579	{
3580	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3581	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3582	pCurLeaf->uEbx = cbXSaveMaxReport;
3583	pCurLeaf->uEcx = cbXSaveMaxReport;
3584	}
3585	}
3586
3587	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3588	* We zero this since we don't know what it may have been used for.
3589	*/
3590	cpumR3CpuIdZeroLeaf(pCpum, 14);
3591
3592	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3593	* also known as Intel Resource Director Technology (RDT) Monitoring
3594	* We zero this as we don't currently virtualize PQM.
3595	*/
3596	cpumR3CpuIdZeroLeaf(pCpum, 15);
3597
3598	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3599	* also known as Intel Resource Director Technology (RDT) Allocation
3600	* We zero this as we don't currently virtualize PQE.
3601	*/
3602	cpumR3CpuIdZeroLeaf(pCpum, 16);
3603
3604	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3605	* We zero this since we don't know what it may have been used for.
3606	*/
3607	cpumR3CpuIdZeroLeaf(pCpum, 17);
3608
3609	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3610	* We zero this as we don't currently virtualize this.
3611	*/
3612	cpumR3CpuIdZeroLeaf(pCpum, 18);
3613
3614	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3615	* We zero this since we don't know what it may have been used for.
3616	*/
3617	cpumR3CpuIdZeroLeaf(pCpum, 19);
3618
3619	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3620	* We zero this as we don't currently virtualize this.
3621	*/
3622	cpumR3CpuIdZeroLeaf(pCpum, 20);
3623
3624	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3625	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3626	* EAX - denominator (unsigned).
3627	* EBX - numerator (unsigned).
3628	* ECX, EDX - reserved.
3629	* AMD: Reserved / undefined / not implemented.
3630	* VIA: Reserved / undefined / not implemented.
3631	* We zero this as we don't currently virtualize this.
3632	*/
3633	cpumR3CpuIdZeroLeaf(pCpum, 21);
3634
3635	/* Cpuid 0x16: Processor frequency info
3636	* Intel: EAX - Core base frequency in MHz.
3637	* EBX - Core maximum frequency in MHz.
3638	* ECX - Bus (reference) frequency in MHz.
3639	* EDX - Reserved.
3640	* AMD: Reserved / undefined / not implemented.
3641	* VIA: Reserved / undefined / not implemented.
3642	* We zero this as we don't currently virtualize this.
3643	*/
3644	cpumR3CpuIdZeroLeaf(pCpum, 22);
3645
3646	/* Cpuid 0x17..0x10000000: Unknown.
3647	* We don't know these and what they mean, so remove them. */
3648	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3649	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3650
3651
3652	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3653	* We remove all these as we're a hypervisor and must provide our own.
3654	*/
3655	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3656	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3657
3658
3659	/* Cpuid 0x80000000 is harmless. */
3660
3661	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3662
3663	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3664
3665	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3666	* Safe to pass on to the guest.
3667	*
3668	* AMD: 0x800000005 L1 cache information
3669	* 0x800000006 L2/L3 cache information
3670	* Intel: 0x800000005 reserved
3671	* 0x800000006 L2 cache information
3672	* VIA: 0x800000005 TLB and L1 cache information
3673	* 0x800000006 L2 cache information
3674	*/
3675
3676	/* Cpuid 0x800000007: Advanced Power Management Information.
3677	* AMD: EAX: Processor feedback capabilities.
3678	* EBX: RAS capabilites.
3679	* ECX: Advanced power monitoring interface.
3680	* EDX: Enhanced power management capabilities.
3681	* Intel: EAX, EBX, ECX - reserved.
3682	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3683	* VIA: Reserved
3684	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3685	*/
3686	uSubLeaf = 0;
3687	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3688	{
3689	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3690	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3691	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3692	{
3693	/*
3694	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3695	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3696	* bit is now configurable.
3697	*/
3698	pCurLeaf->uEdx &= 0
3699	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3700	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3701	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3702	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3703	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3704	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3705	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3706	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3707	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3708	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3709	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3710	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3711	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3712	\| 0;
3713	}
3714	else
3715	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3716	if (!pConfig->fInvariantTsc)
3717	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3718	uSubLeaf++;
3719	}
3720
3721	/* Cpuid 0x80000008:
3722	* AMD: EBX, EDX - reserved
3723	* EAX: Virtual/Physical/Guest address Size
3724	* ECX: Number of cores + APICIdCoreIdSize
3725	* Intel: EAX: Virtual/Physical address Size
3726	* EBX, ECX, EDX - reserved
3727	* VIA: EAX: Virtual/Physical address Size
3728	* EBX, ECX, EDX - reserved
3729	*
3730	* We only expose the virtual+pysical address size to the guest atm.
3731	* On AMD we set the core count, but not the apic id stuff as we're
3732	* currently not doing the apic id assignments in a complatible manner.
3733	*/
3734	uSubLeaf = 0;
3735	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3736	{
3737	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3738	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3739	pCurLeaf->uEdx = 0; /* reserved */
3740
3741	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3742	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3743	pCurLeaf->uEcx = 0;
3744	#ifdef VBOX_WITH_MULTI_CORE
3745	if ( pVM->cCpus > 1
3746	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3747	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3748	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3749	#endif
3750	uSubLeaf++;
3751	}
3752
3753	/* Cpuid 0x80000009: Reserved
3754	* We zero this since we don't know what it may have been used for.
3755	*/
3756	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3757
3758	/* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
3759	* AMD: EAX - SVM revision.
3760	* EBX - Number of ASIDs.
3761	* ECX - Reserved.
3762	* EDX - SVM Feature identification.
3763	*/
3764	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3765	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3766	{
3767	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3768	if ( pExtFeatureLeaf
3769	&& (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM))
3770	{
3771	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3772	if (pSvmFeatureLeaf)
3773	{
3774	pSvmFeatureLeaf->uEax = 0x1;
3775	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3776	pSvmFeatureLeaf->uEcx = 0;
3777	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3778	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3779	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3780	}
3781	else
3782	{
3783	/* Should never happen. */
3784	LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
3785	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3786	}
3787	}
3788	else
3789	{
3790	/* If SVM is not supported, this is reserved, zero out. */
3791	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3792	}
3793	}
3794	else
3795	{
3796	/* Cpuid 0x8000000a: Reserved on Intel.
3797	* We zero this since we don't know what it may have been used for.
3798	*/
3799	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3800	}
3801
3802	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3803	* We clear these as we don't know what purpose they might have. */
3804	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3805	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3806
3807	/* Cpuid 0x80000019: TLB configuration
3808	* Seems to be harmless, pass them thru as is. */
3809
3810	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3811	* Strip anything we don't know what is or addresses feature we don't implement. */
3812	uSubLeaf = 0;
3813	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3814	{
3815	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3816	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3817	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3818	;
3819	pCurLeaf->uEbx = 0; /* reserved */
3820	pCurLeaf->uEcx = 0; /* reserved */
3821	pCurLeaf->uEdx = 0; /* reserved */
3822	uSubLeaf++;
3823	}
3824
3825	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3826	* Clear this as we don't currently virtualize this feature. */
3827	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3828
3829	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3830	* Clear this as we don't currently virtualize this feature. */
3831	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3832
3833	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3834	* We need to sanitize the cores per cache (EAX[25:14]).
3835	*
3836	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3837	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3838	* slightly different meaning.
3839	*/
3840	uSubLeaf = 0;
3841	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3842	{
3843	#ifdef VBOX_WITH_MULTI_CORE
3844	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3845	if (cCores > pVM->cCpus)
3846	cCores = pVM->cCpus;
3847	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3848	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3849	#else
3850	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3851	#endif
3852	uSubLeaf++;
3853	}
3854
3855	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3856	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3857	* setup, we have one compute unit with all the cores in it. Single node.
3858	*/
3859	uSubLeaf = 0;
3860	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3861	{
3862	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3863	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3864	{
3865	#ifdef VBOX_WITH_MULTI_CORE
3866	pCurLeaf->uEbx = pVM->cCpus < 0x100
3867	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3868	#else
3869	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3870	#endif
3871	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3872	}
3873	else
3874	{
3875	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3876	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_HYGON);
3877	pCurLeaf->uEbx = 0; /* Reserved. */
3878	pCurLeaf->uEcx = 0; /* Reserved. */
3879	}
3880	pCurLeaf->uEdx = 0; /* Reserved. */
3881	uSubLeaf++;
3882	}
3883
3884	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3885	* We don't know these and what they mean, so remove them. */
3886	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3887	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3888
3889	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3890	* Just pass it thru for now. */
3891
3892	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3893	* Just pass it thru for now. */
3894
3895	/* Cpuid 0xc0000000: Centaur stuff.
3896	* Harmless, pass it thru. */
3897
3898	/* Cpuid 0xc0000001: Centaur features.
3899	* VIA: EAX - Family, model, stepping.
3900	* EDX - Centaur extended feature flags. Nothing interesting, except may
3901	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3902	* EBX, ECX - reserved.
3903	* We keep EAX but strips the rest.
3904	*/
3905	uSubLeaf = 0;
3906	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3907	{
3908	pCurLeaf->uEbx = 0;
3909	pCurLeaf->uEcx = 0;
3910	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3911	uSubLeaf++;
3912	}
3913
3914	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3915	* We only have fixed stale values, but should be harmless. */
3916
3917	/* Cpuid 0xc0000003: Reserved.
3918	* We zero this since we don't know what it may have been used for.
3919	*/
3920	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3921
3922	/* Cpuid 0xc0000004: Centaur Performance Info.
3923	* We only have fixed stale values, but should be harmless. */
3924
3925
3926	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3927	* We don't know these and what they mean, so remove them. */
3928	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3929	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3930
3931	return VINF_SUCCESS;
3932	#undef PORTABLE_DISABLE_FEATURE_BIT
3933	#undef PORTABLE_CLEAR_BITS_WHEN
3934	}
3935
3936
3937	/**
3938	* Reads a value in /CPUM/IsaExts/ node.
3939	*
3940	* @returns VBox status code (error message raised).
3941	* @param pVM The cross context VM structure. (For errors.)
3942	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3943	* @param pszValueName The value / extension name.
3944	* @param penmValue Where to return the choice.
3945	* @param enmDefault The default choice.
3946	*/
3947	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3948	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3949	{
3950	/*
3951	* Try integer encoding first.
3952	*/
3953	uint64_t uValue;
3954	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3955	if (RT_SUCCESS(rc))
3956	switch (uValue)
3957	{
3958	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3959	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3960	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3961	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3962	default:
3963	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3964	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3965	pszValueName, uValue);
3966	}
3967	/*
3968	* If missing, use default.
3969	*/
3970	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3971	*penmValue = enmDefault;
3972	else
3973	{
3974	if (rc == VERR_CFGM_NOT_INTEGER)
3975	{
3976	/*
3977	* Not an integer, try read it as a string.
3978	*/
3979	char szValue[32];
3980	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3981	if (RT_SUCCESS(rc))
3982	{
3983	RTStrToLower(szValue);
3984	size_t cchValue = strlen(szValue);
3985	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3986	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3987	*penmValue = CPUMISAEXTCFG_DISABLED;
3988	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3989	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3990	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3991	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3992	else if (EQ("portable"))
3993	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3994	else if (EQ("default") \|\| EQ("def"))
3995	*penmValue = enmDefault;
3996	else
3997	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3998	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3999	pszValueName, uValue);
4000	#undef EQ
4001	}
4002	}
4003	if (RT_FAILURE(rc))
4004	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
4005	}
4006	return VINF_SUCCESS;
4007	}
4008
4009
4010	/**
4011	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
4012	*
4013	* @returns VBox status code (error message raised).
4014	* @param pVM The cross context VM structure. (For errors.)
4015	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4016	* @param pszValueName The value / extension name.
4017	* @param penmValue Where to return the choice.
4018	* @param enmDefault The default choice.
4019	* @param fAllowed Allowed choice. Applied both to the result and to
4020	* the default value.
4021	*/
4022	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
4023	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
4024	{
4025	int rc;
4026	if (fAllowed)
4027	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4028	else
4029	{
4030	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
4031	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
4032	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
4033	*penmValue = CPUMISAEXTCFG_DISABLED;
4034	}
4035	return rc;
4036	}
4037
4038
4039	/**
4040	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
4041	*
4042	* @returns VBox status code (error message raised).
4043	* @param pVM The cross context VM structure. (For errors.)
4044	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4045	* @param pCpumCfg The /CPUM node (can be NULL).
4046	* @param pszValueName The value / extension name.
4047	* @param penmValue Where to return the choice.
4048	* @param enmDefault The default choice.
4049	*/
4050	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
4051	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
4052	{
4053	if (CFGMR3Exists(pCpumCfg, pszValueName))
4054	{
4055	if (!CFGMR3Exists(pIsaExts, pszValueName))
4056	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
4057	else
4058	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
4059	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
4060	pszValueName, pszValueName);
4061
4062	bool fLegacy;
4063	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
4064	if (RT_SUCCESS(rc))
4065	{
4066	*penmValue = fLegacy;
4067	return VINF_SUCCESS;
4068	}
4069	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
4070	}
4071
4072	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4073	}
4074
4075
4076	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
4077	{
4078	int rc;
4079
4080	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
4081	* When non-zero CPUID features that could cause portability issues will be
4082	* stripped. The higher the value the more features gets stripped. Higher
4083	* values should only be used when older CPUs are involved since it may
4084	* harm performance and maybe also cause problems with specific guests. */
4085	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
4086	AssertLogRelRCReturn(rc, rc);
4087
4088	/** @cfgm{/CPUM/GuestCpuName, string}
4089	* The name of the CPU we're to emulate. The default is the host CPU.
4090	* Note! CPUs other than "host" one is currently unsupported. */
4091	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
4092	AssertLogRelRCReturn(rc, rc);
4093
4094	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
4095	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
4096	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
4097	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
4098	*/
4099	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
4100	AssertLogRelRCReturn(rc, rc);
4101
4102	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
4103	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
4104	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
4105	* 64-bit linux guests which assume the presence of AMD performance counters
4106	* that we do not virtualize.
4107	*/
4108	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
4109	AssertLogRelRCReturn(rc, rc);
4110
4111	/** @cfgm{/CPUM/ForceVme, boolean, false}
4112	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
4113	* By default the flag is passed thru as is from the host CPU, except
4114	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
4115	* guests and DOS boxes in general.
4116	*/
4117	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
4118	AssertLogRelRCReturn(rc, rc);
4119
4120	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
4121	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
4122	* probably going to be a temporary hack, so don't depend on this.
4123	* The 1st byte of the value is the stepping, the 2nd byte value is the model
4124	* number and the 3rd byte value is the family, and the 4th value must be zero.
4125	*/
4126	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
4127	AssertLogRelRCReturn(rc, rc);
4128
4129	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
4130	* The last standard leaf to keep. The actual last value that is stored in EAX
4131	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
4132	* removed. (This works independently of and differently from NT4LeafLimit.)
4133	* The default is usually set to what we're able to reasonably sanitize.
4134	*/
4135	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
4136	AssertLogRelRCReturn(rc, rc);
4137
4138	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
4139	* The last extended leaf to keep. The actual last value that is stored in EAX
4140	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
4141	* leaf are removed. The default is set to what we're able to sanitize.
4142	*/
4143	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
4144	AssertLogRelRCReturn(rc, rc);
4145
4146	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
4147	* The last extended leaf to keep. The actual last value that is stored in EAX
4148	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
4149	* leaf are removed. The default is set to what we're able to sanitize.
4150	*/
4151	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
4152	AssertLogRelRCReturn(rc, rc);
4153
4154	bool fQueryNestedHwvirt = false
4155	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4156	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4157	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON
4158	#endif
4159	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4160	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
4161	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA
4162	#endif
4163	;
4164	if (fQueryNestedHwvirt)
4165	{
4166	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
4167	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
4168	* The default is false, and when enabled requires a 64-bit CPU with support for
4169	* nested-paging and AMD-V or unrestricted guest mode.
4170	*/
4171	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
4172	AssertLogRelRCReturn(rc, rc);
4173	if ( pConfig->fNestedHWVirt
4174	&& !fNestedPagingAndFullGuestExec)
4175	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
4176	"Cannot enable nested VT-x/AMD-V without nested-paging and unresricted guest execution!\n");
4177
4178	/** @todo Think about enabling this later with NEM/KVM. */
4179	if ( pConfig->fNestedHWVirt
4180	&& VM_IS_NEM_ENABLED(pVM))
4181	{
4182	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used!\n"));
4183	pConfig->fNestedHWVirt = false;
4184	}
4185
4186	/** @cfgm{/CPUM/NestedVmxPreemptTimer, bool, true}
4187	* Whether to expose the VMX-preemption timer feature to the guest (if also
4188	* supported by the host hardware). The default is true, and when disabled will
4189	* prevent exposing the VMX-preemption timer feature to the guest even if the host
4190	* supports it.
4191	*/
4192	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxPreemptTimer", &pVM->cpum.s.fNestedVmxPreemptTimer, true);
4193	AssertLogRelRCReturn(rc, rc);
4194	}
4195
4196	/*
4197	* Instruction Set Architecture (ISA) Extensions.
4198	*/
4199	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
4200	if (pIsaExts)
4201	{
4202	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
4203	"CMPXCHG16B"
4204	"\|MONITOR"
4205	"\|MWaitExtensions"
4206	"\|SSE4.1"
4207	"\|SSE4.2"
4208	"\|XSAVE"
4209	"\|AVX"
4210	"\|AVX2"
4211	"\|AESNI"
4212	"\|PCLMUL"
4213	"\|POPCNT"
4214	"\|MOVBE"
4215	"\|RDRAND"
4216	"\|RDSEED"
4217	"\|CLFLUSHOPT"
4218	"\|FSGSBASE"
4219	"\|PCID"
4220	"\|INVPCID"
4221	"\|FlushCmdMsr"
4222	"\|ABM"
4223	"\|SSE4A"
4224	"\|MISALNSSE"
4225	"\|3DNOWPRF"
4226	"\|AXMMX"
4227	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
4228	if (RT_FAILURE(rc))
4229	return rc;
4230	}
4231
4232	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
4233	* Expose CMPXCHG16B to the guest if supported by the host. For the time
4234	* being the default is to only do this for VMs with nested paging and AMD-V or
4235	* unrestricted guest mode.
4236	*/
4237	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
4238	AssertLogRelRCReturn(rc, rc);
4239
4240	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
4241	* Expose MONITOR/MWAIT instructions to the guest.
4242	*/
4243	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
4244	AssertLogRelRCReturn(rc, rc);
4245
4246	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4247	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4248	* break on interrupt feature (bit 1).
4249	*/
4250	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4251	AssertLogRelRCReturn(rc, rc);
4252
4253	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4254	* Expose SSE4.1 to the guest if available.
4255	*/
4256	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4257	AssertLogRelRCReturn(rc, rc);
4258
4259	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4260	* Expose SSE4.2 to the guest if available.
4261	*/
4262	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4263	AssertLogRelRCReturn(rc, rc);
4264
4265	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
4266	&& pVM->cpum.s.HostFeatures.fXSaveRstor
4267	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor;
4268	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4269
4270	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4271	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4272	* default is to only expose this to VMs with nested paging and AMD-V or
4273	* unrestricted guest execution mode. Not possible to force this one without
4274	* host support at the moment.
4275	*/
4276	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4277	fMayHaveXSave /fAllowed/);
4278	AssertLogRelRCReturn(rc, rc);
4279
4280	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4281	* Expose the AVX instruction set extensions to the guest if available and
4282	* XSAVE is exposed too. For the time being the default is to only expose this
4283	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4284	*/
4285	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4286	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4287	AssertLogRelRCReturn(rc, rc);
4288
4289	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4290	* Expose the AVX2 instruction set extensions to the guest if available and
4291	* XSAVE is exposed too. For the time being the default is to only expose this
4292	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4293	*/
4294	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4295	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4296	AssertLogRelRCReturn(rc, rc);
4297
4298	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4299	* Whether to expose the AES instructions to the guest. For the time being the
4300	* default is to only do this for VMs with nested paging and AMD-V or
4301	* unrestricted guest mode.
4302	*/
4303	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4304	AssertLogRelRCReturn(rc, rc);
4305
4306	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4307	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4308	* being the default is to only do this for VMs with nested paging and AMD-V or
4309	* unrestricted guest mode.
4310	*/
4311	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4312	AssertLogRelRCReturn(rc, rc);
4313
4314	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4315	* Whether to expose the POPCNT instructions to the guest. For the time
4316	* being the default is to only do this for VMs with nested paging and AMD-V or
4317	* unrestricted guest mode.
4318	*/
4319	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4320	AssertLogRelRCReturn(rc, rc);
4321
4322	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4323	* Whether to expose the MOVBE instructions to the guest. For the time
4324	* being the default is to only do this for VMs with nested paging and AMD-V or
4325	* unrestricted guest mode.
4326	*/
4327	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4328	AssertLogRelRCReturn(rc, rc);
4329
4330	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4331	* Whether to expose the RDRAND instructions to the guest. For the time being
4332	* the default is to only do this for VMs with nested paging and AMD-V or
4333	* unrestricted guest mode.
4334	*/
4335	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4336	AssertLogRelRCReturn(rc, rc);
4337
4338	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4339	* Whether to expose the RDSEED instructions to the guest. For the time being
4340	* the default is to only do this for VMs with nested paging and AMD-V or
4341	* unrestricted guest mode.
4342	*/
4343	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4344	AssertLogRelRCReturn(rc, rc);
4345
4346	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4347	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4348	* being the default is to only do this for VMs with nested paging and AMD-V or
4349	* unrestricted guest mode.
4350	*/
4351	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4352	AssertLogRelRCReturn(rc, rc);
4353
4354	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4355	* Whether to expose the read/write FSGSBASE instructions to the guest.
4356	*/
4357	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4358	AssertLogRelRCReturn(rc, rc);
4359
4360	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4361	* Whether to expose the PCID feature to the guest.
4362	*/
4363	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4364	AssertLogRelRCReturn(rc, rc);
4365
4366	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4367	* Whether to expose the INVPCID instruction to the guest.
4368	*/
4369	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4370	AssertLogRelRCReturn(rc, rc);
4371
4372	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
4373	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
4374	*/
4375	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4376	AssertLogRelRCReturn(rc, rc);
4377
4378	/** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
4379	* Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
4380	* the guest. Requires FlushCmdMsr to be present too.
4381	*/
4382	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4383	AssertLogRelRCReturn(rc, rc);
4384
4385	/** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
4386	* Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
4387	*/
4388	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4389	AssertLogRelRCReturn(rc, rc);
4390
4391
4392	/* AMD: */
4393
4394	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4395	* Whether to expose the AMD ABM instructions to the guest. For the time
4396	* being the default is to only do this for VMs with nested paging and AMD-V or
4397	* unrestricted guest mode.
4398	*/
4399	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4400	AssertLogRelRCReturn(rc, rc);
4401
4402	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4403	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4404	* being the default is to only do this for VMs with nested paging and AMD-V or
4405	* unrestricted guest mode.
4406	*/
4407	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4408	AssertLogRelRCReturn(rc, rc);
4409
4410	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4411	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4412	* the time being the default is to only do this for VMs with nested paging and
4413	* AMD-V or unrestricted guest mode.
4414	*/
4415	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4416	AssertLogRelRCReturn(rc, rc);
4417
4418	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4419	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4420	* For the time being the default is to only do this for VMs with nested paging
4421	* and AMD-V or unrestricted guest mode.
4422	*/
4423	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4424	AssertLogRelRCReturn(rc, rc);
4425
4426	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4427	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4428	* the default is to only do this for VMs with nested paging and AMD-V or
4429	* unrestricted guest mode.
4430	*/
4431	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4432	AssertLogRelRCReturn(rc, rc);
4433
4434	return VINF_SUCCESS;
4435	}
4436
4437
4438	/**
4439	* Initializes the emulated CPU's CPUID & MSR information.
4440	*
4441	* @returns VBox status code.
4442	* @param pVM The cross context VM structure.
4443	* @param pHostMsrs Pointer to the host MSRs.
4444	*/
4445	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
4446	{
4447	Assert(pHostMsrs);
4448
4449	PCPUM pCpum = &pVM->cpum.s;
4450	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4451
4452	/*
4453	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4454	* on construction and manage everything from here on.
4455	*/
4456	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4457	{
4458	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4459	pVCpu->cpum.s.fCpuIdApicFeatureVisible = true;
4460	}
4461
4462	/*
4463	* Read the configuration.
4464	*/
4465	CPUMCPUIDCONFIG Config;
4466	RT_ZERO(Config);
4467
4468	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4469	AssertRCReturn(rc, rc);
4470
4471	/*
4472	* Get the guest CPU data from the database and/or the host.
4473	*
4474	* The CPUID and MSRs are currently living on the regular heap to avoid
4475	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4476	* API for the hyper heap). This means special cleanup considerations.
4477	*/
4478	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4479	if (RT_FAILURE(rc))
4480	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4481	? VMSetError(pVM, rc, RT_SRC_POS,
4482	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4483	: rc;
4484
4485	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4486	{
4487	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4488	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4489	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4490	}
4491	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4492
4493	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4494	* Overrides the guest MSRs.
4495	*/
4496	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4497
4498	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4499	* Overrides the CPUID leaf values (from the host CPU usually) used for
4500	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4501	* values when moving a VM to a different machine. Another use is restricting
4502	* (or extending) the feature set exposed to the guest. */
4503	if (RT_SUCCESS(rc))
4504	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4505
4506	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4507	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4508	"Found unsupported configuration node '/CPUM/CPUID/'. "
4509	"Please use IMachine::setCPUIDLeaf() instead.");
4510
4511	CPUMMSRS GuestMsrs;
4512	RT_ZERO(GuestMsrs);
4513
4514	/*
4515	* Pre-explode the CPUID info.
4516	*/
4517	if (RT_SUCCESS(rc))
4518	{
4519	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
4520	&pCpum->GuestFeatures);
4521	}
4522
4523	/*
4524	* Sanitize the cpuid information passed on to the guest.
4525	*/
4526	if (RT_SUCCESS(rc))
4527	{
4528	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4529	if (RT_SUCCESS(rc))
4530	{
4531	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4532	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4533	}
4534	}
4535
4536	/*
4537	* Setup MSRs introduced in microcode updates or that are otherwise not in
4538	* the CPU profile, but are advertised in the CPUID info we just sanitized.
4539	*/
4540	if (RT_SUCCESS(rc))
4541	rc = cpumR3MsrReconcileWithCpuId(pVM);
4542	/*
4543	* MSR fudging.
4544	*/
4545	if (RT_SUCCESS(rc))
4546	{
4547	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4548	* Fudges some common MSRs if not present in the selected CPU database entry.
4549	* This is for trying to keep VMs running when moved between different hosts
4550	* and different CPU vendors. */
4551	bool fEnable;
4552	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4553	if (RT_SUCCESS(rc) && fEnable)
4554	{
4555	rc = cpumR3MsrApplyFudge(pVM);
4556	AssertLogRelRC(rc);
4557	}
4558	}
4559	if (RT_SUCCESS(rc))
4560	{
4561	/*
4562	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4563	* guest CPU features again.
4564	*/
4565	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4566	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4567	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
4568	RTMemFree(pvFree);
4569
4570	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4571	int rc2 = MMHyperDupMem(pVM, pvFree,
4572	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4573	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4574	RTMemFree(pvFree);
4575	AssertLogRelRCReturn(rc1, rc1);
4576	AssertLogRelRCReturn(rc2, rc2);
4577
4578	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4579
4580	/*
4581	* Finally, initialize guest VMX MSRs.
4582	*
4583	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
4584	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
4585	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
4586	*/
4587	if (pVM->cpum.s.GuestFeatures.fVmx)
4588	{
4589	Assert(Config.fNestedHWVirt);
4590	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
4591
4592	/* Copy MSRs to all VCPUs */
4593	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
4594	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4595	{
4596	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4597	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
4598	}
4599	}
4600
4601	/*
4602	* Some more configuration that we're applying at the end of everything
4603	* via the CPUMR3SetGuestCpuIdFeature API.
4604	*/
4605
4606	/* Check if PAE was explicitely enabled by the user. */
4607	bool fEnable;
4608	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4609	AssertRCReturn(rc, rc);
4610	if (fEnable)
4611	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4612
4613	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4614	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4615	AssertRCReturn(rc, rc);
4616	if (fEnable)
4617	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4618
4619	/* Check if speculation control is enabled. */
4620	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4621	AssertRCReturn(rc, rc);
4622	if (fEnable)
4623	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4624
4625	return VINF_SUCCESS;
4626	}
4627
4628	/*
4629	* Failed before switching to hyper heap.
4630	*/
4631	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4632	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4633	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4634	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4635	return rc;
4636	}
4637
4638
4639	/**
4640	* Sets a CPUID feature bit during VM initialization.
4641	*
4642	* Since the CPUID feature bits are generally related to CPU features, other
4643	* CPUM configuration like MSRs can also be modified by calls to this API.
4644	*
4645	* @param pVM The cross context VM structure.
4646	* @param enmFeature The feature to set.
4647	*/
4648	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4649	{
4650	PCPUMCPUIDLEAF pLeaf;
4651	PCPUMMSRRANGE pMsrRange;
4652
4653	switch (enmFeature)
4654	{
4655	/*
4656	* Set the APIC bit in both feature masks.
4657	*/
4658	case CPUMCPUIDFEATURE_APIC:
4659	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4660	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4661	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4662
4663	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4664	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4665	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4666
4667	pVM->cpum.s.GuestFeatures.fApic = 1;
4668
4669	/* Make sure we've got the APICBASE MSR present. */
4670	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4671	if (!pMsrRange)
4672	{
4673	static CPUMMSRRANGE const s_ApicBase =
4674	{
4675	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4676	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4677	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4678	/.szName = / "IA32_APIC_BASE"
4679	};
4680	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4681	AssertLogRelRC(rc);
4682	}
4683
4684	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4685	break;
4686
4687	/*
4688	* Set the x2APIC bit in the standard feature mask.
4689	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4690	*/
4691	case CPUMCPUIDFEATURE_X2APIC:
4692	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4693	if (pLeaf)
4694	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4695	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4696
4697	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4698	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4699	if (pMsrRange)
4700	{
4701	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4702	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4703	}
4704
4705	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4706	break;
4707
4708	/*
4709	* Set the sysenter/sysexit bit in the standard feature mask.
4710	* Assumes the caller knows what it's doing! (host must support these)
4711	*/
4712	case CPUMCPUIDFEATURE_SEP:
4713	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4714	{
4715	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4716	return;
4717	}
4718
4719	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4720	if (pLeaf)
4721	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4722	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4723	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4724	break;
4725
4726	/*
4727	* Set the syscall/sysret bit in the extended feature mask.
4728	* Assumes the caller knows what it's doing! (host must support these)
4729	*/
4730	case CPUMCPUIDFEATURE_SYSCALL:
4731	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4732	if ( !pLeaf
4733	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4734	{
4735	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4736	return;
4737	}
4738
4739	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4740	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4741	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4742	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4743	break;
4744
4745	/*
4746	* Set the PAE bit in both feature masks.
4747	* Assumes the caller knows what it's doing! (host must support these)
4748	*/
4749	case CPUMCPUIDFEATURE_PAE:
4750	if (!pVM->cpum.s.HostFeatures.fPae)
4751	{
4752	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4753	return;
4754	}
4755
4756	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4757	if (pLeaf)
4758	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4759
4760	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4761	if ( pLeaf
4762	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4763	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
4764	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4765
4766	pVM->cpum.s.GuestFeatures.fPae = 1;
4767	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4768	break;
4769
4770	/*
4771	* Set the LONG MODE bit in the extended feature mask.
4772	* Assumes the caller knows what it's doing! (host must support these)
4773	*/
4774	case CPUMCPUIDFEATURE_LONG_MODE:
4775	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4776	if ( !pLeaf
4777	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4778	{
4779	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4780	return;
4781	}
4782
4783	/* Valid for both Intel and AMD. */
4784	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4785	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4786	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
4787	if (pVM->cpum.s.GuestFeatures.fVmx)
4788	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4789	{
4790	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4791	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic &= ~VMX_BASIC_PHYSADDR_WIDTH_32BIT;
4792	}
4793	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4794	break;
4795
4796	/*
4797	* Set the NX/XD bit in the extended feature mask.
4798	* Assumes the caller knows what it's doing! (host must support these)
4799	*/
4800	case CPUMCPUIDFEATURE_NX:
4801	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4802	if ( !pLeaf
4803	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4804	{
4805	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4806	return;
4807	}
4808
4809	/* Valid for both Intel and AMD. */
4810	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4811	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4812	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4813	break;
4814
4815
4816	/*
4817	* Set the LAHF/SAHF support in 64-bit mode.
4818	* Assumes the caller knows what it's doing! (host must support this)
4819	*/
4820	case CPUMCPUIDFEATURE_LAHF:
4821	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4822	if ( !pLeaf
4823	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4824	{
4825	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4826	return;
4827	}
4828
4829	/* Valid for both Intel and AMD. */
4830	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4831	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4832	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4833	break;
4834
4835	/*
4836	* Set the page attribute table bit. This is alternative page level
4837	* cache control that doesn't much matter when everything is
4838	* virtualized, though it may when passing thru device memory.
4839	*/
4840	case CPUMCPUIDFEATURE_PAT:
4841	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4842	if (pLeaf)
4843	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4844
4845	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4846	if ( pLeaf
4847	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4848	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
4849	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4850
4851	pVM->cpum.s.GuestFeatures.fPat = 1;
4852	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4853	break;
4854
4855	/*
4856	* Set the RDTSCP support bit.
4857	* Assumes the caller knows what it's doing! (host must support this)
4858	*/
4859	case CPUMCPUIDFEATURE_RDTSCP:
4860	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4861	if ( !pLeaf
4862	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4863	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4864	{
4865	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4866	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4867	return;
4868	}
4869
4870	/* Valid for both Intel and AMD. */
4871	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4872	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4873	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4874	break;
4875
4876	/*
4877	* Set the Hypervisor Present bit in the standard feature mask.
4878	*/
4879	case CPUMCPUIDFEATURE_HVP:
4880	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4881	if (pLeaf)
4882	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4883	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4884	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4885	break;
4886
4887	/*
4888	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4889	* This currently includes the Present bit and MWAITBREAK bit as well.
4890	*/
4891	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4892	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4893	if ( !pLeaf
4894	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4895	{
4896	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4897	return;
4898	}
4899
4900	/* Valid for both Intel and AMD. */
4901	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4902	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4903	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4904	break;
4905
4906	/*
4907	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
4908	* on Intel CPUs, and different on AMDs.
4909	*/
4910	case CPUMCPUIDFEATURE_SPEC_CTRL:
4911	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
4912	{
4913	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4914	if ( !pLeaf
4915	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
4916	{
4917	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
4918	return;
4919	}
4920
4921	/* The feature can be enabled. Let's see what we can actually do. */
4922	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
4923
4924	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
4925	if (pVM->cpum.s.HostFeatures.fIbrs)
4926	{
4927	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
4928	pVM->cpum.s.GuestFeatures.fIbrs = 1;
4929	if (pVM->cpum.s.HostFeatures.fStibp)
4930	{
4931	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
4932	pVM->cpum.s.GuestFeatures.fStibp = 1;
4933	}
4934
4935	/* Make sure we have the speculation control MSR... */
4936	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
4937	if (!pMsrRange)
4938	{
4939	static CPUMMSRRANGE const s_SpecCtrl =
4940	{
4941	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
4942	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
4943	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4944	/.szName = / "IA32_SPEC_CTRL"
4945	};
4946	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4947	AssertLogRelRC(rc);
4948	}
4949
4950	/* ... and the predictor command MSR. */
4951	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
4952	if (!pMsrRange)
4953	{
4954	/** @todo incorrect fWrGpMask. */
4955	static CPUMMSRRANGE const s_SpecCtrl =
4956	{
4957	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
4958	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
4959	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4960	/.szName = / "IA32_PRED_CMD"
4961	};
4962	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4963	AssertLogRelRC(rc);
4964	}
4965
4966	}
4967
4968	if (pVM->cpum.s.HostFeatures.fArchCap)
4969	{
4970	/* Install the architectural capabilities MSR. */
4971	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
4972	if (!pMsrRange)
4973	{
4974	static CPUMMSRRANGE const s_ArchCaps =
4975	{
4976	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
4977	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
4978	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
4979	/.szName = / "IA32_ARCH_CAPABILITIES"
4980	};
4981	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
4982	AssertLogRelRC(rc);
4983	}
4984	}
4985
4986	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
4987	}
4988	else if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4989	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
4990	{
4991	/* The precise details of AMD's implementation are not yet clear. */
4992	}
4993	break;
4994
4995	default:
4996	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4997	break;
4998	}
4999
5000	/** @todo can probably kill this as this API is now init time only... */
5001	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5002	{
5003	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5004	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5005	}
5006	}
5007
5008
5009	/**
5010	* Queries a CPUID feature bit.
5011	*
5012	* @returns boolean for feature presence
5013	* @param pVM The cross context VM structure.
5014	* @param enmFeature The feature to query.
5015	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
5016	*/
5017	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
5018	{
5019	switch (enmFeature)
5020	{
5021	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
5022	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
5023	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
5024	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
5025	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
5026	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
5027	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
5028	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
5029	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
5030	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
5031	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
5032	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
5033	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
5034
5035	case CPUMCPUIDFEATURE_INVALID:
5036	case CPUMCPUIDFEATURE_32BIT_HACK:
5037	break;
5038	}
5039	AssertFailed();
5040	return false;
5041	}
5042
5043
5044	/**
5045	* Clears a CPUID feature bit.
5046	*
5047	* @param pVM The cross context VM structure.
5048	* @param enmFeature The feature to clear.
5049	*
5050	* @deprecated Probably better to default the feature to disabled and only allow
5051	* setting (enabling) it during construction.
5052	*/
5053	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
5054	{
5055	PCPUMCPUIDLEAF pLeaf;
5056	switch (enmFeature)
5057	{
5058	case CPUMCPUIDFEATURE_APIC:
5059	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
5060	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5061	if (pLeaf)
5062	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
5063
5064	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5065	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
5066	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
5067
5068	pVM->cpum.s.GuestFeatures.fApic = 0;
5069	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
5070	break;
5071
5072	case CPUMCPUIDFEATURE_X2APIC:
5073	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
5074	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5075	if (pLeaf)
5076	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
5077	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
5078	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
5079	break;
5080
5081	case CPUMCPUIDFEATURE_PAE:
5082	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5083	if (pLeaf)
5084	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
5085
5086	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5087	if ( pLeaf
5088	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
5089	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
5090	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
5091
5092	pVM->cpum.s.GuestFeatures.fPae = 0;
5093	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
5094	break;
5095
5096	case CPUMCPUIDFEATURE_PAT:
5097	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5098	if (pLeaf)
5099	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
5100
5101	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5102	if ( pLeaf
5103	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
5104	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
5105	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
5106
5107	pVM->cpum.s.GuestFeatures.fPat = 0;
5108	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
5109	break;
5110
5111	case CPUMCPUIDFEATURE_LONG_MODE:
5112	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5113	if (pLeaf)
5114	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
5115	pVM->cpum.s.GuestFeatures.fLongMode = 0;
5116	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = 32;
5117	if (pVM->cpum.s.GuestFeatures.fVmx)
5118	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5119	{
5120	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5121	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic \|= VMX_BASIC_PHYSADDR_WIDTH_32BIT;
5122	}
5123	break;
5124
5125	case CPUMCPUIDFEATURE_LAHF:
5126	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5127	if (pLeaf)
5128	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
5129	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
5130	break;
5131
5132	case CPUMCPUIDFEATURE_RDTSCP:
5133	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5134	if (pLeaf)
5135	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
5136	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
5137	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
5138	break;
5139
5140	case CPUMCPUIDFEATURE_HVP:
5141	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5142	if (pLeaf)
5143	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
5144	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
5145	break;
5146
5147	case CPUMCPUIDFEATURE_MWAIT_EXTS:
5148	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
5149	if (pLeaf)
5150	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
5151	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
5152	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
5153	break;
5154
5155	case CPUMCPUIDFEATURE_SPEC_CTRL:
5156	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
5157	if (pLeaf)
5158	pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP);
5159	pVM->cpum.s.GuestFeatures.fSpeculationControl = 0;
5160	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
5161	break;
5162
5163	default:
5164	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5165	break;
5166	}
5167
5168	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5169	{
5170	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5171	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5172	}
5173	}
5174
5175
5176
5177	/*
5178	*
5179	*
5180	* Saved state related code.
5181	* Saved state related code.
5182	* Saved state related code.
5183	*
5184	*
5185	*/
5186
5187	/**
5188	* Called both in pass 0 and the final pass.
5189	*
5190	* @param pVM The cross context VM structure.
5191	* @param pSSM The saved state handle.
5192	*/
5193	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
5194	{
5195	/*
5196	* Save all the CPU ID leaves.
5197	*/
5198	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
5199	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5200	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
5201	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5202
5203	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5204
5205	/*
5206	* Save a good portion of the raw CPU IDs as well as they may come in
5207	* handy when validating features for raw mode.
5208	*/
5209	CPUMCPUID aRawStd[16];
5210	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
5211	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5212	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
5213	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
5214
5215	CPUMCPUID aRawExt[32];
5216	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
5217	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5218	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
5219	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
5220	}
5221
5222
5223	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5224	{
5225	uint32_t cCpuIds;
5226	int rc = SSMR3GetU32(pSSM, &cCpuIds);
5227	if (RT_SUCCESS(rc))
5228	{
5229	if (cCpuIds < 64)
5230	{
5231	for (uint32_t i = 0; i < cCpuIds; i++)
5232	{
5233	CPUMCPUID CpuId;
5234	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
5235	if (RT_FAILURE(rc))
5236	break;
5237
5238	CPUMCPUIDLEAF NewLeaf;
5239	NewLeaf.uLeaf = uBase + i;
5240	NewLeaf.uSubLeaf = 0;
5241	NewLeaf.fSubLeafMask = 0;
5242	NewLeaf.uEax = CpuId.uEax;
5243	NewLeaf.uEbx = CpuId.uEbx;
5244	NewLeaf.uEcx = CpuId.uEcx;
5245	NewLeaf.uEdx = CpuId.uEdx;
5246	NewLeaf.fFlags = 0;
5247	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
5248	}
5249	}
5250	else
5251	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5252	}
5253	if (RT_FAILURE(rc))
5254	{
5255	RTMemFree(*ppaLeaves);
5256	*ppaLeaves = NULL;
5257	*pcLeaves = 0;
5258	}
5259	return rc;
5260	}
5261
5262
5263	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5264	{
5265	*ppaLeaves = NULL;
5266	*pcLeaves = 0;
5267
5268	int rc;
5269	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
5270	{
5271	/*
5272	* The new format. Starts by declaring the leave size and count.
5273	*/
5274	uint32_t cbLeaf;
5275	SSMR3GetU32(pSSM, &cbLeaf);
5276	uint32_t cLeaves;
5277	rc = SSMR3GetU32(pSSM, &cLeaves);
5278	if (RT_SUCCESS(rc))
5279	{
5280	if (cbLeaf == sizeof(**ppaLeaves))
5281	{
5282	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
5283	{
5284	/*
5285	* Load the leaves one by one.
5286	*
5287	* The uPrev stuff is a kludge for working around a week worth of bad saved
5288	* states during the CPUID revamp in March 2015. We saved too many leaves
5289	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
5290	* garbage entires at the end of the array when restoring. We also had
5291	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
5292	* this kludge doesn't deal correctly with that, but who cares...
5293	*/
5294	uint32_t uPrev = 0;
5295	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
5296	{
5297	CPUMCPUIDLEAF Leaf;
5298	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
5299	if (RT_SUCCESS(rc))
5300	{
5301	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
5302	\|\| Leaf.uLeaf >= uPrev)
5303	{
5304	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5305	uPrev = Leaf.uLeaf;
5306	}
5307	else
5308	uPrev = UINT32_MAX;
5309	}
5310	}
5311	}
5312	else
5313	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5314	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5315	}
5316	else
5317	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5318	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5319	}
5320	}
5321	else
5322	{
5323	/*
5324	* The old format with its three inflexible arrays.
5325	*/
5326	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5327	if (RT_SUCCESS(rc))
5328	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5329	if (RT_SUCCESS(rc))
5330	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5331	if (RT_SUCCESS(rc))
5332	{
5333	/*
5334	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5335	*/
5336	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5337	if ( pLeaf
5338	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5339	{
5340	CPUMCPUIDLEAF Leaf;
5341	Leaf.uLeaf = 4;
5342	Leaf.fSubLeafMask = UINT32_MAX;
5343	Leaf.uSubLeaf = 0;
5344	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5345	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5346	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5347	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5348	\| UINT32_C(63); /* system coherency line size - 1 */
5349	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5350	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5351	\| (UINT32_C(1) << 5) /* cache level */
5352	\| UINT32_C(1); /* cache type (data) */
5353	Leaf.fFlags = 0;
5354	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5355	if (RT_SUCCESS(rc))
5356	{
5357	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5358	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5359	}
5360	if (RT_SUCCESS(rc))
5361	{
5362	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5363	Leaf.uEcx = 4095; /* sets - 1 */
5364	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5365	Leaf.uEbx \|= UINT32_C(23) << 22;
5366	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5367	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5368	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5369	Leaf.uEax \|= UINT32_C(2) << 5;
5370	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5371	}
5372	}
5373	}
5374	}
5375	return rc;
5376	}
5377
5378
5379	/**
5380	* Loads the CPU ID leaves saved by pass 0, inner worker.
5381	*
5382	* @returns VBox status code.
5383	* @param pVM The cross context VM structure.
5384	* @param pSSM The saved state handle.
5385	* @param uVersion The format version.
5386	* @param paLeaves Guest CPUID leaves loaded from the state.
5387	* @param cLeaves The number of leaves in @a paLeaves.
5388	* @param pMsrs The guest MSRs.
5389	*/
5390	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
5391	{
5392	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5393
5394	/*
5395	* Continue loading the state into stack buffers.
5396	*/
5397	CPUMCPUID GuestDefCpuId;
5398	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5399	AssertRCReturn(rc, rc);
5400
5401	CPUMCPUID aRawStd[16];
5402	uint32_t cRawStd;
5403	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5404	if (cRawStd > RT_ELEMENTS(aRawStd))
5405	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5406	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5407	AssertRCReturn(rc, rc);
5408	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5409	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5410
5411	CPUMCPUID aRawExt[32];
5412	uint32_t cRawExt;
5413	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5414	if (cRawExt > RT_ELEMENTS(aRawExt))
5415	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5416	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5417	AssertRCReturn(rc, rc);
5418	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5419	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5420
5421	/*
5422	* Get the raw CPU IDs for the current host.
5423	*/
5424	CPUMCPUID aHostRawStd[16];
5425	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5426	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5427
5428	CPUMCPUID aHostRawExt[32];
5429	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5430	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5431	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5432
5433	/*
5434	* Get the host and guest overrides so we don't reject the state because
5435	* some feature was enabled thru these interfaces.
5436	* Note! We currently only need the feature leaves, so skip rest.
5437	*/
5438	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5439	CPUMCPUID aHostOverrideStd[2];
5440	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5441	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5442
5443	CPUMCPUID aHostOverrideExt[2];
5444	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5445	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5446
5447	/*
5448	* This can be skipped.
5449	*/
5450	bool fStrictCpuIdChecks;
5451	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5452
5453	/*
5454	* Define a bunch of macros for simplifying the santizing/checking code below.
5455	*/
5456	/* Generic expression + failure message. */
5457	#define CPUID_CHECK_RET(expr, fmt) \
5458	do { \
5459	if (!(expr)) \
5460	{ \
5461	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5462	if (fStrictCpuIdChecks) \
5463	{ \
5464	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5465	RTStrFree(pszMsg); \
5466	return rcCpuid; \
5467	} \
5468	LogRel(("CPUM: %s\n", pszMsg)); \
5469	RTStrFree(pszMsg); \
5470	} \
5471	} while (0)
5472	#define CPUID_CHECK_WRN(expr, fmt) \
5473	do { \
5474	if (!(expr)) \
5475	LogRel(fmt); \
5476	} while (0)
5477
5478	/* For comparing two values and bitch if they differs. */
5479	#define CPUID_CHECK2_RET(what, host, saved) \
5480	do { \
5481	if ((host) != (saved)) \
5482	{ \
5483	if (fStrictCpuIdChecks) \
5484	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5485	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5486	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5487	} \
5488	} while (0)
5489	#define CPUID_CHECK2_WRN(what, host, saved) \
5490	do { \
5491	if ((host) != (saved)) \
5492	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5493	} while (0)
5494
5495	/* For checking raw cpu features (raw mode). */
5496	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5497	do { \
5498	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5499	{ \
5500	if (fStrictCpuIdChecks) \
5501	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5502	N_(#bit " mismatch: host=%d saved=%d"), \
5503	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5504	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5505	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5506	} \
5507	} while (0)
5508	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5509	do { \
5510	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5511	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5512	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5513	} while (0)
5514	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5515
5516	/* For checking guest features. */
5517	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5518	do { \
5519	if ( (aGuestCpuId##set [1].reg & bit) \
5520	&& !(aHostRaw##set [1].reg & bit) \
5521	&& !(aHostOverride##set [1].reg & bit) \
5522	) \
5523	{ \
5524	if (fStrictCpuIdChecks) \
5525	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5526	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5527	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5528	} \
5529	} while (0)
5530	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5531	do { \
5532	if ( (aGuestCpuId##set [1].reg & bit) \
5533	&& !(aHostRaw##set [1].reg & bit) \
5534	&& !(aHostOverride##set [1].reg & bit) \
5535	) \
5536	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5537	} while (0)
5538	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5539	do { \
5540	if ( (aGuestCpuId##set [1].reg & bit) \
5541	&& !(aHostRaw##set [1].reg & bit) \
5542	&& !(aHostOverride##set [1].reg & bit) \
5543	) \
5544	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5545	} while (0)
5546	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5547
5548	/* For checking guest features if AMD guest CPU. */
5549	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5550	do { \
5551	if ( (aGuestCpuId##set [1].reg & bit) \
5552	&& fGuestAmd \
5553	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5554	&& !(aHostOverride##set [1].reg & bit) \
5555	) \
5556	{ \
5557	if (fStrictCpuIdChecks) \
5558	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5559	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5560	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5561	} \
5562	} while (0)
5563	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5564	do { \
5565	if ( (aGuestCpuId##set [1].reg & bit) \
5566	&& fGuestAmd \
5567	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5568	&& !(aHostOverride##set [1].reg & bit) \
5569	) \
5570	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5571	} while (0)
5572	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5573	do { \
5574	if ( (aGuestCpuId##set [1].reg & bit) \
5575	&& fGuestAmd \
5576	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5577	&& !(aHostOverride##set [1].reg & bit) \
5578	) \
5579	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5580	} while (0)
5581	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5582
5583	/* For checking AMD features which have a corresponding bit in the standard
5584	range. (Intel defines very few bits in the extended feature sets.) */
5585	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5586	do { \
5587	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5588	&& !(fHostAmd \
5589	? aHostRawExt[1].reg & (ExtBit) \
5590	: aHostRawStd[1].reg & (StdBit)) \
5591	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5592	) \
5593	{ \
5594	if (fStrictCpuIdChecks) \
5595	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5596	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5597	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5598	} \
5599	} while (0)
5600	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5601	do { \
5602	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5603	&& !(fHostAmd \
5604	? aHostRawExt[1].reg & (ExtBit) \
5605	: aHostRawStd[1].reg & (StdBit)) \
5606	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5607	) \
5608	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5609	} while (0)
5610	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5611	do { \
5612	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5613	&& !(fHostAmd \
5614	? aHostRawExt[1].reg & (ExtBit) \
5615	: aHostRawStd[1].reg & (StdBit)) \
5616	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5617	) \
5618	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5619	} while (0)
5620	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5621
5622
5623	/*
5624	* Verify that we can support the features already exposed to the guest on
5625	* this host.
5626	*
5627	* Most of the features we're emulating requires intercepting instruction
5628	* and doing it the slow way, so there is no need to warn when they aren't
5629	* present in the host CPU. Thus we use IGN instead of EMU on these.
5630	*
5631	* Trailing comments:
5632	* "EMU" - Possible to emulate, could be lots of work and very slow.
5633	* "EMU?" - Can this be emulated?
5634	*/
5635	CPUMCPUID aGuestCpuIdStd[2];
5636	RT_ZERO(aGuestCpuIdStd);
5637	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5638
5639	/* CPUID(1).ecx */
5640	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5641	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5642	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5643	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5644	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5645	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5646	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5647	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5648	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5649	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5650	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5651	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5652	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5653	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5654	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5655	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5656	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5657	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5658	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5659	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5660	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5661	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5662	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5663	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5664	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5665	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5666	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5667	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5668	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5669	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5670	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5671	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5672
5673	/* CPUID(1).edx */
5674	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5675	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5676	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5677	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5678	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5679	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5680	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5681	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5682	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5683	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5684	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5685	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5686	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5687	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5688	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5689	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5690	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5691	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5692	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5693	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5694	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5695	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5696	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5697	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5698	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5699	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5700	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5701	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5702	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5703	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5704	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5705	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5706
5707	/* CPUID(0x80000000). */
5708	CPUMCPUID aGuestCpuIdExt[2];
5709	RT_ZERO(aGuestCpuIdExt);
5710	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5711	{
5712	/** @todo deal with no 0x80000001 on the host. */
5713	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx)
5714	\|\| ASMIsHygonCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5715	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx)
5716	\|\| ASMIsHygonCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5717
5718	/* CPUID(0x80000001).ecx */
5719	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5720	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5721	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5722	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5723	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5724	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5725	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5726	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5727	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5728	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5729	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5730	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5731	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5732	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5733	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5734	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5735	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5736	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5737	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5738	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5739	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5740	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5741	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5742	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5743	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5744	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5745	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5746	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5747	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5748	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5749	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5750	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5751
5752	/* CPUID(0x80000001).edx */
5753	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5754	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5755	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5756	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5757	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5758	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5759	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5760	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5761	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5762	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5763	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5764	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5765	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5766	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5767	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5768	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5769	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5770	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5771	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5772	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5773	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5774	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5775	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5776	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5777	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5778	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5779	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5780	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5781	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5782	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5783	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5784	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5785	}
5786
5787	/** @todo check leaf 7 */
5788
5789	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5790	* ECX=0: EAX - Valid bits in XCR0[31:0].
5791	* EBX - Maximum state size as per current XCR0 value.
5792	* ECX - Maximum state size for all supported features.
5793	* EDX - Valid bits in XCR0[63:32].
5794	* ECX=1: EAX - Various X-features.
5795	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5796	* ECX - Valid bits in IA32_XSS[31:0].
5797	* EDX - Valid bits in IA32_XSS[63:32].
5798	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5799	* if the bit invalid all four registers are set to zero.
5800	* EAX - The state size for this feature.
5801	* EBX - The state byte offset of this feature.
5802	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5803	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5804	*/
5805	uint64_t fGuestXcr0Mask = 0;
5806	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5807	if ( pCurLeaf
5808	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5809	&& ( pCurLeaf->uEax
5810	\|\| pCurLeaf->uEbx
5811	\|\| pCurLeaf->uEcx
5812	\|\| pCurLeaf->uEdx) )
5813	{
5814	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5815	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5816	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5817	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5818	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5819	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5820	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5821	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5822
5823	/* We don't support any additional features yet. */
5824	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5825	if (pCurLeaf && pCurLeaf->uEax)
5826	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5827	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5828	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5829	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5830	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5831	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5832
5833
5834	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5835	{
5836	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5837	if (pCurLeaf)
5838	{
5839	/* If advertised, the state component offset and size must match the one used by host. */
5840	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5841	{
5842	CPUMCPUID RawHost;
5843	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5844	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5845	if ( RawHost.uEbx != pCurLeaf->uEbx
5846	\|\| RawHost.uEax != pCurLeaf->uEax)
5847	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5848	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5849	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5850	}
5851	}
5852	}
5853	}
5854	/* Clear leaf 0xd just in case we're loading an old state... */
5855	else if (pCurLeaf)
5856	{
5857	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5858	{
5859	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5860	if (pCurLeaf)
5861	{
5862	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5863	\|\| ( pCurLeaf->uEax == 0
5864	&& pCurLeaf->uEbx == 0
5865	&& pCurLeaf->uEcx == 0
5866	&& pCurLeaf->uEdx == 0),
5867	("uVersion=%#x; %#x %#x %#x %#x\n",
5868	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5869	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5870	}
5871	}
5872	}
5873
5874	/* Update the fXStateGuestMask value for the VM. */
5875	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5876	{
5877	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5878	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5879	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5880	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5881	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5882	}
5883
5884	#undef CPUID_CHECK_RET
5885	#undef CPUID_CHECK_WRN
5886	#undef CPUID_CHECK2_RET
5887	#undef CPUID_CHECK2_WRN
5888	#undef CPUID_RAW_FEATURE_RET
5889	#undef CPUID_RAW_FEATURE_WRN
5890	#undef CPUID_RAW_FEATURE_IGN
5891	#undef CPUID_GST_FEATURE_RET
5892	#undef CPUID_GST_FEATURE_WRN
5893	#undef CPUID_GST_FEATURE_EMU
5894	#undef CPUID_GST_FEATURE_IGN
5895	#undef CPUID_GST_FEATURE2_RET
5896	#undef CPUID_GST_FEATURE2_WRN
5897	#undef CPUID_GST_FEATURE2_EMU
5898	#undef CPUID_GST_FEATURE2_IGN
5899	#undef CPUID_GST_AMD_FEATURE_RET
5900	#undef CPUID_GST_AMD_FEATURE_WRN
5901	#undef CPUID_GST_AMD_FEATURE_EMU
5902	#undef CPUID_GST_AMD_FEATURE_IGN
5903
5904	/*
5905	* We're good, commit the CPU ID leaves.
5906	*/
5907	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5908	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5909	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5910	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5911	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
5912	AssertLogRelRCReturn(rc, rc);
5913
5914	return VINF_SUCCESS;
5915	}
5916
5917
5918	/**
5919	* Loads the CPU ID leaves saved by pass 0.
5920	*
5921	* @returns VBox status code.
5922	* @param pVM The cross context VM structure.
5923	* @param pSSM The saved state handle.
5924	* @param uVersion The format version.
5925	* @param pMsrs The guest MSRs.
5926	*/
5927	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
5928	{
5929	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5930
5931	/*
5932	* Load the CPUID leaves array first and call worker to do the rest, just so
5933	* we can free the memory when we need to without ending up in column 1000.
5934	*/
5935	PCPUMCPUIDLEAF paLeaves;
5936	uint32_t cLeaves;
5937	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5938	AssertRC(rc);
5939	if (RT_SUCCESS(rc))
5940	{
5941	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
5942	RTMemFree(paLeaves);
5943	}
5944	return rc;
5945	}
5946
5947
5948
5949	/**
5950	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5951	*
5952	* @returns VBox status code.
5953	* @param pVM The cross context VM structure.
5954	* @param pSSM The saved state handle.
5955	* @param uVersion The format version.
5956	*/
5957	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5958	{
5959	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5960
5961	/*
5962	* Restore the CPUID leaves.
5963	*
5964	* Note that we support restoring less than the current amount of standard
5965	* leaves because we've been allowed more is newer version of VBox.
5966	*/
5967	uint32_t cElements;
5968	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5969	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5970	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5971	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5972
5973	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5974	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5975	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5976	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5977
5978	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5979	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5980	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5981	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5982
5983	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5984
5985	/*
5986	* Check that the basic cpuid id information is unchanged.
5987	*/
5988	/** @todo we should check the 64 bits capabilities too! */
5989	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5990	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5991	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5992	uint32_t au32CpuIdSaved[8];
5993	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5994	if (RT_SUCCESS(rc))
5995	{
5996	/* Ignore CPU stepping. */
5997	au32CpuId[4] &= 0xfffffff0;
5998	au32CpuIdSaved[4] &= 0xfffffff0;
5999
6000	/* Ignore APIC ID (AMD specs). */
6001	au32CpuId[5] &= ~0xff000000;
6002	au32CpuIdSaved[5] &= ~0xff000000;
6003
6004	/* Ignore the number of Logical CPUs (AMD specs). */
6005	au32CpuId[5] &= ~0x00ff0000;
6006	au32CpuIdSaved[5] &= ~0x00ff0000;
6007
6008	/* Ignore some advanced capability bits, that we don't expose to the guest. */
6009	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6010	\| X86_CPUID_FEATURE_ECX_VMX
6011	\| X86_CPUID_FEATURE_ECX_SMX
6012	\| X86_CPUID_FEATURE_ECX_EST
6013	\| X86_CPUID_FEATURE_ECX_TM2
6014	\| X86_CPUID_FEATURE_ECX_CNTXID
6015	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6016	\| X86_CPUID_FEATURE_ECX_PDCM
6017	\| X86_CPUID_FEATURE_ECX_DCA
6018	\| X86_CPUID_FEATURE_ECX_X2APIC
6019	);
6020	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6021	\| X86_CPUID_FEATURE_ECX_VMX
6022	\| X86_CPUID_FEATURE_ECX_SMX
6023	\| X86_CPUID_FEATURE_ECX_EST
6024	\| X86_CPUID_FEATURE_ECX_TM2
6025	\| X86_CPUID_FEATURE_ECX_CNTXID
6026	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6027	\| X86_CPUID_FEATURE_ECX_PDCM
6028	\| X86_CPUID_FEATURE_ECX_DCA
6029	\| X86_CPUID_FEATURE_ECX_X2APIC
6030	);
6031
6032	/* Make sure we don't forget to update the masks when enabling
6033	* features in the future.
6034	*/
6035	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
6036	( X86_CPUID_FEATURE_ECX_DTES64
6037	\| X86_CPUID_FEATURE_ECX_VMX
6038	\| X86_CPUID_FEATURE_ECX_SMX
6039	\| X86_CPUID_FEATURE_ECX_EST
6040	\| X86_CPUID_FEATURE_ECX_TM2
6041	\| X86_CPUID_FEATURE_ECX_CNTXID
6042	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6043	\| X86_CPUID_FEATURE_ECX_PDCM
6044	\| X86_CPUID_FEATURE_ECX_DCA
6045	\| X86_CPUID_FEATURE_ECX_X2APIC
6046	)));
6047	/* do the compare */
6048	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
6049	{
6050	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
6051	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
6052	"Saved=%.*Rhxs\n"
6053	"Real =%.*Rhxs\n",
6054	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6055	sizeof(au32CpuId), au32CpuId));
6056	else
6057	{
6058	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
6059	"Saved=%.*Rhxs\n"
6060	"Real =%.*Rhxs\n",
6061	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6062	sizeof(au32CpuId), au32CpuId));
6063	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
6064	}
6065	}
6066	}
6067
6068	return rc;
6069	}
6070
6071
6072
6073	/*
6074	*
6075	*
6076	* CPUID Info Handler.
6077	* CPUID Info Handler.
6078	* CPUID Info Handler.
6079	*
6080	*
6081	*/
6082
6083
6084
6085	/**
6086	* Get L1 cache / TLS associativity.
6087	*/
6088	static const char getCacheAss(unsigned u, char pszBuf)
6089	{
6090	if (u == 0)
6091	return "res0 ";
6092	if (u == 1)
6093	return "direct";
6094	if (u == 255)
6095	return "fully";
6096	if (u >= 256)
6097	return "???";
6098
6099	RTStrPrintf(pszBuf, 16, "%d way", u);
6100	return pszBuf;
6101	}
6102
6103
6104	/**
6105	* Get L2 cache associativity.
6106	*/
6107	const char *getL2CacheAss(unsigned u)
6108	{
6109	switch (u)
6110	{
6111	case 0: return "off ";
6112	case 1: return "direct";
6113	case 2: return "2 way ";
6114	case 3: return "res3 ";
6115	case 4: return "4 way ";
6116	case 5: return "res5 ";
6117	case 6: return "8 way ";
6118	case 7: return "res7 ";
6119	case 8: return "16 way";
6120	case 9: return "res9 ";
6121	case 10: return "res10 ";
6122	case 11: return "res11 ";
6123	case 12: return "res12 ";
6124	case 13: return "res13 ";
6125	case 14: return "res14 ";
6126	case 15: return "fully ";
6127	default: return "????";
6128	}
6129	}
6130
6131
6132	/** CPUID(1).EDX field descriptions. */
6133	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6134	{
6135	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6136	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6137	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6138	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6139	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6140	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6141	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6142	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6143	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6144	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6145	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6146	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6147	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6148	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6149	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6150	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6151	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6152	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6153	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6154	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6155	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6156	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6157	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6158	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6159	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6160	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6161	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6162	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6163	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6164	DBGFREGSUBFIELD_TERMINATOR()
6165	};
6166
6167	/** CPUID(1).ECX field descriptions. */
6168	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6169	{
6170	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6171	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6172	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6173	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6174	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6175	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6176	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6177	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6178	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6179	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6180	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6181	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6182	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6183	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6184	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6185	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6186	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6187	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6188	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6189	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6190	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6191	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6192	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6193	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6194	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6195	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6196	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6197	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6198	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6199	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6200	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6201	DBGFREGSUBFIELD_TERMINATOR()
6202	};
6203
6204	/** CPUID(7,0).EBX field descriptions. */
6205	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6206	{
6207	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6208	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6209	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6210	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6211	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6212	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6213	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6214	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6215	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6216	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6217	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6218	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6219	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6220	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6221	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6222	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6223	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6224	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6225	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6226	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6227	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6228	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6229	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6230	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6231	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6232	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6233	DBGFREGSUBFIELD_TERMINATOR()
6234	};
6235
6236	/** CPUID(7,0).ECX field descriptions. */
6237	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6238	{
6239	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6240	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6241	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6242	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6243	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6244	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6245	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6246	DBGFREGSUBFIELD_TERMINATOR()
6247	};
6248
6249	/** CPUID(7,0).EDX field descriptions. */
6250	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6251	{
6252	DBGFREGSUBFIELD_RO("MD_CLEAR\0" "Supports MDS related buffer clearing", 10, 1, 0),
6253	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6254	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6255	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
6256	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6257	DBGFREGSUBFIELD_RO("CORECAP\0" "Supports IA32_CORE_CAP", 30, 1, 0),
6258	DBGFREGSUBFIELD_RO("SSBD\0" "Supports IA32_SPEC_CTRL.SSBD", 31, 1, 0),
6259	DBGFREGSUBFIELD_TERMINATOR()
6260	};
6261
6262
6263	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6264	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6265	{
6266	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6267	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6268	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6269	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6270	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6271	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6272	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6273	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6274	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6275	DBGFREGSUBFIELD_TERMINATOR()
6276	};
6277
6278	/** CPUID(13,1).EAX field descriptions. */
6279	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6280	{
6281	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6282	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6283	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6284	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6285	DBGFREGSUBFIELD_TERMINATOR()
6286	};
6287
6288
6289	/** CPUID(0x80000001,0).EDX field descriptions. */
6290	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6291	{
6292	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6293	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6294	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6295	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6296	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6297	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6298	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6299	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6300	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6301	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6302	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6303	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6304	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6305	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6306	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6307	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6308	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6309	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6310	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6311	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6312	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6313	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6314	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6315	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6316	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6317	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6318	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6319	DBGFREGSUBFIELD_TERMINATOR()
6320	};
6321
6322	/** CPUID(0x80000001,0).ECX field descriptions. */
6323	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6324	{
6325	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6326	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6327	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6328	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6329	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6330	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6331	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6332	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6333	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6334	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6335	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6336	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6337	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6338	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6339	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6340	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6341	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6342	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6343	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6344	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6345	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6346	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6347	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6348	DBGFREGSUBFIELD_RO("PCX_L2I\0" "L2I/L3 Performance Counter Extensions", 28, 1, 0),
6349	DBGFREGSUBFIELD_RO("MWAITX\0" "MWAITX and MONITORX instructions", 29, 1, 0),
6350	DBGFREGSUBFIELD_TERMINATOR()
6351	};
6352
6353	/** CPUID(0x8000000a,0).EDX field descriptions. */
6354	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
6355	{
6356	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
6357	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
6358	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
6359	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
6360	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
6361	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
6362	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
6363	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
6364	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
6365	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
6366	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
6367	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
6368	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
6369	DBGFREGSUBFIELD_RO("GMET\0" "Guest Mode Execute Trap Extension", 17, 1, 0),
6370	DBGFREGSUBFIELD_TERMINATOR()
6371	};
6372
6373
6374	/** CPUID(0x80000007,0).EDX field descriptions. */
6375	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6376	{
6377	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6378	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6379	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6380	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6381	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6382	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6383	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6384	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6385	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6386	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6387	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6388	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6389	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6390	DBGFREGSUBFIELD_TERMINATOR()
6391	};
6392
6393	/** CPUID(0x80000008,0).EBX field descriptions. */
6394	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6395	{
6396	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6397	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6398	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6399	DBGFREGSUBFIELD_RO("RDPRU\0" "RDPRU instruction", 4, 1, 0),
6400	DBGFREGSUBFIELD_RO("MCOMMIT\0" "MCOMMIT instruction", 8, 1, 0),
6401	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6402	DBGFREGSUBFIELD_TERMINATOR()
6403	};
6404
6405
6406	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6407	const char *pszLeadIn, uint32_t cchWidth)
6408	{
6409	if (pszLeadIn)
6410	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6411
6412	for (uint32_t iBit = 0; iBit < 32; iBit++)
6413	if (RT_BIT_32(iBit) & uVal)
6414	{
6415	while ( pDesc->pszName != NULL
6416	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6417	pDesc++;
6418	if ( pDesc->pszName != NULL
6419	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6420	{
6421	if (pDesc->cBits == 1)
6422	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6423	else
6424	{
6425	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6426	if (pDesc->cBits < 32)
6427	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6428	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6429	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6430	}
6431	}
6432	else
6433	pHlp->pfnPrintf(pHlp, " %u", iBit);
6434	}
6435	if (pszLeadIn)
6436	pHlp->pfnPrintf(pHlp, "\n");
6437	}
6438
6439
6440	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6441	const char *pszLeadIn, uint32_t cchWidth)
6442	{
6443	if (pszLeadIn)
6444	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6445
6446	for (uint32_t iBit = 0; iBit < 64; iBit++)
6447	if (RT_BIT_64(iBit) & uVal)
6448	{
6449	while ( pDesc->pszName != NULL
6450	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6451	pDesc++;
6452	if ( pDesc->pszName != NULL
6453	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6454	{
6455	if (pDesc->cBits == 1)
6456	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6457	else
6458	{
6459	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6460	if (pDesc->cBits < 64)
6461	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6462	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6463	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6464	}
6465	}
6466	else
6467	pHlp->pfnPrintf(pHlp, " %u", iBit);
6468	}
6469	if (pszLeadIn)
6470	pHlp->pfnPrintf(pHlp, "\n");
6471	}
6472
6473
6474	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6475	const char *pszLeadIn, uint32_t cchWidth)
6476	{
6477	if (!uVal)
6478	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6479	else
6480	{
6481	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6482	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6483	pHlp->pfnPrintf(pHlp, " )\n");
6484	}
6485	}
6486
6487
6488	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6489	uint32_t cchWidth)
6490	{
6491	uint32_t uCombined = uVal1 \| uVal2;
6492	for (uint32_t iBit = 0; iBit < 32; iBit++)
6493	if ( (RT_BIT_32(iBit) & uCombined)
6494	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6495	{
6496	while ( pDesc->pszName != NULL
6497	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6498	pDesc++;
6499
6500	if ( pDesc->pszName != NULL
6501	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6502	{
6503	size_t cchMnemonic = strlen(pDesc->pszName);
6504	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6505	size_t cchDesc = strlen(pszDesc);
6506	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6507	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6508	if (pDesc->cBits < 32)
6509	{
6510	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6511	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6512	}
6513
6514	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6515	pDesc->pszName, pszDesc,
6516	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6517	uFieldValue1, uFieldValue2);
6518
6519	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6520	pDesc++;
6521	}
6522	else
6523	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6524	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6525	}
6526	}
6527
6528
6529	/**
6530	* Produces a detailed summary of standard leaf 0x00000001.
6531	*
6532	* @param pHlp The info helper functions.
6533	* @param pCurLeaf The 0x00000001 leaf.
6534	* @param fVerbose Whether to be very verbose or not.
6535	* @param fIntel Set if intel CPU.
6536	*/
6537	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6538	{
6539	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6540	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6541	uint32_t uEAX = pCurLeaf->uEax;
6542	uint32_t uEBX = pCurLeaf->uEbx;
6543
6544	pHlp->pfnPrintf(pHlp,
6545	"%36s %2d \tExtended: %d \tEffective: %d\n"
6546	"%36s %2d \tExtended: %d \tEffective: %d\n"
6547	"%36s %d\n"
6548	"%36s %d (%s)\n"
6549	"%36s %#04x\n"
6550	"%36s %d\n"
6551	"%36s %d\n"
6552	"%36s %#04x\n"
6553	,
6554	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6555	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6556	"Stepping:", ASMGetCpuStepping(uEAX),
6557	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6558	"APIC ID:", (uEBX >> 24) & 0xff,
6559	"Logical CPUs:",(uEBX >> 16) & 0xff,
6560	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6561	"Brand ID:", (uEBX >> 0) & 0xff);
6562	if (fVerbose)
6563	{
6564	CPUMCPUID Host;
6565	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6566	pHlp->pfnPrintf(pHlp, "Features\n");
6567	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6568	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6569	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6570	}
6571	else
6572	{
6573	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6574	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6575	}
6576	}
6577
6578
6579	/**
6580	* Produces a detailed summary of standard leaf 0x00000007.
6581	*
6582	* @param pHlp The info helper functions.
6583	* @param paLeaves The CPUID leaves array.
6584	* @param cLeaves The number of leaves in the array.
6585	* @param pCurLeaf The first 0x00000007 leaf.
6586	* @param fVerbose Whether to be very verbose or not.
6587	*/
6588	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6589	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6590	{
6591	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6592	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6593	for (;;)
6594	{
6595	CPUMCPUID Host;
6596	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6597
6598	switch (pCurLeaf->uSubLeaf)
6599	{
6600	case 0:
6601	if (fVerbose)
6602	{
6603	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6604	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6605	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6606	if (pCurLeaf->uEdx \|\| Host.uEdx)
6607	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6608	}
6609	else
6610	{
6611	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6612	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6613	if (pCurLeaf->uEdx)
6614	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6615	}
6616	break;
6617
6618	default:
6619	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6620	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6621	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6622	break;
6623
6624	}
6625
6626	/* advance. */
6627	pCurLeaf++;
6628	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6629	\|\| pCurLeaf->uLeaf != 0x7)
6630	break;
6631	}
6632	}
6633
6634
6635	/**
6636	* Produces a detailed summary of standard leaf 0x0000000d.
6637	*
6638	* @param pHlp The info helper functions.
6639	* @param paLeaves The CPUID leaves array.
6640	* @param cLeaves The number of leaves in the array.
6641	* @param pCurLeaf The first 0x00000007 leaf.
6642	* @param fVerbose Whether to be very verbose or not.
6643	*/
6644	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6645	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6646	{
6647	RT_NOREF_PV(fVerbose);
6648	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6649	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6650	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6651	{
6652	CPUMCPUID Host;
6653	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6654
6655	switch (uSubLeaf)
6656	{
6657	case 0:
6658	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6659	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6660	pCurLeaf->uEbx, pCurLeaf->uEcx);
6661	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6662
6663	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6664	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6665	"Valid XCR0 bits, guest:", 42);
6666	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6667	"Valid XCR0 bits, host:", 42);
6668	break;
6669
6670	case 1:
6671	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6672	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6673	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6674
6675	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6676	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6677	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6678
6679	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6680	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6681	" Valid IA32_XSS bits, guest:", 42);
6682	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6683	" Valid IA32_XSS bits, host:", 42);
6684	break;
6685
6686	default:
6687	if ( pCurLeaf
6688	&& pCurLeaf->uSubLeaf == uSubLeaf
6689	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6690	{
6691	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6692	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6693	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6694	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6695	if (pCurLeaf->uEdx)
6696	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6697	pHlp->pfnPrintf(pHlp, " --");
6698	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6699	pHlp->pfnPrintf(pHlp, "\n");
6700	}
6701	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6702	{
6703	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6704	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6705	if (Host.uEcx & ~RT_BIT_32(0))
6706	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6707	if (Host.uEdx)
6708	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6709	pHlp->pfnPrintf(pHlp, " --");
6710	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6711	pHlp->pfnPrintf(pHlp, "\n");
6712	}
6713	break;
6714
6715	}
6716
6717	/* advance. */
6718	if (pCurLeaf)
6719	{
6720	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6721	&& pCurLeaf->uSubLeaf <= uSubLeaf
6722	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6723	pCurLeaf++;
6724	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6725	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6726	pCurLeaf = NULL;
6727	}
6728	}
6729	}
6730
6731
6732	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6733	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6734	{
6735	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6736	&& pCurLeaf->uLeaf <= uUpToLeaf)
6737	{
6738	pHlp->pfnPrintf(pHlp,
6739	" %s\n"
6740	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6741	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6742	&& pCurLeaf->uLeaf <= uUpToLeaf)
6743	{
6744	CPUMCPUID Host;
6745	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6746	pHlp->pfnPrintf(pHlp,
6747	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6748	"Hst: %08x %08x %08x %08x\n",
6749	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6750	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6751	pCurLeaf++;
6752	}
6753	}
6754
6755	return pCurLeaf;
6756	}
6757
6758
6759	/**
6760	* Display the guest CpuId leaves.
6761	*
6762	* @param pVM The cross context VM structure.
6763	* @param pHlp The info helper functions.
6764	* @param pszArgs "terse", "default" or "verbose".
6765	*/
6766	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6767	{
6768	/*
6769	* Parse the argument.
6770	*/
6771	unsigned iVerbosity = 1;
6772	if (pszArgs)
6773	{
6774	pszArgs = RTStrStripL(pszArgs);
6775	if (!strcmp(pszArgs, "terse"))
6776	iVerbosity--;
6777	else if (!strcmp(pszArgs, "verbose"))
6778	iVerbosity++;
6779	}
6780
6781	uint32_t uLeaf;
6782	CPUMCPUID Host;
6783	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6784	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6785	PCCPUMCPUIDLEAF pCurLeaf;
6786	PCCPUMCPUIDLEAF pNextLeaf;
6787	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6788	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6789	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6790
6791	/*
6792	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6793	*/
6794	uint32_t cHstMax = ASMCpuId_EAX(0);
6795	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6796	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6797	pHlp->pfnPrintf(pHlp,
6798	" Raw Standard CPUID Leaves\n"
6799	" Leaf/sub-leaf eax ebx ecx edx\n");
6800	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6801	{
6802	uint32_t cMaxSubLeaves = 1;
6803	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6804	cMaxSubLeaves = 16;
6805	else if (uLeaf == 0xd)
6806	cMaxSubLeaves = 128;
6807
6808	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6809	{
6810	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6811	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6812	&& pCurLeaf->uLeaf == uLeaf
6813	&& pCurLeaf->uSubLeaf == uSubLeaf)
6814	{
6815	pHlp->pfnPrintf(pHlp,
6816	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6817	"Hst: %08x %08x %08x %08x\n",
6818	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6819	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6820	pCurLeaf++;
6821	}
6822	else if ( uLeaf != 0xd
6823	\|\| uSubLeaf <= 1
6824	\|\| Host.uEbx != 0 )
6825	pHlp->pfnPrintf(pHlp,
6826	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6827	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6828
6829	/* Done? */
6830	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6831	\|\| pCurLeaf->uLeaf != uLeaf)
6832	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6833	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6834	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6835	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6836	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6837	)
6838	)
6839	break;
6840	}
6841	}
6842	pNextLeaf = pCurLeaf;
6843
6844	/*
6845	* If verbose, decode it.
6846	*/
6847	if (iVerbosity && paLeaves[0].uLeaf == 0)
6848	pHlp->pfnPrintf(pHlp,
6849	"%36s %.04s%.04s%.04s\n"
6850	"%36s 0x00000000-%#010x\n"
6851	,
6852	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6853	"Supports:", paLeaves[0].uEax);
6854
6855	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6856	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6857
6858	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6859	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6860
6861	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6862	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6863
6864	pCurLeaf = pNextLeaf;
6865
6866	/*
6867	* Hypervisor leaves.
6868	*
6869	* Unlike most of the other leaves reported, the guest hypervisor leaves
6870	* aren't a subset of the host CPUID bits.
6871	*/
6872	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6873
6874	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6875	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6876	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6877	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6878	cMax = RT_MAX(cHstMax, cGstMax);
6879	if (cMax >= UINT32_C(0x40000000))
6880	{
6881	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6882
6883	/** @todo dump these in more detail. */
6884
6885	pCurLeaf = pNextLeaf;
6886	}
6887
6888
6889	/*
6890	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6891	* Implemented after AMD specs.
6892	*/
6893	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6894
6895	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6896	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6897	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6898	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6899	cMax = RT_MAX(cHstMax, cGstMax);
6900	if (cMax >= UINT32_C(0x80000000))
6901	{
6902
6903	pHlp->pfnPrintf(pHlp,
6904	" Raw Extended CPUID Leaves\n"
6905	" Leaf/sub-leaf eax ebx ecx edx\n");
6906	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6907	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6908	{
6909	uint32_t cMaxSubLeaves = 1;
6910	if (uLeaf == UINT32_C(0x8000001d))
6911	cMaxSubLeaves = 16;
6912
6913	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6914	{
6915	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6916	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6917	&& pCurLeaf->uLeaf == uLeaf
6918	&& pCurLeaf->uSubLeaf == uSubLeaf)
6919	{
6920	pHlp->pfnPrintf(pHlp,
6921	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6922	"Hst: %08x %08x %08x %08x\n",
6923	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6924	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6925	pCurLeaf++;
6926	}
6927	else if ( uLeaf != 0xd
6928	\|\| uSubLeaf <= 1
6929	\|\| Host.uEbx != 0 )
6930	pHlp->pfnPrintf(pHlp,
6931	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6932	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6933
6934	/* Done? */
6935	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6936	\|\| pCurLeaf->uLeaf != uLeaf)
6937	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6938	break;
6939	}
6940	}
6941	pNextLeaf = pCurLeaf;
6942
6943	/*
6944	* Understandable output
6945	*/
6946	if (iVerbosity)
6947	pHlp->pfnPrintf(pHlp,
6948	"Ext Name: %.4s%.4s%.4s\n"
6949	"Ext Supports: 0x80000000-%#010x\n",
6950	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6951
6952	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6953	if (iVerbosity && pCurLeaf)
6954	{
6955	uint32_t uEAX = pCurLeaf->uEax;
6956	pHlp->pfnPrintf(pHlp,
6957	"Family: %d \tExtended: %d \tEffective: %d\n"
6958	"Model: %d \tExtended: %d \tEffective: %d\n"
6959	"Stepping: %d\n"
6960	"Brand ID: %#05x\n",
6961	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6962	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6963	ASMGetCpuStepping(uEAX),
6964	pCurLeaf->uEbx & 0xfff);
6965
6966	if (iVerbosity == 1)
6967	{
6968	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6969	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6970	}
6971	else
6972	{
6973	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6974	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6975	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6976	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6977	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6978	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
6979	{
6980	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
6981	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6982	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
6983	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
6984	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
6985	}
6986	}
6987	}
6988
6989	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6990	{
6991	char szString[443+1] = {0};
6992	uint32_t pu32 = (uint32_t )szString;
6993	*pu32++ = pCurLeaf->uEax;
6994	*pu32++ = pCurLeaf->uEbx;
6995	*pu32++ = pCurLeaf->uEcx;
6996	*pu32++ = pCurLeaf->uEdx;
6997	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6998	if (pCurLeaf)
6999	{
7000	*pu32++ = pCurLeaf->uEax;
7001	*pu32++ = pCurLeaf->uEbx;
7002	*pu32++ = pCurLeaf->uEcx;
7003	*pu32++ = pCurLeaf->uEdx;
7004	}
7005	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
7006	if (pCurLeaf)
7007	{
7008	*pu32++ = pCurLeaf->uEax;
7009	*pu32++ = pCurLeaf->uEbx;
7010	*pu32++ = pCurLeaf->uEcx;
7011	*pu32++ = pCurLeaf->uEdx;
7012	}
7013	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
7014	}
7015
7016	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
7017	{
7018	uint32_t uEAX = pCurLeaf->uEax;
7019	uint32_t uEBX = pCurLeaf->uEbx;
7020	uint32_t uECX = pCurLeaf->uEcx;
7021	uint32_t uEDX = pCurLeaf->uEdx;
7022	char sz1[32];
7023	char sz2[32];
7024
7025	pHlp->pfnPrintf(pHlp,
7026	"TLB 2/4M Instr/Uni: %s %3d entries\n"
7027	"TLB 2/4M Data: %s %3d entries\n",
7028	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
7029	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
7030	pHlp->pfnPrintf(pHlp,
7031	"TLB 4K Instr/Uni: %s %3d entries\n"
7032	"TLB 4K Data: %s %3d entries\n",
7033	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
7034	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
7035	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
7036	"L1 Instr Cache Lines Per Tag: %d\n"
7037	"L1 Instr Cache Associativity: %s\n"
7038	"L1 Instr Cache Size: %d KB\n",
7039	(uEDX >> 0) & 0xff,
7040	(uEDX >> 8) & 0xff,
7041	getCacheAss((uEDX >> 16) & 0xff, sz1),
7042	(uEDX >> 24) & 0xff);
7043	pHlp->pfnPrintf(pHlp,
7044	"L1 Data Cache Line Size: %d bytes\n"
7045	"L1 Data Cache Lines Per Tag: %d\n"
7046	"L1 Data Cache Associativity: %s\n"
7047	"L1 Data Cache Size: %d KB\n",
7048	(uECX >> 0) & 0xff,
7049	(uECX >> 8) & 0xff,
7050	getCacheAss((uECX >> 16) & 0xff, sz1),
7051	(uECX >> 24) & 0xff);
7052	}
7053
7054	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
7055	{
7056	uint32_t uEAX = pCurLeaf->uEax;
7057	uint32_t uEBX = pCurLeaf->uEbx;
7058	uint32_t uEDX = pCurLeaf->uEdx;
7059
7060	pHlp->pfnPrintf(pHlp,
7061	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
7062	"L2 TLB 2/4M Data: %s %4d entries\n",
7063	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
7064	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
7065	pHlp->pfnPrintf(pHlp,
7066	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
7067	"L2 TLB 4K Data: %s %4d entries\n",
7068	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
7069	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
7070	pHlp->pfnPrintf(pHlp,
7071	"L2 Cache Line Size: %d bytes\n"
7072	"L2 Cache Lines Per Tag: %d\n"
7073	"L2 Cache Associativity: %s\n"
7074	"L2 Cache Size: %d KB\n",
7075	(uEDX >> 0) & 0xff,
7076	(uEDX >> 8) & 0xf,
7077	getL2CacheAss((uEDX >> 12) & 0xf),
7078	(uEDX >> 16) & 0xffff);
7079	}
7080
7081	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
7082	{
7083	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7084	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
7085	{
7086	if (iVerbosity < 1)
7087	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
7088	else
7089	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
7090	}
7091	}
7092
7093	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
7094	if (pCurLeaf != NULL)
7095	{
7096	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7097	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
7098	{
7099	if (iVerbosity < 1)
7100	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
7101	else
7102	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
7103	}
7104
7105	if (iVerbosity)
7106	{
7107	uint32_t uEAX = pCurLeaf->uEax;
7108	uint32_t uECX = pCurLeaf->uEcx;
7109
7110	pHlp->pfnPrintf(pHlp,
7111	"Physical Address Width: %d bits\n"
7112	"Virtual Address Width: %d bits\n"
7113	"Guest Physical Address Width: %d bits\n",
7114	(uEAX >> 0) & 0xff,
7115	(uEAX >> 8) & 0xff,
7116	(uEAX >> 16) & 0xff);
7117	pHlp->pfnPrintf(pHlp,
7118	"Physical Core Count: %d\n",
7119	((uECX >> 0) & 0xff) + 1);
7120	}
7121	}
7122
7123	pCurLeaf = pNextLeaf;
7124	}
7125
7126
7127
7128	/*
7129	* Centaur.
7130	*/
7131	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7132
7133	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7134	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7135	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7136	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7137	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7138	cMax = RT_MAX(cHstMax, cGstMax);
7139	if (cMax >= UINT32_C(0xc0000000))
7140	{
7141	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7142
7143	/*
7144	* Understandable output
7145	*/
7146	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7147	pHlp->pfnPrintf(pHlp,
7148	"Centaur Supports: 0xc0000000-%#010x\n",
7149	pCurLeaf->uEax);
7150
7151	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7152	{
7153	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7154	uint32_t uEdxGst = pCurLeaf->uEdx;
7155	uint32_t uEdxHst = Host.uEdx;
7156
7157	if (iVerbosity == 1)
7158	{
7159	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7160	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7161	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7162	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7163	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7164	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7165	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7166	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7167	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7168	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7169	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7170	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7171	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7172	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7173	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7174	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7175	for (unsigned iBit = 14; iBit < 32; iBit++)
7176	if (uEdxGst & RT_BIT(iBit))
7177	pHlp->pfnPrintf(pHlp, " %d", iBit);
7178	pHlp->pfnPrintf(pHlp, "\n");
7179	}
7180	else
7181	{
7182	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7183	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7184	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7185	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7186	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7187	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7188	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7189	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7190	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7191	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7192	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7193	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7194	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7195	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7196	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7197	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7198	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7199	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7200	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7201	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7202	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7203	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7204	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7205	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7206	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7207	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7208	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7209	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7210	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7211	for (unsigned iBit = 27; iBit < 32; iBit++)
7212	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7213	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7214	pHlp->pfnPrintf(pHlp, "\n");
7215	}
7216	}
7217
7218	pCurLeaf = pNextLeaf;
7219	}
7220
7221	/*
7222	* The remainder.
7223	*/
7224	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7225	}
7226
7227	#endif /* !IN_VBOX_CPU_REPORT */
7228

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 82255

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