CPUMR3CpuId.cpp@ 81150

Last change on this file since 81150 was 80660, checked in by vboxsync, 5 years ago
VMM/CPUM: Nested VMX: bugref:9180 Ensure MSR_IA32_BASIC bit 48 (the VMX physical address width bit) is set/cleared properly to match whether the CPU is capable of 64-bit or not (also is a requirement for kvm-intel module to load in the guest).
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 333.0 KB

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1	/* $Id: CPUMR3CpuId.cpp 80660 2019-09-09 07:47:17Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vm.h>
30	#include <VBox/vmm/mm.h>
31	#include <VBox/sup.h>
32
33	#include <VBox/err.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/ctype.h>
36	#include <iprt/mem.h>
37	#include <iprt/string.h>
38
39
40	/*********************************************************************************************************************************
41	* Defined Constants And Macros *
42	*********************************************************************************************************************************/
43	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
44	#define CPUM_CPUID_MAX_LEAVES 2048
45	/* Max size we accept for the XSAVE area. */
46	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
47	/* Min size we accept for the XSAVE area. */
48	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
49
50
51	/*********************************************************************************************************************************
52	* Global Variables *
53	*********************************************************************************************************************************/
54	/**
55	* The intel pentium family.
56	*/
57	static const CPUMMICROARCH g_aenmIntelFamily06[] =
58	{
59	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
60	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
61	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
63	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
64	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
65	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
66	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
67	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
68	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
69	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
70	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
71	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
72	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
73	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
74	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
75	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
81	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
82	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
83	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [26(0x1a)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Nehalem-EP */
86	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
87	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
88	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
89	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
90	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
91	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
97	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
98	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
99	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
102	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
103	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
104	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
105	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
106	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
107	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
113	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
114	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
115	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
118	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
120	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
121	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
122	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
130	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
131	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
134	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
136	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
137	/* [78(0x4e)] = */ kCpumMicroarch_Intel_Core7_Skylake,
138	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Broadwell-E */
139	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu; skylake <= 4, cascade lake > 5 */
145	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
146	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
147	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
150	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
151	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
152	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
153	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
154	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
155	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
159	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
160	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
161	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
162	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
163	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
164	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
165	/[106(0x6a)] = / kCpumMicroarch_Intel_Unknown,
166	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
167	/[108(0x6c)] = / kCpumMicroarch_Intel_Unknown,
168	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
169	/[110(0x6e)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
170	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
171	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
172	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
173	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
174	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
175	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
176	/[117(0x75)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
177	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
178	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
179	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
180	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
181	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
182	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
183	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
184	/[125(0x7d)] = / kCpumMicroarch_Intel_Unknown,
185	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
186	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
187	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
188	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
189	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
190	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
191	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
192	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
193	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
194	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
195	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
196	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
197	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
198	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
199	/[140(0x8c)] = / kCpumMicroarch_Intel_Unknown,
200	/[141(0x8d)] = / kCpumMicroarch_Intel_Unknown,
201	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
202	/[143(0x8f)] = / kCpumMicroarch_Intel_Unknown,
203	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
204	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
205	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
206	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
207	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
208	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
209	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
210	/[151(0x97)] = / kCpumMicroarch_Intel_Unknown,
211	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
212	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
213	/[154(0x9a)] = / kCpumMicroarch_Intel_Unknown,
214	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
215	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
216	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
217	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
218	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
219	};
220	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0x9f+1);
221
222
223	/**
224	* Figures out the (sub-)micro architecture given a bit of CPUID info.
225	*
226	* @returns Micro architecture.
227	* @param enmVendor The CPU vendor .
228	* @param bFamily The CPU family.
229	* @param bModel The CPU model.
230	* @param bStepping The CPU stepping.
231	*/
232	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
233	uint8_t bModel, uint8_t bStepping)
234	{
235	if (enmVendor == CPUMCPUVENDOR_AMD)
236	{
237	switch (bFamily)
238	{
239	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
240	case 0x03: return kCpumMicroarch_AMD_Am386;
241	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
242	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
243	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
244	case 0x06:
245	switch (bModel)
246	{
247	case 0: return kCpumMicroarch_AMD_K7_Palomino;
248	case 1: return kCpumMicroarch_AMD_K7_Palomino;
249	case 2: return kCpumMicroarch_AMD_K7_Palomino;
250	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
251	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
252	case 6: return kCpumMicroarch_AMD_K7_Palomino;
253	case 7: return kCpumMicroarch_AMD_K7_Morgan;
254	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
255	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
256	}
257	return kCpumMicroarch_AMD_K7_Unknown;
258	case 0x0f:
259	/*
260	* This family is a friggin mess. Trying my best to make some
261	* sense out of it. Too much happened in the 0x0f family to
262	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
263	*
264	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
265	* cpu-world.com, and other places:
266	* - 130nm:
267	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
268	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
269	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
270	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
271	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
272	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
273	* - 90nm:
274	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
275	* - Oakville: 10FC0/DH-D0.
276	* - Georgetown: 10FC0/DH-D0.
277	* - Sonora: 10FC0/DH-D0.
278	* - Venus: 20F71/SH-E4
279	* - Troy: 20F51/SH-E4
280	* - Athens: 20F51/SH-E4
281	* - San Diego: 20F71/SH-E4.
282	* - Lancaster: 20F42/SH-E5
283	* - Newark: 20F42/SH-E5.
284	* - Albany: 20FC2/DH-E6.
285	* - Roma: 20FC2/DH-E6.
286	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
287	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
288	* - 90nm introducing Dual core:
289	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
290	* - Italy: 20F10/JH-E1, 20F12/JH-E6
291	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
292	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
293	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
294	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
295	* - Santa Ana: 40F32/JH-F2, /-F3
296	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
297	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
298	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
299	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
300	* - Keene: 40FC2/DH-F2.
301	* - Richmond: 40FC2/DH-F2
302	* - Taylor: 40F82/BH-F2
303	* - Trinidad: 40F82/BH-F2
304	*
305	* - 65nm:
306	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
307	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
308	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
309	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
310	* - Sherman: /-G1, 70FC2/DH-G2.
311	* - Huron: 70FF2/DH-G2.
312	*/
313	if (bModel < 0x10)
314	return kCpumMicroarch_AMD_K8_130nm;
315	if (bModel >= 0x60 && bModel < 0x80)
316	return kCpumMicroarch_AMD_K8_65nm;
317	if (bModel >= 0x40)
318	return kCpumMicroarch_AMD_K8_90nm_AMDV;
319	switch (bModel)
320	{
321	case 0x21:
322	case 0x23:
323	case 0x2b:
324	case 0x2f:
325	case 0x37:
326	case 0x3f:
327	return kCpumMicroarch_AMD_K8_90nm_DualCore;
328	}
329	return kCpumMicroarch_AMD_K8_90nm;
330	case 0x10:
331	return kCpumMicroarch_AMD_K10;
332	case 0x11:
333	return kCpumMicroarch_AMD_K10_Lion;
334	case 0x12:
335	return kCpumMicroarch_AMD_K10_Llano;
336	case 0x14:
337	return kCpumMicroarch_AMD_Bobcat;
338	case 0x15:
339	switch (bModel)
340	{
341	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
342	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
343	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
344	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
345	case 0x11: /* ?? */
346	case 0x12: /* ?? */
347	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
348	}
349	return kCpumMicroarch_AMD_15h_Unknown;
350	case 0x16:
351	return kCpumMicroarch_AMD_Jaguar;
352	case 0x17:
353	return kCpumMicroarch_AMD_Zen_Ryzen;
354	}
355	return kCpumMicroarch_AMD_Unknown;
356	}
357
358	if (enmVendor == CPUMCPUVENDOR_INTEL)
359	{
360	switch (bFamily)
361	{
362	case 3:
363	return kCpumMicroarch_Intel_80386;
364	case 4:
365	return kCpumMicroarch_Intel_80486;
366	case 5:
367	return kCpumMicroarch_Intel_P5;
368	case 6:
369	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
370	{
371	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
372	if (enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake)
373	{
374	if (bStepping >= 0xa && bStepping <= 0xc)
375	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
376	else if (bStepping >= 0xc)
377	enmMicroArch = kCpumMicroarch_Intel_Core7_WhiskeyLake;
378	}
379	else if ( enmMicroArch == kCpumMicroarch_Intel_Core7_Skylake
380	&& bModel == 0x55
381	&& bStepping >= 5)
382	enmMicroArch = kCpumMicroarch_Intel_Core7_CascadeLake;
383	return enmMicroArch;
384	}
385	return kCpumMicroarch_Intel_Atom_Unknown;
386	case 15:
387	switch (bModel)
388	{
389	case 0: return kCpumMicroarch_Intel_NB_Willamette;
390	case 1: return kCpumMicroarch_Intel_NB_Willamette;
391	case 2: return kCpumMicroarch_Intel_NB_Northwood;
392	case 3: return kCpumMicroarch_Intel_NB_Prescott;
393	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
394	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
395	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
396	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
397	default: return kCpumMicroarch_Intel_NB_Unknown;
398	}
399	break;
400	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
401	case 0:
402	return kCpumMicroarch_Intel_8086;
403	case 1:
404	return kCpumMicroarch_Intel_80186;
405	case 2:
406	return kCpumMicroarch_Intel_80286;
407	}
408	return kCpumMicroarch_Intel_Unknown;
409	}
410
411	if (enmVendor == CPUMCPUVENDOR_VIA)
412	{
413	switch (bFamily)
414	{
415	case 5:
416	switch (bModel)
417	{
418	case 1: return kCpumMicroarch_Centaur_C6;
419	case 4: return kCpumMicroarch_Centaur_C6;
420	case 8: return kCpumMicroarch_Centaur_C2;
421	case 9: return kCpumMicroarch_Centaur_C3;
422	}
423	break;
424
425	case 6:
426	switch (bModel)
427	{
428	case 5: return kCpumMicroarch_VIA_C3_M2;
429	case 6: return kCpumMicroarch_VIA_C3_C5A;
430	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
431	case 8: return kCpumMicroarch_VIA_C3_C5N;
432	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
433	case 10: return kCpumMicroarch_VIA_C7_C5J;
434	case 15: return kCpumMicroarch_VIA_Isaiah;
435	}
436	break;
437	}
438	return kCpumMicroarch_VIA_Unknown;
439	}
440
441	if (enmVendor == CPUMCPUVENDOR_SHANGHAI)
442	{
443	switch (bFamily)
444	{
445	case 6:
446	case 7:
447	return kCpumMicroarch_Shanghai_Wudaokou;
448	default:
449	break;
450	}
451	return kCpumMicroarch_Shanghai_Unknown;
452	}
453
454	if (enmVendor == CPUMCPUVENDOR_CYRIX)
455	{
456	switch (bFamily)
457	{
458	case 4:
459	switch (bModel)
460	{
461	case 9: return kCpumMicroarch_Cyrix_5x86;
462	}
463	break;
464
465	case 5:
466	switch (bModel)
467	{
468	case 2: return kCpumMicroarch_Cyrix_M1;
469	case 4: return kCpumMicroarch_Cyrix_MediaGX;
470	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
471	}
472	break;
473
474	case 6:
475	switch (bModel)
476	{
477	case 0: return kCpumMicroarch_Cyrix_M2;
478	}
479	break;
480
481	}
482	return kCpumMicroarch_Cyrix_Unknown;
483	}
484
485	return kCpumMicroarch_Unknown;
486	}
487
488
489	/**
490	* Translates a microarchitecture enum value to the corresponding string
491	* constant.
492	*
493	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
494	* NULL if the value is invalid.
495	*
496	* @param enmMicroarch The enum value to convert.
497	*/
498	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
499	{
500	switch (enmMicroarch)
501	{
502	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
503	CASE_RET_STR(kCpumMicroarch_Intel_8086);
504	CASE_RET_STR(kCpumMicroarch_Intel_80186);
505	CASE_RET_STR(kCpumMicroarch_Intel_80286);
506	CASE_RET_STR(kCpumMicroarch_Intel_80386);
507	CASE_RET_STR(kCpumMicroarch_Intel_80486);
508	CASE_RET_STR(kCpumMicroarch_Intel_P5);
509
510	CASE_RET_STR(kCpumMicroarch_Intel_P6);
511	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
512	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
513
514	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
515	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
516	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
517
518	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
519	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
520
521	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
522	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
523	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
524	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
525	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
526	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
527	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
528	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
529	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
530	CASE_RET_STR(kCpumMicroarch_Intel_Core7_WhiskeyLake);
531	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CascadeLake);
532	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
533	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
534	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
535
536	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
537	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
538	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
539	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
540	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
541	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
542	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
543	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
544
545	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
546	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
547	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
548	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
549	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
550
551	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
552	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
553	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
554	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
555	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
556	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
557	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
558
559	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
560
561	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
562	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
563	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
564	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
565	CASE_RET_STR(kCpumMicroarch_AMD_K5);
566	CASE_RET_STR(kCpumMicroarch_AMD_K6);
567
568	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
569	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
570	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
571	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
572	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
573	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
574	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
575
576	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
577	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
578	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
579	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
580	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
581
582	CASE_RET_STR(kCpumMicroarch_AMD_K10);
583	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
584	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
585	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
586	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
587
588	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
589	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
590	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
591	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
592	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
593
594	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
595
596	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
597
598	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
599
600	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
601	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
602	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
603	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
604	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
605	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
606	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
607	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
608	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
609	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
610	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
611	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
612	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
613
614	CASE_RET_STR(kCpumMicroarch_Shanghai_Wudaokou);
615	CASE_RET_STR(kCpumMicroarch_Shanghai_Unknown);
616
617	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
618	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
619	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
620	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
621	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
622	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
623
624	CASE_RET_STR(kCpumMicroarch_NEC_V20);
625	CASE_RET_STR(kCpumMicroarch_NEC_V30);
626
627	CASE_RET_STR(kCpumMicroarch_Unknown);
628
629	#undef CASE_RET_STR
630	case kCpumMicroarch_Invalid:
631	case kCpumMicroarch_Intel_End:
632	case kCpumMicroarch_Intel_Core2_End:
633	case kCpumMicroarch_Intel_Core7_End:
634	case kCpumMicroarch_Intel_Atom_End:
635	case kCpumMicroarch_Intel_P6_Core_Atom_End:
636	case kCpumMicroarch_Intel_Phi_End:
637	case kCpumMicroarch_Intel_NB_End:
638	case kCpumMicroarch_AMD_K7_End:
639	case kCpumMicroarch_AMD_K8_End:
640	case kCpumMicroarch_AMD_15h_End:
641	case kCpumMicroarch_AMD_16h_End:
642	case kCpumMicroarch_AMD_Zen_End:
643	case kCpumMicroarch_AMD_End:
644	case kCpumMicroarch_VIA_End:
645	case kCpumMicroarch_Cyrix_End:
646	case kCpumMicroarch_NEC_End:
647	case kCpumMicroarch_Shanghai_End:
648	case kCpumMicroarch_32BitHack:
649	break;
650	/* no default! */
651	}
652
653	return NULL;
654	}
655
656
657	/**
658	* Determins the host CPU MXCSR mask.
659	*
660	* @returns MXCSR mask.
661	*/
662	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
663	{
664	if ( ASMHasCpuId()
665	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
666	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
667	{
668	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
669	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
670	RT_ZERO(*pState);
671	ASMFxSave(pState);
672	if (pState->MXCSR_MASK == 0)
673	return 0xffbf;
674	return pState->MXCSR_MASK;
675	}
676	return 0;
677	}
678
679
680	/**
681	* Gets a matching leaf in the CPUID leaf array.
682	*
683	* @returns Pointer to the matching leaf, or NULL if not found.
684	* @param paLeaves The CPUID leaves to search. This is sorted.
685	* @param cLeaves The number of leaves in the array.
686	* @param uLeaf The leaf to locate.
687	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
688	*/
689	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
690	{
691	/* Lazy bird does linear lookup here since this is only used for the
692	occational CPUID overrides. */
693	for (uint32_t i = 0; i < cLeaves; i++)
694	if ( paLeaves[i].uLeaf == uLeaf
695	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
696	return &paLeaves[i];
697	return NULL;
698	}
699
700
701	#ifndef IN_VBOX_CPU_REPORT
702	/**
703	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
704	*
705	* @returns true if found, false it not.
706	* @param paLeaves The CPUID leaves to search. This is sorted.
707	* @param cLeaves The number of leaves in the array.
708	* @param uLeaf The leaf to locate.
709	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
710	* @param pLegacy The legacy output leaf.
711	*/
712	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
713	PCPUMCPUID pLegacy)
714	{
715	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
716	if (pLeaf)
717	{
718	pLegacy->uEax = pLeaf->uEax;
719	pLegacy->uEbx = pLeaf->uEbx;
720	pLegacy->uEcx = pLeaf->uEcx;
721	pLegacy->uEdx = pLeaf->uEdx;
722	return true;
723	}
724	return false;
725	}
726	#endif /* IN_VBOX_CPU_REPORT */
727
728
729	/**
730	* Ensures that the CPUID leaf array can hold one more leaf.
731	*
732	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
733	* failure.
734	* @param pVM The cross context VM structure. If NULL, use
735	* the process heap, otherwise the VM's hyper heap.
736	* @param ppaLeaves Pointer to the variable holding the array pointer
737	* (input/output).
738	* @param cLeaves The current array size.
739	*
740	* @remarks This function will automatically update the R0 and RC pointers when
741	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
742	* be the corresponding VM's CPUID arrays (which is asserted).
743	*/
744	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
745	{
746	/*
747	* If pVM is not specified, we're on the regular heap and can waste a
748	* little space to speed things up.
749	*/
750	uint32_t cAllocated;
751	if (!pVM)
752	{
753	cAllocated = RT_ALIGN(cLeaves, 16);
754	if (cLeaves + 1 > cAllocated)
755	{
756	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
757	if (pvNew)
758	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
759	else
760	{
761	RTMemFree(*ppaLeaves);
762	*ppaLeaves = NULL;
763	}
764	}
765	}
766	/*
767	* Otherwise, we're on the hyper heap and are probably just inserting
768	* one or two leaves and should conserve space.
769	*/
770	else
771	{
772	#ifdef IN_VBOX_CPU_REPORT
773	AssertReleaseFailed();
774	#else
775	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
776	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
777
778	size_t cb = cLeaves * sizeof(**ppaLeaves);
779	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
780	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
781	if (RT_SUCCESS(rc))
782	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
783	else
784	{
785	*ppaLeaves = NULL;
786	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
787	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
788	}
789	#endif
790	}
791	return *ppaLeaves;
792	}
793
794
795	/**
796	* Append a CPUID leaf or sub-leaf.
797	*
798	* ASSUMES linear insertion order, so we'll won't need to do any searching or
799	* replace anything. Use cpumR3CpuIdInsert() for those cases.
800	*
801	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
802	* the caller need do no more work.
803	* @param ppaLeaves Pointer to the pointer to the array of sorted
804	* CPUID leaves and sub-leaves.
805	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
806	* @param uLeaf The leaf we're adding.
807	* @param uSubLeaf The sub-leaf number.
808	* @param fSubLeafMask The sub-leaf mask.
809	* @param uEax The EAX value.
810	* @param uEbx The EBX value.
811	* @param uEcx The ECX value.
812	* @param uEdx The EDX value.
813	* @param fFlags The flags.
814	*/
815	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
816	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
817	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
818	{
819	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
820	return VERR_NO_MEMORY;
821
822	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
823	Assert( *pcLeaves == 0
824	\|\| pNew[-1].uLeaf < uLeaf
825	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
826
827	pNew->uLeaf = uLeaf;
828	pNew->uSubLeaf = uSubLeaf;
829	pNew->fSubLeafMask = fSubLeafMask;
830	pNew->uEax = uEax;
831	pNew->uEbx = uEbx;
832	pNew->uEcx = uEcx;
833	pNew->uEdx = uEdx;
834	pNew->fFlags = fFlags;
835
836	*pcLeaves += 1;
837	return VINF_SUCCESS;
838	}
839
840
841	/**
842	* Checks that we've updated the CPUID leaves array correctly.
843	*
844	* This is a no-op in non-strict builds.
845	*
846	* @param paLeaves The leaves array.
847	* @param cLeaves The number of leaves.
848	*/
849	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
850	{
851	#ifdef VBOX_STRICT
852	for (uint32_t i = 1; i < cLeaves; i++)
853	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
854	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
855	else
856	{
857	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
858	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
859	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
860	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
861	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
862	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
863	}
864	#else
865	NOREF(paLeaves);
866	NOREF(cLeaves);
867	#endif
868	}
869
870
871	/**
872	* Inserts a CPU ID leaf, replacing any existing ones.
873	*
874	* When inserting a simple leaf where we already got a series of sub-leaves with
875	* the same leaf number (eax), the simple leaf will replace the whole series.
876	*
877	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
878	* host-context heap and has only been allocated/reallocated by the
879	* cpumR3CpuIdEnsureSpace function.
880	*
881	* @returns VBox status code.
882	* @param pVM The cross context VM structure. If NULL, use
883	* the process heap, otherwise the VM's hyper heap.
884	* @param ppaLeaves Pointer to the pointer to the array of sorted
885	* CPUID leaves and sub-leaves. Must be NULL if using
886	* the hyper heap.
887	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
888	* be NULL if using the hyper heap.
889	* @param pNewLeaf Pointer to the data of the new leaf we're about to
890	* insert.
891	*/
892	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
893	{
894	/*
895	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
896	*/
897	if (pVM)
898	{
899	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
900	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
901
902	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
903	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
904	}
905
906	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
907	uint32_t cLeaves = *pcLeaves;
908
909	/*
910	* Validate the new leaf a little.
911	*/
912	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
913	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
914	VERR_INVALID_FLAGS);
915	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
916	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
917	VERR_INVALID_PARAMETER);
918	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
919	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
920	VERR_INVALID_PARAMETER);
921	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
922	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
923	VERR_INVALID_PARAMETER);
924
925	/*
926	* Find insertion point. The lazy bird uses the same excuse as in
927	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
928	*/
929	uint32_t i;
930	if ( cLeaves > 0
931	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
932	{
933	/* Add at end. */
934	i = cLeaves;
935	}
936	else if ( cLeaves > 0
937	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
938	{
939	/* Either replacing the last leaf or dealing with sub-leaves. Spool
940	back to the first sub-leaf to pretend we did the linear search. */
941	i = cLeaves - 1;
942	while ( i > 0
943	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
944	i--;
945	}
946	else
947	{
948	/* Linear search from the start. */
949	i = 0;
950	while ( i < cLeaves
951	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
952	i++;
953	}
954	if ( i < cLeaves
955	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
956	{
957	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
958	{
959	/*
960	* The sub-leaf mask differs, replace all existing leaves with the
961	* same leaf number.
962	*/
963	uint32_t c = 1;
964	while ( i + c < cLeaves
965	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
966	c++;
967	if (c > 1 && i + c < cLeaves)
968	{
969	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
970	*pcLeaves = cLeaves -= c - 1;
971	}
972
973	paLeaves[i] = *pNewLeaf;
974	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
975	return VINF_SUCCESS;
976	}
977
978	/* Find sub-leaf insertion point. */
979	while ( i < cLeaves
980	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
981	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
982	i++;
983
984	/*
985	* If we've got an exactly matching leaf, replace it.
986	*/
987	if ( i < cLeaves
988	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
989	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
990	{
991	paLeaves[i] = *pNewLeaf;
992	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
993	return VINF_SUCCESS;
994	}
995	}
996
997	/*
998	* Adding a new leaf at 'i'.
999	*/
1000	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
1001	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
1002	if (!paLeaves)
1003	return VERR_NO_MEMORY;
1004
1005	if (i < cLeaves)
1006	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
1007	*pcLeaves += 1;
1008	paLeaves[i] = *pNewLeaf;
1009
1010	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1011	return VINF_SUCCESS;
1012	}
1013
1014
1015	#ifndef IN_VBOX_CPU_REPORT
1016	/**
1017	* Removes a range of CPUID leaves.
1018	*
1019	* This will not reallocate the array.
1020	*
1021	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1022	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1023	* @param uFirst The first leaf.
1024	* @param uLast The last leaf.
1025	*/
1026	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1027	{
1028	uint32_t cLeaves = *pcLeaves;
1029
1030	Assert(uFirst <= uLast);
1031
1032	/*
1033	* Find the first one.
1034	*/
1035	uint32_t iFirst = 0;
1036	while ( iFirst < cLeaves
1037	&& paLeaves[iFirst].uLeaf < uFirst)
1038	iFirst++;
1039
1040	/*
1041	* Find the end (last + 1).
1042	*/
1043	uint32_t iEnd = iFirst;
1044	while ( iEnd < cLeaves
1045	&& paLeaves[iEnd].uLeaf <= uLast)
1046	iEnd++;
1047
1048	/*
1049	* Adjust the array if anything needs removing.
1050	*/
1051	if (iFirst < iEnd)
1052	{
1053	if (iEnd < cLeaves)
1054	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1055	*pcLeaves = cLeaves -= (iEnd - iFirst);
1056	}
1057
1058	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1059	}
1060	#endif /* IN_VBOX_CPU_REPORT */
1061
1062
1063	/**
1064	* Checks if ECX make a difference when reading a given CPUID leaf.
1065	*
1066	* @returns @c true if it does, @c false if it doesn't.
1067	* @param uLeaf The leaf we're reading.
1068	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1069	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1070	* final sub-leaf (for leaf 0xb only).
1071	*/
1072	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1073	{
1074	*pfFinalEcxUnchanged = false;
1075
1076	uint32_t auCur[4];
1077	uint32_t auPrev[4];
1078	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1079
1080	/* Look for sub-leaves. */
1081	uint32_t uSubLeaf = 1;
1082	for (;;)
1083	{
1084	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1085	if (memcmp(auCur, auPrev, sizeof(auCur)))
1086	break;
1087
1088	/* Advance / give up. */
1089	uSubLeaf++;
1090	if (uSubLeaf >= 64)
1091	{
1092	*pcSubLeaves = 1;
1093	return false;
1094	}
1095	}
1096
1097	/* Count sub-leaves. */
1098	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1099	uint32_t cRepeats = 0;
1100	uSubLeaf = 0;
1101	for (;;)
1102	{
1103	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1104
1105	/* Figuring out when to stop isn't entirely straight forward as we need
1106	to cover undocumented behavior up to a point and implementation shortcuts. */
1107
1108	/* 1. Look for more than 4 repeating value sets. */
1109	if ( auCur[0] == auPrev[0]
1110	&& auCur[1] == auPrev[1]
1111	&& ( auCur[2] == auPrev[2]
1112	\|\| ( auCur[2] == uSubLeaf
1113	&& auPrev[2] == uSubLeaf - 1) )
1114	&& auCur[3] == auPrev[3])
1115	{
1116	if ( uLeaf != 0xd
1117	\|\| uSubLeaf >= 64
1118	\|\| ( auCur[0] == 0
1119	&& auCur[1] == 0
1120	&& auCur[2] == 0
1121	&& auCur[3] == 0
1122	&& auPrev[2] == 0) )
1123	cRepeats++;
1124	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1125	break;
1126	}
1127	else
1128	cRepeats = 0;
1129
1130	/* 2. Look for zero values. */
1131	if ( auCur[0] == 0
1132	&& auCur[1] == 0
1133	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1134	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1135	&& uSubLeaf >= cMinLeaves)
1136	{
1137	cRepeats = 0;
1138	break;
1139	}
1140
1141	/* 3. Leaf 0xb level type 0 check. */
1142	if ( uLeaf == 0xb
1143	&& (auCur[2] & 0xff00) == 0
1144	&& (auPrev[2] & 0xff00) == 0)
1145	{
1146	cRepeats = 0;
1147	break;
1148	}
1149
1150	/* 99. Give up. */
1151	if (uSubLeaf >= 128)
1152	{
1153	#ifndef IN_VBOX_CPU_REPORT
1154	/* Ok, limit it according to the documentation if possible just to
1155	avoid annoying users with these detection issues. */
1156	uint32_t cDocLimit = UINT32_MAX;
1157	if (uLeaf == 0x4)
1158	cDocLimit = 4;
1159	else if (uLeaf == 0x7)
1160	cDocLimit = 1;
1161	else if (uLeaf == 0xd)
1162	cDocLimit = 63;
1163	else if (uLeaf == 0xf)
1164	cDocLimit = 2;
1165	if (cDocLimit != UINT32_MAX)
1166	{
1167	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1168	*pcSubLeaves = cDocLimit + 3;
1169	return true;
1170	}
1171	#endif
1172	*pcSubLeaves = UINT32_MAX;
1173	return true;
1174	}
1175
1176	/* Advance. */
1177	uSubLeaf++;
1178	memcpy(auPrev, auCur, sizeof(auCur));
1179	}
1180
1181	/* Standard exit. */
1182	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1183	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1184	if (*pcSubLeaves == 0)
1185	*pcSubLeaves = 1;
1186	return true;
1187	}
1188
1189
1190	/**
1191	* Gets a CPU ID leaf.
1192	*
1193	* @returns VBox status code.
1194	* @param pVM The cross context VM structure.
1195	* @param pLeaf Where to store the found leaf.
1196	* @param uLeaf The leaf to locate.
1197	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1198	*/
1199	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1200	{
1201	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1202	uLeaf, uSubLeaf);
1203	if (pcLeaf)
1204	{
1205	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1206	return VINF_SUCCESS;
1207	}
1208
1209	return VERR_NOT_FOUND;
1210	}
1211
1212
1213	/**
1214	* Inserts a CPU ID leaf, replacing any existing ones.
1215	*
1216	* @returns VBox status code.
1217	* @param pVM The cross context VM structure.
1218	* @param pNewLeaf Pointer to the leaf being inserted.
1219	*/
1220	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1221	{
1222	/*
1223	* Validate parameters.
1224	*/
1225	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1226	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1227
1228	/*
1229	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1230	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1231	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1232	*/
1233	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1234	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1235	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1236	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1237	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1238	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1239	{
1240	return VERR_NOT_SUPPORTED;
1241	}
1242
1243	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1244	}
1245
1246	/**
1247	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1248	*
1249	* @returns VBox status code.
1250	* @param ppaLeaves Where to return the array pointer on success.
1251	* Use RTMemFree to release.
1252	* @param pcLeaves Where to return the size of the array on
1253	* success.
1254	*/
1255	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1256	{
1257	*ppaLeaves = NULL;
1258	*pcLeaves = 0;
1259
1260	/*
1261	* Try out various candidates. This must be sorted!
1262	*/
1263	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1264	{
1265	{ UINT32_C(0x00000000), false },
1266	{ UINT32_C(0x10000000), false },
1267	{ UINT32_C(0x20000000), false },
1268	{ UINT32_C(0x30000000), false },
1269	{ UINT32_C(0x40000000), false },
1270	{ UINT32_C(0x50000000), false },
1271	{ UINT32_C(0x60000000), false },
1272	{ UINT32_C(0x70000000), false },
1273	{ UINT32_C(0x80000000), false },
1274	{ UINT32_C(0x80860000), false },
1275	{ UINT32_C(0x8ffffffe), true },
1276	{ UINT32_C(0x8fffffff), true },
1277	{ UINT32_C(0x90000000), false },
1278	{ UINT32_C(0xa0000000), false },
1279	{ UINT32_C(0xb0000000), false },
1280	{ UINT32_C(0xc0000000), false },
1281	{ UINT32_C(0xd0000000), false },
1282	{ UINT32_C(0xe0000000), false },
1283	{ UINT32_C(0xf0000000), false },
1284	};
1285
1286	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1287	{
1288	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1289	uint32_t uEax, uEbx, uEcx, uEdx;
1290	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1291
1292	/*
1293	* Does EAX look like a typical leaf count value?
1294	*/
1295	if ( uEax > uLeaf
1296	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1297	{
1298	/* Yes, dump them. */
1299	uint32_t cLeaves = uEax - uLeaf + 1;
1300	while (cLeaves-- > 0)
1301	{
1302	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1303
1304	uint32_t fFlags = 0;
1305
1306	/* There are currently three known leaves containing an APIC ID
1307	that needs EMT specific attention */
1308	if (uLeaf == 1)
1309	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1310	else if (uLeaf == 0xb && uEcx != 0)
1311	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1312	else if ( uLeaf == UINT32_C(0x8000001e)
1313	&& ( uEax
1314	\|\| uEbx
1315	\|\| uEdx
1316	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1317	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1318
1319	/* The APIC bit is per-VCpu and needs flagging. */
1320	if (uLeaf == 1)
1321	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1322	else if ( uLeaf == UINT32_C(0x80000001)
1323	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1324	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1325	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1326
1327	/* Check three times here to reduce the chance of CPU migration
1328	resulting in false positives with things like the APIC ID. */
1329	uint32_t cSubLeaves;
1330	bool fFinalEcxUnchanged;
1331	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1332	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1333	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1334	{
1335	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1336	{
1337	/* This shouldn't happen. But in case it does, file all
1338	relevant details in the release log. */
1339	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1340	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1341	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1342	{
1343	uint32_t auTmp[4];
1344	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1345	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1346	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1347	}
1348	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1349	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1350	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1351	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1352	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1353	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1354	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1355	}
1356
1357	if (fFinalEcxUnchanged)
1358	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1359
1360	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1361	{
1362	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1363	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1364	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1365	if (RT_FAILURE(rc))
1366	return rc;
1367	}
1368	}
1369	else
1370	{
1371	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1372	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1373	if (RT_FAILURE(rc))
1374	return rc;
1375	}
1376
1377	/* next */
1378	uLeaf++;
1379	}
1380	}
1381	/*
1382	* Special CPUIDs needs special handling as they don't follow the
1383	* leaf count principle used above.
1384	*/
1385	else if (s_aCandidates[iOuter].fSpecial)
1386	{
1387	bool fKeep = false;
1388	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1389	fKeep = true;
1390	else if ( uLeaf == 0x8fffffff
1391	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1392	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1393	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1394	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1395	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1396	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1397	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1398	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1399	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1400	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1401	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1402	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1403	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1404	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1405	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1406	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1407	fKeep = true;
1408	if (fKeep)
1409	{
1410	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1411	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1412	if (RT_FAILURE(rc))
1413	return rc;
1414	}
1415	}
1416	}
1417
1418	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1419	return VINF_SUCCESS;
1420	}
1421
1422
1423	/**
1424	* Determines the method the CPU uses to handle unknown CPUID leaves.
1425	*
1426	* @returns VBox status code.
1427	* @param penmUnknownMethod Where to return the method.
1428	* @param pDefUnknown Where to return default unknown values. This
1429	* will be set, even if the resulting method
1430	* doesn't actually needs it.
1431	*/
1432	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1433	{
1434	uint32_t uLastStd = ASMCpuId_EAX(0);
1435	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1436	if (!ASMIsValidExtRange(uLastExt))
1437	uLastExt = 0x80000000;
1438
1439	uint32_t auChecks[] =
1440	{
1441	uLastStd + 1,
1442	uLastStd + 5,
1443	uLastStd + 8,
1444	uLastStd + 32,
1445	uLastStd + 251,
1446	uLastExt + 1,
1447	uLastExt + 8,
1448	uLastExt + 15,
1449	uLastExt + 63,
1450	uLastExt + 255,
1451	0x7fbbffcc,
1452	0x833f7872,
1453	0xefff2353,
1454	0x35779456,
1455	0x1ef6d33e,
1456	};
1457
1458	static const uint32_t s_auValues[] =
1459	{
1460	0xa95d2156,
1461	0x00000001,
1462	0x00000002,
1463	0x00000008,
1464	0x00000000,
1465	0x55773399,
1466	0x93401769,
1467	0x12039587,
1468	};
1469
1470	/*
1471	* Simple method, all zeros.
1472	*/
1473	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1474	pDefUnknown->uEax = 0;
1475	pDefUnknown->uEbx = 0;
1476	pDefUnknown->uEcx = 0;
1477	pDefUnknown->uEdx = 0;
1478
1479	/*
1480	* Intel has been observed returning the last standard leaf.
1481	*/
1482	uint32_t auLast[4];
1483	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1484
1485	uint32_t cChecks = RT_ELEMENTS(auChecks);
1486	while (cChecks > 0)
1487	{
1488	uint32_t auCur[4];
1489	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1490	if (memcmp(auCur, auLast, sizeof(auCur)))
1491	break;
1492	cChecks--;
1493	}
1494	if (cChecks == 0)
1495	{
1496	/* Now, what happens when the input changes? Esp. ECX. */
1497	uint32_t cTotal = 0;
1498	uint32_t cSame = 0;
1499	uint32_t cLastWithEcx = 0;
1500	uint32_t cNeither = 0;
1501	uint32_t cValues = RT_ELEMENTS(s_auValues);
1502	while (cValues > 0)
1503	{
1504	uint32_t uValue = s_auValues[cValues - 1];
1505	uint32_t auLastWithEcx[4];
1506	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1507	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1508
1509	cChecks = RT_ELEMENTS(auChecks);
1510	while (cChecks > 0)
1511	{
1512	uint32_t auCur[4];
1513	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1514	if (!memcmp(auCur, auLast, sizeof(auCur)))
1515	{
1516	cSame++;
1517	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1518	cLastWithEcx++;
1519	}
1520	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1521	cLastWithEcx++;
1522	else
1523	cNeither++;
1524	cTotal++;
1525	cChecks--;
1526	}
1527	cValues--;
1528	}
1529
1530	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1531	if (cSame == cTotal)
1532	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1533	else if (cLastWithEcx == cTotal)
1534	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1535	else
1536	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1537	pDefUnknown->uEax = auLast[0];
1538	pDefUnknown->uEbx = auLast[1];
1539	pDefUnknown->uEcx = auLast[2];
1540	pDefUnknown->uEdx = auLast[3];
1541	return VINF_SUCCESS;
1542	}
1543
1544	/*
1545	* Unchanged register values?
1546	*/
1547	cChecks = RT_ELEMENTS(auChecks);
1548	while (cChecks > 0)
1549	{
1550	uint32_t const uLeaf = auChecks[cChecks - 1];
1551	uint32_t cValues = RT_ELEMENTS(s_auValues);
1552	while (cValues > 0)
1553	{
1554	uint32_t uValue = s_auValues[cValues - 1];
1555	uint32_t auCur[4];
1556	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1557	if ( auCur[0] != uLeaf
1558	\|\| auCur[1] != uValue
1559	\|\| auCur[2] != uValue
1560	\|\| auCur[3] != uValue)
1561	break;
1562	cValues--;
1563	}
1564	if (cValues != 0)
1565	break;
1566	cChecks--;
1567	}
1568	if (cChecks == 0)
1569	{
1570	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1571	return VINF_SUCCESS;
1572	}
1573
1574	/*
1575	* Just go with the simple method.
1576	*/
1577	return VINF_SUCCESS;
1578	}
1579
1580
1581	/**
1582	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1583	*
1584	* @returns Read only name string.
1585	* @param enmUnknownMethod The method to translate.
1586	*/
1587	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1588	{
1589	switch (enmUnknownMethod)
1590	{
1591	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1592	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1593	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1594	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1595
1596	case CPUMUNKNOWNCPUID_INVALID:
1597	case CPUMUNKNOWNCPUID_END:
1598	case CPUMUNKNOWNCPUID_32BIT_HACK:
1599	break;
1600	}
1601	return "Invalid-unknown-CPUID-method";
1602	}
1603
1604
1605	/**
1606	* Detect the CPU vendor give n the
1607	*
1608	* @returns The vendor.
1609	* @param uEAX EAX from CPUID(0).
1610	* @param uEBX EBX from CPUID(0).
1611	* @param uECX ECX from CPUID(0).
1612	* @param uEDX EDX from CPUID(0).
1613	*/
1614	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1615	{
1616	if (ASMIsValidStdRange(uEAX))
1617	{
1618	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1619	return CPUMCPUVENDOR_AMD;
1620
1621	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1622	return CPUMCPUVENDOR_INTEL;
1623
1624	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1625	return CPUMCPUVENDOR_VIA;
1626
1627	if (ASMIsShanghaiCpuEx(uEBX, uECX, uEDX))
1628	return CPUMCPUVENDOR_SHANGHAI;
1629
1630	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1631	&& uECX == UINT32_C(0x64616574)
1632	&& uEDX == UINT32_C(0x736E4978))
1633	return CPUMCPUVENDOR_CYRIX;
1634
1635	/* "Geode by NSC", example: family 5, model 9. */
1636
1637	/** @todo detect the other buggers... */
1638	}
1639
1640	return CPUMCPUVENDOR_UNKNOWN;
1641	}
1642
1643
1644	/**
1645	* Translates a CPU vendor enum value into the corresponding string constant.
1646	*
1647	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1648	* value name. This can be useful when generating code.
1649	*
1650	* @returns Read only name string.
1651	* @param enmVendor The CPU vendor value.
1652	*/
1653	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1654	{
1655	switch (enmVendor)
1656	{
1657	case CPUMCPUVENDOR_INTEL: return "INTEL";
1658	case CPUMCPUVENDOR_AMD: return "AMD";
1659	case CPUMCPUVENDOR_VIA: return "VIA";
1660	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1661	case CPUMCPUVENDOR_SHANGHAI: return "SHANGHAI";
1662	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1663
1664	case CPUMCPUVENDOR_INVALID:
1665	case CPUMCPUVENDOR_32BIT_HACK:
1666	break;
1667	}
1668	return "Invalid-cpu-vendor";
1669	}
1670
1671
1672	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1673	{
1674	/* Could do binary search, doing linear now because I'm lazy. */
1675	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1676	while (cLeaves-- > 0)
1677	{
1678	if (pLeaf->uLeaf == uLeaf)
1679	return pLeaf;
1680	pLeaf++;
1681	}
1682	return NULL;
1683	}
1684
1685
1686	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1687	{
1688	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1689	if ( !pLeaf
1690	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1691	return pLeaf;
1692
1693	/* Linear sub-leaf search. Lazy as usual. */
1694	cLeaves -= pLeaf - paLeaves;
1695	while ( cLeaves-- > 0
1696	&& pLeaf->uLeaf == uLeaf)
1697	{
1698	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1699	return pLeaf;
1700	pLeaf++;
1701	}
1702
1703	return NULL;
1704	}
1705
1706
1707	static void cpumR3ExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, PCPUMFEATURES pFeatures)
1708	{
1709	Assert(pVmxMsrs);
1710	Assert(pFeatures);
1711	Assert(pFeatures->fVmx);
1712
1713	/* Basic information. */
1714	{
1715	uint64_t const u64Basic = pVmxMsrs->u64Basic;
1716	pFeatures->fVmxInsOutInfo = RT_BF_GET(u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1717	}
1718
1719	/* Pin-based VM-execution controls. */
1720	{
1721	uint32_t const fPinCtls = pVmxMsrs->PinCtls.n.allowed1;
1722	pFeatures->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1723	pFeatures->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1724	pFeatures->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1725	pFeatures->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1726	pFeatures->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1727	}
1728
1729	/* Processor-based VM-execution controls. */
1730	{
1731	uint32_t const fProcCtls = pVmxMsrs->ProcCtls.n.allowed1;
1732	pFeatures->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1733	pFeatures->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1734	pFeatures->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1735	pFeatures->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1736	pFeatures->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1737	pFeatures->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1738	pFeatures->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1739	pFeatures->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1740	pFeatures->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1741	pFeatures->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1742	pFeatures->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1743	pFeatures->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1744	pFeatures->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1745	pFeatures->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1746	pFeatures->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1747	pFeatures->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1748	pFeatures->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1749	pFeatures->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1750	pFeatures->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1751	pFeatures->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1752	pFeatures->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1753	}
1754
1755	/* Secondary processor-based VM-execution controls. */
1756	{
1757	uint32_t const fProcCtls2 = pFeatures->fVmxSecondaryExecCtls ? pVmxMsrs->ProcCtls2.n.allowed1 : 0;
1758	pFeatures->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1759	pFeatures->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1760	pFeatures->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1761	pFeatures->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1762	pFeatures->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1763	pFeatures->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1764	pFeatures->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1765	pFeatures->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1766	pFeatures->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1767	pFeatures->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1768	pFeatures->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1769	pFeatures->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1770	pFeatures->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1771	pFeatures->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1772	pFeatures->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1773	pFeatures->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1774	pFeatures->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1775	pFeatures->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_VE);
1776	pFeatures->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1777	pFeatures->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1778	}
1779
1780	/* VM-exit controls. */
1781	{
1782	uint32_t const fExitCtls = pVmxMsrs->ExitCtls.n.allowed1;
1783	pFeatures->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1784	pFeatures->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1785	pFeatures->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1786	pFeatures->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1787	pFeatures->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1788	pFeatures->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1789	pFeatures->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1790	pFeatures->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1791	}
1792
1793	/* VM-entry controls. */
1794	{
1795	uint32_t const fEntryCtls = pVmxMsrs->EntryCtls.n.allowed1;
1796	pFeatures->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1797	pFeatures->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1798	pFeatures->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1799	pFeatures->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1800	}
1801
1802	/* Miscellaneous data. */
1803	{
1804	uint32_t const fMiscData = pVmxMsrs->u64Misc;
1805	pFeatures->fVmxExitSaveEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_SAVE_EFER_LMA);
1806	pFeatures->fVmxIntelPt = RT_BOOL(fMiscData & VMX_MISC_INTEL_PT);
1807	pFeatures->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1808	pFeatures->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1809	}
1810	}
1811
1812
1813	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures)
1814	{
1815	Assert(pMsrs);
1816	RT_ZERO(*pFeatures);
1817	if (cLeaves >= 2)
1818	{
1819	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1820	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1821	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1822	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1823	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1824	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1825
1826	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1827	pStd0Leaf->uEbx,
1828	pStd0Leaf->uEcx,
1829	pStd0Leaf->uEdx);
1830	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1831	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1832	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1833	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1834	pFeatures->uFamily,
1835	pFeatures->uModel,
1836	pFeatures->uStepping);
1837
1838	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1839	if (pExtLeaf8)
1840	{
1841	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1842	pFeatures->cMaxLinearAddrWidth = (pExtLeaf8->uEax >> 8) & 0xff;
1843	}
1844	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1845	{
1846	pFeatures->cMaxPhysAddrWidth = 36;
1847	pFeatures->cMaxLinearAddrWidth = 36;
1848	}
1849	else
1850	{
1851	pFeatures->cMaxPhysAddrWidth = 32;
1852	pFeatures->cMaxLinearAddrWidth = 32;
1853	}
1854
1855	/* Standard features. */
1856	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1857	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1858	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1859	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1860	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1861	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1862	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1863	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1864	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1865	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1866	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1867	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1868	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1869	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1870	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1871	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1872	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1873	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1874	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1875	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1876	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1877	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1878	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1879	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1880	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1881	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1882	if (pFeatures->fVmx)
1883	cpumR3ExplodeVmxFeatures(&pMsrs->hwvirt.vmx, pFeatures);
1884
1885	/* Structured extended features. */
1886	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1887	if (pSxfLeaf0)
1888	{
1889	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1890	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1891	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1892	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1893	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1894
1895	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1896	pFeatures->fIbrs = pFeatures->fIbpb;
1897	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1898	pFeatures->fFlushCmd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
1899	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1900	pFeatures->fMdsClear = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR);
1901	}
1902
1903	/* MWAIT/MONITOR leaf. */
1904	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1905	if (pMWaitLeaf)
1906	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1907	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1908
1909	/* Extended features. */
1910	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1911	if (pExtLeaf)
1912	{
1913	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1914	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1915	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1916	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1917	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1918	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1919	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1920	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1921	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1922	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1923	}
1924
1925	/* VMX (VMXON, VMCS region and related data structures) physical address width (depends on long-mode). */
1926	pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
1927
1928	if ( pExtLeaf
1929	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1930	{
1931	/* AMD features. */
1932	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1933	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1934	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1935	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1936	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1937	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1938	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1939	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1940	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1941	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1942	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1943	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1944	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1945	if (pFeatures->fSvm)
1946	{
1947	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1948	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1949	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1950	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1951	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1952	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1953	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1954	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1955	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1956	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1957	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1958	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1959	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1960	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1961	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1962	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1963	}
1964	}
1965
1966	/*
1967	* Quirks.
1968	*/
1969	pFeatures->fLeakyFxSR = pExtLeaf
1970	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1971	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1972	&& pFeatures->uFamily >= 6 /* K7 and up */;
1973
1974	/*
1975	* Max extended (/FPU) state.
1976	*/
1977	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1978	if (pFeatures->fXSaveRstor)
1979	{
1980	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1981	if (pXStateLeaf0)
1982	{
1983	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1984	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1985	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1986	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1987	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1988	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1989	{
1990	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1991
1992	/* (paranoia:) */
1993	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1994	if ( pXStateLeaf1
1995	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1996	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1997	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1998	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
1999	}
2000	else
2001	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
2002	pFeatures->fXSaveRstor = 0);
2003	}
2004	else
2005	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
2006	pFeatures->fXSaveRstor = 0);
2007	}
2008	}
2009	else
2010	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
2011	return VINF_SUCCESS;
2012	}
2013
2014
2015	/*
2016	*
2017	* Init related code.
2018	* Init related code.
2019	* Init related code.
2020	*
2021	*
2022	*/
2023	#ifndef IN_VBOX_CPU_REPORT
2024
2025
2026	/**
2027	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
2028	*
2029	* This ignores the fSubLeafMask.
2030	*
2031	* @returns Pointer to the matching leaf, or NULL if not found.
2032	* @param pCpum The CPUM instance data.
2033	* @param uLeaf The leaf to locate.
2034	* @param uSubLeaf The subleaf to locate.
2035	*/
2036	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
2037	{
2038	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
2039	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
2040	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
2041	if (iEnd)
2042	{
2043	uint32_t iBegin = 0;
2044	for (;;)
2045	{
2046	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
2047	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
2048	if (uNeedle < uCur)
2049	{
2050	if (i > iBegin)
2051	iEnd = i;
2052	else
2053	break;
2054	}
2055	else if (uNeedle > uCur)
2056	{
2057	if (i + 1 < iEnd)
2058	iBegin = i + 1;
2059	else
2060	break;
2061	}
2062	else
2063	return &paLeaves[i];
2064	}
2065	}
2066	return NULL;
2067	}
2068
2069
2070	/**
2071	* Loads MSR range overrides.
2072	*
2073	* This must be called before the MSR ranges are moved from the normal heap to
2074	* the hyper heap!
2075	*
2076	* @returns VBox status code (VMSetError called).
2077	* @param pVM The cross context VM structure.
2078	* @param pMsrNode The CFGM node with the MSR overrides.
2079	*/
2080	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
2081	{
2082	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2083	{
2084	/*
2085	* Assemble a valid MSR range.
2086	*/
2087	CPUMMSRRANGE MsrRange;
2088	MsrRange.offCpumCpu = 0;
2089	MsrRange.fReserved = 0;
2090
2091	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
2092	if (RT_FAILURE(rc))
2093	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
2094
2095	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
2096	if (RT_FAILURE(rc))
2097	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
2098	MsrRange.szName, rc);
2099
2100	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
2101	if (RT_FAILURE(rc))
2102	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
2103	MsrRange.szName, rc);
2104
2105	char szType[32];
2106	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
2107	if (RT_FAILURE(rc))
2108	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
2109	MsrRange.szName, rc);
2110	if (!RTStrICmp(szType, "FixedValue"))
2111	{
2112	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
2113	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
2114
2115	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
2116	if (RT_FAILURE(rc))
2117	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
2118	MsrRange.szName, rc);
2119
2120	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
2121	if (RT_FAILURE(rc))
2122	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
2123	MsrRange.szName, rc);
2124
2125	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
2126	if (RT_FAILURE(rc))
2127	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
2128	MsrRange.szName, rc);
2129	}
2130	else
2131	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
2132	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
2133
2134	/*
2135	* Insert the range into the table (replaces/splits/shrinks existing
2136	* MSR ranges).
2137	*/
2138	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
2139	&MsrRange);
2140	if (RT_FAILURE(rc))
2141	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
2142	}
2143
2144	return VINF_SUCCESS;
2145	}
2146
2147
2148	/**
2149	* Loads CPUID leaf overrides.
2150	*
2151	* This must be called before the CPUID leaves are moved from the normal
2152	* heap to the hyper heap!
2153	*
2154	* @returns VBox status code (VMSetError called).
2155	* @param pVM The cross context VM structure.
2156	* @param pParentNode The CFGM node with the CPUID leaves.
2157	* @param pszLabel How to label the overrides we're loading.
2158	*/
2159	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2160	{
2161	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2162	{
2163	/*
2164	* Get the leaf and subleaf numbers.
2165	*/
2166	char szName[128];
2167	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2168	if (RT_FAILURE(rc))
2169	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2170
2171	/* The leaf number is either specified directly or thru the node name. */
2172	uint32_t uLeaf;
2173	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2174	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2175	{
2176	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2177	if (rc != VINF_SUCCESS)
2178	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2179	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2180	}
2181	else if (RT_FAILURE(rc))
2182	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2183	pszLabel, szName, rc);
2184
2185	uint32_t uSubLeaf;
2186	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2187	if (RT_FAILURE(rc))
2188	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2189	pszLabel, szName, rc);
2190
2191	uint32_t fSubLeafMask;
2192	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2193	if (RT_FAILURE(rc))
2194	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2195	pszLabel, szName, rc);
2196
2197	/*
2198	* Look up the specified leaf, since the output register values
2199	* defaults to any existing values. This allows overriding a single
2200	* register, without needing to know the other values.
2201	*/
2202	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2203	CPUMCPUIDLEAF Leaf;
2204	if (pLeaf)
2205	Leaf = *pLeaf;
2206	else
2207	RT_ZERO(Leaf);
2208	Leaf.uLeaf = uLeaf;
2209	Leaf.uSubLeaf = uSubLeaf;
2210	Leaf.fSubLeafMask = fSubLeafMask;
2211
2212	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2213	if (RT_FAILURE(rc))
2214	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2215	pszLabel, szName, rc);
2216	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2217	if (RT_FAILURE(rc))
2218	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2219	pszLabel, szName, rc);
2220	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2221	if (RT_FAILURE(rc))
2222	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2223	pszLabel, szName, rc);
2224	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2225	if (RT_FAILURE(rc))
2226	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2227	pszLabel, szName, rc);
2228
2229	/*
2230	* Insert the leaf into the table (replaces existing ones).
2231	*/
2232	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2233	&Leaf);
2234	if (RT_FAILURE(rc))
2235	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2236	}
2237
2238	return VINF_SUCCESS;
2239	}
2240
2241
2242
2243	/**
2244	* Fetches overrides for a CPUID leaf.
2245	*
2246	* @returns VBox status code.
2247	* @param pLeaf The leaf to load the overrides into.
2248	* @param pCfgNode The CFGM node containing the overrides
2249	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2250	* @param iLeaf The CPUID leaf number.
2251	*/
2252	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2253	{
2254	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2255	if (pLeafNode)
2256	{
2257	uint32_t u32;
2258	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2259	if (RT_SUCCESS(rc))
2260	pLeaf->uEax = u32;
2261	else
2262	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2263
2264	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2265	if (RT_SUCCESS(rc))
2266	pLeaf->uEbx = u32;
2267	else
2268	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2269
2270	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2271	if (RT_SUCCESS(rc))
2272	pLeaf->uEcx = u32;
2273	else
2274	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2275
2276	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2277	if (RT_SUCCESS(rc))
2278	pLeaf->uEdx = u32;
2279	else
2280	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2281
2282	}
2283	return VINF_SUCCESS;
2284	}
2285
2286
2287	/**
2288	* Load the overrides for a set of CPUID leaves.
2289	*
2290	* @returns VBox status code.
2291	* @param paLeaves The leaf array.
2292	* @param cLeaves The number of leaves.
2293	* @param uStart The start leaf number.
2294	* @param pCfgNode The CFGM node containing the overrides
2295	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2296	*/
2297	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2298	{
2299	for (uint32_t i = 0; i < cLeaves; i++)
2300	{
2301	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2302	if (RT_FAILURE(rc))
2303	return rc;
2304	}
2305
2306	return VINF_SUCCESS;
2307	}
2308
2309
2310	/**
2311	* Installs the CPUID leaves and explods the data into structures like
2312	* GuestFeatures and CPUMCTX::aoffXState.
2313	*
2314	* @returns VBox status code.
2315	* @param pVM The cross context VM structure.
2316	* @param pCpum The CPUM part of @a VM.
2317	* @param paLeaves The leaves. These will be copied (but not freed).
2318	* @param cLeaves The number of leaves.
2319	* @param pMsrs The MSRs.
2320	*/
2321	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
2322	{
2323	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2324
2325	/*
2326	* Install the CPUID information.
2327	*/
2328	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2329	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2330
2331	AssertLogRelRCReturn(rc, rc);
2332	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2333	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2334	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2335
2336	/*
2337	* Update the default CPUID leaf if necessary.
2338	*/
2339	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2340	{
2341	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2342	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2343	{
2344	/* We don't use CPUID(0).eax here because of the NT hack that only
2345	changes that value without actually removing any leaves. */
2346	uint32_t i = 0;
2347	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2348	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2349	{
2350	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2351	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2352	i++;
2353	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2354	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2355	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2356	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2357	}
2358	break;
2359	}
2360	default:
2361	break;
2362	}
2363
2364	/*
2365	* Explode the guest CPU features.
2366	*/
2367	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
2368	&pCpum->GuestFeatures);
2369	AssertLogRelRCReturn(rc, rc);
2370
2371	/*
2372	* Adjust the scalable bus frequency according to the CPUID information
2373	* we're now using.
2374	*/
2375	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2376	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2377	? UINT64_C(100000000) /* 100MHz */
2378	: UINT64_C(133333333); /* 133MHz */
2379
2380	/*
2381	* Populate the legacy arrays. Currently used for everything, later only
2382	* for patch manager.
2383	*/
2384	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2385	{
2386	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2387	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2388	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2389	};
2390	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2391	{
2392	uint32_t cLeft = aOldRanges[i].cCpuIds;
2393	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2394	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2395	while (cLeft-- > 0)
2396	{
2397	uLeaf--;
2398	pLegacyLeaf--;
2399
2400	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2401	if (pLeaf)
2402	{
2403	pLegacyLeaf->uEax = pLeaf->uEax;
2404	pLegacyLeaf->uEbx = pLeaf->uEbx;
2405	pLegacyLeaf->uEcx = pLeaf->uEcx;
2406	pLegacyLeaf->uEdx = pLeaf->uEdx;
2407	}
2408	else
2409	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2410	}
2411	}
2412
2413	/*
2414	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2415	*/
2416	PVMCPU pVCpu0 = pVM->apCpusR3[0];
2417	memset(&pVCpu0->cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2418	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2419	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2420	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2421	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2422	{
2423	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2424	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2425	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2426	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2427	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2428	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2429	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2430	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2431	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2432	pCpum->GuestFeatures.cbMaxExtendedState),
2433	VERR_CPUM_IPE_1);
2434	pVCpu0->cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2435	}
2436
2437	/* Copy the CPU #0 data to the other CPUs. */
2438	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
2439	{
2440	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2441	memcpy(&pVCpu->cpum.s.Guest.aoffXState[0], &pVCpu0->cpum.s.Guest.aoffXState[0], sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2442	}
2443
2444	return VINF_SUCCESS;
2445	}
2446
2447
2448	/** @name Instruction Set Extension Options
2449	* @{ */
2450	/** Configuration option type (extended boolean, really). */
2451	typedef uint8_t CPUMISAEXTCFG;
2452	/** Always disable the extension. */
2453	#define CPUMISAEXTCFG_DISABLED false
2454	/** Enable the extension if it's supported by the host CPU. */
2455	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2456	/** Enable the extension if it's supported by the host CPU, but don't let
2457	* the portable CPUID feature disable it. */
2458	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2459	/** Always enable the extension. */
2460	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2461	/** @} */
2462
2463	/**
2464	* CPUID Configuration (from CFGM).
2465	*
2466	* @remarks The members aren't document since we would only be duplicating the
2467	* \@cfgm entries in cpumR3CpuIdReadConfig.
2468	*/
2469	typedef struct CPUMCPUIDCONFIG
2470	{
2471	bool fNt4LeafLimit;
2472	bool fInvariantTsc;
2473	bool fForceVme;
2474	bool fNestedHWVirt;
2475
2476	CPUMISAEXTCFG enmCmpXchg16b;
2477	CPUMISAEXTCFG enmMonitor;
2478	CPUMISAEXTCFG enmMWaitExtensions;
2479	CPUMISAEXTCFG enmSse41;
2480	CPUMISAEXTCFG enmSse42;
2481	CPUMISAEXTCFG enmAvx;
2482	CPUMISAEXTCFG enmAvx2;
2483	CPUMISAEXTCFG enmXSave;
2484	CPUMISAEXTCFG enmAesNi;
2485	CPUMISAEXTCFG enmPClMul;
2486	CPUMISAEXTCFG enmPopCnt;
2487	CPUMISAEXTCFG enmMovBe;
2488	CPUMISAEXTCFG enmRdRand;
2489	CPUMISAEXTCFG enmRdSeed;
2490	CPUMISAEXTCFG enmCLFlushOpt;
2491	CPUMISAEXTCFG enmFsGsBase;
2492	CPUMISAEXTCFG enmPcid;
2493	CPUMISAEXTCFG enmInvpcid;
2494	CPUMISAEXTCFG enmFlushCmdMsr;
2495	CPUMISAEXTCFG enmMdsClear;
2496	CPUMISAEXTCFG enmArchCapMsr;
2497
2498	CPUMISAEXTCFG enmAbm;
2499	CPUMISAEXTCFG enmSse4A;
2500	CPUMISAEXTCFG enmMisAlnSse;
2501	CPUMISAEXTCFG enm3dNowPrf;
2502	CPUMISAEXTCFG enmAmdExtMmx;
2503
2504	uint32_t uMaxStdLeaf;
2505	uint32_t uMaxExtLeaf;
2506	uint32_t uMaxCentaurLeaf;
2507	uint32_t uMaxIntelFamilyModelStep;
2508	char szCpuName[128];
2509	} CPUMCPUIDCONFIG;
2510	/** Pointer to CPUID config (from CFGM). */
2511	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2512
2513
2514	/**
2515	* Mini CPU selection support for making Mac OS X happy.
2516	*
2517	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2518	*
2519	* @param pCpum The CPUM instance data.
2520	* @param pConfig The CPUID configuration we've read from CFGM.
2521	*/
2522	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2523	{
2524	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2525	{
2526	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2527	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2528	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2529	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2530	0);
2531	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2532	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2533	{
2534	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2535	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2536	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2537	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2538	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2539	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2540	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2541	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2542	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2543	pStdFeatureLeaf->uEax = uNew;
2544	}
2545	}
2546	}
2547
2548
2549
2550	/**
2551	* Limit it the number of entries, zapping the remainder.
2552	*
2553	* The limits are masking off stuff about power saving and similar, this
2554	* is perhaps a bit crudely done as there is probably some relatively harmless
2555	* info too in these leaves (like words about having a constant TSC).
2556	*
2557	* @param pCpum The CPUM instance data.
2558	* @param pConfig The CPUID configuration we've read from CFGM.
2559	*/
2560	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2561	{
2562	/*
2563	* Standard leaves.
2564	*/
2565	uint32_t uSubLeaf = 0;
2566	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2567	if (pCurLeaf)
2568	{
2569	uint32_t uLimit = pCurLeaf->uEax;
2570	if (uLimit <= UINT32_C(0x000fffff))
2571	{
2572	if (uLimit > pConfig->uMaxStdLeaf)
2573	{
2574	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2575	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2576	uLimit + 1, UINT32_C(0x000fffff));
2577	}
2578
2579	/* NT4 hack, no zapping of extra leaves here. */
2580	if (pConfig->fNt4LeafLimit && uLimit > 3)
2581	pCurLeaf->uEax = uLimit = 3;
2582
2583	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2584	pCurLeaf->uEax = uLimit;
2585	}
2586	else
2587	{
2588	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2589	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2590	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2591	}
2592	}
2593
2594	/*
2595	* Extended leaves.
2596	*/
2597	uSubLeaf = 0;
2598	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2599	if (pCurLeaf)
2600	{
2601	uint32_t uLimit = pCurLeaf->uEax;
2602	if ( uLimit >= UINT32_C(0x80000000)
2603	&& uLimit <= UINT32_C(0x800fffff))
2604	{
2605	if (uLimit > pConfig->uMaxExtLeaf)
2606	{
2607	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2608	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2609	uLimit + 1, UINT32_C(0x800fffff));
2610	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2611	pCurLeaf->uEax = uLimit;
2612	}
2613	}
2614	else
2615	{
2616	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2617	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2618	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2619	}
2620	}
2621
2622	/*
2623	* Centaur leaves (VIA).
2624	*/
2625	uSubLeaf = 0;
2626	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2627	if (pCurLeaf)
2628	{
2629	uint32_t uLimit = pCurLeaf->uEax;
2630	if ( uLimit >= UINT32_C(0xc0000000)
2631	&& uLimit <= UINT32_C(0xc00fffff))
2632	{
2633	if (uLimit > pConfig->uMaxCentaurLeaf)
2634	{
2635	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2636	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2637	uLimit + 1, UINT32_C(0xcfffffff));
2638	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2639	pCurLeaf->uEax = uLimit;
2640	}
2641	}
2642	else
2643	{
2644	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2645	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2646	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2647	}
2648	}
2649	}
2650
2651
2652	/**
2653	* Clears a CPUID leaf and all sub-leaves (to zero).
2654	*
2655	* @param pCpum The CPUM instance data.
2656	* @param uLeaf The leaf to clear.
2657	*/
2658	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2659	{
2660	uint32_t uSubLeaf = 0;
2661	PCPUMCPUIDLEAF pCurLeaf;
2662	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2663	{
2664	pCurLeaf->uEax = 0;
2665	pCurLeaf->uEbx = 0;
2666	pCurLeaf->uEcx = 0;
2667	pCurLeaf->uEdx = 0;
2668	uSubLeaf++;
2669	}
2670	}
2671
2672
2673	/**
2674	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2675	* the given leaf.
2676	*
2677	* @returns pLeaf.
2678	* @param pCpum The CPUM instance data.
2679	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2680	*/
2681	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2682	{
2683	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2684	if (pLeaf->fSubLeafMask != 0)
2685	{
2686	/*
2687	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2688	* Log everything while we're at it.
2689	*/
2690	LogRel(("CPUM:\n"
2691	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2692	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2693	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2694	for (;;)
2695	{
2696	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2697	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2698	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2699	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2700	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2701	break;
2702	pSubLeaf++;
2703	}
2704	LogRel(("CPUM:\n"));
2705
2706	/*
2707	* Remove the offending sub-leaves.
2708	*/
2709	if (pSubLeaf != pLeaf)
2710	{
2711	if (pSubLeaf != pLast)
2712	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2713	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2714	}
2715
2716	/*
2717	* Convert the first sub-leaf into a single leaf.
2718	*/
2719	pLeaf->uSubLeaf = 0;
2720	pLeaf->fSubLeafMask = 0;
2721	}
2722	return pLeaf;
2723	}
2724
2725
2726	/**
2727	* Sanitizes and adjust the CPUID leaves.
2728	*
2729	* Drop features that aren't virtualized (or virtualizable). Adjust information
2730	* and capabilities to fit the virtualized hardware. Remove information the
2731	* guest shouldn't have (because it's wrong in the virtual world or because it
2732	* gives away host details) or that we don't have documentation for and no idea
2733	* what means.
2734	*
2735	* @returns VBox status code.
2736	* @param pVM The cross context VM structure (for cCpus).
2737	* @param pCpum The CPUM instance data.
2738	* @param pConfig The CPUID configuration we've read from CFGM.
2739	*/
2740	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2741	{
2742	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2743	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2744	{ \
2745	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2746	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2747	}
2748	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2749	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2750	{ \
2751	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2752	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2753	}
2754	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2755	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2756	&& ((a_pLeafReg) & (fBitMask)) \
2757	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2758	{ \
2759	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2760	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2761	}
2762	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2763
2764	/* Cpuid 1:
2765	* EAX: CPU model, family and stepping.
2766	*
2767	* ECX + EDX: Supported features. Only report features we can support.
2768	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2769	* options may require adjusting (i.e. stripping what was enabled).
2770	*
2771	* EBX: Branding, CLFLUSH line size, logical processors per package and
2772	* initial APIC ID.
2773	*/
2774	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2775	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2776	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2777
2778	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2779	\| X86_CPUID_FEATURE_EDX_VME
2780	\| X86_CPUID_FEATURE_EDX_DE
2781	\| X86_CPUID_FEATURE_EDX_PSE
2782	\| X86_CPUID_FEATURE_EDX_TSC
2783	\| X86_CPUID_FEATURE_EDX_MSR
2784	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2785	\| X86_CPUID_FEATURE_EDX_MCE
2786	\| X86_CPUID_FEATURE_EDX_CX8
2787	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2788	//\| RT_BIT_32(10) - not defined
2789	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2790	//\| X86_CPUID_FEATURE_EDX_SEP
2791	\| X86_CPUID_FEATURE_EDX_MTRR
2792	\| X86_CPUID_FEATURE_EDX_PGE
2793	\| X86_CPUID_FEATURE_EDX_MCA
2794	\| X86_CPUID_FEATURE_EDX_CMOV
2795	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2796	\| X86_CPUID_FEATURE_EDX_PSE36
2797	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2798	\| X86_CPUID_FEATURE_EDX_CLFSH
2799	//\| RT_BIT_32(20) - not defined
2800	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2801	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2802	\| X86_CPUID_FEATURE_EDX_MMX
2803	\| X86_CPUID_FEATURE_EDX_FXSR
2804	\| X86_CPUID_FEATURE_EDX_SSE
2805	\| X86_CPUID_FEATURE_EDX_SSE2
2806	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2807	\| X86_CPUID_FEATURE_EDX_HTT
2808	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2809	//\| RT_BIT_32(30) - not defined
2810	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2811	;
2812	pStdFeatureLeaf->uEcx &= 0
2813	\| X86_CPUID_FEATURE_ECX_SSE3
2814	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2815	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2816	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2817	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2818	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2819	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
2820	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2821	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2822	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2823	\| X86_CPUID_FEATURE_ECX_SSSE3
2824	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2825	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2826	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2827	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2828	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2829	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2830	\| (pConfig->enmPcid ? X86_CPUID_FEATURE_ECX_PCID : 0)
2831	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2832	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2833	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2834	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2835	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2836	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2837	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2838	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2839	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2840	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2841	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2842	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2843	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2844	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2845	;
2846
2847	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2848	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2849	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2850	{
2851	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2852	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2853	}
2854
2855	if (pCpum->u8PortableCpuIdLevel > 0)
2856	{
2857	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2858	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2859	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2860	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2861	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2862	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2863	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2864	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
2865	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2866	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2867	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2868	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2869	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2870	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2871	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2872	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2873	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2874	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2875	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2876	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2877
2878	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2879	\| X86_CPUID_FEATURE_EDX_PSN
2880	\| X86_CPUID_FEATURE_EDX_DS
2881	\| X86_CPUID_FEATURE_EDX_ACPI
2882	\| X86_CPUID_FEATURE_EDX_SS
2883	\| X86_CPUID_FEATURE_EDX_TM
2884	\| X86_CPUID_FEATURE_EDX_PBE
2885	)));
2886	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2887	\| X86_CPUID_FEATURE_ECX_CPLDS
2888	\| X86_CPUID_FEATURE_ECX_AES
2889	\| X86_CPUID_FEATURE_ECX_VMX
2890	\| X86_CPUID_FEATURE_ECX_SMX
2891	\| X86_CPUID_FEATURE_ECX_EST
2892	\| X86_CPUID_FEATURE_ECX_TM2
2893	\| X86_CPUID_FEATURE_ECX_CNTXID
2894	\| X86_CPUID_FEATURE_ECX_FMA
2895	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2896	\| X86_CPUID_FEATURE_ECX_PDCM
2897	\| X86_CPUID_FEATURE_ECX_DCA
2898	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2899	)));
2900	}
2901
2902	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2903	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2904
2905	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2906	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2907	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2908	*/
2909	#ifdef VBOX_WITH_MULTI_CORE
2910	if (pVM->cCpus > 1)
2911	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2912	#endif
2913	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2914	{
2915	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2916	core times the number of CPU cores per processor */
2917	#ifdef VBOX_WITH_MULTI_CORE
2918	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2919	#else
2920	/* Single logical processor in a package. */
2921	pStdFeatureLeaf->uEbx \|= (1 << 16);
2922	#endif
2923	}
2924
2925	uint32_t uMicrocodeRev;
2926	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2927	if (RT_SUCCESS(rc))
2928	{
2929	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2930	}
2931	else
2932	{
2933	uMicrocodeRev = 0;
2934	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2935	}
2936
2937	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2938	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2939	*/
2940	if ( (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen)
2941	&& uMicrocodeRev < 0x8001126
2942	&& !pConfig->fForceVme)
2943	{
2944	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2945	LogRel(("CPUM: Zen VME workaround engaged\n"));
2946	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
2947	}
2948
2949	/* Force standard feature bits. */
2950	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2951	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2952	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2953	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2954	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2955	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2956	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2957	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2958	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2959	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2960	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2961	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2962	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2963	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2964	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2965	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2966	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2967	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2968	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2969	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2970	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2971	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2972
2973	pStdFeatureLeaf = NULL; /* Must refetch! */
2974
2975	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2976	* AMD:
2977	* EAX: CPU model, family and stepping.
2978	*
2979	* ECX + EDX: Supported features. Only report features we can support.
2980	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2981	* options may require adjusting (i.e. stripping what was enabled).
2982	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2983	*
2984	* EBX: Branding ID and package type (or reserved).
2985	*
2986	* Intel and probably most others:
2987	* EAX: 0
2988	* EBX: 0
2989	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2990	*/
2991	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2992	if (pExtFeatureLeaf)
2993	{
2994	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2995
2996	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2997	\| X86_CPUID_AMD_FEATURE_EDX_VME
2998	\| X86_CPUID_AMD_FEATURE_EDX_DE
2999	\| X86_CPUID_AMD_FEATURE_EDX_PSE
3000	\| X86_CPUID_AMD_FEATURE_EDX_TSC
3001	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
3002	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
3003	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
3004	\| X86_CPUID_AMD_FEATURE_EDX_CX8
3005	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
3006	//\| RT_BIT_32(10) - reserved
3007	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
3008	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
3009	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3010	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
3011	\| X86_CPUID_AMD_FEATURE_EDX_PGE
3012	\| X86_CPUID_AMD_FEATURE_EDX_MCA
3013	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
3014	\| X86_CPUID_AMD_FEATURE_EDX_PAT
3015	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
3016	//\| RT_BIT_32(18) - reserved
3017	//\| RT_BIT_32(19) - reserved
3018	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
3019	//\| RT_BIT_32(21) - reserved
3020	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
3021	\| X86_CPUID_AMD_FEATURE_EDX_MMX
3022	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
3023	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
3024	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3025	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
3026	//\| RT_BIT_32(28) - reserved
3027	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
3028	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
3029	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
3030	;
3031	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
3032	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
3033	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
3034	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3035	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
3036	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
3037	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
3038	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
3039	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
3040	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
3041	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3042	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
3043	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
3044	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3045	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
3046	//\| RT_BIT_32(14) - reserved
3047	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
3048	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
3049	//\| RT_BIT_32(17) - reserved
3050	//\| RT_BIT_32(18) - reserved
3051	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
3052	//\| RT_BIT_32(20) - reserved
3053	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
3054	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
3055	//\| RT_BIT_32(23) - reserved
3056	//\| RT_BIT_32(24) - reserved
3057	//\| RT_BIT_32(25) - reserved
3058	//\| RT_BIT_32(26) - reserved
3059	//\| RT_BIT_32(27) - reserved
3060	//\| RT_BIT_32(28) - reserved
3061	//\| RT_BIT_32(29) - reserved
3062	//\| RT_BIT_32(30) - reserved
3063	//\| RT_BIT_32(31) - reserved
3064	;
3065	#ifdef VBOX_WITH_MULTI_CORE
3066	if ( pVM->cCpus > 1
3067	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3068	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
3069	#endif
3070
3071	if (pCpum->u8PortableCpuIdLevel > 0)
3072	{
3073	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
3074	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
3075	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
3076	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
3077	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
3078	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
3079	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
3080	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
3081	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
3082	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
3083	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
3084	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
3085	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
3086	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
3087	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
3088	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
3089
3090	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
3091	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3092	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3093	\| X86_CPUID_AMD_FEATURE_ECX_IBS
3094	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3095	\| X86_CPUID_AMD_FEATURE_ECX_WDT
3096	\| X86_CPUID_AMD_FEATURE_ECX_LWP
3097	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
3098	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
3099	\| UINT32_C(0xff964000)
3100	)));
3101	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
3102	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3103	\| RT_BIT(18)
3104	\| RT_BIT(19)
3105	\| RT_BIT(21)
3106	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
3107	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3108	\| RT_BIT(28)
3109	)));
3110	}
3111
3112	/* Force extended feature bits. */
3113	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
3114	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
3115	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
3116	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
3117	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
3118	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
3119	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
3120	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
3121	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3122	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
3123	}
3124	pExtFeatureLeaf = NULL; /* Must refetch! */
3125
3126
3127	/* Cpuid 2:
3128	* Intel: (Nondeterministic) Cache and TLB information
3129	* AMD: Reserved
3130	* VIA: Reserved
3131	* Safe to expose.
3132	*/
3133	uint32_t uSubLeaf = 0;
3134	PCPUMCPUIDLEAF pCurLeaf;
3135	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
3136	{
3137	if ((pCurLeaf->uEax & 0xff) > 1)
3138	{
3139	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
3140	pCurLeaf->uEax &= UINT32_C(0xffffff01);
3141	}
3142	uSubLeaf++;
3143	}
3144
3145	/* Cpuid 3:
3146	* Intel: EAX, EBX - reserved (transmeta uses these)
3147	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3148	* AMD: Reserved
3149	* VIA: Reserved
3150	* Safe to expose
3151	*/
3152	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3153	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3154	{
3155	uSubLeaf = 0;
3156	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3157	{
3158	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3159	if (pCpum->u8PortableCpuIdLevel > 0)
3160	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3161	uSubLeaf++;
3162	}
3163	}
3164
3165	/* Cpuid 4 + ECX:
3166	* Intel: Deterministic Cache Parameters Leaf.
3167	* AMD: Reserved
3168	* VIA: Reserved
3169	* Safe to expose, except for EAX:
3170	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3171	* Bits 31-26: Maximum number of processor cores in this physical package**
3172	* Note: These SMP values are constant regardless of ECX
3173	*/
3174	uSubLeaf = 0;
3175	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3176	{
3177	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3178	#ifdef VBOX_WITH_MULTI_CORE
3179	if ( pVM->cCpus > 1
3180	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3181	{
3182	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3183	/* One logical processor with possibly multiple cores. */
3184	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3185	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3186	}
3187	#endif
3188	uSubLeaf++;
3189	}
3190
3191	/* Cpuid 5: Monitor/mwait Leaf
3192	* Intel: ECX, EDX - reserved
3193	* EAX, EBX - Smallest and largest monitor line size
3194	* AMD: EDX - reserved
3195	* EAX, EBX - Smallest and largest monitor line size
3196	* ECX - extensions (ignored for now)
3197	* VIA: Reserved
3198	* Safe to expose
3199	*/
3200	uSubLeaf = 0;
3201	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3202	{
3203	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3204	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3205	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3206
3207	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3208	if (pConfig->enmMWaitExtensions)
3209	{
3210	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3211	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3212	it shall be part of our power management virtualization model */
3213	#if 0
3214	/* MWAIT sub C-states */
3215	pCurLeaf->uEdx =
3216	(0 << 0) /* 0 in C0 */ \|
3217	(2 << 4) /* 2 in C1 */ \|
3218	(2 << 8) /* 2 in C2 */ \|
3219	(2 << 12) /* 2 in C3 */ \|
3220	(0 << 16) /* 0 in C4 */
3221	;
3222	#endif
3223	}
3224	else
3225	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3226	uSubLeaf++;
3227	}
3228
3229	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3230	* Intel: Various stuff.
3231	* AMD: EAX, EBX, EDX - reserved.
3232	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3233	* present. Same as intel.
3234	* VIA: ??
3235	*
3236	* We clear everything here for now.
3237	*/
3238	cpumR3CpuIdZeroLeaf(pCpum, 6);
3239
3240	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3241	* EAX: Number of sub leaves.
3242	* EBX+ECX+EDX: Feature flags
3243	*
3244	* We only have documentation for one sub-leaf, so clear all other (no need
3245	* to remove them as such, just set them to zero).
3246	*
3247	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3248	* options may require adjusting (i.e. stripping what was enabled).
3249	*/
3250	uSubLeaf = 0;
3251	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3252	{
3253	switch (uSubLeaf)
3254	{
3255	case 0:
3256	{
3257	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3258	pCurLeaf->uEbx &= 0
3259	\| (pConfig->enmFsGsBase ? X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE : 0)
3260	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3261	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3262	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3263	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3264	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
3265	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3266	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3267	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3268	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3269	\| (pConfig->enmInvpcid ? X86_CPUID_STEXT_FEATURE_EBX_INVPCID : 0)
3270	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3271	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3272	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3273	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3274	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3275	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3276	//\| RT_BIT(17) - reserved
3277	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
3278	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3279	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3280	//\| RT_BIT(21) - reserved
3281	//\| RT_BIT(22) - reserved
3282	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
3283	//\| RT_BIT(24) - reserved
3284	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3285	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3286	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3287	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3288	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3289	//\| RT_BIT(30) - reserved
3290	//\| RT_BIT(31) - reserved
3291	;
3292	pCurLeaf->uEcx &= 0
3293	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3294	;
3295	pCurLeaf->uEdx &= 0
3296	\| (pConfig->enmMdsClear ? X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR : 0)
3297	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3298	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3299	\| (pConfig->enmFlushCmdMsr ? X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD : 0)
3300	\| (pConfig->enmArchCapMsr ? X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP : 0)
3301	;
3302
3303	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3304	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3305	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3306	{
3307	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3308	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3309	}
3310
3311	if (pCpum->u8PortableCpuIdLevel > 0)
3312	{
3313	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3314	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3315	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3316	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3317	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3318	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3319	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3320	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3321	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3322	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3323	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3324	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3325	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3326	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3327	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3328	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
3329	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
3330	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
3331	}
3332
3333	/* Dependencies. */
3334	if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
3335	pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3336
3337	/* Force standard feature bits. */
3338	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3339	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3340	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3341	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3342	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3343	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3344	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3345	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3346	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3347	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3348	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3349	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
3350	if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
3351	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3352	if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3353	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
3354	break;
3355	}
3356
3357	default:
3358	/* Invalid index, all values are zero. */
3359	pCurLeaf->uEax = 0;
3360	pCurLeaf->uEbx = 0;
3361	pCurLeaf->uEcx = 0;
3362	pCurLeaf->uEdx = 0;
3363	break;
3364	}
3365	uSubLeaf++;
3366	}
3367
3368	/* Cpuid 8: Marked as reserved by Intel and AMD.
3369	* We zero this since we don't know what it may have been used for.
3370	*/
3371	cpumR3CpuIdZeroLeaf(pCpum, 8);
3372
3373	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3374	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3375	* EBX, ECX, EDX - reserved.
3376	* AMD: Reserved
3377	* VIA: ??
3378	*
3379	* We zero this.
3380	*/
3381	cpumR3CpuIdZeroLeaf(pCpum, 9);
3382
3383	/* Cpuid 0xa: Architectural Performance Monitor Features
3384	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3385	* EBX, ECX, EDX - reserved.
3386	* AMD: Reserved
3387	* VIA: ??
3388	*
3389	* We zero this, for now at least.
3390	*/
3391	cpumR3CpuIdZeroLeaf(pCpum, 10);
3392
3393	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3394	* Intel: EAX - APCI ID shift right for next level.
3395	* EBX - Factory configured cores/threads at this level.
3396	* ECX - Level number (same as input) and level type (1,2,0).
3397	* EDX - Extended initial APIC ID.
3398	* AMD: Reserved
3399	* VIA: ??
3400	*/
3401	uSubLeaf = 0;
3402	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3403	{
3404	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3405	{
3406	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3407	if (bLevelType == 1)
3408	{
3409	/* Thread level - we don't do threads at the moment. */
3410	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3411	pCurLeaf->uEbx = 1;
3412	}
3413	else if (bLevelType == 2)
3414	{
3415	/* Core level. */
3416	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3417	#ifdef VBOX_WITH_MULTI_CORE
3418	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3419	pCurLeaf->uEax++;
3420	#endif
3421	pCurLeaf->uEbx = pVM->cCpus;
3422	}
3423	else
3424	{
3425	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3426	pCurLeaf->uEax = 0;
3427	pCurLeaf->uEbx = 0;
3428	pCurLeaf->uEcx = 0;
3429	}
3430	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3431	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3432	}
3433	else
3434	{
3435	pCurLeaf->uEax = 0;
3436	pCurLeaf->uEbx = 0;
3437	pCurLeaf->uEcx = 0;
3438	pCurLeaf->uEdx = 0;
3439	}
3440	uSubLeaf++;
3441	}
3442
3443	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3444	* We zero this since we don't know what it may have been used for.
3445	*/
3446	cpumR3CpuIdZeroLeaf(pCpum, 12);
3447
3448	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3449	* ECX=0: EAX - Valid bits in XCR0[31:0].
3450	* EBX - Maximum state size as per current XCR0 value.
3451	* ECX - Maximum state size for all supported features.
3452	* EDX - Valid bits in XCR0[63:32].
3453	* ECX=1: EAX - Various X-features.
3454	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3455	* ECX - Valid bits in IA32_XSS[31:0].
3456	* EDX - Valid bits in IA32_XSS[63:32].
3457	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3458	* if the bit invalid all four registers are set to zero.
3459	* EAX - The state size for this feature.
3460	* EBX - The state byte offset of this feature.
3461	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3462	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3463	*
3464	* Clear them all as we don't currently implement extended CPU state.
3465	*/
3466	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3467	uint64_t fGuestXcr0Mask = 0;
3468	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3469	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3470	{
3471	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3472	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3473	fGuestXcr0Mask \|= XSAVE_C_YMM;
3474	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3475	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3476	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3477	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3478
3479	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3480	}
3481	pStdFeatureLeaf = NULL;
3482	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3483
3484	/* Work the sub-leaves. */
3485	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3486	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3487	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3488	{
3489	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3490	if (pCurLeaf)
3491	{
3492	if (fGuestXcr0Mask)
3493	{
3494	switch (uSubLeaf)
3495	{
3496	case 0:
3497	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3498	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3499	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3500	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3501	VERR_CPUM_IPE_1);
3502	cbXSaveMaxActual = pCurLeaf->uEcx;
3503	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3504	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3505	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3506	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3507	VERR_CPUM_IPE_2);
3508	continue;
3509	case 1:
3510	pCurLeaf->uEax &= 0;
3511	pCurLeaf->uEcx &= 0;
3512	pCurLeaf->uEdx &= 0;
3513	/** @todo what about checking ebx? */
3514	continue;
3515	default:
3516	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3517	{
3518	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3519	&& pCurLeaf->uEax > 0
3520	&& pCurLeaf->uEbx < cbXSaveMaxActual
3521	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3522	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3523	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3524	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3525	VERR_CPUM_IPE_2);
3526	AssertLogRel(!(pCurLeaf->uEcx & 1));
3527	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3528	pCurLeaf->uEdx = 0; /* it's reserved... */
3529	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3530	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3531	continue;
3532	}
3533	break;
3534	}
3535	}
3536
3537	/* Clear the leaf. */
3538	pCurLeaf->uEax = 0;
3539	pCurLeaf->uEbx = 0;
3540	pCurLeaf->uEcx = 0;
3541	pCurLeaf->uEdx = 0;
3542	}
3543	}
3544
3545	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3546	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3547	{
3548	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3549	if (pCurLeaf)
3550	{
3551	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3552	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3553	pCurLeaf->uEbx = cbXSaveMaxReport;
3554	pCurLeaf->uEcx = cbXSaveMaxReport;
3555	}
3556	}
3557
3558	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3559	* We zero this since we don't know what it may have been used for.
3560	*/
3561	cpumR3CpuIdZeroLeaf(pCpum, 14);
3562
3563	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3564	* also known as Intel Resource Director Technology (RDT) Monitoring
3565	* We zero this as we don't currently virtualize PQM.
3566	*/
3567	cpumR3CpuIdZeroLeaf(pCpum, 15);
3568
3569	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3570	* also known as Intel Resource Director Technology (RDT) Allocation
3571	* We zero this as we don't currently virtualize PQE.
3572	*/
3573	cpumR3CpuIdZeroLeaf(pCpum, 16);
3574
3575	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3576	* We zero this since we don't know what it may have been used for.
3577	*/
3578	cpumR3CpuIdZeroLeaf(pCpum, 17);
3579
3580	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3581	* We zero this as we don't currently virtualize this.
3582	*/
3583	cpumR3CpuIdZeroLeaf(pCpum, 18);
3584
3585	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3586	* We zero this since we don't know what it may have been used for.
3587	*/
3588	cpumR3CpuIdZeroLeaf(pCpum, 19);
3589
3590	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3591	* We zero this as we don't currently virtualize this.
3592	*/
3593	cpumR3CpuIdZeroLeaf(pCpum, 20);
3594
3595	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3596	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3597	* EAX - denominator (unsigned).
3598	* EBX - numerator (unsigned).
3599	* ECX, EDX - reserved.
3600	* AMD: Reserved / undefined / not implemented.
3601	* VIA: Reserved / undefined / not implemented.
3602	* We zero this as we don't currently virtualize this.
3603	*/
3604	cpumR3CpuIdZeroLeaf(pCpum, 21);
3605
3606	/* Cpuid 0x16: Processor frequency info
3607	* Intel: EAX - Core base frequency in MHz.
3608	* EBX - Core maximum frequency in MHz.
3609	* ECX - Bus (reference) frequency in MHz.
3610	* EDX - Reserved.
3611	* AMD: Reserved / undefined / not implemented.
3612	* VIA: Reserved / undefined / not implemented.
3613	* We zero this as we don't currently virtualize this.
3614	*/
3615	cpumR3CpuIdZeroLeaf(pCpum, 22);
3616
3617	/* Cpuid 0x17..0x10000000: Unknown.
3618	* We don't know these and what they mean, so remove them. */
3619	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3620	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3621
3622
3623	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3624	* We remove all these as we're a hypervisor and must provide our own.
3625	*/
3626	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3627	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3628
3629
3630	/* Cpuid 0x80000000 is harmless. */
3631
3632	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3633
3634	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3635
3636	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3637	* Safe to pass on to the guest.
3638	*
3639	* AMD: 0x800000005 L1 cache information
3640	* 0x800000006 L2/L3 cache information
3641	* Intel: 0x800000005 reserved
3642	* 0x800000006 L2 cache information
3643	* VIA: 0x800000005 TLB and L1 cache information
3644	* 0x800000006 L2 cache information
3645	*/
3646
3647	/* Cpuid 0x800000007: Advanced Power Management Information.
3648	* AMD: EAX: Processor feedback capabilities.
3649	* EBX: RAS capabilites.
3650	* ECX: Advanced power monitoring interface.
3651	* EDX: Enhanced power management capabilities.
3652	* Intel: EAX, EBX, ECX - reserved.
3653	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3654	* VIA: Reserved
3655	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3656	*/
3657	uSubLeaf = 0;
3658	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3659	{
3660	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3661	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3662	{
3663	/*
3664	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3665	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3666	* bit is now configurable.
3667	*/
3668	pCurLeaf->uEdx &= 0
3669	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3670	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3671	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3672	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3673	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3674	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3675	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3676	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3677	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3678	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3679	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3680	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3681	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3682	\| 0;
3683	}
3684	else
3685	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3686	if (!pConfig->fInvariantTsc)
3687	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3688	uSubLeaf++;
3689	}
3690
3691	/* Cpuid 0x80000008:
3692	* AMD: EBX, EDX - reserved
3693	* EAX: Virtual/Physical/Guest address Size
3694	* ECX: Number of cores + APICIdCoreIdSize
3695	* Intel: EAX: Virtual/Physical address Size
3696	* EBX, ECX, EDX - reserved
3697	* VIA: EAX: Virtual/Physical address Size
3698	* EBX, ECX, EDX - reserved
3699	*
3700	* We only expose the virtual+pysical address size to the guest atm.
3701	* On AMD we set the core count, but not the apic id stuff as we're
3702	* currently not doing the apic id assignments in a complatible manner.
3703	*/
3704	uSubLeaf = 0;
3705	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3706	{
3707	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3708	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3709	pCurLeaf->uEdx = 0; /* reserved */
3710
3711	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3712	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3713	pCurLeaf->uEcx = 0;
3714	#ifdef VBOX_WITH_MULTI_CORE
3715	if ( pVM->cCpus > 1
3716	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3717	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3718	#endif
3719	uSubLeaf++;
3720	}
3721
3722	/* Cpuid 0x80000009: Reserved
3723	* We zero this since we don't know what it may have been used for.
3724	*/
3725	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3726
3727	/* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
3728	* AMD: EAX - SVM revision.
3729	* EBX - Number of ASIDs.
3730	* ECX - Reserved.
3731	* EDX - SVM Feature identification.
3732	*/
3733	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3734	{
3735	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3736	if ( pExtFeatureLeaf
3737	&& (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM))
3738	{
3739	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3740	if (pSvmFeatureLeaf)
3741	{
3742	pSvmFeatureLeaf->uEax = 0x1;
3743	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3744	pSvmFeatureLeaf->uEcx = 0;
3745	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3746	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3747	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3748	}
3749	else
3750	{
3751	/* Should never happen. */
3752	LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
3753	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3754	}
3755	}
3756	else
3757	{
3758	/* If SVM is not supported, this is reserved, zero out. */
3759	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3760	}
3761	}
3762	else
3763	{
3764	/* Cpuid 0x8000000a: Reserved on Intel.
3765	* We zero this since we don't know what it may have been used for.
3766	*/
3767	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3768	}
3769
3770	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3771	* We clear these as we don't know what purpose they might have. */
3772	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3773	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3774
3775	/* Cpuid 0x80000019: TLB configuration
3776	* Seems to be harmless, pass them thru as is. */
3777
3778	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3779	* Strip anything we don't know what is or addresses feature we don't implement. */
3780	uSubLeaf = 0;
3781	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3782	{
3783	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3784	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3785	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3786	;
3787	pCurLeaf->uEbx = 0; /* reserved */
3788	pCurLeaf->uEcx = 0; /* reserved */
3789	pCurLeaf->uEdx = 0; /* reserved */
3790	uSubLeaf++;
3791	}
3792
3793	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3794	* Clear this as we don't currently virtualize this feature. */
3795	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3796
3797	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3798	* Clear this as we don't currently virtualize this feature. */
3799	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3800
3801	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3802	* We need to sanitize the cores per cache (EAX[25:14]).
3803	*
3804	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3805	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3806	* slightly different meaning.
3807	*/
3808	uSubLeaf = 0;
3809	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3810	{
3811	#ifdef VBOX_WITH_MULTI_CORE
3812	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3813	if (cCores > pVM->cCpus)
3814	cCores = pVM->cCpus;
3815	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3816	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3817	#else
3818	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3819	#endif
3820	uSubLeaf++;
3821	}
3822
3823	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3824	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3825	* setup, we have one compute unit with all the cores in it. Single node.
3826	*/
3827	uSubLeaf = 0;
3828	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3829	{
3830	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3831	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3832	{
3833	#ifdef VBOX_WITH_MULTI_CORE
3834	pCurLeaf->uEbx = pVM->cCpus < 0x100
3835	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3836	#else
3837	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3838	#endif
3839	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3840	}
3841	else
3842	{
3843	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3844	pCurLeaf->uEbx = 0; /* Reserved. */
3845	pCurLeaf->uEcx = 0; /* Reserved. */
3846	}
3847	pCurLeaf->uEdx = 0; /* Reserved. */
3848	uSubLeaf++;
3849	}
3850
3851	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3852	* We don't know these and what they mean, so remove them. */
3853	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3854	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3855
3856	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3857	* Just pass it thru for now. */
3858
3859	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3860	* Just pass it thru for now. */
3861
3862	/* Cpuid 0xc0000000: Centaur stuff.
3863	* Harmless, pass it thru. */
3864
3865	/* Cpuid 0xc0000001: Centaur features.
3866	* VIA: EAX - Family, model, stepping.
3867	* EDX - Centaur extended feature flags. Nothing interesting, except may
3868	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3869	* EBX, ECX - reserved.
3870	* We keep EAX but strips the rest.
3871	*/
3872	uSubLeaf = 0;
3873	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3874	{
3875	pCurLeaf->uEbx = 0;
3876	pCurLeaf->uEcx = 0;
3877	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3878	uSubLeaf++;
3879	}
3880
3881	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3882	* We only have fixed stale values, but should be harmless. */
3883
3884	/* Cpuid 0xc0000003: Reserved.
3885	* We zero this since we don't know what it may have been used for.
3886	*/
3887	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3888
3889	/* Cpuid 0xc0000004: Centaur Performance Info.
3890	* We only have fixed stale values, but should be harmless. */
3891
3892
3893	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3894	* We don't know these and what they mean, so remove them. */
3895	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3896	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3897
3898	return VINF_SUCCESS;
3899	#undef PORTABLE_DISABLE_FEATURE_BIT
3900	#undef PORTABLE_CLEAR_BITS_WHEN
3901	}
3902
3903
3904	/**
3905	* Reads a value in /CPUM/IsaExts/ node.
3906	*
3907	* @returns VBox status code (error message raised).
3908	* @param pVM The cross context VM structure. (For errors.)
3909	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3910	* @param pszValueName The value / extension name.
3911	* @param penmValue Where to return the choice.
3912	* @param enmDefault The default choice.
3913	*/
3914	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3915	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3916	{
3917	/*
3918	* Try integer encoding first.
3919	*/
3920	uint64_t uValue;
3921	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3922	if (RT_SUCCESS(rc))
3923	switch (uValue)
3924	{
3925	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3926	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3927	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3928	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3929	default:
3930	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3931	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3932	pszValueName, uValue);
3933	}
3934	/*
3935	* If missing, use default.
3936	*/
3937	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3938	*penmValue = enmDefault;
3939	else
3940	{
3941	if (rc == VERR_CFGM_NOT_INTEGER)
3942	{
3943	/*
3944	* Not an integer, try read it as a string.
3945	*/
3946	char szValue[32];
3947	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3948	if (RT_SUCCESS(rc))
3949	{
3950	RTStrToLower(szValue);
3951	size_t cchValue = strlen(szValue);
3952	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3953	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3954	*penmValue = CPUMISAEXTCFG_DISABLED;
3955	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3956	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3957	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3958	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3959	else if (EQ("portable"))
3960	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3961	else if (EQ("default") \|\| EQ("def"))
3962	*penmValue = enmDefault;
3963	else
3964	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3965	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3966	pszValueName, uValue);
3967	#undef EQ
3968	}
3969	}
3970	if (RT_FAILURE(rc))
3971	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3972	}
3973	return VINF_SUCCESS;
3974	}
3975
3976
3977	/**
3978	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3979	*
3980	* @returns VBox status code (error message raised).
3981	* @param pVM The cross context VM structure. (For errors.)
3982	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3983	* @param pszValueName The value / extension name.
3984	* @param penmValue Where to return the choice.
3985	* @param enmDefault The default choice.
3986	* @param fAllowed Allowed choice. Applied both to the result and to
3987	* the default value.
3988	*/
3989	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3990	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3991	{
3992	int rc;
3993	if (fAllowed)
3994	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3995	else
3996	{
3997	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3998	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3999	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
4000	*penmValue = CPUMISAEXTCFG_DISABLED;
4001	}
4002	return rc;
4003	}
4004
4005
4006	/**
4007	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
4008	*
4009	* @returns VBox status code (error message raised).
4010	* @param pVM The cross context VM structure. (For errors.)
4011	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4012	* @param pCpumCfg The /CPUM node (can be NULL).
4013	* @param pszValueName The value / extension name.
4014	* @param penmValue Where to return the choice.
4015	* @param enmDefault The default choice.
4016	*/
4017	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
4018	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
4019	{
4020	if (CFGMR3Exists(pCpumCfg, pszValueName))
4021	{
4022	if (!CFGMR3Exists(pIsaExts, pszValueName))
4023	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
4024	else
4025	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
4026	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
4027	pszValueName, pszValueName);
4028
4029	bool fLegacy;
4030	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
4031	if (RT_SUCCESS(rc))
4032	{
4033	*penmValue = fLegacy;
4034	return VINF_SUCCESS;
4035	}
4036	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
4037	}
4038
4039	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4040	}
4041
4042
4043	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
4044	{
4045	int rc;
4046
4047	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
4048	* When non-zero CPUID features that could cause portability issues will be
4049	* stripped. The higher the value the more features gets stripped. Higher
4050	* values should only be used when older CPUs are involved since it may
4051	* harm performance and maybe also cause problems with specific guests. */
4052	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
4053	AssertLogRelRCReturn(rc, rc);
4054
4055	/** @cfgm{/CPUM/GuestCpuName, string}
4056	* The name of the CPU we're to emulate. The default is the host CPU.
4057	* Note! CPUs other than "host" one is currently unsupported. */
4058	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
4059	AssertLogRelRCReturn(rc, rc);
4060
4061	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
4062	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
4063	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
4064	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
4065	*/
4066	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
4067	AssertLogRelRCReturn(rc, rc);
4068
4069	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
4070	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
4071	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
4072	* 64-bit linux guests which assume the presence of AMD performance counters
4073	* that we do not virtualize.
4074	*/
4075	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
4076	AssertLogRelRCReturn(rc, rc);
4077
4078	/** @cfgm{/CPUM/ForceVme, boolean, false}
4079	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
4080	* By default the flag is passed thru as is from the host CPU, except
4081	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
4082	* guests and DOS boxes in general.
4083	*/
4084	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
4085	AssertLogRelRCReturn(rc, rc);
4086
4087	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
4088	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
4089	* probably going to be a temporary hack, so don't depend on this.
4090	* The 1st byte of the value is the stepping, the 2nd byte value is the model
4091	* number and the 3rd byte value is the family, and the 4th value must be zero.
4092	*/
4093	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
4094	AssertLogRelRCReturn(rc, rc);
4095
4096	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
4097	* The last standard leaf to keep. The actual last value that is stored in EAX
4098	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
4099	* removed. (This works independently of and differently from NT4LeafLimit.)
4100	* The default is usually set to what we're able to reasonably sanitize.
4101	*/
4102	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
4103	AssertLogRelRCReturn(rc, rc);
4104
4105	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
4106	* The last extended leaf to keep. The actual last value that is stored in EAX
4107	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
4108	* leaf are removed. The default is set to what we're able to sanitize.
4109	*/
4110	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
4111	AssertLogRelRCReturn(rc, rc);
4112
4113	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
4114	* The last extended leaf to keep. The actual last value that is stored in EAX
4115	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
4116	* leaf are removed. The default is set to what we're able to sanitize.
4117	*/
4118	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
4119	AssertLogRelRCReturn(rc, rc);
4120
4121	bool fQueryNestedHwvirt = false;
4122	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4123	fQueryNestedHwvirt \|= RT_BOOL(pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD);
4124	#endif
4125	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4126	fQueryNestedHwvirt \|= RT_BOOL( pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
4127	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA);
4128	#endif
4129	if (fQueryNestedHwvirt)
4130	{
4131	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
4132	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
4133	* The default is false, and when enabled requires a 64-bit CPU with support for
4134	* nested-paging and AMD-V or unrestricted guest mode.
4135	*/
4136	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
4137	AssertLogRelRCReturn(rc, rc);
4138	if ( pConfig->fNestedHWVirt
4139	&& !fNestedPagingAndFullGuestExec)
4140	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
4141	"Cannot enable nested VT-x/AMD-V without nested-paging and unresricted guest execution!\n");
4142
4143	/** @todo Think about enabling this later with NEM/KVM. */
4144	if ( pConfig->fNestedHWVirt
4145	&& VM_IS_NEM_ENABLED(pVM))
4146	{
4147	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used!\n"));
4148	pConfig->fNestedHWVirt = false;
4149	}
4150	}
4151
4152	/*
4153	* Instruction Set Architecture (ISA) Extensions.
4154	*/
4155	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
4156	if (pIsaExts)
4157	{
4158	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
4159	"CMPXCHG16B"
4160	"\|MONITOR"
4161	"\|MWaitExtensions"
4162	"\|SSE4.1"
4163	"\|SSE4.2"
4164	"\|XSAVE"
4165	"\|AVX"
4166	"\|AVX2"
4167	"\|AESNI"
4168	"\|PCLMUL"
4169	"\|POPCNT"
4170	"\|MOVBE"
4171	"\|RDRAND"
4172	"\|RDSEED"
4173	"\|CLFLUSHOPT"
4174	"\|FSGSBASE"
4175	"\|PCID"
4176	"\|INVPCID"
4177	"\|FlushCmdMsr"
4178	"\|ABM"
4179	"\|SSE4A"
4180	"\|MISALNSSE"
4181	"\|3DNOWPRF"
4182	"\|AXMMX"
4183	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
4184	if (RT_FAILURE(rc))
4185	return rc;
4186	}
4187
4188	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
4189	* Expose CMPXCHG16B to the guest if supported by the host. For the time
4190	* being the default is to only do this for VMs with nested paging and AMD-V or
4191	* unrestricted guest mode.
4192	*/
4193	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
4194	AssertLogRelRCReturn(rc, rc);
4195
4196	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
4197	* Expose MONITOR/MWAIT instructions to the guest.
4198	*/
4199	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
4200	AssertLogRelRCReturn(rc, rc);
4201
4202	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4203	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4204	* break on interrupt feature (bit 1).
4205	*/
4206	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4207	AssertLogRelRCReturn(rc, rc);
4208
4209	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4210	* Expose SSE4.1 to the guest if available.
4211	*/
4212	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4213	AssertLogRelRCReturn(rc, rc);
4214
4215	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4216	* Expose SSE4.2 to the guest if available.
4217	*/
4218	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4219	AssertLogRelRCReturn(rc, rc);
4220
4221	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
4222	&& pVM->cpum.s.HostFeatures.fXSaveRstor
4223	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor;
4224	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4225
4226	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4227	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4228	* default is to only expose this to VMs with nested paging and AMD-V or
4229	* unrestricted guest execution mode. Not possible to force this one without
4230	* host support at the moment.
4231	*/
4232	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4233	fMayHaveXSave /fAllowed/);
4234	AssertLogRelRCReturn(rc, rc);
4235
4236	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4237	* Expose the AVX instruction set extensions to the guest if available and
4238	* XSAVE is exposed too. For the time being the default is to only expose this
4239	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4240	*/
4241	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4242	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4243	AssertLogRelRCReturn(rc, rc);
4244
4245	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4246	* Expose the AVX2 instruction set extensions to the guest if available and
4247	* XSAVE is exposed too. For the time being the default is to only expose this
4248	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4249	*/
4250	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4251	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4252	AssertLogRelRCReturn(rc, rc);
4253
4254	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4255	* Whether to expose the AES instructions to the guest. For the time being the
4256	* default is to only do this for VMs with nested paging and AMD-V or
4257	* unrestricted guest mode.
4258	*/
4259	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4260	AssertLogRelRCReturn(rc, rc);
4261
4262	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4263	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4264	* being the default is to only do this for VMs with nested paging and AMD-V or
4265	* unrestricted guest mode.
4266	*/
4267	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4268	AssertLogRelRCReturn(rc, rc);
4269
4270	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4271	* Whether to expose the POPCNT instructions to the guest. For the time
4272	* being the default is to only do this for VMs with nested paging and AMD-V or
4273	* unrestricted guest mode.
4274	*/
4275	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4276	AssertLogRelRCReturn(rc, rc);
4277
4278	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4279	* Whether to expose the MOVBE instructions to the guest. For the time
4280	* being the default is to only do this for VMs with nested paging and AMD-V or
4281	* unrestricted guest mode.
4282	*/
4283	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4284	AssertLogRelRCReturn(rc, rc);
4285
4286	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4287	* Whether to expose the RDRAND instructions to the guest. For the time being
4288	* the default is to only do this for VMs with nested paging and AMD-V or
4289	* unrestricted guest mode.
4290	*/
4291	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4292	AssertLogRelRCReturn(rc, rc);
4293
4294	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4295	* Whether to expose the RDSEED instructions to the guest. For the time being
4296	* the default is to only do this for VMs with nested paging and AMD-V or
4297	* unrestricted guest mode.
4298	*/
4299	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4300	AssertLogRelRCReturn(rc, rc);
4301
4302	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4303	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4304	* being the default is to only do this for VMs with nested paging and AMD-V or
4305	* unrestricted guest mode.
4306	*/
4307	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4308	AssertLogRelRCReturn(rc, rc);
4309
4310	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4311	* Whether to expose the read/write FSGSBASE instructions to the guest.
4312	*/
4313	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4314	AssertLogRelRCReturn(rc, rc);
4315
4316	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4317	* Whether to expose the PCID feature to the guest.
4318	*/
4319	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4320	AssertLogRelRCReturn(rc, rc);
4321
4322	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4323	* Whether to expose the INVPCID instruction to the guest.
4324	*/
4325	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4326	AssertLogRelRCReturn(rc, rc);
4327
4328	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
4329	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
4330	*/
4331	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4332	AssertLogRelRCReturn(rc, rc);
4333
4334	/** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
4335	* Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
4336	* the guest. Requires FlushCmdMsr to be present too.
4337	*/
4338	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4339	AssertLogRelRCReturn(rc, rc);
4340
4341	/** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
4342	* Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
4343	*/
4344	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4345	AssertLogRelRCReturn(rc, rc);
4346
4347
4348	/* AMD: */
4349
4350	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4351	* Whether to expose the AMD ABM instructions to the guest. For the time
4352	* being the default is to only do this for VMs with nested paging and AMD-V or
4353	* unrestricted guest mode.
4354	*/
4355	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4356	AssertLogRelRCReturn(rc, rc);
4357
4358	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4359	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4360	* being the default is to only do this for VMs with nested paging and AMD-V or
4361	* unrestricted guest mode.
4362	*/
4363	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4364	AssertLogRelRCReturn(rc, rc);
4365
4366	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4367	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4368	* the time being the default is to only do this for VMs with nested paging and
4369	* AMD-V or unrestricted guest mode.
4370	*/
4371	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4372	AssertLogRelRCReturn(rc, rc);
4373
4374	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4375	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4376	* For the time being the default is to only do this for VMs with nested paging
4377	* and AMD-V or unrestricted guest mode.
4378	*/
4379	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4380	AssertLogRelRCReturn(rc, rc);
4381
4382	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4383	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4384	* the default is to only do this for VMs with nested paging and AMD-V or
4385	* unrestricted guest mode.
4386	*/
4387	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4388	AssertLogRelRCReturn(rc, rc);
4389
4390	return VINF_SUCCESS;
4391	}
4392
4393
4394	/**
4395	* Initializes the emulated CPU's CPUID & MSR information.
4396	*
4397	* @returns VBox status code.
4398	* @param pVM The cross context VM structure.
4399	* @param pHostMsrs Pointer to the host MSRs.
4400	*/
4401	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
4402	{
4403	Assert(pHostMsrs);
4404
4405	PCPUM pCpum = &pVM->cpum.s;
4406	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4407
4408	/*
4409	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4410	* on construction and manage everything from here on.
4411	*/
4412	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4413	{
4414	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4415	pVCpu->cpum.s.fCpuIdApicFeatureVisible = true;
4416	}
4417
4418	/*
4419	* Read the configuration.
4420	*/
4421	CPUMCPUIDCONFIG Config;
4422	RT_ZERO(Config);
4423
4424	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4425	AssertRCReturn(rc, rc);
4426
4427	/*
4428	* Get the guest CPU data from the database and/or the host.
4429	*
4430	* The CPUID and MSRs are currently living on the regular heap to avoid
4431	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4432	* API for the hyper heap). This means special cleanup considerations.
4433	*/
4434	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4435	if (RT_FAILURE(rc))
4436	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4437	? VMSetError(pVM, rc, RT_SRC_POS,
4438	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4439	: rc;
4440
4441	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4442	{
4443	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4444	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4445	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4446	}
4447	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4448
4449	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4450	* Overrides the guest MSRs.
4451	*/
4452	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4453
4454	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4455	* Overrides the CPUID leaf values (from the host CPU usually) used for
4456	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4457	* values when moving a VM to a different machine. Another use is restricting
4458	* (or extending) the feature set exposed to the guest. */
4459	if (RT_SUCCESS(rc))
4460	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4461
4462	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4463	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4464	"Found unsupported configuration node '/CPUM/CPUID/'. "
4465	"Please use IMachine::setCPUIDLeaf() instead.");
4466
4467	CPUMMSRS GuestMsrs;
4468	RT_ZERO(GuestMsrs);
4469
4470	/*
4471	* Pre-explode the CPUID info.
4472	*/
4473	if (RT_SUCCESS(rc))
4474	{
4475	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
4476	&pCpum->GuestFeatures);
4477	}
4478
4479	/*
4480	* Sanitize the cpuid information passed on to the guest.
4481	*/
4482	if (RT_SUCCESS(rc))
4483	{
4484	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4485	if (RT_SUCCESS(rc))
4486	{
4487	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4488	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4489	}
4490	}
4491
4492	/*
4493	* Setup MSRs introduced in microcode updates or that are otherwise not in
4494	* the CPU profile, but are advertised in the CPUID info we just sanitized.
4495	*/
4496	if (RT_SUCCESS(rc))
4497	rc = cpumR3MsrReconcileWithCpuId(pVM);
4498	/*
4499	* MSR fudging.
4500	*/
4501	if (RT_SUCCESS(rc))
4502	{
4503	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4504	* Fudges some common MSRs if not present in the selected CPU database entry.
4505	* This is for trying to keep VMs running when moved between different hosts
4506	* and different CPU vendors. */
4507	bool fEnable;
4508	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4509	if (RT_SUCCESS(rc) && fEnable)
4510	{
4511	rc = cpumR3MsrApplyFudge(pVM);
4512	AssertLogRelRC(rc);
4513	}
4514	}
4515	if (RT_SUCCESS(rc))
4516	{
4517	/*
4518	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4519	* guest CPU features again.
4520	*/
4521	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4522	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4523	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
4524	RTMemFree(pvFree);
4525
4526	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4527	int rc2 = MMHyperDupMem(pVM, pvFree,
4528	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4529	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4530	RTMemFree(pvFree);
4531	AssertLogRelRCReturn(rc1, rc1);
4532	AssertLogRelRCReturn(rc2, rc2);
4533
4534	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4535
4536	/*
4537	* Finally, initialize guest VMX MSRs.
4538	*
4539	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
4540	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
4541	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
4542	*/
4543	if (pVM->cpum.s.GuestFeatures.fVmx)
4544	{
4545	Assert(Config.fNestedHWVirt);
4546	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
4547
4548	/* Copy MSRs to all VCPUs */
4549	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
4550	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4551	{
4552	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4553	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
4554	}
4555	}
4556
4557	/*
4558	* Some more configuration that we're applying at the end of everything
4559	* via the CPUMR3SetGuestCpuIdFeature API.
4560	*/
4561
4562	/* Check if PAE was explicitely enabled by the user. */
4563	bool fEnable;
4564	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4565	AssertRCReturn(rc, rc);
4566	if (fEnable)
4567	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4568
4569	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4570	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4571	AssertRCReturn(rc, rc);
4572	if (fEnable)
4573	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4574
4575	/* Check if speculation control is enabled. */
4576	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4577	AssertRCReturn(rc, rc);
4578	if (fEnable)
4579	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4580
4581	return VINF_SUCCESS;
4582	}
4583
4584	/*
4585	* Failed before switching to hyper heap.
4586	*/
4587	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4588	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4589	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4590	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4591	return rc;
4592	}
4593
4594
4595	/**
4596	* Sets a CPUID feature bit during VM initialization.
4597	*
4598	* Since the CPUID feature bits are generally related to CPU features, other
4599	* CPUM configuration like MSRs can also be modified by calls to this API.
4600	*
4601	* @param pVM The cross context VM structure.
4602	* @param enmFeature The feature to set.
4603	*/
4604	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4605	{
4606	PCPUMCPUIDLEAF pLeaf;
4607	PCPUMMSRRANGE pMsrRange;
4608
4609	switch (enmFeature)
4610	{
4611	/*
4612	* Set the APIC bit in both feature masks.
4613	*/
4614	case CPUMCPUIDFEATURE_APIC:
4615	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4616	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4617	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4618
4619	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4620	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4621	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4622
4623	pVM->cpum.s.GuestFeatures.fApic = 1;
4624
4625	/* Make sure we've got the APICBASE MSR present. */
4626	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4627	if (!pMsrRange)
4628	{
4629	static CPUMMSRRANGE const s_ApicBase =
4630	{
4631	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4632	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4633	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4634	/.szName = / "IA32_APIC_BASE"
4635	};
4636	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4637	AssertLogRelRC(rc);
4638	}
4639
4640	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4641	break;
4642
4643	/*
4644	* Set the x2APIC bit in the standard feature mask.
4645	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4646	*/
4647	case CPUMCPUIDFEATURE_X2APIC:
4648	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4649	if (pLeaf)
4650	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4651	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4652
4653	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4654	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4655	if (pMsrRange)
4656	{
4657	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4658	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4659	}
4660
4661	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4662	break;
4663
4664	/*
4665	* Set the sysenter/sysexit bit in the standard feature mask.
4666	* Assumes the caller knows what it's doing! (host must support these)
4667	*/
4668	case CPUMCPUIDFEATURE_SEP:
4669	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4670	{
4671	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4672	return;
4673	}
4674
4675	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4676	if (pLeaf)
4677	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4678	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4679	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4680	break;
4681
4682	/*
4683	* Set the syscall/sysret bit in the extended feature mask.
4684	* Assumes the caller knows what it's doing! (host must support these)
4685	*/
4686	case CPUMCPUIDFEATURE_SYSCALL:
4687	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4688	if ( !pLeaf
4689	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4690	{
4691	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4692	return;
4693	}
4694
4695	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4696	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4697	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4698	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4699	break;
4700
4701	/*
4702	* Set the PAE bit in both feature masks.
4703	* Assumes the caller knows what it's doing! (host must support these)
4704	*/
4705	case CPUMCPUIDFEATURE_PAE:
4706	if (!pVM->cpum.s.HostFeatures.fPae)
4707	{
4708	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4709	return;
4710	}
4711
4712	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4713	if (pLeaf)
4714	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4715
4716	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4717	if ( pLeaf
4718	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4719	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4720
4721	pVM->cpum.s.GuestFeatures.fPae = 1;
4722	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4723	break;
4724
4725	/*
4726	* Set the LONG MODE bit in the extended feature mask.
4727	* Assumes the caller knows what it's doing! (host must support these)
4728	*/
4729	case CPUMCPUIDFEATURE_LONG_MODE:
4730	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4731	if ( !pLeaf
4732	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4733	{
4734	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4735	return;
4736	}
4737
4738	/* Valid for both Intel and AMD. */
4739	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4740	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4741	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
4742	if (pVM->cpum.s.GuestFeatures.fVmx)
4743	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4744	{
4745	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4746	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic &= ~VMX_BASIC_PHYSADDR_WIDTH_32BIT;
4747	}
4748	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4749	break;
4750
4751	/*
4752	* Set the NX/XD bit in the extended feature mask.
4753	* Assumes the caller knows what it's doing! (host must support these)
4754	*/
4755	case CPUMCPUIDFEATURE_NX:
4756	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4757	if ( !pLeaf
4758	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4759	{
4760	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4761	return;
4762	}
4763
4764	/* Valid for both Intel and AMD. */
4765	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4766	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4767	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4768	break;
4769
4770
4771	/*
4772	* Set the LAHF/SAHF support in 64-bit mode.
4773	* Assumes the caller knows what it's doing! (host must support this)
4774	*/
4775	case CPUMCPUIDFEATURE_LAHF:
4776	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4777	if ( !pLeaf
4778	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4779	{
4780	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4781	return;
4782	}
4783
4784	/* Valid for both Intel and AMD. */
4785	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4786	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4787	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4788	break;
4789
4790	/*
4791	* Set the page attribute table bit. This is alternative page level
4792	* cache control that doesn't much matter when everything is
4793	* virtualized, though it may when passing thru device memory.
4794	*/
4795	case CPUMCPUIDFEATURE_PAT:
4796	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4797	if (pLeaf)
4798	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4799
4800	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4801	if ( pLeaf
4802	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4803	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4804
4805	pVM->cpum.s.GuestFeatures.fPat = 1;
4806	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4807	break;
4808
4809	/*
4810	* Set the RDTSCP support bit.
4811	* Assumes the caller knows what it's doing! (host must support this)
4812	*/
4813	case CPUMCPUIDFEATURE_RDTSCP:
4814	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4815	if ( !pLeaf
4816	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4817	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4818	{
4819	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4820	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4821	return;
4822	}
4823
4824	/* Valid for both Intel and AMD. */
4825	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4826	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4827	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4828	break;
4829
4830	/*
4831	* Set the Hypervisor Present bit in the standard feature mask.
4832	*/
4833	case CPUMCPUIDFEATURE_HVP:
4834	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4835	if (pLeaf)
4836	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4837	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4838	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4839	break;
4840
4841	/*
4842	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4843	* This currently includes the Present bit and MWAITBREAK bit as well.
4844	*/
4845	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4846	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4847	if ( !pLeaf
4848	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4849	{
4850	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4851	return;
4852	}
4853
4854	/* Valid for both Intel and AMD. */
4855	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4856	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4857	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4858	break;
4859
4860	/*
4861	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
4862	* on Intel CPUs, and different on AMDs.
4863	*/
4864	case CPUMCPUIDFEATURE_SPEC_CTRL:
4865	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
4866	{
4867	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4868	if ( !pLeaf
4869	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
4870	{
4871	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
4872	return;
4873	}
4874
4875	/* The feature can be enabled. Let's see what we can actually do. */
4876	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
4877
4878	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
4879	if (pVM->cpum.s.HostFeatures.fIbrs)
4880	{
4881	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
4882	pVM->cpum.s.GuestFeatures.fIbrs = 1;
4883	if (pVM->cpum.s.HostFeatures.fStibp)
4884	{
4885	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
4886	pVM->cpum.s.GuestFeatures.fStibp = 1;
4887	}
4888
4889	/* Make sure we have the speculation control MSR... */
4890	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
4891	if (!pMsrRange)
4892	{
4893	static CPUMMSRRANGE const s_SpecCtrl =
4894	{
4895	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
4896	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
4897	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4898	/.szName = / "IA32_SPEC_CTRL"
4899	};
4900	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4901	AssertLogRelRC(rc);
4902	}
4903
4904	/* ... and the predictor command MSR. */
4905	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
4906	if (!pMsrRange)
4907	{
4908	/** @todo incorrect fWrGpMask. */
4909	static CPUMMSRRANGE const s_SpecCtrl =
4910	{
4911	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
4912	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
4913	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4914	/.szName = / "IA32_PRED_CMD"
4915	};
4916	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4917	AssertLogRelRC(rc);
4918	}
4919
4920	}
4921
4922	if (pVM->cpum.s.HostFeatures.fArchCap)
4923	{
4924	/* Install the architectural capabilities MSR. */
4925	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
4926	if (!pMsrRange)
4927	{
4928	static CPUMMSRRANGE const s_ArchCaps =
4929	{
4930	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
4931	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
4932	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
4933	/.szName = / "IA32_ARCH_CAPABILITIES"
4934	};
4935	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
4936	AssertLogRelRC(rc);
4937	}
4938	}
4939
4940	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
4941	}
4942	else if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4943	{
4944	/* The precise details of AMD's implementation are not yet clear. */
4945	}
4946	break;
4947
4948	default:
4949	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4950	break;
4951	}
4952
4953	/** @todo can probably kill this as this API is now init time only... */
4954	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4955	{
4956	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4957	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4958	}
4959	}
4960
4961
4962	/**
4963	* Queries a CPUID feature bit.
4964	*
4965	* @returns boolean for feature presence
4966	* @param pVM The cross context VM structure.
4967	* @param enmFeature The feature to query.
4968	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4969	*/
4970	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4971	{
4972	switch (enmFeature)
4973	{
4974	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4975	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4976	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4977	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4978	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4979	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4980	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4981	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4982	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
4983	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4984	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4985	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
4986	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
4987
4988	case CPUMCPUIDFEATURE_INVALID:
4989	case CPUMCPUIDFEATURE_32BIT_HACK:
4990	break;
4991	}
4992	AssertFailed();
4993	return false;
4994	}
4995
4996
4997	/**
4998	* Clears a CPUID feature bit.
4999	*
5000	* @param pVM The cross context VM structure.
5001	* @param enmFeature The feature to clear.
5002	*
5003	* @deprecated Probably better to default the feature to disabled and only allow
5004	* setting (enabling) it during construction.
5005	*/
5006	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
5007	{
5008	PCPUMCPUIDLEAF pLeaf;
5009	switch (enmFeature)
5010	{
5011	case CPUMCPUIDFEATURE_APIC:
5012	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
5013	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5014	if (pLeaf)
5015	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
5016
5017	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5018	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
5019	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
5020
5021	pVM->cpum.s.GuestFeatures.fApic = 0;
5022	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
5023	break;
5024
5025	case CPUMCPUIDFEATURE_X2APIC:
5026	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
5027	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5028	if (pLeaf)
5029	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
5030	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
5031	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
5032	break;
5033
5034	case CPUMCPUIDFEATURE_PAE:
5035	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5036	if (pLeaf)
5037	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
5038
5039	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5040	if ( pLeaf
5041	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
5042	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
5043
5044	pVM->cpum.s.GuestFeatures.fPae = 0;
5045	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
5046	break;
5047
5048	case CPUMCPUIDFEATURE_PAT:
5049	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5050	if (pLeaf)
5051	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
5052
5053	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5054	if ( pLeaf
5055	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
5056	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
5057
5058	pVM->cpum.s.GuestFeatures.fPat = 0;
5059	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
5060	break;
5061
5062	case CPUMCPUIDFEATURE_LONG_MODE:
5063	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5064	if (pLeaf)
5065	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
5066	pVM->cpum.s.GuestFeatures.fLongMode = 0;
5067	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = 32;
5068	if (pVM->cpum.s.GuestFeatures.fVmx)
5069	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5070	{
5071	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5072	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic \|= VMX_BASIC_PHYSADDR_WIDTH_32BIT;
5073	}
5074	break;
5075
5076	case CPUMCPUIDFEATURE_LAHF:
5077	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5078	if (pLeaf)
5079	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
5080	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
5081	break;
5082
5083	case CPUMCPUIDFEATURE_RDTSCP:
5084	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5085	if (pLeaf)
5086	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
5087	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
5088	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
5089	break;
5090
5091	case CPUMCPUIDFEATURE_HVP:
5092	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5093	if (pLeaf)
5094	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
5095	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
5096	break;
5097
5098	case CPUMCPUIDFEATURE_MWAIT_EXTS:
5099	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
5100	if (pLeaf)
5101	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
5102	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
5103	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
5104	break;
5105
5106	case CPUMCPUIDFEATURE_SPEC_CTRL:
5107	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
5108	if (pLeaf)
5109	pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP);
5110	pVM->cpum.s.GuestFeatures.fSpeculationControl = 0;
5111	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
5112	break;
5113
5114	default:
5115	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5116	break;
5117	}
5118
5119	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5120	{
5121	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5122	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5123	}
5124	}
5125
5126
5127
5128	/*
5129	*
5130	*
5131	* Saved state related code.
5132	* Saved state related code.
5133	* Saved state related code.
5134	*
5135	*
5136	*/
5137
5138	/**
5139	* Called both in pass 0 and the final pass.
5140	*
5141	* @param pVM The cross context VM structure.
5142	* @param pSSM The saved state handle.
5143	*/
5144	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
5145	{
5146	/*
5147	* Save all the CPU ID leaves.
5148	*/
5149	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
5150	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5151	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
5152	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5153
5154	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5155
5156	/*
5157	* Save a good portion of the raw CPU IDs as well as they may come in
5158	* handy when validating features for raw mode.
5159	*/
5160	CPUMCPUID aRawStd[16];
5161	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
5162	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5163	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
5164	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
5165
5166	CPUMCPUID aRawExt[32];
5167	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
5168	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5169	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
5170	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
5171	}
5172
5173
5174	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5175	{
5176	uint32_t cCpuIds;
5177	int rc = SSMR3GetU32(pSSM, &cCpuIds);
5178	if (RT_SUCCESS(rc))
5179	{
5180	if (cCpuIds < 64)
5181	{
5182	for (uint32_t i = 0; i < cCpuIds; i++)
5183	{
5184	CPUMCPUID CpuId;
5185	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
5186	if (RT_FAILURE(rc))
5187	break;
5188
5189	CPUMCPUIDLEAF NewLeaf;
5190	NewLeaf.uLeaf = uBase + i;
5191	NewLeaf.uSubLeaf = 0;
5192	NewLeaf.fSubLeafMask = 0;
5193	NewLeaf.uEax = CpuId.uEax;
5194	NewLeaf.uEbx = CpuId.uEbx;
5195	NewLeaf.uEcx = CpuId.uEcx;
5196	NewLeaf.uEdx = CpuId.uEdx;
5197	NewLeaf.fFlags = 0;
5198	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
5199	}
5200	}
5201	else
5202	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5203	}
5204	if (RT_FAILURE(rc))
5205	{
5206	RTMemFree(*ppaLeaves);
5207	*ppaLeaves = NULL;
5208	*pcLeaves = 0;
5209	}
5210	return rc;
5211	}
5212
5213
5214	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5215	{
5216	*ppaLeaves = NULL;
5217	*pcLeaves = 0;
5218
5219	int rc;
5220	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
5221	{
5222	/*
5223	* The new format. Starts by declaring the leave size and count.
5224	*/
5225	uint32_t cbLeaf;
5226	SSMR3GetU32(pSSM, &cbLeaf);
5227	uint32_t cLeaves;
5228	rc = SSMR3GetU32(pSSM, &cLeaves);
5229	if (RT_SUCCESS(rc))
5230	{
5231	if (cbLeaf == sizeof(**ppaLeaves))
5232	{
5233	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
5234	{
5235	/*
5236	* Load the leaves one by one.
5237	*
5238	* The uPrev stuff is a kludge for working around a week worth of bad saved
5239	* states during the CPUID revamp in March 2015. We saved too many leaves
5240	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
5241	* garbage entires at the end of the array when restoring. We also had
5242	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
5243	* this kludge doesn't deal correctly with that, but who cares...
5244	*/
5245	uint32_t uPrev = 0;
5246	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
5247	{
5248	CPUMCPUIDLEAF Leaf;
5249	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
5250	if (RT_SUCCESS(rc))
5251	{
5252	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
5253	\|\| Leaf.uLeaf >= uPrev)
5254	{
5255	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5256	uPrev = Leaf.uLeaf;
5257	}
5258	else
5259	uPrev = UINT32_MAX;
5260	}
5261	}
5262	}
5263	else
5264	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5265	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5266	}
5267	else
5268	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5269	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5270	}
5271	}
5272	else
5273	{
5274	/*
5275	* The old format with its three inflexible arrays.
5276	*/
5277	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5278	if (RT_SUCCESS(rc))
5279	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5280	if (RT_SUCCESS(rc))
5281	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5282	if (RT_SUCCESS(rc))
5283	{
5284	/*
5285	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5286	*/
5287	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5288	if ( pLeaf
5289	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5290	{
5291	CPUMCPUIDLEAF Leaf;
5292	Leaf.uLeaf = 4;
5293	Leaf.fSubLeafMask = UINT32_MAX;
5294	Leaf.uSubLeaf = 0;
5295	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5296	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5297	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5298	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5299	\| UINT32_C(63); /* system coherency line size - 1 */
5300	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5301	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5302	\| (UINT32_C(1) << 5) /* cache level */
5303	\| UINT32_C(1); /* cache type (data) */
5304	Leaf.fFlags = 0;
5305	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5306	if (RT_SUCCESS(rc))
5307	{
5308	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5309	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5310	}
5311	if (RT_SUCCESS(rc))
5312	{
5313	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5314	Leaf.uEcx = 4095; /* sets - 1 */
5315	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5316	Leaf.uEbx \|= UINT32_C(23) << 22;
5317	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5318	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5319	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5320	Leaf.uEax \|= UINT32_C(2) << 5;
5321	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5322	}
5323	}
5324	}
5325	}
5326	return rc;
5327	}
5328
5329
5330	/**
5331	* Loads the CPU ID leaves saved by pass 0, inner worker.
5332	*
5333	* @returns VBox status code.
5334	* @param pVM The cross context VM structure.
5335	* @param pSSM The saved state handle.
5336	* @param uVersion The format version.
5337	* @param paLeaves Guest CPUID leaves loaded from the state.
5338	* @param cLeaves The number of leaves in @a paLeaves.
5339	* @param pMsrs The guest MSRs.
5340	*/
5341	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
5342	{
5343	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5344
5345	/*
5346	* Continue loading the state into stack buffers.
5347	*/
5348	CPUMCPUID GuestDefCpuId;
5349	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5350	AssertRCReturn(rc, rc);
5351
5352	CPUMCPUID aRawStd[16];
5353	uint32_t cRawStd;
5354	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5355	if (cRawStd > RT_ELEMENTS(aRawStd))
5356	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5357	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5358	AssertRCReturn(rc, rc);
5359	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5360	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5361
5362	CPUMCPUID aRawExt[32];
5363	uint32_t cRawExt;
5364	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5365	if (cRawExt > RT_ELEMENTS(aRawExt))
5366	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5367	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5368	AssertRCReturn(rc, rc);
5369	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5370	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5371
5372	/*
5373	* Get the raw CPU IDs for the current host.
5374	*/
5375	CPUMCPUID aHostRawStd[16];
5376	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5377	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5378
5379	CPUMCPUID aHostRawExt[32];
5380	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5381	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5382	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5383
5384	/*
5385	* Get the host and guest overrides so we don't reject the state because
5386	* some feature was enabled thru these interfaces.
5387	* Note! We currently only need the feature leaves, so skip rest.
5388	*/
5389	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5390	CPUMCPUID aHostOverrideStd[2];
5391	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5392	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5393
5394	CPUMCPUID aHostOverrideExt[2];
5395	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5396	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5397
5398	/*
5399	* This can be skipped.
5400	*/
5401	bool fStrictCpuIdChecks;
5402	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5403
5404	/*
5405	* Define a bunch of macros for simplifying the santizing/checking code below.
5406	*/
5407	/* Generic expression + failure message. */
5408	#define CPUID_CHECK_RET(expr, fmt) \
5409	do { \
5410	if (!(expr)) \
5411	{ \
5412	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5413	if (fStrictCpuIdChecks) \
5414	{ \
5415	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5416	RTStrFree(pszMsg); \
5417	return rcCpuid; \
5418	} \
5419	LogRel(("CPUM: %s\n", pszMsg)); \
5420	RTStrFree(pszMsg); \
5421	} \
5422	} while (0)
5423	#define CPUID_CHECK_WRN(expr, fmt) \
5424	do { \
5425	if (!(expr)) \
5426	LogRel(fmt); \
5427	} while (0)
5428
5429	/* For comparing two values and bitch if they differs. */
5430	#define CPUID_CHECK2_RET(what, host, saved) \
5431	do { \
5432	if ((host) != (saved)) \
5433	{ \
5434	if (fStrictCpuIdChecks) \
5435	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5436	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5437	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5438	} \
5439	} while (0)
5440	#define CPUID_CHECK2_WRN(what, host, saved) \
5441	do { \
5442	if ((host) != (saved)) \
5443	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5444	} while (0)
5445
5446	/* For checking raw cpu features (raw mode). */
5447	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5448	do { \
5449	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5450	{ \
5451	if (fStrictCpuIdChecks) \
5452	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5453	N_(#bit " mismatch: host=%d saved=%d"), \
5454	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5455	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5456	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5457	} \
5458	} while (0)
5459	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5460	do { \
5461	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5462	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5463	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5464	} while (0)
5465	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5466
5467	/* For checking guest features. */
5468	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5469	do { \
5470	if ( (aGuestCpuId##set [1].reg & bit) \
5471	&& !(aHostRaw##set [1].reg & bit) \
5472	&& !(aHostOverride##set [1].reg & bit) \
5473	) \
5474	{ \
5475	if (fStrictCpuIdChecks) \
5476	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5477	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5478	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5479	} \
5480	} while (0)
5481	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5482	do { \
5483	if ( (aGuestCpuId##set [1].reg & bit) \
5484	&& !(aHostRaw##set [1].reg & bit) \
5485	&& !(aHostOverride##set [1].reg & bit) \
5486	) \
5487	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5488	} while (0)
5489	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5490	do { \
5491	if ( (aGuestCpuId##set [1].reg & bit) \
5492	&& !(aHostRaw##set [1].reg & bit) \
5493	&& !(aHostOverride##set [1].reg & bit) \
5494	) \
5495	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5496	} while (0)
5497	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5498
5499	/* For checking guest features if AMD guest CPU. */
5500	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5501	do { \
5502	if ( (aGuestCpuId##set [1].reg & bit) \
5503	&& fGuestAmd \
5504	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5505	&& !(aHostOverride##set [1].reg & bit) \
5506	) \
5507	{ \
5508	if (fStrictCpuIdChecks) \
5509	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5510	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5511	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5512	} \
5513	} while (0)
5514	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5515	do { \
5516	if ( (aGuestCpuId##set [1].reg & bit) \
5517	&& fGuestAmd \
5518	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5519	&& !(aHostOverride##set [1].reg & bit) \
5520	) \
5521	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5522	} while (0)
5523	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5524	do { \
5525	if ( (aGuestCpuId##set [1].reg & bit) \
5526	&& fGuestAmd \
5527	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5528	&& !(aHostOverride##set [1].reg & bit) \
5529	) \
5530	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5531	} while (0)
5532	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5533
5534	/* For checking AMD features which have a corresponding bit in the standard
5535	range. (Intel defines very few bits in the extended feature sets.) */
5536	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5537	do { \
5538	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5539	&& !(fHostAmd \
5540	? aHostRawExt[1].reg & (ExtBit) \
5541	: aHostRawStd[1].reg & (StdBit)) \
5542	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5543	) \
5544	{ \
5545	if (fStrictCpuIdChecks) \
5546	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5547	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5548	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5549	} \
5550	} while (0)
5551	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5552	do { \
5553	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5554	&& !(fHostAmd \
5555	? aHostRawExt[1].reg & (ExtBit) \
5556	: aHostRawStd[1].reg & (StdBit)) \
5557	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5558	) \
5559	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5560	} while (0)
5561	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5562	do { \
5563	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5564	&& !(fHostAmd \
5565	? aHostRawExt[1].reg & (ExtBit) \
5566	: aHostRawStd[1].reg & (StdBit)) \
5567	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5568	) \
5569	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5570	} while (0)
5571	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5572
5573
5574	/*
5575	* Verify that we can support the features already exposed to the guest on
5576	* this host.
5577	*
5578	* Most of the features we're emulating requires intercepting instruction
5579	* and doing it the slow way, so there is no need to warn when they aren't
5580	* present in the host CPU. Thus we use IGN instead of EMU on these.
5581	*
5582	* Trailing comments:
5583	* "EMU" - Possible to emulate, could be lots of work and very slow.
5584	* "EMU?" - Can this be emulated?
5585	*/
5586	CPUMCPUID aGuestCpuIdStd[2];
5587	RT_ZERO(aGuestCpuIdStd);
5588	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5589
5590	/* CPUID(1).ecx */
5591	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5592	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5593	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5594	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5595	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5596	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5597	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5598	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5599	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5600	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5601	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5602	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5603	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5604	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5605	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5606	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5607	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5608	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5609	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5610	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5611	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5612	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5613	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5614	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5615	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5616	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5617	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5618	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5619	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5620	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5621	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5622	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5623
5624	/* CPUID(1).edx */
5625	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5626	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5627	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5628	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5629	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5630	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5631	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5632	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5633	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5634	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5635	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5636	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5637	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5638	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5639	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5640	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5641	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5642	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5643	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5644	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5645	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5646	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5647	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5648	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5649	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5650	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5651	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5652	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5653	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5654	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5655	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5656	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5657
5658	/* CPUID(0x80000000). */
5659	CPUMCPUID aGuestCpuIdExt[2];
5660	RT_ZERO(aGuestCpuIdExt);
5661	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5662	{
5663	/** @todo deal with no 0x80000001 on the host. */
5664	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5665	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5666
5667	/* CPUID(0x80000001).ecx */
5668	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5669	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5670	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5671	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5672	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5673	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5674	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5675	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5676	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5677	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5678	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5679	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5680	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5681	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5682	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5683	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5684	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5685	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5686	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5687	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5688	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5689	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5690	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5691	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5692	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5693	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5694	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5695	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5696	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5697	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5698	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5699	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5700
5701	/* CPUID(0x80000001).edx */
5702	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5703	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5704	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5705	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5706	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5707	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5708	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5709	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5710	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5711	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5712	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5713	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5714	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5715	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5716	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5717	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5718	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5719	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5720	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5721	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5722	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5723	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5724	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5725	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5726	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5727	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5728	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5729	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5730	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5731	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5732	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5733	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5734	}
5735
5736	/** @todo check leaf 7 */
5737
5738	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5739	* ECX=0: EAX - Valid bits in XCR0[31:0].
5740	* EBX - Maximum state size as per current XCR0 value.
5741	* ECX - Maximum state size for all supported features.
5742	* EDX - Valid bits in XCR0[63:32].
5743	* ECX=1: EAX - Various X-features.
5744	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5745	* ECX - Valid bits in IA32_XSS[31:0].
5746	* EDX - Valid bits in IA32_XSS[63:32].
5747	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5748	* if the bit invalid all four registers are set to zero.
5749	* EAX - The state size for this feature.
5750	* EBX - The state byte offset of this feature.
5751	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5752	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5753	*/
5754	uint64_t fGuestXcr0Mask = 0;
5755	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5756	if ( pCurLeaf
5757	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5758	&& ( pCurLeaf->uEax
5759	\|\| pCurLeaf->uEbx
5760	\|\| pCurLeaf->uEcx
5761	\|\| pCurLeaf->uEdx) )
5762	{
5763	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5764	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5765	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5766	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5767	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5768	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5769	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5770	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5771
5772	/* We don't support any additional features yet. */
5773	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5774	if (pCurLeaf && pCurLeaf->uEax)
5775	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5776	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5777	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5778	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5779	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5780	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5781
5782
5783	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5784	{
5785	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5786	if (pCurLeaf)
5787	{
5788	/* If advertised, the state component offset and size must match the one used by host. */
5789	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5790	{
5791	CPUMCPUID RawHost;
5792	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5793	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5794	if ( RawHost.uEbx != pCurLeaf->uEbx
5795	\|\| RawHost.uEax != pCurLeaf->uEax)
5796	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5797	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5798	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5799	}
5800	}
5801	}
5802	}
5803	/* Clear leaf 0xd just in case we're loading an old state... */
5804	else if (pCurLeaf)
5805	{
5806	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5807	{
5808	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5809	if (pCurLeaf)
5810	{
5811	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5812	\|\| ( pCurLeaf->uEax == 0
5813	&& pCurLeaf->uEbx == 0
5814	&& pCurLeaf->uEcx == 0
5815	&& pCurLeaf->uEdx == 0),
5816	("uVersion=%#x; %#x %#x %#x %#x\n",
5817	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5818	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5819	}
5820	}
5821	}
5822
5823	/* Update the fXStateGuestMask value for the VM. */
5824	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5825	{
5826	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5827	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5828	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5829	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5830	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5831	}
5832
5833	#undef CPUID_CHECK_RET
5834	#undef CPUID_CHECK_WRN
5835	#undef CPUID_CHECK2_RET
5836	#undef CPUID_CHECK2_WRN
5837	#undef CPUID_RAW_FEATURE_RET
5838	#undef CPUID_RAW_FEATURE_WRN
5839	#undef CPUID_RAW_FEATURE_IGN
5840	#undef CPUID_GST_FEATURE_RET
5841	#undef CPUID_GST_FEATURE_WRN
5842	#undef CPUID_GST_FEATURE_EMU
5843	#undef CPUID_GST_FEATURE_IGN
5844	#undef CPUID_GST_FEATURE2_RET
5845	#undef CPUID_GST_FEATURE2_WRN
5846	#undef CPUID_GST_FEATURE2_EMU
5847	#undef CPUID_GST_FEATURE2_IGN
5848	#undef CPUID_GST_AMD_FEATURE_RET
5849	#undef CPUID_GST_AMD_FEATURE_WRN
5850	#undef CPUID_GST_AMD_FEATURE_EMU
5851	#undef CPUID_GST_AMD_FEATURE_IGN
5852
5853	/*
5854	* We're good, commit the CPU ID leaves.
5855	*/
5856	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5857	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5858	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5859	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5860	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
5861	AssertLogRelRCReturn(rc, rc);
5862
5863	return VINF_SUCCESS;
5864	}
5865
5866
5867	/**
5868	* Loads the CPU ID leaves saved by pass 0.
5869	*
5870	* @returns VBox status code.
5871	* @param pVM The cross context VM structure.
5872	* @param pSSM The saved state handle.
5873	* @param uVersion The format version.
5874	* @param pMsrs The guest MSRs.
5875	*/
5876	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
5877	{
5878	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5879
5880	/*
5881	* Load the CPUID leaves array first and call worker to do the rest, just so
5882	* we can free the memory when we need to without ending up in column 1000.
5883	*/
5884	PCPUMCPUIDLEAF paLeaves;
5885	uint32_t cLeaves;
5886	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5887	AssertRC(rc);
5888	if (RT_SUCCESS(rc))
5889	{
5890	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
5891	RTMemFree(paLeaves);
5892	}
5893	return rc;
5894	}
5895
5896
5897
5898	/**
5899	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5900	*
5901	* @returns VBox status code.
5902	* @param pVM The cross context VM structure.
5903	* @param pSSM The saved state handle.
5904	* @param uVersion The format version.
5905	*/
5906	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5907	{
5908	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5909
5910	/*
5911	* Restore the CPUID leaves.
5912	*
5913	* Note that we support restoring less than the current amount of standard
5914	* leaves because we've been allowed more is newer version of VBox.
5915	*/
5916	uint32_t cElements;
5917	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5918	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5919	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5920	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5921
5922	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5923	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5924	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5925	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5926
5927	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5928	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5929	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5930	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5931
5932	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5933
5934	/*
5935	* Check that the basic cpuid id information is unchanged.
5936	*/
5937	/** @todo we should check the 64 bits capabilities too! */
5938	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5939	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5940	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5941	uint32_t au32CpuIdSaved[8];
5942	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5943	if (RT_SUCCESS(rc))
5944	{
5945	/* Ignore CPU stepping. */
5946	au32CpuId[4] &= 0xfffffff0;
5947	au32CpuIdSaved[4] &= 0xfffffff0;
5948
5949	/* Ignore APIC ID (AMD specs). */
5950	au32CpuId[5] &= ~0xff000000;
5951	au32CpuIdSaved[5] &= ~0xff000000;
5952
5953	/* Ignore the number of Logical CPUs (AMD specs). */
5954	au32CpuId[5] &= ~0x00ff0000;
5955	au32CpuIdSaved[5] &= ~0x00ff0000;
5956
5957	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5958	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5959	\| X86_CPUID_FEATURE_ECX_VMX
5960	\| X86_CPUID_FEATURE_ECX_SMX
5961	\| X86_CPUID_FEATURE_ECX_EST
5962	\| X86_CPUID_FEATURE_ECX_TM2
5963	\| X86_CPUID_FEATURE_ECX_CNTXID
5964	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5965	\| X86_CPUID_FEATURE_ECX_PDCM
5966	\| X86_CPUID_FEATURE_ECX_DCA
5967	\| X86_CPUID_FEATURE_ECX_X2APIC
5968	);
5969	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5970	\| X86_CPUID_FEATURE_ECX_VMX
5971	\| X86_CPUID_FEATURE_ECX_SMX
5972	\| X86_CPUID_FEATURE_ECX_EST
5973	\| X86_CPUID_FEATURE_ECX_TM2
5974	\| X86_CPUID_FEATURE_ECX_CNTXID
5975	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5976	\| X86_CPUID_FEATURE_ECX_PDCM
5977	\| X86_CPUID_FEATURE_ECX_DCA
5978	\| X86_CPUID_FEATURE_ECX_X2APIC
5979	);
5980
5981	/* Make sure we don't forget to update the masks when enabling
5982	* features in the future.
5983	*/
5984	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5985	( X86_CPUID_FEATURE_ECX_DTES64
5986	\| X86_CPUID_FEATURE_ECX_VMX
5987	\| X86_CPUID_FEATURE_ECX_SMX
5988	\| X86_CPUID_FEATURE_ECX_EST
5989	\| X86_CPUID_FEATURE_ECX_TM2
5990	\| X86_CPUID_FEATURE_ECX_CNTXID
5991	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5992	\| X86_CPUID_FEATURE_ECX_PDCM
5993	\| X86_CPUID_FEATURE_ECX_DCA
5994	\| X86_CPUID_FEATURE_ECX_X2APIC
5995	)));
5996	/* do the compare */
5997	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5998	{
5999	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
6000	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
6001	"Saved=%.*Rhxs\n"
6002	"Real =%.*Rhxs\n",
6003	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6004	sizeof(au32CpuId), au32CpuId));
6005	else
6006	{
6007	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
6008	"Saved=%.*Rhxs\n"
6009	"Real =%.*Rhxs\n",
6010	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6011	sizeof(au32CpuId), au32CpuId));
6012	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
6013	}
6014	}
6015	}
6016
6017	return rc;
6018	}
6019
6020
6021
6022	/*
6023	*
6024	*
6025	* CPUID Info Handler.
6026	* CPUID Info Handler.
6027	* CPUID Info Handler.
6028	*
6029	*
6030	*/
6031
6032
6033
6034	/**
6035	* Get L1 cache / TLS associativity.
6036	*/
6037	static const char getCacheAss(unsigned u, char pszBuf)
6038	{
6039	if (u == 0)
6040	return "res0 ";
6041	if (u == 1)
6042	return "direct";
6043	if (u == 255)
6044	return "fully";
6045	if (u >= 256)
6046	return "???";
6047
6048	RTStrPrintf(pszBuf, 16, "%d way", u);
6049	return pszBuf;
6050	}
6051
6052
6053	/**
6054	* Get L2 cache associativity.
6055	*/
6056	const char *getL2CacheAss(unsigned u)
6057	{
6058	switch (u)
6059	{
6060	case 0: return "off ";
6061	case 1: return "direct";
6062	case 2: return "2 way ";
6063	case 3: return "res3 ";
6064	case 4: return "4 way ";
6065	case 5: return "res5 ";
6066	case 6: return "8 way ";
6067	case 7: return "res7 ";
6068	case 8: return "16 way";
6069	case 9: return "res9 ";
6070	case 10: return "res10 ";
6071	case 11: return "res11 ";
6072	case 12: return "res12 ";
6073	case 13: return "res13 ";
6074	case 14: return "res14 ";
6075	case 15: return "fully ";
6076	default: return "????";
6077	}
6078	}
6079
6080
6081	/** CPUID(1).EDX field descriptions. */
6082	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6083	{
6084	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6085	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6086	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6087	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6088	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6089	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6090	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6091	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6092	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6093	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6094	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6095	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6096	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6097	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6098	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6099	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6100	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6101	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6102	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6103	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6104	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6105	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6106	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6107	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6108	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6109	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6110	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6111	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6112	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6113	DBGFREGSUBFIELD_TERMINATOR()
6114	};
6115
6116	/** CPUID(1).ECX field descriptions. */
6117	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6118	{
6119	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6120	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6121	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6122	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6123	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6124	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6125	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6126	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6127	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6128	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6129	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6130	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6131	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6132	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6133	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6134	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6135	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6136	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6137	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6138	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6139	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6140	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6141	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6142	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6143	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6144	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6145	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6146	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6147	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6148	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6149	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6150	DBGFREGSUBFIELD_TERMINATOR()
6151	};
6152
6153	/** CPUID(7,0).EBX field descriptions. */
6154	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6155	{
6156	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6157	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6158	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6159	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6160	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6161	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6162	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6163	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6164	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6165	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6166	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6167	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6168	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6169	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6170	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6171	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6172	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6173	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6174	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6175	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6176	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6177	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6178	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6179	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6180	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6181	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6182	DBGFREGSUBFIELD_TERMINATOR()
6183	};
6184
6185	/** CPUID(7,0).ECX field descriptions. */
6186	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6187	{
6188	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6189	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6190	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6191	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6192	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6193	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6194	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6195	DBGFREGSUBFIELD_TERMINATOR()
6196	};
6197
6198	/** CPUID(7,0).EDX field descriptions. */
6199	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6200	{
6201	DBGFREGSUBFIELD_RO("MD_CLEAR\0" "Supports MDS related buffer clearing", 10, 1, 0),
6202	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6203	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6204	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
6205	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6206	DBGFREGSUBFIELD_TERMINATOR()
6207	};
6208
6209
6210	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6211	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6212	{
6213	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6214	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6215	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6216	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6217	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6218	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6219	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6220	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6221	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6222	DBGFREGSUBFIELD_TERMINATOR()
6223	};
6224
6225	/** CPUID(13,1).EAX field descriptions. */
6226	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6227	{
6228	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6229	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6230	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6231	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6232	DBGFREGSUBFIELD_TERMINATOR()
6233	};
6234
6235
6236	/** CPUID(0x80000001,0).EDX field descriptions. */
6237	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6238	{
6239	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6240	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6241	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6242	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6243	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6244	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6245	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6246	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6247	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6248	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6249	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6250	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6251	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6252	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6253	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6254	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6255	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6256	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6257	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6258	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6259	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6260	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6261	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6262	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6263	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6264	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6265	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6266	DBGFREGSUBFIELD_TERMINATOR()
6267	};
6268
6269	/** CPUID(0x80000001,0).ECX field descriptions. */
6270	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6271	{
6272	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6273	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6274	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6275	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6276	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6277	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6278	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6279	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6280	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6281	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6282	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6283	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6284	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6285	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6286	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6287	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6288	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6289	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6290	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6291	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6292	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6293	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6294	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6295	DBGFREGSUBFIELD_TERMINATOR()
6296	};
6297
6298	/** CPUID(0x8000000a,0).EDX field descriptions. */
6299	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
6300	{
6301	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
6302	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
6303	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
6304	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
6305	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
6306	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
6307	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
6308	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
6309	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
6310	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
6311	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
6312	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
6313	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
6314	DBGFREGSUBFIELD_TERMINATOR()
6315	};
6316
6317
6318	/** CPUID(0x80000007,0).EDX field descriptions. */
6319	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6320	{
6321	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6322	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6323	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6324	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6325	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6326	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6327	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6328	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6329	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6330	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6331	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6332	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6333	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6334	DBGFREGSUBFIELD_TERMINATOR()
6335	};
6336
6337	/** CPUID(0x80000008,0).EBX field descriptions. */
6338	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6339	{
6340	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6341	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6342	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6343	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6344	DBGFREGSUBFIELD_TERMINATOR()
6345	};
6346
6347
6348	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6349	const char *pszLeadIn, uint32_t cchWidth)
6350	{
6351	if (pszLeadIn)
6352	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6353
6354	for (uint32_t iBit = 0; iBit < 32; iBit++)
6355	if (RT_BIT_32(iBit) & uVal)
6356	{
6357	while ( pDesc->pszName != NULL
6358	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6359	pDesc++;
6360	if ( pDesc->pszName != NULL
6361	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6362	{
6363	if (pDesc->cBits == 1)
6364	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6365	else
6366	{
6367	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6368	if (pDesc->cBits < 32)
6369	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6370	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6371	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6372	}
6373	}
6374	else
6375	pHlp->pfnPrintf(pHlp, " %u", iBit);
6376	}
6377	if (pszLeadIn)
6378	pHlp->pfnPrintf(pHlp, "\n");
6379	}
6380
6381
6382	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6383	const char *pszLeadIn, uint32_t cchWidth)
6384	{
6385	if (pszLeadIn)
6386	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6387
6388	for (uint32_t iBit = 0; iBit < 64; iBit++)
6389	if (RT_BIT_64(iBit) & uVal)
6390	{
6391	while ( pDesc->pszName != NULL
6392	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6393	pDesc++;
6394	if ( pDesc->pszName != NULL
6395	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6396	{
6397	if (pDesc->cBits == 1)
6398	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6399	else
6400	{
6401	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6402	if (pDesc->cBits < 64)
6403	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6404	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6405	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6406	}
6407	}
6408	else
6409	pHlp->pfnPrintf(pHlp, " %u", iBit);
6410	}
6411	if (pszLeadIn)
6412	pHlp->pfnPrintf(pHlp, "\n");
6413	}
6414
6415
6416	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6417	const char *pszLeadIn, uint32_t cchWidth)
6418	{
6419	if (!uVal)
6420	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6421	else
6422	{
6423	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6424	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6425	pHlp->pfnPrintf(pHlp, " )\n");
6426	}
6427	}
6428
6429
6430	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6431	uint32_t cchWidth)
6432	{
6433	uint32_t uCombined = uVal1 \| uVal2;
6434	for (uint32_t iBit = 0; iBit < 32; iBit++)
6435	if ( (RT_BIT_32(iBit) & uCombined)
6436	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6437	{
6438	while ( pDesc->pszName != NULL
6439	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6440	pDesc++;
6441
6442	if ( pDesc->pszName != NULL
6443	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6444	{
6445	size_t cchMnemonic = strlen(pDesc->pszName);
6446	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6447	size_t cchDesc = strlen(pszDesc);
6448	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6449	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6450	if (pDesc->cBits < 32)
6451	{
6452	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6453	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6454	}
6455
6456	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6457	pDesc->pszName, pszDesc,
6458	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6459	uFieldValue1, uFieldValue2);
6460
6461	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6462	pDesc++;
6463	}
6464	else
6465	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6466	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6467	}
6468	}
6469
6470
6471	/**
6472	* Produces a detailed summary of standard leaf 0x00000001.
6473	*
6474	* @param pHlp The info helper functions.
6475	* @param pCurLeaf The 0x00000001 leaf.
6476	* @param fVerbose Whether to be very verbose or not.
6477	* @param fIntel Set if intel CPU.
6478	*/
6479	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6480	{
6481	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6482	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6483	uint32_t uEAX = pCurLeaf->uEax;
6484	uint32_t uEBX = pCurLeaf->uEbx;
6485
6486	pHlp->pfnPrintf(pHlp,
6487	"%36s %2d \tExtended: %d \tEffective: %d\n"
6488	"%36s %2d \tExtended: %d \tEffective: %d\n"
6489	"%36s %d\n"
6490	"%36s %d (%s)\n"
6491	"%36s %#04x\n"
6492	"%36s %d\n"
6493	"%36s %d\n"
6494	"%36s %#04x\n"
6495	,
6496	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6497	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6498	"Stepping:", ASMGetCpuStepping(uEAX),
6499	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6500	"APIC ID:", (uEBX >> 24) & 0xff,
6501	"Logical CPUs:",(uEBX >> 16) & 0xff,
6502	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6503	"Brand ID:", (uEBX >> 0) & 0xff);
6504	if (fVerbose)
6505	{
6506	CPUMCPUID Host;
6507	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6508	pHlp->pfnPrintf(pHlp, "Features\n");
6509	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6510	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6511	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6512	}
6513	else
6514	{
6515	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6516	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6517	}
6518	}
6519
6520
6521	/**
6522	* Produces a detailed summary of standard leaf 0x00000007.
6523	*
6524	* @param pHlp The info helper functions.
6525	* @param paLeaves The CPUID leaves array.
6526	* @param cLeaves The number of leaves in the array.
6527	* @param pCurLeaf The first 0x00000007 leaf.
6528	* @param fVerbose Whether to be very verbose or not.
6529	*/
6530	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6531	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6532	{
6533	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6534	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6535	for (;;)
6536	{
6537	CPUMCPUID Host;
6538	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6539
6540	switch (pCurLeaf->uSubLeaf)
6541	{
6542	case 0:
6543	if (fVerbose)
6544	{
6545	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6546	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6547	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6548	if (pCurLeaf->uEdx \|\| Host.uEdx)
6549	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6550	}
6551	else
6552	{
6553	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6554	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6555	if (pCurLeaf->uEdx)
6556	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6557	}
6558	break;
6559
6560	default:
6561	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6562	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6563	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6564	break;
6565
6566	}
6567
6568	/* advance. */
6569	pCurLeaf++;
6570	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6571	\|\| pCurLeaf->uLeaf != 0x7)
6572	break;
6573	}
6574	}
6575
6576
6577	/**
6578	* Produces a detailed summary of standard leaf 0x0000000d.
6579	*
6580	* @param pHlp The info helper functions.
6581	* @param paLeaves The CPUID leaves array.
6582	* @param cLeaves The number of leaves in the array.
6583	* @param pCurLeaf The first 0x00000007 leaf.
6584	* @param fVerbose Whether to be very verbose or not.
6585	*/
6586	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6587	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6588	{
6589	RT_NOREF_PV(fVerbose);
6590	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6591	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6592	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6593	{
6594	CPUMCPUID Host;
6595	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6596
6597	switch (uSubLeaf)
6598	{
6599	case 0:
6600	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6601	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6602	pCurLeaf->uEbx, pCurLeaf->uEcx);
6603	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6604
6605	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6606	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6607	"Valid XCR0 bits, guest:", 42);
6608	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6609	"Valid XCR0 bits, host:", 42);
6610	break;
6611
6612	case 1:
6613	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6614	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6615	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6616
6617	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6618	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6619	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6620
6621	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6622	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6623	" Valid IA32_XSS bits, guest:", 42);
6624	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6625	" Valid IA32_XSS bits, host:", 42);
6626	break;
6627
6628	default:
6629	if ( pCurLeaf
6630	&& pCurLeaf->uSubLeaf == uSubLeaf
6631	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6632	{
6633	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6634	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6635	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6636	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6637	if (pCurLeaf->uEdx)
6638	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6639	pHlp->pfnPrintf(pHlp, " --");
6640	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6641	pHlp->pfnPrintf(pHlp, "\n");
6642	}
6643	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6644	{
6645	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6646	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6647	if (Host.uEcx & ~RT_BIT_32(0))
6648	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6649	if (Host.uEdx)
6650	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6651	pHlp->pfnPrintf(pHlp, " --");
6652	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6653	pHlp->pfnPrintf(pHlp, "\n");
6654	}
6655	break;
6656
6657	}
6658
6659	/* advance. */
6660	if (pCurLeaf)
6661	{
6662	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6663	&& pCurLeaf->uSubLeaf <= uSubLeaf
6664	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6665	pCurLeaf++;
6666	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6667	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6668	pCurLeaf = NULL;
6669	}
6670	}
6671	}
6672
6673
6674	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6675	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6676	{
6677	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6678	&& pCurLeaf->uLeaf <= uUpToLeaf)
6679	{
6680	pHlp->pfnPrintf(pHlp,
6681	" %s\n"
6682	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6683	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6684	&& pCurLeaf->uLeaf <= uUpToLeaf)
6685	{
6686	CPUMCPUID Host;
6687	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6688	pHlp->pfnPrintf(pHlp,
6689	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6690	"Hst: %08x %08x %08x %08x\n",
6691	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6692	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6693	pCurLeaf++;
6694	}
6695	}
6696
6697	return pCurLeaf;
6698	}
6699
6700
6701	/**
6702	* Display the guest CpuId leaves.
6703	*
6704	* @param pVM The cross context VM structure.
6705	* @param pHlp The info helper functions.
6706	* @param pszArgs "terse", "default" or "verbose".
6707	*/
6708	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6709	{
6710	/*
6711	* Parse the argument.
6712	*/
6713	unsigned iVerbosity = 1;
6714	if (pszArgs)
6715	{
6716	pszArgs = RTStrStripL(pszArgs);
6717	if (!strcmp(pszArgs, "terse"))
6718	iVerbosity--;
6719	else if (!strcmp(pszArgs, "verbose"))
6720	iVerbosity++;
6721	}
6722
6723	uint32_t uLeaf;
6724	CPUMCPUID Host;
6725	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6726	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6727	PCCPUMCPUIDLEAF pCurLeaf;
6728	PCCPUMCPUIDLEAF pNextLeaf;
6729	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6730	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6731	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6732
6733	/*
6734	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6735	*/
6736	uint32_t cHstMax = ASMCpuId_EAX(0);
6737	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6738	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6739	pHlp->pfnPrintf(pHlp,
6740	" Raw Standard CPUID Leaves\n"
6741	" Leaf/sub-leaf eax ebx ecx edx\n");
6742	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6743	{
6744	uint32_t cMaxSubLeaves = 1;
6745	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6746	cMaxSubLeaves = 16;
6747	else if (uLeaf == 0xd)
6748	cMaxSubLeaves = 128;
6749
6750	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6751	{
6752	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6753	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6754	&& pCurLeaf->uLeaf == uLeaf
6755	&& pCurLeaf->uSubLeaf == uSubLeaf)
6756	{
6757	pHlp->pfnPrintf(pHlp,
6758	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6759	"Hst: %08x %08x %08x %08x\n",
6760	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6761	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6762	pCurLeaf++;
6763	}
6764	else if ( uLeaf != 0xd
6765	\|\| uSubLeaf <= 1
6766	\|\| Host.uEbx != 0 )
6767	pHlp->pfnPrintf(pHlp,
6768	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6769	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6770
6771	/* Done? */
6772	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6773	\|\| pCurLeaf->uLeaf != uLeaf)
6774	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6775	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6776	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6777	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6778	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6779	)
6780	)
6781	break;
6782	}
6783	}
6784	pNextLeaf = pCurLeaf;
6785
6786	/*
6787	* If verbose, decode it.
6788	*/
6789	if (iVerbosity && paLeaves[0].uLeaf == 0)
6790	pHlp->pfnPrintf(pHlp,
6791	"%36s %.04s%.04s%.04s\n"
6792	"%36s 0x00000000-%#010x\n"
6793	,
6794	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6795	"Supports:", paLeaves[0].uEax);
6796
6797	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6798	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6799
6800	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6801	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6802
6803	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6804	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6805
6806	pCurLeaf = pNextLeaf;
6807
6808	/*
6809	* Hypervisor leaves.
6810	*
6811	* Unlike most of the other leaves reported, the guest hypervisor leaves
6812	* aren't a subset of the host CPUID bits.
6813	*/
6814	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6815
6816	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6817	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6818	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6819	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6820	cMax = RT_MAX(cHstMax, cGstMax);
6821	if (cMax >= UINT32_C(0x40000000))
6822	{
6823	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6824
6825	/** @todo dump these in more detail. */
6826
6827	pCurLeaf = pNextLeaf;
6828	}
6829
6830
6831	/*
6832	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6833	* Implemented after AMD specs.
6834	*/
6835	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6836
6837	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6838	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6839	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6840	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6841	cMax = RT_MAX(cHstMax, cGstMax);
6842	if (cMax >= UINT32_C(0x80000000))
6843	{
6844
6845	pHlp->pfnPrintf(pHlp,
6846	" Raw Extended CPUID Leaves\n"
6847	" Leaf/sub-leaf eax ebx ecx edx\n");
6848	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6849	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6850	{
6851	uint32_t cMaxSubLeaves = 1;
6852	if (uLeaf == UINT32_C(0x8000001d))
6853	cMaxSubLeaves = 16;
6854
6855	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6856	{
6857	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6858	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6859	&& pCurLeaf->uLeaf == uLeaf
6860	&& pCurLeaf->uSubLeaf == uSubLeaf)
6861	{
6862	pHlp->pfnPrintf(pHlp,
6863	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6864	"Hst: %08x %08x %08x %08x\n",
6865	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6866	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6867	pCurLeaf++;
6868	}
6869	else if ( uLeaf != 0xd
6870	\|\| uSubLeaf <= 1
6871	\|\| Host.uEbx != 0 )
6872	pHlp->pfnPrintf(pHlp,
6873	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6874	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6875
6876	/* Done? */
6877	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6878	\|\| pCurLeaf->uLeaf != uLeaf)
6879	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6880	break;
6881	}
6882	}
6883	pNextLeaf = pCurLeaf;
6884
6885	/*
6886	* Understandable output
6887	*/
6888	if (iVerbosity)
6889	pHlp->pfnPrintf(pHlp,
6890	"Ext Name: %.4s%.4s%.4s\n"
6891	"Ext Supports: 0x80000000-%#010x\n",
6892	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6893
6894	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6895	if (iVerbosity && pCurLeaf)
6896	{
6897	uint32_t uEAX = pCurLeaf->uEax;
6898	pHlp->pfnPrintf(pHlp,
6899	"Family: %d \tExtended: %d \tEffective: %d\n"
6900	"Model: %d \tExtended: %d \tEffective: %d\n"
6901	"Stepping: %d\n"
6902	"Brand ID: %#05x\n",
6903	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6904	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6905	ASMGetCpuStepping(uEAX),
6906	pCurLeaf->uEbx & 0xfff);
6907
6908	if (iVerbosity == 1)
6909	{
6910	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6911	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6912	}
6913	else
6914	{
6915	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6916	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6917	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6918	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6919	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6920	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
6921	{
6922	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
6923	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6924	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
6925	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
6926	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
6927	}
6928	}
6929	}
6930
6931	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6932	{
6933	char szString[443+1] = {0};
6934	uint32_t pu32 = (uint32_t )szString;
6935	*pu32++ = pCurLeaf->uEax;
6936	*pu32++ = pCurLeaf->uEbx;
6937	*pu32++ = pCurLeaf->uEcx;
6938	*pu32++ = pCurLeaf->uEdx;
6939	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6940	if (pCurLeaf)
6941	{
6942	*pu32++ = pCurLeaf->uEax;
6943	*pu32++ = pCurLeaf->uEbx;
6944	*pu32++ = pCurLeaf->uEcx;
6945	*pu32++ = pCurLeaf->uEdx;
6946	}
6947	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6948	if (pCurLeaf)
6949	{
6950	*pu32++ = pCurLeaf->uEax;
6951	*pu32++ = pCurLeaf->uEbx;
6952	*pu32++ = pCurLeaf->uEcx;
6953	*pu32++ = pCurLeaf->uEdx;
6954	}
6955	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6956	}
6957
6958	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6959	{
6960	uint32_t uEAX = pCurLeaf->uEax;
6961	uint32_t uEBX = pCurLeaf->uEbx;
6962	uint32_t uECX = pCurLeaf->uEcx;
6963	uint32_t uEDX = pCurLeaf->uEdx;
6964	char sz1[32];
6965	char sz2[32];
6966
6967	pHlp->pfnPrintf(pHlp,
6968	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6969	"TLB 2/4M Data: %s %3d entries\n",
6970	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6971	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6972	pHlp->pfnPrintf(pHlp,
6973	"TLB 4K Instr/Uni: %s %3d entries\n"
6974	"TLB 4K Data: %s %3d entries\n",
6975	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6976	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6977	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6978	"L1 Instr Cache Lines Per Tag: %d\n"
6979	"L1 Instr Cache Associativity: %s\n"
6980	"L1 Instr Cache Size: %d KB\n",
6981	(uEDX >> 0) & 0xff,
6982	(uEDX >> 8) & 0xff,
6983	getCacheAss((uEDX >> 16) & 0xff, sz1),
6984	(uEDX >> 24) & 0xff);
6985	pHlp->pfnPrintf(pHlp,
6986	"L1 Data Cache Line Size: %d bytes\n"
6987	"L1 Data Cache Lines Per Tag: %d\n"
6988	"L1 Data Cache Associativity: %s\n"
6989	"L1 Data Cache Size: %d KB\n",
6990	(uECX >> 0) & 0xff,
6991	(uECX >> 8) & 0xff,
6992	getCacheAss((uECX >> 16) & 0xff, sz1),
6993	(uECX >> 24) & 0xff);
6994	}
6995
6996	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6997	{
6998	uint32_t uEAX = pCurLeaf->uEax;
6999	uint32_t uEBX = pCurLeaf->uEbx;
7000	uint32_t uEDX = pCurLeaf->uEdx;
7001
7002	pHlp->pfnPrintf(pHlp,
7003	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
7004	"L2 TLB 2/4M Data: %s %4d entries\n",
7005	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
7006	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
7007	pHlp->pfnPrintf(pHlp,
7008	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
7009	"L2 TLB 4K Data: %s %4d entries\n",
7010	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
7011	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
7012	pHlp->pfnPrintf(pHlp,
7013	"L2 Cache Line Size: %d bytes\n"
7014	"L2 Cache Lines Per Tag: %d\n"
7015	"L2 Cache Associativity: %s\n"
7016	"L2 Cache Size: %d KB\n",
7017	(uEDX >> 0) & 0xff,
7018	(uEDX >> 8) & 0xf,
7019	getL2CacheAss((uEDX >> 12) & 0xf),
7020	(uEDX >> 16) & 0xffff);
7021	}
7022
7023	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
7024	{
7025	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7026	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
7027	{
7028	if (iVerbosity < 1)
7029	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
7030	else
7031	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
7032	}
7033	}
7034
7035	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
7036	if (pCurLeaf != NULL)
7037	{
7038	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7039	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
7040	{
7041	if (iVerbosity < 1)
7042	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
7043	else
7044	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
7045	}
7046
7047	if (iVerbosity)
7048	{
7049	uint32_t uEAX = pCurLeaf->uEax;
7050	uint32_t uECX = pCurLeaf->uEcx;
7051
7052	pHlp->pfnPrintf(pHlp,
7053	"Physical Address Width: %d bits\n"
7054	"Virtual Address Width: %d bits\n"
7055	"Guest Physical Address Width: %d bits\n",
7056	(uEAX >> 0) & 0xff,
7057	(uEAX >> 8) & 0xff,
7058	(uEAX >> 16) & 0xff);
7059	pHlp->pfnPrintf(pHlp,
7060	"Physical Core Count: %d\n",
7061	((uECX >> 0) & 0xff) + 1);
7062	}
7063	}
7064
7065	pCurLeaf = pNextLeaf;
7066	}
7067
7068
7069
7070	/*
7071	* Centaur.
7072	*/
7073	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7074
7075	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7076	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7077	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7078	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7079	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7080	cMax = RT_MAX(cHstMax, cGstMax);
7081	if (cMax >= UINT32_C(0xc0000000))
7082	{
7083	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7084
7085	/*
7086	* Understandable output
7087	*/
7088	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7089	pHlp->pfnPrintf(pHlp,
7090	"Centaur Supports: 0xc0000000-%#010x\n",
7091	pCurLeaf->uEax);
7092
7093	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7094	{
7095	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7096	uint32_t uEdxGst = pCurLeaf->uEdx;
7097	uint32_t uEdxHst = Host.uEdx;
7098
7099	if (iVerbosity == 1)
7100	{
7101	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7102	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7103	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7104	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7105	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7106	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7107	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7108	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7109	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7110	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7111	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7112	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7113	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7114	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7115	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7116	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7117	for (unsigned iBit = 14; iBit < 32; iBit++)
7118	if (uEdxGst & RT_BIT(iBit))
7119	pHlp->pfnPrintf(pHlp, " %d", iBit);
7120	pHlp->pfnPrintf(pHlp, "\n");
7121	}
7122	else
7123	{
7124	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7125	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7126	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7127	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7128	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7129	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7130	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7131	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7132	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7133	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7134	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7135	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7136	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7137	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7138	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7139	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7140	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7141	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7142	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7143	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7144	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7145	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7146	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7147	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7148	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7149	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7150	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7151	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7152	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7153	for (unsigned iBit = 27; iBit < 32; iBit++)
7154	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7155	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7156	pHlp->pfnPrintf(pHlp, "\n");
7157	}
7158	}
7159
7160	pCurLeaf = pNextLeaf;
7161	}
7162
7163	/*
7164	* The remainder.
7165	*/
7166	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7167	}
7168
7169	#endif /* !IN_VBOX_CPU_REPORT */
7170

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 81150

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