CPUMR3CpuId.cpp@ 102371

Last change on this file since 102371 was 102371, checked in by vboxsync, 13 months ago
VMM: Nested VMX: bugref:10318 Enable MTRR reporting and MTRR MSR read+write support to get Windows 10 Hyper-V booting. Guest memory type application based on MTRRs is still a todo for later.
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1	/* $Id: CPUMR3CpuId.cpp 102371 2023-11-29 07:30:05Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_CPUM
33	#include <VBox/vmm/cpum.h>
34	#include <VBox/vmm/dbgf.h>
35	#include <VBox/vmm/hm.h>
36	#include <VBox/vmm/nem.h>
37	#include <VBox/vmm/ssm.h>
38	#include "CPUMInternal.h"
39	#include <VBox/vmm/vmcc.h>
40	#include <VBox/sup.h>
41
42	#include <VBox/err.h>
43	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
44	# include <iprt/asm-amd64-x86.h>
45	#endif
46	#include <iprt/ctype.h>
47	#include <iprt/mem.h>
48	#include <iprt/string.h>
49	#include <iprt/x86-helpers.h>
50
51
52	/*********************************************************************************************************************************
53	* Defined Constants And Macros *
54	*********************************************************************************************************************************/
55	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
56	#define CPUM_CPUID_MAX_LEAVES 2048
57
58
59	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
60	/**
61	* Determins the host CPU MXCSR mask.
62	*
63	* @returns MXCSR mask.
64	*/
65	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
66	{
67	if ( ASMHasCpuId()
68	&& RTX86IsValidStdRange(ASMCpuId_EAX(0))
69	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
70	{
71	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
72	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
73	RT_ZERO(*pState);
74	ASMFxSave(pState);
75	if (pState->MXCSR_MASK == 0)
76	return 0xffbf;
77	return pState->MXCSR_MASK;
78	}
79	return 0;
80	}
81	#endif
82
83
84
85	#ifndef IN_VBOX_CPU_REPORT
86	/**
87	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
88	*
89	* @returns true if found, false it not.
90	* @param paLeaves The CPUID leaves to search. This is sorted.
91	* @param cLeaves The number of leaves in the array.
92	* @param uLeaf The leaf to locate.
93	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
94	* @param pLegacy The legacy output leaf.
95	*/
96	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
97	PCPUMCPUID pLegacy)
98	{
99	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, uLeaf, uSubLeaf);
100	if (pLeaf)
101	{
102	pLegacy->uEax = pLeaf->uEax;
103	pLegacy->uEbx = pLeaf->uEbx;
104	pLegacy->uEcx = pLeaf->uEcx;
105	pLegacy->uEdx = pLeaf->uEdx;
106	return true;
107	}
108	return false;
109	}
110	#endif /* IN_VBOX_CPU_REPORT */
111
112
113	/**
114	* Inserts a CPU ID leaf, replacing any existing ones.
115	*
116	* When inserting a simple leaf where we already got a series of sub-leaves with
117	* the same leaf number (eax), the simple leaf will replace the whole series.
118	*
119	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
120	* host-context heap and has only been allocated/reallocated by the
121	* cpumCpuIdEnsureSpace function.
122	*
123	* @returns VBox status code.
124	* @param pVM The cross context VM structure. If NULL, use
125	* the process heap, otherwise the VM's hyper heap.
126	* @param ppaLeaves Pointer to the pointer to the array of sorted
127	* CPUID leaves and sub-leaves. Must be NULL if using
128	* the hyper heap.
129	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
130	* be NULL if using the hyper heap.
131	* @param pNewLeaf Pointer to the data of the new leaf we're about to
132	* insert.
133	*/
134	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
135	{
136	/*
137	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
138	*/
139	if (pVM)
140	{
141	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
142	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
143	AssertReturn(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 == pVM->cpum.s.GuestInfo.aCpuIdLeaves, VERR_INVALID_PARAMETER);
144
145	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
146	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
147	}
148
149	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
150	uint32_t cLeaves = *pcLeaves;
151
152	/*
153	* Validate the new leaf a little.
154	*/
155	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
156	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
157	VERR_INVALID_FLAGS);
158	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
159	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
160	VERR_INVALID_PARAMETER);
161	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
162	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
163	VERR_INVALID_PARAMETER);
164	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
165	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
166	VERR_INVALID_PARAMETER);
167
168	/*
169	* Find insertion point. The lazy bird uses the same excuse as in
170	* cpumCpuIdGetLeaf(), but optimizes for linear insertion (saved state).
171	*/
172	uint32_t i;
173	if ( cLeaves > 0
174	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
175	{
176	/* Add at end. */
177	i = cLeaves;
178	}
179	else if ( cLeaves > 0
180	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
181	{
182	/* Either replacing the last leaf or dealing with sub-leaves. Spool
183	back to the first sub-leaf to pretend we did the linear search. */
184	i = cLeaves - 1;
185	while ( i > 0
186	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
187	i--;
188	}
189	else
190	{
191	/* Linear search from the start. */
192	i = 0;
193	while ( i < cLeaves
194	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
195	i++;
196	}
197	if ( i < cLeaves
198	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
199	{
200	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
201	{
202	/*
203	* The sub-leaf mask differs, replace all existing leaves with the
204	* same leaf number.
205	*/
206	uint32_t c = 1;
207	while ( i + c < cLeaves
208	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
209	c++;
210	if (c > 1 && i + c < cLeaves)
211	{
212	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
213	*pcLeaves = cLeaves -= c - 1;
214	}
215
216	paLeaves[i] = *pNewLeaf;
217	#ifdef VBOX_STRICT
218	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
219	#endif
220	return VINF_SUCCESS;
221	}
222
223	/* Find sub-leaf insertion point. */
224	while ( i < cLeaves
225	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
226	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
227	i++;
228
229	/*
230	* If we've got an exactly matching leaf, replace it.
231	*/
232	if ( i < cLeaves
233	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
234	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
235	{
236	paLeaves[i] = *pNewLeaf;
237	#ifdef VBOX_STRICT
238	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
239	#endif
240	return VINF_SUCCESS;
241	}
242	}
243
244	/*
245	* Adding a new leaf at 'i'.
246	*/
247	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
248	paLeaves = cpumCpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
249	if (!paLeaves)
250	return VERR_NO_MEMORY;
251
252	if (i < cLeaves)
253	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
254	*pcLeaves += 1;
255	paLeaves[i] = *pNewLeaf;
256
257	#ifdef VBOX_STRICT
258	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
259	#endif
260	return VINF_SUCCESS;
261	}
262
263
264	#ifndef IN_VBOX_CPU_REPORT
265	/**
266	* Removes a range of CPUID leaves.
267	*
268	* This will not reallocate the array.
269	*
270	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
271	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
272	* @param uFirst The first leaf.
273	* @param uLast The last leaf.
274	*/
275	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
276	{
277	uint32_t cLeaves = *pcLeaves;
278
279	Assert(uFirst <= uLast);
280
281	/*
282	* Find the first one.
283	*/
284	uint32_t iFirst = 0;
285	while ( iFirst < cLeaves
286	&& paLeaves[iFirst].uLeaf < uFirst)
287	iFirst++;
288
289	/*
290	* Find the end (last + 1).
291	*/
292	uint32_t iEnd = iFirst;
293	while ( iEnd < cLeaves
294	&& paLeaves[iEnd].uLeaf <= uLast)
295	iEnd++;
296
297	/*
298	* Adjust the array if anything needs removing.
299	*/
300	if (iFirst < iEnd)
301	{
302	if (iEnd < cLeaves)
303	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
304	*pcLeaves = cLeaves -= (iEnd - iFirst);
305	}
306
307	# ifdef VBOX_STRICT
308	cpumCpuIdAssertOrder(paLeaves, *pcLeaves);
309	# endif
310	}
311	#endif /* IN_VBOX_CPU_REPORT */
312
313
314	/**
315	* Gets a CPU ID leaf.
316	*
317	* @returns VBox status code.
318	* @param pVM The cross context VM structure.
319	* @param pLeaf Where to store the found leaf.
320	* @param uLeaf The leaf to locate.
321	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
322	*/
323	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
324	{
325	PCPUMCPUIDLEAF pcLeaf = cpumCpuIdGetLeafInt(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
326	uLeaf, uSubLeaf);
327	if (pcLeaf)
328	{
329	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
330	return VINF_SUCCESS;
331	}
332
333	return VERR_NOT_FOUND;
334	}
335
336
337	/**
338	* Gets all the leaves.
339	*
340	* This only works after the CPUID leaves have been initialized. The interface
341	* is intended for NEM and configuring CPUID leaves for the native hypervisor.
342	*
343	* @returns Pointer to the array of leaves. NULL on failure.
344	* @param pVM The cross context VM structure.
345	* @param pcLeaves Where to return the number of leaves.
346	*/
347	VMMR3_INT_DECL(PCCPUMCPUIDLEAF) CPUMR3CpuIdGetPtr(PVM pVM, uint32_t *pcLeaves)
348	{
349	*pcLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
350	return pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
351	}
352
353
354	/**
355	* Inserts a CPU ID leaf, replacing any existing ones.
356	*
357	* @returns VBox status code.
358	* @param pVM The cross context VM structure.
359	* @param pNewLeaf Pointer to the leaf being inserted.
360	*/
361	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
362	{
363	/*
364	* Validate parameters.
365	*/
366	AssertReturn(pVM, VERR_INVALID_PARAMETER);
367	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
368
369	/*
370	* Disallow replacing CPU ID leaves that this API currently cannot manage.
371	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
372	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
373	*/
374	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
375	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
376	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
377	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
378	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
379	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
380	{
381	return VERR_NOT_SUPPORTED;
382	}
383
384	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
385	}
386
387
388	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
389	/**
390	* Determines the method the CPU uses to handle unknown CPUID leaves.
391	*
392	* @returns VBox status code.
393	* @param penmUnknownMethod Where to return the method.
394	* @param pDefUnknown Where to return default unknown values. This
395	* will be set, even if the resulting method
396	* doesn't actually needs it.
397	*/
398	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
399	{
400	uint32_t uLastStd = ASMCpuId_EAX(0);
401	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
402	if (!RTX86IsValidExtRange(uLastExt))
403	uLastExt = 0x80000000;
404
405	uint32_t auChecks[] =
406	{
407	uLastStd + 1,
408	uLastStd + 5,
409	uLastStd + 8,
410	uLastStd + 32,
411	uLastStd + 251,
412	uLastExt + 1,
413	uLastExt + 8,
414	uLastExt + 15,
415	uLastExt + 63,
416	uLastExt + 255,
417	0x7fbbffcc,
418	0x833f7872,
419	0xefff2353,
420	0x35779456,
421	0x1ef6d33e,
422	};
423
424	static const uint32_t s_auValues[] =
425	{
426	0xa95d2156,
427	0x00000001,
428	0x00000002,
429	0x00000008,
430	0x00000000,
431	0x55773399,
432	0x93401769,
433	0x12039587,
434	};
435
436	/*
437	* Simple method, all zeros.
438	*/
439	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
440	pDefUnknown->uEax = 0;
441	pDefUnknown->uEbx = 0;
442	pDefUnknown->uEcx = 0;
443	pDefUnknown->uEdx = 0;
444
445	/*
446	* Intel has been observed returning the last standard leaf.
447	*/
448	uint32_t auLast[4];
449	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
450
451	uint32_t cChecks = RT_ELEMENTS(auChecks);
452	while (cChecks > 0)
453	{
454	uint32_t auCur[4];
455	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
456	if (memcmp(auCur, auLast, sizeof(auCur)))
457	break;
458	cChecks--;
459	}
460	if (cChecks == 0)
461	{
462	/* Now, what happens when the input changes? Esp. ECX. */
463	uint32_t cTotal = 0;
464	uint32_t cSame = 0;
465	uint32_t cLastWithEcx = 0;
466	uint32_t cNeither = 0;
467	uint32_t cValues = RT_ELEMENTS(s_auValues);
468	while (cValues > 0)
469	{
470	uint32_t uValue = s_auValues[cValues - 1];
471	uint32_t auLastWithEcx[4];
472	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
473	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
474
475	cChecks = RT_ELEMENTS(auChecks);
476	while (cChecks > 0)
477	{
478	uint32_t auCur[4];
479	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
480	if (!memcmp(auCur, auLast, sizeof(auCur)))
481	{
482	cSame++;
483	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
484	cLastWithEcx++;
485	}
486	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
487	cLastWithEcx++;
488	else
489	cNeither++;
490	cTotal++;
491	cChecks--;
492	}
493	cValues--;
494	}
495
496	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
497	if (cSame == cTotal)
498	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
499	else if (cLastWithEcx == cTotal)
500	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
501	else
502	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
503	pDefUnknown->uEax = auLast[0];
504	pDefUnknown->uEbx = auLast[1];
505	pDefUnknown->uEcx = auLast[2];
506	pDefUnknown->uEdx = auLast[3];
507	return VINF_SUCCESS;
508	}
509
510	/*
511	* Unchanged register values?
512	*/
513	cChecks = RT_ELEMENTS(auChecks);
514	while (cChecks > 0)
515	{
516	uint32_t const uLeaf = auChecks[cChecks - 1];
517	uint32_t cValues = RT_ELEMENTS(s_auValues);
518	while (cValues > 0)
519	{
520	uint32_t uValue = s_auValues[cValues - 1];
521	uint32_t auCur[4];
522	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
523	if ( auCur[0] != uLeaf
524	\|\| auCur[1] != uValue
525	\|\| auCur[2] != uValue
526	\|\| auCur[3] != uValue)
527	break;
528	cValues--;
529	}
530	if (cValues != 0)
531	break;
532	cChecks--;
533	}
534	if (cChecks == 0)
535	{
536	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
537	return VINF_SUCCESS;
538	}
539
540	/*
541	* Just go with the simple method.
542	*/
543	return VINF_SUCCESS;
544	}
545	#endif /* RT_ARCH_X86 \|\| RT_ARCH_AMD64 */
546
547
548	/**
549	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
550	*
551	* @returns Read only name string.
552	* @param enmUnknownMethod The method to translate.
553	*/
554	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
555	{
556	switch (enmUnknownMethod)
557	{
558	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
559	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
560	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
561	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
562
563	case CPUMUNKNOWNCPUID_INVALID:
564	case CPUMUNKNOWNCPUID_END:
565	case CPUMUNKNOWNCPUID_32BIT_HACK:
566	break;
567	}
568	return "Invalid-unknown-CPUID-method";
569	}
570
571
572	/*
573	*
574	* Init related code.
575	* Init related code.
576	* Init related code.
577	*
578	*
579	*/
580	#ifndef IN_VBOX_CPU_REPORT
581
582
583	/**
584	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
585	*
586	* This ignores the fSubLeafMask.
587	*
588	* @returns Pointer to the matching leaf, or NULL if not found.
589	* @param pCpum The CPUM instance data.
590	* @param uLeaf The leaf to locate.
591	* @param uSubLeaf The subleaf to locate.
592	*/
593	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
594	{
595	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
596	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
597	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
598	if (iEnd)
599	{
600	uint32_t iBegin = 0;
601	for (;;)
602	{
603	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
604	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
605	if (uNeedle < uCur)
606	{
607	if (i > iBegin)
608	iEnd = i;
609	else
610	break;
611	}
612	else if (uNeedle > uCur)
613	{
614	if (i + 1 < iEnd)
615	iBegin = i + 1;
616	else
617	break;
618	}
619	else
620	return &paLeaves[i];
621	}
622	}
623	return NULL;
624	}
625
626
627	/**
628	* Loads MSR range overrides.
629	*
630	* This must be called before the MSR ranges are moved from the normal heap to
631	* the hyper heap!
632	*
633	* @returns VBox status code (VMSetError called).
634	* @param pVM The cross context VM structure.
635	* @param pMsrNode The CFGM node with the MSR overrides.
636	*/
637	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
638	{
639	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
640	{
641	/*
642	* Assemble a valid MSR range.
643	*/
644	CPUMMSRRANGE MsrRange;
645	MsrRange.offCpumCpu = 0;
646	MsrRange.fReserved = 0;
647
648	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
649	if (RT_FAILURE(rc))
650	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
651
652	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
653	if (RT_FAILURE(rc))
654	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
655	MsrRange.szName, rc);
656
657	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
658	if (RT_FAILURE(rc))
659	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
660	MsrRange.szName, rc);
661
662	char szType[32];
663	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
664	if (RT_FAILURE(rc))
665	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
666	MsrRange.szName, rc);
667	if (!RTStrICmp(szType, "FixedValue"))
668	{
669	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
670	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
671
672	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
673	if (RT_FAILURE(rc))
674	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
675	MsrRange.szName, rc);
676
677	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
678	if (RT_FAILURE(rc))
679	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
680	MsrRange.szName, rc);
681
682	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
683	if (RT_FAILURE(rc))
684	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
685	MsrRange.szName, rc);
686	}
687	else
688	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
689	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
690
691	/*
692	* Insert the range into the table (replaces/splits/shrinks existing
693	* MSR ranges).
694	*/
695	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
696	&MsrRange);
697	if (RT_FAILURE(rc))
698	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
699	}
700
701	return VINF_SUCCESS;
702	}
703
704
705	/**
706	* Loads CPUID leaf overrides.
707	*
708	* This must be called before the CPUID leaves are moved from the normal
709	* heap to the hyper heap!
710	*
711	* @returns VBox status code (VMSetError called).
712	* @param pVM The cross context VM structure.
713	* @param pParentNode The CFGM node with the CPUID leaves.
714	* @param pszLabel How to label the overrides we're loading.
715	*/
716	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
717	{
718	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
719	{
720	/*
721	* Get the leaf and subleaf numbers.
722	*/
723	char szName[128];
724	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
725	if (RT_FAILURE(rc))
726	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
727
728	/* The leaf number is either specified directly or thru the node name. */
729	uint32_t uLeaf;
730	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
731	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
732	{
733	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
734	if (rc != VINF_SUCCESS)
735	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
736	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
737	}
738	else if (RT_FAILURE(rc))
739	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
740	pszLabel, szName, rc);
741
742	uint32_t uSubLeaf;
743	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
744	if (RT_FAILURE(rc))
745	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
746	pszLabel, szName, rc);
747
748	uint32_t fSubLeafMask;
749	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
750	if (RT_FAILURE(rc))
751	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
752	pszLabel, szName, rc);
753
754	/*
755	* Look up the specified leaf, since the output register values
756	* defaults to any existing values. This allows overriding a single
757	* register, without needing to know the other values.
758	*/
759	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
760	CPUMCPUIDLEAF Leaf;
761	if (pLeaf)
762	Leaf = *pLeaf;
763	else
764	RT_ZERO(Leaf);
765	Leaf.uLeaf = uLeaf;
766	Leaf.uSubLeaf = uSubLeaf;
767	Leaf.fSubLeafMask = fSubLeafMask;
768
769	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
770	if (RT_FAILURE(rc))
771	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
772	pszLabel, szName, rc);
773	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
774	if (RT_FAILURE(rc))
775	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
776	pszLabel, szName, rc);
777	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
778	if (RT_FAILURE(rc))
779	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
780	pszLabel, szName, rc);
781	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
782	if (RT_FAILURE(rc))
783	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
784	pszLabel, szName, rc);
785
786	/*
787	* Insert the leaf into the table (replaces existing ones).
788	*/
789	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
790	&Leaf);
791	if (RT_FAILURE(rc))
792	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
793	}
794
795	return VINF_SUCCESS;
796	}
797
798
799
800	/**
801	* Fetches overrides for a CPUID leaf.
802	*
803	* @returns VBox status code.
804	* @param pLeaf The leaf to load the overrides into.
805	* @param pCfgNode The CFGM node containing the overrides
806	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
807	* @param iLeaf The CPUID leaf number.
808	*/
809	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
810	{
811	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
812	if (pLeafNode)
813	{
814	uint32_t u32;
815	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
816	if (RT_SUCCESS(rc))
817	pLeaf->uEax = u32;
818	else
819	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
820
821	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
822	if (RT_SUCCESS(rc))
823	pLeaf->uEbx = u32;
824	else
825	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
826
827	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
828	if (RT_SUCCESS(rc))
829	pLeaf->uEcx = u32;
830	else
831	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
832
833	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
834	if (RT_SUCCESS(rc))
835	pLeaf->uEdx = u32;
836	else
837	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
838
839	}
840	return VINF_SUCCESS;
841	}
842
843
844	/**
845	* Load the overrides for a set of CPUID leaves.
846	*
847	* @returns VBox status code.
848	* @param paLeaves The leaf array.
849	* @param cLeaves The number of leaves.
850	* @param uStart The start leaf number.
851	* @param pCfgNode The CFGM node containing the overrides
852	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
853	*/
854	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
855	{
856	for (uint32_t i = 0; i < cLeaves; i++)
857	{
858	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
859	if (RT_FAILURE(rc))
860	return rc;
861	}
862
863	return VINF_SUCCESS;
864	}
865
866
867	/**
868	* Installs the CPUID leaves and explods the data into structures like
869	* GuestFeatures and CPUMCTX::aoffXState.
870	*
871	* @returns VBox status code.
872	* @param pVM The cross context VM structure.
873	* @param pCpum The CPUM part of @a VM.
874	* @param paLeaves The leaves. These will be copied (but not freed).
875	* @param cLeaves The number of leaves.
876	* @param pMsrs The MSRs.
877	*/
878	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
879	{
880	# ifdef VBOX_STRICT
881	cpumCpuIdAssertOrder(paLeaves, cLeaves);
882	# endif
883
884	/*
885	* Install the CPUID information.
886	*/
887	AssertLogRelMsgReturn(cLeaves <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves),
888	("cLeaves=%u - max %u\n", cLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves)),
889	VERR_CPUM_IPE_1); /** @todo better status! */
890	if (paLeaves != pCpum->GuestInfo.aCpuIdLeaves)
891	memcpy(pCpum->GuestInfo.aCpuIdLeaves, paLeaves, cLeaves * sizeof(paLeaves[0]));
892	pCpum->GuestInfo.paCpuIdLeavesR3 = pCpum->GuestInfo.aCpuIdLeaves;
893	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
894
895	/*
896	* Update the default CPUID leaf if necessary.
897	*/
898	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
899	{
900	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
901	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
902	{
903	/* We don't use CPUID(0).eax here because of the NT hack that only
904	changes that value without actually removing any leaves. */
905	uint32_t i = 0;
906	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
907	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
908	{
909	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
910	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
911	i++;
912	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
913	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
914	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
915	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
916	}
917	break;
918	}
919	default:
920	break;
921	}
922
923	/*
924	* Explode the guest CPU features.
925	*/
926	int rc = cpumCpuIdExplodeFeaturesX86(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
927	&pCpum->GuestFeatures);
928	AssertLogRelRCReturn(rc, rc);
929
930	/*
931	* Adjust the scalable bus frequency according to the CPUID information
932	* we're now using.
933	*/
934	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
935	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
936	? UINT64_C(100000000) /* 100MHz */
937	: UINT64_C(133333333); /* 133MHz */
938
939	/*
940	* Populate the legacy arrays. Currently used for everything, later only
941	* for patch manager.
942	*/
943	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
944	{
945	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
946	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
947	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
948	};
949	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
950	{
951	uint32_t cLeft = aOldRanges[i].cCpuIds;
952	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
953	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
954	while (cLeft-- > 0)
955	{
956	uLeaf--;
957	pLegacyLeaf--;
958
959	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
960	if (pLeaf)
961	{
962	pLegacyLeaf->uEax = pLeaf->uEax;
963	pLegacyLeaf->uEbx = pLeaf->uEbx;
964	pLegacyLeaf->uEcx = pLeaf->uEcx;
965	pLegacyLeaf->uEdx = pLeaf->uEdx;
966	}
967	else
968	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
969	}
970	}
971
972	/*
973	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
974	*/
975	PVMCPU pVCpu0 = pVM->apCpusR3[0];
976	AssertCompile(sizeof(pVCpu0->cpum.s.Guest.abXState) == CPUM_MAX_XSAVE_AREA_SIZE);
977	memset(&pVCpu0->cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVCpu0->cpum.s.Guest.aoffXState));
978	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
979	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
980	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
981	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
982	{
983	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
984	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
985	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
986	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
987	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
988	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
989	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
990	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
991	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
992	pCpum->GuestFeatures.cbMaxExtendedState),
993	VERR_CPUM_IPE_1);
994	pVCpu0->cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
995	}
996
997	/* Copy the CPU #0 data to the other CPUs. */
998	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
999	{
1000	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1001	memcpy(&pVCpu->cpum.s.Guest.aoffXState[0], &pVCpu0->cpum.s.Guest.aoffXState[0], sizeof(pVCpu0->cpum.s.Guest.aoffXState));
1002	}
1003
1004	return VINF_SUCCESS;
1005	}
1006
1007
1008	/** @name Instruction Set Extension Options
1009	* @{ */
1010	/** Configuration option type (extended boolean, really). */
1011	typedef uint8_t CPUMISAEXTCFG;
1012	/** Always disable the extension. */
1013	#define CPUMISAEXTCFG_DISABLED false
1014	/** Enable the extension if it's supported by the host CPU. */
1015	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
1016	/** Enable the extension if it's supported by the host CPU, but don't let
1017	* the portable CPUID feature disable it. */
1018	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
1019	/** Always enable the extension. */
1020	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
1021	/** @} */
1022
1023	/**
1024	* CPUID Configuration (from CFGM).
1025	*
1026	* @remarks The members aren't document since we would only be duplicating the
1027	* \@cfgm entries in cpumR3CpuIdReadConfig.
1028	*/
1029	typedef struct CPUMCPUIDCONFIG
1030	{
1031	bool fNt4LeafLimit;
1032	bool fInvariantTsc;
1033	bool fForceVme;
1034	bool fNestedHWVirt;
1035
1036	CPUMISAEXTCFG enmCmpXchg16b;
1037	CPUMISAEXTCFG enmMonitor;
1038	CPUMISAEXTCFG enmMWaitExtensions;
1039	CPUMISAEXTCFG enmSse41;
1040	CPUMISAEXTCFG enmSse42;
1041	CPUMISAEXTCFG enmAvx;
1042	CPUMISAEXTCFG enmAvx2;
1043	CPUMISAEXTCFG enmXSave;
1044	CPUMISAEXTCFG enmAesNi;
1045	CPUMISAEXTCFG enmPClMul;
1046	CPUMISAEXTCFG enmPopCnt;
1047	CPUMISAEXTCFG enmMovBe;
1048	CPUMISAEXTCFG enmRdRand;
1049	CPUMISAEXTCFG enmRdSeed;
1050	CPUMISAEXTCFG enmSha;
1051	CPUMISAEXTCFG enmAdx;
1052	CPUMISAEXTCFG enmCLFlushOpt;
1053	CPUMISAEXTCFG enmFsGsBase;
1054	CPUMISAEXTCFG enmPcid;
1055	CPUMISAEXTCFG enmInvpcid;
1056	CPUMISAEXTCFG enmFlushCmdMsr;
1057	CPUMISAEXTCFG enmMdsClear;
1058	CPUMISAEXTCFG enmArchCapMsr;
1059
1060	CPUMISAEXTCFG enmAbm;
1061	CPUMISAEXTCFG enmSse4A;
1062	CPUMISAEXTCFG enmMisAlnSse;
1063	CPUMISAEXTCFG enm3dNowPrf;
1064	CPUMISAEXTCFG enmAmdExtMmx;
1065
1066	uint32_t uMaxStdLeaf;
1067	uint32_t uMaxExtLeaf;
1068	uint32_t uMaxCentaurLeaf;
1069	uint32_t uMaxIntelFamilyModelStep;
1070	char szCpuName[128];
1071	} CPUMCPUIDCONFIG;
1072	/** Pointer to CPUID config (from CFGM). */
1073	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
1074
1075
1076	/**
1077	* Mini CPU selection support for making Mac OS X happy.
1078	*
1079	* Executes the /CPUM/MaxIntelFamilyModelStep config.
1080	*
1081	* @param pCpum The CPUM instance data.
1082	* @param pConfig The CPUID configuration we've read from CFGM.
1083	*/
1084	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1085	{
1086	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1087	{
1088	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1089	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(RTX86GetCpuStepping(pStdFeatureLeaf->uEax),
1090	RTX86GetCpuModelIntel(pStdFeatureLeaf->uEax),
1091	RTX86GetCpuFamily(pStdFeatureLeaf->uEax),
1092	0);
1093	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
1094	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
1095	{
1096	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
1097	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
1098	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
1099	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
1100	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
1101	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
1102	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
1103	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
1104	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
1105	pStdFeatureLeaf->uEax = uNew;
1106	}
1107	}
1108	}
1109
1110
1111
1112	/**
1113	* Limit it the number of entries, zapping the remainder.
1114	*
1115	* The limits are masking off stuff about power saving and similar, this
1116	* is perhaps a bit crudely done as there is probably some relatively harmless
1117	* info too in these leaves (like words about having a constant TSC).
1118	*
1119	* @param pCpum The CPUM instance data.
1120	* @param pConfig The CPUID configuration we've read from CFGM.
1121	*/
1122	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1123	{
1124	/*
1125	* Standard leaves.
1126	*/
1127	uint32_t uSubLeaf = 0;
1128	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
1129	if (pCurLeaf)
1130	{
1131	uint32_t uLimit = pCurLeaf->uEax;
1132	if (uLimit <= UINT32_C(0x000fffff))
1133	{
1134	if (uLimit > pConfig->uMaxStdLeaf)
1135	{
1136	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
1137	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1138	uLimit + 1, UINT32_C(0x000fffff));
1139	}
1140
1141	/* NT4 hack, no zapping of extra leaves here. */
1142	if (pConfig->fNt4LeafLimit && uLimit > 3)
1143	pCurLeaf->uEax = uLimit = 3;
1144
1145	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
1146	pCurLeaf->uEax = uLimit;
1147	}
1148	else
1149	{
1150	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
1151	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1152	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
1153	}
1154	}
1155
1156	/*
1157	* Extended leaves.
1158	*/
1159	uSubLeaf = 0;
1160	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
1161	if (pCurLeaf)
1162	{
1163	uint32_t uLimit = pCurLeaf->uEax;
1164	if ( uLimit >= UINT32_C(0x80000000)
1165	&& uLimit <= UINT32_C(0x800fffff))
1166	{
1167	if (uLimit > pConfig->uMaxExtLeaf)
1168	{
1169	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
1170	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1171	uLimit + 1, UINT32_C(0x800fffff));
1172	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
1173	pCurLeaf->uEax = uLimit;
1174	}
1175	}
1176	else
1177	{
1178	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
1179	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1180	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
1181	}
1182	}
1183
1184	/*
1185	* Centaur leaves (VIA).
1186	*/
1187	uSubLeaf = 0;
1188	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
1189	if (pCurLeaf)
1190	{
1191	uint32_t uLimit = pCurLeaf->uEax;
1192	if ( uLimit >= UINT32_C(0xc0000000)
1193	&& uLimit <= UINT32_C(0xc00fffff))
1194	{
1195	if (uLimit > pConfig->uMaxCentaurLeaf)
1196	{
1197	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
1198	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1199	uLimit + 1, UINT32_C(0xcfffffff));
1200	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
1201	pCurLeaf->uEax = uLimit;
1202	}
1203	}
1204	else
1205	{
1206	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
1207	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1208	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
1209	}
1210	}
1211	}
1212
1213
1214	/**
1215	* Clears a CPUID leaf and all sub-leaves (to zero).
1216	*
1217	* @param pCpum The CPUM instance data.
1218	* @param uLeaf The leaf to clear.
1219	*/
1220	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
1221	{
1222	uint32_t uSubLeaf = 0;
1223	PCPUMCPUIDLEAF pCurLeaf;
1224	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
1225	{
1226	pCurLeaf->uEax = 0;
1227	pCurLeaf->uEbx = 0;
1228	pCurLeaf->uEcx = 0;
1229	pCurLeaf->uEdx = 0;
1230	uSubLeaf++;
1231	}
1232	}
1233
1234
1235	/**
1236	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
1237	* the given leaf.
1238	*
1239	* @returns pLeaf.
1240	* @param pCpum The CPUM instance data.
1241	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
1242	*/
1243	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
1244	{
1245	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
1246	if (pLeaf->fSubLeafMask != 0)
1247	{
1248	/*
1249	* Figure out how many sub-leaves in need of removal (we'll keep the first).
1250	* Log everything while we're at it.
1251	*/
1252	LogRel(("CPUM:\n"
1253	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
1254	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
1255	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
1256	for (;;)
1257	{
1258	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
1259	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
1260	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
1261	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
1262	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
1263	break;
1264	pSubLeaf++;
1265	}
1266	LogRel(("CPUM:\n"));
1267
1268	/*
1269	* Remove the offending sub-leaves.
1270	*/
1271	if (pSubLeaf != pLeaf)
1272	{
1273	if (pSubLeaf != pLast)
1274	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
1275	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
1276	}
1277
1278	/*
1279	* Convert the first sub-leaf into a single leaf.
1280	*/
1281	pLeaf->uSubLeaf = 0;
1282	pLeaf->fSubLeafMask = 0;
1283	}
1284	return pLeaf;
1285	}
1286
1287
1288	/**
1289	* Sanitizes and adjust the CPUID leaves.
1290	*
1291	* Drop features that aren't virtualized (or virtualizable). Adjust information
1292	* and capabilities to fit the virtualized hardware. Remove information the
1293	* guest shouldn't have (because it's wrong in the virtual world or because it
1294	* gives away host details) or that we don't have documentation for and no idea
1295	* what means.
1296	*
1297	* @returns VBox status code.
1298	* @param pVM The cross context VM structure (for cCpus).
1299	* @param pCpum The CPUM instance data.
1300	* @param pConfig The CPUID configuration we've read from CFGM.
1301	*/
1302	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1303	{
1304	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
1305	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
1306	{ \
1307	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
1308	(a_pLeafReg) &= ~(uint32_t)(fMask); \
1309	}
1310	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
1311	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
1312	{ \
1313	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
1314	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
1315	}
1316	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
1317	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
1318	&& ((a_pLeafReg) & (fBitMask)) \
1319	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
1320	{ \
1321	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
1322	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
1323	}
1324	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
1325
1326	/* The CPUID entries we start with here isn't necessarily the ones of the host, so we
1327	must consult HostFeatures when processing CPUMISAEXTCFG variables. */
1328	PCCPUMFEATURES pHstFeat = &pCpum->HostFeatures;
1329	#define PASSTHRU_FEATURE(enmConfig, fHostFeature, fConst) \
1330	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) ? (fConst) : 0)
1331	#define PASSTHRU_FEATURE_EX(enmConfig, fHostFeature, fAndExpr, fConst) \
1332	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) && (fAndExpr) ? (fConst) : 0)
1333	#define PASSTHRU_FEATURE_TODO(enmConfig, fConst) ((enmConfig) ? (fConst) : 0)
1334
1335	/* Cpuid 1:
1336	* EAX: CPU model, family and stepping.
1337	*
1338	* ECX + EDX: Supported features. Only report features we can support.
1339	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1340	* options may require adjusting (i.e. stripping what was enabled).
1341	*
1342	* EBX: Branding, CLFLUSH line size, logical processors per package and
1343	* initial APIC ID.
1344	*/
1345	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
1346	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
1347	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
1348
1349	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
1350	\| X86_CPUID_FEATURE_EDX_VME
1351	\| X86_CPUID_FEATURE_EDX_DE
1352	\| X86_CPUID_FEATURE_EDX_PSE
1353	\| X86_CPUID_FEATURE_EDX_TSC
1354	\| X86_CPUID_FEATURE_EDX_MSR
1355	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
1356	\| X86_CPUID_FEATURE_EDX_MCE
1357	\| X86_CPUID_FEATURE_EDX_CX8
1358	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
1359	//\| RT_BIT_32(10) - not defined
1360	\| X86_CPUID_FEATURE_EDX_SEP
1361	\| X86_CPUID_FEATURE_EDX_MTRR
1362	\| X86_CPUID_FEATURE_EDX_PGE
1363	\| X86_CPUID_FEATURE_EDX_MCA
1364	\| X86_CPUID_FEATURE_EDX_CMOV
1365	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
1366	\| X86_CPUID_FEATURE_EDX_PSE36
1367	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
1368	\| X86_CPUID_FEATURE_EDX_CLFSH
1369	//\| RT_BIT_32(20) - not defined
1370	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
1371	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
1372	\| X86_CPUID_FEATURE_EDX_MMX
1373	\| X86_CPUID_FEATURE_EDX_FXSR
1374	\| X86_CPUID_FEATURE_EDX_SSE
1375	\| X86_CPUID_FEATURE_EDX_SSE2
1376	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
1377	\| X86_CPUID_FEATURE_EDX_HTT
1378	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
1379	//\| RT_BIT_32(30) - not defined
1380	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
1381	;
1382	pStdFeatureLeaf->uEcx &= X86_CPUID_FEATURE_ECX_SSE3
1383	\| PASSTHRU_FEATURE_TODO(pConfig->enmPClMul, X86_CPUID_FEATURE_ECX_PCLMUL)
1384	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
1385	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
1386	\| PASSTHRU_FEATURE_EX(pConfig->enmMonitor, pHstFeat->fMonitorMWait, pVM->cCpus == 1, X86_CPUID_FEATURE_ECX_MONITOR)
1387	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
1388	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
1389	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
1390	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
1391	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
1392	\| X86_CPUID_FEATURE_ECX_SSSE3
1393	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
1394	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
1395	\| PASSTHRU_FEATURE(pConfig->enmCmpXchg16b, pHstFeat->fCmpXchg16b, X86_CPUID_FEATURE_ECX_CX16)
1396	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
1397	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1398	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
1399	\| PASSTHRU_FEATURE(pConfig->enmPcid, pHstFeat->fPcid, X86_CPUID_FEATURE_ECX_PCID)
1400	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
1401	\| PASSTHRU_FEATURE(pConfig->enmSse41, pHstFeat->fSse41, X86_CPUID_FEATURE_ECX_SSE4_1)
1402	\| PASSTHRU_FEATURE(pConfig->enmSse42, pHstFeat->fSse42, X86_CPUID_FEATURE_ECX_SSE4_2)
1403	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
1404	\| PASSTHRU_FEATURE_TODO(pConfig->enmMovBe, X86_CPUID_FEATURE_ECX_MOVBE)
1405	\| PASSTHRU_FEATURE(pConfig->enmPopCnt, pHstFeat->fPopCnt, X86_CPUID_FEATURE_ECX_POPCNT)
1406	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
1407	\| PASSTHRU_FEATURE_TODO(pConfig->enmAesNi, X86_CPUID_FEATURE_ECX_AES)
1408	\| PASSTHRU_FEATURE(pConfig->enmXSave, pHstFeat->fXSaveRstor, X86_CPUID_FEATURE_ECX_XSAVE)
1409	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
1410	\| PASSTHRU_FEATURE(pConfig->enmAvx, pHstFeat->fAvx, X86_CPUID_FEATURE_ECX_AVX)
1411	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
1412	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdRand, X86_CPUID_FEATURE_ECX_RDRAND)
1413	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
1414	;
1415
1416	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
1417	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
1418	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
1419	{
1420	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
1421	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
1422	}
1423
1424	if (pCpum->u8PortableCpuIdLevel > 0)
1425	{
1426	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
1427	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
1428	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
1429	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
1430	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
1431	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
1432	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
1433	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
1434	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
1435	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
1436	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
1437	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
1438	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
1439	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
1440	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
1441	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
1442	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
1443	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
1444	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
1445	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
1446
1447	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP ///??
1448	\| X86_CPUID_FEATURE_EDX_PSN
1449	\| X86_CPUID_FEATURE_EDX_DS
1450	\| X86_CPUID_FEATURE_EDX_ACPI
1451	\| X86_CPUID_FEATURE_EDX_SS
1452	\| X86_CPUID_FEATURE_EDX_TM
1453	\| X86_CPUID_FEATURE_EDX_PBE
1454	)));
1455	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
1456	\| X86_CPUID_FEATURE_ECX_CPLDS
1457	\| X86_CPUID_FEATURE_ECX_AES
1458	\| X86_CPUID_FEATURE_ECX_VMX
1459	\| X86_CPUID_FEATURE_ECX_SMX
1460	\| X86_CPUID_FEATURE_ECX_EST
1461	\| X86_CPUID_FEATURE_ECX_TM2
1462	\| X86_CPUID_FEATURE_ECX_CNTXID
1463	\| X86_CPUID_FEATURE_ECX_FMA
1464	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1465	\| X86_CPUID_FEATURE_ECX_PDCM
1466	\| X86_CPUID_FEATURE_ECX_DCA
1467	\| X86_CPUID_FEATURE_ECX_OSXSAVE
1468	)));
1469	}
1470
1471	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
1472	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
1473
1474	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
1475	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
1476	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
1477	*/
1478	#ifdef VBOX_WITH_MULTI_CORE
1479	if (pVM->cCpus > 1)
1480	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
1481	#endif
1482	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
1483	{
1484	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
1485	core times the number of CPU cores per processor */
1486	#ifdef VBOX_WITH_MULTI_CORE
1487	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
1488	#else
1489	/* Single logical processor in a package. */
1490	pStdFeatureLeaf->uEbx \|= (1 << 16);
1491	#endif
1492	}
1493
1494	uint32_t uMicrocodeRev;
1495	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
1496	if (RT_SUCCESS(rc))
1497	{
1498	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
1499	}
1500	else
1501	{
1502	uMicrocodeRev = 0;
1503	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
1504	}
1505
1506	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
1507	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
1508	*/
1509	if ( ( pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen
1510	/** @todo The following ASSUMES that Hygon uses the same version numbering
1511	* as AMD and that they shipped buggy firmware. */
1512	\|\| pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Hygon_Dhyana)
1513	&& uMicrocodeRev < 0x8001126
1514	&& !pConfig->fForceVme)
1515	{
1516	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
1517	LogRel(("CPUM: Zen VME workaround engaged\n"));
1518	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
1519	}
1520
1521	/* Force standard feature bits. */
1522	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
1523	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
1524	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
1525	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
1526	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
1527	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
1528	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1529	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
1530	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1531	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
1532	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
1533	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
1534	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
1535	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
1536	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
1537	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
1538	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
1539	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
1540	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1541	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
1542	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
1543	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
1544
1545	pStdFeatureLeaf = NULL; /* Must refetch! */
1546
1547	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
1548	* AMD:
1549	* EAX: CPU model, family and stepping.
1550	*
1551	* ECX + EDX: Supported features. Only report features we can support.
1552	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1553	* options may require adjusting (i.e. stripping what was enabled).
1554	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
1555	*
1556	* EBX: Branding ID and package type (or reserved).
1557	*
1558	* Intel and probably most others:
1559	* EAX: 0
1560	* EBX: 0
1561	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
1562	*/
1563	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
1564	if (pExtFeatureLeaf)
1565	{
1566	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
1567
1568	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
1569	\| X86_CPUID_AMD_FEATURE_EDX_VME
1570	\| X86_CPUID_AMD_FEATURE_EDX_DE
1571	\| X86_CPUID_AMD_FEATURE_EDX_PSE
1572	\| X86_CPUID_AMD_FEATURE_EDX_TSC
1573	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
1574	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
1575	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
1576	\| X86_CPUID_AMD_FEATURE_EDX_CX8
1577	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
1578	//\| RT_BIT_32(10) - reserved
1579	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1580	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
1581	\| X86_CPUID_AMD_FEATURE_EDX_PGE
1582	\| X86_CPUID_AMD_FEATURE_EDX_MCA
1583	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
1584	\| X86_CPUID_AMD_FEATURE_EDX_PAT
1585	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
1586	//\| RT_BIT_32(18) - reserved
1587	//\| RT_BIT_32(19) - reserved
1588	\| X86_CPUID_EXT_FEATURE_EDX_NX
1589	//\| RT_BIT_32(21) - reserved
1590	\| PASSTHRU_FEATURE(pConfig->enmAmdExtMmx, pHstFeat->fAmdMmxExts, X86_CPUID_AMD_FEATURE_EDX_AXMMX)
1591	\| X86_CPUID_AMD_FEATURE_EDX_MMX
1592	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
1593	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
1594	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1595	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
1596	//\| RT_BIT_32(28) - reserved
1597	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
1598	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
1599	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
1600	;
1601	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
1602	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
1603	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
1604	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1605	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
1606	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
1607	\| PASSTHRU_FEATURE(pConfig->enmAbm, pHstFeat->fAbm, X86_CPUID_AMD_FEATURE_ECX_ABM)
1608	\| PASSTHRU_FEATURE_TODO(pConfig->enmSse4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A)
1609	\| PASSTHRU_FEATURE_TODO(pConfig->enmMisAlnSse, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE)
1610	\| PASSTHRU_FEATURE(pConfig->enm3dNowPrf, pHstFeat->f3DNowPrefetch, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1611	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
1612	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
1613	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
1614	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1615	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
1616	//\| RT_BIT_32(14) - reserved
1617	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
1618	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
1619	//\| RT_BIT_32(17) - reserved
1620	//\| RT_BIT_32(18) - reserved
1621	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
1622	//\| RT_BIT_32(20) - reserved
1623	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
1624	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
1625	//\| RT_BIT_32(23) - reserved
1626	//\| RT_BIT_32(24) - reserved
1627	//\| RT_BIT_32(25) - reserved
1628	//\| RT_BIT_32(26) - reserved
1629	//\| RT_BIT_32(27) - reserved
1630	//\| RT_BIT_32(28) - reserved
1631	//\| RT_BIT_32(29) - reserved
1632	//\| RT_BIT_32(30) - reserved
1633	//\| RT_BIT_32(31) - reserved
1634	;
1635	#ifdef VBOX_WITH_MULTI_CORE
1636	if ( pVM->cCpus > 1
1637	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
1638	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
1639	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
1640	#endif
1641
1642	if (pCpum->u8PortableCpuIdLevel > 0)
1643	{
1644	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1645	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
1646	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
1647	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
1648	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
1649	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
1650	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
1651	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
1652	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
1653	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
1654	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1655	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1656	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1657	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1658	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1659	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1660
1661	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
1662	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1663	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
1664	\| X86_CPUID_AMD_FEATURE_ECX_IBS
1665	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1666	\| X86_CPUID_AMD_FEATURE_ECX_WDT
1667	\| X86_CPUID_AMD_FEATURE_ECX_LWP
1668	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
1669	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
1670	\| UINT32_C(0xff964000)
1671	)));
1672	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
1673	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1674	\| RT_BIT(18)
1675	\| RT_BIT(19)
1676	\| RT_BIT(21)
1677	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
1678	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1679	\| RT_BIT(28)
1680	)));
1681	}
1682
1683	/* Force extended feature bits. */
1684	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
1685	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
1686	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
1687	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
1688	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
1689	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
1690	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
1691	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
1692	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1693	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
1694	}
1695	pExtFeatureLeaf = NULL; /* Must refetch! */
1696
1697
1698	/* Cpuid 2:
1699	* Intel: (Nondeterministic) Cache and TLB information
1700	* AMD: Reserved
1701	* VIA: Reserved
1702	* Safe to expose.
1703	*/
1704	uint32_t uSubLeaf = 0;
1705	PCPUMCPUIDLEAF pCurLeaf;
1706	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
1707	{
1708	if ((pCurLeaf->uEax & 0xff) > 1)
1709	{
1710	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
1711	pCurLeaf->uEax &= UINT32_C(0xffffff01);
1712	}
1713	uSubLeaf++;
1714	}
1715
1716	/* Cpuid 3:
1717	* Intel: EAX, EBX - reserved (transmeta uses these)
1718	* ECX, EDX - Processor Serial Number if available, otherwise reserved
1719	* AMD: Reserved
1720	* VIA: Reserved
1721	* Safe to expose
1722	*/
1723	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1724	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
1725	{
1726	uSubLeaf = 0;
1727	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
1728	{
1729	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1730	if (pCpum->u8PortableCpuIdLevel > 0)
1731	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1732	uSubLeaf++;
1733	}
1734	}
1735
1736	/* Cpuid 4 + ECX:
1737	* Intel: Deterministic Cache Parameters Leaf.
1738	* AMD: Reserved
1739	* VIA: Reserved
1740	* Safe to expose, except for EAX:
1741	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
1742	* Bits 31-26: Maximum number of processor cores in this physical package**
1743	* Note: These SMP values are constant regardless of ECX
1744	*/
1745	uSubLeaf = 0;
1746	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
1747	{
1748	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
1749	#ifdef VBOX_WITH_MULTI_CORE
1750	if ( pVM->cCpus > 1
1751	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1752	{
1753	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
1754	/* One logical processor with possibly multiple cores. */
1755	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
1756	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
1757	}
1758	#endif
1759	uSubLeaf++;
1760	}
1761
1762	/* Cpuid 5: Monitor/mwait Leaf
1763	* Intel: ECX, EDX - reserved
1764	* EAX, EBX - Smallest and largest monitor line size
1765	* AMD: EDX - reserved
1766	* EAX, EBX - Smallest and largest monitor line size
1767	* ECX - extensions (ignored for now)
1768	* VIA: Reserved
1769	* Safe to expose
1770	*/
1771	uSubLeaf = 0;
1772	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
1773	{
1774	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1775	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
1776	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1777
1778	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1779	if (pConfig->enmMWaitExtensions)
1780	{
1781	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
1782	/** @todo for now we just expose host's MWAIT C-states, although conceptually
1783	it shall be part of our power management virtualization model */
1784	#if 0
1785	/* MWAIT sub C-states */
1786	pCurLeaf->uEdx =
1787	(0 << 0) /* 0 in C0 */ \|
1788	(2 << 4) /* 2 in C1 */ \|
1789	(2 << 8) /* 2 in C2 */ \|
1790	(2 << 12) /* 2 in C3 */ \|
1791	(0 << 16) /* 0 in C4 */
1792	;
1793	#endif
1794	}
1795	else
1796	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1797	uSubLeaf++;
1798	}
1799
1800	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
1801	* Intel: Various stuff.
1802	* AMD: EAX, EBX, EDX - reserved.
1803	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
1804	* present. Same as intel.
1805	* VIA: ??
1806	*
1807	* We clear everything here for now.
1808	*/
1809	cpumR3CpuIdZeroLeaf(pCpum, 6);
1810
1811	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
1812	* EAX: Number of sub leaves.
1813	* EBX+ECX+EDX: Feature flags
1814	*
1815	* We only have documentation for one sub-leaf, so clear all other (no need
1816	* to remove them as such, just set them to zero).
1817	*
1818	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1819	* options may require adjusting (i.e. stripping what was enabled).
1820	*/
1821	uSubLeaf = 0;
1822	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
1823	{
1824	switch (uSubLeaf)
1825	{
1826	case 0:
1827	{
1828	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
1829	pCurLeaf->uEbx &= 0
1830	\| PASSTHRU_FEATURE(pConfig->enmFsGsBase, pHstFeat->fFsGsBase, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE)
1831	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
1832	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
1833	\| X86_CPUID_STEXT_FEATURE_EBX_BMI1
1834	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
1835	\| PASSTHRU_FEATURE(pConfig->enmAvx2, pHstFeat->fAvx2, X86_CPUID_STEXT_FEATURE_EBX_AVX2)
1836	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
1837	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
1838	\| X86_CPUID_STEXT_FEATURE_EBX_BMI2
1839	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
1840	\| PASSTHRU_FEATURE(pConfig->enmInvpcid, pHstFeat->fInvpcid, X86_CPUID_STEXT_FEATURE_EBX_INVPCID)
1841	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
1842	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
1843	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
1844	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
1845	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
1846	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
1847	//\| RT_BIT(17) - reserved
1848	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdSeed, X86_CPUID_STEXT_FEATURE_EBX_RDSEED)
1849	\| PASSTHRU_FEATURE(pConfig->enmAdx, pHstFeat->fAdx, X86_CPUID_STEXT_FEATURE_EBX_ADX)
1850	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
1851	//\| RT_BIT(21) - reserved
1852	//\| RT_BIT(22) - reserved
1853	\| PASSTHRU_FEATURE(pConfig->enmCLFlushOpt, pHstFeat->fClFlushOpt, X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT)
1854	//\| RT_BIT(24) - reserved
1855	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
1856	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
1857	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
1858	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
1859	\| PASSTHRU_FEATURE(pConfig->enmSha, pHstFeat->fSha, X86_CPUID_STEXT_FEATURE_EBX_SHA)
1860	//\| RT_BIT(30) - reserved
1861	//\| RT_BIT(31) - reserved
1862	;
1863	pCurLeaf->uEcx &= 0
1864	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
1865	;
1866	pCurLeaf->uEdx &= 0
1867	\| PASSTHRU_FEATURE(pConfig->enmMdsClear, pHstFeat->fMdsClear, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR)
1868	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
1869	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
1870	\| PASSTHRU_FEATURE(pConfig->enmFlushCmdMsr, pHstFeat->fFlushCmd, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD)
1871	\| PASSTHRU_FEATURE(pConfig->enmArchCapMsr, pHstFeat->fArchCap, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
1872	;
1873
1874	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
1875	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
1876	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
1877	{
1878	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
1879	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
1880	}
1881
1882	if (pCpum->u8PortableCpuIdLevel > 0)
1883	{
1884	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
1885	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
1886	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
1887	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
1888	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
1889	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
1890	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1891	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
1892	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, ADX, X86_CPUID_STEXT_FEATURE_EBX_ADX, pConfig->enmAdx);
1893	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
1894	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
1895	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
1896	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
1897	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
1898	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA, pConfig->enmSha);
1899	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
1900	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
1901	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
1902	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
1903	}
1904
1905	/* Dependencies. */
1906	if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
1907	pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
1908
1909	/* Force standard feature bits. */
1910	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
1911	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
1912	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1913	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
1914	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
1915	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
1916	if (pConfig->enmAdx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1917	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_ADX;
1918	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
1919	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
1920	if (pConfig->enmSha == CPUMISAEXTCFG_ENABLED_ALWAYS)
1921	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_SHA;
1922	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
1923	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
1924	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
1925	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
1926	if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
1927	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
1928	if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
1929	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
1930	break;
1931	}
1932
1933	default:
1934	/* Invalid index, all values are zero. */
1935	pCurLeaf->uEax = 0;
1936	pCurLeaf->uEbx = 0;
1937	pCurLeaf->uEcx = 0;
1938	pCurLeaf->uEdx = 0;
1939	break;
1940	}
1941	uSubLeaf++;
1942	}
1943
1944	/* Cpuid 8: Marked as reserved by Intel and AMD.
1945	* We zero this since we don't know what it may have been used for.
1946	*/
1947	cpumR3CpuIdZeroLeaf(pCpum, 8);
1948
1949	/* Cpuid 9: Direct Cache Access (DCA) Parameters
1950	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
1951	* EBX, ECX, EDX - reserved.
1952	* AMD: Reserved
1953	* VIA: ??
1954	*
1955	* We zero this.
1956	*/
1957	cpumR3CpuIdZeroLeaf(pCpum, 9);
1958
1959	/* Cpuid 0xa: Architectural Performance Monitor Features
1960	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
1961	* EBX, ECX, EDX - reserved.
1962	* AMD: Reserved
1963	* VIA: ??
1964	*
1965	* We zero this, for now at least.
1966	*/
1967	cpumR3CpuIdZeroLeaf(pCpum, 10);
1968
1969	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
1970	* Intel: EAX - APCI ID shift right for next level.
1971	* EBX - Factory configured cores/threads at this level.
1972	* ECX - Level number (same as input) and level type (1,2,0).
1973	* EDX - Extended initial APIC ID.
1974	* AMD: Reserved
1975	* VIA: ??
1976	*/
1977	uSubLeaf = 0;
1978	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
1979	{
1980	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
1981	{
1982	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
1983	if (bLevelType == 1)
1984	{
1985	/* Thread level - we don't do threads at the moment. */
1986	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
1987	pCurLeaf->uEbx = 1;
1988	}
1989	else if (bLevelType == 2)
1990	{
1991	/* Core level. */
1992	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
1993	#ifdef VBOX_WITH_MULTI_CORE
1994	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
1995	pCurLeaf->uEax++;
1996	#endif
1997	pCurLeaf->uEbx = pVM->cCpus;
1998	}
1999	else
2000	{
2001	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
2002	pCurLeaf->uEax = 0;
2003	pCurLeaf->uEbx = 0;
2004	pCurLeaf->uEcx = 0;
2005	}
2006	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
2007	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
2008	}
2009	else
2010	{
2011	pCurLeaf->uEax = 0;
2012	pCurLeaf->uEbx = 0;
2013	pCurLeaf->uEcx = 0;
2014	pCurLeaf->uEdx = 0;
2015	}
2016	uSubLeaf++;
2017	}
2018
2019	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
2020	* We zero this since we don't know what it may have been used for.
2021	*/
2022	cpumR3CpuIdZeroLeaf(pCpum, 12);
2023
2024	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
2025	* ECX=0: EAX - Valid bits in XCR0[31:0].
2026	* EBX - Maximum state size as per current XCR0 value.
2027	* ECX - Maximum state size for all supported features.
2028	* EDX - Valid bits in XCR0[63:32].
2029	* ECX=1: EAX - Various X-features.
2030	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
2031	* ECX - Valid bits in IA32_XSS[31:0].
2032	* EDX - Valid bits in IA32_XSS[63:32].
2033	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
2034	* if the bit invalid all four registers are set to zero.
2035	* EAX - The state size for this feature.
2036	* EBX - The state byte offset of this feature.
2037	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
2038	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
2039	*
2040	* Clear them all as we don't currently implement extended CPU state.
2041	*/
2042	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
2043	uint64_t fGuestXcr0Mask = 0;
2044	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2045	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
2046	{
2047	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
2048	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
2049	fGuestXcr0Mask \|= XSAVE_C_YMM;
2050	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
2051	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
2052	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
2053	fGuestXcr0Mask &= pCpum->fXStateHostMask;
2054
2055	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
2056	}
2057	pStdFeatureLeaf = NULL;
2058	pCpum->fXStateGuestMask = fGuestXcr0Mask;
2059
2060	/* Work the sub-leaves. */
2061	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
2062	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
2063	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
2064	{
2065	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
2066	if (pCurLeaf)
2067	{
2068	if (fGuestXcr0Mask)
2069	{
2070	switch (uSubLeaf)
2071	{
2072	case 0:
2073	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
2074	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
2075	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2076	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
2077	VERR_CPUM_IPE_1);
2078	cbXSaveMaxActual = pCurLeaf->uEcx;
2079	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
2080	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
2081	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
2082	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
2083	VERR_CPUM_IPE_2);
2084	continue;
2085	case 1:
2086	pCurLeaf->uEax &= 0;
2087	pCurLeaf->uEcx &= 0;
2088	pCurLeaf->uEdx &= 0;
2089	/** @todo what about checking ebx? */
2090	continue;
2091	default:
2092	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
2093	{
2094	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
2095	&& pCurLeaf->uEax > 0
2096	&& pCurLeaf->uEbx < cbXSaveMaxActual
2097	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2098	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
2099	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
2100	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
2101	VERR_CPUM_IPE_2);
2102	AssertLogRel(!(pCurLeaf->uEcx & 1));
2103	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
2104	pCurLeaf->uEdx = 0; /* it's reserved... */
2105	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
2106	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
2107	continue;
2108	}
2109	break;
2110	}
2111	}
2112
2113	/* Clear the leaf. */
2114	pCurLeaf->uEax = 0;
2115	pCurLeaf->uEbx = 0;
2116	pCurLeaf->uEcx = 0;
2117	pCurLeaf->uEdx = 0;
2118	}
2119	}
2120
2121	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
2122	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
2123	{
2124	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
2125	if (pCurLeaf)
2126	{
2127	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
2128	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
2129	pCurLeaf->uEbx = cbXSaveMaxReport;
2130	pCurLeaf->uEcx = cbXSaveMaxReport;
2131	}
2132	}
2133
2134	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
2135	* We zero this since we don't know what it may have been used for.
2136	*/
2137	cpumR3CpuIdZeroLeaf(pCpum, 14);
2138
2139	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
2140	* also known as Intel Resource Director Technology (RDT) Monitoring
2141	* We zero this as we don't currently virtualize PQM.
2142	*/
2143	cpumR3CpuIdZeroLeaf(pCpum, 15);
2144
2145	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
2146	* also known as Intel Resource Director Technology (RDT) Allocation
2147	* We zero this as we don't currently virtualize PQE.
2148	*/
2149	cpumR3CpuIdZeroLeaf(pCpum, 16);
2150
2151	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
2152	* We zero this since we don't know what it may have been used for.
2153	*/
2154	cpumR3CpuIdZeroLeaf(pCpum, 17);
2155
2156	/* Cpuid 0x12 + ECX: SGX resource enumeration.
2157	* We zero this as we don't currently virtualize this.
2158	*/
2159	cpumR3CpuIdZeroLeaf(pCpum, 18);
2160
2161	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
2162	* We zero this since we don't know what it may have been used for.
2163	*/
2164	cpumR3CpuIdZeroLeaf(pCpum, 19);
2165
2166	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
2167	* We zero this as we don't currently virtualize this.
2168	*/
2169	cpumR3CpuIdZeroLeaf(pCpum, 20);
2170
2171	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
2172	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
2173	* EAX - denominator (unsigned).
2174	* EBX - numerator (unsigned).
2175	* ECX, EDX - reserved.
2176	* AMD: Reserved / undefined / not implemented.
2177	* VIA: Reserved / undefined / not implemented.
2178	* We zero this as we don't currently virtualize this.
2179	*/
2180	cpumR3CpuIdZeroLeaf(pCpum, 21);
2181
2182	/* Cpuid 0x16: Processor frequency info
2183	* Intel: EAX - Core base frequency in MHz.
2184	* EBX - Core maximum frequency in MHz.
2185	* ECX - Bus (reference) frequency in MHz.
2186	* EDX - Reserved.
2187	* AMD: Reserved / undefined / not implemented.
2188	* VIA: Reserved / undefined / not implemented.
2189	* We zero this as we don't currently virtualize this.
2190	*/
2191	cpumR3CpuIdZeroLeaf(pCpum, 22);
2192
2193	/* Cpuid 0x17..0x10000000: Unknown.
2194	* We don't know these and what they mean, so remove them. */
2195	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2196	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
2197
2198
2199	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
2200	* We remove all these as we're a hypervisor and must provide our own.
2201	*/
2202	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2203	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
2204
2205
2206	/* Cpuid 0x80000000 is harmless. */
2207
2208	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
2209
2210	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
2211
2212	/* Cpuid 0x80000005 & 0x80000006 contain information about L1, L2 & L3 cache and TLB identifiers.
2213	* Safe to pass on to the guest.
2214	*
2215	* AMD: 0x80000005 L1 cache information
2216	* 0x80000006 L2/L3 cache information
2217	* Intel: 0x80000005 reserved
2218	* 0x80000006 L2 cache information
2219	* VIA: 0x80000005 TLB and L1 cache information
2220	* 0x80000006 L2 cache information
2221	*/
2222
2223	uSubLeaf = 0;
2224	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000006), uSubLeaf)) != NULL)
2225	{
2226	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2227	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2228	{
2229	/*
2230	* Some AMD CPUs (e.g. Ryzen 7940HS) report zero L3 cache line size here and refer
2231	* to CPUID Fn8000_001D. This triggers division by zero in Linux if the
2232	* TopologyExtensions aka TOPOEXT bit in Fn8000_0001_ECX is not set, or if the kernel
2233	* is old enough (e.g. Linux 3.13) that it does not know about the topology extension
2234	* CPUID leaves.
2235	* We put a non-zero value in the cache line size here, if possible the actual value
2236	* gleaned from Fn8000_001D, or worst case a made-up valid number.
2237	*/
2238	PCPUMCPUIDLEAF pTopoLeaf;
2239	uint32_t uTopoSubLeaf;
2240	uint32_t uCacheLineSize;
2241
2242	if ((pCurLeaf->uEdx & 0xff) == 0)
2243	{
2244	uTopoSubLeaf = 0;
2245
2246	uCacheLineSize = 64; /* Use 64-byte line size as a fallback. */
2247
2248	/* Find L3 cache information. Have to check the cache level in EAX. */
2249	while ((pTopoLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uTopoSubLeaf)) != NULL)
2250	{
2251	if (((pTopoLeaf->uEax >> 5) & 0x07) == 3) {
2252	uCacheLineSize = (pTopoLeaf->uEbx & 0xfff) + 1;
2253	/* Fn8000_0006 can't report power of two line sizes greater than 128. */
2254	if (uCacheLineSize > 128)
2255	uCacheLineSize = 128;
2256
2257	break;
2258	}
2259	uTopoSubLeaf++;
2260	}
2261
2262	Assert(uCacheLineSize < 256);
2263	pCurLeaf->uEdx \|= uCacheLineSize;
2264	LogRel(("CPUM: AMD L3 cache line size in CPUID leaf 0x80000006 was zero, adjusting to %u\n", uCacheLineSize));
2265	}
2266	}
2267	uSubLeaf++;
2268	}
2269
2270	/* Cpuid 0x80000007: Advanced Power Management Information.
2271	* AMD: EAX: Processor feedback capabilities.
2272	* EBX: RAS capabilites.
2273	* ECX: Advanced power monitoring interface.
2274	* EDX: Enhanced power management capabilities.
2275	* Intel: EAX, EBX, ECX - reserved.
2276	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
2277	* VIA: Reserved
2278	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
2279	*/
2280	uSubLeaf = 0;
2281	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
2282	{
2283	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
2284	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2285	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2286	{
2287	/*
2288	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
2289	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
2290	* bit is now configurable.
2291	*/
2292	pCurLeaf->uEdx &= 0
2293	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
2294	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
2295	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
2296	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
2297	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
2298	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
2299	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
2300	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
2301	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
2302	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
2303	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
2304	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
2305	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
2306	\| 0;
2307	}
2308	else
2309	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
2310	if (!pConfig->fInvariantTsc)
2311	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
2312	uSubLeaf++;
2313	}
2314
2315	/* Cpuid 0x80000008:
2316	* AMD: EAX: Long Mode Size Identifiers
2317	* EBX: Extended Feature Identifiers
2318	* ECX: Number of cores + APICIdCoreIdSize
2319	* EDX: RDPRU Register Identifier Range
2320	* Intel: EAX: Virtual/Physical address Size
2321	* EBX, ECX, EDX - reserved
2322	* VIA: EAX: Virtual/Physical address Size
2323	* EBX, ECX, EDX - reserved
2324	*
2325	* We only expose the virtual+pysical address size to the guest atm.
2326	* On AMD we set the core count, but not the apic id stuff as we're
2327	* currently not doing the apic id assignments in a compatible manner.
2328	*/
2329	uSubLeaf = 0;
2330	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
2331	{
2332	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
2333	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2334	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2335	{
2336	/* Expose XSaveErPtr aka RstrFpErrPtrs to guest. */
2337	pCurLeaf->uEbx &= X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR; /* reserved - [12] == IBPB */
2338	}
2339	else
2340	pCurLeaf->uEbx = 0; /* reserved */
2341
2342	pCurLeaf->uEdx = 0; /* reserved */
2343
2344	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
2345	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
2346	pCurLeaf->uEcx = 0;
2347	#ifdef VBOX_WITH_MULTI_CORE
2348	if ( pVM->cCpus > 1
2349	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2350	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
2351	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
2352	#endif
2353	uSubLeaf++;
2354	}
2355
2356	/* Cpuid 0x80000009: Reserved
2357	* We zero this since we don't know what it may have been used for.
2358	*/
2359	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
2360
2361	/* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
2362	* AMD: EAX - SVM revision.
2363	* EBX - Number of ASIDs.
2364	* ECX - Reserved.
2365	* EDX - SVM Feature identification.
2366	*/
2367	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2368	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2369	{
2370	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2371	if ( pExtFeatureLeaf
2372	&& (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM))
2373	{
2374	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
2375	if (pSvmFeatureLeaf)
2376	{
2377	pSvmFeatureLeaf->uEax = 0x1;
2378	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
2379	pSvmFeatureLeaf->uEcx = 0;
2380	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
2381	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
2382	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
2383	}
2384	else
2385	{
2386	/* Should never happen. */
2387	LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
2388	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2389	}
2390	}
2391	else
2392	{
2393	/* If SVM is not supported, this is reserved, zero out. */
2394	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2395	}
2396	}
2397	else
2398	{
2399	/* Cpuid 0x8000000a: Reserved on Intel.
2400	* We zero this since we don't know what it may have been used for.
2401	*/
2402	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2403	}
2404
2405	/* Cpuid 0x8000000b thru 0x80000018: Reserved
2406	* We clear these as we don't know what purpose they might have. */
2407	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
2408	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
2409
2410	/* Cpuid 0x80000019: TLB configuration
2411	* Seems to be harmless, pass them thru as is. */
2412
2413	/* Cpuid 0x8000001a: Peformance optimization identifiers.
2414	* Strip anything we don't know what is or addresses feature we don't implement. */
2415	uSubLeaf = 0;
2416	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
2417	{
2418	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
2419	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
2420	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
2421	;
2422	pCurLeaf->uEbx = 0; /* reserved */
2423	pCurLeaf->uEcx = 0; /* reserved */
2424	pCurLeaf->uEdx = 0; /* reserved */
2425	uSubLeaf++;
2426	}
2427
2428	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
2429	* Clear this as we don't currently virtualize this feature. */
2430	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
2431
2432	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
2433	* Clear this as we don't currently virtualize this feature. */
2434	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
2435
2436	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
2437	* We need to sanitize the cores per cache (EAX[25:14]).
2438	*
2439	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
2440	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
2441	* slightly different meaning.
2442	*/
2443	uSubLeaf = 0;
2444	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
2445	{
2446	#ifdef VBOX_WITH_MULTI_CORE
2447	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
2448	if (cCores > pVM->cCpus)
2449	cCores = pVM->cCpus;
2450	pCurLeaf->uEax &= UINT32_C(0x00003fff);
2451	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
2452	#else
2453	pCurLeaf->uEax &= UINT32_C(0x00003fff);
2454	#endif
2455	uSubLeaf++;
2456	}
2457
2458	/* Cpuid 0x8000001e: Get APIC / unit / node information.
2459	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
2460	* setup, we have one compute unit with all the cores in it. Single node.
2461	*/
2462	uSubLeaf = 0;
2463	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
2464	{
2465	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
2466	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
2467	{
2468	#ifdef VBOX_WITH_MULTI_CORE
2469	pCurLeaf->uEbx = pVM->cCpus < 0x100
2470	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
2471	#else
2472	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
2473	#endif
2474	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
2475	}
2476	else
2477	{
2478	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
2479	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_HYGON);
2480	pCurLeaf->uEbx = 0; /* Reserved. */
2481	pCurLeaf->uEcx = 0; /* Reserved. */
2482	}
2483	pCurLeaf->uEdx = 0; /* Reserved. */
2484	uSubLeaf++;
2485	}
2486
2487	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
2488	* We don't know these and what they mean, so remove them. */
2489	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2490	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
2491
2492	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
2493	* Just pass it thru for now. */
2494
2495	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
2496	* Just pass it thru for now. */
2497
2498	/* Cpuid 0xc0000000: Centaur stuff.
2499	* Harmless, pass it thru. */
2500
2501	/* Cpuid 0xc0000001: Centaur features.
2502	* VIA: EAX - Family, model, stepping.
2503	* EDX - Centaur extended feature flags. Nothing interesting, except may
2504	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
2505	* EBX, ECX - reserved.
2506	* We keep EAX but strips the rest.
2507	*/
2508	uSubLeaf = 0;
2509	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
2510	{
2511	pCurLeaf->uEbx = 0;
2512	pCurLeaf->uEcx = 0;
2513	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
2514	uSubLeaf++;
2515	}
2516
2517	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
2518	* We only have fixed stale values, but should be harmless. */
2519
2520	/* Cpuid 0xc0000003: Reserved.
2521	* We zero this since we don't know what it may have been used for.
2522	*/
2523	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
2524
2525	/* Cpuid 0xc0000004: Centaur Performance Info.
2526	* We only have fixed stale values, but should be harmless. */
2527
2528
2529	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
2530	* We don't know these and what they mean, so remove them. */
2531	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2532	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
2533
2534	return VINF_SUCCESS;
2535	#undef PORTABLE_DISABLE_FEATURE_BIT
2536	#undef PORTABLE_CLEAR_BITS_WHEN
2537	}
2538
2539
2540	/**
2541	* Reads a value in /CPUM/IsaExts/ node.
2542	*
2543	* @returns VBox status code (error message raised).
2544	* @param pVM The cross context VM structure. (For errors.)
2545	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2546	* @param pszValueName The value / extension name.
2547	* @param penmValue Where to return the choice.
2548	* @param enmDefault The default choice.
2549	*/
2550	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
2551	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
2552	{
2553	/*
2554	* Try integer encoding first.
2555	*/
2556	uint64_t uValue;
2557	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
2558	if (RT_SUCCESS(rc))
2559	switch (uValue)
2560	{
2561	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
2562	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
2563	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
2564	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
2565	default:
2566	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
2567	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
2568	pszValueName, uValue);
2569	}
2570	/*
2571	* If missing, use default.
2572	*/
2573	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
2574	*penmValue = enmDefault;
2575	else
2576	{
2577	if (rc == VERR_CFGM_NOT_INTEGER)
2578	{
2579	/*
2580	* Not an integer, try read it as a string.
2581	*/
2582	char szValue[32];
2583	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
2584	if (RT_SUCCESS(rc))
2585	{
2586	RTStrToLower(szValue);
2587	size_t cchValue = strlen(szValue);
2588	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
2589	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
2590	*penmValue = CPUMISAEXTCFG_DISABLED;
2591	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
2592	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
2593	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
2594	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
2595	else if (EQ("portable"))
2596	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
2597	else if (EQ("default") \|\| EQ("def"))
2598	*penmValue = enmDefault;
2599	else
2600	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
2601	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
2602	pszValueName, uValue);
2603	#undef EQ
2604	}
2605	}
2606	if (RT_FAILURE(rc))
2607	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
2608	}
2609	return VINF_SUCCESS;
2610	}
2611
2612
2613	/**
2614	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
2615	*
2616	* @returns VBox status code (error message raised).
2617	* @param pVM The cross context VM structure. (For errors.)
2618	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2619	* @param pszValueName The value / extension name.
2620	* @param penmValue Where to return the choice.
2621	* @param enmDefault The default choice.
2622	* @param fAllowed Allowed choice. Applied both to the result and to
2623	* the default value.
2624	*/
2625	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
2626	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
2627	{
2628	int rc;
2629	if (fAllowed)
2630	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
2631	else
2632	{
2633	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
2634	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
2635	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
2636	*penmValue = CPUMISAEXTCFG_DISABLED;
2637	}
2638	return rc;
2639	}
2640
2641
2642	/**
2643	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
2644	*
2645	* @returns VBox status code (error message raised).
2646	* @param pVM The cross context VM structure. (For errors.)
2647	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2648	* @param pCpumCfg The /CPUM node (can be NULL).
2649	* @param pszValueName The value / extension name.
2650	* @param penmValue Where to return the choice.
2651	* @param enmDefault The default choice.
2652	*/
2653	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
2654	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
2655	{
2656	if (CFGMR3Exists(pCpumCfg, pszValueName))
2657	{
2658	if (!CFGMR3Exists(pIsaExts, pszValueName))
2659	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
2660	else
2661	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
2662	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
2663	pszValueName, pszValueName);
2664
2665	bool fLegacy;
2666	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
2667	if (RT_SUCCESS(rc))
2668	{
2669	*penmValue = fLegacy;
2670	return VINF_SUCCESS;
2671	}
2672	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
2673	}
2674
2675	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
2676	}
2677
2678
2679	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
2680	{
2681	int rc;
2682
2683	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
2684	* When non-zero CPUID features that could cause portability issues will be
2685	* stripped. The higher the value the more features gets stripped. Higher
2686	* values should only be used when older CPUs are involved since it may
2687	* harm performance and maybe also cause problems with specific guests. */
2688	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
2689	AssertLogRelRCReturn(rc, rc);
2690
2691	/** @cfgm{/CPUM/GuestCpuName, string}
2692	* The name of the CPU we're to emulate. The default is the host CPU.
2693	* Note! CPUs other than "host" one is currently unsupported. */
2694	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
2695	AssertLogRelRCReturn(rc, rc);
2696
2697	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
2698	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
2699	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
2700	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
2701	*/
2702	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
2703	AssertLogRelRCReturn(rc, rc);
2704
2705	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
2706	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
2707	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
2708	* 64-bit linux guests which assume the presence of AMD performance counters
2709	* that we do not virtualize.
2710	*/
2711	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
2712	AssertLogRelRCReturn(rc, rc);
2713
2714	/** @cfgm{/CPUM/ForceVme, boolean, false}
2715	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
2716	* By default the flag is passed thru as is from the host CPU, except
2717	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
2718	* guests and DOS boxes in general.
2719	*/
2720	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
2721	AssertLogRelRCReturn(rc, rc);
2722
2723	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
2724	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
2725	* probably going to be a temporary hack, so don't depend on this.
2726	* The 1st byte of the value is the stepping, the 2nd byte value is the model
2727	* number and the 3rd byte value is the family, and the 4th value must be zero.
2728	*/
2729	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
2730	AssertLogRelRCReturn(rc, rc);
2731
2732	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
2733	* The last standard leaf to keep. The actual last value that is stored in EAX
2734	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
2735	* removed. (This works independently of and differently from NT4LeafLimit.)
2736	* The default is usually set to what we're able to reasonably sanitize.
2737	*/
2738	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
2739	AssertLogRelRCReturn(rc, rc);
2740
2741	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
2742	* The last extended leaf to keep. The actual last value that is stored in EAX
2743	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
2744	* leaf are removed. The default is set to what we're able to sanitize.
2745	*/
2746	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
2747	AssertLogRelRCReturn(rc, rc);
2748
2749	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
2750	* The last extended leaf to keep. The actual last value that is stored in EAX
2751	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
2752	* leaf are removed. The default is set to what we're able to sanitize.
2753	*/
2754	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
2755	AssertLogRelRCReturn(rc, rc);
2756
2757	bool fQueryNestedHwvirt = false
2758	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2759	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2760	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON
2761	#endif
2762	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2763	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
2764	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA
2765	#endif
2766	;
2767	if (fQueryNestedHwvirt)
2768	{
2769	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
2770	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
2771	* The default is false, and when enabled requires a 64-bit CPU with support for
2772	* nested-paging and AMD-V or unrestricted guest mode.
2773	*/
2774	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
2775	AssertLogRelRCReturn(rc, rc);
2776	if (pConfig->fNestedHWVirt)
2777	{
2778	/** @todo Think about enabling this later with NEM/KVM. */
2779	if (VM_IS_NEM_ENABLED(pVM))
2780	{
2781	LogRel(("CPUM: Warning! Can't turn on nested VT-x/AMD-V when NEM is used! (later)\n"));
2782	pConfig->fNestedHWVirt = false;
2783	}
2784	else if (!fNestedPagingAndFullGuestExec)
2785	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
2786	"Cannot enable nested VT-x/AMD-V without nested-paging and unrestricted guest execution!\n");
2787	}
2788	}
2789
2790	/*
2791	* Instruction Set Architecture (ISA) Extensions.
2792	*/
2793	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
2794	if (pIsaExts)
2795	{
2796	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
2797	"CMPXCHG16B"
2798	"\|MONITOR"
2799	"\|MWaitExtensions"
2800	"\|SSE4.1"
2801	"\|SSE4.2"
2802	"\|XSAVE"
2803	"\|AVX"
2804	"\|AVX2"
2805	"\|AESNI"
2806	"\|PCLMUL"
2807	"\|POPCNT"
2808	"\|MOVBE"
2809	"\|RDRAND"
2810	"\|RDSEED"
2811	"\|ADX"
2812	"\|CLFLUSHOPT"
2813	"\|SHA"
2814	"\|FSGSBASE"
2815	"\|PCID"
2816	"\|INVPCID"
2817	"\|FlushCmdMsr"
2818	"\|ABM"
2819	"\|SSE4A"
2820	"\|MISALNSSE"
2821	"\|3DNOWPRF"
2822	"\|AXMMX"
2823	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
2824	if (RT_FAILURE(rc))
2825	return rc;
2826	}
2827
2828	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, true}
2829	* Expose CMPXCHG16B to the guest if available. All host CPUs which support
2830	* hardware virtualization have it.
2831	*/
2832	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, true);
2833	AssertLogRelRCReturn(rc, rc);
2834
2835	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
2836	* Expose MONITOR/MWAIT instructions to the guest.
2837	*/
2838	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
2839	AssertLogRelRCReturn(rc, rc);
2840
2841	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
2842	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
2843	* break on interrupt feature (bit 1).
2844	*/
2845	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
2846	AssertLogRelRCReturn(rc, rc);
2847
2848	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
2849	* Expose SSE4.1 to the guest if available.
2850	*/
2851	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
2852	AssertLogRelRCReturn(rc, rc);
2853
2854	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
2855	* Expose SSE4.2 to the guest if available.
2856	*/
2857	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
2858	AssertLogRelRCReturn(rc, rc);
2859
2860	bool const fMayHaveXSave = pVM->cpum.s.HostFeatures.fXSaveRstor
2861	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
2862	&& ( VM_IS_NEM_ENABLED(pVM)
2863	? NEMHCGetFeatures(pVM) & NEM_FEAT_F_XSAVE_XRSTOR
2864	: VM_IS_EXEC_ENGINE_IEM(pVM)
2865	? false /** @todo IEM and XSAVE @bugref{9898} */
2866	: fNestedPagingAndFullGuestExec);
2867	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
2868
2869	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
2870	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
2871	* default is to only expose this to VMs with nested paging and AMD-V or
2872	* unrestricted guest execution mode. Not possible to force this one without
2873	* host support at the moment.
2874	*/
2875	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
2876	fMayHaveXSave /fAllowed/);
2877	AssertLogRelRCReturn(rc, rc);
2878
2879	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
2880	* Expose the AVX instruction set extensions to the guest if available and
2881	* XSAVE is exposed too. For the time being the default is to only expose this
2882	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
2883	*/
2884	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
2885	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
2886	AssertLogRelRCReturn(rc, rc);
2887
2888	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
2889	* Expose the AVX2 instruction set extensions to the guest if available and
2890	* XSAVE is exposed too. For the time being the default is to only expose this
2891	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
2892	*/
2893	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
2894	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
2895	AssertLogRelRCReturn(rc, rc);
2896
2897	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
2898	* Whether to expose the AES instructions to the guest. For the time being the
2899	* default is to only do this for VMs with nested paging and AMD-V or
2900	* unrestricted guest mode.
2901	*/
2902	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
2903	AssertLogRelRCReturn(rc, rc);
2904
2905	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
2906	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
2907	* being the default is to only do this for VMs with nested paging and AMD-V or
2908	* unrestricted guest mode.
2909	*/
2910	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
2911	AssertLogRelRCReturn(rc, rc);
2912
2913	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, true}
2914	* Whether to expose the POPCNT instructions to the guest.
2915	*/
2916	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, CPUMISAEXTCFG_ENABLED_SUPPORTED);
2917	AssertLogRelRCReturn(rc, rc);
2918
2919	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
2920	* Whether to expose the MOVBE instructions to the guest. For the time
2921	* being the default is to only do this for VMs with nested paging and AMD-V or
2922	* unrestricted guest mode.
2923	*/
2924	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
2925	AssertLogRelRCReturn(rc, rc);
2926
2927	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
2928	* Whether to expose the RDRAND instructions to the guest. For the time being
2929	* the default is to only do this for VMs with nested paging and AMD-V or
2930	* unrestricted guest mode.
2931	*/
2932	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
2933	AssertLogRelRCReturn(rc, rc);
2934
2935	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
2936	* Whether to expose the RDSEED instructions to the guest. For the time being
2937	* the default is to only do this for VMs with nested paging and AMD-V or
2938	* unrestricted guest mode.
2939	*/
2940	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
2941	AssertLogRelRCReturn(rc, rc);
2942
2943	/** @cfgm{/CPUM/IsaExts/ADX, isaextcfg, depends}
2944	* Whether to expose the ADX instructions to the guest. For the time being
2945	* the default is to only do this for VMs with nested paging and AMD-V or
2946	* unrestricted guest mode.
2947	*/
2948	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ADX", &pConfig->enmAdx, fNestedPagingAndFullGuestExec);
2949	AssertLogRelRCReturn(rc, rc);
2950
2951	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
2952	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
2953	* being the default is to only do this for VMs with nested paging and AMD-V or
2954	* unrestricted guest mode.
2955	*/
2956	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
2957	AssertLogRelRCReturn(rc, rc);
2958
2959	/** @cfgm{/CPUM/IsaExts/SHA, isaextcfg, depends}
2960	* Whether to expose the SHA instructions to the guest. For the time being
2961	* the default is to only do this for VMs with nested paging and AMD-V or
2962	* unrestricted guest mode.
2963	*/
2964	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SHA", &pConfig->enmSha, fNestedPagingAndFullGuestExec);
2965	AssertLogRelRCReturn(rc, rc);
2966
2967	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
2968	* Whether to expose the read/write FSGSBASE instructions to the guest.
2969	*/
2970	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
2971	AssertLogRelRCReturn(rc, rc);
2972
2973	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
2974	* Whether to expose the PCID feature to the guest.
2975	*/
2976	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
2977	AssertLogRelRCReturn(rc, rc);
2978
2979	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
2980	* Whether to expose the INVPCID instruction to the guest.
2981	*/
2982	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
2983	AssertLogRelRCReturn(rc, rc);
2984
2985	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
2986	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
2987	*/
2988	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
2989	AssertLogRelRCReturn(rc, rc);
2990
2991	/** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
2992	* Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
2993	* the guest. Requires FlushCmdMsr to be present too.
2994	*/
2995	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
2996	AssertLogRelRCReturn(rc, rc);
2997
2998	/** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
2999	* Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
3000	*/
3001	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
3002	AssertLogRelRCReturn(rc, rc);
3003
3004
3005	/* AMD: */
3006
3007	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, true}
3008	* Whether to expose the AMD ABM instructions to the guest.
3009	*/
3010	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, CPUMISAEXTCFG_ENABLED_SUPPORTED);
3011	AssertLogRelRCReturn(rc, rc);
3012
3013	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
3014	* Whether to expose the AMD SSE4A instructions to the guest. For the time
3015	* being the default is to only do this for VMs with nested paging and AMD-V or
3016	* unrestricted guest mode.
3017	*/
3018	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
3019	AssertLogRelRCReturn(rc, rc);
3020
3021	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
3022	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
3023	* the time being the default is to only do this for VMs with nested paging and
3024	* AMD-V or unrestricted guest mode.
3025	*/
3026	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
3027	AssertLogRelRCReturn(rc, rc);
3028
3029	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
3030	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
3031	* For the time being the default is to only do this for VMs with nested paging
3032	* and AMD-V or unrestricted guest mode.
3033	*/
3034	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
3035	AssertLogRelRCReturn(rc, rc);
3036
3037	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
3038	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
3039	* the default is to only do this for VMs with nested paging and AMD-V or
3040	* unrestricted guest mode.
3041	*/
3042	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
3043	AssertLogRelRCReturn(rc, rc);
3044
3045	return VINF_SUCCESS;
3046	}
3047
3048
3049	/**
3050	* Initializes the emulated CPU's CPUID & MSR information.
3051	*
3052	* @returns VBox status code.
3053	* @param pVM The cross context VM structure.
3054	* @param pHostMsrs Pointer to the host MSRs.
3055	*/
3056	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
3057	{
3058	Assert(pHostMsrs);
3059
3060	PCPUM pCpum = &pVM->cpum.s;
3061	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
3062
3063	/*
3064	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
3065	* on construction and manage everything from here on.
3066	*/
3067	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3068	{
3069	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3070	pVCpu->cpum.s.fCpuIdApicFeatureVisible = true;
3071	}
3072
3073	/*
3074	* Read the configuration.
3075	*/
3076	CPUMCPUIDCONFIG Config;
3077	RT_ZERO(Config);
3078
3079	bool const fNestedPagingAndFullGuestExec = VM_IS_NEM_ENABLED(pVM)
3080	\|\| HMAreNestedPagingAndFullGuestExecEnabled(pVM);
3081	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, fNestedPagingAndFullGuestExec);
3082	AssertRCReturn(rc, rc);
3083
3084	/*
3085	* Get the guest CPU data from the database and/or the host.
3086	*
3087	* The CPUID and MSRs are currently living on the regular heap to avoid
3088	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
3089	* API for the hyper heap). This means special cleanup considerations.
3090	*/
3091	/** @todo The hyper heap will be removed ASAP, so the final destination is
3092	* now a fixed sized arrays in the VM structure. Maybe we can simplify
3093	* this allocation fun a little now? Or maybe it's too convenient for
3094	* the CPU reporter code... No time to figure that out now. */
3095	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
3096	if (RT_FAILURE(rc))
3097	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
3098	? VMSetError(pVM, rc, RT_SRC_POS,
3099	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
3100	: rc;
3101
3102	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
3103	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
3104	{
3105	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
3106	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
3107	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
3108	}
3109	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
3110	#else
3111	LogRel(("CPUM: MXCSR_MASK=%#x\n", pCpum->GuestInfo.fMxCsrMask));
3112	#endif
3113
3114	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
3115	* Overrides the guest MSRs.
3116	*/
3117	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
3118
3119	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
3120	* Overrides the CPUID leaf values (from the host CPU usually) used for
3121	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
3122	* values when moving a VM to a different machine. Another use is restricting
3123	* (or extending) the feature set exposed to the guest. */
3124	if (RT_SUCCESS(rc))
3125	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
3126
3127	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
3128	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
3129	"Found unsupported configuration node '/CPUM/CPUID/'. "
3130	"Please use IMachine::setCPUIDLeaf() instead.");
3131
3132	CPUMMSRS GuestMsrs;
3133	RT_ZERO(GuestMsrs);
3134
3135	/*
3136	* Pre-explode the CPUID info.
3137	*/
3138	if (RT_SUCCESS(rc))
3139	rc = cpumCpuIdExplodeFeaturesX86(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
3140	&pCpum->GuestFeatures);
3141
3142	/*
3143	* Sanitize the cpuid information passed on to the guest.
3144	*/
3145	if (RT_SUCCESS(rc))
3146	{
3147	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
3148	if (RT_SUCCESS(rc))
3149	{
3150	cpumR3CpuIdLimitLeaves(pCpum, &Config);
3151	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
3152	}
3153	}
3154
3155	/*
3156	* Setup MSRs introduced in microcode updates or that are otherwise not in
3157	* the CPU profile, but are advertised in the CPUID info we just sanitized.
3158	*/
3159	if (RT_SUCCESS(rc))
3160	rc = cpumR3MsrReconcileWithCpuId(pVM);
3161	/*
3162	* MSR fudging.
3163	*/
3164	if (RT_SUCCESS(rc))
3165	{
3166	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
3167	* Fudges some common MSRs if not present in the selected CPU database entry.
3168	* This is for trying to keep VMs running when moved between different hosts
3169	* and different CPU vendors. */
3170	bool fEnable;
3171	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
3172	if (RT_SUCCESS(rc) && fEnable)
3173	{
3174	rc = cpumR3MsrApplyFudge(pVM);
3175	AssertLogRelRC(rc);
3176	}
3177	}
3178	if (RT_SUCCESS(rc))
3179	{
3180	/*
3181	* Move the MSR and CPUID arrays over to the static VM structure allocations
3182	* and explode guest CPU features again.
3183	*/
3184	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
3185	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
3186	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
3187	RTMemFree(pvFree);
3188
3189	AssertFatalMsg(pCpum->GuestInfo.cMsrRanges <= RT_ELEMENTS(pCpum->GuestInfo.aMsrRanges),
3190	("%u\n", pCpum->GuestInfo.cMsrRanges));
3191	memcpy(pCpum->GuestInfo.aMsrRanges, pCpum->GuestInfo.paMsrRangesR3,
3192	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges);
3193	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
3194	pCpum->GuestInfo.paMsrRangesR3 = pCpum->GuestInfo.aMsrRanges;
3195
3196	AssertLogRelRCReturn(rc, rc);
3197
3198	/*
3199	* Some more configuration that we're applying at the end of everything
3200	* via the CPUMR3SetGuestCpuIdFeature API.
3201	*/
3202
3203	/* Check if 64-bit guest supported was enabled. */
3204	bool fEnable64bit;
3205	rc = CFGMR3QueryBoolDef(pCpumCfg, "Enable64bit", &fEnable64bit, false);
3206	AssertRCReturn(rc, rc);
3207	if (fEnable64bit)
3208	{
3209	/* In case of a CPU upgrade: */
3210	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
3211	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* (Long mode only on Intel CPUs.) */
3212	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
3213	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
3214	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
3215
3216	/* The actual feature: */
3217	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
3218	}
3219
3220	/* Check if PAE was explicitely enabled by the user. */
3221	bool fEnable;
3222	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, fEnable64bit);
3223	AssertRCReturn(rc, rc);
3224	if (fEnable && !pVM->cpum.s.GuestFeatures.fPae)
3225	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
3226
3227	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
3228	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, fEnable64bit);
3229	AssertRCReturn(rc, rc);
3230	if (fEnable && !pVM->cpum.s.GuestFeatures.fNoExecute)
3231	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
3232
3233	/* Check if speculation control is enabled. */
3234	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
3235	AssertRCReturn(rc, rc);
3236	if (fEnable)
3237	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
3238	else
3239	{
3240	/*
3241	* Set the "SSBD-not-needed" flag to work around a bug in some Linux kernels when the VIRT_SPEC_CTL
3242	* feature is not exposed on AMD CPUs and there is only 1 vCPU configured.
3243	* This was observed with kernel "4.15.0-29-generic #31~16.04.1-Ubuntu" but more versions are likely affected.
3244	*
3245	* The kernel doesn't initialize a lock and causes a NULL pointer exception later on when configuring SSBD:
3246	* EIP: _raw_spin_lock+0x14/0x30
3247	* EFLAGS: 00010046 CPU: 0
3248	* EAX: 00000000 EBX: 00000001 ECX: 00000004 EDX: 00000000
3249	* ESI: 00000000 EDI: 00000000 EBP: ee023f1c ESP: ee023f18
3250	* DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
3251	* CR0: 80050033 CR2: 00000004 CR3: 3671c180 CR4: 000006f0
3252	* Call Trace:
3253	* speculative_store_bypass_update+0x8e/0x180
3254	* ssb_prctl_set+0xc0/0xe0
3255	* arch_seccomp_spec_mitigate+0x1d/0x20
3256	* do_seccomp+0x3cb/0x610
3257	* SyS_seccomp+0x16/0x20
3258	* do_fast_syscall_32+0x7f/0x1d0
3259	* entry_SYSENTER_32+0x4e/0x7c
3260	*
3261	* The lock would've been initialized in process.c:speculative_store_bypass_ht_init() called from two places in smpboot.c.
3262	* First when a secondary CPU is started and second in native_smp_prepare_cpus() which is not called in a single vCPU environment.
3263	*
3264	* As spectre control features are completely disabled anyway when we arrived here there is no harm done in informing the
3265	* guest to not even try.
3266	*/
3267	if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3268	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3269	{
3270	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x80000008), 0);
3271	if (pLeaf)
3272	{
3273	pLeaf->uEbx \|= X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED;
3274	LogRel(("CPUM: Set SSBD not required flag for AMD to work around some buggy Linux kernels!\n"));
3275	}
3276	}
3277	}
3278
3279	/*
3280	* MTRR support.
3281	* We've always reported the MTRR feature bit in CPUID.
3282	* Here we allow exposing MTRRs with reasonable default values just to get Nested Hyper-V
3283	* going. MTRR support isn't feature complete, see @bugref{10318} and bugref{10498}.
3284	*/
3285	if (pVM->cpum.s.GuestFeatures.fMtrr)
3286	{
3287	/* Check if MTRR read+write support is enabled. */
3288	bool fEnableMtrrWrite;
3289	rc = CFGMR3QueryBoolDef(pCpumCfg, "MTRRWrite", &fEnableMtrrWrite, true);
3290	AssertRCReturn(rc, rc);
3291	if (fEnableMtrrWrite)
3292	{
3293	pVM->cpum.s.fMtrrRead = true;
3294	pVM->cpum.s.fMtrrWrite = true;
3295	LogRel(("CPUM: Enabled MTRR read-write support\n"));
3296	}
3297	else
3298	{
3299	/* Check if MTRR read-only reporting is enabled. */
3300	rc = CFGMR3QueryBoolDef(pCpumCfg, "MTRR", &pVM->cpum.s.fMtrrRead, true);
3301	AssertRCReturn(rc, rc);
3302	LogRel(("CPUM: Enabled MTRR read-only support\n"));
3303	}
3304
3305	/* Setup MTRR capability based on what the host supports. */
3306	Assert(!pVM->cpum.s.fMtrrWrite \|\| pVM->cpum.s.fMtrrRead);
3307	if (pVM->cpum.s.fMtrrRead)
3308	{
3309	Assert(pVM->cpum.s.HostFeatures.fMtrr);
3310
3311	/* Lookup the number of variable-range MTRRs supported on the host. */
3312	PCCPUMMSRRANGE pMtrrCapRange = cpumLookupMsrRange(pVM, MSR_IA32_MTRR_CAP);
3313	AssertLogRelReturn(pMtrrCapRange, VERR_CPUM_IPE_2);
3314	uint8_t const cHostVarRangeRegs = pMtrrCapRange->uValue & MSR_IA32_MTRR_CAP_VCNT_MASK;
3315
3316	/* Construct guest MTRR support capabilities. */
3317	uint8_t const cGuestVarRangeRegs = RT_MIN(cHostVarRangeRegs, CPUMCTX_MAX_MTRRVAR_COUNT);
3318	uint64_t const uGstMtrrCap = cGuestVarRangeRegs
3319	\| MSR_IA32_MTRR_CAP_FIX
3320	\| MSR_IA32_MTRR_CAP_WC;
3321	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3322	{
3323	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3324	pVCpu->cpum.s.GuestMsrs.msr.MtrrCap = uGstMtrrCap;
3325	pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = MSR_IA32_MTRR_DEF_TYPE_FIXED_EN
3326	\| MSR_IA32_MTRR_DEF_TYPE_MTRR_EN
3327	\| X86_MTRR_MT_UC;
3328	}
3329	LogRel(("CPUM: Enabled fixed-range MTRRs and %u variable-range MTRRs\n", cGuestVarRangeRegs));
3330	}
3331	}
3332
3333	/*
3334	* Finally, initialize guest VMX MSRs.
3335	*
3336	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
3337	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
3338	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
3339	*/
3340	/** @todo r=bird: given that long mode never used to be enabled before the
3341	* VMINITCOMPLETED_RING0 state, and we're a lot earlier here in ring-3
3342	* init, the above comment cannot be entirely accurate. */
3343	if (pVM->cpum.s.GuestFeatures.fVmx)
3344	{
3345	Assert(Config.fNestedHWVirt);
3346	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, pCpumCfg, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
3347
3348	/* Copy MSRs to all VCPUs */
3349	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
3350	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3351	{
3352	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3353	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
3354	}
3355	}
3356
3357	return VINF_SUCCESS;
3358	}
3359
3360	/*
3361	* Failed before switching to hyper heap.
3362	*/
3363	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
3364	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
3365	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
3366	pCpum->GuestInfo.paMsrRangesR3 = NULL;
3367	return rc;
3368	}
3369
3370
3371	/**
3372	* Sets a CPUID feature bit during VM initialization.
3373	*
3374	* Since the CPUID feature bits are generally related to CPU features, other
3375	* CPUM configuration like MSRs can also be modified by calls to this API.
3376	*
3377	* @param pVM The cross context VM structure.
3378	* @param enmFeature The feature to set.
3379	*/
3380	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
3381	{
3382	PCPUMCPUIDLEAF pLeaf;
3383	PCPUMMSRRANGE pMsrRange;
3384
3385	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
3386	# define CHECK_X86_HOST_FEATURE_RET(a_fFeature, a_szFeature) \
3387	if (!pVM->cpum.s.HostFeatures. a_fFeature) \
3388	{ \
3389	LogRel(("CPUM: WARNING! Can't turn on " a_szFeature " when the host doesn't support it!\n")); \
3390	return; \
3391	} else do { } while (0)
3392	#else
3393	# define CHECK_X86_HOST_FEATURE_RET(a_fFeature, a_szFeature) do { } while (0)
3394	#endif
3395
3396	#define GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(a_fFeature, a_szFeature) \
3397	do \
3398	{ \
3399	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001)); \
3400	if (!pLeaf) \
3401	{ \
3402	LogRel(("CPUM: WARNING! Can't turn on " a_szFeature " when no 0x80000001 CPUID leaf!\n")); \
3403	return; \
3404	} \
3405	CHECK_X86_HOST_FEATURE_RET(a_fFeature,a_szFeature); \
3406	} while (0)
3407
3408	switch (enmFeature)
3409	{
3410	/*
3411	* Set the APIC bit in both feature masks.
3412	*/
3413	case CPUMCPUIDFEATURE_APIC:
3414	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3415	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
3416	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
3417
3418	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3419	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
3420	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
3421
3422	pVM->cpum.s.GuestFeatures.fApic = 1;
3423
3424	/* Make sure we've got the APICBASE MSR present. */
3425	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
3426	if (!pMsrRange)
3427	{
3428	static CPUMMSRRANGE const s_ApicBase =
3429	{
3430	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
3431	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
3432	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3433	/.szName = / "IA32_APIC_BASE"
3434	};
3435	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
3436	AssertLogRelRC(rc);
3437	}
3438
3439	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
3440	break;
3441
3442	/*
3443	* Set the x2APIC bit in the standard feature mask.
3444	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
3445	*/
3446	case CPUMCPUIDFEATURE_X2APIC:
3447	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3448	if (pLeaf)
3449	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
3450	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
3451
3452	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
3453	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
3454	if (pMsrRange)
3455	{
3456	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
3457	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
3458	}
3459
3460	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
3461	break;
3462
3463	/*
3464	* Set the sysenter/sysexit bit in the standard feature mask.
3465	* Assumes the caller knows what it's doing! (host must support these)
3466	*/
3467	case CPUMCPUIDFEATURE_SEP:
3468	CHECK_X86_HOST_FEATURE_RET(fSysEnter, "SEP");
3469	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3470	if (pLeaf)
3471	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
3472	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
3473	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
3474	break;
3475
3476	/*
3477	* Set the syscall/sysret bit in the extended feature mask.
3478	* Assumes the caller knows what it's doing! (host must support these)
3479	*/
3480	case CPUMCPUIDFEATURE_SYSCALL:
3481	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fSysCall, "SYSCALL/SYSRET");
3482
3483	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
3484	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
3485	pVM->cpum.s.GuestFeatures.fSysCall = 1;
3486	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
3487	break;
3488
3489	/*
3490	* Set the PAE bit in both feature masks.
3491	* Assumes the caller knows what it's doing! (host must support these)
3492	*/
3493	case CPUMCPUIDFEATURE_PAE:
3494	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3495	if (pLeaf)
3496	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
3497
3498	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3499	if ( pLeaf
3500	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3501	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3502	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
3503
3504	pVM->cpum.s.GuestFeatures.fPae = 1;
3505	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
3506	break;
3507
3508	/*
3509	* Set the LONG MODE bit in the extended feature mask.
3510	* Assumes the caller knows what it's doing! (host must support these)
3511	*/
3512	case CPUMCPUIDFEATURE_LONG_MODE:
3513	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fLongMode, "LONG MODE");
3514
3515	/* Valid for both Intel and AMD. */
3516	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
3517	pVM->cpum.s.GuestFeatures.fLongMode = 1;
3518	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
3519	if (pVM->cpum.s.GuestFeatures.fVmx)
3520	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3521	{
3522	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3523	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic &= ~VMX_BASIC_PHYSADDR_WIDTH_32BIT;
3524	}
3525	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
3526	break;
3527
3528	/*
3529	* Set the NX/XD bit in the extended feature mask.
3530	* Assumes the caller knows what it's doing! (host must support these)
3531	*/
3532	case CPUMCPUIDFEATURE_NX:
3533	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fNoExecute, "NX/XD");
3534
3535	/* Valid for both Intel and AMD. */
3536	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
3537	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
3538	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
3539	break;
3540
3541
3542	/*
3543	* Set the LAHF/SAHF support in 64-bit mode.
3544	* Assumes the caller knows what it's doing! (host must support this)
3545	*/
3546	case CPUMCPUIDFEATURE_LAHF:
3547	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fLahfSahf, "LAHF/SAHF");
3548
3549	/* Valid for both Intel and AMD. */
3550	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
3551	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
3552	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
3553	break;
3554
3555	/*
3556	* Set the RDTSCP support bit.
3557	* Assumes the caller knows what it's doing! (host must support this)
3558	*/
3559	case CPUMCPUIDFEATURE_RDTSCP:
3560	if (pVM->cpum.s.u8PortableCpuIdLevel > 0)
3561	return;
3562	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fRdTscP, "RDTSCP");
3563	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3564
3565	/* Valid for both Intel and AMD. */
3566	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
3567	pVM->cpum.s.HostFeatures.fRdTscP = 1;
3568	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
3569	break;
3570
3571	/*
3572	* Set the Hypervisor Present bit in the standard feature mask.
3573	*/
3574	case CPUMCPUIDFEATURE_HVP:
3575	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3576	if (pLeaf)
3577	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
3578	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
3579	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
3580	break;
3581
3582	/*
3583	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
3584	* on Intel CPUs, and different on AMDs.
3585	*/
3586	case CPUMCPUIDFEATURE_SPEC_CTRL:
3587	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3588	{
3589	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
3590	if ( !pLeaf
3591	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
3592	{
3593	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
3594	return;
3595	}
3596
3597	/* The feature can be enabled. Let's see what we can actually do. */
3598	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
3599
3600	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
3601	if (pVM->cpum.s.HostFeatures.fIbrs)
3602	{
3603	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
3604	pVM->cpum.s.GuestFeatures.fIbrs = 1;
3605	if (pVM->cpum.s.HostFeatures.fStibp)
3606	{
3607	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
3608	pVM->cpum.s.GuestFeatures.fStibp = 1;
3609	}
3610
3611	/* Make sure we have the speculation control MSR... */
3612	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
3613	if (!pMsrRange)
3614	{
3615	static CPUMMSRRANGE const s_SpecCtrl =
3616	{
3617	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
3618	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
3619	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3620	/.szName = / "IA32_SPEC_CTRL"
3621	};
3622	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
3623	AssertLogRelRC(rc);
3624	}
3625
3626	/* ... and the predictor command MSR. */
3627	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
3628	if (!pMsrRange)
3629	{
3630	/** @todo incorrect fWrGpMask. */
3631	static CPUMMSRRANGE const s_SpecCtrl =
3632	{
3633	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
3634	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
3635	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3636	/.szName = / "IA32_PRED_CMD"
3637	};
3638	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
3639	AssertLogRelRC(rc);
3640	}
3641
3642	}
3643
3644	if (pVM->cpum.s.HostFeatures.fArchCap)
3645	{
3646	/* Install the architectural capabilities MSR. */
3647	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
3648	if (!pMsrRange)
3649	{
3650	static CPUMMSRRANGE const s_ArchCaps =
3651	{
3652	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
3653	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
3654	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
3655	/.szName = / "IA32_ARCH_CAPABILITIES"
3656	};
3657	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
3658	AssertLogRelRC(rc);
3659	}
3660
3661	/* Advertise IBRS_ALL if present at this point... */
3662	if (pVM->cpum.s.HostFeatures.fArchCap & MSR_IA32_ARCH_CAP_F_IBRS_ALL)
3663	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps \|= MSR_IA32_ARCH_CAP_F_IBRS_ALL);
3664	}
3665
3666	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
3667	}
3668	else if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3669	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3670	{
3671	/* The precise details of AMD's implementation are not yet clear. */
3672	}
3673	break;
3674
3675	default:
3676	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
3677	break;
3678	}
3679
3680	/** @todo can probably kill this as this API is now init time only... */
3681	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3682	{
3683	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3684	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
3685	}
3686
3687	#undef GET_8000_0001_CHECK_X86_HOST_FEATURE_RET
3688	#undef CHECK_X86_HOST_FEATURE_RET
3689	}
3690
3691
3692	/**
3693	* Queries a CPUID feature bit.
3694	*
3695	* @returns boolean for feature presence
3696	* @param pVM The cross context VM structure.
3697	* @param enmFeature The feature to query.
3698	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
3699	*/
3700	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
3701	{
3702	switch (enmFeature)
3703	{
3704	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
3705	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
3706	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
3707	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
3708	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
3709	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
3710	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
3711	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
3712	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
3713	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
3714	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
3715	case CPUMCPUIDFEATURE_INVALID:
3716	case CPUMCPUIDFEATURE_32BIT_HACK:
3717	break;
3718	}
3719	AssertFailed();
3720	return false;
3721	}
3722
3723
3724	/**
3725	* Clears a CPUID feature bit.
3726	*
3727	* @param pVM The cross context VM structure.
3728	* @param enmFeature The feature to clear.
3729	*
3730	* @deprecated Probably better to default the feature to disabled and only allow
3731	* setting (enabling) it during construction.
3732	*/
3733	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
3734	{
3735	PCPUMCPUIDLEAF pLeaf;
3736	switch (enmFeature)
3737	{
3738	case CPUMCPUIDFEATURE_APIC:
3739	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
3740	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3741	if (pLeaf)
3742	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
3743
3744	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3745	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
3746	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
3747
3748	pVM->cpum.s.GuestFeatures.fApic = 0;
3749	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
3750	break;
3751
3752	case CPUMCPUIDFEATURE_X2APIC:
3753	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
3754	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3755	if (pLeaf)
3756	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
3757	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
3758	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
3759	break;
3760
3761	#if 0
3762	case CPUMCPUIDFEATURE_PAE:
3763	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3764	if (pLeaf)
3765	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
3766
3767	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3768	if ( pLeaf
3769	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3770	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3771	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
3772
3773	pVM->cpum.s.GuestFeatures.fPae = 0;
3774	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
3775	break;
3776
3777	case CPUMCPUIDFEATURE_LONG_MODE:
3778	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3779	if (pLeaf)
3780	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
3781	pVM->cpum.s.GuestFeatures.fLongMode = 0;
3782	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = 32;
3783	if (pVM->cpum.s.GuestFeatures.fVmx)
3784	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3785	{
3786	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3787	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic \|= VMX_BASIC_PHYSADDR_WIDTH_32BIT;
3788	}
3789	break;
3790
3791	case CPUMCPUIDFEATURE_LAHF:
3792	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3793	if (pLeaf)
3794	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
3795	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
3796	break;
3797	#endif
3798	case CPUMCPUIDFEATURE_RDTSCP:
3799	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3800	if (pLeaf)
3801	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
3802	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
3803	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
3804	break;
3805
3806	#if 0
3807	case CPUMCPUIDFEATURE_HVP:
3808	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3809	if (pLeaf)
3810	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
3811	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
3812	break;
3813
3814	case CPUMCPUIDFEATURE_SPEC_CTRL:
3815	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
3816	if (pLeaf)
3817	pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP);
3818	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL);
3819	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
3820	break;
3821	#endif
3822	default:
3823	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
3824	break;
3825	}
3826
3827	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3828	{
3829	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3830	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
3831	}
3832	}
3833
3834
3835	/**
3836	* Do some final polishing after all calls to CPUMR3SetGuestCpuIdFeature and
3837	* CPUMR3ClearGuestCpuIdFeature are (probably) done.
3838	*
3839	* @param pVM The cross context VM structure.
3840	*/
3841	void cpumR3CpuIdRing3InitDone(PVM pVM)
3842	{
3843	/*
3844	* Do not advertise NX w/o PAE, seems to confuse windows 7 (black screen very
3845	* early in real mode).
3846	*/
3847	PCPUMCPUIDLEAF pStdLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3848	PCPUMCPUIDLEAF pExtLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3849	if (pStdLeaf && pExtLeaf)
3850	{
3851	if ( !(pStdLeaf->uEdx & X86_CPUID_FEATURE_EDX_PAE)
3852	&& (pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX))
3853	pExtLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_NX;
3854	}
3855	}
3856
3857
3858	/*
3859	*
3860	*
3861	* Saved state related code.
3862	* Saved state related code.
3863	* Saved state related code.
3864	*
3865	*
3866	*/
3867
3868	/**
3869	* Called both in pass 0 and the final pass.
3870	*
3871	* @param pVM The cross context VM structure.
3872	* @param pSSM The saved state handle.
3873	*/
3874	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
3875	{
3876	/*
3877	* Save all the CPU ID leaves.
3878	*/
3879	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
3880	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
3881	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
3882	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
3883
3884	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
3885
3886	/*
3887	* Save a good portion of the raw CPU IDs as well as they may come in
3888	* handy when validating features for raw mode.
3889	*/
3890	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
3891	CPUMCPUID aRawStd[16];
3892	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
3893	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
3894	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
3895	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
3896
3897	CPUMCPUID aRawExt[32];
3898	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
3899	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
3900	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
3901	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
3902
3903	#else
3904	/* Two zero counts on non-x86 hosts. */
3905	SSMR3PutU32(pSSM, 0);
3906	SSMR3PutU32(pSSM, 0);
3907	#endif
3908	}
3909
3910
3911	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
3912	{
3913	uint32_t cCpuIds;
3914	int rc = SSMR3GetU32(pSSM, &cCpuIds);
3915	if (RT_SUCCESS(rc))
3916	{
3917	if (cCpuIds < 64)
3918	{
3919	for (uint32_t i = 0; i < cCpuIds; i++)
3920	{
3921	CPUMCPUID CpuId;
3922	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
3923	if (RT_FAILURE(rc))
3924	break;
3925
3926	CPUMCPUIDLEAF NewLeaf;
3927	NewLeaf.uLeaf = uBase + i;
3928	NewLeaf.uSubLeaf = 0;
3929	NewLeaf.fSubLeafMask = 0;
3930	NewLeaf.uEax = CpuId.uEax;
3931	NewLeaf.uEbx = CpuId.uEbx;
3932	NewLeaf.uEcx = CpuId.uEcx;
3933	NewLeaf.uEdx = CpuId.uEdx;
3934	NewLeaf.fFlags = 0;
3935	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
3936	}
3937	}
3938	else
3939	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3940	}
3941	if (RT_FAILURE(rc))
3942	{
3943	RTMemFree(*ppaLeaves);
3944	*ppaLeaves = NULL;
3945	*pcLeaves = 0;
3946	}
3947	return rc;
3948	}
3949
3950
3951	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
3952	{
3953	*ppaLeaves = NULL;
3954	*pcLeaves = 0;
3955
3956	int rc;
3957	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
3958	{
3959	/*
3960	* The new format. Starts by declaring the leave size and count.
3961	*/
3962	uint32_t cbLeaf;
3963	SSMR3GetU32(pSSM, &cbLeaf);
3964	uint32_t cLeaves;
3965	rc = SSMR3GetU32(pSSM, &cLeaves);
3966	if (RT_SUCCESS(rc))
3967	{
3968	if (cbLeaf == sizeof(**ppaLeaves))
3969	{
3970	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
3971	{
3972	/*
3973	* Load the leaves one by one.
3974	*
3975	* The uPrev stuff is a kludge for working around a week worth of bad saved
3976	* states during the CPUID revamp in March 2015. We saved too many leaves
3977	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
3978	* garbage entires at the end of the array when restoring. We also had
3979	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
3980	* this kludge doesn't deal correctly with that, but who cares...
3981	*/
3982	uint32_t uPrev = 0;
3983	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
3984	{
3985	CPUMCPUIDLEAF Leaf;
3986	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
3987	if (RT_SUCCESS(rc))
3988	{
3989	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
3990	\|\| Leaf.uLeaf >= uPrev)
3991	{
3992	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3993	uPrev = Leaf.uLeaf;
3994	}
3995	else
3996	uPrev = UINT32_MAX;
3997	}
3998	}
3999	}
4000	else
4001	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
4002	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
4003	}
4004	else
4005	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
4006	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
4007	}
4008	}
4009	else
4010	{
4011	/*
4012	* The old format with its three inflexible arrays.
4013	*/
4014	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
4015	if (RT_SUCCESS(rc))
4016	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
4017	if (RT_SUCCESS(rc))
4018	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
4019	if (RT_SUCCESS(rc))
4020	{
4021	/*
4022	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
4023	*/
4024	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(ppaLeaves, pcLeaves, 0, 0);
4025	if ( pLeaf
4026	&& RTX86IsIntelCpu(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
4027	{
4028	CPUMCPUIDLEAF Leaf;
4029	Leaf.uLeaf = 4;
4030	Leaf.fSubLeafMask = UINT32_MAX;
4031	Leaf.uSubLeaf = 0;
4032	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
4033	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
4034	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
4035	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
4036	\| UINT32_C(63); /* system coherency line size - 1 */
4037	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
4038	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
4039	\| (UINT32_C(1) << 5) /* cache level */
4040	\| UINT32_C(1); /* cache type (data) */
4041	Leaf.fFlags = 0;
4042	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4043	if (RT_SUCCESS(rc))
4044	{
4045	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
4046	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4047	}
4048	if (RT_SUCCESS(rc))
4049	{
4050	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
4051	Leaf.uEcx = 4095; /* sets - 1 */
4052	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
4053	Leaf.uEbx \|= UINT32_C(23) << 22;
4054	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
4055	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
4056	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
4057	Leaf.uEax \|= UINT32_C(2) << 5;
4058	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4059	}
4060	}
4061	}
4062	}
4063	return rc;
4064	}
4065
4066
4067	/**
4068	* Loads the CPU ID leaves saved by pass 0, inner worker.
4069	*
4070	* @returns VBox status code.
4071	* @param pVM The cross context VM structure.
4072	* @param pSSM The saved state handle.
4073	* @param uVersion The format version.
4074	* @param paLeaves Guest CPUID leaves loaded from the state.
4075	* @param cLeaves The number of leaves in @a paLeaves.
4076	* @param pMsrs The guest MSRs.
4077	*/
4078	static int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
4079	{
4080	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4081	#if !defined(RT_ARCH_AMD64) && !defined(RT_ARCH_X86)
4082	AssertMsgFailed(("Port me!"));
4083	#endif
4084
4085	/*
4086	* Continue loading the state into stack buffers.
4087	*/
4088	CPUMCPUID GuestDefCpuId;
4089	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
4090	AssertRCReturn(rc, rc);
4091
4092	CPUMCPUID aRawStd[16];
4093	uint32_t cRawStd;
4094	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
4095	if (cRawStd > RT_ELEMENTS(aRawStd))
4096	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4097	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
4098	AssertRCReturn(rc, rc);
4099	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
4100	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4101	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4102	#else
4103	RT_ZERO(aRawStd[i]);
4104	#endif
4105
4106	CPUMCPUID aRawExt[32];
4107	uint32_t cRawExt;
4108	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
4109	if (cRawExt > RT_ELEMENTS(aRawExt))
4110	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4111	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
4112	AssertRCReturn(rc, rc);
4113	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
4114	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4115	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4116	#else
4117	RT_ZERO(aRawExt[i]);
4118	#endif
4119
4120	/*
4121	* Get the raw CPU IDs for the current host.
4122	*/
4123	CPUMCPUID aHostRawStd[16];
4124	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4125	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
4126	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
4127	#else
4128	RT_ZERO(aHostRawStd);
4129	#endif
4130
4131	CPUMCPUID aHostRawExt[32];
4132	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4133	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
4134	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
4135	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
4136	#else
4137	RT_ZERO(aHostRawExt);
4138	#endif
4139
4140	/*
4141	* Get the host and guest overrides so we don't reject the state because
4142	* some feature was enabled thru these interfaces.
4143	* Note! We currently only need the feature leaves, so skip rest.
4144	*/
4145	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
4146	CPUMCPUID aHostOverrideStd[2];
4147	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
4148	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
4149
4150	CPUMCPUID aHostOverrideExt[2];
4151	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
4152	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
4153
4154	/*
4155	* This can be skipped.
4156	*/
4157	bool fStrictCpuIdChecks;
4158	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
4159
4160	/*
4161	* Define a bunch of macros for simplifying the santizing/checking code below.
4162	*/
4163	/* Generic expression + failure message. */
4164	#define CPUID_CHECK_RET(expr, fmt) \
4165	do { \
4166	if (!(expr)) \
4167	{ \
4168	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
4169	if (fStrictCpuIdChecks) \
4170	{ \
4171	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
4172	RTStrFree(pszMsg); \
4173	return rcCpuid; \
4174	} \
4175	LogRel(("CPUM: %s\n", pszMsg)); \
4176	RTStrFree(pszMsg); \
4177	} \
4178	} while (0)
4179	#define CPUID_CHECK_WRN(expr, fmt) \
4180	do { \
4181	if (!(expr)) \
4182	LogRel(fmt); \
4183	} while (0)
4184
4185	/* For comparing two values and bitch if they differs. */
4186	#define CPUID_CHECK2_RET(what, host, saved) \
4187	do { \
4188	if ((host) != (saved)) \
4189	{ \
4190	if (fStrictCpuIdChecks) \
4191	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4192	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
4193	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4194	} \
4195	} while (0)
4196	#define CPUID_CHECK2_WRN(what, host, saved) \
4197	do { \
4198	if ((host) != (saved)) \
4199	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4200	} while (0)
4201
4202	/* For checking raw cpu features (raw mode). */
4203	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
4204	do { \
4205	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4206	{ \
4207	if (fStrictCpuIdChecks) \
4208	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4209	N_(#bit " mismatch: host=%d saved=%d"), \
4210	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
4211	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4212	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4213	} \
4214	} while (0)
4215	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
4216	do { \
4217	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4218	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4219	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4220	} while (0)
4221	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
4222
4223	/* For checking guest features. */
4224	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
4225	do { \
4226	if ( (aGuestCpuId##set [1].reg & bit) \
4227	&& !(aHostRaw##set [1].reg & bit) \
4228	&& !(aHostOverride##set [1].reg & bit) \
4229	) \
4230	{ \
4231	if (fStrictCpuIdChecks) \
4232	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4233	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4234	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4235	} \
4236	} while (0)
4237	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
4238	do { \
4239	if ( (aGuestCpuId##set [1].reg & bit) \
4240	&& !(aHostRaw##set [1].reg & bit) \
4241	&& !(aHostOverride##set [1].reg & bit) \
4242	) \
4243	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4244	} while (0)
4245	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
4246	do { \
4247	if ( (aGuestCpuId##set [1].reg & bit) \
4248	&& !(aHostRaw##set [1].reg & bit) \
4249	&& !(aHostOverride##set [1].reg & bit) \
4250	) \
4251	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4252	} while (0)
4253	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
4254
4255	/* For checking guest features if AMD guest CPU. */
4256	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
4257	do { \
4258	if ( (aGuestCpuId##set [1].reg & bit) \
4259	&& fGuestAmd \
4260	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4261	&& !(aHostOverride##set [1].reg & bit) \
4262	) \
4263	{ \
4264	if (fStrictCpuIdChecks) \
4265	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4266	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4267	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4268	} \
4269	} while (0)
4270	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
4271	do { \
4272	if ( (aGuestCpuId##set [1].reg & bit) \
4273	&& fGuestAmd \
4274	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4275	&& !(aHostOverride##set [1].reg & bit) \
4276	) \
4277	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4278	} while (0)
4279	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
4280	do { \
4281	if ( (aGuestCpuId##set [1].reg & bit) \
4282	&& fGuestAmd \
4283	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4284	&& !(aHostOverride##set [1].reg & bit) \
4285	) \
4286	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4287	} while (0)
4288	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
4289
4290	/* For checking AMD features which have a corresponding bit in the standard
4291	range. (Intel defines very few bits in the extended feature sets.) */
4292	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
4293	do { \
4294	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4295	&& !(fHostAmd \
4296	? aHostRawExt[1].reg & (ExtBit) \
4297	: aHostRawStd[1].reg & (StdBit)) \
4298	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4299	) \
4300	{ \
4301	if (fStrictCpuIdChecks) \
4302	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4303	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
4304	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4305	} \
4306	} while (0)
4307	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
4308	do { \
4309	if ( (aGuestCpuId[1].reg & (ExtBit)) \
4310	&& !(fHostAmd \
4311	? aHostRawExt[1].reg & (ExtBit) \
4312	: aHostRawStd[1].reg & (StdBit)) \
4313	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4314	) \
4315	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4316	} while (0)
4317	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
4318	do { \
4319	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4320	&& !(fHostAmd \
4321	? aHostRawExt[1].reg & (ExtBit) \
4322	: aHostRawStd[1].reg & (StdBit)) \
4323	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4324	) \
4325	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4326	} while (0)
4327	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
4328
4329
4330	/*
4331	* Verify that we can support the features already exposed to the guest on
4332	* this host.
4333	*
4334	* Most of the features we're emulating requires intercepting instruction
4335	* and doing it the slow way, so there is no need to warn when they aren't
4336	* present in the host CPU. Thus we use IGN instead of EMU on these.
4337	*
4338	* Trailing comments:
4339	* "EMU" - Possible to emulate, could be lots of work and very slow.
4340	* "EMU?" - Can this be emulated?
4341	*/
4342	CPUMCPUID aGuestCpuIdStd[2];
4343	RT_ZERO(aGuestCpuIdStd);
4344	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
4345
4346	/* CPUID(1).ecx */
4347	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
4348	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
4349	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
4350	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4351	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
4352	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
4353	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
4354	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
4355	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
4356	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
4357	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
4358	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
4359	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
4360	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
4361	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
4362	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
4363	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
4364	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4365	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
4366	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
4367	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
4368	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4369	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
4370	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
4371	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4372	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
4373	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
4374	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
4375	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
4376	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4377	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4378	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
4379
4380	/* CPUID(1).edx */
4381	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4382	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4383	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
4384	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4385	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4386	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4387	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4388	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4389	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4390	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4391	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
4392	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4393	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4394	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4395	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4396	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4397	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4398	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4399	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4400	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
4401	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
4402	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
4403	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
4404	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4405	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4406	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
4407	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
4408	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
4409	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
4410	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
4411	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
4412	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
4413
4414	/* CPUID(0x80000000). */
4415	CPUMCPUID aGuestCpuIdExt[2];
4416	RT_ZERO(aGuestCpuIdExt);
4417	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
4418	{
4419	/** @todo deal with no 0x80000001 on the host. */
4420	bool const fHostAmd = RTX86IsAmdCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx)
4421	\|\| RTX86IsHygonCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
4422	bool const fGuestAmd = RTX86IsAmdCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx)
4423	\|\| RTX86IsHygonCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
4424
4425	/* CPUID(0x80000001).ecx */
4426	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
4427	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
4428	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
4429	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
4430	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
4431	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
4432	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
4433	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
4434	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
4435	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
4436	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
4437	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
4438	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
4439	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
4440	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4441	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4442	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4443	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4444	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4445	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4446	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4447	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4448	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4449	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4450	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4451	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4452	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4453	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4454	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4455	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4456	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4457	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4458
4459	/* CPUID(0x80000001).edx */
4460	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
4461	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
4462	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
4463	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
4464	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4465	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4466	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
4467	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
4468	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4469	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
4470	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
4471	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
4472	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
4473	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
4474	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
4475	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4476	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
4477	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
4478	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
4479	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
4480	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4481	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
4482	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4483	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4484	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4485	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4486	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4487	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4488	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
4489	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4490	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4491	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4492	}
4493
4494	/** @todo check leaf 7 */
4495
4496	/* CPUID(d) - XCR0 stuff - takes ECX as input.
4497	* ECX=0: EAX - Valid bits in XCR0[31:0].
4498	* EBX - Maximum state size as per current XCR0 value.
4499	* ECX - Maximum state size for all supported features.
4500	* EDX - Valid bits in XCR0[63:32].
4501	* ECX=1: EAX - Various X-features.
4502	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
4503	* ECX - Valid bits in IA32_XSS[31:0].
4504	* EDX - Valid bits in IA32_XSS[63:32].
4505	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
4506	* if the bit invalid all four registers are set to zero.
4507	* EAX - The state size for this feature.
4508	* EBX - The state byte offset of this feature.
4509	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
4510	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
4511	*/
4512	uint64_t fGuestXcr0Mask = 0;
4513	PCPUMCPUIDLEAF pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
4514	if ( pCurLeaf
4515	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
4516	&& ( pCurLeaf->uEax
4517	\|\| pCurLeaf->uEbx
4518	\|\| pCurLeaf->uEcx
4519	\|\| pCurLeaf->uEdx) )
4520	{
4521	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
4522	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
4523	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4524	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
4525	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
4526	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
4527	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4528	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
4529
4530	/* We don't support any additional features yet. */
4531	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
4532	if (pCurLeaf && pCurLeaf->uEax)
4533	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4534	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
4535	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
4536	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4537	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
4538	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
4539
4540
4541	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4542	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
4543	{
4544	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4545	if (pCurLeaf)
4546	{
4547	/* If advertised, the state component offset and size must match the one used by host. */
4548	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
4549	{
4550	CPUMCPUID RawHost;
4551	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
4552	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
4553	if ( RawHost.uEbx != pCurLeaf->uEbx
4554	\|\| RawHost.uEax != pCurLeaf->uEax)
4555	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4556	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
4557	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
4558	}
4559	}
4560	}
4561	#endif
4562	}
4563	/* Clear leaf 0xd just in case we're loading an old state... */
4564	else if (pCurLeaf)
4565	{
4566	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
4567	{
4568	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4569	if (pCurLeaf)
4570	{
4571	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
4572	\|\| ( pCurLeaf->uEax == 0
4573	&& pCurLeaf->uEbx == 0
4574	&& pCurLeaf->uEcx == 0
4575	&& pCurLeaf->uEdx == 0),
4576	("uVersion=%#x; %#x %#x %#x %#x\n",
4577	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
4578	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
4579	}
4580	}
4581	}
4582
4583	/* Update the fXStateGuestMask value for the VM. */
4584	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
4585	{
4586	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
4587	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
4588	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
4589	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4590	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
4591	}
4592
4593	#undef CPUID_CHECK_RET
4594	#undef CPUID_CHECK_WRN
4595	#undef CPUID_CHECK2_RET
4596	#undef CPUID_CHECK2_WRN
4597	#undef CPUID_RAW_FEATURE_RET
4598	#undef CPUID_RAW_FEATURE_WRN
4599	#undef CPUID_RAW_FEATURE_IGN
4600	#undef CPUID_GST_FEATURE_RET
4601	#undef CPUID_GST_FEATURE_WRN
4602	#undef CPUID_GST_FEATURE_EMU
4603	#undef CPUID_GST_FEATURE_IGN
4604	#undef CPUID_GST_FEATURE2_RET
4605	#undef CPUID_GST_FEATURE2_WRN
4606	#undef CPUID_GST_FEATURE2_EMU
4607	#undef CPUID_GST_FEATURE2_IGN
4608	#undef CPUID_GST_AMD_FEATURE_RET
4609	#undef CPUID_GST_AMD_FEATURE_WRN
4610	#undef CPUID_GST_AMD_FEATURE_EMU
4611	#undef CPUID_GST_AMD_FEATURE_IGN
4612
4613	/*
4614	* We're good, commit the CPU ID leaves.
4615	*/
4616	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
4617	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
4618	AssertLogRelRCReturn(rc, rc);
4619
4620	return VINF_SUCCESS;
4621	}
4622
4623
4624	/**
4625	* Loads the CPU ID leaves saved by pass 0.
4626	*
4627	* @returns VBox status code.
4628	* @param pVM The cross context VM structure.
4629	* @param pSSM The saved state handle.
4630	* @param uVersion The format version.
4631	* @param pMsrs The guest MSRs.
4632	*/
4633	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
4634	{
4635	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4636
4637	/*
4638	* Load the CPUID leaves array first and call worker to do the rest, just so
4639	* we can free the memory when we need to without ending up in column 1000.
4640	*/
4641	PCPUMCPUIDLEAF paLeaves;
4642	uint32_t cLeaves;
4643	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
4644	AssertRC(rc);
4645	if (RT_SUCCESS(rc))
4646	{
4647	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
4648	RTMemFree(paLeaves);
4649	}
4650	return rc;
4651	}
4652
4653
4654
4655	/**
4656	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
4657	*
4658	* @returns VBox status code.
4659	* @param pVM The cross context VM structure.
4660	* @param pSSM The saved state handle.
4661	* @param uVersion The format version.
4662	*/
4663	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
4664	{
4665	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4666
4667	/*
4668	* Restore the CPUID leaves.
4669	*
4670	* Note that we support restoring less than the current amount of standard
4671	* leaves because we've been allowed more is newer version of VBox.
4672	*/
4673	uint32_t cElements;
4674	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
4675	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
4676	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4677	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
4678
4679	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
4680	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
4681	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4682	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
4683
4684	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
4685	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
4686	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4687	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
4688
4689	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4690
4691	/*
4692	* Check that the basic cpuid id information is unchanged.
4693	*/
4694	/** @todo we should check the 64 bits capabilities too! */
4695	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
4696	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4697	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
4698	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
4699	#endif
4700	uint32_t au32CpuIdSaved[8];
4701	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
4702	if (RT_SUCCESS(rc))
4703	{
4704	/* Ignore CPU stepping. */
4705	au32CpuId[4] &= 0xfffffff0;
4706	au32CpuIdSaved[4] &= 0xfffffff0;
4707
4708	/* Ignore APIC ID (AMD specs). */
4709	au32CpuId[5] &= ~0xff000000;
4710	au32CpuIdSaved[5] &= ~0xff000000;
4711
4712	/* Ignore the number of Logical CPUs (AMD specs). */
4713	au32CpuId[5] &= ~0x00ff0000;
4714	au32CpuIdSaved[5] &= ~0x00ff0000;
4715
4716	/* Ignore some advanced capability bits, that we don't expose to the guest. */
4717	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
4718	\| X86_CPUID_FEATURE_ECX_VMX
4719	\| X86_CPUID_FEATURE_ECX_SMX
4720	\| X86_CPUID_FEATURE_ECX_EST
4721	\| X86_CPUID_FEATURE_ECX_TM2
4722	\| X86_CPUID_FEATURE_ECX_CNTXID
4723	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
4724	\| X86_CPUID_FEATURE_ECX_PDCM
4725	\| X86_CPUID_FEATURE_ECX_DCA
4726	\| X86_CPUID_FEATURE_ECX_X2APIC
4727	);
4728	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
4729	\| X86_CPUID_FEATURE_ECX_VMX
4730	\| X86_CPUID_FEATURE_ECX_SMX
4731	\| X86_CPUID_FEATURE_ECX_EST
4732	\| X86_CPUID_FEATURE_ECX_TM2
4733	\| X86_CPUID_FEATURE_ECX_CNTXID
4734	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
4735	\| X86_CPUID_FEATURE_ECX_PDCM
4736	\| X86_CPUID_FEATURE_ECX_DCA
4737	\| X86_CPUID_FEATURE_ECX_X2APIC
4738	);
4739
4740	/* Make sure we don't forget to update the masks when enabling
4741	* features in the future.
4742	*/
4743	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
4744	( X86_CPUID_FEATURE_ECX_DTES64
4745	\| X86_CPUID_FEATURE_ECX_VMX
4746	\| X86_CPUID_FEATURE_ECX_SMX
4747	\| X86_CPUID_FEATURE_ECX_EST
4748	\| X86_CPUID_FEATURE_ECX_TM2
4749	\| X86_CPUID_FEATURE_ECX_CNTXID
4750	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
4751	\| X86_CPUID_FEATURE_ECX_PDCM
4752	\| X86_CPUID_FEATURE_ECX_DCA
4753	\| X86_CPUID_FEATURE_ECX_X2APIC
4754	)));
4755	/* do the compare */
4756	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
4757	{
4758	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
4759	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
4760	"Saved=%.*Rhxs\n"
4761	"Real =%.*Rhxs\n",
4762	sizeof(au32CpuIdSaved), au32CpuIdSaved,
4763	sizeof(au32CpuId), au32CpuId));
4764	else
4765	{
4766	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
4767	"Saved=%.*Rhxs\n"
4768	"Real =%.*Rhxs\n",
4769	sizeof(au32CpuIdSaved), au32CpuIdSaved,
4770	sizeof(au32CpuId), au32CpuId));
4771	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
4772	}
4773	}
4774	}
4775
4776	return rc;
4777	}
4778
4779
4780
4781	/*
4782	*
4783	*
4784	* CPUID Info Handler.
4785	* CPUID Info Handler.
4786	* CPUID Info Handler.
4787	*
4788	*
4789	*/
4790
4791
4792
4793	/**
4794	* Get L1 cache / TLS associativity.
4795	*/
4796	static const char getCacheAss(unsigned u, char pszBuf)
4797	{
4798	if (u == 0)
4799	return "res0 ";
4800	if (u == 1)
4801	return "direct";
4802	if (u == 255)
4803	return "fully";
4804	if (u >= 256)
4805	return "???";
4806
4807	RTStrPrintf(pszBuf, 16, "%d way", u);
4808	return pszBuf;
4809	}
4810
4811
4812	/**
4813	* Get L2/L3 cache associativity.
4814	*/
4815	static const char *getL23CacheAss(unsigned u)
4816	{
4817	switch (u)
4818	{
4819	case 0: return "off ";
4820	case 1: return "direct";
4821	case 2: return "2 way ";
4822	case 3: return "3 way ";
4823	case 4: return "4 way ";
4824	case 5: return "6 way ";
4825	case 6: return "8 way ";
4826	case 7: return "res7 ";
4827	case 8: return "16 way";
4828	case 9: return "tpoext"; /* Overridden by Fn8000_001D */
4829	case 10: return "32 way";
4830	case 11: return "48 way";
4831	case 12: return "64 way";
4832	case 13: return "96 way";
4833	case 14: return "128way";
4834	case 15: return "fully ";
4835	default: return "????";
4836	}
4837	}
4838
4839
4840	/** CPUID(1).EDX field descriptions. */
4841	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
4842	{
4843	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
4844	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
4845	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
4846	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
4847	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
4848	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
4849	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
4850	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
4851	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
4852	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
4853	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
4854	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
4855	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
4856	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
4857	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
4858	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
4859	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
4860	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
4861	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
4862	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
4863	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
4864	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
4865	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
4866	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
4867	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
4868	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
4869	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
4870	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
4871	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
4872	DBGFREGSUBFIELD_TERMINATOR()
4873	};
4874
4875	/** CPUID(1).ECX field descriptions. */
4876	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
4877	{
4878	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
4879	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
4880	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
4881	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
4882	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
4883	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
4884	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
4885	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
4886	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
4887	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
4888	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
4889	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
4890	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
4891	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
4892	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
4893	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
4894	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
4895	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
4896	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
4897	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
4898	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
4899	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
4900	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
4901	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
4902	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
4903	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
4904	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
4905	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
4906	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
4907	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
4908	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
4909	DBGFREGSUBFIELD_TERMINATOR()
4910	};
4911
4912	/** CPUID(7,0).EBX field descriptions. */
4913	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
4914	{
4915	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
4916	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
4917	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
4918	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
4919	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
4920	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
4921	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
4922	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
4923	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
4924	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
4925	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
4926	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
4927	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
4928	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
4929	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
4930	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
4931	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
4932	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
4933	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
4934	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
4935	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
4936	DBGFREGSUBFIELD_RO("CLWB\0" "CLWB instruction", 24, 1, 0),
4937	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
4938	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
4939	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
4940	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
4941	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
4942	DBGFREGSUBFIELD_TERMINATOR()
4943	};
4944
4945	/** CPUID(7,0).ECX field descriptions. */
4946	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
4947	{
4948	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
4949	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
4950	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
4951	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
4952	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
4953	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
4954	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
4955	DBGFREGSUBFIELD_TERMINATOR()
4956	};
4957
4958	/** CPUID(7,0).EDX field descriptions. */
4959	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
4960	{
4961	DBGFREGSUBFIELD_RO("MD_CLEAR\0" "Supports MDS related buffer clearing", 10, 1, 0),
4962	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
4963	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
4964	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
4965	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
4966	DBGFREGSUBFIELD_RO("CORECAP\0" "Supports IA32_CORE_CAP", 30, 1, 0),
4967	DBGFREGSUBFIELD_RO("SSBD\0" "Supports IA32_SPEC_CTRL.SSBD", 31, 1, 0),
4968	DBGFREGSUBFIELD_TERMINATOR()
4969	};
4970
4971
4972	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
4973	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
4974	{
4975	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
4976	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
4977	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
4978	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
4979	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
4980	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
4981	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
4982	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
4983	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
4984	DBGFREGSUBFIELD_TERMINATOR()
4985	};
4986
4987	/** CPUID(13,1).EAX field descriptions. */
4988	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
4989	{
4990	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
4991	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
4992	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
4993	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
4994	DBGFREGSUBFIELD_TERMINATOR()
4995	};
4996
4997
4998	/** CPUID(0x80000001,0).EDX field descriptions. */
4999	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
5000	{
5001	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5002	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5003	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5004	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5005	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5006	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
5007	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5008	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5009	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5010	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5011	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
5012	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5013	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5014	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5015	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5016	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5017	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5018	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
5019	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
5020	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5021	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
5022	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
5023	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
5024	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
5025	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
5026	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
5027	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
5028	DBGFREGSUBFIELD_TERMINATOR()
5029	};
5030
5031	/** CPUID(0x80000001,0).ECX field descriptions. */
5032	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
5033	{
5034	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
5035	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
5036	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
5037	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
5038	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
5039	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
5040	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
5041	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
5042	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
5043	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
5044	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
5045	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
5046	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
5047	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
5048	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
5049	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
5050	DBGFREGSUBFIELD_RO("TCE\0" "Translation Cache Extension support", 17, 1, 0),
5051	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
5052	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
5053	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
5054	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
5055	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
5056	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
5057	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
5058	DBGFREGSUBFIELD_RO("PCX_L2I\0" "L2I/L3 Performance Counter Extensions", 28, 1, 0),
5059	DBGFREGSUBFIELD_RO("MONITORX\0" "MWAITX and MONITORX instructions", 29, 1, 0),
5060	DBGFREGSUBFIELD_RO("AddrMaskExt\0" "BP Addressing masking extended to bit 31", 30, 1, 0),
5061	DBGFREGSUBFIELD_TERMINATOR()
5062	};
5063
5064	/** CPUID(0x8000000a,0).EDX field descriptions. */
5065	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
5066	{
5067	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
5068	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
5069	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
5070	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
5071	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
5072	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
5073	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
5074	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
5075	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
5076	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
5077	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
5078	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
5079	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
5080	DBGFREGSUBFIELD_RO("GMET\0" "Guest Mode Execute Trap Extension", 17, 1, 0),
5081	DBGFREGSUBFIELD_RO("x2AVIC\0" "AVIC support for x2APIC mode", 18, 1, 0),
5082	DBGFREGSUBFIELD_RO("SSSCheck\0" "SVM supervisor shadow stack restrictions", 19, 1, 0),
5083	DBGFREGSUBFIELD_RO("SpecCtrl\0" "SPEC_CTRL virtualization", 20, 1, 0),
5084	DBGFREGSUBFIELD_RO("ROGPT\0" "Read-Only Guest Page Table feature support", 21, 1, 0),
5085	DBGFREGSUBFIELD_RO("HOST_MCE_OVERRIDE\0" "Guest #MC can be intercepted", 23, 1, 0),
5086	DBGFREGSUBFIELD_RO("TlbiCtl\0" "INVLPGB/TLBSYNC enable and intercept", 24, 1, 0),
5087	DBGFREGSUBFIELD_RO("VNMI\0" "NMI Virtualization", 25, 1, 0),
5088	DBGFREGSUBFIELD_RO("IbsVirt\0" "IBS Virtualization", 26, 1, 0),
5089	DBGFREGSUBFIELD_RO("ExtLvtAvicAccessChg\0" "Extended LVT AVIC access changes", 27, 1, 0),
5090	DBGFREGSUBFIELD_RO("NestedVirtVmcbAddrChk\0""Guest VMCB address check", 28, 1, 0),
5091	DBGFREGSUBFIELD_RO("BusLockThreshold\0" "Bus Lock Threshold", 29, 1, 0),
5092	DBGFREGSUBFIELD_TERMINATOR()
5093	};
5094
5095
5096	/** CPUID(0x80000007,0).EDX field descriptions. */
5097	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
5098	{
5099	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
5100	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
5101	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
5102	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
5103	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
5104	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
5105	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
5106	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
5107	DBGFREGSUBFIELD_RO("CPB\0" "Core Performance Boost", 9, 1, 0),
5108	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
5109	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
5110	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
5111	DBGFREGSUBFIELD_RO("ConnectedStandby\0" "Connected Standby", 13, 1, 0),
5112	DBGFREGSUBFIELD_RO("RAPL\0" "Running average power limit", 14, 1, 0),
5113	DBGFREGSUBFIELD_TERMINATOR()
5114	};
5115
5116	/** CPUID(0x80000008,0).EBX field descriptions. */
5117	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
5118	{
5119	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
5120	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
5121	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR)", 2, 1, 0),
5122	DBGFREGSUBFIELD_RO("INVLPGB\0" "INVLPGB and TLBSYNC instructions", 3, 1, 0),
5123	DBGFREGSUBFIELD_RO("RDPRU\0" "RDPRU instruction", 4, 1, 0),
5124	DBGFREGSUBFIELD_RO("BE\0" "Bandwidth Enforcement extension", 6, 1, 0),
5125	DBGFREGSUBFIELD_RO("MCOMMIT\0" "MCOMMIT instruction", 8, 1, 0),
5126	DBGFREGSUBFIELD_RO("WBNOINVD\0" "WBNOINVD instruction", 9, 1, 0),
5127	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
5128	DBGFREGSUBFIELD_RO("INT_WBINVD\0" "WBINVD/WBNOINVD interruptible", 13, 1, 0),
5129	DBGFREGSUBFIELD_RO("IBRS\0" "Indirect Branch Restricted Speculation", 14, 1, 0),
5130	DBGFREGSUBFIELD_RO("STIBP\0" "Single Thread Indirect Branch Prediction", 15, 1, 0),
5131	DBGFREGSUBFIELD_RO("IbrsAlwaysOn\0" "Processor prefers that IBRS be left on", 16, 1, 0),
5132	DBGFREGSUBFIELD_RO("StibpAlwaysOn\0""Processor prefers that STIBP be left on", 17, 1, 0),
5133	DBGFREGSUBFIELD_RO("IbrsPreferred\0""IBRS preferred over software solution", 18, 1, 0),
5134	DBGFREGSUBFIELD_RO("IbrsSameMode\0" "IBRS limits same mode speculation", 19, 1, 0),
5135	DBGFREGSUBFIELD_RO("EferLmsleUnsupported\0" "EFER.LMSLE is unsupported", 20, 1, 0),
5136	DBGFREGSUBFIELD_RO("INVLPGBnestedPages\0" "INVLPGB for nested translation", 21, 1, 0),
5137	DBGFREGSUBFIELD_RO("SSBD\0" "Speculative Store Bypass Disable", 24, 1, 0),
5138	DBGFREGSUBFIELD_RO("SsbdVirtSpecCtrl\0" "Use VIRT_SPEC_CTL for SSBD", 25, 1, 0),
5139	DBGFREGSUBFIELD_RO("SsbdNotRequired\0" "SSBD not needed on this processor", 26, 1, 0),
5140	DBGFREGSUBFIELD_RO("CPPC\0" "Collaborative Processor Performance Control", 27, 1, 0),
5141	DBGFREGSUBFIELD_RO("PSFD\0" "Predictive Store Forward Disable", 28, 1, 0),
5142	DBGFREGSUBFIELD_RO("BTC_NO\0" "Unaffected by branch type confusion", 29, 1, 0),
5143	DBGFREGSUBFIELD_RO("IBPB_RET\0" "Clears RA predictor when PRED_CMD.IBPB set", 30, 1, 0),
5144	DBGFREGSUBFIELD_TERMINATOR()
5145	};
5146
5147
5148	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
5149	const char *pszLeadIn, uint32_t cchWidth)
5150	{
5151	if (pszLeadIn)
5152	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5153
5154	for (uint32_t iBit = 0; iBit < 32; iBit++)
5155	if (RT_BIT_32(iBit) & uVal)
5156	{
5157	while ( pDesc->pszName != NULL
5158	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5159	pDesc++;
5160	if ( pDesc->pszName != NULL
5161	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5162	{
5163	if (pDesc->cBits == 1)
5164	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5165	else
5166	{
5167	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
5168	if (pDesc->cBits < 32)
5169	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5170	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
5171	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5172	}
5173	}
5174	else
5175	pHlp->pfnPrintf(pHlp, " %u", iBit);
5176	}
5177	if (pszLeadIn)
5178	pHlp->pfnPrintf(pHlp, "\n");
5179	}
5180
5181
5182	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5183	const char *pszLeadIn, uint32_t cchWidth)
5184	{
5185	if (pszLeadIn)
5186	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5187
5188	for (uint32_t iBit = 0; iBit < 64; iBit++)
5189	if (RT_BIT_64(iBit) & uVal)
5190	{
5191	while ( pDesc->pszName != NULL
5192	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5193	pDesc++;
5194	if ( pDesc->pszName != NULL
5195	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5196	{
5197	if (pDesc->cBits == 1)
5198	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5199	else
5200	{
5201	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
5202	if (pDesc->cBits < 64)
5203	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
5204	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
5205	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5206	}
5207	}
5208	else
5209	pHlp->pfnPrintf(pHlp, " %u", iBit);
5210	}
5211	if (pszLeadIn)
5212	pHlp->pfnPrintf(pHlp, "\n");
5213	}
5214
5215
5216	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5217	const char *pszLeadIn, uint32_t cchWidth)
5218	{
5219	if (!uVal)
5220	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5221	else
5222	{
5223	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5224	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
5225	pHlp->pfnPrintf(pHlp, " )\n");
5226	}
5227	}
5228
5229
5230	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
5231	uint32_t cchWidth)
5232	{
5233	uint32_t uCombined = uVal1 \| uVal2;
5234	for (uint32_t iBit = 0; iBit < 32; iBit++)
5235	if ( (RT_BIT_32(iBit) & uCombined)
5236	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
5237	{
5238	while ( pDesc->pszName != NULL
5239	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5240	pDesc++;
5241
5242	if ( pDesc->pszName != NULL
5243	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5244	{
5245	size_t cchMnemonic = strlen(pDesc->pszName);
5246	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
5247	size_t cchDesc = strlen(pszDesc);
5248	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
5249	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
5250	if (pDesc->cBits < 32)
5251	{
5252	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5253	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5254	}
5255
5256	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
5257	pDesc->pszName, pszDesc,
5258	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
5259	uFieldValue1, uFieldValue2);
5260
5261	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
5262	pDesc++;
5263	}
5264	else
5265	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
5266	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
5267	}
5268	}
5269
5270
5271	/**
5272	* Produces a detailed summary of standard leaf 0x00000001.
5273	*
5274	* @param pHlp The info helper functions.
5275	* @param pCurLeaf The 0x00000001 leaf.
5276	* @param fVerbose Whether to be very verbose or not.
5277	* @param fIntel Set if intel CPU.
5278	*/
5279	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
5280	{
5281	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
5282	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
5283	uint32_t uEAX = pCurLeaf->uEax;
5284	uint32_t uEBX = pCurLeaf->uEbx;
5285
5286	pHlp->pfnPrintf(pHlp,
5287	"%36s %2d \tExtended: %d \tEffective: %d\n"
5288	"%36s %2d \tExtended: %d \tEffective: %d\n"
5289	"%36s %d\n"
5290	"%36s %d (%s)\n"
5291	"%36s %#04x\n"
5292	"%36s %d\n"
5293	"%36s %d\n"
5294	"%36s %#04x\n"
5295	,
5296	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
5297	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
5298	"Stepping:", RTX86GetCpuStepping(uEAX),
5299	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
5300	"APIC ID:", (uEBX >> 24) & 0xff,
5301	"Logical CPUs:",(uEBX >> 16) & 0xff,
5302	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
5303	"Brand ID:", (uEBX >> 0) & 0xff);
5304	if (fVerbose)
5305	{
5306	CPUMCPUID Host = {0};
5307	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5308	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5309	#endif
5310	pHlp->pfnPrintf(pHlp, "Features\n");
5311	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5312	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
5313	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
5314	}
5315	else
5316	{
5317	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
5318	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
5319	}
5320	}
5321
5322
5323	/**
5324	* Produces a detailed summary of standard leaf 0x00000007.
5325	*
5326	* @param pHlp The info helper functions.
5327	* @param paLeaves The CPUID leaves array.
5328	* @param cLeaves The number of leaves in the array.
5329	* @param pCurLeaf The first 0x00000007 leaf.
5330	* @param fVerbose Whether to be very verbose or not.
5331	*/
5332	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5333	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5334	{
5335	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
5336	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
5337	for (;;)
5338	{
5339	CPUMCPUID Host = {0};
5340	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5341	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5342	#endif
5343
5344	switch (pCurLeaf->uSubLeaf)
5345	{
5346	case 0:
5347	if (fVerbose)
5348	{
5349	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5350	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
5351	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
5352	if (pCurLeaf->uEdx \|\| Host.uEdx)
5353	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
5354	}
5355	else
5356	{
5357	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
5358	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
5359	if (pCurLeaf->uEdx)
5360	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
5361	}
5362	break;
5363
5364	default:
5365	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
5366	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
5367	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
5368	break;
5369
5370	}
5371
5372	/* advance. */
5373	pCurLeaf++;
5374	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5375	\|\| pCurLeaf->uLeaf != 0x7)
5376	break;
5377	}
5378	}
5379
5380
5381	/**
5382	* Produces a detailed summary of standard leaf 0x0000000d.
5383	*
5384	* @param pHlp The info helper functions.
5385	* @param paLeaves The CPUID leaves array.
5386	* @param cLeaves The number of leaves in the array.
5387	* @param pCurLeaf The first 0x00000007 leaf.
5388	* @param fVerbose Whether to be very verbose or not.
5389	*/
5390	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5391	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5392	{
5393	RT_NOREF_PV(fVerbose);
5394	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
5395	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
5396	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5397	{
5398	CPUMCPUID Host = {0};
5399	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5400	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5401	#endif
5402
5403	switch (uSubLeaf)
5404	{
5405	case 0:
5406	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5407	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
5408	pCurLeaf->uEbx, pCurLeaf->uEcx);
5409	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
5410
5411	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5412	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
5413	"Valid XCR0 bits, guest:", 42);
5414	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
5415	"Valid XCR0 bits, host:", 42);
5416	break;
5417
5418	case 1:
5419	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5420	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
5421	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
5422
5423	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5424	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
5425	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
5426
5427	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5428	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
5429	" Valid IA32_XSS bits, guest:", 42);
5430	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
5431	" Valid IA32_XSS bits, host:", 42);
5432	break;
5433
5434	default:
5435	if ( pCurLeaf
5436	&& pCurLeaf->uSubLeaf == uSubLeaf
5437	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
5438	{
5439	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
5440	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5441	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
5442	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
5443	if (pCurLeaf->uEdx)
5444	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
5445	pHlp->pfnPrintf(pHlp, " --");
5446	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5447	pHlp->pfnPrintf(pHlp, "\n");
5448	}
5449	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
5450	{
5451	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
5452	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5453	if (Host.uEcx & ~RT_BIT_32(0))
5454	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
5455	if (Host.uEdx)
5456	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
5457	pHlp->pfnPrintf(pHlp, " --");
5458	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5459	pHlp->pfnPrintf(pHlp, "\n");
5460	}
5461	break;
5462
5463	}
5464
5465	/* advance. */
5466	if (pCurLeaf)
5467	{
5468	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5469	&& pCurLeaf->uSubLeaf <= uSubLeaf
5470	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
5471	pCurLeaf++;
5472	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5473	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
5474	pCurLeaf = NULL;
5475	}
5476	}
5477	}
5478
5479
5480	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5481	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
5482	{
5483	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5484	&& pCurLeaf->uLeaf <= uUpToLeaf)
5485	{
5486	pHlp->pfnPrintf(pHlp,
5487	" %s\n"
5488	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
5489	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5490	&& pCurLeaf->uLeaf <= uUpToLeaf)
5491	{
5492	CPUMCPUID Host = {0};
5493	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5494	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5495	#endif
5496	pHlp->pfnPrintf(pHlp,
5497	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5498	"Hst: %08x %08x %08x %08x\n",
5499	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5500	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5501	pCurLeaf++;
5502	}
5503	}
5504
5505	return pCurLeaf;
5506	}
5507
5508
5509	/**
5510	* Display the guest CpuId leaves.
5511	*
5512	* @param pVM The cross context VM structure.
5513	* @param pHlp The info helper functions.
5514	* @param pszArgs "terse", "default" or "verbose".
5515	*/
5516	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
5517	{
5518	/*
5519	* Parse the argument.
5520	*/
5521	unsigned iVerbosity = 1;
5522	if (pszArgs)
5523	{
5524	pszArgs = RTStrStripL(pszArgs);
5525	if (!strcmp(pszArgs, "terse"))
5526	iVerbosity--;
5527	else if (!strcmp(pszArgs, "verbose"))
5528	iVerbosity++;
5529	}
5530
5531	uint32_t uLeaf;
5532	CPUMCPUID Host = {0};
5533	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
5534	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
5535	PCCPUMCPUIDLEAF pCurLeaf;
5536	PCCPUMCPUIDLEAF pNextLeaf;
5537	bool const fIntel = RTX86IsIntelCpu(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
5538	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
5539	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
5540
5541	/*
5542	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
5543	*/
5544	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5545	uint32_t cHstMax = ASMCpuId_EAX(0);
5546	#else
5547	uint32_t cHstMax = 0;
5548	#endif
5549	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
5550	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
5551	pHlp->pfnPrintf(pHlp,
5552	" Raw Standard CPUID Leaves\n"
5553	" Leaf/sub-leaf eax ebx ecx edx\n");
5554	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
5555	{
5556	uint32_t cMaxSubLeaves = 1;
5557	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
5558	cMaxSubLeaves = 16;
5559	else if (uLeaf == 0xd)
5560	cMaxSubLeaves = 128;
5561
5562	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5563	{
5564	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5565	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5566	#endif
5567	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5568	&& pCurLeaf->uLeaf == uLeaf
5569	&& pCurLeaf->uSubLeaf == uSubLeaf)
5570	{
5571	pHlp->pfnPrintf(pHlp,
5572	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5573	"Hst: %08x %08x %08x %08x\n",
5574	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5575	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5576	pCurLeaf++;
5577	}
5578	else if ( uLeaf != 0xd
5579	\|\| uSubLeaf <= 1
5580	\|\| Host.uEbx != 0 )
5581	pHlp->pfnPrintf(pHlp,
5582	"Hst: %08x/%04x %08x %08x %08x %08x\n",
5583	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5584
5585	/* Done? */
5586	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5587	\|\| pCurLeaf->uLeaf != uLeaf)
5588	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
5589	\|\| (uLeaf == 0x7 && Host.uEax == 0)
5590	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
5591	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
5592	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
5593	)
5594	)
5595	break;
5596	}
5597	}
5598	pNextLeaf = pCurLeaf;
5599
5600	/*
5601	* If verbose, decode it.
5602	*/
5603	if (iVerbosity && paLeaves[0].uLeaf == 0)
5604	pHlp->pfnPrintf(pHlp,
5605	"%36s %.04s%.04s%.04s\n"
5606	"%36s 0x00000000-%#010x\n"
5607	,
5608	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
5609	"Supports:", paLeaves[0].uEax);
5610
5611	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
5612	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
5613
5614	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
5615	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5616
5617	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
5618	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5619
5620	pCurLeaf = pNextLeaf;
5621
5622	/*
5623	* Hypervisor leaves.
5624	*
5625	* Unlike most of the other leaves reported, the guest hypervisor leaves
5626	* aren't a subset of the host CPUID bits.
5627	*/
5628	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
5629
5630	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5631	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5632	#endif
5633	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
5634	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
5635	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
5636	cMax = RT_MAX(cHstMax, cGstMax);
5637	if (cMax >= UINT32_C(0x40000000))
5638	{
5639	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
5640
5641	/** @todo dump these in more detail. */
5642
5643	pCurLeaf = pNextLeaf;
5644	}
5645
5646
5647	/*
5648	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
5649	* Implemented after AMD specs.
5650	*/
5651	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
5652
5653	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5654	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5655	#endif
5656	cHstMax = RTX86IsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
5657	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
5658	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
5659	cMax = RT_MAX(cHstMax, cGstMax);
5660	if (cMax >= UINT32_C(0x80000000))
5661	{
5662
5663	pHlp->pfnPrintf(pHlp,
5664	" Raw Extended CPUID Leaves\n"
5665	" Leaf/sub-leaf eax ebx ecx edx\n");
5666	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
5667	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
5668	{
5669	uint32_t cMaxSubLeaves = 1;
5670	if (uLeaf == UINT32_C(0x8000001d))
5671	cMaxSubLeaves = 16;
5672
5673	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5674	{
5675	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5676	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5677	#endif
5678	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5679	&& pCurLeaf->uLeaf == uLeaf
5680	&& pCurLeaf->uSubLeaf == uSubLeaf)
5681	{
5682	pHlp->pfnPrintf(pHlp,
5683	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5684	"Hst: %08x %08x %08x %08x\n",
5685	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5686	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5687	pCurLeaf++;
5688	}
5689	else if ( uLeaf != 0xd
5690	\|\| uSubLeaf <= 1
5691	\|\| Host.uEbx != 0 )
5692	pHlp->pfnPrintf(pHlp,
5693	"Hst: %08x/%04x %08x %08x %08x %08x\n",
5694	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5695
5696	/* Done? */
5697	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5698	\|\| pCurLeaf->uLeaf != uLeaf)
5699	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
5700	break;
5701	}
5702	}
5703	pNextLeaf = pCurLeaf;
5704
5705	/*
5706	* Understandable output
5707	*/
5708	if (iVerbosity)
5709	pHlp->pfnPrintf(pHlp,
5710	"Ext Name: %.4s%.4s%.4s\n"
5711	"Ext Supports: 0x80000000-%#010x\n",
5712	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
5713
5714	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
5715	if (iVerbosity && pCurLeaf)
5716	{
5717	uint32_t uEAX = pCurLeaf->uEax;
5718	pHlp->pfnPrintf(pHlp,
5719	"Family: %d \tExtended: %d \tEffective: %d\n"
5720	"Model: %d \tExtended: %d \tEffective: %d\n"
5721	"Stepping: %d\n"
5722	"Brand ID: %#05x\n",
5723	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
5724	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
5725	RTX86GetCpuStepping(uEAX),
5726	pCurLeaf->uEbx & 0xfff);
5727
5728	if (iVerbosity == 1)
5729	{
5730	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
5731	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
5732	}
5733	else
5734	{
5735	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5736	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5737	#endif
5738	pHlp->pfnPrintf(pHlp, "Ext Features\n");
5739	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5740	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
5741	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
5742	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
5743	{
5744	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
5745	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5746	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5747	#endif
5748	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
5749	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
5750	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
5751	}
5752	}
5753	}
5754
5755	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
5756	{
5757	char szString[443+1] = {0};
5758	uint32_t pu32 = (uint32_t )szString;
5759	*pu32++ = pCurLeaf->uEax;
5760	*pu32++ = pCurLeaf->uEbx;
5761	*pu32++ = pCurLeaf->uEcx;
5762	*pu32++ = pCurLeaf->uEdx;
5763	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
5764	if (pCurLeaf)
5765	{
5766	*pu32++ = pCurLeaf->uEax;
5767	*pu32++ = pCurLeaf->uEbx;
5768	*pu32++ = pCurLeaf->uEcx;
5769	*pu32++ = pCurLeaf->uEdx;
5770	}
5771	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
5772	if (pCurLeaf)
5773	{
5774	*pu32++ = pCurLeaf->uEax;
5775	*pu32++ = pCurLeaf->uEbx;
5776	*pu32++ = pCurLeaf->uEcx;
5777	*pu32++ = pCurLeaf->uEdx;
5778	}
5779	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
5780	}
5781
5782	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
5783	{
5784	uint32_t uEAX = pCurLeaf->uEax;
5785	uint32_t uEBX = pCurLeaf->uEbx;
5786	uint32_t uECX = pCurLeaf->uEcx;
5787	uint32_t uEDX = pCurLeaf->uEdx;
5788	char sz1[32];
5789	char sz2[32];
5790
5791	pHlp->pfnPrintf(pHlp,
5792	"TLB 2/4M Instr/Uni: %s %3d entries\n"
5793	"TLB 2/4M Data: %s %3d entries\n",
5794	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
5795	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
5796	pHlp->pfnPrintf(pHlp,
5797	"TLB 4K Instr/Uni: %s %3d entries\n"
5798	"TLB 4K Data: %s %3d entries\n",
5799	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
5800	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
5801	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
5802	"L1 Instr Cache Lines Per Tag: %d\n"
5803	"L1 Instr Cache Associativity: %s\n"
5804	"L1 Instr Cache Size: %d KB\n",
5805	(uEDX >> 0) & 0xff,
5806	(uEDX >> 8) & 0xff,
5807	getCacheAss((uEDX >> 16) & 0xff, sz1),
5808	(uEDX >> 24) & 0xff);
5809	pHlp->pfnPrintf(pHlp,
5810	"L1 Data Cache Line Size: %d bytes\n"
5811	"L1 Data Cache Lines Per Tag: %d\n"
5812	"L1 Data Cache Associativity: %s\n"
5813	"L1 Data Cache Size: %d KB\n",
5814	(uECX >> 0) & 0xff,
5815	(uECX >> 8) & 0xff,
5816	getCacheAss((uECX >> 16) & 0xff, sz1),
5817	(uECX >> 24) & 0xff);
5818	}
5819
5820	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
5821	{
5822	uint32_t uEAX = pCurLeaf->uEax;
5823	uint32_t uEBX = pCurLeaf->uEbx;
5824	uint32_t uECX = pCurLeaf->uEcx;
5825	uint32_t uEDX = pCurLeaf->uEdx;
5826
5827	pHlp->pfnPrintf(pHlp,
5828	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
5829	"L2 TLB 2/4M Data: %s %4d entries\n",
5830	getL23CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
5831	getL23CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
5832	pHlp->pfnPrintf(pHlp,
5833	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
5834	"L2 TLB 4K Data: %s %4d entries\n",
5835	getL23CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
5836	getL23CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
5837	pHlp->pfnPrintf(pHlp,
5838	"L2 Cache Line Size: %d bytes\n"
5839	"L2 Cache Lines Per Tag: %d\n"
5840	"L2 Cache Associativity: %s\n"
5841	"L2 Cache Size: %d KB\n",
5842	(uECX >> 0) & 0xff,
5843	(uECX >> 8) & 0xf,
5844	getL23CacheAss((uECX >> 12) & 0xf),
5845	(uECX >> 16) & 0xffff);
5846	pHlp->pfnPrintf(pHlp,
5847	"L3 Cache Line Size: %d bytes\n"
5848	"L3 Cache Lines Per Tag: %d\n"
5849	"L3 Cache Associativity: %s\n"
5850	"L3 Cache Size: %d KB\n",
5851	(uEDX >> 0) & 0xff,
5852	(uEDX >> 8) & 0xf,
5853	getL23CacheAss((uEDX >> 12) & 0xf),
5854	((uEDX >> 18) & 0x3fff) * 512);
5855	}
5856
5857	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
5858	{
5859	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5860	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5861	#endif
5862	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
5863	{
5864	if (iVerbosity < 1)
5865	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
5866	else
5867	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
5868	}
5869	}
5870
5871	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
5872	if (pCurLeaf != NULL)
5873	{
5874	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5875	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5876	#endif
5877	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
5878	{
5879	if (iVerbosity < 1)
5880	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
5881	else
5882	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
5883	}
5884
5885	if (iVerbosity)
5886	{
5887	uint32_t uEAX = pCurLeaf->uEax;
5888	uint32_t uECX = pCurLeaf->uEcx;
5889
5890	/** @todo 0x80000008:EAX[23:16] is only defined for AMD. We'll get 0 on Intel. On
5891	* AMD if we get 0, the guest physical address width should be taken from
5892	* 0x80000008:EAX[7:0] instead. Guest Physical address width is relevant
5893	* for guests using nested paging. */
5894	pHlp->pfnPrintf(pHlp,
5895	"Physical Address Width: %d bits\n"
5896	"Virtual Address Width: %d bits\n"
5897	"Guest Physical Address Width: %d bits\n",
5898	(uEAX >> 0) & 0xff,
5899	(uEAX >> 8) & 0xff,
5900	(uEAX >> 16) & 0xff);
5901
5902	/** @todo 0x80000008:ECX is reserved on Intel (we'll get incorrect physical core
5903	* count here). */
5904	pHlp->pfnPrintf(pHlp,
5905	"Physical Core Count: %d\n",
5906	((uECX >> 0) & 0xff) + 1);
5907	}
5908	}
5909
5910	pCurLeaf = pNextLeaf;
5911	}
5912
5913
5914
5915	/*
5916	* Centaur.
5917	*/
5918	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
5919
5920	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5921	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5922	#endif
5923	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
5924	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
5925	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
5926	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
5927	cMax = RT_MAX(cHstMax, cGstMax);
5928	if (cMax >= UINT32_C(0xc0000000))
5929	{
5930	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
5931
5932	/*
5933	* Understandable output
5934	*/
5935	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
5936	pHlp->pfnPrintf(pHlp,
5937	"Centaur Supports: 0xc0000000-%#010x\n",
5938	pCurLeaf->uEax);
5939
5940	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
5941	{
5942	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5943	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5944	#endif
5945	uint32_t uEdxGst = pCurLeaf->uEdx;
5946	uint32_t uEdxHst = Host.uEdx;
5947
5948	if (iVerbosity == 1)
5949	{
5950	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
5951	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
5952	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
5953	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
5954	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
5955	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
5956	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
5957	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
5958	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
5959	/* possibly indicating MM/HE and MM/HE-E on older chips... */
5960	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
5961	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
5962	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
5963	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
5964	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
5965	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
5966	for (unsigned iBit = 14; iBit < 32; iBit++)
5967	if (uEdxGst & RT_BIT(iBit))
5968	pHlp->pfnPrintf(pHlp, " %d", iBit);
5969	pHlp->pfnPrintf(pHlp, "\n");
5970	}
5971	else
5972	{
5973	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
5974	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
5975	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
5976	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
5977	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
5978	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
5979	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
5980	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
5981	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
5982	/* possibly indicating MM/HE and MM/HE-E on older chips... */
5983	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
5984	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
5985	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
5986	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
5987	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
5988	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
5989	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
5990	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
5991	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
5992	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
5993	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
5994	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
5995	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
5996	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
5997	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
5998	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
5999	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
6000	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
6001	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
6002	for (unsigned iBit = 27; iBit < 32; iBit++)
6003	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
6004	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
6005	pHlp->pfnPrintf(pHlp, "\n");
6006	}
6007	}
6008
6009	pCurLeaf = pNextLeaf;
6010	}
6011
6012	/*
6013	* The remainder.
6014	*/
6015	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
6016	}
6017
6018	#endif /* !IN_VBOX_CPU_REPORT */
6019

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 102371

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