CPUMR3CpuId.cpp@ 94319

Last change on this file since 94319 was 93924, checked in by vboxsync, 3 years ago
VMM: Nested VMX: bugref:10092 Accidentally enabled nested EPT and UX by default in r150150, undid that.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 344.6 KB

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1	/* $Id: CPUMR3CpuId.cpp 93924 2022-02-24 15:16:25Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vmcc.h>
30	#include <VBox/sup.h>
31
32	#include <VBox/err.h>
33	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
34	# include <iprt/asm-amd64-x86.h>
35	#endif
36	#include <iprt/ctype.h>
37	#include <iprt/mem.h>
38	#include <iprt/string.h>
39	#include <iprt/x86-helpers.h>
40
41
42	/*********************************************************************************************************************************
43	* Defined Constants And Macros *
44	*********************************************************************************************************************************/
45	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
46	#define CPUM_CPUID_MAX_LEAVES 2048
47	/** Max size we accept for the XSAVE area.
48	* @see CPUMCTX::abXSave */
49	#define CPUM_MAX_XSAVE_AREA_SIZE (0x4000 - 0x300)
50	/* Min size we accept for the XSAVE area. */
51	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
52
53
54	/*********************************************************************************************************************************
55	* Global Variables *
56	*********************************************************************************************************************************/
57	/**
58	* The intel pentium family.
59	*/
60	static const CPUMMICROARCH g_aenmIntelFamily06[] =
61	{
62	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
63	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
64	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
65	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
66	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
67	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
68	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
69	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
70	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
71	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
72	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
73	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
74	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
75	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
76	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
77	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
78	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
81	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
82	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
83	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
84	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
85	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
86	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
87	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
88	/* [26(0x1a)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Nehalem-EP */
89	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
90	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
91	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
92	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
93	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
94	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
97	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
98	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
99	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
100	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
101	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
102	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
103	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
104	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
105	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
106	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
107	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
108	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
109	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
110	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
113	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
114	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
115	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
116	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
117	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
118	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
120	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
121	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
122	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
124	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
125	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
126	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
129	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
130	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
131	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
132	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
133	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
134	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
136	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
137	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
138	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
139	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
140	/* [78(0x4e)] = */ kCpumMicroarch_Intel_Core7_Skylake,
141	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Broadwell-E */
142	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
145	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
146	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
147	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu; skylake <= 4, cascade lake > 5 */
148	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
149	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
150	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
151	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
152	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
153	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
154	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
155	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
156	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
157	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
158	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
159	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
160	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
161	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
162	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
163	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
164	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
165	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
166	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
167	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
168	/[106(0x6a)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
169	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
170	/[108(0x6c)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
171	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
172	/[110(0x6e)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
173	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
174	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
175	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
176	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
177	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
178	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
179	/[117(0x75)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
180	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
181	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
182	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
183	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
184	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
185	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
186	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
187	/[125(0x7d)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
188	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
189	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
190	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
191	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
192	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
193	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
194	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
195	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
196	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
197	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
198	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
199	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
200	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
201	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
202	/[140(0x8c)] = / kCpumMicroarch_Intel_Core7_TigerLake, /* 11th Gen Intel(R) Core(TM) i7-1185G7 @ 3.00GHz (bird) */
203	/[141(0x8d)] = / kCpumMicroarch_Intel_Core7_TigerLake, /* unconfirmed */
204	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
205	/[143(0x8f)] = / kCpumMicroarch_Intel_Core7_SapphireRapids,
206	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
207	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
208	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
209	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
210	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
211	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
212	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
213	/[151(0x97)] = / kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
214	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
215	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
216	/[154(0x9a)] = / kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
217	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
218	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
219	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
220	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
221	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
222	/[160(0xa0)] = / kCpumMicroarch_Intel_Unknown,
223	/[161(0xa1)] = / kCpumMicroarch_Intel_Unknown,
224	/[162(0xa2)] = / kCpumMicroarch_Intel_Unknown,
225	/[163(0xa3)] = / kCpumMicroarch_Intel_Unknown,
226	/[164(0xa4)] = / kCpumMicroarch_Intel_Unknown,
227	/[165(0xa5)] = / kCpumMicroarch_Intel_Core7_CometLake, /* unconfirmed */
228	/[166(0xa6)] = / kCpumMicroarch_Intel_Unknown,
229	/[167(0xa7)] = / kCpumMicroarch_Intel_Core7_CypressCove, /* 14nm backport, unconfirmed */
230	};
231	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0xa7+1);
232
233
234	/**
235	* Figures out the (sub-)micro architecture given a bit of CPUID info.
236	*
237	* @returns Micro architecture.
238	* @param enmVendor The CPU vendor.
239	* @param bFamily The CPU family.
240	* @param bModel The CPU model.
241	* @param bStepping The CPU stepping.
242	*/
243	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
244	uint8_t bModel, uint8_t bStepping)
245	{
246	if (enmVendor == CPUMCPUVENDOR_AMD)
247	{
248	switch (bFamily)
249	{
250	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
251	case 0x03: return kCpumMicroarch_AMD_Am386;
252	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
253	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
254	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
255	case 0x06:
256	switch (bModel)
257	{
258	case 0: return kCpumMicroarch_AMD_K7_Palomino;
259	case 1: return kCpumMicroarch_AMD_K7_Palomino;
260	case 2: return kCpumMicroarch_AMD_K7_Palomino;
261	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
262	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
263	case 6: return kCpumMicroarch_AMD_K7_Palomino;
264	case 7: return kCpumMicroarch_AMD_K7_Morgan;
265	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
266	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
267	}
268	return kCpumMicroarch_AMD_K7_Unknown;
269	case 0x0f:
270	/*
271	* This family is a friggin mess. Trying my best to make some
272	* sense out of it. Too much happened in the 0x0f family to
273	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
274	*
275	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
276	* cpu-world.com, and other places:
277	* - 130nm:
278	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
279	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
280	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
281	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
282	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
283	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
284	* - 90nm:
285	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
286	* - Oakville: 10FC0/DH-D0.
287	* - Georgetown: 10FC0/DH-D0.
288	* - Sonora: 10FC0/DH-D0.
289	* - Venus: 20F71/SH-E4
290	* - Troy: 20F51/SH-E4
291	* - Athens: 20F51/SH-E4
292	* - San Diego: 20F71/SH-E4.
293	* - Lancaster: 20F42/SH-E5
294	* - Newark: 20F42/SH-E5.
295	* - Albany: 20FC2/DH-E6.
296	* - Roma: 20FC2/DH-E6.
297	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
298	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
299	* - 90nm introducing Dual core:
300	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
301	* - Italy: 20F10/JH-E1, 20F12/JH-E6
302	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
303	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
304	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
305	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
306	* - Santa Ana: 40F32/JH-F2, /-F3
307	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
308	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
309	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
310	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
311	* - Keene: 40FC2/DH-F2.
312	* - Richmond: 40FC2/DH-F2
313	* - Taylor: 40F82/BH-F2
314	* - Trinidad: 40F82/BH-F2
315	*
316	* - 65nm:
317	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
318	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
319	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
320	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
321	* - Sherman: /-G1, 70FC2/DH-G2.
322	* - Huron: 70FF2/DH-G2.
323	*/
324	if (bModel < 0x10)
325	return kCpumMicroarch_AMD_K8_130nm;
326	if (bModel >= 0x60 && bModel < 0x80)
327	return kCpumMicroarch_AMD_K8_65nm;
328	if (bModel >= 0x40)
329	return kCpumMicroarch_AMD_K8_90nm_AMDV;
330	switch (bModel)
331	{
332	case 0x21:
333	case 0x23:
334	case 0x2b:
335	case 0x2f:
336	case 0x37:
337	case 0x3f:
338	return kCpumMicroarch_AMD_K8_90nm_DualCore;
339	}
340	return kCpumMicroarch_AMD_K8_90nm;
341	case 0x10:
342	return kCpumMicroarch_AMD_K10;
343	case 0x11:
344	return kCpumMicroarch_AMD_K10_Lion;
345	case 0x12:
346	return kCpumMicroarch_AMD_K10_Llano;
347	case 0x14:
348	return kCpumMicroarch_AMD_Bobcat;
349	case 0x15:
350	switch (bModel)
351	{
352	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
353	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
354	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
355	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
356	case 0x11: /* ?? */
357	case 0x12: /* ?? */
358	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
359	}
360	return kCpumMicroarch_AMD_15h_Unknown;
361	case 0x16:
362	return kCpumMicroarch_AMD_Jaguar;
363	case 0x17:
364	return kCpumMicroarch_AMD_Zen_Ryzen;
365	}
366	return kCpumMicroarch_AMD_Unknown;
367	}
368
369	if (enmVendor == CPUMCPUVENDOR_INTEL)
370	{
371	switch (bFamily)
372	{
373	case 3:
374	return kCpumMicroarch_Intel_80386;
375	case 4:
376	return kCpumMicroarch_Intel_80486;
377	case 5:
378	return kCpumMicroarch_Intel_P5;
379	case 6:
380	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
381	{
382	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
383	if (enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake)
384	{
385	if (bStepping >= 0xa && bStepping <= 0xc)
386	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
387	else if (bStepping >= 0xc)
388	enmMicroArch = kCpumMicroarch_Intel_Core7_WhiskeyLake;
389	}
390	else if ( enmMicroArch == kCpumMicroarch_Intel_Core7_Skylake
391	&& bModel == 0x55
392	&& bStepping >= 5)
393	enmMicroArch = kCpumMicroarch_Intel_Core7_CascadeLake;
394	return enmMicroArch;
395	}
396	return kCpumMicroarch_Intel_Atom_Unknown;
397	case 15:
398	switch (bModel)
399	{
400	case 0: return kCpumMicroarch_Intel_NB_Willamette;
401	case 1: return kCpumMicroarch_Intel_NB_Willamette;
402	case 2: return kCpumMicroarch_Intel_NB_Northwood;
403	case 3: return kCpumMicroarch_Intel_NB_Prescott;
404	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
405	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
406	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
407	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
408	default: return kCpumMicroarch_Intel_NB_Unknown;
409	}
410	break;
411	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
412	case 0:
413	return kCpumMicroarch_Intel_8086;
414	case 1:
415	return kCpumMicroarch_Intel_80186;
416	case 2:
417	return kCpumMicroarch_Intel_80286;
418	}
419	return kCpumMicroarch_Intel_Unknown;
420	}
421
422	if (enmVendor == CPUMCPUVENDOR_VIA)
423	{
424	switch (bFamily)
425	{
426	case 5:
427	switch (bModel)
428	{
429	case 1: return kCpumMicroarch_Centaur_C6;
430	case 4: return kCpumMicroarch_Centaur_C6;
431	case 8: return kCpumMicroarch_Centaur_C2;
432	case 9: return kCpumMicroarch_Centaur_C3;
433	}
434	break;
435
436	case 6:
437	switch (bModel)
438	{
439	case 5: return kCpumMicroarch_VIA_C3_M2;
440	case 6: return kCpumMicroarch_VIA_C3_C5A;
441	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
442	case 8: return kCpumMicroarch_VIA_C3_C5N;
443	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
444	case 10: return kCpumMicroarch_VIA_C7_C5J;
445	case 15: return kCpumMicroarch_VIA_Isaiah;
446	}
447	break;
448	}
449	return kCpumMicroarch_VIA_Unknown;
450	}
451
452	if (enmVendor == CPUMCPUVENDOR_SHANGHAI)
453	{
454	switch (bFamily)
455	{
456	case 6:
457	case 7:
458	return kCpumMicroarch_Shanghai_Wudaokou;
459	default:
460	break;
461	}
462	return kCpumMicroarch_Shanghai_Unknown;
463	}
464
465	if (enmVendor == CPUMCPUVENDOR_CYRIX)
466	{
467	switch (bFamily)
468	{
469	case 4:
470	switch (bModel)
471	{
472	case 9: return kCpumMicroarch_Cyrix_5x86;
473	}
474	break;
475
476	case 5:
477	switch (bModel)
478	{
479	case 2: return kCpumMicroarch_Cyrix_M1;
480	case 4: return kCpumMicroarch_Cyrix_MediaGX;
481	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
482	}
483	break;
484
485	case 6:
486	switch (bModel)
487	{
488	case 0: return kCpumMicroarch_Cyrix_M2;
489	}
490	break;
491
492	}
493	return kCpumMicroarch_Cyrix_Unknown;
494	}
495
496	if (enmVendor == CPUMCPUVENDOR_HYGON)
497	{
498	switch (bFamily)
499	{
500	case 0x18:
501	return kCpumMicroarch_Hygon_Dhyana;
502	default:
503	break;
504	}
505	return kCpumMicroarch_Hygon_Unknown;
506	}
507
508	return kCpumMicroarch_Unknown;
509	}
510
511
512	/**
513	* Translates a microarchitecture enum value to the corresponding string
514	* constant.
515	*
516	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
517	* NULL if the value is invalid.
518	*
519	* @param enmMicroarch The enum value to convert.
520	*/
521	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
522	{
523	switch (enmMicroarch)
524	{
525	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
526	CASE_RET_STR(kCpumMicroarch_Intel_8086);
527	CASE_RET_STR(kCpumMicroarch_Intel_80186);
528	CASE_RET_STR(kCpumMicroarch_Intel_80286);
529	CASE_RET_STR(kCpumMicroarch_Intel_80386);
530	CASE_RET_STR(kCpumMicroarch_Intel_80486);
531	CASE_RET_STR(kCpumMicroarch_Intel_P5);
532
533	CASE_RET_STR(kCpumMicroarch_Intel_P6);
534	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
535	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
536
537	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
538	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
539	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
540
541	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
542	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
543
544	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
545	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
546	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
547	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
548	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
549	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
550	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
551	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
552	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
553	CASE_RET_STR(kCpumMicroarch_Intel_Core7_WhiskeyLake);
554	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CascadeLake);
555	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
556	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CometLake);
557	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
558	CASE_RET_STR(kCpumMicroarch_Intel_Core7_RocketLake);
559	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
560	CASE_RET_STR(kCpumMicroarch_Intel_Core7_AlderLake);
561	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SapphireRapids);
562
563	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
564	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
565	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
566	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
567	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
568	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
569	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
570	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
571
572	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
573	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
574	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
575	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
576	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
577
578	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
579	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
580	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
581	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
582	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
583	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
584	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
585
586	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
587
588	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
589	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
590	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
591	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
592	CASE_RET_STR(kCpumMicroarch_AMD_K5);
593	CASE_RET_STR(kCpumMicroarch_AMD_K6);
594
595	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
596	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
597	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
598	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
599	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
600	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
601	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
602
603	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
604	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
605	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
606	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
607	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
608
609	CASE_RET_STR(kCpumMicroarch_AMD_K10);
610	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
611	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
612	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
613	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
614
615	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
616	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
617	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
618	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
619	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
620
621	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
622
623	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
624
625	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
626
627	CASE_RET_STR(kCpumMicroarch_Hygon_Dhyana);
628	CASE_RET_STR(kCpumMicroarch_Hygon_Unknown);
629
630	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
631	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
632	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
633	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
634	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
635	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
636	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
637	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
638	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
639	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
640	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
641	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
642	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
643
644	CASE_RET_STR(kCpumMicroarch_Shanghai_Wudaokou);
645	CASE_RET_STR(kCpumMicroarch_Shanghai_Unknown);
646
647	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
648	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
649	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
650	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
651	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
652	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
653
654	CASE_RET_STR(kCpumMicroarch_NEC_V20);
655	CASE_RET_STR(kCpumMicroarch_NEC_V30);
656
657	CASE_RET_STR(kCpumMicroarch_Unknown);
658
659	#undef CASE_RET_STR
660	case kCpumMicroarch_Invalid:
661	case kCpumMicroarch_Intel_End:
662	case kCpumMicroarch_Intel_Core2_End:
663	case kCpumMicroarch_Intel_Core7_End:
664	case kCpumMicroarch_Intel_Atom_End:
665	case kCpumMicroarch_Intel_P6_Core_Atom_End:
666	case kCpumMicroarch_Intel_Phi_End:
667	case kCpumMicroarch_Intel_NB_End:
668	case kCpumMicroarch_AMD_K7_End:
669	case kCpumMicroarch_AMD_K8_End:
670	case kCpumMicroarch_AMD_15h_End:
671	case kCpumMicroarch_AMD_16h_End:
672	case kCpumMicroarch_AMD_Zen_End:
673	case kCpumMicroarch_AMD_End:
674	case kCpumMicroarch_Hygon_End:
675	case kCpumMicroarch_VIA_End:
676	case kCpumMicroarch_Shanghai_End:
677	case kCpumMicroarch_Cyrix_End:
678	case kCpumMicroarch_NEC_End:
679	case kCpumMicroarch_32BitHack:
680	break;
681	/* no default! */
682	}
683
684	return NULL;
685	}
686
687
688	/**
689	* Determins the host CPU MXCSR mask.
690	*
691	* @returns MXCSR mask.
692	*/
693	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
694	{
695	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
696	if ( ASMHasCpuId()
697	&& RTX86IsValidStdRange(ASMCpuId_EAX(0))
698	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
699	{
700	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
701	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
702	RT_ZERO(*pState);
703	ASMFxSave(pState);
704	if (pState->MXCSR_MASK == 0)
705	return 0xffbf;
706	return pState->MXCSR_MASK;
707	}
708	#endif
709	return 0;
710	}
711
712
713	/**
714	* Gets a matching leaf in the CPUID leaf array.
715	*
716	* @returns Pointer to the matching leaf, or NULL if not found.
717	* @param paLeaves The CPUID leaves to search. This is sorted.
718	* @param cLeaves The number of leaves in the array.
719	* @param uLeaf The leaf to locate.
720	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
721	*/
722	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
723	{
724	/* Lazy bird does linear lookup here since this is only used for the
725	occational CPUID overrides. */
726	for (uint32_t i = 0; i < cLeaves; i++)
727	if ( paLeaves[i].uLeaf == uLeaf
728	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
729	return &paLeaves[i];
730	return NULL;
731	}
732
733
734	#ifndef IN_VBOX_CPU_REPORT
735	/**
736	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
737	*
738	* @returns true if found, false it not.
739	* @param paLeaves The CPUID leaves to search. This is sorted.
740	* @param cLeaves The number of leaves in the array.
741	* @param uLeaf The leaf to locate.
742	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
743	* @param pLegacy The legacy output leaf.
744	*/
745	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
746	PCPUMCPUID pLegacy)
747	{
748	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
749	if (pLeaf)
750	{
751	pLegacy->uEax = pLeaf->uEax;
752	pLegacy->uEbx = pLeaf->uEbx;
753	pLegacy->uEcx = pLeaf->uEcx;
754	pLegacy->uEdx = pLeaf->uEdx;
755	return true;
756	}
757	return false;
758	}
759	#endif /* IN_VBOX_CPU_REPORT */
760
761
762	/**
763	* Ensures that the CPUID leaf array can hold one more leaf.
764	*
765	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
766	* failure.
767	* @param pVM The cross context VM structure. If NULL, use
768	* the process heap, otherwise the VM's hyper heap.
769	* @param ppaLeaves Pointer to the variable holding the array pointer
770	* (input/output).
771	* @param cLeaves The current array size.
772	*
773	* @remarks This function will automatically update the R0 and RC pointers when
774	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
775	* be the corresponding VM's CPUID arrays (which is asserted).
776	*/
777	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
778	{
779	/*
780	* If pVM is not specified, we're on the regular heap and can waste a
781	* little space to speed things up.
782	*/
783	uint32_t cAllocated;
784	if (!pVM)
785	{
786	cAllocated = RT_ALIGN(cLeaves, 16);
787	if (cLeaves + 1 > cAllocated)
788	{
789	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
790	if (pvNew)
791	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
792	else
793	{
794	RTMemFree(*ppaLeaves);
795	*ppaLeaves = NULL;
796	}
797	}
798	}
799	/*
800	* Otherwise, we're on the hyper heap and are probably just inserting
801	* one or two leaves and should conserve space.
802	*/
803	else
804	{
805	#ifdef IN_VBOX_CPU_REPORT
806	AssertReleaseFailed();
807	#else
808	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
809	Assert(*ppaLeaves == pVM->cpum.s.GuestInfo.aCpuIdLeaves);
810	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
811
812	if (cLeaves + 1 <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves))
813	{ }
814	else
815	{
816	*ppaLeaves = NULL;
817	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: Out of CPUID space!\n"));
818	}
819	#endif
820	}
821	return *ppaLeaves;
822	}
823
824
825	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
826	/**
827	* Append a CPUID leaf or sub-leaf.
828	*
829	* ASSUMES linear insertion order, so we'll won't need to do any searching or
830	* replace anything. Use cpumR3CpuIdInsert() for those cases.
831	*
832	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
833	* the caller need do no more work.
834	* @param ppaLeaves Pointer to the pointer to the array of sorted
835	* CPUID leaves and sub-leaves.
836	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
837	* @param uLeaf The leaf we're adding.
838	* @param uSubLeaf The sub-leaf number.
839	* @param fSubLeafMask The sub-leaf mask.
840	* @param uEax The EAX value.
841	* @param uEbx The EBX value.
842	* @param uEcx The ECX value.
843	* @param uEdx The EDX value.
844	* @param fFlags The flags.
845	*/
846	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
847	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
848	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
849	{
850	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
851	return VERR_NO_MEMORY;
852
853	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
854	Assert( *pcLeaves == 0
855	\|\| pNew[-1].uLeaf < uLeaf
856	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
857
858	pNew->uLeaf = uLeaf;
859	pNew->uSubLeaf = uSubLeaf;
860	pNew->fSubLeafMask = fSubLeafMask;
861	pNew->uEax = uEax;
862	pNew->uEbx = uEbx;
863	pNew->uEcx = uEcx;
864	pNew->uEdx = uEdx;
865	pNew->fFlags = fFlags;
866
867	*pcLeaves += 1;
868	return VINF_SUCCESS;
869	}
870	#endif /* RT_ARCH_X86 \|\| RT_ARCH_AMD64 */
871
872
873	/**
874	* Checks that we've updated the CPUID leaves array correctly.
875	*
876	* This is a no-op in non-strict builds.
877	*
878	* @param paLeaves The leaves array.
879	* @param cLeaves The number of leaves.
880	*/
881	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
882	{
883	#ifdef VBOX_STRICT
884	for (uint32_t i = 1; i < cLeaves; i++)
885	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
886	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
887	else
888	{
889	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
890	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
891	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
892	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
893	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
894	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
895	}
896	#else
897	NOREF(paLeaves);
898	NOREF(cLeaves);
899	#endif
900	}
901
902
903	/**
904	* Inserts a CPU ID leaf, replacing any existing ones.
905	*
906	* When inserting a simple leaf where we already got a series of sub-leaves with
907	* the same leaf number (eax), the simple leaf will replace the whole series.
908	*
909	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
910	* host-context heap and has only been allocated/reallocated by the
911	* cpumR3CpuIdEnsureSpace function.
912	*
913	* @returns VBox status code.
914	* @param pVM The cross context VM structure. If NULL, use
915	* the process heap, otherwise the VM's hyper heap.
916	* @param ppaLeaves Pointer to the pointer to the array of sorted
917	* CPUID leaves and sub-leaves. Must be NULL if using
918	* the hyper heap.
919	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
920	* be NULL if using the hyper heap.
921	* @param pNewLeaf Pointer to the data of the new leaf we're about to
922	* insert.
923	*/
924	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
925	{
926	/*
927	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
928	*/
929	if (pVM)
930	{
931	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
932	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
933	AssertReturn(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 == pVM->cpum.s.GuestInfo.aCpuIdLeaves, VERR_INVALID_PARAMETER);
934
935	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
936	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
937	}
938
939	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
940	uint32_t cLeaves = *pcLeaves;
941
942	/*
943	* Validate the new leaf a little.
944	*/
945	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
946	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
947	VERR_INVALID_FLAGS);
948	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
949	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
950	VERR_INVALID_PARAMETER);
951	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
952	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
953	VERR_INVALID_PARAMETER);
954	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
955	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
956	VERR_INVALID_PARAMETER);
957
958	/*
959	* Find insertion point. The lazy bird uses the same excuse as in
960	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
961	*/
962	uint32_t i;
963	if ( cLeaves > 0
964	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
965	{
966	/* Add at end. */
967	i = cLeaves;
968	}
969	else if ( cLeaves > 0
970	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
971	{
972	/* Either replacing the last leaf or dealing with sub-leaves. Spool
973	back to the first sub-leaf to pretend we did the linear search. */
974	i = cLeaves - 1;
975	while ( i > 0
976	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
977	i--;
978	}
979	else
980	{
981	/* Linear search from the start. */
982	i = 0;
983	while ( i < cLeaves
984	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
985	i++;
986	}
987	if ( i < cLeaves
988	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
989	{
990	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
991	{
992	/*
993	* The sub-leaf mask differs, replace all existing leaves with the
994	* same leaf number.
995	*/
996	uint32_t c = 1;
997	while ( i + c < cLeaves
998	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
999	c++;
1000	if (c > 1 && i + c < cLeaves)
1001	{
1002	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
1003	*pcLeaves = cLeaves -= c - 1;
1004	}
1005
1006	paLeaves[i] = *pNewLeaf;
1007	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1008	return VINF_SUCCESS;
1009	}
1010
1011	/* Find sub-leaf insertion point. */
1012	while ( i < cLeaves
1013	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
1014	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
1015	i++;
1016
1017	/*
1018	* If we've got an exactly matching leaf, replace it.
1019	*/
1020	if ( i < cLeaves
1021	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
1022	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
1023	{
1024	paLeaves[i] = *pNewLeaf;
1025	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1026	return VINF_SUCCESS;
1027	}
1028	}
1029
1030	/*
1031	* Adding a new leaf at 'i'.
1032	*/
1033	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
1034	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
1035	if (!paLeaves)
1036	return VERR_NO_MEMORY;
1037
1038	if (i < cLeaves)
1039	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
1040	*pcLeaves += 1;
1041	paLeaves[i] = *pNewLeaf;
1042
1043	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1044	return VINF_SUCCESS;
1045	}
1046
1047
1048	#ifndef IN_VBOX_CPU_REPORT
1049	/**
1050	* Removes a range of CPUID leaves.
1051	*
1052	* This will not reallocate the array.
1053	*
1054	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1055	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1056	* @param uFirst The first leaf.
1057	* @param uLast The last leaf.
1058	*/
1059	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1060	{
1061	uint32_t cLeaves = *pcLeaves;
1062
1063	Assert(uFirst <= uLast);
1064
1065	/*
1066	* Find the first one.
1067	*/
1068	uint32_t iFirst = 0;
1069	while ( iFirst < cLeaves
1070	&& paLeaves[iFirst].uLeaf < uFirst)
1071	iFirst++;
1072
1073	/*
1074	* Find the end (last + 1).
1075	*/
1076	uint32_t iEnd = iFirst;
1077	while ( iEnd < cLeaves
1078	&& paLeaves[iEnd].uLeaf <= uLast)
1079	iEnd++;
1080
1081	/*
1082	* Adjust the array if anything needs removing.
1083	*/
1084	if (iFirst < iEnd)
1085	{
1086	if (iEnd < cLeaves)
1087	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1088	*pcLeaves = cLeaves -= (iEnd - iFirst);
1089	}
1090
1091	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1092	}
1093	#endif /* IN_VBOX_CPU_REPORT */
1094
1095
1096	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
1097	/**
1098	* Checks if ECX make a difference when reading a given CPUID leaf.
1099	*
1100	* @returns @c true if it does, @c false if it doesn't.
1101	* @param uLeaf The leaf we're reading.
1102	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1103	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1104	* final sub-leaf (for leaf 0xb only).
1105	*/
1106	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1107	{
1108	*pfFinalEcxUnchanged = false;
1109
1110	uint32_t auCur[4];
1111	uint32_t auPrev[4];
1112	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1113
1114	/* Look for sub-leaves. */
1115	uint32_t uSubLeaf = 1;
1116	for (;;)
1117	{
1118	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1119	if (memcmp(auCur, auPrev, sizeof(auCur)))
1120	break;
1121
1122	/* Advance / give up. */
1123	uSubLeaf++;
1124	if (uSubLeaf >= 64)
1125	{
1126	*pcSubLeaves = 1;
1127	return false;
1128	}
1129	}
1130
1131	/* Count sub-leaves. */
1132	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1133	uint32_t cRepeats = 0;
1134	uSubLeaf = 0;
1135	for (;;)
1136	{
1137	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1138
1139	/* Figuring out when to stop isn't entirely straight forward as we need
1140	to cover undocumented behavior up to a point and implementation shortcuts. */
1141
1142	/* 1. Look for more than 4 repeating value sets. */
1143	if ( auCur[0] == auPrev[0]
1144	&& auCur[1] == auPrev[1]
1145	&& ( auCur[2] == auPrev[2]
1146	\|\| ( auCur[2] == uSubLeaf
1147	&& auPrev[2] == uSubLeaf - 1) )
1148	&& auCur[3] == auPrev[3])
1149	{
1150	if ( uLeaf != 0xd
1151	\|\| uSubLeaf >= 64
1152	\|\| ( auCur[0] == 0
1153	&& auCur[1] == 0
1154	&& auCur[2] == 0
1155	&& auCur[3] == 0
1156	&& auPrev[2] == 0) )
1157	cRepeats++;
1158	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1159	break;
1160	}
1161	else
1162	cRepeats = 0;
1163
1164	/* 2. Look for zero values. */
1165	if ( auCur[0] == 0
1166	&& auCur[1] == 0
1167	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1168	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1169	&& uSubLeaf >= cMinLeaves)
1170	{
1171	cRepeats = 0;
1172	break;
1173	}
1174
1175	/* 3. Leaf 0xb level type 0 check. */
1176	if ( uLeaf == 0xb
1177	&& (auCur[2] & 0xff00) == 0
1178	&& (auPrev[2] & 0xff00) == 0)
1179	{
1180	cRepeats = 0;
1181	break;
1182	}
1183
1184	/* 99. Give up. */
1185	if (uSubLeaf >= 128)
1186	{
1187	# ifndef IN_VBOX_CPU_REPORT
1188	/* Ok, limit it according to the documentation if possible just to
1189	avoid annoying users with these detection issues. */
1190	uint32_t cDocLimit = UINT32_MAX;
1191	if (uLeaf == 0x4)
1192	cDocLimit = 4;
1193	else if (uLeaf == 0x7)
1194	cDocLimit = 1;
1195	else if (uLeaf == 0xd)
1196	cDocLimit = 63;
1197	else if (uLeaf == 0xf)
1198	cDocLimit = 2;
1199	if (cDocLimit != UINT32_MAX)
1200	{
1201	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1202	*pcSubLeaves = cDocLimit + 3;
1203	return true;
1204	}
1205	# endif
1206	*pcSubLeaves = UINT32_MAX;
1207	return true;
1208	}
1209
1210	/* Advance. */
1211	uSubLeaf++;
1212	memcpy(auPrev, auCur, sizeof(auCur));
1213	}
1214
1215	/* Standard exit. */
1216	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1217	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1218	if (*pcSubLeaves == 0)
1219	*pcSubLeaves = 1;
1220	return true;
1221	}
1222	#endif /* RT_ARCH_X86 \|\| RT_ARCH_AMD64 */
1223
1224
1225	/**
1226	* Gets a CPU ID leaf.
1227	*
1228	* @returns VBox status code.
1229	* @param pVM The cross context VM structure.
1230	* @param pLeaf Where to store the found leaf.
1231	* @param uLeaf The leaf to locate.
1232	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1233	*/
1234	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1235	{
1236	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1237	uLeaf, uSubLeaf);
1238	if (pcLeaf)
1239	{
1240	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1241	return VINF_SUCCESS;
1242	}
1243
1244	return VERR_NOT_FOUND;
1245	}
1246
1247
1248	/**
1249	* Gets all the leaves.
1250	*
1251	* This only works after the CPUID leaves have been initialized. The interface
1252	* is intended for NEM and configuring CPUID leaves for the native hypervisor.
1253	*
1254	* @returns Pointer to the array of leaves. NULL on failure.
1255	* @param pVM The cross context VM structure.
1256	* @param pcLeaves Where to return the number of leaves.
1257	*/
1258	VMMR3_INT_DECL(PCCPUMCPUIDLEAF) CPUMR3CpuIdGetPtr(PVM pVM, uint32_t *pcLeaves)
1259	{
1260	*pcLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
1261	return pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
1262	}
1263
1264
1265	/**
1266	* Inserts a CPU ID leaf, replacing any existing ones.
1267	*
1268	* @returns VBox status code.
1269	* @param pVM The cross context VM structure.
1270	* @param pNewLeaf Pointer to the leaf being inserted.
1271	*/
1272	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1273	{
1274	/*
1275	* Validate parameters.
1276	*/
1277	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1278	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1279
1280	/*
1281	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1282	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1283	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1284	*/
1285	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1286	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1287	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1288	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1289	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1290	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1291	{
1292	return VERR_NOT_SUPPORTED;
1293	}
1294
1295	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1296	}
1297
1298	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
1299
1300	/**
1301	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1302	*
1303	* @returns VBox status code.
1304	* @param ppaLeaves Where to return the array pointer on success.
1305	* Use RTMemFree to release.
1306	* @param pcLeaves Where to return the size of the array on
1307	* success.
1308	*/
1309	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1310	{
1311	*ppaLeaves = NULL;
1312	*pcLeaves = 0;
1313
1314	/*
1315	* Try out various candidates. This must be sorted!
1316	*/
1317	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1318	{
1319	{ UINT32_C(0x00000000), false },
1320	{ UINT32_C(0x10000000), false },
1321	{ UINT32_C(0x20000000), false },
1322	{ UINT32_C(0x30000000), false },
1323	{ UINT32_C(0x40000000), false },
1324	{ UINT32_C(0x50000000), false },
1325	{ UINT32_C(0x60000000), false },
1326	{ UINT32_C(0x70000000), false },
1327	{ UINT32_C(0x80000000), false },
1328	{ UINT32_C(0x80860000), false },
1329	{ UINT32_C(0x8ffffffe), true },
1330	{ UINT32_C(0x8fffffff), true },
1331	{ UINT32_C(0x90000000), false },
1332	{ UINT32_C(0xa0000000), false },
1333	{ UINT32_C(0xb0000000), false },
1334	{ UINT32_C(0xc0000000), false },
1335	{ UINT32_C(0xd0000000), false },
1336	{ UINT32_C(0xe0000000), false },
1337	{ UINT32_C(0xf0000000), false },
1338	};
1339
1340	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1341	{
1342	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1343	uint32_t uEax, uEbx, uEcx, uEdx;
1344	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1345
1346	/*
1347	* Does EAX look like a typical leaf count value?
1348	*/
1349	if ( uEax > uLeaf
1350	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1351	{
1352	/* Yes, dump them. */
1353	uint32_t cLeaves = uEax - uLeaf + 1;
1354	while (cLeaves-- > 0)
1355	{
1356	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1357
1358	uint32_t fFlags = 0;
1359
1360	/* There are currently three known leaves containing an APIC ID
1361	that needs EMT specific attention */
1362	if (uLeaf == 1)
1363	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1364	else if (uLeaf == 0xb && uEcx != 0)
1365	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1366	else if ( uLeaf == UINT32_C(0x8000001e)
1367	&& ( uEax
1368	\|\| uEbx
1369	\|\| uEdx
1370	\|\| RTX86IsAmdCpu((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1371	\|\| RTX86IsHygonCpu((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1372	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1373
1374	/* The APIC bit is per-VCpu and needs flagging. */
1375	if (uLeaf == 1)
1376	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1377	else if ( uLeaf == UINT32_C(0x80000001)
1378	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1379	\|\| RTX86IsAmdCpu((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1380	\|\| RTX86IsHygonCpu((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1381	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1382
1383	/* Check three times here to reduce the chance of CPU migration
1384	resulting in false positives with things like the APIC ID. */
1385	uint32_t cSubLeaves;
1386	bool fFinalEcxUnchanged;
1387	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1388	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1389	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1390	{
1391	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1392	{
1393	/* This shouldn't happen. But in case it does, file all
1394	relevant details in the release log. */
1395	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1396	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1397	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1398	{
1399	uint32_t auTmp[4];
1400	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1401	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1402	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1403	}
1404	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1405	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1406	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1407	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1408	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1409	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1410	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1411	}
1412
1413	if (fFinalEcxUnchanged)
1414	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1415
1416	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1417	{
1418	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1419	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1420	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1421	if (RT_FAILURE(rc))
1422	return rc;
1423	}
1424	}
1425	else
1426	{
1427	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1428	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1429	if (RT_FAILURE(rc))
1430	return rc;
1431	}
1432
1433	/* next */
1434	uLeaf++;
1435	}
1436	}
1437	/*
1438	* Special CPUIDs needs special handling as they don't follow the
1439	* leaf count principle used above.
1440	*/
1441	else if (s_aCandidates[iOuter].fSpecial)
1442	{
1443	bool fKeep = false;
1444	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1445	fKeep = true;
1446	else if ( uLeaf == 0x8fffffff
1447	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1448	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1449	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1450	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1451	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1452	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1453	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1454	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1455	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1456	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1457	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1458	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1459	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1460	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1461	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1462	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1463	fKeep = true;
1464	if (fKeep)
1465	{
1466	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1467	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1468	if (RT_FAILURE(rc))
1469	return rc;
1470	}
1471	}
1472	}
1473
1474	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1475	return VINF_SUCCESS;
1476	}
1477
1478
1479	/**
1480	* Determines the method the CPU uses to handle unknown CPUID leaves.
1481	*
1482	* @returns VBox status code.
1483	* @param penmUnknownMethod Where to return the method.
1484	* @param pDefUnknown Where to return default unknown values. This
1485	* will be set, even if the resulting method
1486	* doesn't actually needs it.
1487	*/
1488	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1489	{
1490	uint32_t uLastStd = ASMCpuId_EAX(0);
1491	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1492	if (!RTX86IsValidExtRange(uLastExt))
1493	uLastExt = 0x80000000;
1494
1495	uint32_t auChecks[] =
1496	{
1497	uLastStd + 1,
1498	uLastStd + 5,
1499	uLastStd + 8,
1500	uLastStd + 32,
1501	uLastStd + 251,
1502	uLastExt + 1,
1503	uLastExt + 8,
1504	uLastExt + 15,
1505	uLastExt + 63,
1506	uLastExt + 255,
1507	0x7fbbffcc,
1508	0x833f7872,
1509	0xefff2353,
1510	0x35779456,
1511	0x1ef6d33e,
1512	};
1513
1514	static const uint32_t s_auValues[] =
1515	{
1516	0xa95d2156,
1517	0x00000001,
1518	0x00000002,
1519	0x00000008,
1520	0x00000000,
1521	0x55773399,
1522	0x93401769,
1523	0x12039587,
1524	};
1525
1526	/*
1527	* Simple method, all zeros.
1528	*/
1529	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1530	pDefUnknown->uEax = 0;
1531	pDefUnknown->uEbx = 0;
1532	pDefUnknown->uEcx = 0;
1533	pDefUnknown->uEdx = 0;
1534
1535	/*
1536	* Intel has been observed returning the last standard leaf.
1537	*/
1538	uint32_t auLast[4];
1539	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1540
1541	uint32_t cChecks = RT_ELEMENTS(auChecks);
1542	while (cChecks > 0)
1543	{
1544	uint32_t auCur[4];
1545	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1546	if (memcmp(auCur, auLast, sizeof(auCur)))
1547	break;
1548	cChecks--;
1549	}
1550	if (cChecks == 0)
1551	{
1552	/* Now, what happens when the input changes? Esp. ECX. */
1553	uint32_t cTotal = 0;
1554	uint32_t cSame = 0;
1555	uint32_t cLastWithEcx = 0;
1556	uint32_t cNeither = 0;
1557	uint32_t cValues = RT_ELEMENTS(s_auValues);
1558	while (cValues > 0)
1559	{
1560	uint32_t uValue = s_auValues[cValues - 1];
1561	uint32_t auLastWithEcx[4];
1562	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1563	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1564
1565	cChecks = RT_ELEMENTS(auChecks);
1566	while (cChecks > 0)
1567	{
1568	uint32_t auCur[4];
1569	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1570	if (!memcmp(auCur, auLast, sizeof(auCur)))
1571	{
1572	cSame++;
1573	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1574	cLastWithEcx++;
1575	}
1576	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1577	cLastWithEcx++;
1578	else
1579	cNeither++;
1580	cTotal++;
1581	cChecks--;
1582	}
1583	cValues--;
1584	}
1585
1586	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1587	if (cSame == cTotal)
1588	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1589	else if (cLastWithEcx == cTotal)
1590	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1591	else
1592	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1593	pDefUnknown->uEax = auLast[0];
1594	pDefUnknown->uEbx = auLast[1];
1595	pDefUnknown->uEcx = auLast[2];
1596	pDefUnknown->uEdx = auLast[3];
1597	return VINF_SUCCESS;
1598	}
1599
1600	/*
1601	* Unchanged register values?
1602	*/
1603	cChecks = RT_ELEMENTS(auChecks);
1604	while (cChecks > 0)
1605	{
1606	uint32_t const uLeaf = auChecks[cChecks - 1];
1607	uint32_t cValues = RT_ELEMENTS(s_auValues);
1608	while (cValues > 0)
1609	{
1610	uint32_t uValue = s_auValues[cValues - 1];
1611	uint32_t auCur[4];
1612	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1613	if ( auCur[0] != uLeaf
1614	\|\| auCur[1] != uValue
1615	\|\| auCur[2] != uValue
1616	\|\| auCur[3] != uValue)
1617	break;
1618	cValues--;
1619	}
1620	if (cValues != 0)
1621	break;
1622	cChecks--;
1623	}
1624	if (cChecks == 0)
1625	{
1626	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1627	return VINF_SUCCESS;
1628	}
1629
1630	/*
1631	* Just go with the simple method.
1632	*/
1633	return VINF_SUCCESS;
1634	}
1635
1636	#endif /* RT_ARCH_X86 \|\| RT_ARCH_AMD64 */
1637
1638	/**
1639	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1640	*
1641	* @returns Read only name string.
1642	* @param enmUnknownMethod The method to translate.
1643	*/
1644	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1645	{
1646	switch (enmUnknownMethod)
1647	{
1648	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1649	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1650	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1651	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1652
1653	case CPUMUNKNOWNCPUID_INVALID:
1654	case CPUMUNKNOWNCPUID_END:
1655	case CPUMUNKNOWNCPUID_32BIT_HACK:
1656	break;
1657	}
1658	return "Invalid-unknown-CPUID-method";
1659	}
1660
1661
1662	/**
1663	* Detect the CPU vendor give n the
1664	*
1665	* @returns The vendor.
1666	* @param uEAX EAX from CPUID(0).
1667	* @param uEBX EBX from CPUID(0).
1668	* @param uECX ECX from CPUID(0).
1669	* @param uEDX EDX from CPUID(0).
1670	*/
1671	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1672	{
1673	if (RTX86IsValidStdRange(uEAX))
1674	{
1675	if (RTX86IsAmdCpu(uEBX, uECX, uEDX))
1676	return CPUMCPUVENDOR_AMD;
1677
1678	if (RTX86IsIntelCpu(uEBX, uECX, uEDX))
1679	return CPUMCPUVENDOR_INTEL;
1680
1681	if (RTX86IsViaCentaurCpu(uEBX, uECX, uEDX))
1682	return CPUMCPUVENDOR_VIA;
1683
1684	if (RTX86IsShanghaiCpu(uEBX, uECX, uEDX))
1685	return CPUMCPUVENDOR_SHANGHAI;
1686
1687	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1688	&& uECX == UINT32_C(0x64616574)
1689	&& uEDX == UINT32_C(0x736E4978))
1690	return CPUMCPUVENDOR_CYRIX;
1691
1692	if (RTX86IsHygonCpu(uEBX, uECX, uEDX))
1693	return CPUMCPUVENDOR_HYGON;
1694
1695	/* "Geode by NSC", example: family 5, model 9. */
1696
1697	/** @todo detect the other buggers... */
1698	}
1699
1700	return CPUMCPUVENDOR_UNKNOWN;
1701	}
1702
1703
1704	/**
1705	* Translates a CPU vendor enum value into the corresponding string constant.
1706	*
1707	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1708	* value name. This can be useful when generating code.
1709	*
1710	* @returns Read only name string.
1711	* @param enmVendor The CPU vendor value.
1712	*/
1713	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1714	{
1715	switch (enmVendor)
1716	{
1717	case CPUMCPUVENDOR_INTEL: return "INTEL";
1718	case CPUMCPUVENDOR_AMD: return "AMD";
1719	case CPUMCPUVENDOR_VIA: return "VIA";
1720	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1721	case CPUMCPUVENDOR_SHANGHAI: return "SHANGHAI";
1722	case CPUMCPUVENDOR_HYGON: return "HYGON";
1723	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1724
1725	case CPUMCPUVENDOR_INVALID:
1726	case CPUMCPUVENDOR_32BIT_HACK:
1727	break;
1728	}
1729	return "Invalid-cpu-vendor";
1730	}
1731
1732
1733	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1734	{
1735	/* Could do binary search, doing linear now because I'm lazy. */
1736	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1737	while (cLeaves-- > 0)
1738	{
1739	if (pLeaf->uLeaf == uLeaf)
1740	return pLeaf;
1741	pLeaf++;
1742	}
1743	return NULL;
1744	}
1745
1746
1747	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1748	{
1749	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1750	if ( !pLeaf
1751	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1752	return pLeaf;
1753
1754	/* Linear sub-leaf search. Lazy as usual. */
1755	cLeaves -= pLeaf - paLeaves;
1756	while ( cLeaves-- > 0
1757	&& pLeaf->uLeaf == uLeaf)
1758	{
1759	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1760	return pLeaf;
1761	pLeaf++;
1762	}
1763
1764	return NULL;
1765	}
1766
1767
1768	static void cpumR3ExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, PCPUMFEATURES pFeatures)
1769	{
1770	Assert(pVmxMsrs);
1771	Assert(pFeatures);
1772	Assert(pFeatures->fVmx);
1773
1774	/* Basic information. */
1775	bool const fVmxTrueMsrs = RT_BOOL(pVmxMsrs->u64Basic & VMX_BF_BASIC_TRUE_CTLS_MASK);
1776	{
1777	uint64_t const u64Basic = pVmxMsrs->u64Basic;
1778	pFeatures->fVmxInsOutInfo = RT_BF_GET(u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1779	}
1780
1781	/* Pin-based VM-execution controls. */
1782	{
1783	uint32_t const fPinCtls = fVmxTrueMsrs ? pVmxMsrs->TruePinCtls.n.allowed1 : pVmxMsrs->PinCtls.n.allowed1;
1784	pFeatures->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1785	pFeatures->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1786	pFeatures->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1787	pFeatures->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1788	pFeatures->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1789	}
1790
1791	/* Processor-based VM-execution controls. */
1792	{
1793	uint32_t const fProcCtls = fVmxTrueMsrs ? pVmxMsrs->TrueProcCtls.n.allowed1 : pVmxMsrs->ProcCtls.n.allowed1;
1794	pFeatures->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1795	pFeatures->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1796	pFeatures->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1797	pFeatures->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1798	pFeatures->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1799	pFeatures->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1800	pFeatures->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1801	pFeatures->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1802	pFeatures->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1803	pFeatures->fVmxTertiaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TERTIARY_CTLS);
1804	pFeatures->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1805	pFeatures->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1806	pFeatures->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1807	pFeatures->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1808	pFeatures->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1809	pFeatures->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1810	pFeatures->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1811	pFeatures->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1812	pFeatures->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1813	pFeatures->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1814	pFeatures->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1815	pFeatures->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1816	}
1817
1818	/* Secondary processor-based VM-execution controls. */
1819	{
1820	uint32_t const fProcCtls2 = pFeatures->fVmxSecondaryExecCtls ? pVmxMsrs->ProcCtls2.n.allowed1 : 0;
1821	pFeatures->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1822	pFeatures->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1823	pFeatures->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1824	pFeatures->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1825	pFeatures->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1826	pFeatures->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1827	pFeatures->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1828	pFeatures->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1829	pFeatures->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1830	pFeatures->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1831	pFeatures->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1832	pFeatures->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1833	pFeatures->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1834	pFeatures->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1835	pFeatures->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1836	pFeatures->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1837	pFeatures->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1838	pFeatures->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE);
1839	pFeatures->fVmxConcealVmxFromPt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1840	pFeatures->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1841	pFeatures->fVmxModeBasedExecuteEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1842	pFeatures->fVmxSppEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_SPP_EPT);
1843	pFeatures->fVmxPtEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PT_EPT);
1844	pFeatures->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1845	pFeatures->fVmxUserWaitPause = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1846	pFeatures->fVmxEnclvExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_ENCLV_EXIT);
1847	}
1848
1849	/* Tertiary processor-based VM-execution controls. */
1850	{
1851	uint64_t const fProcCtls3 = pFeatures->fVmxTertiaryExecCtls ? pVmxMsrs->u64ProcCtls3 : 0;
1852	pFeatures->fVmxLoadIwKeyExit = RT_BOOL(fProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT);
1853	}
1854
1855	/* VM-exit controls. */
1856	{
1857	uint32_t const fExitCtls = fVmxTrueMsrs ? pVmxMsrs->TrueExitCtls.n.allowed1 : pVmxMsrs->ExitCtls.n.allowed1;
1858	pFeatures->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1859	pFeatures->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1860	pFeatures->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1861	pFeatures->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1862	pFeatures->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1863	pFeatures->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1864	pFeatures->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1865	pFeatures->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1866	}
1867
1868	/* VM-entry controls. */
1869	{
1870	uint32_t const fEntryCtls = fVmxTrueMsrs ? pVmxMsrs->TrueEntryCtls.n.allowed1 : pVmxMsrs->EntryCtls.n.allowed1;
1871	pFeatures->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1872	pFeatures->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1873	pFeatures->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1874	pFeatures->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1875	}
1876
1877	/* Miscellaneous data. */
1878	{
1879	uint32_t const fMiscData = pVmxMsrs->u64Misc;
1880	pFeatures->fVmxExitSaveEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_SAVE_EFER_LMA);
1881	pFeatures->fVmxPt = RT_BOOL(fMiscData & VMX_MISC_INTEL_PT);
1882	pFeatures->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1883	pFeatures->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1884	}
1885	}
1886
1887
1888	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures)
1889	{
1890	Assert(pMsrs);
1891	RT_ZERO(*pFeatures);
1892	if (cLeaves >= 2)
1893	{
1894	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1895	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1896	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1897	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1898	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1899	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1900
1901	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1902	pStd0Leaf->uEbx,
1903	pStd0Leaf->uEcx,
1904	pStd0Leaf->uEdx);
1905	pFeatures->uFamily = RTX86GetCpuFamily(pStd1Leaf->uEax);
1906	pFeatures->uModel = RTX86GetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1907	pFeatures->uStepping = RTX86GetCpuStepping(pStd1Leaf->uEax);
1908	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1909	pFeatures->uFamily,
1910	pFeatures->uModel,
1911	pFeatures->uStepping);
1912
1913	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1914	if (pExtLeaf8)
1915	{
1916	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1917	pFeatures->cMaxLinearAddrWidth = (pExtLeaf8->uEax >> 8) & 0xff;
1918	}
1919	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1920	{
1921	pFeatures->cMaxPhysAddrWidth = 36;
1922	pFeatures->cMaxLinearAddrWidth = 36;
1923	}
1924	else
1925	{
1926	pFeatures->cMaxPhysAddrWidth = 32;
1927	pFeatures->cMaxLinearAddrWidth = 32;
1928	}
1929
1930	/* Standard features. */
1931	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1932	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1933	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1934	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1935	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1936	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1937	pFeatures->fPge = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PGE);
1938	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1939	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1940	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1941	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1942	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1943	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1944	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1945	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1946	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1947	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1948	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1949	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1950	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1951	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1952	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1953	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1954	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1955	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1956	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1957	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1958	if (pFeatures->fVmx)
1959	cpumR3ExplodeVmxFeatures(&pMsrs->hwvirt.vmx, pFeatures);
1960
1961	/* Structured extended features. */
1962	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1963	if (pSxfLeaf0)
1964	{
1965	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1966	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1967	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1968	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1969	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1970
1971	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1972	pFeatures->fIbrs = pFeatures->fIbpb;
1973	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1974	pFeatures->fFlushCmd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
1975	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1976	pFeatures->fMdsClear = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR);
1977	}
1978
1979	/* MWAIT/MONITOR leaf. */
1980	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1981	if (pMWaitLeaf)
1982	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1983	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1984
1985	/* Extended features. */
1986	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1987	if (pExtLeaf)
1988	{
1989	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1990	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1991	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1992	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1993	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1994	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1995	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1996	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1997	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1998	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1999	}
2000
2001	/* VMX (VMXON, VMCS region and related data structures) physical address width (depends on long-mode). */
2002	pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
2003
2004	if ( pExtLeaf
2005	&& ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
2006	\|\| pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON))
2007	{
2008	/* AMD features. */
2009	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
2010	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
2011	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
2012	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
2013	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
2014	pFeatures->fPge \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PGE);
2015	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
2016	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
2017	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
2018	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
2019	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
2020	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2021	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
2022	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
2023	if (pFeatures->fSvm)
2024	{
2025	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
2026	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
2027	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
2028	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
2029	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
2030	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
2031	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
2032	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
2033	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
2034	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
2035	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
2036	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
2037	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
2038	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
2039	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
2040	pFeatures->fSvmGmet = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_GMET);
2041	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
2042	}
2043	}
2044
2045	/*
2046	* Quirks.
2047	*/
2048	pFeatures->fLeakyFxSR = pExtLeaf
2049	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
2050	&& ( ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
2051	&& pFeatures->uFamily >= 6 /* K7 and up */)
2052	\|\| pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON);
2053
2054	/*
2055	* Max extended (/FPU) state.
2056	*/
2057	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
2058	if (pFeatures->fXSaveRstor)
2059	{
2060	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
2061	if (pXStateLeaf0)
2062	{
2063	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
2064	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
2065	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
2066	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
2067	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
2068	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
2069	{
2070	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
2071
2072	/* (paranoia:) */
2073	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
2074	if ( pXStateLeaf1
2075	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
2076	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
2077	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
2078	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
2079	}
2080	else
2081	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
2082	pFeatures->fXSaveRstor = 0);
2083	}
2084	else
2085	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
2086	pFeatures->fXSaveRstor = 0);
2087	}
2088	}
2089	else
2090	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
2091	return VINF_SUCCESS;
2092	}
2093
2094
2095	/*
2096	*
2097	* Init related code.
2098	* Init related code.
2099	* Init related code.
2100	*
2101	*
2102	*/
2103	#ifndef IN_VBOX_CPU_REPORT
2104
2105
2106	/**
2107	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
2108	*
2109	* This ignores the fSubLeafMask.
2110	*
2111	* @returns Pointer to the matching leaf, or NULL if not found.
2112	* @param pCpum The CPUM instance data.
2113	* @param uLeaf The leaf to locate.
2114	* @param uSubLeaf The subleaf to locate.
2115	*/
2116	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
2117	{
2118	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
2119	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
2120	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
2121	if (iEnd)
2122	{
2123	uint32_t iBegin = 0;
2124	for (;;)
2125	{
2126	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
2127	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
2128	if (uNeedle < uCur)
2129	{
2130	if (i > iBegin)
2131	iEnd = i;
2132	else
2133	break;
2134	}
2135	else if (uNeedle > uCur)
2136	{
2137	if (i + 1 < iEnd)
2138	iBegin = i + 1;
2139	else
2140	break;
2141	}
2142	else
2143	return &paLeaves[i];
2144	}
2145	}
2146	return NULL;
2147	}
2148
2149
2150	/**
2151	* Loads MSR range overrides.
2152	*
2153	* This must be called before the MSR ranges are moved from the normal heap to
2154	* the hyper heap!
2155	*
2156	* @returns VBox status code (VMSetError called).
2157	* @param pVM The cross context VM structure.
2158	* @param pMsrNode The CFGM node with the MSR overrides.
2159	*/
2160	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
2161	{
2162	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2163	{
2164	/*
2165	* Assemble a valid MSR range.
2166	*/
2167	CPUMMSRRANGE MsrRange;
2168	MsrRange.offCpumCpu = 0;
2169	MsrRange.fReserved = 0;
2170
2171	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
2172	if (RT_FAILURE(rc))
2173	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
2174
2175	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
2176	if (RT_FAILURE(rc))
2177	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
2178	MsrRange.szName, rc);
2179
2180	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
2181	if (RT_FAILURE(rc))
2182	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
2183	MsrRange.szName, rc);
2184
2185	char szType[32];
2186	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
2187	if (RT_FAILURE(rc))
2188	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
2189	MsrRange.szName, rc);
2190	if (!RTStrICmp(szType, "FixedValue"))
2191	{
2192	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
2193	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
2194
2195	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
2196	if (RT_FAILURE(rc))
2197	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
2198	MsrRange.szName, rc);
2199
2200	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
2201	if (RT_FAILURE(rc))
2202	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
2203	MsrRange.szName, rc);
2204
2205	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
2206	if (RT_FAILURE(rc))
2207	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
2208	MsrRange.szName, rc);
2209	}
2210	else
2211	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
2212	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
2213
2214	/*
2215	* Insert the range into the table (replaces/splits/shrinks existing
2216	* MSR ranges).
2217	*/
2218	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
2219	&MsrRange);
2220	if (RT_FAILURE(rc))
2221	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
2222	}
2223
2224	return VINF_SUCCESS;
2225	}
2226
2227
2228	/**
2229	* Loads CPUID leaf overrides.
2230	*
2231	* This must be called before the CPUID leaves are moved from the normal
2232	* heap to the hyper heap!
2233	*
2234	* @returns VBox status code (VMSetError called).
2235	* @param pVM The cross context VM structure.
2236	* @param pParentNode The CFGM node with the CPUID leaves.
2237	* @param pszLabel How to label the overrides we're loading.
2238	*/
2239	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2240	{
2241	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2242	{
2243	/*
2244	* Get the leaf and subleaf numbers.
2245	*/
2246	char szName[128];
2247	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2248	if (RT_FAILURE(rc))
2249	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2250
2251	/* The leaf number is either specified directly or thru the node name. */
2252	uint32_t uLeaf;
2253	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2254	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2255	{
2256	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2257	if (rc != VINF_SUCCESS)
2258	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2259	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2260	}
2261	else if (RT_FAILURE(rc))
2262	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2263	pszLabel, szName, rc);
2264
2265	uint32_t uSubLeaf;
2266	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2267	if (RT_FAILURE(rc))
2268	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2269	pszLabel, szName, rc);
2270
2271	uint32_t fSubLeafMask;
2272	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2273	if (RT_FAILURE(rc))
2274	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2275	pszLabel, szName, rc);
2276
2277	/*
2278	* Look up the specified leaf, since the output register values
2279	* defaults to any existing values. This allows overriding a single
2280	* register, without needing to know the other values.
2281	*/
2282	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2283	CPUMCPUIDLEAF Leaf;
2284	if (pLeaf)
2285	Leaf = *pLeaf;
2286	else
2287	RT_ZERO(Leaf);
2288	Leaf.uLeaf = uLeaf;
2289	Leaf.uSubLeaf = uSubLeaf;
2290	Leaf.fSubLeafMask = fSubLeafMask;
2291
2292	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2293	if (RT_FAILURE(rc))
2294	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2295	pszLabel, szName, rc);
2296	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2297	if (RT_FAILURE(rc))
2298	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2299	pszLabel, szName, rc);
2300	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2301	if (RT_FAILURE(rc))
2302	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2303	pszLabel, szName, rc);
2304	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2305	if (RT_FAILURE(rc))
2306	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2307	pszLabel, szName, rc);
2308
2309	/*
2310	* Insert the leaf into the table (replaces existing ones).
2311	*/
2312	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2313	&Leaf);
2314	if (RT_FAILURE(rc))
2315	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2316	}
2317
2318	return VINF_SUCCESS;
2319	}
2320
2321
2322
2323	/**
2324	* Fetches overrides for a CPUID leaf.
2325	*
2326	* @returns VBox status code.
2327	* @param pLeaf The leaf to load the overrides into.
2328	* @param pCfgNode The CFGM node containing the overrides
2329	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2330	* @param iLeaf The CPUID leaf number.
2331	*/
2332	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2333	{
2334	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2335	if (pLeafNode)
2336	{
2337	uint32_t u32;
2338	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2339	if (RT_SUCCESS(rc))
2340	pLeaf->uEax = u32;
2341	else
2342	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2343
2344	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2345	if (RT_SUCCESS(rc))
2346	pLeaf->uEbx = u32;
2347	else
2348	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2349
2350	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2351	if (RT_SUCCESS(rc))
2352	pLeaf->uEcx = u32;
2353	else
2354	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2355
2356	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2357	if (RT_SUCCESS(rc))
2358	pLeaf->uEdx = u32;
2359	else
2360	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2361
2362	}
2363	return VINF_SUCCESS;
2364	}
2365
2366
2367	/**
2368	* Load the overrides for a set of CPUID leaves.
2369	*
2370	* @returns VBox status code.
2371	* @param paLeaves The leaf array.
2372	* @param cLeaves The number of leaves.
2373	* @param uStart The start leaf number.
2374	* @param pCfgNode The CFGM node containing the overrides
2375	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2376	*/
2377	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2378	{
2379	for (uint32_t i = 0; i < cLeaves; i++)
2380	{
2381	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2382	if (RT_FAILURE(rc))
2383	return rc;
2384	}
2385
2386	return VINF_SUCCESS;
2387	}
2388
2389
2390	/**
2391	* Installs the CPUID leaves and explods the data into structures like
2392	* GuestFeatures and CPUMCTX::aoffXState.
2393	*
2394	* @returns VBox status code.
2395	* @param pVM The cross context VM structure.
2396	* @param pCpum The CPUM part of @a VM.
2397	* @param paLeaves The leaves. These will be copied (but not freed).
2398	* @param cLeaves The number of leaves.
2399	* @param pMsrs The MSRs.
2400	*/
2401	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
2402	{
2403	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2404
2405	/*
2406	* Install the CPUID information.
2407	*/
2408	AssertLogRelMsgReturn(cLeaves <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves),
2409	("cLeaves=%u - max %u\n", cLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves)),
2410	VERR_CPUM_IPE_1); /** @todo better status! */
2411	if (paLeaves != pCpum->GuestInfo.aCpuIdLeaves)
2412	memcpy(pCpum->GuestInfo.aCpuIdLeaves, paLeaves, cLeaves * sizeof(paLeaves[0]));
2413	pCpum->GuestInfo.paCpuIdLeavesR3 = pCpum->GuestInfo.aCpuIdLeaves;
2414	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2415
2416	/*
2417	* Update the default CPUID leaf if necessary.
2418	*/
2419	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2420	{
2421	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2422	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2423	{
2424	/* We don't use CPUID(0).eax here because of the NT hack that only
2425	changes that value without actually removing any leaves. */
2426	uint32_t i = 0;
2427	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2428	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2429	{
2430	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2431	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2432	i++;
2433	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2434	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2435	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2436	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2437	}
2438	break;
2439	}
2440	default:
2441	break;
2442	}
2443
2444	/*
2445	* Explode the guest CPU features.
2446	*/
2447	int rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
2448	&pCpum->GuestFeatures);
2449	AssertLogRelRCReturn(rc, rc);
2450
2451	/*
2452	* Adjust the scalable bus frequency according to the CPUID information
2453	* we're now using.
2454	*/
2455	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2456	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2457	? UINT64_C(100000000) /* 100MHz */
2458	: UINT64_C(133333333); /* 133MHz */
2459
2460	/*
2461	* Populate the legacy arrays. Currently used for everything, later only
2462	* for patch manager.
2463	*/
2464	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2465	{
2466	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2467	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2468	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2469	};
2470	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2471	{
2472	uint32_t cLeft = aOldRanges[i].cCpuIds;
2473	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2474	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2475	while (cLeft-- > 0)
2476	{
2477	uLeaf--;
2478	pLegacyLeaf--;
2479
2480	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2481	if (pLeaf)
2482	{
2483	pLegacyLeaf->uEax = pLeaf->uEax;
2484	pLegacyLeaf->uEbx = pLeaf->uEbx;
2485	pLegacyLeaf->uEcx = pLeaf->uEcx;
2486	pLegacyLeaf->uEdx = pLeaf->uEdx;
2487	}
2488	else
2489	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2490	}
2491	}
2492
2493	/*
2494	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2495	*/
2496	PVMCPU pVCpu0 = pVM->apCpusR3[0];
2497	AssertCompile(sizeof(pVCpu0->cpum.s.Guest.abXState) == CPUM_MAX_XSAVE_AREA_SIZE);
2498	memset(&pVCpu0->cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2499	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2500	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2501	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2502	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2503	{
2504	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2505	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2506	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2507	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2508	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2509	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2510	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2511	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2512	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2513	pCpum->GuestFeatures.cbMaxExtendedState),
2514	VERR_CPUM_IPE_1);
2515	pVCpu0->cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2516	}
2517
2518	/* Copy the CPU #0 data to the other CPUs. */
2519	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
2520	{
2521	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2522	memcpy(&pVCpu->cpum.s.Guest.aoffXState[0], &pVCpu0->cpum.s.Guest.aoffXState[0], sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2523	}
2524
2525	return VINF_SUCCESS;
2526	}
2527
2528
2529	/** @name Instruction Set Extension Options
2530	* @{ */
2531	/** Configuration option type (extended boolean, really). */
2532	typedef uint8_t CPUMISAEXTCFG;
2533	/** Always disable the extension. */
2534	#define CPUMISAEXTCFG_DISABLED false
2535	/** Enable the extension if it's supported by the host CPU. */
2536	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2537	/** Enable the extension if it's supported by the host CPU, but don't let
2538	* the portable CPUID feature disable it. */
2539	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2540	/** Always enable the extension. */
2541	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2542	/** @} */
2543
2544	/**
2545	* CPUID Configuration (from CFGM).
2546	*
2547	* @remarks The members aren't document since we would only be duplicating the
2548	* \@cfgm entries in cpumR3CpuIdReadConfig.
2549	*/
2550	typedef struct CPUMCPUIDCONFIG
2551	{
2552	bool fNt4LeafLimit;
2553	bool fInvariantTsc;
2554	bool fForceVme;
2555	bool fNestedHWVirt;
2556
2557	CPUMISAEXTCFG enmCmpXchg16b;
2558	CPUMISAEXTCFG enmMonitor;
2559	CPUMISAEXTCFG enmMWaitExtensions;
2560	CPUMISAEXTCFG enmSse41;
2561	CPUMISAEXTCFG enmSse42;
2562	CPUMISAEXTCFG enmAvx;
2563	CPUMISAEXTCFG enmAvx2;
2564	CPUMISAEXTCFG enmXSave;
2565	CPUMISAEXTCFG enmAesNi;
2566	CPUMISAEXTCFG enmPClMul;
2567	CPUMISAEXTCFG enmPopCnt;
2568	CPUMISAEXTCFG enmMovBe;
2569	CPUMISAEXTCFG enmRdRand;
2570	CPUMISAEXTCFG enmRdSeed;
2571	CPUMISAEXTCFG enmCLFlushOpt;
2572	CPUMISAEXTCFG enmFsGsBase;
2573	CPUMISAEXTCFG enmPcid;
2574	CPUMISAEXTCFG enmInvpcid;
2575	CPUMISAEXTCFG enmFlushCmdMsr;
2576	CPUMISAEXTCFG enmMdsClear;
2577	CPUMISAEXTCFG enmArchCapMsr;
2578
2579	CPUMISAEXTCFG enmAbm;
2580	CPUMISAEXTCFG enmSse4A;
2581	CPUMISAEXTCFG enmMisAlnSse;
2582	CPUMISAEXTCFG enm3dNowPrf;
2583	CPUMISAEXTCFG enmAmdExtMmx;
2584
2585	uint32_t uMaxStdLeaf;
2586	uint32_t uMaxExtLeaf;
2587	uint32_t uMaxCentaurLeaf;
2588	uint32_t uMaxIntelFamilyModelStep;
2589	char szCpuName[128];
2590	} CPUMCPUIDCONFIG;
2591	/** Pointer to CPUID config (from CFGM). */
2592	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2593
2594
2595	/**
2596	* Mini CPU selection support for making Mac OS X happy.
2597	*
2598	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2599	*
2600	* @param pCpum The CPUM instance data.
2601	* @param pConfig The CPUID configuration we've read from CFGM.
2602	*/
2603	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2604	{
2605	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2606	{
2607	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2608	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(RTX86GetCpuStepping(pStdFeatureLeaf->uEax),
2609	RTX86GetCpuModelIntel(pStdFeatureLeaf->uEax),
2610	RTX86GetCpuFamily(pStdFeatureLeaf->uEax),
2611	0);
2612	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2613	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2614	{
2615	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2616	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2617	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2618	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2619	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2620	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2621	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2622	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2623	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2624	pStdFeatureLeaf->uEax = uNew;
2625	}
2626	}
2627	}
2628
2629
2630
2631	/**
2632	* Limit it the number of entries, zapping the remainder.
2633	*
2634	* The limits are masking off stuff about power saving and similar, this
2635	* is perhaps a bit crudely done as there is probably some relatively harmless
2636	* info too in these leaves (like words about having a constant TSC).
2637	*
2638	* @param pCpum The CPUM instance data.
2639	* @param pConfig The CPUID configuration we've read from CFGM.
2640	*/
2641	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2642	{
2643	/*
2644	* Standard leaves.
2645	*/
2646	uint32_t uSubLeaf = 0;
2647	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2648	if (pCurLeaf)
2649	{
2650	uint32_t uLimit = pCurLeaf->uEax;
2651	if (uLimit <= UINT32_C(0x000fffff))
2652	{
2653	if (uLimit > pConfig->uMaxStdLeaf)
2654	{
2655	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2656	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2657	uLimit + 1, UINT32_C(0x000fffff));
2658	}
2659
2660	/* NT4 hack, no zapping of extra leaves here. */
2661	if (pConfig->fNt4LeafLimit && uLimit > 3)
2662	pCurLeaf->uEax = uLimit = 3;
2663
2664	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2665	pCurLeaf->uEax = uLimit;
2666	}
2667	else
2668	{
2669	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2670	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2671	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2672	}
2673	}
2674
2675	/*
2676	* Extended leaves.
2677	*/
2678	uSubLeaf = 0;
2679	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2680	if (pCurLeaf)
2681	{
2682	uint32_t uLimit = pCurLeaf->uEax;
2683	if ( uLimit >= UINT32_C(0x80000000)
2684	&& uLimit <= UINT32_C(0x800fffff))
2685	{
2686	if (uLimit > pConfig->uMaxExtLeaf)
2687	{
2688	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2689	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2690	uLimit + 1, UINT32_C(0x800fffff));
2691	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2692	pCurLeaf->uEax = uLimit;
2693	}
2694	}
2695	else
2696	{
2697	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2698	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2699	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2700	}
2701	}
2702
2703	/*
2704	* Centaur leaves (VIA).
2705	*/
2706	uSubLeaf = 0;
2707	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2708	if (pCurLeaf)
2709	{
2710	uint32_t uLimit = pCurLeaf->uEax;
2711	if ( uLimit >= UINT32_C(0xc0000000)
2712	&& uLimit <= UINT32_C(0xc00fffff))
2713	{
2714	if (uLimit > pConfig->uMaxCentaurLeaf)
2715	{
2716	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2717	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2718	uLimit + 1, UINT32_C(0xcfffffff));
2719	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2720	pCurLeaf->uEax = uLimit;
2721	}
2722	}
2723	else
2724	{
2725	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2726	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2727	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2728	}
2729	}
2730	}
2731
2732
2733	/**
2734	* Clears a CPUID leaf and all sub-leaves (to zero).
2735	*
2736	* @param pCpum The CPUM instance data.
2737	* @param uLeaf The leaf to clear.
2738	*/
2739	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2740	{
2741	uint32_t uSubLeaf = 0;
2742	PCPUMCPUIDLEAF pCurLeaf;
2743	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2744	{
2745	pCurLeaf->uEax = 0;
2746	pCurLeaf->uEbx = 0;
2747	pCurLeaf->uEcx = 0;
2748	pCurLeaf->uEdx = 0;
2749	uSubLeaf++;
2750	}
2751	}
2752
2753
2754	/**
2755	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2756	* the given leaf.
2757	*
2758	* @returns pLeaf.
2759	* @param pCpum The CPUM instance data.
2760	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2761	*/
2762	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2763	{
2764	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2765	if (pLeaf->fSubLeafMask != 0)
2766	{
2767	/*
2768	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2769	* Log everything while we're at it.
2770	*/
2771	LogRel(("CPUM:\n"
2772	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2773	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2774	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2775	for (;;)
2776	{
2777	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2778	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2779	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2780	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2781	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2782	break;
2783	pSubLeaf++;
2784	}
2785	LogRel(("CPUM:\n"));
2786
2787	/*
2788	* Remove the offending sub-leaves.
2789	*/
2790	if (pSubLeaf != pLeaf)
2791	{
2792	if (pSubLeaf != pLast)
2793	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2794	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2795	}
2796
2797	/*
2798	* Convert the first sub-leaf into a single leaf.
2799	*/
2800	pLeaf->uSubLeaf = 0;
2801	pLeaf->fSubLeafMask = 0;
2802	}
2803	return pLeaf;
2804	}
2805
2806
2807	/**
2808	* Sanitizes and adjust the CPUID leaves.
2809	*
2810	* Drop features that aren't virtualized (or virtualizable). Adjust information
2811	* and capabilities to fit the virtualized hardware. Remove information the
2812	* guest shouldn't have (because it's wrong in the virtual world or because it
2813	* gives away host details) or that we don't have documentation for and no idea
2814	* what means.
2815	*
2816	* @returns VBox status code.
2817	* @param pVM The cross context VM structure (for cCpus).
2818	* @param pCpum The CPUM instance data.
2819	* @param pConfig The CPUID configuration we've read from CFGM.
2820	*/
2821	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2822	{
2823	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2824	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2825	{ \
2826	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2827	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2828	}
2829	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2830	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2831	{ \
2832	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2833	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2834	}
2835	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2836	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2837	&& ((a_pLeafReg) & (fBitMask)) \
2838	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2839	{ \
2840	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2841	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2842	}
2843	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2844
2845	/* The CPUID entries we start with here isn't necessarily the ones of the host, so we
2846	must consult HostFeatures when processing CPUMISAEXTCFG variables. */
2847	PCCPUMFEATURES pHstFeat = &pCpum->HostFeatures;
2848	#define PASSTHRU_FEATURE(enmConfig, fHostFeature, fConst) \
2849	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) ? (fConst) : 0)
2850	#define PASSTHRU_FEATURE_EX(enmConfig, fHostFeature, fAndExpr, fConst) \
2851	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) && (fAndExpr) ? (fConst) : 0)
2852	#define PASSTHRU_FEATURE_TODO(enmConfig, fConst) ((enmConfig) ? (fConst) : 0)
2853
2854	/* Cpuid 1:
2855	* EAX: CPU model, family and stepping.
2856	*
2857	* ECX + EDX: Supported features. Only report features we can support.
2858	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2859	* options may require adjusting (i.e. stripping what was enabled).
2860	*
2861	* EBX: Branding, CLFLUSH line size, logical processors per package and
2862	* initial APIC ID.
2863	*/
2864	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2865	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2866	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2867
2868	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2869	\| X86_CPUID_FEATURE_EDX_VME
2870	\| X86_CPUID_FEATURE_EDX_DE
2871	\| X86_CPUID_FEATURE_EDX_PSE
2872	\| X86_CPUID_FEATURE_EDX_TSC
2873	\| X86_CPUID_FEATURE_EDX_MSR
2874	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2875	\| X86_CPUID_FEATURE_EDX_MCE
2876	\| X86_CPUID_FEATURE_EDX_CX8
2877	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2878	//\| RT_BIT_32(10) - not defined
2879	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2880	//\| X86_CPUID_FEATURE_EDX_SEP
2881	\| X86_CPUID_FEATURE_EDX_MTRR
2882	\| X86_CPUID_FEATURE_EDX_PGE
2883	\| X86_CPUID_FEATURE_EDX_MCA
2884	\| X86_CPUID_FEATURE_EDX_CMOV
2885	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2886	\| X86_CPUID_FEATURE_EDX_PSE36
2887	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2888	\| X86_CPUID_FEATURE_EDX_CLFSH
2889	//\| RT_BIT_32(20) - not defined
2890	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2891	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2892	\| X86_CPUID_FEATURE_EDX_MMX
2893	\| X86_CPUID_FEATURE_EDX_FXSR
2894	\| X86_CPUID_FEATURE_EDX_SSE
2895	\| X86_CPUID_FEATURE_EDX_SSE2
2896	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2897	\| X86_CPUID_FEATURE_EDX_HTT
2898	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2899	//\| RT_BIT_32(30) - not defined
2900	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2901	;
2902	pStdFeatureLeaf->uEcx &= X86_CPUID_FEATURE_ECX_SSE3
2903	\| PASSTHRU_FEATURE_TODO(pConfig->enmPClMul, X86_CPUID_FEATURE_ECX_PCLMUL)
2904	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2905	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2906	\| PASSTHRU_FEATURE_EX(pConfig->enmMonitor, pHstFeat->fMonitorMWait, pVM->cCpus == 1, X86_CPUID_FEATURE_ECX_MONITOR)
2907	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2908	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
2909	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2910	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2911	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2912	\| X86_CPUID_FEATURE_ECX_SSSE3
2913	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2914	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2915	\| PASSTHRU_FEATURE(pConfig->enmCmpXchg16b, pHstFeat->fMovCmpXchg16b, X86_CPUID_FEATURE_ECX_CX16)
2916	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2917	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2918	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2919	\| PASSTHRU_FEATURE(pConfig->enmPcid, pHstFeat->fPcid, X86_CPUID_FEATURE_ECX_PCID)
2920	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2921	\| PASSTHRU_FEATURE(pConfig->enmSse41, pHstFeat->fSse41, X86_CPUID_FEATURE_ECX_SSE4_1)
2922	\| PASSTHRU_FEATURE(pConfig->enmSse42, pHstFeat->fSse42, X86_CPUID_FEATURE_ECX_SSE4_2)
2923	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2924	\| PASSTHRU_FEATURE_TODO(pConfig->enmMovBe, X86_CPUID_FEATURE_ECX_MOVBE)
2925	\| PASSTHRU_FEATURE_TODO(pConfig->enmPopCnt, X86_CPUID_FEATURE_ECX_POPCNT)
2926	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2927	\| PASSTHRU_FEATURE_TODO(pConfig->enmAesNi, X86_CPUID_FEATURE_ECX_AES)
2928	\| PASSTHRU_FEATURE(pConfig->enmXSave, pHstFeat->fXSaveRstor, X86_CPUID_FEATURE_ECX_XSAVE)
2929	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2930	\| PASSTHRU_FEATURE(pConfig->enmAvx, pHstFeat->fAvx, X86_CPUID_FEATURE_ECX_AVX)
2931	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2932	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdRand, X86_CPUID_FEATURE_ECX_RDRAND)
2933	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2934	;
2935
2936	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2937	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2938	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2939	{
2940	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2941	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2942	}
2943
2944	if (pCpum->u8PortableCpuIdLevel > 0)
2945	{
2946	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2947	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2948	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2949	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2950	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2951	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2952	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2953	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
2954	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2955	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2956	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2957	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2958	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2959	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2960	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2961	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2962	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2963	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2964	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2965	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2966
2967	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2968	\| X86_CPUID_FEATURE_EDX_PSN
2969	\| X86_CPUID_FEATURE_EDX_DS
2970	\| X86_CPUID_FEATURE_EDX_ACPI
2971	\| X86_CPUID_FEATURE_EDX_SS
2972	\| X86_CPUID_FEATURE_EDX_TM
2973	\| X86_CPUID_FEATURE_EDX_PBE
2974	)));
2975	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2976	\| X86_CPUID_FEATURE_ECX_CPLDS
2977	\| X86_CPUID_FEATURE_ECX_AES
2978	\| X86_CPUID_FEATURE_ECX_VMX
2979	\| X86_CPUID_FEATURE_ECX_SMX
2980	\| X86_CPUID_FEATURE_ECX_EST
2981	\| X86_CPUID_FEATURE_ECX_TM2
2982	\| X86_CPUID_FEATURE_ECX_CNTXID
2983	\| X86_CPUID_FEATURE_ECX_FMA
2984	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2985	\| X86_CPUID_FEATURE_ECX_PDCM
2986	\| X86_CPUID_FEATURE_ECX_DCA
2987	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2988	)));
2989	}
2990
2991	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2992	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2993
2994	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2995	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2996	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2997	*/
2998	#ifdef VBOX_WITH_MULTI_CORE
2999	if (pVM->cCpus > 1)
3000	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
3001	#endif
3002	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
3003	{
3004	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
3005	core times the number of CPU cores per processor */
3006	#ifdef VBOX_WITH_MULTI_CORE
3007	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
3008	#else
3009	/* Single logical processor in a package. */
3010	pStdFeatureLeaf->uEbx \|= (1 << 16);
3011	#endif
3012	}
3013
3014	uint32_t uMicrocodeRev;
3015	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
3016	if (RT_SUCCESS(rc))
3017	{
3018	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
3019	}
3020	else
3021	{
3022	uMicrocodeRev = 0;
3023	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
3024	}
3025
3026	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
3027	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
3028	*/
3029	if ( ( pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen
3030	/** @todo The following ASSUMES that Hygon uses the same version numbering
3031	* as AMD and that they shipped buggy firmware. */
3032	\|\| pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Hygon_Dhyana)
3033	&& uMicrocodeRev < 0x8001126
3034	&& !pConfig->fForceVme)
3035	{
3036	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
3037	LogRel(("CPUM: Zen VME workaround engaged\n"));
3038	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
3039	}
3040
3041	/* Force standard feature bits. */
3042	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
3043	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
3044	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
3045	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
3046	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
3047	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
3048	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3049	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
3050	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3051	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
3052	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
3053	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
3054	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3055	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
3056	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
3057	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
3058	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
3059	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
3060	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3061	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
3062	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
3063	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
3064
3065	pStdFeatureLeaf = NULL; /* Must refetch! */
3066
3067	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
3068	* AMD:
3069	* EAX: CPU model, family and stepping.
3070	*
3071	* ECX + EDX: Supported features. Only report features we can support.
3072	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3073	* options may require adjusting (i.e. stripping what was enabled).
3074	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
3075	*
3076	* EBX: Branding ID and package type (or reserved).
3077	*
3078	* Intel and probably most others:
3079	* EAX: 0
3080	* EBX: 0
3081	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
3082	*/
3083	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3084	if (pExtFeatureLeaf)
3085	{
3086	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
3087
3088	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
3089	\| X86_CPUID_AMD_FEATURE_EDX_VME
3090	\| X86_CPUID_AMD_FEATURE_EDX_DE
3091	\| X86_CPUID_AMD_FEATURE_EDX_PSE
3092	\| X86_CPUID_AMD_FEATURE_EDX_TSC
3093	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
3094	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
3095	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
3096	\| X86_CPUID_AMD_FEATURE_EDX_CX8
3097	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
3098	//\| RT_BIT_32(10) - reserved
3099	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
3100	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
3101	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3102	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
3103	\| X86_CPUID_AMD_FEATURE_EDX_PGE
3104	\| X86_CPUID_AMD_FEATURE_EDX_MCA
3105	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
3106	\| X86_CPUID_AMD_FEATURE_EDX_PAT
3107	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
3108	//\| RT_BIT_32(18) - reserved
3109	//\| RT_BIT_32(19) - reserved
3110	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
3111	//\| RT_BIT_32(21) - reserved
3112	\| PASSTHRU_FEATURE(pConfig->enmAmdExtMmx, pHstFeat->fAmdMmxExts, X86_CPUID_AMD_FEATURE_EDX_AXMMX)
3113	\| X86_CPUID_AMD_FEATURE_EDX_MMX
3114	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
3115	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
3116	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3117	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
3118	//\| RT_BIT_32(28) - reserved
3119	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
3120	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
3121	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
3122	;
3123	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
3124	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
3125	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
3126	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3127	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
3128	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
3129	\| PASSTHRU_FEATURE_TODO(pConfig->enmAbm, X86_CPUID_AMD_FEATURE_ECX_ABM)
3130	\| PASSTHRU_FEATURE_TODO(pConfig->enmSse4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A)
3131	\| PASSTHRU_FEATURE_TODO(pConfig->enmMisAlnSse, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE)
3132	\| PASSTHRU_FEATURE(pConfig->enm3dNowPrf, pHstFeat->f3DNowPrefetch, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
3133	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3134	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
3135	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
3136	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3137	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
3138	//\| RT_BIT_32(14) - reserved
3139	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
3140	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
3141	//\| RT_BIT_32(17) - reserved
3142	//\| RT_BIT_32(18) - reserved
3143	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
3144	//\| RT_BIT_32(20) - reserved
3145	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
3146	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
3147	//\| RT_BIT_32(23) - reserved
3148	//\| RT_BIT_32(24) - reserved
3149	//\| RT_BIT_32(25) - reserved
3150	//\| RT_BIT_32(26) - reserved
3151	//\| RT_BIT_32(27) - reserved
3152	//\| RT_BIT_32(28) - reserved
3153	//\| RT_BIT_32(29) - reserved
3154	//\| RT_BIT_32(30) - reserved
3155	//\| RT_BIT_32(31) - reserved
3156	;
3157	#ifdef VBOX_WITH_MULTI_CORE
3158	if ( pVM->cCpus > 1
3159	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3160	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3161	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
3162	#endif
3163
3164	if (pCpum->u8PortableCpuIdLevel > 0)
3165	{
3166	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
3167	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
3168	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
3169	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
3170	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
3171	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
3172	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
3173	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
3174	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
3175	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
3176	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
3177	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
3178	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
3179	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
3180	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
3181	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
3182
3183	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
3184	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3185	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3186	\| X86_CPUID_AMD_FEATURE_ECX_IBS
3187	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3188	\| X86_CPUID_AMD_FEATURE_ECX_WDT
3189	\| X86_CPUID_AMD_FEATURE_ECX_LWP
3190	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
3191	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
3192	\| UINT32_C(0xff964000)
3193	)));
3194	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
3195	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3196	\| RT_BIT(18)
3197	\| RT_BIT(19)
3198	\| RT_BIT(21)
3199	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
3200	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3201	\| RT_BIT(28)
3202	)));
3203	}
3204
3205	/* Force extended feature bits. */
3206	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
3207	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
3208	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
3209	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
3210	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
3211	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
3212	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
3213	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
3214	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3215	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
3216	}
3217	pExtFeatureLeaf = NULL; /* Must refetch! */
3218
3219
3220	/* Cpuid 2:
3221	* Intel: (Nondeterministic) Cache and TLB information
3222	* AMD: Reserved
3223	* VIA: Reserved
3224	* Safe to expose.
3225	*/
3226	uint32_t uSubLeaf = 0;
3227	PCPUMCPUIDLEAF pCurLeaf;
3228	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
3229	{
3230	if ((pCurLeaf->uEax & 0xff) > 1)
3231	{
3232	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
3233	pCurLeaf->uEax &= UINT32_C(0xffffff01);
3234	}
3235	uSubLeaf++;
3236	}
3237
3238	/* Cpuid 3:
3239	* Intel: EAX, EBX - reserved (transmeta uses these)
3240	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3241	* AMD: Reserved
3242	* VIA: Reserved
3243	* Safe to expose
3244	*/
3245	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3246	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3247	{
3248	uSubLeaf = 0;
3249	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3250	{
3251	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3252	if (pCpum->u8PortableCpuIdLevel > 0)
3253	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3254	uSubLeaf++;
3255	}
3256	}
3257
3258	/* Cpuid 4 + ECX:
3259	* Intel: Deterministic Cache Parameters Leaf.
3260	* AMD: Reserved
3261	* VIA: Reserved
3262	* Safe to expose, except for EAX:
3263	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3264	* Bits 31-26: Maximum number of processor cores in this physical package**
3265	* Note: These SMP values are constant regardless of ECX
3266	*/
3267	uSubLeaf = 0;
3268	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3269	{
3270	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3271	#ifdef VBOX_WITH_MULTI_CORE
3272	if ( pVM->cCpus > 1
3273	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3274	{
3275	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3276	/* One logical processor with possibly multiple cores. */
3277	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3278	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3279	}
3280	#endif
3281	uSubLeaf++;
3282	}
3283
3284	/* Cpuid 5: Monitor/mwait Leaf
3285	* Intel: ECX, EDX - reserved
3286	* EAX, EBX - Smallest and largest monitor line size
3287	* AMD: EDX - reserved
3288	* EAX, EBX - Smallest and largest monitor line size
3289	* ECX - extensions (ignored for now)
3290	* VIA: Reserved
3291	* Safe to expose
3292	*/
3293	uSubLeaf = 0;
3294	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3295	{
3296	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3297	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3298	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3299
3300	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3301	if (pConfig->enmMWaitExtensions)
3302	{
3303	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3304	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3305	it shall be part of our power management virtualization model */
3306	#if 0
3307	/* MWAIT sub C-states */
3308	pCurLeaf->uEdx =
3309	(0 << 0) /* 0 in C0 */ \|
3310	(2 << 4) /* 2 in C1 */ \|
3311	(2 << 8) /* 2 in C2 */ \|
3312	(2 << 12) /* 2 in C3 */ \|
3313	(0 << 16) /* 0 in C4 */
3314	;
3315	#endif
3316	}
3317	else
3318	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3319	uSubLeaf++;
3320	}
3321
3322	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3323	* Intel: Various stuff.
3324	* AMD: EAX, EBX, EDX - reserved.
3325	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3326	* present. Same as intel.
3327	* VIA: ??
3328	*
3329	* We clear everything here for now.
3330	*/
3331	cpumR3CpuIdZeroLeaf(pCpum, 6);
3332
3333	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3334	* EAX: Number of sub leaves.
3335	* EBX+ECX+EDX: Feature flags
3336	*
3337	* We only have documentation for one sub-leaf, so clear all other (no need
3338	* to remove them as such, just set them to zero).
3339	*
3340	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3341	* options may require adjusting (i.e. stripping what was enabled).
3342	*/
3343	uSubLeaf = 0;
3344	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3345	{
3346	switch (uSubLeaf)
3347	{
3348	case 0:
3349	{
3350	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3351	pCurLeaf->uEbx &= 0
3352	\| PASSTHRU_FEATURE(pConfig->enmFsGsBase, pHstFeat->fFsGsBase, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE)
3353	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3354	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3355	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3356	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3357	\| PASSTHRU_FEATURE(pConfig->enmAvx2, pHstFeat->fAvx2, X86_CPUID_STEXT_FEATURE_EBX_AVX2)
3358	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3359	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3360	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3361	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3362	\| PASSTHRU_FEATURE(pConfig->enmInvpcid, pHstFeat->fInvpcid, X86_CPUID_STEXT_FEATURE_EBX_INVPCID)
3363	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3364	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3365	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3366	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3367	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3368	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3369	//\| RT_BIT(17) - reserved
3370	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdSeed, X86_CPUID_STEXT_FEATURE_EBX_RDSEED)
3371	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3372	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3373	//\| RT_BIT(21) - reserved
3374	//\| RT_BIT(22) - reserved
3375	\| PASSTHRU_FEATURE(pConfig->enmCLFlushOpt, pHstFeat->fClFlushOpt, X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT)
3376	//\| RT_BIT(24) - reserved
3377	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3378	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3379	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3380	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3381	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3382	//\| RT_BIT(30) - reserved
3383	//\| RT_BIT(31) - reserved
3384	;
3385	pCurLeaf->uEcx &= 0
3386	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3387	;
3388	pCurLeaf->uEdx &= 0
3389	\| PASSTHRU_FEATURE(pConfig->enmMdsClear, pHstFeat->fMdsClear, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR)
3390	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3391	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3392	\| PASSTHRU_FEATURE(pConfig->enmFlushCmdMsr, pHstFeat->fFlushCmd, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD)
3393	\| PASSTHRU_FEATURE(pConfig->enmArchCapMsr, pHstFeat->fArchCap, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
3394	;
3395
3396	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3397	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3398	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3399	{
3400	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3401	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3402	}
3403
3404	if (pCpum->u8PortableCpuIdLevel > 0)
3405	{
3406	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3407	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3408	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3409	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3410	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3411	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3412	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3413	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3414	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3415	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3416	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3417	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3418	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3419	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3420	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3421	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
3422	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
3423	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
3424	}
3425
3426	/* Dependencies. */
3427	if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
3428	pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3429
3430	/* Force standard feature bits. */
3431	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3432	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3433	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3434	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3435	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3436	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3437	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3438	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3439	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3440	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3441	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3442	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
3443	if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
3444	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3445	if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3446	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
3447	break;
3448	}
3449
3450	default:
3451	/* Invalid index, all values are zero. */
3452	pCurLeaf->uEax = 0;
3453	pCurLeaf->uEbx = 0;
3454	pCurLeaf->uEcx = 0;
3455	pCurLeaf->uEdx = 0;
3456	break;
3457	}
3458	uSubLeaf++;
3459	}
3460
3461	/* Cpuid 8: Marked as reserved by Intel and AMD.
3462	* We zero this since we don't know what it may have been used for.
3463	*/
3464	cpumR3CpuIdZeroLeaf(pCpum, 8);
3465
3466	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3467	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3468	* EBX, ECX, EDX - reserved.
3469	* AMD: Reserved
3470	* VIA: ??
3471	*
3472	* We zero this.
3473	*/
3474	cpumR3CpuIdZeroLeaf(pCpum, 9);
3475
3476	/* Cpuid 0xa: Architectural Performance Monitor Features
3477	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3478	* EBX, ECX, EDX - reserved.
3479	* AMD: Reserved
3480	* VIA: ??
3481	*
3482	* We zero this, for now at least.
3483	*/
3484	cpumR3CpuIdZeroLeaf(pCpum, 10);
3485
3486	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3487	* Intel: EAX - APCI ID shift right for next level.
3488	* EBX - Factory configured cores/threads at this level.
3489	* ECX - Level number (same as input) and level type (1,2,0).
3490	* EDX - Extended initial APIC ID.
3491	* AMD: Reserved
3492	* VIA: ??
3493	*/
3494	uSubLeaf = 0;
3495	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3496	{
3497	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3498	{
3499	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3500	if (bLevelType == 1)
3501	{
3502	/* Thread level - we don't do threads at the moment. */
3503	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3504	pCurLeaf->uEbx = 1;
3505	}
3506	else if (bLevelType == 2)
3507	{
3508	/* Core level. */
3509	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3510	#ifdef VBOX_WITH_MULTI_CORE
3511	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3512	pCurLeaf->uEax++;
3513	#endif
3514	pCurLeaf->uEbx = pVM->cCpus;
3515	}
3516	else
3517	{
3518	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3519	pCurLeaf->uEax = 0;
3520	pCurLeaf->uEbx = 0;
3521	pCurLeaf->uEcx = 0;
3522	}
3523	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3524	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3525	}
3526	else
3527	{
3528	pCurLeaf->uEax = 0;
3529	pCurLeaf->uEbx = 0;
3530	pCurLeaf->uEcx = 0;
3531	pCurLeaf->uEdx = 0;
3532	}
3533	uSubLeaf++;
3534	}
3535
3536	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3537	* We zero this since we don't know what it may have been used for.
3538	*/
3539	cpumR3CpuIdZeroLeaf(pCpum, 12);
3540
3541	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3542	* ECX=0: EAX - Valid bits in XCR0[31:0].
3543	* EBX - Maximum state size as per current XCR0 value.
3544	* ECX - Maximum state size for all supported features.
3545	* EDX - Valid bits in XCR0[63:32].
3546	* ECX=1: EAX - Various X-features.
3547	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3548	* ECX - Valid bits in IA32_XSS[31:0].
3549	* EDX - Valid bits in IA32_XSS[63:32].
3550	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3551	* if the bit invalid all four registers are set to zero.
3552	* EAX - The state size for this feature.
3553	* EBX - The state byte offset of this feature.
3554	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3555	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3556	*
3557	* Clear them all as we don't currently implement extended CPU state.
3558	*/
3559	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3560	uint64_t fGuestXcr0Mask = 0;
3561	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3562	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3563	{
3564	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3565	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3566	fGuestXcr0Mask \|= XSAVE_C_YMM;
3567	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3568	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3569	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3570	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3571
3572	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3573	}
3574	pStdFeatureLeaf = NULL;
3575	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3576
3577	/* Work the sub-leaves. */
3578	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3579	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3580	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3581	{
3582	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3583	if (pCurLeaf)
3584	{
3585	if (fGuestXcr0Mask)
3586	{
3587	switch (uSubLeaf)
3588	{
3589	case 0:
3590	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3591	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3592	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3593	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3594	VERR_CPUM_IPE_1);
3595	cbXSaveMaxActual = pCurLeaf->uEcx;
3596	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3597	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3598	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3599	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3600	VERR_CPUM_IPE_2);
3601	continue;
3602	case 1:
3603	pCurLeaf->uEax &= 0;
3604	pCurLeaf->uEcx &= 0;
3605	pCurLeaf->uEdx &= 0;
3606	/** @todo what about checking ebx? */
3607	continue;
3608	default:
3609	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3610	{
3611	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3612	&& pCurLeaf->uEax > 0
3613	&& pCurLeaf->uEbx < cbXSaveMaxActual
3614	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3615	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3616	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3617	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3618	VERR_CPUM_IPE_2);
3619	AssertLogRel(!(pCurLeaf->uEcx & 1));
3620	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3621	pCurLeaf->uEdx = 0; /* it's reserved... */
3622	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3623	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3624	continue;
3625	}
3626	break;
3627	}
3628	}
3629
3630	/* Clear the leaf. */
3631	pCurLeaf->uEax = 0;
3632	pCurLeaf->uEbx = 0;
3633	pCurLeaf->uEcx = 0;
3634	pCurLeaf->uEdx = 0;
3635	}
3636	}
3637
3638	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3639	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3640	{
3641	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3642	if (pCurLeaf)
3643	{
3644	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3645	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3646	pCurLeaf->uEbx = cbXSaveMaxReport;
3647	pCurLeaf->uEcx = cbXSaveMaxReport;
3648	}
3649	}
3650
3651	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3652	* We zero this since we don't know what it may have been used for.
3653	*/
3654	cpumR3CpuIdZeroLeaf(pCpum, 14);
3655
3656	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3657	* also known as Intel Resource Director Technology (RDT) Monitoring
3658	* We zero this as we don't currently virtualize PQM.
3659	*/
3660	cpumR3CpuIdZeroLeaf(pCpum, 15);
3661
3662	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3663	* also known as Intel Resource Director Technology (RDT) Allocation
3664	* We zero this as we don't currently virtualize PQE.
3665	*/
3666	cpumR3CpuIdZeroLeaf(pCpum, 16);
3667
3668	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3669	* We zero this since we don't know what it may have been used for.
3670	*/
3671	cpumR3CpuIdZeroLeaf(pCpum, 17);
3672
3673	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3674	* We zero this as we don't currently virtualize this.
3675	*/
3676	cpumR3CpuIdZeroLeaf(pCpum, 18);
3677
3678	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3679	* We zero this since we don't know what it may have been used for.
3680	*/
3681	cpumR3CpuIdZeroLeaf(pCpum, 19);
3682
3683	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3684	* We zero this as we don't currently virtualize this.
3685	*/
3686	cpumR3CpuIdZeroLeaf(pCpum, 20);
3687
3688	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3689	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3690	* EAX - denominator (unsigned).
3691	* EBX - numerator (unsigned).
3692	* ECX, EDX - reserved.
3693	* AMD: Reserved / undefined / not implemented.
3694	* VIA: Reserved / undefined / not implemented.
3695	* We zero this as we don't currently virtualize this.
3696	*/
3697	cpumR3CpuIdZeroLeaf(pCpum, 21);
3698
3699	/* Cpuid 0x16: Processor frequency info
3700	* Intel: EAX - Core base frequency in MHz.
3701	* EBX - Core maximum frequency in MHz.
3702	* ECX - Bus (reference) frequency in MHz.
3703	* EDX - Reserved.
3704	* AMD: Reserved / undefined / not implemented.
3705	* VIA: Reserved / undefined / not implemented.
3706	* We zero this as we don't currently virtualize this.
3707	*/
3708	cpumR3CpuIdZeroLeaf(pCpum, 22);
3709
3710	/* Cpuid 0x17..0x10000000: Unknown.
3711	* We don't know these and what they mean, so remove them. */
3712	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3713	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3714
3715
3716	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3717	* We remove all these as we're a hypervisor and must provide our own.
3718	*/
3719	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3720	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3721
3722
3723	/* Cpuid 0x80000000 is harmless. */
3724
3725	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3726
3727	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3728
3729	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3730	* Safe to pass on to the guest.
3731	*
3732	* AMD: 0x800000005 L1 cache information
3733	* 0x800000006 L2/L3 cache information
3734	* Intel: 0x800000005 reserved
3735	* 0x800000006 L2 cache information
3736	* VIA: 0x800000005 TLB and L1 cache information
3737	* 0x800000006 L2 cache information
3738	*/
3739
3740	/* Cpuid 0x800000007: Advanced Power Management Information.
3741	* AMD: EAX: Processor feedback capabilities.
3742	* EBX: RAS capabilites.
3743	* ECX: Advanced power monitoring interface.
3744	* EDX: Enhanced power management capabilities.
3745	* Intel: EAX, EBX, ECX - reserved.
3746	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3747	* VIA: Reserved
3748	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3749	*/
3750	uSubLeaf = 0;
3751	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3752	{
3753	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3754	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3755	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3756	{
3757	/*
3758	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3759	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3760	* bit is now configurable.
3761	*/
3762	pCurLeaf->uEdx &= 0
3763	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3764	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3765	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3766	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3767	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3768	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3769	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3770	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3771	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3772	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3773	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3774	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3775	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3776	\| 0;
3777	}
3778	else
3779	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3780	if (!pConfig->fInvariantTsc)
3781	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3782	uSubLeaf++;
3783	}
3784
3785	/* Cpuid 0x80000008:
3786	* AMD: EBX, EDX - reserved
3787	* EAX: Virtual/Physical/Guest address Size
3788	* ECX: Number of cores + APICIdCoreIdSize
3789	* Intel: EAX: Virtual/Physical address Size
3790	* EBX, ECX, EDX - reserved
3791	* VIA: EAX: Virtual/Physical address Size
3792	* EBX, ECX, EDX - reserved
3793	*
3794	* We only expose the virtual+pysical address size to the guest atm.
3795	* On AMD we set the core count, but not the apic id stuff as we're
3796	* currently not doing the apic id assignments in a complatible manner.
3797	*/
3798	uSubLeaf = 0;
3799	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3800	{
3801	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3802	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3803	pCurLeaf->uEdx = 0; /* reserved */
3804
3805	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3806	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3807	pCurLeaf->uEcx = 0;
3808	#ifdef VBOX_WITH_MULTI_CORE
3809	if ( pVM->cCpus > 1
3810	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3811	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3812	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3813	#endif
3814	uSubLeaf++;
3815	}
3816
3817	/* Cpuid 0x80000009: Reserved
3818	* We zero this since we don't know what it may have been used for.
3819	*/
3820	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3821
3822	/* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
3823	* AMD: EAX - SVM revision.
3824	* EBX - Number of ASIDs.
3825	* ECX - Reserved.
3826	* EDX - SVM Feature identification.
3827	*/
3828	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3829	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3830	{
3831	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3832	if ( pExtFeatureLeaf
3833	&& (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM))
3834	{
3835	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3836	if (pSvmFeatureLeaf)
3837	{
3838	pSvmFeatureLeaf->uEax = 0x1;
3839	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3840	pSvmFeatureLeaf->uEcx = 0;
3841	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3842	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3843	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3844	}
3845	else
3846	{
3847	/* Should never happen. */
3848	LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
3849	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3850	}
3851	}
3852	else
3853	{
3854	/* If SVM is not supported, this is reserved, zero out. */
3855	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3856	}
3857	}
3858	else
3859	{
3860	/* Cpuid 0x8000000a: Reserved on Intel.
3861	* We zero this since we don't know what it may have been used for.
3862	*/
3863	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3864	}
3865
3866	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3867	* We clear these as we don't know what purpose they might have. */
3868	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3869	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3870
3871	/* Cpuid 0x80000019: TLB configuration
3872	* Seems to be harmless, pass them thru as is. */
3873
3874	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3875	* Strip anything we don't know what is or addresses feature we don't implement. */
3876	uSubLeaf = 0;
3877	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3878	{
3879	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3880	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3881	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3882	;
3883	pCurLeaf->uEbx = 0; /* reserved */
3884	pCurLeaf->uEcx = 0; /* reserved */
3885	pCurLeaf->uEdx = 0; /* reserved */
3886	uSubLeaf++;
3887	}
3888
3889	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3890	* Clear this as we don't currently virtualize this feature. */
3891	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3892
3893	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3894	* Clear this as we don't currently virtualize this feature. */
3895	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3896
3897	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3898	* We need to sanitize the cores per cache (EAX[25:14]).
3899	*
3900	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3901	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3902	* slightly different meaning.
3903	*/
3904	uSubLeaf = 0;
3905	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3906	{
3907	#ifdef VBOX_WITH_MULTI_CORE
3908	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3909	if (cCores > pVM->cCpus)
3910	cCores = pVM->cCpus;
3911	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3912	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3913	#else
3914	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3915	#endif
3916	uSubLeaf++;
3917	}
3918
3919	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3920	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3921	* setup, we have one compute unit with all the cores in it. Single node.
3922	*/
3923	uSubLeaf = 0;
3924	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3925	{
3926	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3927	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3928	{
3929	#ifdef VBOX_WITH_MULTI_CORE
3930	pCurLeaf->uEbx = pVM->cCpus < 0x100
3931	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3932	#else
3933	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3934	#endif
3935	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3936	}
3937	else
3938	{
3939	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3940	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_HYGON);
3941	pCurLeaf->uEbx = 0; /* Reserved. */
3942	pCurLeaf->uEcx = 0; /* Reserved. */
3943	}
3944	pCurLeaf->uEdx = 0; /* Reserved. */
3945	uSubLeaf++;
3946	}
3947
3948	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3949	* We don't know these and what they mean, so remove them. */
3950	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3951	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3952
3953	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3954	* Just pass it thru for now. */
3955
3956	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3957	* Just pass it thru for now. */
3958
3959	/* Cpuid 0xc0000000: Centaur stuff.
3960	* Harmless, pass it thru. */
3961
3962	/* Cpuid 0xc0000001: Centaur features.
3963	* VIA: EAX - Family, model, stepping.
3964	* EDX - Centaur extended feature flags. Nothing interesting, except may
3965	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3966	* EBX, ECX - reserved.
3967	* We keep EAX but strips the rest.
3968	*/
3969	uSubLeaf = 0;
3970	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3971	{
3972	pCurLeaf->uEbx = 0;
3973	pCurLeaf->uEcx = 0;
3974	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3975	uSubLeaf++;
3976	}
3977
3978	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3979	* We only have fixed stale values, but should be harmless. */
3980
3981	/* Cpuid 0xc0000003: Reserved.
3982	* We zero this since we don't know what it may have been used for.
3983	*/
3984	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3985
3986	/* Cpuid 0xc0000004: Centaur Performance Info.
3987	* We only have fixed stale values, but should be harmless. */
3988
3989
3990	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3991	* We don't know these and what they mean, so remove them. */
3992	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3993	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3994
3995	return VINF_SUCCESS;
3996	#undef PORTABLE_DISABLE_FEATURE_BIT
3997	#undef PORTABLE_CLEAR_BITS_WHEN
3998	}
3999
4000
4001	/**
4002	* Reads a value in /CPUM/IsaExts/ node.
4003	*
4004	* @returns VBox status code (error message raised).
4005	* @param pVM The cross context VM structure. (For errors.)
4006	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4007	* @param pszValueName The value / extension name.
4008	* @param penmValue Where to return the choice.
4009	* @param enmDefault The default choice.
4010	*/
4011	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
4012	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
4013	{
4014	/*
4015	* Try integer encoding first.
4016	*/
4017	uint64_t uValue;
4018	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
4019	if (RT_SUCCESS(rc))
4020	switch (uValue)
4021	{
4022	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
4023	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
4024	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
4025	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
4026	default:
4027	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
4028	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
4029	pszValueName, uValue);
4030	}
4031	/*
4032	* If missing, use default.
4033	*/
4034	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
4035	*penmValue = enmDefault;
4036	else
4037	{
4038	if (rc == VERR_CFGM_NOT_INTEGER)
4039	{
4040	/*
4041	* Not an integer, try read it as a string.
4042	*/
4043	char szValue[32];
4044	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
4045	if (RT_SUCCESS(rc))
4046	{
4047	RTStrToLower(szValue);
4048	size_t cchValue = strlen(szValue);
4049	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
4050	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
4051	*penmValue = CPUMISAEXTCFG_DISABLED;
4052	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
4053	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
4054	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
4055	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
4056	else if (EQ("portable"))
4057	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
4058	else if (EQ("default") \|\| EQ("def"))
4059	*penmValue = enmDefault;
4060	else
4061	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
4062	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
4063	pszValueName, uValue);
4064	#undef EQ
4065	}
4066	}
4067	if (RT_FAILURE(rc))
4068	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
4069	}
4070	return VINF_SUCCESS;
4071	}
4072
4073
4074	/**
4075	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
4076	*
4077	* @returns VBox status code (error message raised).
4078	* @param pVM The cross context VM structure. (For errors.)
4079	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4080	* @param pszValueName The value / extension name.
4081	* @param penmValue Where to return the choice.
4082	* @param enmDefault The default choice.
4083	* @param fAllowed Allowed choice. Applied both to the result and to
4084	* the default value.
4085	*/
4086	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
4087	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
4088	{
4089	int rc;
4090	if (fAllowed)
4091	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4092	else
4093	{
4094	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
4095	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
4096	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
4097	*penmValue = CPUMISAEXTCFG_DISABLED;
4098	}
4099	return rc;
4100	}
4101
4102
4103	/**
4104	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
4105	*
4106	* @returns VBox status code (error message raised).
4107	* @param pVM The cross context VM structure. (For errors.)
4108	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4109	* @param pCpumCfg The /CPUM node (can be NULL).
4110	* @param pszValueName The value / extension name.
4111	* @param penmValue Where to return the choice.
4112	* @param enmDefault The default choice.
4113	*/
4114	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
4115	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
4116	{
4117	if (CFGMR3Exists(pCpumCfg, pszValueName))
4118	{
4119	if (!CFGMR3Exists(pIsaExts, pszValueName))
4120	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
4121	else
4122	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
4123	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
4124	pszValueName, pszValueName);
4125
4126	bool fLegacy;
4127	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
4128	if (RT_SUCCESS(rc))
4129	{
4130	*penmValue = fLegacy;
4131	return VINF_SUCCESS;
4132	}
4133	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
4134	}
4135
4136	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4137	}
4138
4139
4140	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
4141	{
4142	int rc;
4143
4144	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
4145	* When non-zero CPUID features that could cause portability issues will be
4146	* stripped. The higher the value the more features gets stripped. Higher
4147	* values should only be used when older CPUs are involved since it may
4148	* harm performance and maybe also cause problems with specific guests. */
4149	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
4150	AssertLogRelRCReturn(rc, rc);
4151
4152	/** @cfgm{/CPUM/GuestCpuName, string}
4153	* The name of the CPU we're to emulate. The default is the host CPU.
4154	* Note! CPUs other than "host" one is currently unsupported. */
4155	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
4156	AssertLogRelRCReturn(rc, rc);
4157
4158	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
4159	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
4160	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
4161	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
4162	*/
4163	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
4164	AssertLogRelRCReturn(rc, rc);
4165
4166	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
4167	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
4168	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
4169	* 64-bit linux guests which assume the presence of AMD performance counters
4170	* that we do not virtualize.
4171	*/
4172	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
4173	AssertLogRelRCReturn(rc, rc);
4174
4175	/** @cfgm{/CPUM/ForceVme, boolean, false}
4176	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
4177	* By default the flag is passed thru as is from the host CPU, except
4178	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
4179	* guests and DOS boxes in general.
4180	*/
4181	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
4182	AssertLogRelRCReturn(rc, rc);
4183
4184	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
4185	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
4186	* probably going to be a temporary hack, so don't depend on this.
4187	* The 1st byte of the value is the stepping, the 2nd byte value is the model
4188	* number and the 3rd byte value is the family, and the 4th value must be zero.
4189	*/
4190	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
4191	AssertLogRelRCReturn(rc, rc);
4192
4193	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
4194	* The last standard leaf to keep. The actual last value that is stored in EAX
4195	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
4196	* removed. (This works independently of and differently from NT4LeafLimit.)
4197	* The default is usually set to what we're able to reasonably sanitize.
4198	*/
4199	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
4200	AssertLogRelRCReturn(rc, rc);
4201
4202	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
4203	* The last extended leaf to keep. The actual last value that is stored in EAX
4204	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
4205	* leaf are removed. The default is set to what we're able to sanitize.
4206	*/
4207	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
4208	AssertLogRelRCReturn(rc, rc);
4209
4210	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
4211	* The last extended leaf to keep. The actual last value that is stored in EAX
4212	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
4213	* leaf are removed. The default is set to what we're able to sanitize.
4214	*/
4215	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
4216	AssertLogRelRCReturn(rc, rc);
4217
4218	bool fQueryNestedHwvirt = false
4219	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4220	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4221	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON
4222	#endif
4223	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4224	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
4225	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA
4226	#endif
4227	;
4228	if (fQueryNestedHwvirt)
4229	{
4230	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
4231	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
4232	* The default is false, and when enabled requires a 64-bit CPU with support for
4233	* nested-paging and AMD-V or unrestricted guest mode.
4234	*/
4235	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
4236	AssertLogRelRCReturn(rc, rc);
4237	if (pConfig->fNestedHWVirt)
4238	{
4239	/** @todo Think about enabling this later with NEM/KVM. */
4240	if (VM_IS_NEM_ENABLED(pVM))
4241	{
4242	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used! (later)\n"));
4243	pConfig->fNestedHWVirt = false;
4244	}
4245	else if (!fNestedPagingAndFullGuestExec)
4246	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
4247	"Cannot enable nested VT-x/AMD-V without nested-paging and unrestricted guest execution!\n");
4248	}
4249
4250	if (pConfig->fNestedHWVirt)
4251	{
4252	/** @cfgm{/CPUM/NestedVmxPreemptTimer, bool, true}
4253	* Whether to expose the VMX-preemption timer feature to the guest (if also
4254	* supported by the host hardware). When disabled will prevent exposing the
4255	* VMX-preemption timer feature to the guest even if the host supports it.
4256	*
4257	* @todo Currently disabled, see @bugref{9180#c108}.
4258	*/
4259	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxPreemptTimer", &pVM->cpum.s.fNestedVmxPreemptTimer, false);
4260	AssertLogRelRCReturn(rc, rc);
4261
4262	/** @cfgm{/CPUM/NestedVmxEpt, bool, true}
4263	* Whether to expose the EPT feature to the guest. The default is false. When
4264	* disabled will automatically prevent exposing features that rely on
4265	*/
4266	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxEpt", &pVM->cpum.s.fNestedVmxEpt, false);
4267	AssertLogRelRCReturn(rc, rc);
4268
4269	/** @cfgm{/CPUM/NestedVmxUnrestrictedGuest, bool, true}
4270	* Whether to expose the Unrestricted Guest feature to the guest. The default is
4271	* false. When disabled will automatically prevent exposing features that rely on
4272	* it.
4273	*/
4274	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxUnrestrictedGuest", &pVM->cpum.s.fNestedVmxUnrestrictedGuest, false);
4275	AssertLogRelRCReturn(rc, rc);
4276
4277	if ( pVM->cpum.s.fNestedVmxUnrestrictedGuest
4278	&& !pVM->cpum.s.fNestedVmxEpt)
4279	{
4280	LogRel(("CPUM: WARNING! Can't expose \"Unrestricted Guest\" to the guest when EPT is not exposed!\n"));
4281	pVM->cpum.s.fNestedVmxUnrestrictedGuest = false;
4282	}
4283	}
4284	}
4285
4286	/*
4287	* Instruction Set Architecture (ISA) Extensions.
4288	*/
4289	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
4290	if (pIsaExts)
4291	{
4292	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
4293	"CMPXCHG16B"
4294	"\|MONITOR"
4295	"\|MWaitExtensions"
4296	"\|SSE4.1"
4297	"\|SSE4.2"
4298	"\|XSAVE"
4299	"\|AVX"
4300	"\|AVX2"
4301	"\|AESNI"
4302	"\|PCLMUL"
4303	"\|POPCNT"
4304	"\|MOVBE"
4305	"\|RDRAND"
4306	"\|RDSEED"
4307	"\|CLFLUSHOPT"
4308	"\|FSGSBASE"
4309	"\|PCID"
4310	"\|INVPCID"
4311	"\|FlushCmdMsr"
4312	"\|ABM"
4313	"\|SSE4A"
4314	"\|MISALNSSE"
4315	"\|3DNOWPRF"
4316	"\|AXMMX"
4317	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
4318	if (RT_FAILURE(rc))
4319	return rc;
4320	}
4321
4322	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, true}
4323	* Expose CMPXCHG16B to the guest if available. All host CPUs which support
4324	* hardware virtualization have it.
4325	*/
4326	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, true);
4327	AssertLogRelRCReturn(rc, rc);
4328
4329	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
4330	* Expose MONITOR/MWAIT instructions to the guest.
4331	*/
4332	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
4333	AssertLogRelRCReturn(rc, rc);
4334
4335	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4336	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4337	* break on interrupt feature (bit 1).
4338	*/
4339	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4340	AssertLogRelRCReturn(rc, rc);
4341
4342	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4343	* Expose SSE4.1 to the guest if available.
4344	*/
4345	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4346	AssertLogRelRCReturn(rc, rc);
4347
4348	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4349	* Expose SSE4.2 to the guest if available.
4350	*/
4351	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4352	AssertLogRelRCReturn(rc, rc);
4353
4354	bool const fMayHaveXSave = pVM->cpum.s.HostFeatures.fXSaveRstor
4355	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
4356	&& ( VM_IS_NEM_ENABLED(pVM)
4357	? NEMHCGetFeatures(pVM) & NEM_FEAT_F_XSAVE_XRSTOR
4358	: VM_IS_EXEC_ENGINE_IEM(pVM)
4359	? false /** @todo IEM and XSAVE @bugref{9898} */
4360	: fNestedPagingAndFullGuestExec);
4361	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4362
4363	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4364	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4365	* default is to only expose this to VMs with nested paging and AMD-V or
4366	* unrestricted guest execution mode. Not possible to force this one without
4367	* host support at the moment.
4368	*/
4369	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4370	fMayHaveXSave /fAllowed/);
4371	AssertLogRelRCReturn(rc, rc);
4372
4373	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4374	* Expose the AVX instruction set extensions to the guest if available and
4375	* XSAVE is exposed too. For the time being the default is to only expose this
4376	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4377	*/
4378	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4379	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4380	AssertLogRelRCReturn(rc, rc);
4381
4382	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4383	* Expose the AVX2 instruction set extensions to the guest if available and
4384	* XSAVE is exposed too. For the time being the default is to only expose this
4385	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4386	*/
4387	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4388	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4389	AssertLogRelRCReturn(rc, rc);
4390
4391	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4392	* Whether to expose the AES instructions to the guest. For the time being the
4393	* default is to only do this for VMs with nested paging and AMD-V or
4394	* unrestricted guest mode.
4395	*/
4396	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4397	AssertLogRelRCReturn(rc, rc);
4398
4399	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4400	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4401	* being the default is to only do this for VMs with nested paging and AMD-V or
4402	* unrestricted guest mode.
4403	*/
4404	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4405	AssertLogRelRCReturn(rc, rc);
4406
4407	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4408	* Whether to expose the POPCNT instructions to the guest. For the time
4409	* being the default is to only do this for VMs with nested paging and AMD-V or
4410	* unrestricted guest mode.
4411	*/
4412	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4413	AssertLogRelRCReturn(rc, rc);
4414
4415	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4416	* Whether to expose the MOVBE instructions to the guest. For the time
4417	* being the default is to only do this for VMs with nested paging and AMD-V or
4418	* unrestricted guest mode.
4419	*/
4420	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4421	AssertLogRelRCReturn(rc, rc);
4422
4423	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4424	* Whether to expose the RDRAND instructions to the guest. For the time being
4425	* the default is to only do this for VMs with nested paging and AMD-V or
4426	* unrestricted guest mode.
4427	*/
4428	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4429	AssertLogRelRCReturn(rc, rc);
4430
4431	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4432	* Whether to expose the RDSEED instructions to the guest. For the time being
4433	* the default is to only do this for VMs with nested paging and AMD-V or
4434	* unrestricted guest mode.
4435	*/
4436	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4437	AssertLogRelRCReturn(rc, rc);
4438
4439	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4440	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4441	* being the default is to only do this for VMs with nested paging and AMD-V or
4442	* unrestricted guest mode.
4443	*/
4444	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4445	AssertLogRelRCReturn(rc, rc);
4446
4447	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4448	* Whether to expose the read/write FSGSBASE instructions to the guest.
4449	*/
4450	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4451	AssertLogRelRCReturn(rc, rc);
4452
4453	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4454	* Whether to expose the PCID feature to the guest.
4455	*/
4456	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4457	AssertLogRelRCReturn(rc, rc);
4458
4459	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4460	* Whether to expose the INVPCID instruction to the guest.
4461	*/
4462	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4463	AssertLogRelRCReturn(rc, rc);
4464
4465	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
4466	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
4467	*/
4468	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4469	AssertLogRelRCReturn(rc, rc);
4470
4471	/** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
4472	* Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
4473	* the guest. Requires FlushCmdMsr to be present too.
4474	*/
4475	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4476	AssertLogRelRCReturn(rc, rc);
4477
4478	/** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
4479	* Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
4480	*/
4481	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4482	AssertLogRelRCReturn(rc, rc);
4483
4484
4485	/* AMD: */
4486
4487	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4488	* Whether to expose the AMD ABM instructions to the guest. For the time
4489	* being the default is to only do this for VMs with nested paging and AMD-V or
4490	* unrestricted guest mode.
4491	*/
4492	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4493	AssertLogRelRCReturn(rc, rc);
4494
4495	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4496	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4497	* being the default is to only do this for VMs with nested paging and AMD-V or
4498	* unrestricted guest mode.
4499	*/
4500	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4501	AssertLogRelRCReturn(rc, rc);
4502
4503	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4504	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4505	* the time being the default is to only do this for VMs with nested paging and
4506	* AMD-V or unrestricted guest mode.
4507	*/
4508	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4509	AssertLogRelRCReturn(rc, rc);
4510
4511	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4512	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4513	* For the time being the default is to only do this for VMs with nested paging
4514	* and AMD-V or unrestricted guest mode.
4515	*/
4516	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4517	AssertLogRelRCReturn(rc, rc);
4518
4519	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4520	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4521	* the default is to only do this for VMs with nested paging and AMD-V or
4522	* unrestricted guest mode.
4523	*/
4524	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4525	AssertLogRelRCReturn(rc, rc);
4526
4527	return VINF_SUCCESS;
4528	}
4529
4530
4531	/**
4532	* Initializes the emulated CPU's CPUID & MSR information.
4533	*
4534	* @returns VBox status code.
4535	* @param pVM The cross context VM structure.
4536	* @param pHostMsrs Pointer to the host MSRs.
4537	*/
4538	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
4539	{
4540	Assert(pHostMsrs);
4541
4542	PCPUM pCpum = &pVM->cpum.s;
4543	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4544
4545	/*
4546	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4547	* on construction and manage everything from here on.
4548	*/
4549	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4550	{
4551	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4552	pVCpu->cpum.s.fCpuIdApicFeatureVisible = true;
4553	}
4554
4555	/*
4556	* Read the configuration.
4557	*/
4558	CPUMCPUIDCONFIG Config;
4559	RT_ZERO(Config);
4560
4561	bool const fNestedPagingAndFullGuestExec = VM_IS_NEM_ENABLED(pVM)
4562	\|\| VM_IS_EXEC_ENGINE_IEM(pVM)
4563	\|\| HMAreNestedPagingAndFullGuestExecEnabled(pVM);
4564	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, fNestedPagingAndFullGuestExec);
4565	AssertRCReturn(rc, rc);
4566
4567	/*
4568	* Get the guest CPU data from the database and/or the host.
4569	*
4570	* The CPUID and MSRs are currently living on the regular heap to avoid
4571	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4572	* API for the hyper heap). This means special cleanup considerations.
4573	*/
4574	/** @todo The hyper heap will be removed ASAP, so the final destination is
4575	* now a fixed sized arrays in the VM structure. Maybe we can simplify
4576	* this allocation fun a little now? Or maybe it's too convenient for
4577	* the CPU reporter code... No time to figure that out now. */
4578	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4579	if (RT_FAILURE(rc))
4580	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4581	? VMSetError(pVM, rc, RT_SRC_POS,
4582	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4583	: rc;
4584
4585	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4586	{
4587	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4588	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4589	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4590	}
4591	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4592
4593	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4594	* Overrides the guest MSRs.
4595	*/
4596	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4597
4598	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4599	* Overrides the CPUID leaf values (from the host CPU usually) used for
4600	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4601	* values when moving a VM to a different machine. Another use is restricting
4602	* (or extending) the feature set exposed to the guest. */
4603	if (RT_SUCCESS(rc))
4604	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4605
4606	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4607	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4608	"Found unsupported configuration node '/CPUM/CPUID/'. "
4609	"Please use IMachine::setCPUIDLeaf() instead.");
4610
4611	CPUMMSRS GuestMsrs;
4612	RT_ZERO(GuestMsrs);
4613
4614	/*
4615	* Pre-explode the CPUID info.
4616	*/
4617	if (RT_SUCCESS(rc))
4618	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
4619	&pCpum->GuestFeatures);
4620
4621	/*
4622	* Sanitize the cpuid information passed on to the guest.
4623	*/
4624	if (RT_SUCCESS(rc))
4625	{
4626	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4627	if (RT_SUCCESS(rc))
4628	{
4629	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4630	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4631	}
4632	}
4633
4634	/*
4635	* Setup MSRs introduced in microcode updates or that are otherwise not in
4636	* the CPU profile, but are advertised in the CPUID info we just sanitized.
4637	*/
4638	if (RT_SUCCESS(rc))
4639	rc = cpumR3MsrReconcileWithCpuId(pVM);
4640	/*
4641	* MSR fudging.
4642	*/
4643	if (RT_SUCCESS(rc))
4644	{
4645	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4646	* Fudges some common MSRs if not present in the selected CPU database entry.
4647	* This is for trying to keep VMs running when moved between different hosts
4648	* and different CPU vendors. */
4649	bool fEnable;
4650	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4651	if (RT_SUCCESS(rc) && fEnable)
4652	{
4653	rc = cpumR3MsrApplyFudge(pVM);
4654	AssertLogRelRC(rc);
4655	}
4656	}
4657	if (RT_SUCCESS(rc))
4658	{
4659	/*
4660	* Move the MSR and CPUID arrays over to the static VM structure allocations
4661	* and explode guest CPU features again.
4662	*/
4663	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4664	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4665	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
4666	RTMemFree(pvFree);
4667
4668	AssertFatalMsg(pCpum->GuestInfo.cMsrRanges <= RT_ELEMENTS(pCpum->GuestInfo.aMsrRanges),
4669	("%u\n", pCpum->GuestInfo.cMsrRanges));
4670	memcpy(pCpum->GuestInfo.aMsrRanges, pCpum->GuestInfo.paMsrRangesR3,
4671	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges);
4672	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4673	pCpum->GuestInfo.paMsrRangesR3 = pCpum->GuestInfo.aMsrRanges;
4674
4675	AssertLogRelRCReturn(rc, rc);
4676
4677	/*
4678	* Finally, initialize guest VMX MSRs.
4679	*
4680	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
4681	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
4682	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
4683	*/
4684	if (pVM->cpum.s.GuestFeatures.fVmx)
4685	{
4686	Assert(Config.fNestedHWVirt);
4687	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
4688
4689	/* Copy MSRs to all VCPUs */
4690	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
4691	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4692	{
4693	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4694	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
4695	}
4696	}
4697
4698	/*
4699	* Some more configuration that we're applying at the end of everything
4700	* via the CPUMR3SetGuestCpuIdFeature API.
4701	*/
4702
4703	/* Check if PAE was explicitely enabled by the user. */
4704	bool fEnable;
4705	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4706	AssertRCReturn(rc, rc);
4707	if (fEnable)
4708	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4709
4710	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4711	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4712	AssertRCReturn(rc, rc);
4713	if (fEnable)
4714	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4715
4716	/* Check if speculation control is enabled. */
4717	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4718	AssertRCReturn(rc, rc);
4719	if (fEnable)
4720	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4721	else
4722	{
4723	/*
4724	* Set the "SSBD-not-needed" flag to work around a bug in some Linux kernels when the VIRT_SPEC_CTL
4725	* feature is not exposed on AMD CPUs and there is only 1 vCPU configured.
4726	* This was observed with kernel "4.15.0-29-generic #31~16.04.1-Ubuntu" but more versions are likely affected.
4727	*
4728	* The kernel doesn't initialize a lock and causes a NULL pointer exception later on when configuring SSBD:
4729	* EIP: _raw_spin_lock+0x14/0x30
4730	* EFLAGS: 00010046 CPU: 0
4731	* EAX: 00000000 EBX: 00000001 ECX: 00000004 EDX: 00000000
4732	* ESI: 00000000 EDI: 00000000 EBP: ee023f1c ESP: ee023f18
4733	* DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
4734	* CR0: 80050033 CR2: 00000004 CR3: 3671c180 CR4: 000006f0
4735	* Call Trace:
4736	* speculative_store_bypass_update+0x8e/0x180
4737	* ssb_prctl_set+0xc0/0xe0
4738	* arch_seccomp_spec_mitigate+0x1d/0x20
4739	* do_seccomp+0x3cb/0x610
4740	* SyS_seccomp+0x16/0x20
4741	* do_fast_syscall_32+0x7f/0x1d0
4742	* entry_SYSENTER_32+0x4e/0x7c
4743	*
4744	* The lock would've been initialized in process.c:speculative_store_bypass_ht_init() called from two places in smpboot.c.
4745	* First when a secondary CPU is started and second in native_smp_prepare_cpus() which is not called in a single vCPU environment.
4746	*
4747	* As spectre control features are completely disabled anyway when we arrived here there is no harm done in informing the
4748	* guest to not even try.
4749	*/
4750	if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4751	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
4752	{
4753	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x80000008), 0);
4754	if (pLeaf)
4755	{
4756	pLeaf->uEbx \|= X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED;
4757	LogRel(("CPUM: Set SSBD not required flag for AMD to work around some buggy Linux kernels!\n"));
4758	}
4759	}
4760	}
4761
4762	return VINF_SUCCESS;
4763	}
4764
4765	/*
4766	* Failed before switching to hyper heap.
4767	*/
4768	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4769	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4770	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4771	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4772	return rc;
4773	}
4774
4775
4776	/**
4777	* Sets a CPUID feature bit during VM initialization.
4778	*
4779	* Since the CPUID feature bits are generally related to CPU features, other
4780	* CPUM configuration like MSRs can also be modified by calls to this API.
4781	*
4782	* @param pVM The cross context VM structure.
4783	* @param enmFeature The feature to set.
4784	*/
4785	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4786	{
4787	PCPUMCPUIDLEAF pLeaf;
4788	PCPUMMSRRANGE pMsrRange;
4789
4790	switch (enmFeature)
4791	{
4792	/*
4793	* Set the APIC bit in both feature masks.
4794	*/
4795	case CPUMCPUIDFEATURE_APIC:
4796	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4797	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4798	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4799
4800	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4801	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4802	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4803
4804	pVM->cpum.s.GuestFeatures.fApic = 1;
4805
4806	/* Make sure we've got the APICBASE MSR present. */
4807	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4808	if (!pMsrRange)
4809	{
4810	static CPUMMSRRANGE const s_ApicBase =
4811	{
4812	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4813	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4814	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4815	/.szName = / "IA32_APIC_BASE"
4816	};
4817	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4818	AssertLogRelRC(rc);
4819	}
4820
4821	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4822	break;
4823
4824	/*
4825	* Set the x2APIC bit in the standard feature mask.
4826	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4827	*/
4828	case CPUMCPUIDFEATURE_X2APIC:
4829	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4830	if (pLeaf)
4831	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4832	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4833
4834	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4835	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4836	if (pMsrRange)
4837	{
4838	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4839	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4840	}
4841
4842	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4843	break;
4844
4845	/*
4846	* Set the sysenter/sysexit bit in the standard feature mask.
4847	* Assumes the caller knows what it's doing! (host must support these)
4848	*/
4849	case CPUMCPUIDFEATURE_SEP:
4850	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4851	{
4852	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4853	return;
4854	}
4855
4856	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4857	if (pLeaf)
4858	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4859	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4860	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4861	break;
4862
4863	/*
4864	* Set the syscall/sysret bit in the extended feature mask.
4865	* Assumes the caller knows what it's doing! (host must support these)
4866	*/
4867	case CPUMCPUIDFEATURE_SYSCALL:
4868	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4869	if ( !pLeaf
4870	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4871	{
4872	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4873	return;
4874	}
4875
4876	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4877	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4878	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4879	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4880	break;
4881
4882	/*
4883	* Set the PAE bit in both feature masks.
4884	* Assumes the caller knows what it's doing! (host must support these)
4885	*/
4886	case CPUMCPUIDFEATURE_PAE:
4887	if (!pVM->cpum.s.HostFeatures.fPae)
4888	{
4889	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4890	return;
4891	}
4892
4893	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4894	if (pLeaf)
4895	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4896
4897	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4898	if ( pLeaf
4899	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4900	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
4901	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4902
4903	pVM->cpum.s.GuestFeatures.fPae = 1;
4904	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4905	break;
4906
4907	/*
4908	* Set the LONG MODE bit in the extended feature mask.
4909	* Assumes the caller knows what it's doing! (host must support these)
4910	*/
4911	case CPUMCPUIDFEATURE_LONG_MODE:
4912	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4913	if ( !pLeaf
4914	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4915	{
4916	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4917	return;
4918	}
4919
4920	/* Valid for both Intel and AMD. */
4921	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4922	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4923	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
4924	if (pVM->cpum.s.GuestFeatures.fVmx)
4925	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4926	{
4927	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4928	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic &= ~VMX_BASIC_PHYSADDR_WIDTH_32BIT;
4929	}
4930	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4931	break;
4932
4933	/*
4934	* Set the NX/XD bit in the extended feature mask.
4935	* Assumes the caller knows what it's doing! (host must support these)
4936	*/
4937	case CPUMCPUIDFEATURE_NX:
4938	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4939	if ( !pLeaf
4940	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4941	{
4942	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4943	return;
4944	}
4945
4946	/* Valid for both Intel and AMD. */
4947	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4948	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4949	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4950	break;
4951
4952
4953	/*
4954	* Set the LAHF/SAHF support in 64-bit mode.
4955	* Assumes the caller knows what it's doing! (host must support this)
4956	*/
4957	case CPUMCPUIDFEATURE_LAHF:
4958	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4959	if ( !pLeaf
4960	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4961	{
4962	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4963	return;
4964	}
4965
4966	/* Valid for both Intel and AMD. */
4967	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4968	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4969	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4970	break;
4971
4972	/*
4973	* Set the RDTSCP support bit.
4974	* Assumes the caller knows what it's doing! (host must support this)
4975	*/
4976	case CPUMCPUIDFEATURE_RDTSCP:
4977	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4978	if ( !pLeaf
4979	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4980	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4981	{
4982	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4983	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4984	return;
4985	}
4986
4987	/* Valid for both Intel and AMD. */
4988	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4989	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4990	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4991	break;
4992
4993	/*
4994	* Set the Hypervisor Present bit in the standard feature mask.
4995	*/
4996	case CPUMCPUIDFEATURE_HVP:
4997	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4998	if (pLeaf)
4999	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
5000	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
5001	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
5002	break;
5003
5004	/*
5005	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
5006	* on Intel CPUs, and different on AMDs.
5007	*/
5008	case CPUMCPUIDFEATURE_SPEC_CTRL:
5009	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
5010	{
5011	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
5012	if ( !pLeaf
5013	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
5014	{
5015	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
5016	return;
5017	}
5018
5019	/* The feature can be enabled. Let's see what we can actually do. */
5020	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
5021
5022	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
5023	if (pVM->cpum.s.HostFeatures.fIbrs)
5024	{
5025	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
5026	pVM->cpum.s.GuestFeatures.fIbrs = 1;
5027	if (pVM->cpum.s.HostFeatures.fStibp)
5028	{
5029	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
5030	pVM->cpum.s.GuestFeatures.fStibp = 1;
5031	}
5032
5033	/* Make sure we have the speculation control MSR... */
5034	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
5035	if (!pMsrRange)
5036	{
5037	static CPUMMSRRANGE const s_SpecCtrl =
5038	{
5039	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
5040	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
5041	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
5042	/.szName = / "IA32_SPEC_CTRL"
5043	};
5044	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
5045	AssertLogRelRC(rc);
5046	}
5047
5048	/* ... and the predictor command MSR. */
5049	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
5050	if (!pMsrRange)
5051	{
5052	/** @todo incorrect fWrGpMask. */
5053	static CPUMMSRRANGE const s_SpecCtrl =
5054	{
5055	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
5056	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
5057	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
5058	/.szName = / "IA32_PRED_CMD"
5059	};
5060	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
5061	AssertLogRelRC(rc);
5062	}
5063
5064	}
5065
5066	if (pVM->cpum.s.HostFeatures.fArchCap)
5067	{
5068	/* Install the architectural capabilities MSR. */
5069	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
5070	if (!pMsrRange)
5071	{
5072	static CPUMMSRRANGE const s_ArchCaps =
5073	{
5074	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
5075	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
5076	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
5077	/.szName = / "IA32_ARCH_CAPABILITIES"
5078	};
5079	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
5080	AssertLogRelRC(rc);
5081	}
5082
5083	/* Advertise IBRS_ALL if present at this point... */
5084	if (pVM->cpum.s.HostFeatures.fArchCap & MSR_IA32_ARCH_CAP_F_IBRS_ALL)
5085	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps \|= MSR_IA32_ARCH_CAP_F_IBRS_ALL);
5086	}
5087
5088	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
5089	}
5090	else if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
5091	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
5092	{
5093	/* The precise details of AMD's implementation are not yet clear. */
5094	}
5095	break;
5096
5097	default:
5098	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5099	break;
5100	}
5101
5102	/** @todo can probably kill this as this API is now init time only... */
5103	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5104	{
5105	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5106	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5107	}
5108	}
5109
5110
5111	/**
5112	* Queries a CPUID feature bit.
5113	*
5114	* @returns boolean for feature presence
5115	* @param pVM The cross context VM structure.
5116	* @param enmFeature The feature to query.
5117	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
5118	*/
5119	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
5120	{
5121	switch (enmFeature)
5122	{
5123	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
5124	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
5125	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
5126	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
5127	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
5128	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
5129	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
5130	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
5131	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
5132	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
5133	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
5134	case CPUMCPUIDFEATURE_INVALID:
5135	case CPUMCPUIDFEATURE_32BIT_HACK:
5136	break;
5137	}
5138	AssertFailed();
5139	return false;
5140	}
5141
5142
5143	/**
5144	* Clears a CPUID feature bit.
5145	*
5146	* @param pVM The cross context VM structure.
5147	* @param enmFeature The feature to clear.
5148	*
5149	* @deprecated Probably better to default the feature to disabled and only allow
5150	* setting (enabling) it during construction.
5151	*/
5152	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
5153	{
5154	PCPUMCPUIDLEAF pLeaf;
5155	switch (enmFeature)
5156	{
5157	case CPUMCPUIDFEATURE_APIC:
5158	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
5159	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5160	if (pLeaf)
5161	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
5162
5163	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5164	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
5165	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
5166
5167	pVM->cpum.s.GuestFeatures.fApic = 0;
5168	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
5169	break;
5170
5171	case CPUMCPUIDFEATURE_X2APIC:
5172	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
5173	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5174	if (pLeaf)
5175	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
5176	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
5177	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
5178	break;
5179
5180	case CPUMCPUIDFEATURE_PAE:
5181	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5182	if (pLeaf)
5183	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
5184
5185	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5186	if ( pLeaf
5187	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
5188	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
5189	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
5190
5191	pVM->cpum.s.GuestFeatures.fPae = 0;
5192	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
5193	break;
5194
5195	case CPUMCPUIDFEATURE_LONG_MODE:
5196	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5197	if (pLeaf)
5198	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
5199	pVM->cpum.s.GuestFeatures.fLongMode = 0;
5200	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = 32;
5201	if (pVM->cpum.s.GuestFeatures.fVmx)
5202	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5203	{
5204	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5205	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic \|= VMX_BASIC_PHYSADDR_WIDTH_32BIT;
5206	}
5207	break;
5208
5209	case CPUMCPUIDFEATURE_LAHF:
5210	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5211	if (pLeaf)
5212	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
5213	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
5214	break;
5215
5216	case CPUMCPUIDFEATURE_RDTSCP:
5217	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5218	if (pLeaf)
5219	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
5220	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
5221	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
5222	break;
5223
5224	case CPUMCPUIDFEATURE_HVP:
5225	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5226	if (pLeaf)
5227	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
5228	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
5229	break;
5230
5231	case CPUMCPUIDFEATURE_SPEC_CTRL:
5232	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
5233	if (pLeaf)
5234	pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP);
5235	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL);
5236	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
5237	break;
5238
5239	default:
5240	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5241	break;
5242	}
5243
5244	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5245	{
5246	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5247	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5248	}
5249	}
5250
5251
5252
5253	/*
5254	*
5255	*
5256	* Saved state related code.
5257	* Saved state related code.
5258	* Saved state related code.
5259	*
5260	*
5261	*/
5262
5263	/**
5264	* Called both in pass 0 and the final pass.
5265	*
5266	* @param pVM The cross context VM structure.
5267	* @param pSSM The saved state handle.
5268	*/
5269	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
5270	{
5271	/*
5272	* Save all the CPU ID leaves.
5273	*/
5274	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
5275	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5276	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
5277	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5278
5279	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5280
5281	/*
5282	* Save a good portion of the raw CPU IDs as well as they may come in
5283	* handy when validating features for raw mode.
5284	*/
5285	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5286	CPUMCPUID aRawStd[16];
5287	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
5288	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5289	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
5290	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
5291
5292	CPUMCPUID aRawExt[32];
5293	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
5294	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5295	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
5296	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
5297
5298	#else
5299	/* Two zero counts on non-x86 hosts. */
5300	SSMR3PutU32(pSSM, 0);
5301	SSMR3PutU32(pSSM, 0);
5302	#endif
5303	}
5304
5305
5306	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5307	{
5308	uint32_t cCpuIds;
5309	int rc = SSMR3GetU32(pSSM, &cCpuIds);
5310	if (RT_SUCCESS(rc))
5311	{
5312	if (cCpuIds < 64)
5313	{
5314	for (uint32_t i = 0; i < cCpuIds; i++)
5315	{
5316	CPUMCPUID CpuId;
5317	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
5318	if (RT_FAILURE(rc))
5319	break;
5320
5321	CPUMCPUIDLEAF NewLeaf;
5322	NewLeaf.uLeaf = uBase + i;
5323	NewLeaf.uSubLeaf = 0;
5324	NewLeaf.fSubLeafMask = 0;
5325	NewLeaf.uEax = CpuId.uEax;
5326	NewLeaf.uEbx = CpuId.uEbx;
5327	NewLeaf.uEcx = CpuId.uEcx;
5328	NewLeaf.uEdx = CpuId.uEdx;
5329	NewLeaf.fFlags = 0;
5330	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
5331	}
5332	}
5333	else
5334	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5335	}
5336	if (RT_FAILURE(rc))
5337	{
5338	RTMemFree(*ppaLeaves);
5339	*ppaLeaves = NULL;
5340	*pcLeaves = 0;
5341	}
5342	return rc;
5343	}
5344
5345
5346	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5347	{
5348	*ppaLeaves = NULL;
5349	*pcLeaves = 0;
5350
5351	int rc;
5352	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
5353	{
5354	/*
5355	* The new format. Starts by declaring the leave size and count.
5356	*/
5357	uint32_t cbLeaf;
5358	SSMR3GetU32(pSSM, &cbLeaf);
5359	uint32_t cLeaves;
5360	rc = SSMR3GetU32(pSSM, &cLeaves);
5361	if (RT_SUCCESS(rc))
5362	{
5363	if (cbLeaf == sizeof(**ppaLeaves))
5364	{
5365	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
5366	{
5367	/*
5368	* Load the leaves one by one.
5369	*
5370	* The uPrev stuff is a kludge for working around a week worth of bad saved
5371	* states during the CPUID revamp in March 2015. We saved too many leaves
5372	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
5373	* garbage entires at the end of the array when restoring. We also had
5374	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
5375	* this kludge doesn't deal correctly with that, but who cares...
5376	*/
5377	uint32_t uPrev = 0;
5378	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
5379	{
5380	CPUMCPUIDLEAF Leaf;
5381	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
5382	if (RT_SUCCESS(rc))
5383	{
5384	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
5385	\|\| Leaf.uLeaf >= uPrev)
5386	{
5387	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5388	uPrev = Leaf.uLeaf;
5389	}
5390	else
5391	uPrev = UINT32_MAX;
5392	}
5393	}
5394	}
5395	else
5396	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5397	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5398	}
5399	else
5400	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5401	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5402	}
5403	}
5404	else
5405	{
5406	/*
5407	* The old format with its three inflexible arrays.
5408	*/
5409	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5410	if (RT_SUCCESS(rc))
5411	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5412	if (RT_SUCCESS(rc))
5413	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5414	if (RT_SUCCESS(rc))
5415	{
5416	/*
5417	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5418	*/
5419	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5420	if ( pLeaf
5421	&& RTX86IsIntelCpu(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5422	{
5423	CPUMCPUIDLEAF Leaf;
5424	Leaf.uLeaf = 4;
5425	Leaf.fSubLeafMask = UINT32_MAX;
5426	Leaf.uSubLeaf = 0;
5427	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5428	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5429	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5430	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5431	\| UINT32_C(63); /* system coherency line size - 1 */
5432	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5433	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5434	\| (UINT32_C(1) << 5) /* cache level */
5435	\| UINT32_C(1); /* cache type (data) */
5436	Leaf.fFlags = 0;
5437	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5438	if (RT_SUCCESS(rc))
5439	{
5440	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5441	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5442	}
5443	if (RT_SUCCESS(rc))
5444	{
5445	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5446	Leaf.uEcx = 4095; /* sets - 1 */
5447	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5448	Leaf.uEbx \|= UINT32_C(23) << 22;
5449	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5450	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5451	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5452	Leaf.uEax \|= UINT32_C(2) << 5;
5453	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5454	}
5455	}
5456	}
5457	}
5458	return rc;
5459	}
5460
5461
5462	/**
5463	* Loads the CPU ID leaves saved by pass 0, inner worker.
5464	*
5465	* @returns VBox status code.
5466	* @param pVM The cross context VM structure.
5467	* @param pSSM The saved state handle.
5468	* @param uVersion The format version.
5469	* @param paLeaves Guest CPUID leaves loaded from the state.
5470	* @param cLeaves The number of leaves in @a paLeaves.
5471	* @param pMsrs The guest MSRs.
5472	*/
5473	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
5474	{
5475	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5476
5477	/*
5478	* Continue loading the state into stack buffers.
5479	*/
5480	CPUMCPUID GuestDefCpuId;
5481	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5482	AssertRCReturn(rc, rc);
5483
5484	CPUMCPUID aRawStd[16];
5485	uint32_t cRawStd;
5486	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5487	if (cRawStd > RT_ELEMENTS(aRawStd))
5488	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5489	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5490	AssertRCReturn(rc, rc);
5491	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5492	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5493	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5494	#else
5495	RT_ZERO(aRawStd[i]);
5496	#endif
5497
5498	CPUMCPUID aRawExt[32];
5499	uint32_t cRawExt;
5500	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5501	if (cRawExt > RT_ELEMENTS(aRawExt))
5502	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5503	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5504	AssertRCReturn(rc, rc);
5505	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5506	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5507	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5508	#else
5509	RT_ZERO(aRawExt[i]);
5510	#endif
5511
5512	/*
5513	* Get the raw CPU IDs for the current host.
5514	*/
5515	CPUMCPUID aHostRawStd[16];
5516	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5517	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5518	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5519	#else
5520	RT_ZERO(aHostRawStd);
5521	#endif
5522
5523	CPUMCPUID aHostRawExt[32];
5524	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5525	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5526	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5527	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5528	#else
5529	RT_ZERO(aHostRawExt);
5530	#endif
5531
5532	/*
5533	* Get the host and guest overrides so we don't reject the state because
5534	* some feature was enabled thru these interfaces.
5535	* Note! We currently only need the feature leaves, so skip rest.
5536	*/
5537	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5538	CPUMCPUID aHostOverrideStd[2];
5539	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5540	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5541
5542	CPUMCPUID aHostOverrideExt[2];
5543	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5544	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5545
5546	/*
5547	* This can be skipped.
5548	*/
5549	bool fStrictCpuIdChecks;
5550	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5551
5552	/*
5553	* Define a bunch of macros for simplifying the santizing/checking code below.
5554	*/
5555	/* Generic expression + failure message. */
5556	#define CPUID_CHECK_RET(expr, fmt) \
5557	do { \
5558	if (!(expr)) \
5559	{ \
5560	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5561	if (fStrictCpuIdChecks) \
5562	{ \
5563	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5564	RTStrFree(pszMsg); \
5565	return rcCpuid; \
5566	} \
5567	LogRel(("CPUM: %s\n", pszMsg)); \
5568	RTStrFree(pszMsg); \
5569	} \
5570	} while (0)
5571	#define CPUID_CHECK_WRN(expr, fmt) \
5572	do { \
5573	if (!(expr)) \
5574	LogRel(fmt); \
5575	} while (0)
5576
5577	/* For comparing two values and bitch if they differs. */
5578	#define CPUID_CHECK2_RET(what, host, saved) \
5579	do { \
5580	if ((host) != (saved)) \
5581	{ \
5582	if (fStrictCpuIdChecks) \
5583	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5584	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5585	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5586	} \
5587	} while (0)
5588	#define CPUID_CHECK2_WRN(what, host, saved) \
5589	do { \
5590	if ((host) != (saved)) \
5591	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5592	} while (0)
5593
5594	/* For checking raw cpu features (raw mode). */
5595	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5596	do { \
5597	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5598	{ \
5599	if (fStrictCpuIdChecks) \
5600	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5601	N_(#bit " mismatch: host=%d saved=%d"), \
5602	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5603	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5604	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5605	} \
5606	} while (0)
5607	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5608	do { \
5609	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5610	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5611	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5612	} while (0)
5613	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5614
5615	/* For checking guest features. */
5616	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5617	do { \
5618	if ( (aGuestCpuId##set [1].reg & bit) \
5619	&& !(aHostRaw##set [1].reg & bit) \
5620	&& !(aHostOverride##set [1].reg & bit) \
5621	) \
5622	{ \
5623	if (fStrictCpuIdChecks) \
5624	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5625	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5626	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5627	} \
5628	} while (0)
5629	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5630	do { \
5631	if ( (aGuestCpuId##set [1].reg & bit) \
5632	&& !(aHostRaw##set [1].reg & bit) \
5633	&& !(aHostOverride##set [1].reg & bit) \
5634	) \
5635	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5636	} while (0)
5637	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5638	do { \
5639	if ( (aGuestCpuId##set [1].reg & bit) \
5640	&& !(aHostRaw##set [1].reg & bit) \
5641	&& !(aHostOverride##set [1].reg & bit) \
5642	) \
5643	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5644	} while (0)
5645	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5646
5647	/* For checking guest features if AMD guest CPU. */
5648	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5649	do { \
5650	if ( (aGuestCpuId##set [1].reg & bit) \
5651	&& fGuestAmd \
5652	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5653	&& !(aHostOverride##set [1].reg & bit) \
5654	) \
5655	{ \
5656	if (fStrictCpuIdChecks) \
5657	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5658	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5659	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5660	} \
5661	} while (0)
5662	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5663	do { \
5664	if ( (aGuestCpuId##set [1].reg & bit) \
5665	&& fGuestAmd \
5666	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5667	&& !(aHostOverride##set [1].reg & bit) \
5668	) \
5669	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5670	} while (0)
5671	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5672	do { \
5673	if ( (aGuestCpuId##set [1].reg & bit) \
5674	&& fGuestAmd \
5675	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5676	&& !(aHostOverride##set [1].reg & bit) \
5677	) \
5678	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5679	} while (0)
5680	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5681
5682	/* For checking AMD features which have a corresponding bit in the standard
5683	range. (Intel defines very few bits in the extended feature sets.) */
5684	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5685	do { \
5686	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5687	&& !(fHostAmd \
5688	? aHostRawExt[1].reg & (ExtBit) \
5689	: aHostRawStd[1].reg & (StdBit)) \
5690	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5691	) \
5692	{ \
5693	if (fStrictCpuIdChecks) \
5694	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5695	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5696	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5697	} \
5698	} while (0)
5699	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5700	do { \
5701	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5702	&& !(fHostAmd \
5703	? aHostRawExt[1].reg & (ExtBit) \
5704	: aHostRawStd[1].reg & (StdBit)) \
5705	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5706	) \
5707	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5708	} while (0)
5709	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5710	do { \
5711	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5712	&& !(fHostAmd \
5713	? aHostRawExt[1].reg & (ExtBit) \
5714	: aHostRawStd[1].reg & (StdBit)) \
5715	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5716	) \
5717	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5718	} while (0)
5719	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5720
5721
5722	/*
5723	* Verify that we can support the features already exposed to the guest on
5724	* this host.
5725	*
5726	* Most of the features we're emulating requires intercepting instruction
5727	* and doing it the slow way, so there is no need to warn when they aren't
5728	* present in the host CPU. Thus we use IGN instead of EMU on these.
5729	*
5730	* Trailing comments:
5731	* "EMU" - Possible to emulate, could be lots of work and very slow.
5732	* "EMU?" - Can this be emulated?
5733	*/
5734	CPUMCPUID aGuestCpuIdStd[2];
5735	RT_ZERO(aGuestCpuIdStd);
5736	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5737
5738	/* CPUID(1).ecx */
5739	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5740	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5741	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5742	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5743	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5744	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5745	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5746	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5747	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5748	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5749	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5750	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5751	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5752	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5753	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5754	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5755	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5756	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5757	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5758	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5759	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5760	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5761	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5762	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5763	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5764	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5765	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5766	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5767	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5768	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5769	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5770	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5771
5772	/* CPUID(1).edx */
5773	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5774	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5775	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5776	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5777	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5778	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5779	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5780	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5781	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5782	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5783	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5784	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5785	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5786	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5787	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5788	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5789	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5790	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5791	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5792	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5793	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5794	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5795	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5796	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5797	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5798	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5799	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5800	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5801	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5802	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5803	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5804	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5805
5806	/* CPUID(0x80000000). */
5807	CPUMCPUID aGuestCpuIdExt[2];
5808	RT_ZERO(aGuestCpuIdExt);
5809	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5810	{
5811	/** @todo deal with no 0x80000001 on the host. */
5812	bool const fHostAmd = RTX86IsAmdCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx)
5813	\|\| RTX86IsHygonCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5814	bool const fGuestAmd = RTX86IsAmdCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx)
5815	\|\| RTX86IsHygonCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5816
5817	/* CPUID(0x80000001).ecx */
5818	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5819	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5820	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5821	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5822	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5823	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5824	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5825	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5826	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5827	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5828	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5829	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5830	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5831	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5832	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5833	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5834	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5835	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5836	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5837	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5838	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5839	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5840	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5841	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5842	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5843	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5844	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5845	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5846	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5847	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5848	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5849	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5850
5851	/* CPUID(0x80000001).edx */
5852	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5853	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5854	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5855	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5856	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5857	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5858	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5859	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5860	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5861	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5862	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5863	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5864	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5865	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5866	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5867	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5868	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5869	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5870	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5871	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5872	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5873	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5874	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5875	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5876	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5877	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5878	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5879	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5880	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5881	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5882	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5883	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5884	}
5885
5886	/** @todo check leaf 7 */
5887
5888	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5889	* ECX=0: EAX - Valid bits in XCR0[31:0].
5890	* EBX - Maximum state size as per current XCR0 value.
5891	* ECX - Maximum state size for all supported features.
5892	* EDX - Valid bits in XCR0[63:32].
5893	* ECX=1: EAX - Various X-features.
5894	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5895	* ECX - Valid bits in IA32_XSS[31:0].
5896	* EDX - Valid bits in IA32_XSS[63:32].
5897	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5898	* if the bit invalid all four registers are set to zero.
5899	* EAX - The state size for this feature.
5900	* EBX - The state byte offset of this feature.
5901	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5902	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5903	*/
5904	uint64_t fGuestXcr0Mask = 0;
5905	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5906	if ( pCurLeaf
5907	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5908	&& ( pCurLeaf->uEax
5909	\|\| pCurLeaf->uEbx
5910	\|\| pCurLeaf->uEcx
5911	\|\| pCurLeaf->uEdx) )
5912	{
5913	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5914	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5915	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5916	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5917	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5918	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5919	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5920	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5921
5922	/* We don't support any additional features yet. */
5923	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5924	if (pCurLeaf && pCurLeaf->uEax)
5925	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5926	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5927	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5928	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5929	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5930	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5931
5932
5933	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5934	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5935	{
5936	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5937	if (pCurLeaf)
5938	{
5939	/* If advertised, the state component offset and size must match the one used by host. */
5940	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5941	{
5942	CPUMCPUID RawHost;
5943	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5944	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5945	if ( RawHost.uEbx != pCurLeaf->uEbx
5946	\|\| RawHost.uEax != pCurLeaf->uEax)
5947	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5948	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5949	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5950	}
5951	}
5952	}
5953	#endif
5954	}
5955	/* Clear leaf 0xd just in case we're loading an old state... */
5956	else if (pCurLeaf)
5957	{
5958	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5959	{
5960	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5961	if (pCurLeaf)
5962	{
5963	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5964	\|\| ( pCurLeaf->uEax == 0
5965	&& pCurLeaf->uEbx == 0
5966	&& pCurLeaf->uEcx == 0
5967	&& pCurLeaf->uEdx == 0),
5968	("uVersion=%#x; %#x %#x %#x %#x\n",
5969	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5970	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5971	}
5972	}
5973	}
5974
5975	/* Update the fXStateGuestMask value for the VM. */
5976	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5977	{
5978	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5979	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5980	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5981	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5982	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5983	}
5984
5985	#undef CPUID_CHECK_RET
5986	#undef CPUID_CHECK_WRN
5987	#undef CPUID_CHECK2_RET
5988	#undef CPUID_CHECK2_WRN
5989	#undef CPUID_RAW_FEATURE_RET
5990	#undef CPUID_RAW_FEATURE_WRN
5991	#undef CPUID_RAW_FEATURE_IGN
5992	#undef CPUID_GST_FEATURE_RET
5993	#undef CPUID_GST_FEATURE_WRN
5994	#undef CPUID_GST_FEATURE_EMU
5995	#undef CPUID_GST_FEATURE_IGN
5996	#undef CPUID_GST_FEATURE2_RET
5997	#undef CPUID_GST_FEATURE2_WRN
5998	#undef CPUID_GST_FEATURE2_EMU
5999	#undef CPUID_GST_FEATURE2_IGN
6000	#undef CPUID_GST_AMD_FEATURE_RET
6001	#undef CPUID_GST_AMD_FEATURE_WRN
6002	#undef CPUID_GST_AMD_FEATURE_EMU
6003	#undef CPUID_GST_AMD_FEATURE_IGN
6004
6005	/*
6006	* We're good, commit the CPU ID leaves.
6007	*/
6008	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
6009	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
6010	AssertLogRelRCReturn(rc, rc);
6011
6012	return VINF_SUCCESS;
6013	}
6014
6015
6016	/**
6017	* Loads the CPU ID leaves saved by pass 0.
6018	*
6019	* @returns VBox status code.
6020	* @param pVM The cross context VM structure.
6021	* @param pSSM The saved state handle.
6022	* @param uVersion The format version.
6023	* @param pMsrs The guest MSRs.
6024	*/
6025	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
6026	{
6027	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
6028
6029	/*
6030	* Load the CPUID leaves array first and call worker to do the rest, just so
6031	* we can free the memory when we need to without ending up in column 1000.
6032	*/
6033	PCPUMCPUIDLEAF paLeaves;
6034	uint32_t cLeaves;
6035	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
6036	AssertRC(rc);
6037	if (RT_SUCCESS(rc))
6038	{
6039	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
6040	RTMemFree(paLeaves);
6041	}
6042	return rc;
6043	}
6044
6045
6046
6047	/**
6048	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
6049	*
6050	* @returns VBox status code.
6051	* @param pVM The cross context VM structure.
6052	* @param pSSM The saved state handle.
6053	* @param uVersion The format version.
6054	*/
6055	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
6056	{
6057	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
6058
6059	/*
6060	* Restore the CPUID leaves.
6061	*
6062	* Note that we support restoring less than the current amount of standard
6063	* leaves because we've been allowed more is newer version of VBox.
6064	*/
6065	uint32_t cElements;
6066	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6067	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
6068	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6069	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
6070
6071	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6072	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
6073	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6074	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
6075
6076	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6077	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
6078	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6079	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
6080
6081	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
6082
6083	/*
6084	* Check that the basic cpuid id information is unchanged.
6085	*/
6086	/** @todo we should check the 64 bits capabilities too! */
6087	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
6088	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6089	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
6090	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
6091	#endif
6092	uint32_t au32CpuIdSaved[8];
6093	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
6094	if (RT_SUCCESS(rc))
6095	{
6096	/* Ignore CPU stepping. */
6097	au32CpuId[4] &= 0xfffffff0;
6098	au32CpuIdSaved[4] &= 0xfffffff0;
6099
6100	/* Ignore APIC ID (AMD specs). */
6101	au32CpuId[5] &= ~0xff000000;
6102	au32CpuIdSaved[5] &= ~0xff000000;
6103
6104	/* Ignore the number of Logical CPUs (AMD specs). */
6105	au32CpuId[5] &= ~0x00ff0000;
6106	au32CpuIdSaved[5] &= ~0x00ff0000;
6107
6108	/* Ignore some advanced capability bits, that we don't expose to the guest. */
6109	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6110	\| X86_CPUID_FEATURE_ECX_VMX
6111	\| X86_CPUID_FEATURE_ECX_SMX
6112	\| X86_CPUID_FEATURE_ECX_EST
6113	\| X86_CPUID_FEATURE_ECX_TM2
6114	\| X86_CPUID_FEATURE_ECX_CNTXID
6115	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6116	\| X86_CPUID_FEATURE_ECX_PDCM
6117	\| X86_CPUID_FEATURE_ECX_DCA
6118	\| X86_CPUID_FEATURE_ECX_X2APIC
6119	);
6120	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6121	\| X86_CPUID_FEATURE_ECX_VMX
6122	\| X86_CPUID_FEATURE_ECX_SMX
6123	\| X86_CPUID_FEATURE_ECX_EST
6124	\| X86_CPUID_FEATURE_ECX_TM2
6125	\| X86_CPUID_FEATURE_ECX_CNTXID
6126	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6127	\| X86_CPUID_FEATURE_ECX_PDCM
6128	\| X86_CPUID_FEATURE_ECX_DCA
6129	\| X86_CPUID_FEATURE_ECX_X2APIC
6130	);
6131
6132	/* Make sure we don't forget to update the masks when enabling
6133	* features in the future.
6134	*/
6135	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
6136	( X86_CPUID_FEATURE_ECX_DTES64
6137	\| X86_CPUID_FEATURE_ECX_VMX
6138	\| X86_CPUID_FEATURE_ECX_SMX
6139	\| X86_CPUID_FEATURE_ECX_EST
6140	\| X86_CPUID_FEATURE_ECX_TM2
6141	\| X86_CPUID_FEATURE_ECX_CNTXID
6142	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6143	\| X86_CPUID_FEATURE_ECX_PDCM
6144	\| X86_CPUID_FEATURE_ECX_DCA
6145	\| X86_CPUID_FEATURE_ECX_X2APIC
6146	)));
6147	/* do the compare */
6148	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
6149	{
6150	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
6151	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
6152	"Saved=%.*Rhxs\n"
6153	"Real =%.*Rhxs\n",
6154	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6155	sizeof(au32CpuId), au32CpuId));
6156	else
6157	{
6158	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
6159	"Saved=%.*Rhxs\n"
6160	"Real =%.*Rhxs\n",
6161	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6162	sizeof(au32CpuId), au32CpuId));
6163	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
6164	}
6165	}
6166	}
6167
6168	return rc;
6169	}
6170
6171
6172
6173	/*
6174	*
6175	*
6176	* CPUID Info Handler.
6177	* CPUID Info Handler.
6178	* CPUID Info Handler.
6179	*
6180	*
6181	*/
6182
6183
6184
6185	/**
6186	* Get L1 cache / TLS associativity.
6187	*/
6188	static const char getCacheAss(unsigned u, char pszBuf)
6189	{
6190	if (u == 0)
6191	return "res0 ";
6192	if (u == 1)
6193	return "direct";
6194	if (u == 255)
6195	return "fully";
6196	if (u >= 256)
6197	return "???";
6198
6199	RTStrPrintf(pszBuf, 16, "%d way", u);
6200	return pszBuf;
6201	}
6202
6203
6204	/**
6205	* Get L2 cache associativity.
6206	*/
6207	const char *getL2CacheAss(unsigned u)
6208	{
6209	switch (u)
6210	{
6211	case 0: return "off ";
6212	case 1: return "direct";
6213	case 2: return "2 way ";
6214	case 3: return "res3 ";
6215	case 4: return "4 way ";
6216	case 5: return "res5 ";
6217	case 6: return "8 way ";
6218	case 7: return "res7 ";
6219	case 8: return "16 way";
6220	case 9: return "res9 ";
6221	case 10: return "res10 ";
6222	case 11: return "res11 ";
6223	case 12: return "res12 ";
6224	case 13: return "res13 ";
6225	case 14: return "res14 ";
6226	case 15: return "fully ";
6227	default: return "????";
6228	}
6229	}
6230
6231
6232	/** CPUID(1).EDX field descriptions. */
6233	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6234	{
6235	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6236	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6237	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6238	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6239	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6240	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6241	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6242	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6243	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6244	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6245	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6246	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6247	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6248	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6249	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6250	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6251	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6252	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6253	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6254	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6255	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6256	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6257	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6258	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6259	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6260	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6261	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6262	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6263	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6264	DBGFREGSUBFIELD_TERMINATOR()
6265	};
6266
6267	/** CPUID(1).ECX field descriptions. */
6268	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6269	{
6270	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6271	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6272	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6273	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6274	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6275	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6276	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6277	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6278	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6279	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6280	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6281	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6282	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6283	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6284	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6285	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6286	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6287	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6288	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6289	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6290	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6291	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6292	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6293	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6294	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6295	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6296	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6297	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6298	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6299	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6300	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6301	DBGFREGSUBFIELD_TERMINATOR()
6302	};
6303
6304	/** CPUID(7,0).EBX field descriptions. */
6305	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6306	{
6307	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6308	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6309	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6310	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6311	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6312	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6313	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6314	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6315	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6316	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6317	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6318	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6319	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6320	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6321	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6322	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6323	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6324	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6325	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6326	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6327	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6328	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6329	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6330	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6331	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6332	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6333	DBGFREGSUBFIELD_TERMINATOR()
6334	};
6335
6336	/** CPUID(7,0).ECX field descriptions. */
6337	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6338	{
6339	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6340	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6341	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6342	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6343	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6344	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6345	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6346	DBGFREGSUBFIELD_TERMINATOR()
6347	};
6348
6349	/** CPUID(7,0).EDX field descriptions. */
6350	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6351	{
6352	DBGFREGSUBFIELD_RO("MD_CLEAR\0" "Supports MDS related buffer clearing", 10, 1, 0),
6353	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6354	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6355	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
6356	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6357	DBGFREGSUBFIELD_RO("CORECAP\0" "Supports IA32_CORE_CAP", 30, 1, 0),
6358	DBGFREGSUBFIELD_RO("SSBD\0" "Supports IA32_SPEC_CTRL.SSBD", 31, 1, 0),
6359	DBGFREGSUBFIELD_TERMINATOR()
6360	};
6361
6362
6363	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6364	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6365	{
6366	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6367	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6368	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6369	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6370	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6371	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6372	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6373	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6374	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6375	DBGFREGSUBFIELD_TERMINATOR()
6376	};
6377
6378	/** CPUID(13,1).EAX field descriptions. */
6379	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6380	{
6381	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6382	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6383	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6384	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6385	DBGFREGSUBFIELD_TERMINATOR()
6386	};
6387
6388
6389	/** CPUID(0x80000001,0).EDX field descriptions. */
6390	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6391	{
6392	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6393	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6394	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6395	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6396	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6397	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6398	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6399	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6400	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6401	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6402	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6403	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6404	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6405	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6406	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6407	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6408	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6409	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6410	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6411	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6412	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6413	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6414	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6415	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6416	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6417	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6418	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6419	DBGFREGSUBFIELD_TERMINATOR()
6420	};
6421
6422	/** CPUID(0x80000001,0).ECX field descriptions. */
6423	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6424	{
6425	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6426	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6427	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6428	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6429	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6430	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6431	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6432	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6433	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6434	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6435	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6436	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6437	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6438	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6439	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6440	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6441	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6442	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6443	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6444	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6445	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6446	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6447	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6448	DBGFREGSUBFIELD_RO("PCX_L2I\0" "L2I/L3 Performance Counter Extensions", 28, 1, 0),
6449	DBGFREGSUBFIELD_RO("MWAITX\0" "MWAITX and MONITORX instructions", 29, 1, 0),
6450	DBGFREGSUBFIELD_TERMINATOR()
6451	};
6452
6453	/** CPUID(0x8000000a,0).EDX field descriptions. */
6454	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
6455	{
6456	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
6457	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
6458	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
6459	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
6460	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
6461	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
6462	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
6463	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
6464	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
6465	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
6466	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
6467	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
6468	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
6469	DBGFREGSUBFIELD_RO("GMET\0" "Guest Mode Execute Trap Extension", 17, 1, 0),
6470	DBGFREGSUBFIELD_TERMINATOR()
6471	};
6472
6473
6474	/** CPUID(0x80000007,0).EDX field descriptions. */
6475	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6476	{
6477	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6478	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6479	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6480	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6481	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6482	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6483	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6484	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6485	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6486	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6487	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6488	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6489	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6490	DBGFREGSUBFIELD_TERMINATOR()
6491	};
6492
6493	/** CPUID(0x80000008,0).EBX field descriptions. */
6494	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6495	{
6496	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6497	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6498	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6499	DBGFREGSUBFIELD_RO("RDPRU\0" "RDPRU instruction", 4, 1, 0),
6500	DBGFREGSUBFIELD_RO("MCOMMIT\0" "MCOMMIT instruction", 8, 1, 0),
6501	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6502	DBGFREGSUBFIELD_TERMINATOR()
6503	};
6504
6505
6506	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6507	const char *pszLeadIn, uint32_t cchWidth)
6508	{
6509	if (pszLeadIn)
6510	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6511
6512	for (uint32_t iBit = 0; iBit < 32; iBit++)
6513	if (RT_BIT_32(iBit) & uVal)
6514	{
6515	while ( pDesc->pszName != NULL
6516	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6517	pDesc++;
6518	if ( pDesc->pszName != NULL
6519	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6520	{
6521	if (pDesc->cBits == 1)
6522	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6523	else
6524	{
6525	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6526	if (pDesc->cBits < 32)
6527	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6528	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6529	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6530	}
6531	}
6532	else
6533	pHlp->pfnPrintf(pHlp, " %u", iBit);
6534	}
6535	if (pszLeadIn)
6536	pHlp->pfnPrintf(pHlp, "\n");
6537	}
6538
6539
6540	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6541	const char *pszLeadIn, uint32_t cchWidth)
6542	{
6543	if (pszLeadIn)
6544	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6545
6546	for (uint32_t iBit = 0; iBit < 64; iBit++)
6547	if (RT_BIT_64(iBit) & uVal)
6548	{
6549	while ( pDesc->pszName != NULL
6550	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6551	pDesc++;
6552	if ( pDesc->pszName != NULL
6553	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6554	{
6555	if (pDesc->cBits == 1)
6556	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6557	else
6558	{
6559	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6560	if (pDesc->cBits < 64)
6561	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6562	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6563	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6564	}
6565	}
6566	else
6567	pHlp->pfnPrintf(pHlp, " %u", iBit);
6568	}
6569	if (pszLeadIn)
6570	pHlp->pfnPrintf(pHlp, "\n");
6571	}
6572
6573
6574	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6575	const char *pszLeadIn, uint32_t cchWidth)
6576	{
6577	if (!uVal)
6578	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6579	else
6580	{
6581	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6582	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6583	pHlp->pfnPrintf(pHlp, " )\n");
6584	}
6585	}
6586
6587
6588	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6589	uint32_t cchWidth)
6590	{
6591	uint32_t uCombined = uVal1 \| uVal2;
6592	for (uint32_t iBit = 0; iBit < 32; iBit++)
6593	if ( (RT_BIT_32(iBit) & uCombined)
6594	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6595	{
6596	while ( pDesc->pszName != NULL
6597	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6598	pDesc++;
6599
6600	if ( pDesc->pszName != NULL
6601	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6602	{
6603	size_t cchMnemonic = strlen(pDesc->pszName);
6604	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6605	size_t cchDesc = strlen(pszDesc);
6606	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6607	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6608	if (pDesc->cBits < 32)
6609	{
6610	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6611	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6612	}
6613
6614	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6615	pDesc->pszName, pszDesc,
6616	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6617	uFieldValue1, uFieldValue2);
6618
6619	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6620	pDesc++;
6621	}
6622	else
6623	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6624	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6625	}
6626	}
6627
6628
6629	/**
6630	* Produces a detailed summary of standard leaf 0x00000001.
6631	*
6632	* @param pHlp The info helper functions.
6633	* @param pCurLeaf The 0x00000001 leaf.
6634	* @param fVerbose Whether to be very verbose or not.
6635	* @param fIntel Set if intel CPU.
6636	*/
6637	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6638	{
6639	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6640	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6641	uint32_t uEAX = pCurLeaf->uEax;
6642	uint32_t uEBX = pCurLeaf->uEbx;
6643
6644	pHlp->pfnPrintf(pHlp,
6645	"%36s %2d \tExtended: %d \tEffective: %d\n"
6646	"%36s %2d \tExtended: %d \tEffective: %d\n"
6647	"%36s %d\n"
6648	"%36s %d (%s)\n"
6649	"%36s %#04x\n"
6650	"%36s %d\n"
6651	"%36s %d\n"
6652	"%36s %#04x\n"
6653	,
6654	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
6655	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
6656	"Stepping:", RTX86GetCpuStepping(uEAX),
6657	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6658	"APIC ID:", (uEBX >> 24) & 0xff,
6659	"Logical CPUs:",(uEBX >> 16) & 0xff,
6660	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6661	"Brand ID:", (uEBX >> 0) & 0xff);
6662	if (fVerbose)
6663	{
6664	CPUMCPUID Host = {0};
6665	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6666	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6667	#endif
6668	pHlp->pfnPrintf(pHlp, "Features\n");
6669	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6670	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6671	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6672	}
6673	else
6674	{
6675	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6676	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6677	}
6678	}
6679
6680
6681	/**
6682	* Produces a detailed summary of standard leaf 0x00000007.
6683	*
6684	* @param pHlp The info helper functions.
6685	* @param paLeaves The CPUID leaves array.
6686	* @param cLeaves The number of leaves in the array.
6687	* @param pCurLeaf The first 0x00000007 leaf.
6688	* @param fVerbose Whether to be very verbose or not.
6689	*/
6690	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6691	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6692	{
6693	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6694	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6695	for (;;)
6696	{
6697	CPUMCPUID Host = {0};
6698	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6699	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6700	#endif
6701
6702	switch (pCurLeaf->uSubLeaf)
6703	{
6704	case 0:
6705	if (fVerbose)
6706	{
6707	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6708	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6709	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6710	if (pCurLeaf->uEdx \|\| Host.uEdx)
6711	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6712	}
6713	else
6714	{
6715	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6716	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6717	if (pCurLeaf->uEdx)
6718	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6719	}
6720	break;
6721
6722	default:
6723	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6724	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6725	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6726	break;
6727
6728	}
6729
6730	/* advance. */
6731	pCurLeaf++;
6732	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6733	\|\| pCurLeaf->uLeaf != 0x7)
6734	break;
6735	}
6736	}
6737
6738
6739	/**
6740	* Produces a detailed summary of standard leaf 0x0000000d.
6741	*
6742	* @param pHlp The info helper functions.
6743	* @param paLeaves The CPUID leaves array.
6744	* @param cLeaves The number of leaves in the array.
6745	* @param pCurLeaf The first 0x00000007 leaf.
6746	* @param fVerbose Whether to be very verbose or not.
6747	*/
6748	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6749	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6750	{
6751	RT_NOREF_PV(fVerbose);
6752	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6753	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6754	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6755	{
6756	CPUMCPUID Host = {0};
6757	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6758	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6759	#endif
6760
6761	switch (uSubLeaf)
6762	{
6763	case 0:
6764	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6765	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6766	pCurLeaf->uEbx, pCurLeaf->uEcx);
6767	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6768
6769	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6770	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6771	"Valid XCR0 bits, guest:", 42);
6772	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6773	"Valid XCR0 bits, host:", 42);
6774	break;
6775
6776	case 1:
6777	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6778	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6779	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6780
6781	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6782	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6783	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6784
6785	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6786	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6787	" Valid IA32_XSS bits, guest:", 42);
6788	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6789	" Valid IA32_XSS bits, host:", 42);
6790	break;
6791
6792	default:
6793	if ( pCurLeaf
6794	&& pCurLeaf->uSubLeaf == uSubLeaf
6795	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6796	{
6797	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6798	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6799	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6800	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6801	if (pCurLeaf->uEdx)
6802	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6803	pHlp->pfnPrintf(pHlp, " --");
6804	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6805	pHlp->pfnPrintf(pHlp, "\n");
6806	}
6807	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6808	{
6809	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6810	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6811	if (Host.uEcx & ~RT_BIT_32(0))
6812	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6813	if (Host.uEdx)
6814	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6815	pHlp->pfnPrintf(pHlp, " --");
6816	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6817	pHlp->pfnPrintf(pHlp, "\n");
6818	}
6819	break;
6820
6821	}
6822
6823	/* advance. */
6824	if (pCurLeaf)
6825	{
6826	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6827	&& pCurLeaf->uSubLeaf <= uSubLeaf
6828	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6829	pCurLeaf++;
6830	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6831	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6832	pCurLeaf = NULL;
6833	}
6834	}
6835	}
6836
6837
6838	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6839	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6840	{
6841	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6842	&& pCurLeaf->uLeaf <= uUpToLeaf)
6843	{
6844	pHlp->pfnPrintf(pHlp,
6845	" %s\n"
6846	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6847	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6848	&& pCurLeaf->uLeaf <= uUpToLeaf)
6849	{
6850	CPUMCPUID Host = {0};
6851	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6852	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6853	#endif
6854	pHlp->pfnPrintf(pHlp,
6855	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6856	"Hst: %08x %08x %08x %08x\n",
6857	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6858	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6859	pCurLeaf++;
6860	}
6861	}
6862
6863	return pCurLeaf;
6864	}
6865
6866
6867	/**
6868	* Display the guest CpuId leaves.
6869	*
6870	* @param pVM The cross context VM structure.
6871	* @param pHlp The info helper functions.
6872	* @param pszArgs "terse", "default" or "verbose".
6873	*/
6874	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6875	{
6876	/*
6877	* Parse the argument.
6878	*/
6879	unsigned iVerbosity = 1;
6880	if (pszArgs)
6881	{
6882	pszArgs = RTStrStripL(pszArgs);
6883	if (!strcmp(pszArgs, "terse"))
6884	iVerbosity--;
6885	else if (!strcmp(pszArgs, "verbose"))
6886	iVerbosity++;
6887	}
6888
6889	uint32_t uLeaf;
6890	CPUMCPUID Host = {0};
6891	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6892	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6893	PCCPUMCPUIDLEAF pCurLeaf;
6894	PCCPUMCPUIDLEAF pNextLeaf;
6895	bool const fIntel = RTX86IsIntelCpu(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6896	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6897	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6898
6899	/*
6900	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6901	*/
6902	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6903	uint32_t cHstMax = ASMCpuId_EAX(0);
6904	#else
6905	uint32_t cHstMax = 0;
6906	#endif
6907	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6908	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6909	pHlp->pfnPrintf(pHlp,
6910	" Raw Standard CPUID Leaves\n"
6911	" Leaf/sub-leaf eax ebx ecx edx\n");
6912	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6913	{
6914	uint32_t cMaxSubLeaves = 1;
6915	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6916	cMaxSubLeaves = 16;
6917	else if (uLeaf == 0xd)
6918	cMaxSubLeaves = 128;
6919
6920	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6921	{
6922	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6923	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6924	#endif
6925	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6926	&& pCurLeaf->uLeaf == uLeaf
6927	&& pCurLeaf->uSubLeaf == uSubLeaf)
6928	{
6929	pHlp->pfnPrintf(pHlp,
6930	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6931	"Hst: %08x %08x %08x %08x\n",
6932	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6933	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6934	pCurLeaf++;
6935	}
6936	else if ( uLeaf != 0xd
6937	\|\| uSubLeaf <= 1
6938	\|\| Host.uEbx != 0 )
6939	pHlp->pfnPrintf(pHlp,
6940	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6941	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6942
6943	/* Done? */
6944	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6945	\|\| pCurLeaf->uLeaf != uLeaf)
6946	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6947	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6948	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6949	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6950	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6951	)
6952	)
6953	break;
6954	}
6955	}
6956	pNextLeaf = pCurLeaf;
6957
6958	/*
6959	* If verbose, decode it.
6960	*/
6961	if (iVerbosity && paLeaves[0].uLeaf == 0)
6962	pHlp->pfnPrintf(pHlp,
6963	"%36s %.04s%.04s%.04s\n"
6964	"%36s 0x00000000-%#010x\n"
6965	,
6966	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6967	"Supports:", paLeaves[0].uEax);
6968
6969	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6970	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6971
6972	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6973	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6974
6975	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6976	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6977
6978	pCurLeaf = pNextLeaf;
6979
6980	/*
6981	* Hypervisor leaves.
6982	*
6983	* Unlike most of the other leaves reported, the guest hypervisor leaves
6984	* aren't a subset of the host CPUID bits.
6985	*/
6986	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6987
6988	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6989	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6990	#endif
6991	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6992	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6993	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6994	cMax = RT_MAX(cHstMax, cGstMax);
6995	if (cMax >= UINT32_C(0x40000000))
6996	{
6997	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6998
6999	/** @todo dump these in more detail. */
7000
7001	pCurLeaf = pNextLeaf;
7002	}
7003
7004
7005	/*
7006	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
7007	* Implemented after AMD specs.
7008	*/
7009	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
7010
7011	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7012	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7013	#endif
7014	cHstMax = RTX86IsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
7015	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
7016	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
7017	cMax = RT_MAX(cHstMax, cGstMax);
7018	if (cMax >= UINT32_C(0x80000000))
7019	{
7020
7021	pHlp->pfnPrintf(pHlp,
7022	" Raw Extended CPUID Leaves\n"
7023	" Leaf/sub-leaf eax ebx ecx edx\n");
7024	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
7025	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
7026	{
7027	uint32_t cMaxSubLeaves = 1;
7028	if (uLeaf == UINT32_C(0x8000001d))
7029	cMaxSubLeaves = 16;
7030
7031	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
7032	{
7033	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7034	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7035	#endif
7036	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
7037	&& pCurLeaf->uLeaf == uLeaf
7038	&& pCurLeaf->uSubLeaf == uSubLeaf)
7039	{
7040	pHlp->pfnPrintf(pHlp,
7041	"Gst: %08x/%04x %08x %08x %08x %08x\n"
7042	"Hst: %08x %08x %08x %08x\n",
7043	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
7044	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
7045	pCurLeaf++;
7046	}
7047	else if ( uLeaf != 0xd
7048	\|\| uSubLeaf <= 1
7049	\|\| Host.uEbx != 0 )
7050	pHlp->pfnPrintf(pHlp,
7051	"Hst: %08x/%04x %08x %08x %08x %08x\n",
7052	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
7053
7054	/* Done? */
7055	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
7056	\|\| pCurLeaf->uLeaf != uLeaf)
7057	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
7058	break;
7059	}
7060	}
7061	pNextLeaf = pCurLeaf;
7062
7063	/*
7064	* Understandable output
7065	*/
7066	if (iVerbosity)
7067	pHlp->pfnPrintf(pHlp,
7068	"Ext Name: %.4s%.4s%.4s\n"
7069	"Ext Supports: 0x80000000-%#010x\n",
7070	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
7071
7072	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
7073	if (iVerbosity && pCurLeaf)
7074	{
7075	uint32_t uEAX = pCurLeaf->uEax;
7076	pHlp->pfnPrintf(pHlp,
7077	"Family: %d \tExtended: %d \tEffective: %d\n"
7078	"Model: %d \tExtended: %d \tEffective: %d\n"
7079	"Stepping: %d\n"
7080	"Brand ID: %#05x\n",
7081	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
7082	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
7083	RTX86GetCpuStepping(uEAX),
7084	pCurLeaf->uEbx & 0xfff);
7085
7086	if (iVerbosity == 1)
7087	{
7088	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
7089	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
7090	}
7091	else
7092	{
7093	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7094	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7095	#endif
7096	pHlp->pfnPrintf(pHlp, "Ext Features\n");
7097	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
7098	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
7099	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
7100	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
7101	{
7102	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
7103	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7104	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7105	#endif
7106	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
7107	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
7108	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
7109	}
7110	}
7111	}
7112
7113	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
7114	{
7115	char szString[443+1] = {0};
7116	uint32_t pu32 = (uint32_t )szString;
7117	*pu32++ = pCurLeaf->uEax;
7118	*pu32++ = pCurLeaf->uEbx;
7119	*pu32++ = pCurLeaf->uEcx;
7120	*pu32++ = pCurLeaf->uEdx;
7121	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
7122	if (pCurLeaf)
7123	{
7124	*pu32++ = pCurLeaf->uEax;
7125	*pu32++ = pCurLeaf->uEbx;
7126	*pu32++ = pCurLeaf->uEcx;
7127	*pu32++ = pCurLeaf->uEdx;
7128	}
7129	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
7130	if (pCurLeaf)
7131	{
7132	*pu32++ = pCurLeaf->uEax;
7133	*pu32++ = pCurLeaf->uEbx;
7134	*pu32++ = pCurLeaf->uEcx;
7135	*pu32++ = pCurLeaf->uEdx;
7136	}
7137	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
7138	}
7139
7140	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
7141	{
7142	uint32_t uEAX = pCurLeaf->uEax;
7143	uint32_t uEBX = pCurLeaf->uEbx;
7144	uint32_t uECX = pCurLeaf->uEcx;
7145	uint32_t uEDX = pCurLeaf->uEdx;
7146	char sz1[32];
7147	char sz2[32];
7148
7149	pHlp->pfnPrintf(pHlp,
7150	"TLB 2/4M Instr/Uni: %s %3d entries\n"
7151	"TLB 2/4M Data: %s %3d entries\n",
7152	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
7153	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
7154	pHlp->pfnPrintf(pHlp,
7155	"TLB 4K Instr/Uni: %s %3d entries\n"
7156	"TLB 4K Data: %s %3d entries\n",
7157	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
7158	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
7159	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
7160	"L1 Instr Cache Lines Per Tag: %d\n"
7161	"L1 Instr Cache Associativity: %s\n"
7162	"L1 Instr Cache Size: %d KB\n",
7163	(uEDX >> 0) & 0xff,
7164	(uEDX >> 8) & 0xff,
7165	getCacheAss((uEDX >> 16) & 0xff, sz1),
7166	(uEDX >> 24) & 0xff);
7167	pHlp->pfnPrintf(pHlp,
7168	"L1 Data Cache Line Size: %d bytes\n"
7169	"L1 Data Cache Lines Per Tag: %d\n"
7170	"L1 Data Cache Associativity: %s\n"
7171	"L1 Data Cache Size: %d KB\n",
7172	(uECX >> 0) & 0xff,
7173	(uECX >> 8) & 0xff,
7174	getCacheAss((uECX >> 16) & 0xff, sz1),
7175	(uECX >> 24) & 0xff);
7176	}
7177
7178	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
7179	{
7180	uint32_t uEAX = pCurLeaf->uEax;
7181	uint32_t uEBX = pCurLeaf->uEbx;
7182	uint32_t uEDX = pCurLeaf->uEdx;
7183
7184	pHlp->pfnPrintf(pHlp,
7185	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
7186	"L2 TLB 2/4M Data: %s %4d entries\n",
7187	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
7188	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
7189	pHlp->pfnPrintf(pHlp,
7190	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
7191	"L2 TLB 4K Data: %s %4d entries\n",
7192	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
7193	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
7194	pHlp->pfnPrintf(pHlp,
7195	"L2 Cache Line Size: %d bytes\n"
7196	"L2 Cache Lines Per Tag: %d\n"
7197	"L2 Cache Associativity: %s\n"
7198	"L2 Cache Size: %d KB\n",
7199	(uEDX >> 0) & 0xff,
7200	(uEDX >> 8) & 0xf,
7201	getL2CacheAss((uEDX >> 12) & 0xf),
7202	(uEDX >> 16) & 0xffff);
7203	}
7204
7205	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
7206	{
7207	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7208	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7209	#endif
7210	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
7211	{
7212	if (iVerbosity < 1)
7213	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
7214	else
7215	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
7216	}
7217	}
7218
7219	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
7220	if (pCurLeaf != NULL)
7221	{
7222	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7223	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7224	#endif
7225	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
7226	{
7227	if (iVerbosity < 1)
7228	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
7229	else
7230	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
7231	}
7232
7233	if (iVerbosity)
7234	{
7235	uint32_t uEAX = pCurLeaf->uEax;
7236	uint32_t uECX = pCurLeaf->uEcx;
7237
7238	/** @todo 0x80000008:EAX[23:16] is only defined for AMD. We'll get 0 on Intel. On
7239	* AMD if we get 0, the guest physical address width should be taken from
7240	* 0x80000008:EAX[7:0] instead. Guest Physical address width is relevant
7241	* for guests using nested paging. */
7242	pHlp->pfnPrintf(pHlp,
7243	"Physical Address Width: %d bits\n"
7244	"Virtual Address Width: %d bits\n"
7245	"Guest Physical Address Width: %d bits\n",
7246	(uEAX >> 0) & 0xff,
7247	(uEAX >> 8) & 0xff,
7248	(uEAX >> 16) & 0xff);
7249
7250	/** @todo 0x80000008:ECX is reserved on Intel (we'll get incorrect physical core
7251	* count here). */
7252	pHlp->pfnPrintf(pHlp,
7253	"Physical Core Count: %d\n",
7254	((uECX >> 0) & 0xff) + 1);
7255	}
7256	}
7257
7258	pCurLeaf = pNextLeaf;
7259	}
7260
7261
7262
7263	/*
7264	* Centaur.
7265	*/
7266	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7267
7268	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7269	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7270	#endif
7271	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7272	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7273	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7274	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7275	cMax = RT_MAX(cHstMax, cGstMax);
7276	if (cMax >= UINT32_C(0xc0000000))
7277	{
7278	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7279
7280	/*
7281	* Understandable output
7282	*/
7283	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7284	pHlp->pfnPrintf(pHlp,
7285	"Centaur Supports: 0xc0000000-%#010x\n",
7286	pCurLeaf->uEax);
7287
7288	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7289	{
7290	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
7291	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7292	#endif
7293	uint32_t uEdxGst = pCurLeaf->uEdx;
7294	uint32_t uEdxHst = Host.uEdx;
7295
7296	if (iVerbosity == 1)
7297	{
7298	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7299	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7300	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7301	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7302	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7303	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7304	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7305	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7306	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7307	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7308	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7309	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7310	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7311	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7312	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7313	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7314	for (unsigned iBit = 14; iBit < 32; iBit++)
7315	if (uEdxGst & RT_BIT(iBit))
7316	pHlp->pfnPrintf(pHlp, " %d", iBit);
7317	pHlp->pfnPrintf(pHlp, "\n");
7318	}
7319	else
7320	{
7321	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7322	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7323	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7324	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7325	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7326	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7327	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7328	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7329	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7330	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7331	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7332	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7333	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7334	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7335	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7336	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7337	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7338	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7339	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7340	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7341	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7342	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7343	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7344	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7345	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7346	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7347	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7348	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7349	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7350	for (unsigned iBit = 27; iBit < 32; iBit++)
7351	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7352	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7353	pHlp->pfnPrintf(pHlp, "\n");
7354	}
7355	}
7356
7357	pCurLeaf = pNextLeaf;
7358	}
7359
7360	/*
7361	* The remainder.
7362	*/
7363	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7364	}
7365
7366	#endif /* !IN_VBOX_CPU_REPORT */
7367

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 94319

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