CPUMR3CpuId.cpp@ 76570

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1	/* $Id: CPUMR3CpuId.cpp 76553 2019-01-01 01:45:53Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vm.h>
30	#include <VBox/vmm/mm.h>
31	#include <VBox/sup.h>
32
33	#include <VBox/err.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/ctype.h>
36	#include <iprt/mem.h>
37	#include <iprt/string.h>
38
39
40	/*********************************************************************************************************************************
41	* Defined Constants And Macros *
42	*********************************************************************************************************************************/
43	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
44	#define CPUM_CPUID_MAX_LEAVES 2048
45	/* Max size we accept for the XSAVE area. */
46	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
47	/* Min size we accept for the XSAVE area. */
48	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
49
50
51	/*********************************************************************************************************************************
52	* Global Variables *
53	*********************************************************************************************************************************/
54	/**
55	* The intel pentium family.
56	*/
57	static const CPUMMICROARCH g_aenmIntelFamily06[] =
58	{
59	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
60	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
61	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
63	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
64	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
65	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
66	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
67	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
68	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
69	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
70	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
71	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
72	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
73	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
74	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
75	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
81	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
82	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
83	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
86	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
87	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
88	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
89	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
90	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
91	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
97	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
98	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
99	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
102	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
103	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
104	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
105	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
106	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
107	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
113	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
114	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
115	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
118	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
120	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
121	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
122	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
130	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
131	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
134	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
136	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
137	/* [78(0x4e)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed */
138	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / unconfirmed, Broadwell-E */
139	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu */
145	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
146	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
147	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
150	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
151	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
152	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
153	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
154	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
155	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
159	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
160	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
161	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
162	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
163	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
164	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
165	/[106(0x6a)] = / kCpumMicroarch_Intel_Unknown,
166	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
167	/[108(0x6c)] = / kCpumMicroarch_Intel_Unknown,
168	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
169	/[110(0x6e)] = / kCpumMicroarch_Intel_Unknown,
170	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
171	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
172	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
173	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
174	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
175	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
176	/[117(0x75)] = / kCpumMicroarch_Intel_Unknown,
177	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
178	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
179	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
180	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
181	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
182	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
183	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
184	/[125(0x7d)] = / kCpumMicroarch_Intel_Unknown,
185	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
186	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
187	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
188	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
189	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
190	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
191	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
192	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
193	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
194	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
195	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
196	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
197	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
198	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
199	/[140(0x8c)] = / kCpumMicroarch_Intel_Unknown,
200	/[141(0x8d)] = / kCpumMicroarch_Intel_Unknown,
201	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
202	/[143(0x8f)] = / kCpumMicroarch_Intel_Unknown,
203	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
204	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
205	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
206	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
207	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
208	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
209	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
210	/[151(0x97)] = / kCpumMicroarch_Intel_Unknown,
211	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
212	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
213	/[154(0x9a)] = / kCpumMicroarch_Intel_Unknown,
214	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
215	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
216	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
217	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
218	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
219	};
220	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0x9f+1);
221
222
223	/**
224	* Figures out the (sub-)micro architecture given a bit of CPUID info.
225	*
226	* @returns Micro architecture.
227	* @param enmVendor The CPU vendor .
228	* @param bFamily The CPU family.
229	* @param bModel The CPU model.
230	* @param bStepping The CPU stepping.
231	*/
232	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
233	uint8_t bModel, uint8_t bStepping)
234	{
235	if (enmVendor == CPUMCPUVENDOR_AMD)
236	{
237	switch (bFamily)
238	{
239	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
240	case 0x03: return kCpumMicroarch_AMD_Am386;
241	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
242	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
243	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
244	case 0x06:
245	switch (bModel)
246	{
247	case 0: return kCpumMicroarch_AMD_K7_Palomino;
248	case 1: return kCpumMicroarch_AMD_K7_Palomino;
249	case 2: return kCpumMicroarch_AMD_K7_Palomino;
250	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
251	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
252	case 6: return kCpumMicroarch_AMD_K7_Palomino;
253	case 7: return kCpumMicroarch_AMD_K7_Morgan;
254	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
255	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
256	}
257	return kCpumMicroarch_AMD_K7_Unknown;
258	case 0x0f:
259	/*
260	* This family is a friggin mess. Trying my best to make some
261	* sense out of it. Too much happened in the 0x0f family to
262	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
263	*
264	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
265	* cpu-world.com, and other places:
266	* - 130nm:
267	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
268	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
269	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
270	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
271	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
272	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
273	* - 90nm:
274	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
275	* - Oakville: 10FC0/DH-D0.
276	* - Georgetown: 10FC0/DH-D0.
277	* - Sonora: 10FC0/DH-D0.
278	* - Venus: 20F71/SH-E4
279	* - Troy: 20F51/SH-E4
280	* - Athens: 20F51/SH-E4
281	* - San Diego: 20F71/SH-E4.
282	* - Lancaster: 20F42/SH-E5
283	* - Newark: 20F42/SH-E5.
284	* - Albany: 20FC2/DH-E6.
285	* - Roma: 20FC2/DH-E6.
286	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
287	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
288	* - 90nm introducing Dual core:
289	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
290	* - Italy: 20F10/JH-E1, 20F12/JH-E6
291	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
292	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
293	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
294	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
295	* - Santa Ana: 40F32/JH-F2, /-F3
296	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
297	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
298	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
299	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
300	* - Keene: 40FC2/DH-F2.
301	* - Richmond: 40FC2/DH-F2
302	* - Taylor: 40F82/BH-F2
303	* - Trinidad: 40F82/BH-F2
304	*
305	* - 65nm:
306	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
307	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
308	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
309	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
310	* - Sherman: /-G1, 70FC2/DH-G2.
311	* - Huron: 70FF2/DH-G2.
312	*/
313	if (bModel < 0x10)
314	return kCpumMicroarch_AMD_K8_130nm;
315	if (bModel >= 0x60 && bModel < 0x80)
316	return kCpumMicroarch_AMD_K8_65nm;
317	if (bModel >= 0x40)
318	return kCpumMicroarch_AMD_K8_90nm_AMDV;
319	switch (bModel)
320	{
321	case 0x21:
322	case 0x23:
323	case 0x2b:
324	case 0x2f:
325	case 0x37:
326	case 0x3f:
327	return kCpumMicroarch_AMD_K8_90nm_DualCore;
328	}
329	return kCpumMicroarch_AMD_K8_90nm;
330	case 0x10:
331	return kCpumMicroarch_AMD_K10;
332	case 0x11:
333	return kCpumMicroarch_AMD_K10_Lion;
334	case 0x12:
335	return kCpumMicroarch_AMD_K10_Llano;
336	case 0x14:
337	return kCpumMicroarch_AMD_Bobcat;
338	case 0x15:
339	switch (bModel)
340	{
341	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
342	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
343	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
344	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
345	case 0x11: /* ?? */
346	case 0x12: /* ?? */
347	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
348	}
349	return kCpumMicroarch_AMD_15h_Unknown;
350	case 0x16:
351	return kCpumMicroarch_AMD_Jaguar;
352	case 0x17:
353	return kCpumMicroarch_AMD_Zen_Ryzen;
354	}
355	return kCpumMicroarch_AMD_Unknown;
356	}
357
358	if (enmVendor == CPUMCPUVENDOR_INTEL)
359	{
360	switch (bFamily)
361	{
362	case 3:
363	return kCpumMicroarch_Intel_80386;
364	case 4:
365	return kCpumMicroarch_Intel_80486;
366	case 5:
367	return kCpumMicroarch_Intel_P5;
368	case 6:
369	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
370	{
371	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
372	if ( enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake
373	&& bStepping >= 0xa)
374	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
375	return enmMicroArch;
376	}
377	return kCpumMicroarch_Intel_Atom_Unknown;
378	case 15:
379	switch (bModel)
380	{
381	case 0: return kCpumMicroarch_Intel_NB_Willamette;
382	case 1: return kCpumMicroarch_Intel_NB_Willamette;
383	case 2: return kCpumMicroarch_Intel_NB_Northwood;
384	case 3: return kCpumMicroarch_Intel_NB_Prescott;
385	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
386	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
387	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
388	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
389	default: return kCpumMicroarch_Intel_NB_Unknown;
390	}
391	break;
392	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
393	case 0:
394	return kCpumMicroarch_Intel_8086;
395	case 1:
396	return kCpumMicroarch_Intel_80186;
397	case 2:
398	return kCpumMicroarch_Intel_80286;
399	}
400	return kCpumMicroarch_Intel_Unknown;
401	}
402
403	if (enmVendor == CPUMCPUVENDOR_VIA)
404	{
405	switch (bFamily)
406	{
407	case 5:
408	switch (bModel)
409	{
410	case 1: return kCpumMicroarch_Centaur_C6;
411	case 4: return kCpumMicroarch_Centaur_C6;
412	case 8: return kCpumMicroarch_Centaur_C2;
413	case 9: return kCpumMicroarch_Centaur_C3;
414	}
415	break;
416
417	case 6:
418	switch (bModel)
419	{
420	case 5: return kCpumMicroarch_VIA_C3_M2;
421	case 6: return kCpumMicroarch_VIA_C3_C5A;
422	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
423	case 8: return kCpumMicroarch_VIA_C3_C5N;
424	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
425	case 10: return kCpumMicroarch_VIA_C7_C5J;
426	case 15: return kCpumMicroarch_VIA_Isaiah;
427	}
428	break;
429	}
430	return kCpumMicroarch_VIA_Unknown;
431	}
432
433	if (enmVendor == CPUMCPUVENDOR_CYRIX)
434	{
435	switch (bFamily)
436	{
437	case 4:
438	switch (bModel)
439	{
440	case 9: return kCpumMicroarch_Cyrix_5x86;
441	}
442	break;
443
444	case 5:
445	switch (bModel)
446	{
447	case 2: return kCpumMicroarch_Cyrix_M1;
448	case 4: return kCpumMicroarch_Cyrix_MediaGX;
449	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
450	}
451	break;
452
453	case 6:
454	switch (bModel)
455	{
456	case 0: return kCpumMicroarch_Cyrix_M2;
457	}
458	break;
459
460	}
461	return kCpumMicroarch_Cyrix_Unknown;
462	}
463
464	return kCpumMicroarch_Unknown;
465	}
466
467
468	/**
469	* Translates a microarchitecture enum value to the corresponding string
470	* constant.
471	*
472	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
473	* NULL if the value is invalid.
474	*
475	* @param enmMicroarch The enum value to convert.
476	*/
477	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
478	{
479	switch (enmMicroarch)
480	{
481	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
482	CASE_RET_STR(kCpumMicroarch_Intel_8086);
483	CASE_RET_STR(kCpumMicroarch_Intel_80186);
484	CASE_RET_STR(kCpumMicroarch_Intel_80286);
485	CASE_RET_STR(kCpumMicroarch_Intel_80386);
486	CASE_RET_STR(kCpumMicroarch_Intel_80486);
487	CASE_RET_STR(kCpumMicroarch_Intel_P5);
488
489	CASE_RET_STR(kCpumMicroarch_Intel_P6);
490	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
491	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
492
493	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
494	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
495	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
496
497	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
498	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
499
500	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
501	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
502	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
503	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
504	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
505	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
506	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
507	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
508	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
509	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
510	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
511	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
512
513	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
514	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
515	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
516	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
517	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
518	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
519	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
520	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
521
522	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
523	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
524	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
525	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
526	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
527
528	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
529	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
530	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
531	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
532	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
533	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
534	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
535
536	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
537
538	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
539	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
540	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
541	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
542	CASE_RET_STR(kCpumMicroarch_AMD_K5);
543	CASE_RET_STR(kCpumMicroarch_AMD_K6);
544
545	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
546	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
547	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
548	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
549	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
550	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
551	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
552
553	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
554	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
555	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
556	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
557	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
558
559	CASE_RET_STR(kCpumMicroarch_AMD_K10);
560	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
561	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
562	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
563	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
564
565	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
566	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
567	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
568	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
569	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
570
571	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
572
573	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
574
575	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
576
577	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
578	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
579	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
580	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
581	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
582	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
583	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
584	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
585	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
586	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
587	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
588	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
589	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
590
591	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
592	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
593	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
594	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
595	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
596	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
597
598	CASE_RET_STR(kCpumMicroarch_NEC_V20);
599	CASE_RET_STR(kCpumMicroarch_NEC_V30);
600
601	CASE_RET_STR(kCpumMicroarch_Unknown);
602
603	#undef CASE_RET_STR
604	case kCpumMicroarch_Invalid:
605	case kCpumMicroarch_Intel_End:
606	case kCpumMicroarch_Intel_Core2_End:
607	case kCpumMicroarch_Intel_Core7_End:
608	case kCpumMicroarch_Intel_Atom_End:
609	case kCpumMicroarch_Intel_P6_Core_Atom_End:
610	case kCpumMicroarch_Intel_Phi_End:
611	case kCpumMicroarch_Intel_NB_End:
612	case kCpumMicroarch_AMD_K7_End:
613	case kCpumMicroarch_AMD_K8_End:
614	case kCpumMicroarch_AMD_15h_End:
615	case kCpumMicroarch_AMD_16h_End:
616	case kCpumMicroarch_AMD_Zen_End:
617	case kCpumMicroarch_AMD_End:
618	case kCpumMicroarch_VIA_End:
619	case kCpumMicroarch_Cyrix_End:
620	case kCpumMicroarch_NEC_End:
621	case kCpumMicroarch_32BitHack:
622	break;
623	/* no default! */
624	}
625
626	return NULL;
627	}
628
629
630	/**
631	* Determins the host CPU MXCSR mask.
632	*
633	* @returns MXCSR mask.
634	*/
635	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
636	{
637	if ( ASMHasCpuId()
638	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
639	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
640	{
641	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
642	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
643	RT_ZERO(*pState);
644	ASMFxSave(pState);
645	if (pState->MXCSR_MASK == 0)
646	return 0xffbf;
647	return pState->MXCSR_MASK;
648	}
649	return 0;
650	}
651
652
653	/**
654	* Gets a matching leaf in the CPUID leaf array.
655	*
656	* @returns Pointer to the matching leaf, or NULL if not found.
657	* @param paLeaves The CPUID leaves to search. This is sorted.
658	* @param cLeaves The number of leaves in the array.
659	* @param uLeaf The leaf to locate.
660	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
661	*/
662	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
663	{
664	/* Lazy bird does linear lookup here since this is only used for the
665	occational CPUID overrides. */
666	for (uint32_t i = 0; i < cLeaves; i++)
667	if ( paLeaves[i].uLeaf == uLeaf
668	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
669	return &paLeaves[i];
670	return NULL;
671	}
672
673
674	#ifndef IN_VBOX_CPU_REPORT
675	/**
676	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
677	*
678	* @returns true if found, false it not.
679	* @param paLeaves The CPUID leaves to search. This is sorted.
680	* @param cLeaves The number of leaves in the array.
681	* @param uLeaf The leaf to locate.
682	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
683	* @param pLegacy The legacy output leaf.
684	*/
685	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
686	PCPUMCPUID pLegacy)
687	{
688	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
689	if (pLeaf)
690	{
691	pLegacy->uEax = pLeaf->uEax;
692	pLegacy->uEbx = pLeaf->uEbx;
693	pLegacy->uEcx = pLeaf->uEcx;
694	pLegacy->uEdx = pLeaf->uEdx;
695	return true;
696	}
697	return false;
698	}
699	#endif /* IN_VBOX_CPU_REPORT */
700
701
702	/**
703	* Ensures that the CPUID leaf array can hold one more leaf.
704	*
705	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
706	* failure.
707	* @param pVM The cross context VM structure. If NULL, use
708	* the process heap, otherwise the VM's hyper heap.
709	* @param ppaLeaves Pointer to the variable holding the array pointer
710	* (input/output).
711	* @param cLeaves The current array size.
712	*
713	* @remarks This function will automatically update the R0 and RC pointers when
714	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
715	* be the corresponding VM's CPUID arrays (which is asserted).
716	*/
717	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
718	{
719	/*
720	* If pVM is not specified, we're on the regular heap and can waste a
721	* little space to speed things up.
722	*/
723	uint32_t cAllocated;
724	if (!pVM)
725	{
726	cAllocated = RT_ALIGN(cLeaves, 16);
727	if (cLeaves + 1 > cAllocated)
728	{
729	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
730	if (pvNew)
731	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
732	else
733	{
734	RTMemFree(*ppaLeaves);
735	*ppaLeaves = NULL;
736	}
737	}
738	}
739	/*
740	* Otherwise, we're on the hyper heap and are probably just inserting
741	* one or two leaves and should conserve space.
742	*/
743	else
744	{
745	#ifdef IN_VBOX_CPU_REPORT
746	AssertReleaseFailed();
747	#else
748	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
749	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
750
751	size_t cb = cLeaves * sizeof(**ppaLeaves);
752	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
753	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
754	if (RT_SUCCESS(rc))
755	{
756	/* Update the R0 and RC pointers. */
757	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
758	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
759	}
760	else
761	{
762	*ppaLeaves = NULL;
763	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
764	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
765	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
766	}
767	#endif
768	}
769	return *ppaLeaves;
770	}
771
772
773	/**
774	* Append a CPUID leaf or sub-leaf.
775	*
776	* ASSUMES linear insertion order, so we'll won't need to do any searching or
777	* replace anything. Use cpumR3CpuIdInsert() for those cases.
778	*
779	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
780	* the caller need do no more work.
781	* @param ppaLeaves Pointer to the pointer to the array of sorted
782	* CPUID leaves and sub-leaves.
783	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
784	* @param uLeaf The leaf we're adding.
785	* @param uSubLeaf The sub-leaf number.
786	* @param fSubLeafMask The sub-leaf mask.
787	* @param uEax The EAX value.
788	* @param uEbx The EBX value.
789	* @param uEcx The ECX value.
790	* @param uEdx The EDX value.
791	* @param fFlags The flags.
792	*/
793	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
794	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
795	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
796	{
797	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
798	return VERR_NO_MEMORY;
799
800	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
801	Assert( *pcLeaves == 0
802	\|\| pNew[-1].uLeaf < uLeaf
803	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
804
805	pNew->uLeaf = uLeaf;
806	pNew->uSubLeaf = uSubLeaf;
807	pNew->fSubLeafMask = fSubLeafMask;
808	pNew->uEax = uEax;
809	pNew->uEbx = uEbx;
810	pNew->uEcx = uEcx;
811	pNew->uEdx = uEdx;
812	pNew->fFlags = fFlags;
813
814	*pcLeaves += 1;
815	return VINF_SUCCESS;
816	}
817
818
819	/**
820	* Checks that we've updated the CPUID leaves array correctly.
821	*
822	* This is a no-op in non-strict builds.
823	*
824	* @param paLeaves The leaves array.
825	* @param cLeaves The number of leaves.
826	*/
827	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
828	{
829	#ifdef VBOX_STRICT
830	for (uint32_t i = 1; i < cLeaves; i++)
831	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
832	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
833	else
834	{
835	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
836	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
837	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
838	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
839	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
840	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
841	}
842	#else
843	NOREF(paLeaves);
844	NOREF(cLeaves);
845	#endif
846	}
847
848
849	/**
850	* Inserts a CPU ID leaf, replacing any existing ones.
851	*
852	* When inserting a simple leaf where we already got a series of sub-leaves with
853	* the same leaf number (eax), the simple leaf will replace the whole series.
854	*
855	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
856	* host-context heap and has only been allocated/reallocated by the
857	* cpumR3CpuIdEnsureSpace function.
858	*
859	* @returns VBox status code.
860	* @param pVM The cross context VM structure. If NULL, use
861	* the process heap, otherwise the VM's hyper heap.
862	* @param ppaLeaves Pointer to the pointer to the array of sorted
863	* CPUID leaves and sub-leaves. Must be NULL if using
864	* the hyper heap.
865	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
866	* be NULL if using the hyper heap.
867	* @param pNewLeaf Pointer to the data of the new leaf we're about to
868	* insert.
869	*/
870	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
871	{
872	/*
873	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
874	*/
875	if (pVM)
876	{
877	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
878	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
879
880	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
881	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
882	}
883
884	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
885	uint32_t cLeaves = *pcLeaves;
886
887	/*
888	* Validate the new leaf a little.
889	*/
890	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
891	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
892	VERR_INVALID_FLAGS);
893	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
894	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
895	VERR_INVALID_PARAMETER);
896	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
897	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
898	VERR_INVALID_PARAMETER);
899	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
900	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
901	VERR_INVALID_PARAMETER);
902
903	/*
904	* Find insertion point. The lazy bird uses the same excuse as in
905	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
906	*/
907	uint32_t i;
908	if ( cLeaves > 0
909	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
910	{
911	/* Add at end. */
912	i = cLeaves;
913	}
914	else if ( cLeaves > 0
915	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
916	{
917	/* Either replacing the last leaf or dealing with sub-leaves. Spool
918	back to the first sub-leaf to pretend we did the linear search. */
919	i = cLeaves - 1;
920	while ( i > 0
921	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
922	i--;
923	}
924	else
925	{
926	/* Linear search from the start. */
927	i = 0;
928	while ( i < cLeaves
929	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
930	i++;
931	}
932	if ( i < cLeaves
933	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
934	{
935	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
936	{
937	/*
938	* The sub-leaf mask differs, replace all existing leaves with the
939	* same leaf number.
940	*/
941	uint32_t c = 1;
942	while ( i + c < cLeaves
943	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
944	c++;
945	if (c > 1 && i + c < cLeaves)
946	{
947	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
948	*pcLeaves = cLeaves -= c - 1;
949	}
950
951	paLeaves[i] = *pNewLeaf;
952	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
953	return VINF_SUCCESS;
954	}
955
956	/* Find sub-leaf insertion point. */
957	while ( i < cLeaves
958	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
959	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
960	i++;
961
962	/*
963	* If we've got an exactly matching leaf, replace it.
964	*/
965	if ( i < cLeaves
966	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
967	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
968	{
969	paLeaves[i] = *pNewLeaf;
970	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
971	return VINF_SUCCESS;
972	}
973	}
974
975	/*
976	* Adding a new leaf at 'i'.
977	*/
978	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
979	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
980	if (!paLeaves)
981	return VERR_NO_MEMORY;
982
983	if (i < cLeaves)
984	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
985	*pcLeaves += 1;
986	paLeaves[i] = *pNewLeaf;
987
988	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
989	return VINF_SUCCESS;
990	}
991
992
993	#ifndef IN_VBOX_CPU_REPORT
994	/**
995	* Removes a range of CPUID leaves.
996	*
997	* This will not reallocate the array.
998	*
999	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1000	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1001	* @param uFirst The first leaf.
1002	* @param uLast The last leaf.
1003	*/
1004	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1005	{
1006	uint32_t cLeaves = *pcLeaves;
1007
1008	Assert(uFirst <= uLast);
1009
1010	/*
1011	* Find the first one.
1012	*/
1013	uint32_t iFirst = 0;
1014	while ( iFirst < cLeaves
1015	&& paLeaves[iFirst].uLeaf < uFirst)
1016	iFirst++;
1017
1018	/*
1019	* Find the end (last + 1).
1020	*/
1021	uint32_t iEnd = iFirst;
1022	while ( iEnd < cLeaves
1023	&& paLeaves[iEnd].uLeaf <= uLast)
1024	iEnd++;
1025
1026	/*
1027	* Adjust the array if anything needs removing.
1028	*/
1029	if (iFirst < iEnd)
1030	{
1031	if (iEnd < cLeaves)
1032	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1033	*pcLeaves = cLeaves -= (iEnd - iFirst);
1034	}
1035
1036	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1037	}
1038	#endif /* IN_VBOX_CPU_REPORT */
1039
1040
1041	/**
1042	* Checks if ECX make a difference when reading a given CPUID leaf.
1043	*
1044	* @returns @c true if it does, @c false if it doesn't.
1045	* @param uLeaf The leaf we're reading.
1046	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1047	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1048	* final sub-leaf (for leaf 0xb only).
1049	*/
1050	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1051	{
1052	*pfFinalEcxUnchanged = false;
1053
1054	uint32_t auCur[4];
1055	uint32_t auPrev[4];
1056	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1057
1058	/* Look for sub-leaves. */
1059	uint32_t uSubLeaf = 1;
1060	for (;;)
1061	{
1062	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1063	if (memcmp(auCur, auPrev, sizeof(auCur)))
1064	break;
1065
1066	/* Advance / give up. */
1067	uSubLeaf++;
1068	if (uSubLeaf >= 64)
1069	{
1070	*pcSubLeaves = 1;
1071	return false;
1072	}
1073	}
1074
1075	/* Count sub-leaves. */
1076	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1077	uint32_t cRepeats = 0;
1078	uSubLeaf = 0;
1079	for (;;)
1080	{
1081	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1082
1083	/* Figuring out when to stop isn't entirely straight forward as we need
1084	to cover undocumented behavior up to a point and implementation shortcuts. */
1085
1086	/* 1. Look for more than 4 repeating value sets. */
1087	if ( auCur[0] == auPrev[0]
1088	&& auCur[1] == auPrev[1]
1089	&& ( auCur[2] == auPrev[2]
1090	\|\| ( auCur[2] == uSubLeaf
1091	&& auPrev[2] == uSubLeaf - 1) )
1092	&& auCur[3] == auPrev[3])
1093	{
1094	if ( uLeaf != 0xd
1095	\|\| uSubLeaf >= 64
1096	\|\| ( auCur[0] == 0
1097	&& auCur[1] == 0
1098	&& auCur[2] == 0
1099	&& auCur[3] == 0
1100	&& auPrev[2] == 0) )
1101	cRepeats++;
1102	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1103	break;
1104	}
1105	else
1106	cRepeats = 0;
1107
1108	/* 2. Look for zero values. */
1109	if ( auCur[0] == 0
1110	&& auCur[1] == 0
1111	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1112	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1113	&& uSubLeaf >= cMinLeaves)
1114	{
1115	cRepeats = 0;
1116	break;
1117	}
1118
1119	/* 3. Leaf 0xb level type 0 check. */
1120	if ( uLeaf == 0xb
1121	&& (auCur[2] & 0xff00) == 0
1122	&& (auPrev[2] & 0xff00) == 0)
1123	{
1124	cRepeats = 0;
1125	break;
1126	}
1127
1128	/* 99. Give up. */
1129	if (uSubLeaf >= 128)
1130	{
1131	#ifndef IN_VBOX_CPU_REPORT
1132	/* Ok, limit it according to the documentation if possible just to
1133	avoid annoying users with these detection issues. */
1134	uint32_t cDocLimit = UINT32_MAX;
1135	if (uLeaf == 0x4)
1136	cDocLimit = 4;
1137	else if (uLeaf == 0x7)
1138	cDocLimit = 1;
1139	else if (uLeaf == 0xd)
1140	cDocLimit = 63;
1141	else if (uLeaf == 0xf)
1142	cDocLimit = 2;
1143	if (cDocLimit != UINT32_MAX)
1144	{
1145	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1146	*pcSubLeaves = cDocLimit + 3;
1147	return true;
1148	}
1149	#endif
1150	*pcSubLeaves = UINT32_MAX;
1151	return true;
1152	}
1153
1154	/* Advance. */
1155	uSubLeaf++;
1156	memcpy(auPrev, auCur, sizeof(auCur));
1157	}
1158
1159	/* Standard exit. */
1160	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1161	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1162	if (*pcSubLeaves == 0)
1163	*pcSubLeaves = 1;
1164	return true;
1165	}
1166
1167
1168	/**
1169	* Gets a CPU ID leaf.
1170	*
1171	* @returns VBox status code.
1172	* @param pVM The cross context VM structure.
1173	* @param pLeaf Where to store the found leaf.
1174	* @param uLeaf The leaf to locate.
1175	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1176	*/
1177	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1178	{
1179	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1180	uLeaf, uSubLeaf);
1181	if (pcLeaf)
1182	{
1183	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1184	return VINF_SUCCESS;
1185	}
1186
1187	return VERR_NOT_FOUND;
1188	}
1189
1190
1191	/**
1192	* Inserts a CPU ID leaf, replacing any existing ones.
1193	*
1194	* @returns VBox status code.
1195	* @param pVM The cross context VM structure.
1196	* @param pNewLeaf Pointer to the leaf being inserted.
1197	*/
1198	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1199	{
1200	/*
1201	* Validate parameters.
1202	*/
1203	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1204	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1205
1206	/*
1207	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1208	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1209	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1210	*/
1211	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1212	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1213	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1214	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1215	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1216	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1217	{
1218	return VERR_NOT_SUPPORTED;
1219	}
1220
1221	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1222	}
1223
1224	/**
1225	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1226	*
1227	* @returns VBox status code.
1228	* @param ppaLeaves Where to return the array pointer on success.
1229	* Use RTMemFree to release.
1230	* @param pcLeaves Where to return the size of the array on
1231	* success.
1232	*/
1233	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1234	{
1235	*ppaLeaves = NULL;
1236	*pcLeaves = 0;
1237
1238	/*
1239	* Try out various candidates. This must be sorted!
1240	*/
1241	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1242	{
1243	{ UINT32_C(0x00000000), false },
1244	{ UINT32_C(0x10000000), false },
1245	{ UINT32_C(0x20000000), false },
1246	{ UINT32_C(0x30000000), false },
1247	{ UINT32_C(0x40000000), false },
1248	{ UINT32_C(0x50000000), false },
1249	{ UINT32_C(0x60000000), false },
1250	{ UINT32_C(0x70000000), false },
1251	{ UINT32_C(0x80000000), false },
1252	{ UINT32_C(0x80860000), false },
1253	{ UINT32_C(0x8ffffffe), true },
1254	{ UINT32_C(0x8fffffff), true },
1255	{ UINT32_C(0x90000000), false },
1256	{ UINT32_C(0xa0000000), false },
1257	{ UINT32_C(0xb0000000), false },
1258	{ UINT32_C(0xc0000000), false },
1259	{ UINT32_C(0xd0000000), false },
1260	{ UINT32_C(0xe0000000), false },
1261	{ UINT32_C(0xf0000000), false },
1262	};
1263
1264	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1265	{
1266	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1267	uint32_t uEax, uEbx, uEcx, uEdx;
1268	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1269
1270	/*
1271	* Does EAX look like a typical leaf count value?
1272	*/
1273	if ( uEax > uLeaf
1274	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1275	{
1276	/* Yes, dump them. */
1277	uint32_t cLeaves = uEax - uLeaf + 1;
1278	while (cLeaves-- > 0)
1279	{
1280	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1281
1282	uint32_t fFlags = 0;
1283
1284	/* There are currently three known leaves containing an APIC ID
1285	that needs EMT specific attention */
1286	if (uLeaf == 1)
1287	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1288	else if (uLeaf == 0xb && uEcx != 0)
1289	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1290	else if ( uLeaf == UINT32_C(0x8000001e)
1291	&& ( uEax
1292	\|\| uEbx
1293	\|\| uEdx
1294	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1295	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1296
1297	/* The APIC bit is per-VCpu and needs flagging. */
1298	if (uLeaf == 1)
1299	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1300	else if ( uLeaf == UINT32_C(0x80000001)
1301	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1302	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1303	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1304
1305	/* Check three times here to reduce the chance of CPU migration
1306	resulting in false positives with things like the APIC ID. */
1307	uint32_t cSubLeaves;
1308	bool fFinalEcxUnchanged;
1309	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1310	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1311	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1312	{
1313	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1314	{
1315	/* This shouldn't happen. But in case it does, file all
1316	relevant details in the release log. */
1317	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1318	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1319	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1320	{
1321	uint32_t auTmp[4];
1322	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1323	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1324	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1325	}
1326	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1327	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1328	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1329	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1330	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1331	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1332	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1333	}
1334
1335	if (fFinalEcxUnchanged)
1336	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1337
1338	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1339	{
1340	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1341	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1342	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1343	if (RT_FAILURE(rc))
1344	return rc;
1345	}
1346	}
1347	else
1348	{
1349	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1350	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1351	if (RT_FAILURE(rc))
1352	return rc;
1353	}
1354
1355	/* next */
1356	uLeaf++;
1357	}
1358	}
1359	/*
1360	* Special CPUIDs needs special handling as they don't follow the
1361	* leaf count principle used above.
1362	*/
1363	else if (s_aCandidates[iOuter].fSpecial)
1364	{
1365	bool fKeep = false;
1366	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1367	fKeep = true;
1368	else if ( uLeaf == 0x8fffffff
1369	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1370	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1371	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1372	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1373	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1374	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1375	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1376	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1377	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1378	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1379	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1380	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1381	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1382	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1383	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1384	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1385	fKeep = true;
1386	if (fKeep)
1387	{
1388	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1389	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1390	if (RT_FAILURE(rc))
1391	return rc;
1392	}
1393	}
1394	}
1395
1396	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1397	return VINF_SUCCESS;
1398	}
1399
1400
1401	/**
1402	* Determines the method the CPU uses to handle unknown CPUID leaves.
1403	*
1404	* @returns VBox status code.
1405	* @param penmUnknownMethod Where to return the method.
1406	* @param pDefUnknown Where to return default unknown values. This
1407	* will be set, even if the resulting method
1408	* doesn't actually needs it.
1409	*/
1410	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1411	{
1412	uint32_t uLastStd = ASMCpuId_EAX(0);
1413	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1414	if (!ASMIsValidExtRange(uLastExt))
1415	uLastExt = 0x80000000;
1416
1417	uint32_t auChecks[] =
1418	{
1419	uLastStd + 1,
1420	uLastStd + 5,
1421	uLastStd + 8,
1422	uLastStd + 32,
1423	uLastStd + 251,
1424	uLastExt + 1,
1425	uLastExt + 8,
1426	uLastExt + 15,
1427	uLastExt + 63,
1428	uLastExt + 255,
1429	0x7fbbffcc,
1430	0x833f7872,
1431	0xefff2353,
1432	0x35779456,
1433	0x1ef6d33e,
1434	};
1435
1436	static const uint32_t s_auValues[] =
1437	{
1438	0xa95d2156,
1439	0x00000001,
1440	0x00000002,
1441	0x00000008,
1442	0x00000000,
1443	0x55773399,
1444	0x93401769,
1445	0x12039587,
1446	};
1447
1448	/*
1449	* Simple method, all zeros.
1450	*/
1451	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1452	pDefUnknown->uEax = 0;
1453	pDefUnknown->uEbx = 0;
1454	pDefUnknown->uEcx = 0;
1455	pDefUnknown->uEdx = 0;
1456
1457	/*
1458	* Intel has been observed returning the last standard leaf.
1459	*/
1460	uint32_t auLast[4];
1461	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1462
1463	uint32_t cChecks = RT_ELEMENTS(auChecks);
1464	while (cChecks > 0)
1465	{
1466	uint32_t auCur[4];
1467	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1468	if (memcmp(auCur, auLast, sizeof(auCur)))
1469	break;
1470	cChecks--;
1471	}
1472	if (cChecks == 0)
1473	{
1474	/* Now, what happens when the input changes? Esp. ECX. */
1475	uint32_t cTotal = 0;
1476	uint32_t cSame = 0;
1477	uint32_t cLastWithEcx = 0;
1478	uint32_t cNeither = 0;
1479	uint32_t cValues = RT_ELEMENTS(s_auValues);
1480	while (cValues > 0)
1481	{
1482	uint32_t uValue = s_auValues[cValues - 1];
1483	uint32_t auLastWithEcx[4];
1484	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1485	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1486
1487	cChecks = RT_ELEMENTS(auChecks);
1488	while (cChecks > 0)
1489	{
1490	uint32_t auCur[4];
1491	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1492	if (!memcmp(auCur, auLast, sizeof(auCur)))
1493	{
1494	cSame++;
1495	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1496	cLastWithEcx++;
1497	}
1498	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1499	cLastWithEcx++;
1500	else
1501	cNeither++;
1502	cTotal++;
1503	cChecks--;
1504	}
1505	cValues--;
1506	}
1507
1508	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1509	if (cSame == cTotal)
1510	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1511	else if (cLastWithEcx == cTotal)
1512	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1513	else
1514	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1515	pDefUnknown->uEax = auLast[0];
1516	pDefUnknown->uEbx = auLast[1];
1517	pDefUnknown->uEcx = auLast[2];
1518	pDefUnknown->uEdx = auLast[3];
1519	return VINF_SUCCESS;
1520	}
1521
1522	/*
1523	* Unchanged register values?
1524	*/
1525	cChecks = RT_ELEMENTS(auChecks);
1526	while (cChecks > 0)
1527	{
1528	uint32_t const uLeaf = auChecks[cChecks - 1];
1529	uint32_t cValues = RT_ELEMENTS(s_auValues);
1530	while (cValues > 0)
1531	{
1532	uint32_t uValue = s_auValues[cValues - 1];
1533	uint32_t auCur[4];
1534	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1535	if ( auCur[0] != uLeaf
1536	\|\| auCur[1] != uValue
1537	\|\| auCur[2] != uValue
1538	\|\| auCur[3] != uValue)
1539	break;
1540	cValues--;
1541	}
1542	if (cValues != 0)
1543	break;
1544	cChecks--;
1545	}
1546	if (cChecks == 0)
1547	{
1548	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1549	return VINF_SUCCESS;
1550	}
1551
1552	/*
1553	* Just go with the simple method.
1554	*/
1555	return VINF_SUCCESS;
1556	}
1557
1558
1559	/**
1560	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1561	*
1562	* @returns Read only name string.
1563	* @param enmUnknownMethod The method to translate.
1564	*/
1565	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1566	{
1567	switch (enmUnknownMethod)
1568	{
1569	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1570	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1571	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1572	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1573
1574	case CPUMUNKNOWNCPUID_INVALID:
1575	case CPUMUNKNOWNCPUID_END:
1576	case CPUMUNKNOWNCPUID_32BIT_HACK:
1577	break;
1578	}
1579	return "Invalid-unknown-CPUID-method";
1580	}
1581
1582
1583	/**
1584	* Detect the CPU vendor give n the
1585	*
1586	* @returns The vendor.
1587	* @param uEAX EAX from CPUID(0).
1588	* @param uEBX EBX from CPUID(0).
1589	* @param uECX ECX from CPUID(0).
1590	* @param uEDX EDX from CPUID(0).
1591	*/
1592	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1593	{
1594	if (ASMIsValidStdRange(uEAX))
1595	{
1596	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1597	return CPUMCPUVENDOR_AMD;
1598
1599	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1600	return CPUMCPUVENDOR_INTEL;
1601
1602	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1603	return CPUMCPUVENDOR_VIA;
1604
1605	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1606	&& uECX == UINT32_C(0x64616574)
1607	&& uEDX == UINT32_C(0x736E4978))
1608	return CPUMCPUVENDOR_CYRIX;
1609
1610	/* "Geode by NSC", example: family 5, model 9. */
1611
1612	/** @todo detect the other buggers... */
1613	}
1614
1615	return CPUMCPUVENDOR_UNKNOWN;
1616	}
1617
1618
1619	/**
1620	* Translates a CPU vendor enum value into the corresponding string constant.
1621	*
1622	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1623	* value name. This can be useful when generating code.
1624	*
1625	* @returns Read only name string.
1626	* @param enmVendor The CPU vendor value.
1627	*/
1628	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1629	{
1630	switch (enmVendor)
1631	{
1632	case CPUMCPUVENDOR_INTEL: return "INTEL";
1633	case CPUMCPUVENDOR_AMD: return "AMD";
1634	case CPUMCPUVENDOR_VIA: return "VIA";
1635	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1636	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1637
1638	case CPUMCPUVENDOR_INVALID:
1639	case CPUMCPUVENDOR_32BIT_HACK:
1640	break;
1641	}
1642	return "Invalid-cpu-vendor";
1643	}
1644
1645
1646	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1647	{
1648	/* Could do binary search, doing linear now because I'm lazy. */
1649	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1650	while (cLeaves-- > 0)
1651	{
1652	if (pLeaf->uLeaf == uLeaf)
1653	return pLeaf;
1654	pLeaf++;
1655	}
1656	return NULL;
1657	}
1658
1659
1660	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1661	{
1662	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1663	if ( !pLeaf
1664	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1665	return pLeaf;
1666
1667	/* Linear sub-leaf search. Lazy as usual. */
1668	cLeaves -= pLeaf - paLeaves;
1669	while ( cLeaves-- > 0
1670	&& pLeaf->uLeaf == uLeaf)
1671	{
1672	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1673	return pLeaf;
1674	pLeaf++;
1675	}
1676
1677	return NULL;
1678	}
1679
1680
1681	static void cpumR3ExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, PCPUMFEATURES pFeatures)
1682	{
1683	Assert(pVmxMsrs);
1684	Assert(pFeatures);
1685	Assert(pFeatures->fVmx);
1686
1687	/* Basic information. */
1688	{
1689	uint64_t const u64Basic = pVmxMsrs->u64Basic;
1690	pFeatures->fVmxInsOutInfo = RT_BF_GET(u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1691	}
1692
1693	/* Pin-based VM-execution controls. */
1694	{
1695	uint32_t const fPinCtls = pVmxMsrs->PinCtls.n.allowed1;
1696	pFeatures->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1697	pFeatures->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1698	pFeatures->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1699	pFeatures->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1700	pFeatures->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1701	}
1702
1703	/* Processor-based VM-execution controls. */
1704	{
1705	uint32_t const fProcCtls = pVmxMsrs->ProcCtls.n.allowed1;
1706	pFeatures->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1707	pFeatures->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1708	pFeatures->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1709	pFeatures->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1710	pFeatures->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1711	pFeatures->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1712	pFeatures->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1713	pFeatures->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1714	pFeatures->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1715	pFeatures->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1716	pFeatures->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1717	pFeatures->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1718	pFeatures->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1719	pFeatures->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1720	pFeatures->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1721	pFeatures->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1722	pFeatures->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1723	pFeatures->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1724	pFeatures->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1725	pFeatures->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1726	pFeatures->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1727	}
1728
1729	/* Secondary processor-based VM-execution controls. */
1730	{
1731	uint32_t const fProcCtls2 = pFeatures->fVmxSecondaryExecCtls ? pVmxMsrs->ProcCtls2.n.allowed1 : 0;
1732	pFeatures->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1733	pFeatures->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1734	pFeatures->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1735	pFeatures->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1736	pFeatures->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1737	pFeatures->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1738	pFeatures->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1739	pFeatures->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1740	pFeatures->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1741	pFeatures->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1742	pFeatures->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1743	pFeatures->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1744	pFeatures->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1745	pFeatures->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1746	pFeatures->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1747	pFeatures->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1748	pFeatures->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1749	pFeatures->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_VE);
1750	pFeatures->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1751	pFeatures->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1752	}
1753
1754	/* VM-exit controls. */
1755	{
1756	uint32_t const fExitCtls = pVmxMsrs->ExitCtls.n.allowed1;
1757	pFeatures->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1758	pFeatures->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1759	pFeatures->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1760	pFeatures->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1761	pFeatures->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1762	pFeatures->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1763	pFeatures->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1764	pFeatures->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1765	}
1766
1767	/* VM-entry controls. */
1768	{
1769	uint32_t const fEntryCtls = pVmxMsrs->EntryCtls.n.allowed1;
1770	pFeatures->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1771	pFeatures->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1772	pFeatures->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1773	pFeatures->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1774	}
1775
1776	/* Miscellaneous data. */
1777	{
1778	uint32_t const fMiscData = pVmxMsrs->u64Misc;
1779	pFeatures->fVmxExitSaveEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_SAVE_EFER_LMA);
1780	pFeatures->fVmxIntelPt = RT_BOOL(fMiscData & VMX_MISC_INTEL_PT);
1781	pFeatures->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1782	pFeatures->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1783	}
1784	}
1785
1786
1787	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures)
1788	{
1789	Assert(pMsrs);
1790	RT_ZERO(*pFeatures);
1791	if (cLeaves >= 2)
1792	{
1793	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1794	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1795	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1796	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1797	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1798	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1799
1800	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1801	pStd0Leaf->uEbx,
1802	pStd0Leaf->uEcx,
1803	pStd0Leaf->uEdx);
1804	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1805	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1806	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1807	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1808	pFeatures->uFamily,
1809	pFeatures->uModel,
1810	pFeatures->uStepping);
1811
1812	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1813	if (pExtLeaf8)
1814	{
1815	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1816	pFeatures->cMaxLinearAddrWidth = (pExtLeaf8->uEax >> 8) & 0xff;
1817	}
1818	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1819	{
1820	pFeatures->cMaxPhysAddrWidth = 36;
1821	pFeatures->cMaxLinearAddrWidth = 36;
1822	}
1823	else
1824	{
1825	pFeatures->cMaxPhysAddrWidth = 32;
1826	pFeatures->cMaxLinearAddrWidth = 32;
1827	}
1828
1829	/* Standard features. */
1830	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1831	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1832	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1833	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1834	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1835	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1836	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1837	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1838	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1839	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1840	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1841	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1842	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1843	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1844	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1845	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1846	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1847	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1848	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1849	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1850	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1851	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1852	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1853	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1854	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1855	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1856	if (pFeatures->fVmx)
1857	cpumR3ExplodeVmxFeatures(&pMsrs->hwvirt.vmx, pFeatures);
1858
1859	/* Structured extended features. */
1860	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1861	if (pSxfLeaf0)
1862	{
1863	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1864	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1865	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1866	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1867	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1868
1869	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1870	pFeatures->fIbrs = pFeatures->fIbpb;
1871	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1872	#if 0 // Disabled until IA32_ARCH_CAPABILITIES support can be tested
1873	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1874	#endif
1875	}
1876
1877	/* MWAIT/MONITOR leaf. */
1878	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1879	if (pMWaitLeaf)
1880	{
1881	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1882	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1883	}
1884
1885	/* Extended features. */
1886	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1887	if (pExtLeaf)
1888	{
1889	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1890	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1891	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1892	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1893	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1894	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1895	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1896	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1897	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1898	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1899	}
1900
1901	/* VMX (VMXON, VMCS region and related data structures') physical address width (depends on long-mode). */
1902	pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
1903
1904	if ( pExtLeaf
1905	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1906	{
1907	/* AMD features. */
1908	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1909	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1910	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1911	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1912	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1913	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1914	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1915	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1916	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1917	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1918	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1919	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1920	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1921	if (pFeatures->fSvm)
1922	{
1923	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1924	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1925	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1926	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1927	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1928	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1929	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1930	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1931	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1932	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1933	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1934	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1935	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1936	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1937	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1938	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1939	}
1940	}
1941
1942	/*
1943	* Quirks.
1944	*/
1945	pFeatures->fLeakyFxSR = pExtLeaf
1946	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1947	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1948	&& pFeatures->uFamily >= 6 /* K7 and up */;
1949
1950	/*
1951	* Max extended (/FPU) state.
1952	*/
1953	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1954	if (pFeatures->fXSaveRstor)
1955	{
1956	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1957	if (pXStateLeaf0)
1958	{
1959	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1960	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1961	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1962	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1963	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1964	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1965	{
1966	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1967
1968	/* (paranoia:) */
1969	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1970	if ( pXStateLeaf1
1971	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1972	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1973	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1974	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
1975	}
1976	else
1977	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1978	pFeatures->fXSaveRstor = 0);
1979	}
1980	else
1981	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1982	pFeatures->fXSaveRstor = 0);
1983	}
1984	}
1985	else
1986	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1987	return VINF_SUCCESS;
1988	}
1989
1990
1991	/*
1992	*
1993	* Init related code.
1994	* Init related code.
1995	* Init related code.
1996	*
1997	*
1998	*/
1999	#ifdef VBOX_IN_VMM
2000
2001
2002	/**
2003	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
2004	*
2005	* This ignores the fSubLeafMask.
2006	*
2007	* @returns Pointer to the matching leaf, or NULL if not found.
2008	* @param paLeaves The CPUID leaves to search. This is sorted.
2009	* @param cLeaves The number of leaves in the array.
2010	* @param uLeaf The leaf to locate.
2011	* @param uSubLeaf The subleaf to locate.
2012	*/
2013	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
2014	{
2015	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
2016	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
2017	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
2018	if (iEnd)
2019	{
2020	uint32_t iBegin = 0;
2021	for (;;)
2022	{
2023	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
2024	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
2025	if (uNeedle < uCur)
2026	{
2027	if (i > iBegin)
2028	iEnd = i;
2029	else
2030	break;
2031	}
2032	else if (uNeedle > uCur)
2033	{
2034	if (i + 1 < iEnd)
2035	iBegin = i + 1;
2036	else
2037	break;
2038	}
2039	else
2040	return &paLeaves[i];
2041	}
2042	}
2043	return NULL;
2044	}
2045
2046
2047	/**
2048	* Loads MSR range overrides.
2049	*
2050	* This must be called before the MSR ranges are moved from the normal heap to
2051	* the hyper heap!
2052	*
2053	* @returns VBox status code (VMSetError called).
2054	* @param pVM The cross context VM structure.
2055	* @param pMsrNode The CFGM node with the MSR overrides.
2056	*/
2057	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
2058	{
2059	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2060	{
2061	/*
2062	* Assemble a valid MSR range.
2063	*/
2064	CPUMMSRRANGE MsrRange;
2065	MsrRange.offCpumCpu = 0;
2066	MsrRange.fReserved = 0;
2067
2068	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
2069	if (RT_FAILURE(rc))
2070	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
2071
2072	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
2073	if (RT_FAILURE(rc))
2074	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
2075	MsrRange.szName, rc);
2076
2077	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
2078	if (RT_FAILURE(rc))
2079	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
2080	MsrRange.szName, rc);
2081
2082	char szType[32];
2083	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
2084	if (RT_FAILURE(rc))
2085	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
2086	MsrRange.szName, rc);
2087	if (!RTStrICmp(szType, "FixedValue"))
2088	{
2089	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
2090	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
2091
2092	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
2093	if (RT_FAILURE(rc))
2094	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
2095	MsrRange.szName, rc);
2096
2097	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
2098	if (RT_FAILURE(rc))
2099	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
2100	MsrRange.szName, rc);
2101
2102	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
2103	if (RT_FAILURE(rc))
2104	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
2105	MsrRange.szName, rc);
2106	}
2107	else
2108	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
2109	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
2110
2111	/*
2112	* Insert the range into the table (replaces/splits/shrinks existing
2113	* MSR ranges).
2114	*/
2115	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
2116	&MsrRange);
2117	if (RT_FAILURE(rc))
2118	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
2119	}
2120
2121	return VINF_SUCCESS;
2122	}
2123
2124
2125	/**
2126	* Loads CPUID leaf overrides.
2127	*
2128	* This must be called before the CPUID leaves are moved from the normal
2129	* heap to the hyper heap!
2130	*
2131	* @returns VBox status code (VMSetError called).
2132	* @param pVM The cross context VM structure.
2133	* @param pParentNode The CFGM node with the CPUID leaves.
2134	* @param pszLabel How to label the overrides we're loading.
2135	*/
2136	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2137	{
2138	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2139	{
2140	/*
2141	* Get the leaf and subleaf numbers.
2142	*/
2143	char szName[128];
2144	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2145	if (RT_FAILURE(rc))
2146	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2147
2148	/* The leaf number is either specified directly or thru the node name. */
2149	uint32_t uLeaf;
2150	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2151	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2152	{
2153	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2154	if (rc != VINF_SUCCESS)
2155	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2156	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2157	}
2158	else if (RT_FAILURE(rc))
2159	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2160	pszLabel, szName, rc);
2161
2162	uint32_t uSubLeaf;
2163	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2164	if (RT_FAILURE(rc))
2165	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2166	pszLabel, szName, rc);
2167
2168	uint32_t fSubLeafMask;
2169	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2170	if (RT_FAILURE(rc))
2171	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2172	pszLabel, szName, rc);
2173
2174	/*
2175	* Look up the specified leaf, since the output register values
2176	* defaults to any existing values. This allows overriding a single
2177	* register, without needing to know the other values.
2178	*/
2179	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2180	CPUMCPUIDLEAF Leaf;
2181	if (pLeaf)
2182	Leaf = *pLeaf;
2183	else
2184	RT_ZERO(Leaf);
2185	Leaf.uLeaf = uLeaf;
2186	Leaf.uSubLeaf = uSubLeaf;
2187	Leaf.fSubLeafMask = fSubLeafMask;
2188
2189	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2190	if (RT_FAILURE(rc))
2191	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2192	pszLabel, szName, rc);
2193	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2194	if (RT_FAILURE(rc))
2195	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2196	pszLabel, szName, rc);
2197	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2198	if (RT_FAILURE(rc))
2199	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2200	pszLabel, szName, rc);
2201	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2202	if (RT_FAILURE(rc))
2203	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2204	pszLabel, szName, rc);
2205
2206	/*
2207	* Insert the leaf into the table (replaces existing ones).
2208	*/
2209	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2210	&Leaf);
2211	if (RT_FAILURE(rc))
2212	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2213	}
2214
2215	return VINF_SUCCESS;
2216	}
2217
2218
2219
2220	/**
2221	* Fetches overrides for a CPUID leaf.
2222	*
2223	* @returns VBox status code.
2224	* @param pLeaf The leaf to load the overrides into.
2225	* @param pCfgNode The CFGM node containing the overrides
2226	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2227	* @param iLeaf The CPUID leaf number.
2228	*/
2229	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2230	{
2231	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2232	if (pLeafNode)
2233	{
2234	uint32_t u32;
2235	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2236	if (RT_SUCCESS(rc))
2237	pLeaf->uEax = u32;
2238	else
2239	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2240
2241	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2242	if (RT_SUCCESS(rc))
2243	pLeaf->uEbx = u32;
2244	else
2245	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2246
2247	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2248	if (RT_SUCCESS(rc))
2249	pLeaf->uEcx = u32;
2250	else
2251	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2252
2253	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2254	if (RT_SUCCESS(rc))
2255	pLeaf->uEdx = u32;
2256	else
2257	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2258
2259	}
2260	return VINF_SUCCESS;
2261	}
2262
2263
2264	/**
2265	* Load the overrides for a set of CPUID leaves.
2266	*
2267	* @returns VBox status code.
2268	* @param paLeaves The leaf array.
2269	* @param cLeaves The number of leaves.
2270	* @param uStart The start leaf number.
2271	* @param pCfgNode The CFGM node containing the overrides
2272	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2273	*/
2274	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2275	{
2276	for (uint32_t i = 0; i < cLeaves; i++)
2277	{
2278	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2279	if (RT_FAILURE(rc))
2280	return rc;
2281	}
2282
2283	return VINF_SUCCESS;
2284	}
2285
2286
2287	/**
2288	* Installs the CPUID leaves and explods the data into structures like
2289	* GuestFeatures and CPUMCTX::aoffXState.
2290	*
2291	* @returns VBox status code.
2292	* @param pVM The cross context VM structure.
2293	* @param pCpum The CPUM part of @a VM.
2294	* @param paLeaves The leaves. These will be copied (but not freed).
2295	* @param cLeaves The number of leaves.
2296	* @param pMsrs The MSRs.
2297	*/
2298	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
2299	{
2300	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2301
2302	/*
2303	* Install the CPUID information.
2304	*/
2305	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2306	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2307
2308	AssertLogRelRCReturn(rc, rc);
2309	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2310	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2311	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2312	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2313	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2314
2315	/*
2316	* Update the default CPUID leaf if necessary.
2317	*/
2318	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2319	{
2320	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2321	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2322	{
2323	/* We don't use CPUID(0).eax here because of the NT hack that only
2324	changes that value without actually removing any leaves. */
2325	uint32_t i = 0;
2326	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2327	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2328	{
2329	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2330	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2331	i++;
2332	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2333	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2334	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2335	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2336	}
2337	break;
2338	}
2339	default:
2340	break;
2341	}
2342
2343	/*
2344	* Explode the guest CPU features.
2345	*/
2346	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
2347	&pCpum->GuestFeatures);
2348	AssertLogRelRCReturn(rc, rc);
2349
2350	/*
2351	* Adjust the scalable bus frequency according to the CPUID information
2352	* we're now using.
2353	*/
2354	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2355	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2356	? UINT64_C(100000000) /* 100MHz */
2357	: UINT64_C(133333333); /* 133MHz */
2358
2359	/*
2360	* Populate the legacy arrays. Currently used for everything, later only
2361	* for patch manager.
2362	*/
2363	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2364	{
2365	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2366	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2367	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2368	};
2369	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2370	{
2371	uint32_t cLeft = aOldRanges[i].cCpuIds;
2372	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2373	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2374	while (cLeft-- > 0)
2375	{
2376	uLeaf--;
2377	pLegacyLeaf--;
2378
2379	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2380	if (pLeaf)
2381	{
2382	pLegacyLeaf->uEax = pLeaf->uEax;
2383	pLegacyLeaf->uEbx = pLeaf->uEbx;
2384	pLegacyLeaf->uEcx = pLeaf->uEcx;
2385	pLegacyLeaf->uEdx = pLeaf->uEdx;
2386	}
2387	else
2388	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2389	}
2390	}
2391
2392	/*
2393	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2394	*/
2395	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2396	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2397	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2398	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2399	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2400	{
2401	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2402	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2403	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2404	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2405	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2406	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2407	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2408	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2409	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2410	pCpum->GuestFeatures.cbMaxExtendedState),
2411	VERR_CPUM_IPE_1);
2412	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2413	}
2414	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2415
2416	/* Copy the CPU #0 data to the other CPUs. */
2417	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2418	{
2419	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2420	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2421	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2422	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2423	}
2424
2425	return VINF_SUCCESS;
2426	}
2427
2428
2429	/** @name Instruction Set Extension Options
2430	* @{ */
2431	/** Configuration option type (extended boolean, really). */
2432	typedef uint8_t CPUMISAEXTCFG;
2433	/** Always disable the extension. */
2434	#define CPUMISAEXTCFG_DISABLED false
2435	/** Enable the extension if it's supported by the host CPU. */
2436	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2437	/** Enable the extension if it's supported by the host CPU, but don't let
2438	* the portable CPUID feature disable it. */
2439	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2440	/** Always enable the extension. */
2441	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2442	/** @} */
2443
2444	/**
2445	* CPUID Configuration (from CFGM).
2446	*
2447	* @remarks The members aren't document since we would only be duplicating the
2448	* \@cfgm entries in cpumR3CpuIdReadConfig.
2449	*/
2450	typedef struct CPUMCPUIDCONFIG
2451	{
2452	bool fNt4LeafLimit;
2453	bool fInvariantTsc;
2454	bool fForceVme;
2455	bool fNestedHWVirt;
2456
2457	CPUMISAEXTCFG enmCmpXchg16b;
2458	CPUMISAEXTCFG enmMonitor;
2459	CPUMISAEXTCFG enmMWaitExtensions;
2460	CPUMISAEXTCFG enmSse41;
2461	CPUMISAEXTCFG enmSse42;
2462	CPUMISAEXTCFG enmAvx;
2463	CPUMISAEXTCFG enmAvx2;
2464	CPUMISAEXTCFG enmXSave;
2465	CPUMISAEXTCFG enmAesNi;
2466	CPUMISAEXTCFG enmPClMul;
2467	CPUMISAEXTCFG enmPopCnt;
2468	CPUMISAEXTCFG enmMovBe;
2469	CPUMISAEXTCFG enmRdRand;
2470	CPUMISAEXTCFG enmRdSeed;
2471	CPUMISAEXTCFG enmCLFlushOpt;
2472	CPUMISAEXTCFG enmFsGsBase;
2473	CPUMISAEXTCFG enmPcid;
2474	CPUMISAEXTCFG enmInvpcid;
2475
2476	CPUMISAEXTCFG enmAbm;
2477	CPUMISAEXTCFG enmSse4A;
2478	CPUMISAEXTCFG enmMisAlnSse;
2479	CPUMISAEXTCFG enm3dNowPrf;
2480	CPUMISAEXTCFG enmAmdExtMmx;
2481
2482	uint32_t uMaxStdLeaf;
2483	uint32_t uMaxExtLeaf;
2484	uint32_t uMaxCentaurLeaf;
2485	uint32_t uMaxIntelFamilyModelStep;
2486	char szCpuName[128];
2487	} CPUMCPUIDCONFIG;
2488	/** Pointer to CPUID config (from CFGM). */
2489	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2490
2491
2492	/**
2493	* Mini CPU selection support for making Mac OS X happy.
2494	*
2495	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2496	*
2497	* @param pCpum The CPUM instance data.
2498	* @param pConfig The CPUID configuration we've read from CFGM.
2499	*/
2500	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2501	{
2502	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2503	{
2504	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2505	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2506	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2507	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2508	0);
2509	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2510	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2511	{
2512	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2513	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2514	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2515	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2516	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2517	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2518	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2519	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2520	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2521	pStdFeatureLeaf->uEax = uNew;
2522	}
2523	}
2524	}
2525
2526
2527
2528	/**
2529	* Limit it the number of entries, zapping the remainder.
2530	*
2531	* The limits are masking off stuff about power saving and similar, this
2532	* is perhaps a bit crudely done as there is probably some relatively harmless
2533	* info too in these leaves (like words about having a constant TSC).
2534	*
2535	* @param pCpum The CPUM instance data.
2536	* @param pConfig The CPUID configuration we've read from CFGM.
2537	*/
2538	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2539	{
2540	/*
2541	* Standard leaves.
2542	*/
2543	uint32_t uSubLeaf = 0;
2544	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2545	if (pCurLeaf)
2546	{
2547	uint32_t uLimit = pCurLeaf->uEax;
2548	if (uLimit <= UINT32_C(0x000fffff))
2549	{
2550	if (uLimit > pConfig->uMaxStdLeaf)
2551	{
2552	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2553	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2554	uLimit + 1, UINT32_C(0x000fffff));
2555	}
2556
2557	/* NT4 hack, no zapping of extra leaves here. */
2558	if (pConfig->fNt4LeafLimit && uLimit > 3)
2559	pCurLeaf->uEax = uLimit = 3;
2560
2561	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2562	pCurLeaf->uEax = uLimit;
2563	}
2564	else
2565	{
2566	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2567	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2568	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2569	}
2570	}
2571
2572	/*
2573	* Extended leaves.
2574	*/
2575	uSubLeaf = 0;
2576	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2577	if (pCurLeaf)
2578	{
2579	uint32_t uLimit = pCurLeaf->uEax;
2580	if ( uLimit >= UINT32_C(0x80000000)
2581	&& uLimit <= UINT32_C(0x800fffff))
2582	{
2583	if (uLimit > pConfig->uMaxExtLeaf)
2584	{
2585	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2586	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2587	uLimit + 1, UINT32_C(0x800fffff));
2588	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2589	pCurLeaf->uEax = uLimit;
2590	}
2591	}
2592	else
2593	{
2594	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2595	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2596	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2597	}
2598	}
2599
2600	/*
2601	* Centaur leaves (VIA).
2602	*/
2603	uSubLeaf = 0;
2604	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2605	if (pCurLeaf)
2606	{
2607	uint32_t uLimit = pCurLeaf->uEax;
2608	if ( uLimit >= UINT32_C(0xc0000000)
2609	&& uLimit <= UINT32_C(0xc00fffff))
2610	{
2611	if (uLimit > pConfig->uMaxCentaurLeaf)
2612	{
2613	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2614	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2615	uLimit + 1, UINT32_C(0xcfffffff));
2616	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2617	pCurLeaf->uEax = uLimit;
2618	}
2619	}
2620	else
2621	{
2622	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2623	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2624	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2625	}
2626	}
2627	}
2628
2629
2630	/**
2631	* Clears a CPUID leaf and all sub-leaves (to zero).
2632	*
2633	* @param pCpum The CPUM instance data.
2634	* @param uLeaf The leaf to clear.
2635	*/
2636	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2637	{
2638	uint32_t uSubLeaf = 0;
2639	PCPUMCPUIDLEAF pCurLeaf;
2640	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2641	{
2642	pCurLeaf->uEax = 0;
2643	pCurLeaf->uEbx = 0;
2644	pCurLeaf->uEcx = 0;
2645	pCurLeaf->uEdx = 0;
2646	uSubLeaf++;
2647	}
2648	}
2649
2650
2651	/**
2652	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2653	* the given leaf.
2654	*
2655	* @returns pLeaf.
2656	* @param pCpum The CPUM instance data.
2657	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2658	*/
2659	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2660	{
2661	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2662	if (pLeaf->fSubLeafMask != 0)
2663	{
2664	/*
2665	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2666	* Log everything while we're at it.
2667	*/
2668	LogRel(("CPUM:\n"
2669	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2670	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2671	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2672	for (;;)
2673	{
2674	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2675	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2676	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2677	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2678	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2679	break;
2680	pSubLeaf++;
2681	}
2682	LogRel(("CPUM:\n"));
2683
2684	/*
2685	* Remove the offending sub-leaves.
2686	*/
2687	if (pSubLeaf != pLeaf)
2688	{
2689	if (pSubLeaf != pLast)
2690	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2691	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2692	}
2693
2694	/*
2695	* Convert the first sub-leaf into a single leaf.
2696	*/
2697	pLeaf->uSubLeaf = 0;
2698	pLeaf->fSubLeafMask = 0;
2699	}
2700	return pLeaf;
2701	}
2702
2703
2704	/**
2705	* Sanitizes and adjust the CPUID leaves.
2706	*
2707	* Drop features that aren't virtualized (or virtualizable). Adjust information
2708	* and capabilities to fit the virtualized hardware. Remove information the
2709	* guest shouldn't have (because it's wrong in the virtual world or because it
2710	* gives away host details) or that we don't have documentation for and no idea
2711	* what means.
2712	*
2713	* @returns VBox status code.
2714	* @param pVM The cross context VM structure (for cCpus).
2715	* @param pCpum The CPUM instance data.
2716	* @param pConfig The CPUID configuration we've read from CFGM.
2717	*/
2718	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2719	{
2720	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2721	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2722	{ \
2723	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2724	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2725	}
2726	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2727	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2728	{ \
2729	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2730	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2731	}
2732	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2733	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2734	&& ((a_pLeafReg) & (fBitMask)) \
2735	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2736	{ \
2737	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2738	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2739	}
2740	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2741
2742	/* Cpuid 1:
2743	* EAX: CPU model, family and stepping.
2744	*
2745	* ECX + EDX: Supported features. Only report features we can support.
2746	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2747	* options may require adjusting (i.e. stripping what was enabled).
2748	*
2749	* EBX: Branding, CLFLUSH line size, logical processors per package and
2750	* initial APIC ID.
2751	*/
2752	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2753	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2754	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2755
2756	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2757	\| X86_CPUID_FEATURE_EDX_VME
2758	\| X86_CPUID_FEATURE_EDX_DE
2759	\| X86_CPUID_FEATURE_EDX_PSE
2760	\| X86_CPUID_FEATURE_EDX_TSC
2761	\| X86_CPUID_FEATURE_EDX_MSR
2762	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2763	\| X86_CPUID_FEATURE_EDX_MCE
2764	\| X86_CPUID_FEATURE_EDX_CX8
2765	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2766	//\| RT_BIT_32(10) - not defined
2767	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2768	//\| X86_CPUID_FEATURE_EDX_SEP
2769	\| X86_CPUID_FEATURE_EDX_MTRR
2770	\| X86_CPUID_FEATURE_EDX_PGE
2771	\| X86_CPUID_FEATURE_EDX_MCA
2772	\| X86_CPUID_FEATURE_EDX_CMOV
2773	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2774	\| X86_CPUID_FEATURE_EDX_PSE36
2775	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2776	\| X86_CPUID_FEATURE_EDX_CLFSH
2777	//\| RT_BIT_32(20) - not defined
2778	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2779	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2780	\| X86_CPUID_FEATURE_EDX_MMX
2781	\| X86_CPUID_FEATURE_EDX_FXSR
2782	\| X86_CPUID_FEATURE_EDX_SSE
2783	\| X86_CPUID_FEATURE_EDX_SSE2
2784	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2785	\| X86_CPUID_FEATURE_EDX_HTT
2786	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2787	//\| RT_BIT_32(30) - not defined
2788	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2789	;
2790	pStdFeatureLeaf->uEcx &= 0
2791	\| X86_CPUID_FEATURE_ECX_SSE3
2792	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2793	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2794	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2795	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2796	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2797	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
2798	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2799	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2800	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2801	\| X86_CPUID_FEATURE_ECX_SSSE3
2802	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2803	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2804	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2805	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2806	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2807	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2808	\| (pConfig->enmPcid ? X86_CPUID_FEATURE_ECX_PCID : 0)
2809	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2810	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2811	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2812	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2813	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2814	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2815	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2816	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2817	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2818	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2819	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2820	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2821	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2822	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2823	;
2824
2825	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2826	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2827	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2828	{
2829	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2830	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2831	}
2832
2833	if (pCpum->u8PortableCpuIdLevel > 0)
2834	{
2835	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2836	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2837	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2838	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2839	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2840	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2841	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2842	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
2843	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2844	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2845	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2846	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2847	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2848	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2849	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2850	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2851	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2852	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2853	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2854	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2855
2856	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2857	\| X86_CPUID_FEATURE_EDX_PSN
2858	\| X86_CPUID_FEATURE_EDX_DS
2859	\| X86_CPUID_FEATURE_EDX_ACPI
2860	\| X86_CPUID_FEATURE_EDX_SS
2861	\| X86_CPUID_FEATURE_EDX_TM
2862	\| X86_CPUID_FEATURE_EDX_PBE
2863	)));
2864	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2865	\| X86_CPUID_FEATURE_ECX_CPLDS
2866	\| X86_CPUID_FEATURE_ECX_AES
2867	\| X86_CPUID_FEATURE_ECX_VMX
2868	\| X86_CPUID_FEATURE_ECX_SMX
2869	\| X86_CPUID_FEATURE_ECX_EST
2870	\| X86_CPUID_FEATURE_ECX_TM2
2871	\| X86_CPUID_FEATURE_ECX_CNTXID
2872	\| X86_CPUID_FEATURE_ECX_FMA
2873	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2874	\| X86_CPUID_FEATURE_ECX_PDCM
2875	\| X86_CPUID_FEATURE_ECX_DCA
2876	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2877	)));
2878	}
2879
2880	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2881	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2882
2883	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2884	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2885	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2886	*/
2887	#ifdef VBOX_WITH_MULTI_CORE
2888	if (pVM->cCpus > 1)
2889	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2890	#endif
2891	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2892	{
2893	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2894	core times the number of CPU cores per processor */
2895	#ifdef VBOX_WITH_MULTI_CORE
2896	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2897	#else
2898	/* Single logical processor in a package. */
2899	pStdFeatureLeaf->uEbx \|= (1 << 16);
2900	#endif
2901	}
2902
2903	uint32_t uMicrocodeRev;
2904	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2905	if (RT_SUCCESS(rc))
2906	{
2907	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2908	}
2909	else
2910	{
2911	uMicrocodeRev = 0;
2912	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2913	}
2914
2915	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2916	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2917	*/
2918	if ( (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen)
2919	&& uMicrocodeRev < 0x8001126
2920	&& !pConfig->fForceVme)
2921	{
2922	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2923	LogRel(("CPUM: Zen VME workaround engaged\n"));
2924	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
2925	}
2926
2927	/* Force standard feature bits. */
2928	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2929	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2930	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2931	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2932	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2933	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2934	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2935	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2936	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2937	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2938	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2939	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2940	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2941	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2942	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2943	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2944	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2945	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2946	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2947	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2948	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2949	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2950
2951	pStdFeatureLeaf = NULL; /* Must refetch! */
2952
2953	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2954	* AMD:
2955	* EAX: CPU model, family and stepping.
2956	*
2957	* ECX + EDX: Supported features. Only report features we can support.
2958	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2959	* options may require adjusting (i.e. stripping what was enabled).
2960	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2961	*
2962	* EBX: Branding ID and package type (or reserved).
2963	*
2964	* Intel and probably most others:
2965	* EAX: 0
2966	* EBX: 0
2967	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2968	*/
2969	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2970	if (pExtFeatureLeaf)
2971	{
2972	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2973
2974	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2975	\| X86_CPUID_AMD_FEATURE_EDX_VME
2976	\| X86_CPUID_AMD_FEATURE_EDX_DE
2977	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2978	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2979	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2980	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2981	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2982	\| X86_CPUID_AMD_FEATURE_EDX_CX8
2983	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2984	//\| RT_BIT_32(10) - reserved
2985	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2986	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2987	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2988	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
2989	\| X86_CPUID_AMD_FEATURE_EDX_PGE
2990	\| X86_CPUID_AMD_FEATURE_EDX_MCA
2991	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
2992	\| X86_CPUID_AMD_FEATURE_EDX_PAT
2993	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
2994	//\| RT_BIT_32(18) - reserved
2995	//\| RT_BIT_32(19) - reserved
2996	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2997	//\| RT_BIT_32(21) - reserved
2998	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
2999	\| X86_CPUID_AMD_FEATURE_EDX_MMX
3000	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
3001	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
3002	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3003	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
3004	//\| RT_BIT_32(28) - reserved
3005	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
3006	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
3007	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
3008	;
3009	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
3010	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
3011	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
3012	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3013	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
3014	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
3015	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
3016	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
3017	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
3018	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
3019	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3020	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
3021	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
3022	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3023	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
3024	//\| RT_BIT_32(14) - reserved
3025	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
3026	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
3027	//\| RT_BIT_32(17) - reserved
3028	//\| RT_BIT_32(18) - reserved
3029	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
3030	//\| RT_BIT_32(20) - reserved
3031	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
3032	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
3033	//\| RT_BIT_32(23) - reserved
3034	//\| RT_BIT_32(24) - reserved
3035	//\| RT_BIT_32(25) - reserved
3036	//\| RT_BIT_32(26) - reserved
3037	//\| RT_BIT_32(27) - reserved
3038	//\| RT_BIT_32(28) - reserved
3039	//\| RT_BIT_32(29) - reserved
3040	//\| RT_BIT_32(30) - reserved
3041	//\| RT_BIT_32(31) - reserved
3042	;
3043	#ifdef VBOX_WITH_MULTI_CORE
3044	if ( pVM->cCpus > 1
3045	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3046	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
3047	#endif
3048
3049	if (pCpum->u8PortableCpuIdLevel > 0)
3050	{
3051	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
3052	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
3053	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
3054	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
3055	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
3056	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
3057	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
3058	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
3059	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
3060	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
3061	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
3062	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
3063	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
3064	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
3065	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
3066	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
3067
3068	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
3069	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3070	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3071	\| X86_CPUID_AMD_FEATURE_ECX_IBS
3072	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3073	\| X86_CPUID_AMD_FEATURE_ECX_WDT
3074	\| X86_CPUID_AMD_FEATURE_ECX_LWP
3075	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
3076	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
3077	\| UINT32_C(0xff964000)
3078	)));
3079	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
3080	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3081	\| RT_BIT(18)
3082	\| RT_BIT(19)
3083	\| RT_BIT(21)
3084	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
3085	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3086	\| RT_BIT(28)
3087	)));
3088	}
3089
3090	/* Force extended feature bits. */
3091	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
3092	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
3093	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
3094	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
3095	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
3096	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
3097	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
3098	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
3099	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3100	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
3101	}
3102	pExtFeatureLeaf = NULL; /* Must refetch! */
3103
3104
3105	/* Cpuid 2:
3106	* Intel: (Nondeterministic) Cache and TLB information
3107	* AMD: Reserved
3108	* VIA: Reserved
3109	* Safe to expose.
3110	*/
3111	uint32_t uSubLeaf = 0;
3112	PCPUMCPUIDLEAF pCurLeaf;
3113	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
3114	{
3115	if ((pCurLeaf->uEax & 0xff) > 1)
3116	{
3117	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
3118	pCurLeaf->uEax &= UINT32_C(0xffffff01);
3119	}
3120	uSubLeaf++;
3121	}
3122
3123	/* Cpuid 3:
3124	* Intel: EAX, EBX - reserved (transmeta uses these)
3125	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3126	* AMD: Reserved
3127	* VIA: Reserved
3128	* Safe to expose
3129	*/
3130	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3131	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3132	{
3133	uSubLeaf = 0;
3134	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3135	{
3136	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3137	if (pCpum->u8PortableCpuIdLevel > 0)
3138	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3139	uSubLeaf++;
3140	}
3141	}
3142
3143	/* Cpuid 4 + ECX:
3144	* Intel: Deterministic Cache Parameters Leaf.
3145	* AMD: Reserved
3146	* VIA: Reserved
3147	* Safe to expose, except for EAX:
3148	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3149	* Bits 31-26: Maximum number of processor cores in this physical package**
3150	* Note: These SMP values are constant regardless of ECX
3151	*/
3152	uSubLeaf = 0;
3153	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3154	{
3155	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3156	#ifdef VBOX_WITH_MULTI_CORE
3157	if ( pVM->cCpus > 1
3158	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3159	{
3160	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3161	/* One logical processor with possibly multiple cores. */
3162	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3163	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3164	}
3165	#endif
3166	uSubLeaf++;
3167	}
3168
3169	/* Cpuid 5: Monitor/mwait Leaf
3170	* Intel: ECX, EDX - reserved
3171	* EAX, EBX - Smallest and largest monitor line size
3172	* AMD: EDX - reserved
3173	* EAX, EBX - Smallest and largest monitor line size
3174	* ECX - extensions (ignored for now)
3175	* VIA: Reserved
3176	* Safe to expose
3177	*/
3178	uSubLeaf = 0;
3179	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3180	{
3181	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3182	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3183	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3184
3185	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3186	if (pConfig->enmMWaitExtensions)
3187	{
3188	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3189	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3190	it shall be part of our power management virtualization model */
3191	#if 0
3192	/* MWAIT sub C-states */
3193	pCurLeaf->uEdx =
3194	(0 << 0) /* 0 in C0 */ \|
3195	(2 << 4) /* 2 in C1 */ \|
3196	(2 << 8) /* 2 in C2 */ \|
3197	(2 << 12) /* 2 in C3 */ \|
3198	(0 << 16) /* 0 in C4 */
3199	;
3200	#endif
3201	}
3202	else
3203	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3204	uSubLeaf++;
3205	}
3206
3207	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3208	* Intel: Various stuff.
3209	* AMD: EAX, EBX, EDX - reserved.
3210	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3211	* present. Same as intel.
3212	* VIA: ??
3213	*
3214	* We clear everything here for now.
3215	*/
3216	cpumR3CpuIdZeroLeaf(pCpum, 6);
3217
3218	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3219	* EAX: Number of sub leaves.
3220	* EBX+ECX+EDX: Feature flags
3221	*
3222	* We only have documentation for one sub-leaf, so clear all other (no need
3223	* to remove them as such, just set them to zero).
3224	*
3225	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3226	* options may require adjusting (i.e. stripping what was enabled).
3227	*/
3228	uSubLeaf = 0;
3229	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3230	{
3231	switch (uSubLeaf)
3232	{
3233	case 0:
3234	{
3235	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3236	pCurLeaf->uEbx &= 0
3237	\| (pConfig->enmFsGsBase ? X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE : 0)
3238	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3239	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3240	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3241	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3242	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
3243	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3244	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3245	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3246	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3247	\| (pConfig->enmInvpcid ? X86_CPUID_STEXT_FEATURE_EBX_INVPCID : 0)
3248	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3249	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3250	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3251	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3252	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3253	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3254	//\| RT_BIT(17) - reserved
3255	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
3256	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3257	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3258	//\| RT_BIT(21) - reserved
3259	//\| RT_BIT(22) - reserved
3260	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
3261	//\| RT_BIT(24) - reserved
3262	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3263	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3264	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3265	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3266	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3267	//\| RT_BIT(30) - reserved
3268	//\| RT_BIT(31) - reserved
3269	;
3270	pCurLeaf->uEcx &= 0
3271	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3272	;
3273	pCurLeaf->uEdx &= 0
3274	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3275	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3276	//\| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT(29)
3277	;
3278
3279	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3280	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3281	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3282	{
3283	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3284	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3285	}
3286
3287	if (pCpum->u8PortableCpuIdLevel > 0)
3288	{
3289	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3290	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3291	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3292	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3293	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3294	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3295	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3296	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3297	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3298	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3299	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3300	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3301	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3302	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3303	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3304	}
3305
3306	/* Force standard feature bits. */
3307	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3308	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3309	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3310	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3311	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3312	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3313	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3314	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3315	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3316	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3317	break;
3318	}
3319
3320	default:
3321	/* Invalid index, all values are zero. */
3322	pCurLeaf->uEax = 0;
3323	pCurLeaf->uEbx = 0;
3324	pCurLeaf->uEcx = 0;
3325	pCurLeaf->uEdx = 0;
3326	break;
3327	}
3328	uSubLeaf++;
3329	}
3330
3331	/* Cpuid 8: Marked as reserved by Intel and AMD.
3332	* We zero this since we don't know what it may have been used for.
3333	*/
3334	cpumR3CpuIdZeroLeaf(pCpum, 8);
3335
3336	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3337	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3338	* EBX, ECX, EDX - reserved.
3339	* AMD: Reserved
3340	* VIA: ??
3341	*
3342	* We zero this.
3343	*/
3344	cpumR3CpuIdZeroLeaf(pCpum, 9);
3345
3346	/* Cpuid 0xa: Architectural Performance Monitor Features
3347	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3348	* EBX, ECX, EDX - reserved.
3349	* AMD: Reserved
3350	* VIA: ??
3351	*
3352	* We zero this, for now at least.
3353	*/
3354	cpumR3CpuIdZeroLeaf(pCpum, 10);
3355
3356	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3357	* Intel: EAX - APCI ID shift right for next level.
3358	* EBX - Factory configured cores/threads at this level.
3359	* ECX - Level number (same as input) and level type (1,2,0).
3360	* EDX - Extended initial APIC ID.
3361	* AMD: Reserved
3362	* VIA: ??
3363	*/
3364	uSubLeaf = 0;
3365	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3366	{
3367	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3368	{
3369	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3370	if (bLevelType == 1)
3371	{
3372	/* Thread level - we don't do threads at the moment. */
3373	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3374	pCurLeaf->uEbx = 1;
3375	}
3376	else if (bLevelType == 2)
3377	{
3378	/* Core level. */
3379	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3380	#ifdef VBOX_WITH_MULTI_CORE
3381	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3382	pCurLeaf->uEax++;
3383	#endif
3384	pCurLeaf->uEbx = pVM->cCpus;
3385	}
3386	else
3387	{
3388	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3389	pCurLeaf->uEax = 0;
3390	pCurLeaf->uEbx = 0;
3391	pCurLeaf->uEcx = 0;
3392	}
3393	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3394	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3395	}
3396	else
3397	{
3398	pCurLeaf->uEax = 0;
3399	pCurLeaf->uEbx = 0;
3400	pCurLeaf->uEcx = 0;
3401	pCurLeaf->uEdx = 0;
3402	}
3403	uSubLeaf++;
3404	}
3405
3406	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3407	* We zero this since we don't know what it may have been used for.
3408	*/
3409	cpumR3CpuIdZeroLeaf(pCpum, 12);
3410
3411	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3412	* ECX=0: EAX - Valid bits in XCR0[31:0].
3413	* EBX - Maximum state size as per current XCR0 value.
3414	* ECX - Maximum state size for all supported features.
3415	* EDX - Valid bits in XCR0[63:32].
3416	* ECX=1: EAX - Various X-features.
3417	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3418	* ECX - Valid bits in IA32_XSS[31:0].
3419	* EDX - Valid bits in IA32_XSS[63:32].
3420	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3421	* if the bit invalid all four registers are set to zero.
3422	* EAX - The state size for this feature.
3423	* EBX - The state byte offset of this feature.
3424	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3425	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3426	*
3427	* Clear them all as we don't currently implement extended CPU state.
3428	*/
3429	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3430	uint64_t fGuestXcr0Mask = 0;
3431	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3432	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3433	{
3434	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3435	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3436	fGuestXcr0Mask \|= XSAVE_C_YMM;
3437	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3438	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3439	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3440	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3441
3442	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3443	}
3444	pStdFeatureLeaf = NULL;
3445	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3446
3447	/* Work the sub-leaves. */
3448	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3449	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3450	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3451	{
3452	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3453	if (pCurLeaf)
3454	{
3455	if (fGuestXcr0Mask)
3456	{
3457	switch (uSubLeaf)
3458	{
3459	case 0:
3460	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3461	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3462	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3463	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3464	VERR_CPUM_IPE_1);
3465	cbXSaveMaxActual = pCurLeaf->uEcx;
3466	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3467	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3468	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3469	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3470	VERR_CPUM_IPE_2);
3471	continue;
3472	case 1:
3473	pCurLeaf->uEax &= 0;
3474	pCurLeaf->uEcx &= 0;
3475	pCurLeaf->uEdx &= 0;
3476	/** @todo what about checking ebx? */
3477	continue;
3478	default:
3479	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3480	{
3481	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3482	&& pCurLeaf->uEax > 0
3483	&& pCurLeaf->uEbx < cbXSaveMaxActual
3484	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3485	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3486	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3487	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3488	VERR_CPUM_IPE_2);
3489	AssertLogRel(!(pCurLeaf->uEcx & 1));
3490	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3491	pCurLeaf->uEdx = 0; /* it's reserved... */
3492	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3493	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3494	continue;
3495	}
3496	break;
3497	}
3498	}
3499
3500	/* Clear the leaf. */
3501	pCurLeaf->uEax = 0;
3502	pCurLeaf->uEbx = 0;
3503	pCurLeaf->uEcx = 0;
3504	pCurLeaf->uEdx = 0;
3505	}
3506	}
3507
3508	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3509	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3510	{
3511	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3512	if (pCurLeaf)
3513	{
3514	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3515	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3516	pCurLeaf->uEbx = cbXSaveMaxReport;
3517	pCurLeaf->uEcx = cbXSaveMaxReport;
3518	}
3519	}
3520
3521	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3522	* We zero this since we don't know what it may have been used for.
3523	*/
3524	cpumR3CpuIdZeroLeaf(pCpum, 14);
3525
3526	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3527	* also known as Intel Resource Director Technology (RDT) Monitoring
3528	* We zero this as we don't currently virtualize PQM.
3529	*/
3530	cpumR3CpuIdZeroLeaf(pCpum, 15);
3531
3532	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3533	* also known as Intel Resource Director Technology (RDT) Allocation
3534	* We zero this as we don't currently virtualize PQE.
3535	*/
3536	cpumR3CpuIdZeroLeaf(pCpum, 16);
3537
3538	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3539	* We zero this since we don't know what it may have been used for.
3540	*/
3541	cpumR3CpuIdZeroLeaf(pCpum, 17);
3542
3543	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3544	* We zero this as we don't currently virtualize this.
3545	*/
3546	cpumR3CpuIdZeroLeaf(pCpum, 18);
3547
3548	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3549	* We zero this since we don't know what it may have been used for.
3550	*/
3551	cpumR3CpuIdZeroLeaf(pCpum, 19);
3552
3553	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3554	* We zero this as we don't currently virtualize this.
3555	*/
3556	cpumR3CpuIdZeroLeaf(pCpum, 20);
3557
3558	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3559	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3560	* EAX - denominator (unsigned).
3561	* EBX - numerator (unsigned).
3562	* ECX, EDX - reserved.
3563	* AMD: Reserved / undefined / not implemented.
3564	* VIA: Reserved / undefined / not implemented.
3565	* We zero this as we don't currently virtualize this.
3566	*/
3567	cpumR3CpuIdZeroLeaf(pCpum, 21);
3568
3569	/* Cpuid 0x16: Processor frequency info
3570	* Intel: EAX - Core base frequency in MHz.
3571	* EBX - Core maximum frequency in MHz.
3572	* ECX - Bus (reference) frequency in MHz.
3573	* EDX - Reserved.
3574	* AMD: Reserved / undefined / not implemented.
3575	* VIA: Reserved / undefined / not implemented.
3576	* We zero this as we don't currently virtualize this.
3577	*/
3578	cpumR3CpuIdZeroLeaf(pCpum, 22);
3579
3580	/* Cpuid 0x17..0x10000000: Unknown.
3581	* We don't know these and what they mean, so remove them. */
3582	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3583	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3584
3585
3586	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3587	* We remove all these as we're a hypervisor and must provide our own.
3588	*/
3589	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3590	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3591
3592
3593	/* Cpuid 0x80000000 is harmless. */
3594
3595	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3596
3597	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3598
3599	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3600	* Safe to pass on to the guest.
3601	*
3602	* AMD: 0x800000005 L1 cache information
3603	* 0x800000006 L2/L3 cache information
3604	* Intel: 0x800000005 reserved
3605	* 0x800000006 L2 cache information
3606	* VIA: 0x800000005 TLB and L1 cache information
3607	* 0x800000006 L2 cache information
3608	*/
3609
3610	/* Cpuid 0x800000007: Advanced Power Management Information.
3611	* AMD: EAX: Processor feedback capabilities.
3612	* EBX: RAS capabilites.
3613	* ECX: Advanced power monitoring interface.
3614	* EDX: Enhanced power management capabilities.
3615	* Intel: EAX, EBX, ECX - reserved.
3616	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3617	* VIA: Reserved
3618	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3619	*/
3620	uSubLeaf = 0;
3621	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3622	{
3623	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3624	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3625	{
3626	/*
3627	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3628	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3629	* bit is now configurable.
3630	*/
3631	pCurLeaf->uEdx &= 0
3632	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3633	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3634	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3635	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3636	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3637	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3638	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3639	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3640	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3641	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3642	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3643	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3644	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3645	\| 0;
3646	}
3647	else
3648	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3649	if (!pConfig->fInvariantTsc)
3650	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3651	uSubLeaf++;
3652	}
3653
3654	/* Cpuid 0x80000008:
3655	* AMD: EBX, EDX - reserved
3656	* EAX: Virtual/Physical/Guest address Size
3657	* ECX: Number of cores + APICIdCoreIdSize
3658	* Intel: EAX: Virtual/Physical address Size
3659	* EBX, ECX, EDX - reserved
3660	* VIA: EAX: Virtual/Physical address Size
3661	* EBX, ECX, EDX - reserved
3662	*
3663	* We only expose the virtual+pysical address size to the guest atm.
3664	* On AMD we set the core count, but not the apic id stuff as we're
3665	* currently not doing the apic id assignments in a complatible manner.
3666	*/
3667	uSubLeaf = 0;
3668	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3669	{
3670	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3671	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3672	pCurLeaf->uEdx = 0; /* reserved */
3673
3674	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3675	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3676	pCurLeaf->uEcx = 0;
3677	#ifdef VBOX_WITH_MULTI_CORE
3678	if ( pVM->cCpus > 1
3679	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3680	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3681	#endif
3682	uSubLeaf++;
3683	}
3684
3685	/* Cpuid 0x80000009: Reserved
3686	* We zero this since we don't know what it may have been used for.
3687	*/
3688	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3689
3690	/* Cpuid 0x8000000a: SVM Information
3691	* AMD: EAX - SVM revision.
3692	* EBX - Number of ASIDs.
3693	* ECX - Reserved.
3694	* EDX - SVM Feature identification.
3695	*/
3696	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3697	if (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
3698	{
3699	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3700	pSvmFeatureLeaf->uEax = 0x1;
3701	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3702	pSvmFeatureLeaf->uEcx = 0;
3703	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3704	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3705	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3706	}
3707	else
3708	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3709
3710	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3711	* We clear these as we don't know what purpose they might have. */
3712	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3713	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3714
3715	/* Cpuid 0x80000019: TLB configuration
3716	* Seems to be harmless, pass them thru as is. */
3717
3718	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3719	* Strip anything we don't know what is or addresses feature we don't implement. */
3720	uSubLeaf = 0;
3721	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3722	{
3723	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3724	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3725	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3726	;
3727	pCurLeaf->uEbx = 0; /* reserved */
3728	pCurLeaf->uEcx = 0; /* reserved */
3729	pCurLeaf->uEdx = 0; /* reserved */
3730	uSubLeaf++;
3731	}
3732
3733	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3734	* Clear this as we don't currently virtualize this feature. */
3735	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3736
3737	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3738	* Clear this as we don't currently virtualize this feature. */
3739	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3740
3741	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3742	* We need to sanitize the cores per cache (EAX[25:14]).
3743	*
3744	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3745	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3746	* slightly different meaning.
3747	*/
3748	uSubLeaf = 0;
3749	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3750	{
3751	#ifdef VBOX_WITH_MULTI_CORE
3752	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3753	if (cCores > pVM->cCpus)
3754	cCores = pVM->cCpus;
3755	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3756	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3757	#else
3758	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3759	#endif
3760	uSubLeaf++;
3761	}
3762
3763	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3764	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3765	* setup, we have one compute unit with all the cores in it. Single node.
3766	*/
3767	uSubLeaf = 0;
3768	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3769	{
3770	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3771	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3772	{
3773	#ifdef VBOX_WITH_MULTI_CORE
3774	pCurLeaf->uEbx = pVM->cCpus < 0x100
3775	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3776	#else
3777	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3778	#endif
3779	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3780	}
3781	else
3782	{
3783	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3784	pCurLeaf->uEbx = 0; /* Reserved. */
3785	pCurLeaf->uEcx = 0; /* Reserved. */
3786	}
3787	pCurLeaf->uEdx = 0; /* Reserved. */
3788	uSubLeaf++;
3789	}
3790
3791	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3792	* We don't know these and what they mean, so remove them. */
3793	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3794	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3795
3796	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3797	* Just pass it thru for now. */
3798
3799	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3800	* Just pass it thru for now. */
3801
3802	/* Cpuid 0xc0000000: Centaur stuff.
3803	* Harmless, pass it thru. */
3804
3805	/* Cpuid 0xc0000001: Centaur features.
3806	* VIA: EAX - Family, model, stepping.
3807	* EDX - Centaur extended feature flags. Nothing interesting, except may
3808	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3809	* EBX, ECX - reserved.
3810	* We keep EAX but strips the rest.
3811	*/
3812	uSubLeaf = 0;
3813	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3814	{
3815	pCurLeaf->uEbx = 0;
3816	pCurLeaf->uEcx = 0;
3817	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3818	uSubLeaf++;
3819	}
3820
3821	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3822	* We only have fixed stale values, but should be harmless. */
3823
3824	/* Cpuid 0xc0000003: Reserved.
3825	* We zero this since we don't know what it may have been used for.
3826	*/
3827	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3828
3829	/* Cpuid 0xc0000004: Centaur Performance Info.
3830	* We only have fixed stale values, but should be harmless. */
3831
3832
3833	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3834	* We don't know these and what they mean, so remove them. */
3835	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3836	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3837
3838	return VINF_SUCCESS;
3839	#undef PORTABLE_DISABLE_FEATURE_BIT
3840	#undef PORTABLE_CLEAR_BITS_WHEN
3841	}
3842
3843
3844	/**
3845	* Reads a value in /CPUM/IsaExts/ node.
3846	*
3847	* @returns VBox status code (error message raised).
3848	* @param pVM The cross context VM structure. (For errors.)
3849	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3850	* @param pszValueName The value / extension name.
3851	* @param penmValue Where to return the choice.
3852	* @param enmDefault The default choice.
3853	*/
3854	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3855	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3856	{
3857	/*
3858	* Try integer encoding first.
3859	*/
3860	uint64_t uValue;
3861	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3862	if (RT_SUCCESS(rc))
3863	switch (uValue)
3864	{
3865	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3866	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3867	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3868	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3869	default:
3870	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3871	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3872	pszValueName, uValue);
3873	}
3874	/*
3875	* If missing, use default.
3876	*/
3877	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3878	*penmValue = enmDefault;
3879	else
3880	{
3881	if (rc == VERR_CFGM_NOT_INTEGER)
3882	{
3883	/*
3884	* Not an integer, try read it as a string.
3885	*/
3886	char szValue[32];
3887	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3888	if (RT_SUCCESS(rc))
3889	{
3890	RTStrToLower(szValue);
3891	size_t cchValue = strlen(szValue);
3892	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3893	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3894	*penmValue = CPUMISAEXTCFG_DISABLED;
3895	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3896	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3897	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3898	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3899	else if (EQ("portable"))
3900	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3901	else if (EQ("default") \|\| EQ("def"))
3902	*penmValue = enmDefault;
3903	else
3904	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3905	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3906	pszValueName, uValue);
3907	#undef EQ
3908	}
3909	}
3910	if (RT_FAILURE(rc))
3911	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3912	}
3913	return VINF_SUCCESS;
3914	}
3915
3916
3917	/**
3918	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3919	*
3920	* @returns VBox status code (error message raised).
3921	* @param pVM The cross context VM structure. (For errors.)
3922	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3923	* @param pszValueName The value / extension name.
3924	* @param penmValue Where to return the choice.
3925	* @param enmDefault The default choice.
3926	* @param fAllowed Allowed choice. Applied both to the result and to
3927	* the default value.
3928	*/
3929	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3930	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3931	{
3932	int rc;
3933	if (fAllowed)
3934	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3935	else
3936	{
3937	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3938	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3939	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3940	*penmValue = CPUMISAEXTCFG_DISABLED;
3941	}
3942	return rc;
3943	}
3944
3945
3946	/**
3947	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3948	*
3949	* @returns VBox status code (error message raised).
3950	* @param pVM The cross context VM structure. (For errors.)
3951	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3952	* @param pCpumCfg The /CPUM node (can be NULL).
3953	* @param pszValueName The value / extension name.
3954	* @param penmValue Where to return the choice.
3955	* @param enmDefault The default choice.
3956	*/
3957	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3958	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3959	{
3960	if (CFGMR3Exists(pCpumCfg, pszValueName))
3961	{
3962	if (!CFGMR3Exists(pIsaExts, pszValueName))
3963	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3964	else
3965	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3966	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3967	pszValueName, pszValueName);
3968
3969	bool fLegacy;
3970	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3971	if (RT_SUCCESS(rc))
3972	{
3973	*penmValue = fLegacy;
3974	return VINF_SUCCESS;
3975	}
3976	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
3977	}
3978
3979	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3980	}
3981
3982
3983	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
3984	{
3985	int rc;
3986
3987	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3988	* When non-zero CPUID features that could cause portability issues will be
3989	* stripped. The higher the value the more features gets stripped. Higher
3990	* values should only be used when older CPUs are involved since it may
3991	* harm performance and maybe also cause problems with specific guests. */
3992	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
3993	AssertLogRelRCReturn(rc, rc);
3994
3995	/** @cfgm{/CPUM/GuestCpuName, string}
3996	* The name of the CPU we're to emulate. The default is the host CPU.
3997	* Note! CPUs other than "host" one is currently unsupported. */
3998	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3999	AssertLogRelRCReturn(rc, rc);
4000
4001	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
4002	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
4003	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
4004	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
4005	*/
4006	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
4007	AssertLogRelRCReturn(rc, rc);
4008
4009	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
4010	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
4011	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
4012	* 64-bit linux guests which assume the presence of AMD performance counters
4013	* that we do not virtualize.
4014	*/
4015	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
4016	AssertLogRelRCReturn(rc, rc);
4017
4018	/** @cfgm{/CPUM/ForceVme, boolean, false}
4019	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
4020	* By default the flag is passed thru as is from the host CPU, except
4021	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
4022	* guests and DOS boxes in general.
4023	*/
4024	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
4025	AssertLogRelRCReturn(rc, rc);
4026
4027	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
4028	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
4029	* probably going to be a temporary hack, so don't depend on this.
4030	* The 1st byte of the value is the stepping, the 2nd byte value is the model
4031	* number and the 3rd byte value is the family, and the 4th value must be zero.
4032	*/
4033	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
4034	AssertLogRelRCReturn(rc, rc);
4035
4036	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
4037	* The last standard leaf to keep. The actual last value that is stored in EAX
4038	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
4039	* removed. (This works independently of and differently from NT4LeafLimit.)
4040	* The default is usually set to what we're able to reasonably sanitize.
4041	*/
4042	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
4043	AssertLogRelRCReturn(rc, rc);
4044
4045	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
4046	* The last extended leaf to keep. The actual last value that is stored in EAX
4047	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
4048	* leaf are removed. The default is set to what we're able to sanitize.
4049	*/
4050	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
4051	AssertLogRelRCReturn(rc, rc);
4052
4053	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
4054	* The last extended leaf to keep. The actual last value that is stored in EAX
4055	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
4056	* leaf are removed. The default is set to what we're able to sanitize.
4057	*/
4058	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
4059	AssertLogRelRCReturn(rc, rc);
4060
4061	bool fQueryNestedHwvirt = false;
4062	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4063	fQueryNestedHwvirt \|= RT_BOOL(pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD);
4064	#endif
4065	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4066	fQueryNestedHwvirt \|= RT_BOOL( pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
4067	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA);
4068	#endif
4069	if (fQueryNestedHwvirt)
4070	{
4071	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
4072	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
4073	* The default is false, and when enabled requires a 64-bit CPU with support for
4074	* nested-paging and AMD-V or unrestricted guest mode.
4075	*/
4076	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
4077	AssertLogRelRCReturn(rc, rc);
4078	if ( pConfig->fNestedHWVirt
4079	&& !fNestedPagingAndFullGuestExec)
4080	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
4081	"Cannot enable nested VT-x/AMD-V without nested-paging and unresricted guest execution!\n");
4082
4083	/** @todo Think about enabling this later with NEM/KVM. */
4084	if ( pConfig->fNestedHWVirt
4085	&& VM_IS_NEM_ENABLED(pVM))
4086	{
4087	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used!\n"));
4088	pConfig->fNestedHWVirt = false;
4089	}
4090
4091	#if HC_ARCH_BITS == 32
4092	/* We don't support nested hardware virtualization on 32-bit hosts. */
4093	if (pConfig->fNestedHWVirt)
4094	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
4095	"Cannot enable nested VT-x/AMD-V on a 32-bit host\n");
4096	#endif
4097	}
4098
4099	/*
4100	* Instruction Set Architecture (ISA) Extensions.
4101	*/
4102	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
4103	if (pIsaExts)
4104	{
4105	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
4106	"CMPXCHG16B"
4107	"\|MONITOR"
4108	"\|MWaitExtensions"
4109	"\|SSE4.1"
4110	"\|SSE4.2"
4111	"\|XSAVE"
4112	"\|AVX"
4113	"\|AVX2"
4114	"\|AESNI"
4115	"\|PCLMUL"
4116	"\|POPCNT"
4117	"\|MOVBE"
4118	"\|RDRAND"
4119	"\|RDSEED"
4120	"\|CLFLUSHOPT"
4121	"\|FSGSBASE"
4122	"\|PCID"
4123	"\|INVPCID"
4124	"\|ABM"
4125	"\|SSE4A"
4126	"\|MISALNSSE"
4127	"\|3DNOWPRF"
4128	"\|AXMMX"
4129	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
4130	if (RT_FAILURE(rc))
4131	return rc;
4132	}
4133
4134	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
4135	* Expose CMPXCHG16B to the guest if supported by the host. For the time
4136	* being the default is to only do this for VMs with nested paging and AMD-V or
4137	* unrestricted guest mode.
4138	*/
4139	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
4140	AssertLogRelRCReturn(rc, rc);
4141
4142	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
4143	* Expose MONITOR/MWAIT instructions to the guest.
4144	*/
4145	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
4146	AssertLogRelRCReturn(rc, rc);
4147
4148	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4149	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4150	* break on interrupt feature (bit 1).
4151	*/
4152	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4153	AssertLogRelRCReturn(rc, rc);
4154
4155	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4156	* Expose SSE4.1 to the guest if available.
4157	*/
4158	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4159	AssertLogRelRCReturn(rc, rc);
4160
4161	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4162	* Expose SSE4.2 to the guest if available.
4163	*/
4164	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4165	AssertLogRelRCReturn(rc, rc);
4166
4167	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
4168	&& pVM->cpum.s.HostFeatures.fXSaveRstor
4169	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
4170	#if HC_ARCH_BITS == 32 /* Seems this may be broken when doing 64-bit on 32-bit, just disable it for now. */
4171	&& ( !HMIsLongModeAllowed(pVM)
4172	\|\| NEMHCIsLongModeAllowed(pVM))
4173	#endif
4174	;
4175	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4176
4177	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4178	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4179	* default is to only expose this to VMs with nested paging and AMD-V or
4180	* unrestricted guest execution mode. Not possible to force this one without
4181	* host support at the moment.
4182	*/
4183	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4184	fMayHaveXSave /fAllowed/);
4185	AssertLogRelRCReturn(rc, rc);
4186
4187	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4188	* Expose the AVX instruction set extensions to the guest if available and
4189	* XSAVE is exposed too. For the time being the default is to only expose this
4190	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4191	*/
4192	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4193	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4194	AssertLogRelRCReturn(rc, rc);
4195
4196	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4197	* Expose the AVX2 instruction set extensions to the guest if available and
4198	* XSAVE is exposed too. For the time being the default is to only expose this
4199	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4200	*/
4201	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4202	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4203	AssertLogRelRCReturn(rc, rc);
4204
4205	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4206	* Whether to expose the AES instructions to the guest. For the time being the
4207	* default is to only do this for VMs with nested paging and AMD-V or
4208	* unrestricted guest mode.
4209	*/
4210	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4211	AssertLogRelRCReturn(rc, rc);
4212
4213	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4214	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4215	* being the default is to only do this for VMs with nested paging and AMD-V or
4216	* unrestricted guest mode.
4217	*/
4218	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4219	AssertLogRelRCReturn(rc, rc);
4220
4221	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4222	* Whether to expose the POPCNT instructions to the guest. For the time
4223	* being the default is to only do this for VMs with nested paging and AMD-V or
4224	* unrestricted guest mode.
4225	*/
4226	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4227	AssertLogRelRCReturn(rc, rc);
4228
4229	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4230	* Whether to expose the MOVBE instructions to the guest. For the time
4231	* being the default is to only do this for VMs with nested paging and AMD-V or
4232	* unrestricted guest mode.
4233	*/
4234	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4235	AssertLogRelRCReturn(rc, rc);
4236
4237	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4238	* Whether to expose the RDRAND instructions to the guest. For the time being
4239	* the default is to only do this for VMs with nested paging and AMD-V or
4240	* unrestricted guest mode.
4241	*/
4242	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4243	AssertLogRelRCReturn(rc, rc);
4244
4245	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4246	* Whether to expose the RDSEED instructions to the guest. For the time being
4247	* the default is to only do this for VMs with nested paging and AMD-V or
4248	* unrestricted guest mode.
4249	*/
4250	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4251	AssertLogRelRCReturn(rc, rc);
4252
4253	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4254	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4255	* being the default is to only do this for VMs with nested paging and AMD-V or
4256	* unrestricted guest mode.
4257	*/
4258	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4259	AssertLogRelRCReturn(rc, rc);
4260
4261	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4262	* Whether to expose the read/write FSGSBASE instructions to the guest.
4263	*/
4264	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4265	AssertLogRelRCReturn(rc, rc);
4266
4267	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4268	* Whether to expose the PCID feature to the guest.
4269	*/
4270	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4271	AssertLogRelRCReturn(rc, rc);
4272
4273	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4274	* Whether to expose the INVPCID instruction to the guest.
4275	*/
4276	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4277	AssertLogRelRCReturn(rc, rc);
4278
4279
4280	/* AMD: */
4281
4282	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4283	* Whether to expose the AMD ABM instructions to the guest. For the time
4284	* being the default is to only do this for VMs with nested paging and AMD-V or
4285	* unrestricted guest mode.
4286	*/
4287	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4288	AssertLogRelRCReturn(rc, rc);
4289
4290	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4291	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4292	* being the default is to only do this for VMs with nested paging and AMD-V or
4293	* unrestricted guest mode.
4294	*/
4295	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4296	AssertLogRelRCReturn(rc, rc);
4297
4298	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4299	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4300	* the time being the default is to only do this for VMs with nested paging and
4301	* AMD-V or unrestricted guest mode.
4302	*/
4303	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4304	AssertLogRelRCReturn(rc, rc);
4305
4306	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4307	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4308	* For the time being the default is to only do this for VMs with nested paging
4309	* and AMD-V or unrestricted guest mode.
4310	*/
4311	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4312	AssertLogRelRCReturn(rc, rc);
4313
4314	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4315	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4316	* the default is to only do this for VMs with nested paging and AMD-V or
4317	* unrestricted guest mode.
4318	*/
4319	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4320	AssertLogRelRCReturn(rc, rc);
4321
4322	return VINF_SUCCESS;
4323	}
4324
4325
4326	/**
4327	* Initializes the emulated CPU's CPUID & MSR information.
4328	*
4329	* @returns VBox status code.
4330	* @param pVM The cross context VM structure.
4331	* @param pHostMsrs Pointer to the host MSRs.
4332	*/
4333	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
4334	{
4335	Assert(pHostMsrs);
4336
4337	PCPUM pCpum = &pVM->cpum.s;
4338	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4339
4340	/*
4341	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4342	* on construction and manage everything from here on.
4343	*/
4344	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
4345	pVM->aCpus[iCpu].cpum.s.fCpuIdApicFeatureVisible = true;
4346
4347	/*
4348	* Read the configuration.
4349	*/
4350	CPUMCPUIDCONFIG Config;
4351	RT_ZERO(Config);
4352
4353	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4354	AssertRCReturn(rc, rc);
4355
4356	/*
4357	* Get the guest CPU data from the database and/or the host.
4358	*
4359	* The CPUID and MSRs are currently living on the regular heap to avoid
4360	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4361	* API for the hyper heap). This means special cleanup considerations.
4362	*/
4363	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4364	if (RT_FAILURE(rc))
4365	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4366	? VMSetError(pVM, rc, RT_SRC_POS,
4367	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4368	: rc;
4369
4370	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4371	{
4372	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4373	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4374	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4375	}
4376	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4377
4378	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4379	* Overrides the guest MSRs.
4380	*/
4381	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4382
4383	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4384	* Overrides the CPUID leaf values (from the host CPU usually) used for
4385	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4386	* values when moving a VM to a different machine. Another use is restricting
4387	* (or extending) the feature set exposed to the guest. */
4388	if (RT_SUCCESS(rc))
4389	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4390
4391	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4392	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4393	"Found unsupported configuration node '/CPUM/CPUID/'. "
4394	"Please use IMachine::setCPUIDLeaf() instead.");
4395
4396	CPUMMSRS GuestMsrs;
4397	RT_ZERO(GuestMsrs);
4398
4399	/*
4400	* Pre-explode the CPUID info.
4401	*/
4402	if (RT_SUCCESS(rc))
4403	{
4404	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
4405	&pCpum->GuestFeatures);
4406	}
4407
4408	/*
4409	* Sanitize the cpuid information passed on to the guest.
4410	*/
4411	if (RT_SUCCESS(rc))
4412	{
4413	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4414	if (RT_SUCCESS(rc))
4415	{
4416	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4417	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4418	}
4419	}
4420
4421	/*
4422	* MSR fudging.
4423	*/
4424	if (RT_SUCCESS(rc))
4425	{
4426	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4427	* Fudges some common MSRs if not present in the selected CPU database entry.
4428	* This is for trying to keep VMs running when moved between different hosts
4429	* and different CPU vendors. */
4430	bool fEnable;
4431	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4432	if (RT_SUCCESS(rc) && fEnable)
4433	{
4434	rc = cpumR3MsrApplyFudge(pVM);
4435	AssertLogRelRC(rc);
4436	}
4437	}
4438	if (RT_SUCCESS(rc))
4439	{
4440	/*
4441	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4442	* guest CPU features again.
4443	*/
4444	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4445	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4446	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
4447	RTMemFree(pvFree);
4448
4449	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4450	int rc2 = MMHyperDupMem(pVM, pvFree,
4451	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4452	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4453	RTMemFree(pvFree);
4454	AssertLogRelRCReturn(rc1, rc1);
4455	AssertLogRelRCReturn(rc2, rc2);
4456
4457	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4458	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
4459
4460	/*
4461	* Finally, initialize guest VMX MSRs.
4462	*
4463	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
4464	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
4465	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
4466	*/
4467	if (pVM->cpum.s.GuestFeatures.fVmx)
4468	{
4469	Assert(Config.fNestedHWVirt);
4470	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
4471
4472	/* Copy MSRs to all VCPUs */
4473	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
4474	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4475	{
4476	PVMCPU pVCpu = &pVM->aCpus[idCpu];
4477	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
4478	}
4479	}
4480
4481	/*
4482	* Some more configuration that we're applying at the end of everything
4483	* via the CPUMSetGuestCpuIdFeature API.
4484	*/
4485
4486	/* Check if PAE was explicitely enabled by the user. */
4487	bool fEnable;
4488	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4489	AssertRCReturn(rc, rc);
4490	if (fEnable)
4491	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4492
4493	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4494	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4495	AssertRCReturn(rc, rc);
4496	if (fEnable)
4497	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4498
4499	/* Check if speculation control is enabled. */
4500	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4501	AssertRCReturn(rc, rc);
4502	if (fEnable)
4503	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4504
4505	return VINF_SUCCESS;
4506	}
4507
4508	/*
4509	* Failed before switching to hyper heap.
4510	*/
4511	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4512	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4513	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4514	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4515	return rc;
4516	}
4517
4518
4519	/**
4520	* Sets a CPUID feature bit during VM initialization.
4521	*
4522	* Since the CPUID feature bits are generally related to CPU features, other
4523	* CPUM configuration like MSRs can also be modified by calls to this API.
4524	*
4525	* @param pVM The cross context VM structure.
4526	* @param enmFeature The feature to set.
4527	*/
4528	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4529	{
4530	PCPUMCPUIDLEAF pLeaf;
4531	PCPUMMSRRANGE pMsrRange;
4532
4533	switch (enmFeature)
4534	{
4535	/*
4536	* Set the APIC bit in both feature masks.
4537	*/
4538	case CPUMCPUIDFEATURE_APIC:
4539	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4540	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4541	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4542
4543	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4544	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4545	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4546
4547	pVM->cpum.s.GuestFeatures.fApic = 1;
4548
4549	/* Make sure we've got the APICBASE MSR present. */
4550	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4551	if (!pMsrRange)
4552	{
4553	static CPUMMSRRANGE const s_ApicBase =
4554	{
4555	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4556	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4557	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4558	/.szName = / "IA32_APIC_BASE"
4559	};
4560	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4561	AssertLogRelRC(rc);
4562	}
4563
4564	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4565	break;
4566
4567	/*
4568	* Set the x2APIC bit in the standard feature mask.
4569	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4570	*/
4571	case CPUMCPUIDFEATURE_X2APIC:
4572	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4573	if (pLeaf)
4574	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4575	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4576
4577	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4578	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4579	if (pMsrRange)
4580	{
4581	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4582	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4583	}
4584
4585	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4586	break;
4587
4588	/*
4589	* Set the sysenter/sysexit bit in the standard feature mask.
4590	* Assumes the caller knows what it's doing! (host must support these)
4591	*/
4592	case CPUMCPUIDFEATURE_SEP:
4593	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4594	{
4595	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4596	return;
4597	}
4598
4599	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4600	if (pLeaf)
4601	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4602	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4603	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4604	break;
4605
4606	/*
4607	* Set the syscall/sysret bit in the extended feature mask.
4608	* Assumes the caller knows what it's doing! (host must support these)
4609	*/
4610	case CPUMCPUIDFEATURE_SYSCALL:
4611	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4612	if ( !pLeaf
4613	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4614	{
4615	#if HC_ARCH_BITS == 32
4616	/* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32-bit
4617	mode by Intel, even when the cpu is capable of doing so in
4618	64-bit mode. Long mode requires syscall support. */
4619	if (!pVM->cpum.s.HostFeatures.fLongMode)
4620	#endif
4621	{
4622	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4623	return;
4624	}
4625	}
4626
4627	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4628	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4629	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4630	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4631	break;
4632
4633	/*
4634	* Set the PAE bit in both feature masks.
4635	* Assumes the caller knows what it's doing! (host must support these)
4636	*/
4637	case CPUMCPUIDFEATURE_PAE:
4638	if (!pVM->cpum.s.HostFeatures.fPae)
4639	{
4640	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4641	return;
4642	}
4643
4644	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4645	if (pLeaf)
4646	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4647
4648	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4649	if ( pLeaf
4650	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4651	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4652
4653	pVM->cpum.s.GuestFeatures.fPae = 1;
4654	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4655	break;
4656
4657	/*
4658	* Set the LONG MODE bit in the extended feature mask.
4659	* Assumes the caller knows what it's doing! (host must support these)
4660	*/
4661	case CPUMCPUIDFEATURE_LONG_MODE:
4662	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4663	if ( !pLeaf
4664	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4665	{
4666	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4667	return;
4668	}
4669
4670	/* Valid for both Intel and AMD. */
4671	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4672	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4673	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4674	break;
4675
4676	/*
4677	* Set the NX/XD bit in the extended feature mask.
4678	* Assumes the caller knows what it's doing! (host must support these)
4679	*/
4680	case CPUMCPUIDFEATURE_NX:
4681	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4682	if ( !pLeaf
4683	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4684	{
4685	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4686	return;
4687	}
4688
4689	/* Valid for both Intel and AMD. */
4690	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4691	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4692	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4693	break;
4694
4695
4696	/*
4697	* Set the LAHF/SAHF support in 64-bit mode.
4698	* Assumes the caller knows what it's doing! (host must support this)
4699	*/
4700	case CPUMCPUIDFEATURE_LAHF:
4701	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4702	if ( !pLeaf
4703	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4704	{
4705	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4706	return;
4707	}
4708
4709	/* Valid for both Intel and AMD. */
4710	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4711	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4712	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4713	break;
4714
4715	/*
4716	* Set the page attribute table bit. This is alternative page level
4717	* cache control that doesn't much matter when everything is
4718	* virtualized, though it may when passing thru device memory.
4719	*/
4720	case CPUMCPUIDFEATURE_PAT:
4721	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4722	if (pLeaf)
4723	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4724
4725	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4726	if ( pLeaf
4727	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4728	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4729
4730	pVM->cpum.s.GuestFeatures.fPat = 1;
4731	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4732	break;
4733
4734	/*
4735	* Set the RDTSCP support bit.
4736	* Assumes the caller knows what it's doing! (host must support this)
4737	*/
4738	case CPUMCPUIDFEATURE_RDTSCP:
4739	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4740	if ( !pLeaf
4741	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4742	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4743	{
4744	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4745	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4746	return;
4747	}
4748
4749	/* Valid for both Intel and AMD. */
4750	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4751	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4752	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4753	break;
4754
4755	/*
4756	* Set the Hypervisor Present bit in the standard feature mask.
4757	*/
4758	case CPUMCPUIDFEATURE_HVP:
4759	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4760	if (pLeaf)
4761	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4762	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4763	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4764	break;
4765
4766	/*
4767	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4768	* This currently includes the Present bit and MWAITBREAK bit as well.
4769	*/
4770	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4771	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4772	if ( !pLeaf
4773	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4774	{
4775	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4776	return;
4777	}
4778
4779	/* Valid for both Intel and AMD. */
4780	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4781	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4782	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4783	break;
4784
4785	/*
4786	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
4787	* on Intel CPUs, and different on AMDs.
4788	*/
4789	case CPUMCPUIDFEATURE_SPEC_CTRL:
4790	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
4791	{
4792	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4793	if ( !pLeaf
4794	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
4795	{
4796	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
4797	return;
4798	}
4799
4800	/* The feature can be enabled. Let's see what we can actually do. */
4801	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
4802
4803	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
4804	if (pVM->cpum.s.HostFeatures.fIbrs)
4805	{
4806	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
4807	pVM->cpum.s.GuestFeatures.fIbrs = 1;
4808	if (pVM->cpum.s.HostFeatures.fStibp)
4809	{
4810	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
4811	pVM->cpum.s.GuestFeatures.fStibp = 1;
4812	}
4813
4814	/* Make sure we have the speculation control MSR... */
4815	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
4816	if (!pMsrRange)
4817	{
4818	static CPUMMSRRANGE const s_SpecCtrl =
4819	{
4820	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
4821	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
4822	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4823	/.szName = / "IA32_SPEC_CTRL"
4824	};
4825	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4826	AssertLogRelRC(rc);
4827	}
4828
4829	/* ... and the predictor command MSR. */
4830	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
4831	if (!pMsrRange)
4832	{
4833	static CPUMMSRRANGE const s_SpecCtrl =
4834	{
4835	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
4836	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
4837	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4838	/.szName = / "IA32_PRED_CMD"
4839	};
4840	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4841	AssertLogRelRC(rc);
4842	}
4843
4844	}
4845
4846	if (pVM->cpum.s.HostFeatures.fArchCap) {
4847	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
4848
4849	/* Install the architectural capabilities MSR. */
4850	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
4851	if (!pMsrRange)
4852	{
4853	static CPUMMSRRANGE const s_ArchCaps =
4854	{
4855	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
4856	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
4857	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
4858	/.szName = / "IA32_ARCH_CAPABILITIES"
4859	};
4860	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
4861	AssertLogRelRC(rc);
4862	}
4863	}
4864
4865	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
4866	}
4867	else if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4868	{
4869	/* The precise details of AMD's implementation are not yet clear. */
4870	}
4871	break;
4872
4873	default:
4874	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4875	break;
4876	}
4877
4878	/** @todo can probably kill this as this API is now init time only... */
4879	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4880	{
4881	PVMCPU pVCpu = &pVM->aCpus[i];
4882	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4883	}
4884	}
4885
4886
4887	/**
4888	* Queries a CPUID feature bit.
4889	*
4890	* @returns boolean for feature presence
4891	* @param pVM The cross context VM structure.
4892	* @param enmFeature The feature to query.
4893	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4894	*/
4895	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4896	{
4897	switch (enmFeature)
4898	{
4899	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4900	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4901	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4902	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4903	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4904	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4905	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4906	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4907	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
4908	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4909	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4910	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
4911	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
4912
4913	case CPUMCPUIDFEATURE_INVALID:
4914	case CPUMCPUIDFEATURE_32BIT_HACK:
4915	break;
4916	}
4917	AssertFailed();
4918	return false;
4919	}
4920
4921
4922	/**
4923	* Clears a CPUID feature bit.
4924	*
4925	* @param pVM The cross context VM structure.
4926	* @param enmFeature The feature to clear.
4927	*
4928	* @deprecated Probably better to default the feature to disabled and only allow
4929	* setting (enabling) it during construction.
4930	*/
4931	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4932	{
4933	PCPUMCPUIDLEAF pLeaf;
4934	switch (enmFeature)
4935	{
4936	case CPUMCPUIDFEATURE_APIC:
4937	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
4938	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4939	if (pLeaf)
4940	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
4941
4942	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4943	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4944	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
4945
4946	pVM->cpum.s.GuestFeatures.fApic = 0;
4947	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
4948	break;
4949
4950	case CPUMCPUIDFEATURE_X2APIC:
4951	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
4952	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4953	if (pLeaf)
4954	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
4955	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
4956	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
4957	break;
4958
4959	case CPUMCPUIDFEATURE_PAE:
4960	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4961	if (pLeaf)
4962	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
4963
4964	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4965	if ( pLeaf
4966	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4967	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
4968
4969	pVM->cpum.s.GuestFeatures.fPae = 0;
4970	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
4971	break;
4972
4973	case CPUMCPUIDFEATURE_PAT:
4974	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4975	if (pLeaf)
4976	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
4977
4978	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4979	if ( pLeaf
4980	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4981	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
4982
4983	pVM->cpum.s.GuestFeatures.fPat = 0;
4984	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
4985	break;
4986
4987	case CPUMCPUIDFEATURE_LONG_MODE:
4988	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4989	if (pLeaf)
4990	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4991	pVM->cpum.s.GuestFeatures.fLongMode = 0;
4992	break;
4993
4994	case CPUMCPUIDFEATURE_LAHF:
4995	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4996	if (pLeaf)
4997	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4998	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
4999	break;
5000
5001	case CPUMCPUIDFEATURE_RDTSCP:
5002	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5003	if (pLeaf)
5004	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
5005	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
5006	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
5007	break;
5008
5009	case CPUMCPUIDFEATURE_HVP:
5010	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5011	if (pLeaf)
5012	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
5013	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
5014	break;
5015
5016	case CPUMCPUIDFEATURE_MWAIT_EXTS:
5017	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
5018	if (pLeaf)
5019	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
5020	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
5021	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
5022	break;
5023
5024	case CPUMCPUIDFEATURE_SPEC_CTRL:
5025	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
5026	if (pLeaf)
5027	/pVM->cpum.s.aGuestCpuIdPatmStd[7].uEdx =/ pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP \| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
5028	pVM->cpum.s.GuestFeatures.fSpeculationControl = 0;
5029	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
5030	break;
5031
5032	default:
5033	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5034	break;
5035	}
5036
5037	for (VMCPUID i = 0; i < pVM->cCpus; i++)
5038	{
5039	PVMCPU pVCpu = &pVM->aCpus[i];
5040	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5041	}
5042	}
5043
5044
5045
5046	/*
5047	*
5048	*
5049	* Saved state related code.
5050	* Saved state related code.
5051	* Saved state related code.
5052	*
5053	*
5054	*/
5055
5056	/**
5057	* Called both in pass 0 and the final pass.
5058	*
5059	* @param pVM The cross context VM structure.
5060	* @param pSSM The saved state handle.
5061	*/
5062	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
5063	{
5064	/*
5065	* Save all the CPU ID leaves.
5066	*/
5067	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
5068	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5069	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
5070	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5071
5072	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5073
5074	/*
5075	* Save a good portion of the raw CPU IDs as well as they may come in
5076	* handy when validating features for raw mode.
5077	*/
5078	CPUMCPUID aRawStd[16];
5079	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
5080	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5081	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
5082	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
5083
5084	CPUMCPUID aRawExt[32];
5085	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
5086	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5087	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
5088	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
5089	}
5090
5091
5092	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5093	{
5094	uint32_t cCpuIds;
5095	int rc = SSMR3GetU32(pSSM, &cCpuIds);
5096	if (RT_SUCCESS(rc))
5097	{
5098	if (cCpuIds < 64)
5099	{
5100	for (uint32_t i = 0; i < cCpuIds; i++)
5101	{
5102	CPUMCPUID CpuId;
5103	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
5104	if (RT_FAILURE(rc))
5105	break;
5106
5107	CPUMCPUIDLEAF NewLeaf;
5108	NewLeaf.uLeaf = uBase + i;
5109	NewLeaf.uSubLeaf = 0;
5110	NewLeaf.fSubLeafMask = 0;
5111	NewLeaf.uEax = CpuId.uEax;
5112	NewLeaf.uEbx = CpuId.uEbx;
5113	NewLeaf.uEcx = CpuId.uEcx;
5114	NewLeaf.uEdx = CpuId.uEdx;
5115	NewLeaf.fFlags = 0;
5116	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
5117	}
5118	}
5119	else
5120	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5121	}
5122	if (RT_FAILURE(rc))
5123	{
5124	RTMemFree(*ppaLeaves);
5125	*ppaLeaves = NULL;
5126	*pcLeaves = 0;
5127	}
5128	return rc;
5129	}
5130
5131
5132	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5133	{
5134	*ppaLeaves = NULL;
5135	*pcLeaves = 0;
5136
5137	int rc;
5138	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
5139	{
5140	/*
5141	* The new format. Starts by declaring the leave size and count.
5142	*/
5143	uint32_t cbLeaf;
5144	SSMR3GetU32(pSSM, &cbLeaf);
5145	uint32_t cLeaves;
5146	rc = SSMR3GetU32(pSSM, &cLeaves);
5147	if (RT_SUCCESS(rc))
5148	{
5149	if (cbLeaf == sizeof(**ppaLeaves))
5150	{
5151	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
5152	{
5153	/*
5154	* Load the leaves one by one.
5155	*
5156	* The uPrev stuff is a kludge for working around a week worth of bad saved
5157	* states during the CPUID revamp in March 2015. We saved too many leaves
5158	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
5159	* garbage entires at the end of the array when restoring. We also had
5160	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
5161	* this kludge doesn't deal correctly with that, but who cares...
5162	*/
5163	uint32_t uPrev = 0;
5164	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
5165	{
5166	CPUMCPUIDLEAF Leaf;
5167	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
5168	if (RT_SUCCESS(rc))
5169	{
5170	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
5171	\|\| Leaf.uLeaf >= uPrev)
5172	{
5173	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5174	uPrev = Leaf.uLeaf;
5175	}
5176	else
5177	uPrev = UINT32_MAX;
5178	}
5179	}
5180	}
5181	else
5182	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5183	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5184	}
5185	else
5186	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5187	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5188	}
5189	}
5190	else
5191	{
5192	/*
5193	* The old format with its three inflexible arrays.
5194	*/
5195	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5196	if (RT_SUCCESS(rc))
5197	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5198	if (RT_SUCCESS(rc))
5199	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5200	if (RT_SUCCESS(rc))
5201	{
5202	/*
5203	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5204	*/
5205	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5206	if ( pLeaf
5207	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5208	{
5209	CPUMCPUIDLEAF Leaf;
5210	Leaf.uLeaf = 4;
5211	Leaf.fSubLeafMask = UINT32_MAX;
5212	Leaf.uSubLeaf = 0;
5213	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5214	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5215	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5216	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5217	\| UINT32_C(63); /* system coherency line size - 1 */
5218	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5219	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5220	\| (UINT32_C(1) << 5) /* cache level */
5221	\| UINT32_C(1); /* cache type (data) */
5222	Leaf.fFlags = 0;
5223	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5224	if (RT_SUCCESS(rc))
5225	{
5226	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5227	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5228	}
5229	if (RT_SUCCESS(rc))
5230	{
5231	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5232	Leaf.uEcx = 4095; /* sets - 1 */
5233	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5234	Leaf.uEbx \|= UINT32_C(23) << 22;
5235	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5236	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5237	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5238	Leaf.uEax \|= UINT32_C(2) << 5;
5239	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5240	}
5241	}
5242	}
5243	}
5244	return rc;
5245	}
5246
5247
5248	/**
5249	* Loads the CPU ID leaves saved by pass 0, inner worker.
5250	*
5251	* @returns VBox status code.
5252	* @param pVM The cross context VM structure.
5253	* @param pSSM The saved state handle.
5254	* @param uVersion The format version.
5255	* @param paLeaves Guest CPUID leaves loaded from the state.
5256	* @param cLeaves The number of leaves in @a paLeaves.
5257	* @param pMsrs The guest MSRs.
5258	*/
5259	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
5260	{
5261	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5262
5263	/*
5264	* Continue loading the state into stack buffers.
5265	*/
5266	CPUMCPUID GuestDefCpuId;
5267	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5268	AssertRCReturn(rc, rc);
5269
5270	CPUMCPUID aRawStd[16];
5271	uint32_t cRawStd;
5272	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5273	if (cRawStd > RT_ELEMENTS(aRawStd))
5274	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5275	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5276	AssertRCReturn(rc, rc);
5277	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5278	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5279
5280	CPUMCPUID aRawExt[32];
5281	uint32_t cRawExt;
5282	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5283	if (cRawExt > RT_ELEMENTS(aRawExt))
5284	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5285	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5286	AssertRCReturn(rc, rc);
5287	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5288	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5289
5290	/*
5291	* Get the raw CPU IDs for the current host.
5292	*/
5293	CPUMCPUID aHostRawStd[16];
5294	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5295	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5296
5297	CPUMCPUID aHostRawExt[32];
5298	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5299	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5300	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5301
5302	/*
5303	* Get the host and guest overrides so we don't reject the state because
5304	* some feature was enabled thru these interfaces.
5305	* Note! We currently only need the feature leaves, so skip rest.
5306	*/
5307	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5308	CPUMCPUID aHostOverrideStd[2];
5309	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5310	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5311
5312	CPUMCPUID aHostOverrideExt[2];
5313	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5314	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5315
5316	/*
5317	* This can be skipped.
5318	*/
5319	bool fStrictCpuIdChecks;
5320	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5321
5322	/*
5323	* Define a bunch of macros for simplifying the santizing/checking code below.
5324	*/
5325	/* Generic expression + failure message. */
5326	#define CPUID_CHECK_RET(expr, fmt) \
5327	do { \
5328	if (!(expr)) \
5329	{ \
5330	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5331	if (fStrictCpuIdChecks) \
5332	{ \
5333	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5334	RTStrFree(pszMsg); \
5335	return rcCpuid; \
5336	} \
5337	LogRel(("CPUM: %s\n", pszMsg)); \
5338	RTStrFree(pszMsg); \
5339	} \
5340	} while (0)
5341	#define CPUID_CHECK_WRN(expr, fmt) \
5342	do { \
5343	if (!(expr)) \
5344	LogRel(fmt); \
5345	} while (0)
5346
5347	/* For comparing two values and bitch if they differs. */
5348	#define CPUID_CHECK2_RET(what, host, saved) \
5349	do { \
5350	if ((host) != (saved)) \
5351	{ \
5352	if (fStrictCpuIdChecks) \
5353	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5354	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5355	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5356	} \
5357	} while (0)
5358	#define CPUID_CHECK2_WRN(what, host, saved) \
5359	do { \
5360	if ((host) != (saved)) \
5361	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5362	} while (0)
5363
5364	/* For checking raw cpu features (raw mode). */
5365	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5366	do { \
5367	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5368	{ \
5369	if (fStrictCpuIdChecks) \
5370	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5371	N_(#bit " mismatch: host=%d saved=%d"), \
5372	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5373	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5374	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5375	} \
5376	} while (0)
5377	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5378	do { \
5379	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5380	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5381	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5382	} while (0)
5383	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5384
5385	/* For checking guest features. */
5386	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5387	do { \
5388	if ( (aGuestCpuId##set [1].reg & bit) \
5389	&& !(aHostRaw##set [1].reg & bit) \
5390	&& !(aHostOverride##set [1].reg & bit) \
5391	) \
5392	{ \
5393	if (fStrictCpuIdChecks) \
5394	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5395	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5396	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5397	} \
5398	} while (0)
5399	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5400	do { \
5401	if ( (aGuestCpuId##set [1].reg & bit) \
5402	&& !(aHostRaw##set [1].reg & bit) \
5403	&& !(aHostOverride##set [1].reg & bit) \
5404	) \
5405	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5406	} while (0)
5407	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5408	do { \
5409	if ( (aGuestCpuId##set [1].reg & bit) \
5410	&& !(aHostRaw##set [1].reg & bit) \
5411	&& !(aHostOverride##set [1].reg & bit) \
5412	) \
5413	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5414	} while (0)
5415	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5416
5417	/* For checking guest features if AMD guest CPU. */
5418	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5419	do { \
5420	if ( (aGuestCpuId##set [1].reg & bit) \
5421	&& fGuestAmd \
5422	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5423	&& !(aHostOverride##set [1].reg & bit) \
5424	) \
5425	{ \
5426	if (fStrictCpuIdChecks) \
5427	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5428	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5429	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5430	} \
5431	} while (0)
5432	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5433	do { \
5434	if ( (aGuestCpuId##set [1].reg & bit) \
5435	&& fGuestAmd \
5436	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5437	&& !(aHostOverride##set [1].reg & bit) \
5438	) \
5439	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5440	} while (0)
5441	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5442	do { \
5443	if ( (aGuestCpuId##set [1].reg & bit) \
5444	&& fGuestAmd \
5445	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5446	&& !(aHostOverride##set [1].reg & bit) \
5447	) \
5448	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5449	} while (0)
5450	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5451
5452	/* For checking AMD features which have a corresponding bit in the standard
5453	range. (Intel defines very few bits in the extended feature sets.) */
5454	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5455	do { \
5456	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5457	&& !(fHostAmd \
5458	? aHostRawExt[1].reg & (ExtBit) \
5459	: aHostRawStd[1].reg & (StdBit)) \
5460	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5461	) \
5462	{ \
5463	if (fStrictCpuIdChecks) \
5464	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5465	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5466	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5467	} \
5468	} while (0)
5469	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5470	do { \
5471	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5472	&& !(fHostAmd \
5473	? aHostRawExt[1].reg & (ExtBit) \
5474	: aHostRawStd[1].reg & (StdBit)) \
5475	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5476	) \
5477	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5478	} while (0)
5479	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5480	do { \
5481	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5482	&& !(fHostAmd \
5483	? aHostRawExt[1].reg & (ExtBit) \
5484	: aHostRawStd[1].reg & (StdBit)) \
5485	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5486	) \
5487	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5488	} while (0)
5489	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5490
5491	/*
5492	* For raw-mode we'll require that the CPUs are very similar since we don't
5493	* intercept CPUID instructions for user mode applications.
5494	*/
5495	if (VM_IS_RAW_MODE_ENABLED(pVM))
5496	{
5497	/* CPUID(0) */
5498	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
5499	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
5500	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
5501	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5502	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
5503	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
5504	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
5505	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
5506	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5507
5508	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
5509
5510	/* CPUID(1).eax */
5511	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
5512	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
5513	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
5514
5515	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
5516	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
5517	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
5518
5519	/* CPUID(1).ecx */
5520	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
5521	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
5522	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
5523	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5524	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
5525	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
5526	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
5527	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
5528	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
5529	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
5530	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
5531	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
5532	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
5533	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
5534	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
5535	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
5536	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5537	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5538	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
5539	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
5540	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
5541	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5542	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
5543	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
5544	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5545	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
5546	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
5547	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5548	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
5549	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5550	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5551	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
5552
5553	/* CPUID(1).edx */
5554	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5555	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5556	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
5557	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5558	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
5559	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
5560	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5561	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5562	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
5563	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5564	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5565	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5566	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5567	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5568	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5569	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
5570	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5571	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5572	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5573	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
5574	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5575	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
5576	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
5577	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
5578	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
5579	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
5580	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
5581	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
5582	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
5583	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
5584	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
5585	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
5586
5587	/* CPUID(2) - config, mostly about caches. ignore. */
5588	/* CPUID(3) - processor serial number. ignore. */
5589	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
5590	/* CPUID(5) - mwait/monitor config. ignore. */
5591	/* CPUID(6) - power management. ignore. */
5592	/* CPUID(7) - ???. ignore. */
5593	/* CPUID(8) - ???. ignore. */
5594	/* CPUID(9) - DCA. ignore for now. */
5595	/* CPUID(a) - PeMo info. ignore for now. */
5596	/* CPUID(b) - topology info - takes ECX as input. ignore. */
5597
5598	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
5599	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
5600	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
5601	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
5602	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
5603	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
5604	{
5605	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
5606	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
5607	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
5608	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
5609	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
5610	}
5611
5612	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
5613	Note! Intel have/is marking many of the fields here as reserved. We
5614	will verify them as if it's an AMD CPU. */
5615	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
5616	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
5617	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
5618	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
5619	{
5620	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
5621	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
5622	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
5623	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5624	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
5625	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
5626	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
5627
5628	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
5629	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
5630	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
5631	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
5632	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
5633	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5634
5635	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
5636	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
5637	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
5638	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
5639
5640	/* CPUID(0x80000001).ecx */
5641	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
5642	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
5643	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
5644	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
5645	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
5646	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
5647	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
5648	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
5649	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
5650	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
5651	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
5652	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
5653	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
5654	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
5655	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5656	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5657	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5658	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5659	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5660	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5661	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5662	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5663	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5664	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5665	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5666	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5667	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5668	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5669	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5670	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5671	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5672	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5673
5674	/* CPUID(0x80000001).edx */
5675	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
5676	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
5677	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
5678	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
5679	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
5680	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
5681	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
5682	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
5683	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
5684	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
5685	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5686	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
5687	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
5688	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
5689	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
5690	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
5691	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
5692	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
5693	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5694	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5695	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5696	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
5697	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5698	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
5699	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
5700	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5701	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5702	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5703	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
5704	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5705	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5706	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5707
5708	/** @todo verify the rest as well. */
5709	}
5710	}
5711
5712
5713
5714	/*
5715	* Verify that we can support the features already exposed to the guest on
5716	* this host.
5717	*
5718	* Most of the features we're emulating requires intercepting instruction
5719	* and doing it the slow way, so there is no need to warn when they aren't
5720	* present in the host CPU. Thus we use IGN instead of EMU on these.
5721	*
5722	* Trailing comments:
5723	* "EMU" - Possible to emulate, could be lots of work and very slow.
5724	* "EMU?" - Can this be emulated?
5725	*/
5726	CPUMCPUID aGuestCpuIdStd[2];
5727	RT_ZERO(aGuestCpuIdStd);
5728	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5729
5730	/* CPUID(1).ecx */
5731	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5732	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5733	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5734	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5735	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5736	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5737	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5738	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5739	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5740	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5741	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5742	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5743	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5744	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5745	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5746	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5747	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5748	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5749	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5750	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5751	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5752	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5753	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5754	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5755	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5756	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5757	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5758	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5759	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5760	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5761	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5762	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5763
5764	/* CPUID(1).edx */
5765	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5766	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5767	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5768	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5769	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5770	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5771	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5772	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5773	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5774	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5775	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5776	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5777	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5778	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5779	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5780	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5781	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5782	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5783	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5784	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5785	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5786	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5787	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5788	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5789	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5790	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5791	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5792	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5793	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5794	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5795	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5796	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5797
5798	/* CPUID(0x80000000). */
5799	CPUMCPUID aGuestCpuIdExt[2];
5800	RT_ZERO(aGuestCpuIdExt);
5801	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5802	{
5803	/** @todo deal with no 0x80000001 on the host. */
5804	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5805	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5806
5807	/* CPUID(0x80000001).ecx */
5808	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5809	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5810	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5811	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5812	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5813	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5814	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5815	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5816	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5817	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5818	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5819	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5820	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5821	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5822	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5823	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5824	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5825	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5826	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5827	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5828	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5829	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5830	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5831	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5832	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5833	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5834	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5835	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5836	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5837	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5838	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5839	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5840
5841	/* CPUID(0x80000001).edx */
5842	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5843	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5844	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5845	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5846	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5847	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5848	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5849	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5850	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5851	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5852	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5853	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5854	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5855	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5856	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5857	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5858	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5859	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5860	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5861	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5862	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5863	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5864	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5865	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5866	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5867	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5868	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5869	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5870	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5871	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5872	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5873	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5874	}
5875
5876	/** @todo check leaf 7 */
5877
5878	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5879	* ECX=0: EAX - Valid bits in XCR0[31:0].
5880	* EBX - Maximum state size as per current XCR0 value.
5881	* ECX - Maximum state size for all supported features.
5882	* EDX - Valid bits in XCR0[63:32].
5883	* ECX=1: EAX - Various X-features.
5884	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5885	* ECX - Valid bits in IA32_XSS[31:0].
5886	* EDX - Valid bits in IA32_XSS[63:32].
5887	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5888	* if the bit invalid all four registers are set to zero.
5889	* EAX - The state size for this feature.
5890	* EBX - The state byte offset of this feature.
5891	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5892	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5893	*/
5894	uint64_t fGuestXcr0Mask = 0;
5895	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5896	if ( pCurLeaf
5897	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5898	&& ( pCurLeaf->uEax
5899	\|\| pCurLeaf->uEbx
5900	\|\| pCurLeaf->uEcx
5901	\|\| pCurLeaf->uEdx) )
5902	{
5903	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5904	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5905	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5906	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5907	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5908	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5909	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5910	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5911
5912	/* We don't support any additional features yet. */
5913	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5914	if (pCurLeaf && pCurLeaf->uEax)
5915	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5916	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5917	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5918	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5919	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5920	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5921
5922
5923	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5924	{
5925	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5926	if (pCurLeaf)
5927	{
5928	/* If advertised, the state component offset and size must match the one used by host. */
5929	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5930	{
5931	CPUMCPUID RawHost;
5932	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5933	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5934	if ( RawHost.uEbx != pCurLeaf->uEbx
5935	\|\| RawHost.uEax != pCurLeaf->uEax)
5936	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5937	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5938	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5939	}
5940	}
5941	}
5942	}
5943	/* Clear leaf 0xd just in case we're loading an old state... */
5944	else if (pCurLeaf)
5945	{
5946	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5947	{
5948	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5949	if (pCurLeaf)
5950	{
5951	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5952	\|\| ( pCurLeaf->uEax == 0
5953	&& pCurLeaf->uEbx == 0
5954	&& pCurLeaf->uEcx == 0
5955	&& pCurLeaf->uEdx == 0),
5956	("uVersion=%#x; %#x %#x %#x %#x\n",
5957	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5958	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5959	}
5960	}
5961	}
5962
5963	/* Update the fXStateGuestMask value for the VM. */
5964	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5965	{
5966	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5967	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5968	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5969	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5970	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5971	}
5972
5973	#undef CPUID_CHECK_RET
5974	#undef CPUID_CHECK_WRN
5975	#undef CPUID_CHECK2_RET
5976	#undef CPUID_CHECK2_WRN
5977	#undef CPUID_RAW_FEATURE_RET
5978	#undef CPUID_RAW_FEATURE_WRN
5979	#undef CPUID_RAW_FEATURE_IGN
5980	#undef CPUID_GST_FEATURE_RET
5981	#undef CPUID_GST_FEATURE_WRN
5982	#undef CPUID_GST_FEATURE_EMU
5983	#undef CPUID_GST_FEATURE_IGN
5984	#undef CPUID_GST_FEATURE2_RET
5985	#undef CPUID_GST_FEATURE2_WRN
5986	#undef CPUID_GST_FEATURE2_EMU
5987	#undef CPUID_GST_FEATURE2_IGN
5988	#undef CPUID_GST_AMD_FEATURE_RET
5989	#undef CPUID_GST_AMD_FEATURE_WRN
5990	#undef CPUID_GST_AMD_FEATURE_EMU
5991	#undef CPUID_GST_AMD_FEATURE_IGN
5992
5993	/*
5994	* We're good, commit the CPU ID leaves.
5995	*/
5996	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5997	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5998	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5999	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
6000	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
6001	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
6002	AssertLogRelRCReturn(rc, rc);
6003
6004	return VINF_SUCCESS;
6005	}
6006
6007
6008	/**
6009	* Loads the CPU ID leaves saved by pass 0.
6010	*
6011	* @returns VBox status code.
6012	* @param pVM The cross context VM structure.
6013	* @param pSSM The saved state handle.
6014	* @param uVersion The format version.
6015	* @param pMsrs The guest MSRs.
6016	*/
6017	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
6018	{
6019	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
6020
6021	/*
6022	* Load the CPUID leaves array first and call worker to do the rest, just so
6023	* we can free the memory when we need to without ending up in column 1000.
6024	*/
6025	PCPUMCPUIDLEAF paLeaves;
6026	uint32_t cLeaves;
6027	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
6028	AssertRC(rc);
6029	if (RT_SUCCESS(rc))
6030	{
6031	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
6032	RTMemFree(paLeaves);
6033	}
6034	return rc;
6035	}
6036
6037
6038
6039	/**
6040	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
6041	*
6042	* @returns VBox status code.
6043	* @param pVM The cross context VM structure.
6044	* @param pSSM The saved state handle.
6045	* @param uVersion The format version.
6046	*/
6047	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
6048	{
6049	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
6050
6051	/*
6052	* Restore the CPUID leaves.
6053	*
6054	* Note that we support restoring less than the current amount of standard
6055	* leaves because we've been allowed more is newer version of VBox.
6056	*/
6057	uint32_t cElements;
6058	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6059	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
6060	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6061	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
6062
6063	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6064	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
6065	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6066	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
6067
6068	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6069	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
6070	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6071	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
6072
6073	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
6074
6075	/*
6076	* Check that the basic cpuid id information is unchanged.
6077	*/
6078	/** @todo we should check the 64 bits capabilities too! */
6079	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
6080	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
6081	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
6082	uint32_t au32CpuIdSaved[8];
6083	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
6084	if (RT_SUCCESS(rc))
6085	{
6086	/* Ignore CPU stepping. */
6087	au32CpuId[4] &= 0xfffffff0;
6088	au32CpuIdSaved[4] &= 0xfffffff0;
6089
6090	/* Ignore APIC ID (AMD specs). */
6091	au32CpuId[5] &= ~0xff000000;
6092	au32CpuIdSaved[5] &= ~0xff000000;
6093
6094	/* Ignore the number of Logical CPUs (AMD specs). */
6095	au32CpuId[5] &= ~0x00ff0000;
6096	au32CpuIdSaved[5] &= ~0x00ff0000;
6097
6098	/* Ignore some advanced capability bits, that we don't expose to the guest. */
6099	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6100	\| X86_CPUID_FEATURE_ECX_VMX
6101	\| X86_CPUID_FEATURE_ECX_SMX
6102	\| X86_CPUID_FEATURE_ECX_EST
6103	\| X86_CPUID_FEATURE_ECX_TM2
6104	\| X86_CPUID_FEATURE_ECX_CNTXID
6105	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6106	\| X86_CPUID_FEATURE_ECX_PDCM
6107	\| X86_CPUID_FEATURE_ECX_DCA
6108	\| X86_CPUID_FEATURE_ECX_X2APIC
6109	);
6110	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6111	\| X86_CPUID_FEATURE_ECX_VMX
6112	\| X86_CPUID_FEATURE_ECX_SMX
6113	\| X86_CPUID_FEATURE_ECX_EST
6114	\| X86_CPUID_FEATURE_ECX_TM2
6115	\| X86_CPUID_FEATURE_ECX_CNTXID
6116	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6117	\| X86_CPUID_FEATURE_ECX_PDCM
6118	\| X86_CPUID_FEATURE_ECX_DCA
6119	\| X86_CPUID_FEATURE_ECX_X2APIC
6120	);
6121
6122	/* Make sure we don't forget to update the masks when enabling
6123	* features in the future.
6124	*/
6125	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
6126	( X86_CPUID_FEATURE_ECX_DTES64
6127	\| X86_CPUID_FEATURE_ECX_VMX
6128	\| X86_CPUID_FEATURE_ECX_SMX
6129	\| X86_CPUID_FEATURE_ECX_EST
6130	\| X86_CPUID_FEATURE_ECX_TM2
6131	\| X86_CPUID_FEATURE_ECX_CNTXID
6132	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6133	\| X86_CPUID_FEATURE_ECX_PDCM
6134	\| X86_CPUID_FEATURE_ECX_DCA
6135	\| X86_CPUID_FEATURE_ECX_X2APIC
6136	)));
6137	/* do the compare */
6138	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
6139	{
6140	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
6141	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
6142	"Saved=%.*Rhxs\n"
6143	"Real =%.*Rhxs\n",
6144	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6145	sizeof(au32CpuId), au32CpuId));
6146	else
6147	{
6148	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
6149	"Saved=%.*Rhxs\n"
6150	"Real =%.*Rhxs\n",
6151	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6152	sizeof(au32CpuId), au32CpuId));
6153	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
6154	}
6155	}
6156	}
6157
6158	return rc;
6159	}
6160
6161
6162
6163	/*
6164	*
6165	*
6166	* CPUID Info Handler.
6167	* CPUID Info Handler.
6168	* CPUID Info Handler.
6169	*
6170	*
6171	*/
6172
6173
6174
6175	/**
6176	* Get L1 cache / TLS associativity.
6177	*/
6178	static const char getCacheAss(unsigned u, char pszBuf)
6179	{
6180	if (u == 0)
6181	return "res0 ";
6182	if (u == 1)
6183	return "direct";
6184	if (u == 255)
6185	return "fully";
6186	if (u >= 256)
6187	return "???";
6188
6189	RTStrPrintf(pszBuf, 16, "%d way", u);
6190	return pszBuf;
6191	}
6192
6193
6194	/**
6195	* Get L2 cache associativity.
6196	*/
6197	const char *getL2CacheAss(unsigned u)
6198	{
6199	switch (u)
6200	{
6201	case 0: return "off ";
6202	case 1: return "direct";
6203	case 2: return "2 way ";
6204	case 3: return "res3 ";
6205	case 4: return "4 way ";
6206	case 5: return "res5 ";
6207	case 6: return "8 way ";
6208	case 7: return "res7 ";
6209	case 8: return "16 way";
6210	case 9: return "res9 ";
6211	case 10: return "res10 ";
6212	case 11: return "res11 ";
6213	case 12: return "res12 ";
6214	case 13: return "res13 ";
6215	case 14: return "res14 ";
6216	case 15: return "fully ";
6217	default: return "????";
6218	}
6219	}
6220
6221
6222	/** CPUID(1).EDX field descriptions. */
6223	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6224	{
6225	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6226	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6227	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6228	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6229	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6230	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6231	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6232	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6233	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6234	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6235	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6236	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6237	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6238	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6239	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6240	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6241	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6242	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6243	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6244	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6245	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6246	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6247	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6248	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6249	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6250	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6251	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6252	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6253	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6254	DBGFREGSUBFIELD_TERMINATOR()
6255	};
6256
6257	/** CPUID(1).ECX field descriptions. */
6258	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6259	{
6260	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6261	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6262	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6263	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6264	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6265	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6266	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6267	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6268	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6269	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6270	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6271	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6272	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6273	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6274	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6275	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6276	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6277	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6278	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6279	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6280	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6281	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6282	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6283	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6284	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6285	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6286	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6287	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6288	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6289	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6290	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6291	DBGFREGSUBFIELD_TERMINATOR()
6292	};
6293
6294	/** CPUID(7,0).EBX field descriptions. */
6295	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6296	{
6297	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6298	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6299	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6300	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6301	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6302	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6303	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6304	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6305	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6306	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6307	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6308	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6309	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6310	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6311	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6312	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6313	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6314	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6315	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6316	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6317	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6318	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6319	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6320	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6321	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6322	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6323	DBGFREGSUBFIELD_TERMINATOR()
6324	};
6325
6326	/** CPUID(7,0).ECX field descriptions. */
6327	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6328	{
6329	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6330	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6331	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6332	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6333	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6334	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6335	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6336	DBGFREGSUBFIELD_TERMINATOR()
6337	};
6338
6339	/** CPUID(7,0).EDX field descriptions. */
6340	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6341	{
6342	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6343	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6344	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6345	DBGFREGSUBFIELD_TERMINATOR()
6346	};
6347
6348
6349	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6350	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6351	{
6352	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6353	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6354	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6355	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6356	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6357	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6358	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6359	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6360	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6361	DBGFREGSUBFIELD_TERMINATOR()
6362	};
6363
6364	/** CPUID(13,1).EAX field descriptions. */
6365	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6366	{
6367	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6368	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6369	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6370	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6371	DBGFREGSUBFIELD_TERMINATOR()
6372	};
6373
6374
6375	/** CPUID(0x80000001,0).EDX field descriptions. */
6376	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6377	{
6378	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6379	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6380	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6381	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6382	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6383	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6384	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6385	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6386	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6387	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6388	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6389	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6390	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6391	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6392	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6393	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6394	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6395	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6396	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6397	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6398	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6399	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6400	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6401	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6402	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6403	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6404	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6405	DBGFREGSUBFIELD_TERMINATOR()
6406	};
6407
6408	/** CPUID(0x80000001,0).ECX field descriptions. */
6409	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6410	{
6411	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6412	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6413	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6414	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6415	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6416	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6417	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6418	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6419	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6420	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6421	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6422	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6423	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6424	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6425	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6426	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6427	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6428	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6429	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6430	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6431	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6432	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6433	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6434	DBGFREGSUBFIELD_TERMINATOR()
6435	};
6436
6437	/** CPUID(0x8000000a,0).EDX field descriptions. */
6438	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
6439	{
6440	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
6441	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
6442	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
6443	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
6444	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
6445	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
6446	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
6447	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
6448	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
6449	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
6450	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
6451	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
6452	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
6453	DBGFREGSUBFIELD_TERMINATOR()
6454	};
6455
6456
6457	/** CPUID(0x80000007,0).EDX field descriptions. */
6458	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6459	{
6460	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6461	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6462	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6463	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6464	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6465	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6466	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6467	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6468	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6469	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6470	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6471	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6472	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6473	DBGFREGSUBFIELD_TERMINATOR()
6474	};
6475
6476	/** CPUID(0x80000008,0).EBX field descriptions. */
6477	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6478	{
6479	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6480	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6481	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6482	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6483	DBGFREGSUBFIELD_TERMINATOR()
6484	};
6485
6486
6487	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6488	const char *pszLeadIn, uint32_t cchWidth)
6489	{
6490	if (pszLeadIn)
6491	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6492
6493	for (uint32_t iBit = 0; iBit < 32; iBit++)
6494	if (RT_BIT_32(iBit) & uVal)
6495	{
6496	while ( pDesc->pszName != NULL
6497	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6498	pDesc++;
6499	if ( pDesc->pszName != NULL
6500	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6501	{
6502	if (pDesc->cBits == 1)
6503	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6504	else
6505	{
6506	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6507	if (pDesc->cBits < 32)
6508	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6509	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6510	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6511	}
6512	}
6513	else
6514	pHlp->pfnPrintf(pHlp, " %u", iBit);
6515	}
6516	if (pszLeadIn)
6517	pHlp->pfnPrintf(pHlp, "\n");
6518	}
6519
6520
6521	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6522	const char *pszLeadIn, uint32_t cchWidth)
6523	{
6524	if (pszLeadIn)
6525	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6526
6527	for (uint32_t iBit = 0; iBit < 64; iBit++)
6528	if (RT_BIT_64(iBit) & uVal)
6529	{
6530	while ( pDesc->pszName != NULL
6531	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6532	pDesc++;
6533	if ( pDesc->pszName != NULL
6534	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6535	{
6536	if (pDesc->cBits == 1)
6537	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6538	else
6539	{
6540	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6541	if (pDesc->cBits < 64)
6542	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6543	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6544	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6545	}
6546	}
6547	else
6548	pHlp->pfnPrintf(pHlp, " %u", iBit);
6549	}
6550	if (pszLeadIn)
6551	pHlp->pfnPrintf(pHlp, "\n");
6552	}
6553
6554
6555	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6556	const char *pszLeadIn, uint32_t cchWidth)
6557	{
6558	if (!uVal)
6559	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6560	else
6561	{
6562	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6563	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6564	pHlp->pfnPrintf(pHlp, " )\n");
6565	}
6566	}
6567
6568
6569	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6570	uint32_t cchWidth)
6571	{
6572	uint32_t uCombined = uVal1 \| uVal2;
6573	for (uint32_t iBit = 0; iBit < 32; iBit++)
6574	if ( (RT_BIT_32(iBit) & uCombined)
6575	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6576	{
6577	while ( pDesc->pszName != NULL
6578	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6579	pDesc++;
6580
6581	if ( pDesc->pszName != NULL
6582	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6583	{
6584	size_t cchMnemonic = strlen(pDesc->pszName);
6585	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6586	size_t cchDesc = strlen(pszDesc);
6587	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6588	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6589	if (pDesc->cBits < 32)
6590	{
6591	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6592	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6593	}
6594
6595	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6596	pDesc->pszName, pszDesc,
6597	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6598	uFieldValue1, uFieldValue2);
6599
6600	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6601	pDesc++;
6602	}
6603	else
6604	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6605	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6606	}
6607	}
6608
6609
6610	/**
6611	* Produces a detailed summary of standard leaf 0x00000001.
6612	*
6613	* @param pHlp The info helper functions.
6614	* @param pCurLeaf The 0x00000001 leaf.
6615	* @param fVerbose Whether to be very verbose or not.
6616	* @param fIntel Set if intel CPU.
6617	*/
6618	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6619	{
6620	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6621	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6622	uint32_t uEAX = pCurLeaf->uEax;
6623	uint32_t uEBX = pCurLeaf->uEbx;
6624
6625	pHlp->pfnPrintf(pHlp,
6626	"%36s %2d \tExtended: %d \tEffective: %d\n"
6627	"%36s %2d \tExtended: %d \tEffective: %d\n"
6628	"%36s %d\n"
6629	"%36s %d (%s)\n"
6630	"%36s %#04x\n"
6631	"%36s %d\n"
6632	"%36s %d\n"
6633	"%36s %#04x\n"
6634	,
6635	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6636	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6637	"Stepping:", ASMGetCpuStepping(uEAX),
6638	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6639	"APIC ID:", (uEBX >> 24) & 0xff,
6640	"Logical CPUs:",(uEBX >> 16) & 0xff,
6641	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6642	"Brand ID:", (uEBX >> 0) & 0xff);
6643	if (fVerbose)
6644	{
6645	CPUMCPUID Host;
6646	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6647	pHlp->pfnPrintf(pHlp, "Features\n");
6648	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6649	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6650	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6651	}
6652	else
6653	{
6654	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6655	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6656	}
6657	}
6658
6659
6660	/**
6661	* Produces a detailed summary of standard leaf 0x00000007.
6662	*
6663	* @param pHlp The info helper functions.
6664	* @param paLeaves The CPUID leaves array.
6665	* @param cLeaves The number of leaves in the array.
6666	* @param pCurLeaf The first 0x00000007 leaf.
6667	* @param fVerbose Whether to be very verbose or not.
6668	*/
6669	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6670	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6671	{
6672	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6673	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6674	for (;;)
6675	{
6676	CPUMCPUID Host;
6677	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6678
6679	switch (pCurLeaf->uSubLeaf)
6680	{
6681	case 0:
6682	if (fVerbose)
6683	{
6684	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6685	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6686	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6687	if (pCurLeaf->uEdx \|\| Host.uEdx)
6688	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6689	}
6690	else
6691	{
6692	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6693	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6694	if (pCurLeaf->uEdx)
6695	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6696	}
6697	break;
6698
6699	default:
6700	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6701	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6702	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6703	break;
6704
6705	}
6706
6707	/* advance. */
6708	pCurLeaf++;
6709	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6710	\|\| pCurLeaf->uLeaf != 0x7)
6711	break;
6712	}
6713	}
6714
6715
6716	/**
6717	* Produces a detailed summary of standard leaf 0x0000000d.
6718	*
6719	* @param pHlp The info helper functions.
6720	* @param paLeaves The CPUID leaves array.
6721	* @param cLeaves The number of leaves in the array.
6722	* @param pCurLeaf The first 0x00000007 leaf.
6723	* @param fVerbose Whether to be very verbose or not.
6724	*/
6725	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6726	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6727	{
6728	RT_NOREF_PV(fVerbose);
6729	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6730	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6731	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6732	{
6733	CPUMCPUID Host;
6734	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6735
6736	switch (uSubLeaf)
6737	{
6738	case 0:
6739	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6740	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6741	pCurLeaf->uEbx, pCurLeaf->uEcx);
6742	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6743
6744	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6745	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6746	"Valid XCR0 bits, guest:", 42);
6747	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6748	"Valid XCR0 bits, host:", 42);
6749	break;
6750
6751	case 1:
6752	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6753	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6754	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6755
6756	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6757	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6758	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6759
6760	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6761	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6762	" Valid IA32_XSS bits, guest:", 42);
6763	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6764	" Valid IA32_XSS bits, host:", 42);
6765	break;
6766
6767	default:
6768	if ( pCurLeaf
6769	&& pCurLeaf->uSubLeaf == uSubLeaf
6770	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6771	{
6772	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6773	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6774	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6775	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6776	if (pCurLeaf->uEdx)
6777	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6778	pHlp->pfnPrintf(pHlp, " --");
6779	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6780	pHlp->pfnPrintf(pHlp, "\n");
6781	}
6782	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6783	{
6784	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6785	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6786	if (Host.uEcx & ~RT_BIT_32(0))
6787	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6788	if (Host.uEdx)
6789	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6790	pHlp->pfnPrintf(pHlp, " --");
6791	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6792	pHlp->pfnPrintf(pHlp, "\n");
6793	}
6794	break;
6795
6796	}
6797
6798	/* advance. */
6799	if (pCurLeaf)
6800	{
6801	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6802	&& pCurLeaf->uSubLeaf <= uSubLeaf
6803	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6804	pCurLeaf++;
6805	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6806	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6807	pCurLeaf = NULL;
6808	}
6809	}
6810	}
6811
6812
6813	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6814	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6815	{
6816	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6817	&& pCurLeaf->uLeaf <= uUpToLeaf)
6818	{
6819	pHlp->pfnPrintf(pHlp,
6820	" %s\n"
6821	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6822	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6823	&& pCurLeaf->uLeaf <= uUpToLeaf)
6824	{
6825	CPUMCPUID Host;
6826	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6827	pHlp->pfnPrintf(pHlp,
6828	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6829	"Hst: %08x %08x %08x %08x\n",
6830	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6831	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6832	pCurLeaf++;
6833	}
6834	}
6835
6836	return pCurLeaf;
6837	}
6838
6839
6840	/**
6841	* Display the guest CpuId leaves.
6842	*
6843	* @param pVM The cross context VM structure.
6844	* @param pHlp The info helper functions.
6845	* @param pszArgs "terse", "default" or "verbose".
6846	*/
6847	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6848	{
6849	/*
6850	* Parse the argument.
6851	*/
6852	unsigned iVerbosity = 1;
6853	if (pszArgs)
6854	{
6855	pszArgs = RTStrStripL(pszArgs);
6856	if (!strcmp(pszArgs, "terse"))
6857	iVerbosity--;
6858	else if (!strcmp(pszArgs, "verbose"))
6859	iVerbosity++;
6860	}
6861
6862	uint32_t uLeaf;
6863	CPUMCPUID Host;
6864	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6865	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6866	PCCPUMCPUIDLEAF pCurLeaf;
6867	PCCPUMCPUIDLEAF pNextLeaf;
6868	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6869	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6870	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6871
6872	/*
6873	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6874	*/
6875	uint32_t cHstMax = ASMCpuId_EAX(0);
6876	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6877	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6878	pHlp->pfnPrintf(pHlp,
6879	" Raw Standard CPUID Leaves\n"
6880	" Leaf/sub-leaf eax ebx ecx edx\n");
6881	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6882	{
6883	uint32_t cMaxSubLeaves = 1;
6884	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6885	cMaxSubLeaves = 16;
6886	else if (uLeaf == 0xd)
6887	cMaxSubLeaves = 128;
6888
6889	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6890	{
6891	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6892	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6893	&& pCurLeaf->uLeaf == uLeaf
6894	&& pCurLeaf->uSubLeaf == uSubLeaf)
6895	{
6896	pHlp->pfnPrintf(pHlp,
6897	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6898	"Hst: %08x %08x %08x %08x\n",
6899	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6900	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6901	pCurLeaf++;
6902	}
6903	else if ( uLeaf != 0xd
6904	\|\| uSubLeaf <= 1
6905	\|\| Host.uEbx != 0 )
6906	pHlp->pfnPrintf(pHlp,
6907	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6908	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6909
6910	/* Done? */
6911	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6912	\|\| pCurLeaf->uLeaf != uLeaf)
6913	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6914	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6915	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6916	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6917	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6918	)
6919	)
6920	break;
6921	}
6922	}
6923	pNextLeaf = pCurLeaf;
6924
6925	/*
6926	* If verbose, decode it.
6927	*/
6928	if (iVerbosity && paLeaves[0].uLeaf == 0)
6929	pHlp->pfnPrintf(pHlp,
6930	"%36s %.04s%.04s%.04s\n"
6931	"%36s 0x00000000-%#010x\n"
6932	,
6933	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6934	"Supports:", paLeaves[0].uEax);
6935
6936	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6937	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6938
6939	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6940	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6941
6942	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6943	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6944
6945	pCurLeaf = pNextLeaf;
6946
6947	/*
6948	* Hypervisor leaves.
6949	*
6950	* Unlike most of the other leaves reported, the guest hypervisor leaves
6951	* aren't a subset of the host CPUID bits.
6952	*/
6953	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6954
6955	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6956	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6957	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6958	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6959	cMax = RT_MAX(cHstMax, cGstMax);
6960	if (cMax >= UINT32_C(0x40000000))
6961	{
6962	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6963
6964	/** @todo dump these in more detail. */
6965
6966	pCurLeaf = pNextLeaf;
6967	}
6968
6969
6970	/*
6971	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6972	* Implemented after AMD specs.
6973	*/
6974	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6975
6976	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6977	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6978	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6979	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6980	cMax = RT_MAX(cHstMax, cGstMax);
6981	if (cMax >= UINT32_C(0x80000000))
6982	{
6983
6984	pHlp->pfnPrintf(pHlp,
6985	" Raw Extended CPUID Leaves\n"
6986	" Leaf/sub-leaf eax ebx ecx edx\n");
6987	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6988	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6989	{
6990	uint32_t cMaxSubLeaves = 1;
6991	if (uLeaf == UINT32_C(0x8000001d))
6992	cMaxSubLeaves = 16;
6993
6994	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6995	{
6996	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6997	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6998	&& pCurLeaf->uLeaf == uLeaf
6999	&& pCurLeaf->uSubLeaf == uSubLeaf)
7000	{
7001	pHlp->pfnPrintf(pHlp,
7002	"Gst: %08x/%04x %08x %08x %08x %08x\n"
7003	"Hst: %08x %08x %08x %08x\n",
7004	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
7005	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
7006	pCurLeaf++;
7007	}
7008	else if ( uLeaf != 0xd
7009	\|\| uSubLeaf <= 1
7010	\|\| Host.uEbx != 0 )
7011	pHlp->pfnPrintf(pHlp,
7012	"Hst: %08x/%04x %08x %08x %08x %08x\n",
7013	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
7014
7015	/* Done? */
7016	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
7017	\|\| pCurLeaf->uLeaf != uLeaf)
7018	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
7019	break;
7020	}
7021	}
7022	pNextLeaf = pCurLeaf;
7023
7024	/*
7025	* Understandable output
7026	*/
7027	if (iVerbosity)
7028	pHlp->pfnPrintf(pHlp,
7029	"Ext Name: %.4s%.4s%.4s\n"
7030	"Ext Supports: 0x80000000-%#010x\n",
7031	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
7032
7033	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
7034	if (iVerbosity && pCurLeaf)
7035	{
7036	uint32_t uEAX = pCurLeaf->uEax;
7037	pHlp->pfnPrintf(pHlp,
7038	"Family: %d \tExtended: %d \tEffective: %d\n"
7039	"Model: %d \tExtended: %d \tEffective: %d\n"
7040	"Stepping: %d\n"
7041	"Brand ID: %#05x\n",
7042	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
7043	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
7044	ASMGetCpuStepping(uEAX),
7045	pCurLeaf->uEbx & 0xfff);
7046
7047	if (iVerbosity == 1)
7048	{
7049	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
7050	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
7051	}
7052	else
7053	{
7054	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7055	pHlp->pfnPrintf(pHlp, "Ext Features\n");
7056	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
7057	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
7058	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
7059	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
7060	{
7061	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
7062	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7063	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
7064	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
7065	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
7066	}
7067	}
7068	}
7069
7070	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
7071	{
7072	char szString[443+1] = {0};
7073	uint32_t pu32 = (uint32_t )szString;
7074	*pu32++ = pCurLeaf->uEax;
7075	*pu32++ = pCurLeaf->uEbx;
7076	*pu32++ = pCurLeaf->uEcx;
7077	*pu32++ = pCurLeaf->uEdx;
7078	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
7079	if (pCurLeaf)
7080	{
7081	*pu32++ = pCurLeaf->uEax;
7082	*pu32++ = pCurLeaf->uEbx;
7083	*pu32++ = pCurLeaf->uEcx;
7084	*pu32++ = pCurLeaf->uEdx;
7085	}
7086	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
7087	if (pCurLeaf)
7088	{
7089	*pu32++ = pCurLeaf->uEax;
7090	*pu32++ = pCurLeaf->uEbx;
7091	*pu32++ = pCurLeaf->uEcx;
7092	*pu32++ = pCurLeaf->uEdx;
7093	}
7094	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
7095	}
7096
7097	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
7098	{
7099	uint32_t uEAX = pCurLeaf->uEax;
7100	uint32_t uEBX = pCurLeaf->uEbx;
7101	uint32_t uECX = pCurLeaf->uEcx;
7102	uint32_t uEDX = pCurLeaf->uEdx;
7103	char sz1[32];
7104	char sz2[32];
7105
7106	pHlp->pfnPrintf(pHlp,
7107	"TLB 2/4M Instr/Uni: %s %3d entries\n"
7108	"TLB 2/4M Data: %s %3d entries\n",
7109	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
7110	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
7111	pHlp->pfnPrintf(pHlp,
7112	"TLB 4K Instr/Uni: %s %3d entries\n"
7113	"TLB 4K Data: %s %3d entries\n",
7114	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
7115	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
7116	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
7117	"L1 Instr Cache Lines Per Tag: %d\n"
7118	"L1 Instr Cache Associativity: %s\n"
7119	"L1 Instr Cache Size: %d KB\n",
7120	(uEDX >> 0) & 0xff,
7121	(uEDX >> 8) & 0xff,
7122	getCacheAss((uEDX >> 16) & 0xff, sz1),
7123	(uEDX >> 24) & 0xff);
7124	pHlp->pfnPrintf(pHlp,
7125	"L1 Data Cache Line Size: %d bytes\n"
7126	"L1 Data Cache Lines Per Tag: %d\n"
7127	"L1 Data Cache Associativity: %s\n"
7128	"L1 Data Cache Size: %d KB\n",
7129	(uECX >> 0) & 0xff,
7130	(uECX >> 8) & 0xff,
7131	getCacheAss((uECX >> 16) & 0xff, sz1),
7132	(uECX >> 24) & 0xff);
7133	}
7134
7135	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
7136	{
7137	uint32_t uEAX = pCurLeaf->uEax;
7138	uint32_t uEBX = pCurLeaf->uEbx;
7139	uint32_t uEDX = pCurLeaf->uEdx;
7140
7141	pHlp->pfnPrintf(pHlp,
7142	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
7143	"L2 TLB 2/4M Data: %s %4d entries\n",
7144	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
7145	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
7146	pHlp->pfnPrintf(pHlp,
7147	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
7148	"L2 TLB 4K Data: %s %4d entries\n",
7149	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
7150	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
7151	pHlp->pfnPrintf(pHlp,
7152	"L2 Cache Line Size: %d bytes\n"
7153	"L2 Cache Lines Per Tag: %d\n"
7154	"L2 Cache Associativity: %s\n"
7155	"L2 Cache Size: %d KB\n",
7156	(uEDX >> 0) & 0xff,
7157	(uEDX >> 8) & 0xf,
7158	getL2CacheAss((uEDX >> 12) & 0xf),
7159	(uEDX >> 16) & 0xffff);
7160	}
7161
7162	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
7163	{
7164	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7165	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
7166	{
7167	if (iVerbosity < 1)
7168	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
7169	else
7170	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
7171	}
7172	}
7173
7174	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
7175	if (pCurLeaf != NULL)
7176	{
7177	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7178	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
7179	{
7180	if (iVerbosity < 1)
7181	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
7182	else
7183	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
7184	}
7185
7186	if (iVerbosity)
7187	{
7188	uint32_t uEAX = pCurLeaf->uEax;
7189	uint32_t uECX = pCurLeaf->uEcx;
7190
7191	pHlp->pfnPrintf(pHlp,
7192	"Physical Address Width: %d bits\n"
7193	"Virtual Address Width: %d bits\n"
7194	"Guest Physical Address Width: %d bits\n",
7195	(uEAX >> 0) & 0xff,
7196	(uEAX >> 8) & 0xff,
7197	(uEAX >> 16) & 0xff);
7198	pHlp->pfnPrintf(pHlp,
7199	"Physical Core Count: %d\n",
7200	((uECX >> 0) & 0xff) + 1);
7201	}
7202	}
7203
7204	pCurLeaf = pNextLeaf;
7205	}
7206
7207
7208
7209	/*
7210	* Centaur.
7211	*/
7212	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7213
7214	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7215	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7216	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7217	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7218	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7219	cMax = RT_MAX(cHstMax, cGstMax);
7220	if (cMax >= UINT32_C(0xc0000000))
7221	{
7222	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7223
7224	/*
7225	* Understandable output
7226	*/
7227	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7228	pHlp->pfnPrintf(pHlp,
7229	"Centaur Supports: 0xc0000000-%#010x\n",
7230	pCurLeaf->uEax);
7231
7232	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7233	{
7234	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7235	uint32_t uEdxGst = pCurLeaf->uEdx;
7236	uint32_t uEdxHst = Host.uEdx;
7237
7238	if (iVerbosity == 1)
7239	{
7240	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7241	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7242	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7243	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7244	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7245	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7246	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7247	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7248	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7249	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7250	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7251	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7252	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7253	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7254	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7255	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7256	for (unsigned iBit = 14; iBit < 32; iBit++)
7257	if (uEdxGst & RT_BIT(iBit))
7258	pHlp->pfnPrintf(pHlp, " %d", iBit);
7259	pHlp->pfnPrintf(pHlp, "\n");
7260	}
7261	else
7262	{
7263	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7264	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7265	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7266	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7267	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7268	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7269	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7270	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7271	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7272	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7273	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7274	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7275	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7276	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7277	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7278	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7279	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7280	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7281	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7282	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7283	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7284	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7285	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7286	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7287	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7288	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7289	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7290	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7291	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7292	for (unsigned iBit = 27; iBit < 32; iBit++)
7293	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7294	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7295	pHlp->pfnPrintf(pHlp, "\n");
7296	}
7297	}
7298
7299	pCurLeaf = pNextLeaf;
7300	}
7301
7302	/*
7303	* The remainder.
7304	*/
7305	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7306	}
7307
7308
7309
7310
7311
7312	/*
7313	*
7314	*
7315	* PATM interfaces.
7316	* PATM interfaces.
7317	* PATM interfaces.
7318	*
7319	*
7320	*/
7321
7322
7323	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
7324	/** @name Patchmanager CPUID legacy table APIs
7325	* @{
7326	*/
7327
7328	/**
7329	* Gets a pointer to the default CPUID leaf.
7330	*
7331	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
7332	* @param pVM The cross context VM structure.
7333	* @remark Intended for PATM only.
7334	*/
7335	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
7336	{
7337	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
7338	}
7339
7340
7341	/**
7342	* Gets a number of standard CPUID leaves (PATM only).
7343	*
7344	* @returns Number of leaves.
7345	* @param pVM The cross context VM structure.
7346	* @remark Intended for PATM - legacy, don't use in new code.
7347	*/
7348	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
7349	{
7350	RT_NOREF_PV(pVM);
7351	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
7352	}
7353
7354
7355	/**
7356	* Gets a number of extended CPUID leaves (PATM only).
7357	*
7358	* @returns Number of leaves.
7359	* @param pVM The cross context VM structure.
7360	* @remark Intended for PATM - legacy, don't use in new code.
7361	*/
7362	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
7363	{
7364	RT_NOREF_PV(pVM);
7365	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
7366	}
7367
7368
7369	/**
7370	* Gets a number of centaur CPUID leaves.
7371	*
7372	* @returns Number of leaves.
7373	* @param pVM The cross context VM structure.
7374	* @remark Intended for PATM - legacy, don't use in new code.
7375	*/
7376	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
7377	{
7378	RT_NOREF_PV(pVM);
7379	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
7380	}
7381
7382
7383	/**
7384	* Gets a pointer to the array of standard CPUID leaves.
7385	*
7386	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
7387	*
7388	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
7389	* @param pVM The cross context VM structure.
7390	* @remark Intended for PATM - legacy, don't use in new code.
7391	*/
7392	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
7393	{
7394	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
7395	}
7396
7397
7398	/**
7399	* Gets a pointer to the array of extended CPUID leaves.
7400	*
7401	* CPUMGetGuestCpuIdExtMax() give the size of the array.
7402	*
7403	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
7404	* @param pVM The cross context VM structure.
7405	* @remark Intended for PATM - legacy, don't use in new code.
7406	*/
7407	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
7408	{
7409	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
7410	}
7411
7412
7413	/**
7414	* Gets a pointer to the array of centaur CPUID leaves.
7415	*
7416	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
7417	*
7418	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
7419	* @param pVM The cross context VM structure.
7420	* @remark Intended for PATM - legacy, don't use in new code.
7421	*/
7422	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
7423	{
7424	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
7425	}
7426
7427	/** @} */
7428	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
7429
7430	#endif /* VBOX_IN_VMM */
7431

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 76570

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