CPUMR3CpuId.cpp@ 51574

Last change on this file since 51574 was 51344, checked in by vboxsync, 11 years ago
VMM/CPUM: Hyper heap fixes.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 56.8 KB

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1	/* $Id: CPUMR3CpuId.cpp 51344 2014-05-22 11:04:58Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2014 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_CPUM
22	#include <VBox/vmm/cpum.h>
23	#include "CPUMInternal.h"
24	#include <VBox/vmm/vm.h>
25	#include <VBox/vmm/mm.h>
26
27	#include <VBox/err.h>
28	#include <iprt/asm-amd64-x86.h>
29	#include <iprt/ctype.h>
30	#include <iprt/mem.h>
31	#include <iprt/string.h>
32
33
34	/*******************************************************************************
35	* Global Variables *
36	*******************************************************************************/
37	/**
38	* The intel pentium family.
39	*/
40	static const CPUMMICROARCH g_aenmIntelFamily06[] =
41	{
42	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
43	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
44	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
45	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
46	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
47	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
48	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
49	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
50	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
51	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
52	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
53	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
54	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
55	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
56	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
57	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
58	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
59	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
60	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
61	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
63	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
64	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
65	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
66	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
67	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
68	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
69	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
70	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
71	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
72	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
73	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
74	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
75	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
80	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
81	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
82	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
83	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
85	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
86	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
87	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
88	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
89	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
90	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
91	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
96	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
97	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
98	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
99	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
101	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
102	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
103	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
104	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
105	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
106	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
107	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
112	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
113	/* [71(0x47)] = */ kCpumMicroarch_Intel_Unknown,
114	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
115	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
117	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
118	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
120	/* [78(0x4e)] = */ kCpumMicroarch_Intel_Unknown,
121	/* [79(0x4f)] = */ kCpumMicroarch_Intel_Unknown,
122	};
123
124
125
126	/**
127	* Figures out the (sub-)micro architecture given a bit of CPUID info.
128	*
129	* @returns Micro architecture.
130	* @param enmVendor The CPU vendor .
131	* @param bFamily The CPU family.
132	* @param bModel The CPU model.
133	* @param bStepping The CPU stepping.
134	*/
135	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
136	uint8_t bModel, uint8_t bStepping)
137	{
138	if (enmVendor == CPUMCPUVENDOR_AMD)
139	{
140	switch (bFamily)
141	{
142	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
143	case 0x03: return kCpumMicroarch_AMD_Am386;
144	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
145	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
146	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
147	case 0x06:
148	switch (bModel)
149	{
150	case 0: kCpumMicroarch_AMD_K7_Palomino;
151	case 1: kCpumMicroarch_AMD_K7_Palomino;
152	case 2: kCpumMicroarch_AMD_K7_Palomino;
153	case 3: kCpumMicroarch_AMD_K7_Spitfire;
154	case 4: kCpumMicroarch_AMD_K7_Thunderbird;
155	case 6: kCpumMicroarch_AMD_K7_Palomino;
156	case 7: kCpumMicroarch_AMD_K7_Morgan;
157	case 8: kCpumMicroarch_AMD_K7_Thoroughbred;
158	case 10: kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
159	}
160	return kCpumMicroarch_AMD_K7_Unknown;
161	case 0x0f:
162	/*
163	* This family is a friggin mess. Trying my best to make some
164	* sense out of it. Too much happened in the 0x0f family to
165	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
166	*
167	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
168	* cpu-world.com, and other places:
169	* - 130nm:
170	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
171	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
172	* - Newcastle: FC0/DH-CG (errum #180: FE0/DH-CG), FF0/DH-CG
173	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
174	* - Odessa: FC0/DH-CG (errum #180: FE0/DH-CG)
175	* - Paris: FF0/DH-CG, FC0/DH-CG (errum #180: FE0/DH-CG),
176	* - 90nm:
177	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
178	* - Oakville: 10FC0/DH-D0.
179	* - Georgetown: 10FC0/DH-D0.
180	* - Sonora: 10FC0/DH-D0.
181	* - Venus: 20F71/SH-E4
182	* - Troy: 20F51/SH-E4
183	* - Athens: 20F51/SH-E4
184	* - San Diego: 20F71/SH-E4.
185	* - Lancaster: 20F42/SH-E5
186	* - Newark: 20F42/SH-E5.
187	* - Albany: 20FC2/DH-E6.
188	* - Roma: 20FC2/DH-E6.
189	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
190	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
191	* - 90nm introducing Dual core:
192	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
193	* - Italy: 20F10/JH-E1, 20F12/JH-E6
194	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
195	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
196	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
197	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
198	* - Santa Ana: 40F32/JH-F2, /-F3
199	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
200	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
201	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
202	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
203	* - Keene: 40FC2/DH-F2.
204	* - Richmond: 40FC2/DH-F2
205	* - Taylor: 40F82/BH-F2
206	* - Trinidad: 40F82/BH-F2
207	*
208	* - 65nm:
209	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
210	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
211	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
212	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
213	* - Sherman: /-G1, 70FC2/DH-G2.
214	* - Huron: 70FF2/DH-G2.
215	*/
216	if (bModel < 0x10)
217	return kCpumMicroarch_AMD_K8_130nm;
218	if (bModel >= 0x60 && bModel < 0x80)
219	return kCpumMicroarch_AMD_K8_65nm;
220	if (bModel >= 0x40)
221	return kCpumMicroarch_AMD_K8_90nm_AMDV;
222	switch (bModel)
223	{
224	case 0x21:
225	case 0x23:
226	case 0x2b:
227	case 0x2f:
228	case 0x37:
229	case 0x3f:
230	return kCpumMicroarch_AMD_K8_90nm_DualCore;
231	}
232	return kCpumMicroarch_AMD_K8_90nm;
233	case 0x10:
234	return kCpumMicroarch_AMD_K10;
235	case 0x11:
236	return kCpumMicroarch_AMD_K10_Lion;
237	case 0x12:
238	return kCpumMicroarch_AMD_K10_Llano;
239	case 0x14:
240	return kCpumMicroarch_AMD_Bobcat;
241	case 0x15:
242	switch (bModel)
243	{
244	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
245	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
246	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
247	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
248	case 0x11: /* ?? */
249	case 0x12: /* ?? */
250	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
251	}
252	return kCpumMicroarch_AMD_15h_Unknown;
253	case 0x16:
254	return kCpumMicroarch_AMD_Jaguar;
255
256	}
257	return kCpumMicroarch_AMD_Unknown;
258	}
259
260	if (enmVendor == CPUMCPUVENDOR_INTEL)
261	{
262	switch (bFamily)
263	{
264	case 3:
265	return kCpumMicroarch_Intel_80386;
266	case 4:
267	return kCpumMicroarch_Intel_80486;
268	case 5:
269	return kCpumMicroarch_Intel_P5;
270	case 6:
271	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
272	return g_aenmIntelFamily06[bModel];
273	return kCpumMicroarch_Intel_Atom_Unknown;
274	case 15:
275	switch (bModel)
276	{
277	case 0: return kCpumMicroarch_Intel_NB_Willamette;
278	case 1: return kCpumMicroarch_Intel_NB_Willamette;
279	case 2: return kCpumMicroarch_Intel_NB_Northwood;
280	case 3: return kCpumMicroarch_Intel_NB_Prescott;
281	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
282	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
283	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
284	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
285	default: return kCpumMicroarch_Intel_NB_Unknown;
286	}
287	break;
288	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
289	case 1:
290	return kCpumMicroarch_Intel_8086;
291	case 2:
292	return kCpumMicroarch_Intel_80286;
293	}
294	return kCpumMicroarch_Intel_Unknown;
295	}
296
297	if (enmVendor == CPUMCPUVENDOR_VIA)
298	{
299	switch (bFamily)
300	{
301	case 5:
302	switch (bModel)
303	{
304	case 1: return kCpumMicroarch_Centaur_C6;
305	case 4: return kCpumMicroarch_Centaur_C6;
306	case 8: return kCpumMicroarch_Centaur_C2;
307	case 9: return kCpumMicroarch_Centaur_C3;
308	}
309	break;
310
311	case 6:
312	switch (bModel)
313	{
314	case 5: return kCpumMicroarch_VIA_C3_M2;
315	case 6: return kCpumMicroarch_VIA_C3_C5A;
316	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
317	case 8: return kCpumMicroarch_VIA_C3_C5N;
318	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
319	case 10: return kCpumMicroarch_VIA_C7_C5J;
320	case 15: return kCpumMicroarch_VIA_Isaiah;
321	}
322	break;
323	}
324	return kCpumMicroarch_VIA_Unknown;
325	}
326
327	if (enmVendor == CPUMCPUVENDOR_CYRIX)
328	{
329	switch (bFamily)
330	{
331	case 4:
332	switch (bModel)
333	{
334	case 9: return kCpumMicroarch_Cyrix_5x86;
335	}
336	break;
337
338	case 5:
339	switch (bModel)
340	{
341	case 2: return kCpumMicroarch_Cyrix_M1;
342	case 4: return kCpumMicroarch_Cyrix_MediaGX;
343	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
344	}
345	break;
346
347	case 6:
348	switch (bModel)
349	{
350	case 0: return kCpumMicroarch_Cyrix_M2;
351	}
352	break;
353
354	}
355	return kCpumMicroarch_Cyrix_Unknown;
356	}
357
358	return kCpumMicroarch_Unknown;
359	}
360
361
362	/**
363	* Translates a microarchitecture enum value to the corresponding string
364	* constant.
365	*
366	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
367	* NULL if the value is invalid.
368	*
369	* @param enmMicroarch The enum value to convert.
370	*/
371	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
372	{
373	switch (enmMicroarch)
374	{
375	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
376	CASE_RET_STR(kCpumMicroarch_Intel_8086);
377	CASE_RET_STR(kCpumMicroarch_Intel_80186);
378	CASE_RET_STR(kCpumMicroarch_Intel_80286);
379	CASE_RET_STR(kCpumMicroarch_Intel_80386);
380	CASE_RET_STR(kCpumMicroarch_Intel_80486);
381	CASE_RET_STR(kCpumMicroarch_Intel_P5);
382
383	CASE_RET_STR(kCpumMicroarch_Intel_P6);
384	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
385	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
386
387	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
388	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
389	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
390
391	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
392	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
393
394	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
395	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
396	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
397	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
398	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
399	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
400	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
401	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Cannonlake);
402
403	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
404	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
405	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
406	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
407	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
408	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
409	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
410
411	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
412	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
413	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
414	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
415	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
416	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
417	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
418
419	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
420
421	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
422	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
423	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
424	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
425	CASE_RET_STR(kCpumMicroarch_AMD_K5);
426	CASE_RET_STR(kCpumMicroarch_AMD_K6);
427
428	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
429	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
430	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
431	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
432	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
433	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
434	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
435
436	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
437	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
438	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
439	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
440	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
441
442	CASE_RET_STR(kCpumMicroarch_AMD_K10);
443	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
444	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
445	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
446	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
447
448	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
449	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
450	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
451	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
452	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
453
454	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
455
456	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
457
458	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
459	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
460	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
461	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
462	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
463	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
464	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
465	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
466	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
467	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
468	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
469	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
470	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
471
472	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
473	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
474	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
475	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
476	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
477	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
478
479	CASE_RET_STR(kCpumMicroarch_Unknown);
480
481	#undef CASE_RET_STR
482	case kCpumMicroarch_Invalid:
483	case kCpumMicroarch_Intel_End:
484	case kCpumMicroarch_Intel_Core7_End:
485	case kCpumMicroarch_Intel_Atom_End:
486	case kCpumMicroarch_Intel_P6_Core_Atom_End:
487	case kCpumMicroarch_Intel_NB_End:
488	case kCpumMicroarch_AMD_K7_End:
489	case kCpumMicroarch_AMD_K8_End:
490	case kCpumMicroarch_AMD_15h_End:
491	case kCpumMicroarch_AMD_16h_End:
492	case kCpumMicroarch_AMD_End:
493	case kCpumMicroarch_VIA_End:
494	case kCpumMicroarch_Cyrix_End:
495	case kCpumMicroarch_32BitHack:
496	break;
497	/* no default! */
498	}
499
500	return NULL;
501	}
502
503
504
505	/**
506	* Gets a matching leaf in the CPUID leaf array.
507	*
508	* @returns Pointer to the matching leaf, or NULL if not found.
509	* @param paLeaves The CPUID leaves to search. This is sorted.
510	* @param cLeaves The number of leaves in the array.
511	* @param uLeaf The leaf to locate.
512	* @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
513	*/
514	PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
515	{
516	/* Lazy bird does linear lookup here since this is only used for the
517	occational CPUID overrides. */
518	for (uint32_t i = 0; i < cLeaves; i++)
519	if ( paLeaves[i].uLeaf == uLeaf
520	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
521	return &paLeaves[i];
522	return NULL;
523	}
524
525
526	/**
527	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
528	*
529	* @returns true if found, false it not.
530	* @param paLeaves The CPUID leaves to search. This is sorted.
531	* @param cLeaves The number of leaves in the array.
532	* @param uLeaf The leaf to locate.
533	* @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
534	* @param pLegacy The legacy output leaf.
535	*/
536	bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf, PCPUMCPUID pLeagcy)
537	{
538	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
539	if (pLeaf)
540	{
541	pLeagcy->eax = pLeaf->uEax;
542	pLeagcy->ebx = pLeaf->uEbx;
543	pLeagcy->ecx = pLeaf->uEcx;
544	pLeagcy->edx = pLeaf->uEdx;
545	return true;
546	}
547	return false;
548	}
549
550
551	/**
552	* Ensures that the CPUID leaf array can hold one more leaf.
553	*
554	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
555	* failure.
556	* @param pVM Pointer to the VM, used as the heap selector. Passing
557	* NULL uses the host-context heap, otherwise the VM's
558	* hyper heap is used.
559	* @param ppaLeaves Pointer to the variable holding the array pointer
560	* (input/output).
561	* @param cLeaves The current array size.
562	*
563	* @remarks This function will automatically update the R0 and RC pointers when
564	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
565	* be the corresponding VM's CPUID arrays (which is asserted).
566	*/
567	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
568	{
569	uint32_t cAllocated;
570	if (!pVM)
571	cAllocated = RT_ALIGN(cLeaves, 16);
572	else
573	{
574	/*
575	* We're using the hyper heap now, but when the arrays were copied over to it from
576	* the host-context heap, we only copy the exact size and not the ensured size.
577	* See @bugref{7270}.
578	*/
579	cAllocated = cLeaves;
580	}
581
582	if (cLeaves + 1 > cAllocated)
583	{
584	void *pvNew;
585	#ifndef IN_VBOX_CPU_REPORT
586	if (pVM)
587	{
588	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
589	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
590
591	size_t cb = cAllocated * sizeof(**ppaLeaves);
592	size_t cbNew = (cAllocated + 16) * sizeof(**ppaLeaves);
593	int rc = MMR3HyperRealloc(pVM, *ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, &pvNew);
594	if (RT_FAILURE(rc))
595	{
596	*ppaLeaves = NULL;
597	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
598	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
599	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
600	return NULL;
601	}
602	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
603	}
604	else
605	#endif
606	{
607	pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) sizeof(**ppaLeaves));
608	if (!pvNew)
609	{
610	RTMemFree(*ppaLeaves);
611	*ppaLeaves = NULL;
612	return NULL;
613	}
614	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
615	}
616	}
617
618	#ifndef IN_VBOX_CPU_REPORT
619	/* Update the R0 and RC pointers. */
620	if (pVM)
621	{
622	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
623	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
624	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
625	}
626	#endif
627
628	return *ppaLeaves;
629	}
630
631
632	/**
633	* Append a CPUID leaf or sub-leaf.
634	*
635	* ASSUMES linear insertion order, so we'll won't need to do any searching or
636	* replace anything. Use cpumR3CpuIdInsert() for those cases.
637	*
638	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
639	* the caller need do no more work.
640	* @param ppaLeaves Pointer to the the pointer to the array of sorted
641	* CPUID leaves and sub-leaves.
642	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
643	* @param uLeaf The leaf we're adding.
644	* @param uSubLeaf The sub-leaf number.
645	* @param fSubLeafMask The sub-leaf mask.
646	* @param uEax The EAX value.
647	* @param uEbx The EBX value.
648	* @param uEcx The ECX value.
649	* @param uEdx The EDX value.
650	* @param fFlags The flags.
651	*/
652	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
653	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
654	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
655	{
656	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
657	return VERR_NO_MEMORY;
658
659	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
660	Assert( *pcLeaves == 0
661	\|\| pNew[-1].uLeaf < uLeaf
662	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
663
664	pNew->uLeaf = uLeaf;
665	pNew->uSubLeaf = uSubLeaf;
666	pNew->fSubLeafMask = fSubLeafMask;
667	pNew->uEax = uEax;
668	pNew->uEbx = uEbx;
669	pNew->uEcx = uEcx;
670	pNew->uEdx = uEdx;
671	pNew->fFlags = fFlags;
672
673	*pcLeaves += 1;
674	return VINF_SUCCESS;
675	}
676
677
678	/**
679	* Inserts a CPU ID leaf, replacing any existing ones.
680	*
681	* When inserting a simple leaf where we already got a series of subleaves with
682	* the same leaf number (eax), the simple leaf will replace the whole series.
683	*
684	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
685	* host-context heap and has only been allocated/reallocated by the
686	* cpumR3CpuIdEnsureSpace function.
687	*
688	* @returns VBox status code.
689	* @param pVM Pointer to the VM, used as the heap selector.
690	* Passing NULL uses the host-context heap, otherwise
691	* the VM's hyper heap is used.
692	* @param ppaLeaves Pointer to the the pointer to the array of sorted
693	* CPUID leaves and sub-leaves. Must be NULL if using
694	* the hyper heap.
695	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must be
696	* NULL if using the hyper heap.
697	* @param pNewLeaf Pointer to the data of the new leaf we're about to
698	* insert.
699	*/
700	int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
701	{
702	/*
703	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
704	*/
705	if (pVM)
706	{
707	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
708	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
709
710	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
711	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
712	}
713
714	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
715	uint32_t cLeaves = *pcLeaves;
716
717	/*
718	* Validate the new leaf a little.
719	*/
720	AssertReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED), VERR_INVALID_FLAGS);
721	AssertReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0, VERR_INVALID_PARAMETER);
722	AssertReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1), VERR_INVALID_PARAMETER);
723	AssertReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf, VERR_INVALID_PARAMETER);
724
725	/*
726	* Find insertion point. The lazy bird uses the same excuse as in
727	* cpumR3CpuIdGetLeaf().
728	*/
729	uint32_t i = 0;
730	while ( i < cLeaves
731	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
732	i++;
733	if ( i < cLeaves
734	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
735	{
736	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
737	{
738	/*
739	* The subleaf mask differs, replace all existing leaves with the
740	* same leaf number.
741	*/
742	uint32_t c = 1;
743	while ( i + c < cLeaves
744	&& paLeaves[i + c].uSubLeaf == pNewLeaf->uLeaf)
745	c++;
746	if (c > 1 && i + c < cLeaves)
747	{
748	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
749	*pcLeaves = cLeaves -= c - 1;
750	}
751
752	paLeaves[i] = *pNewLeaf;
753	return VINF_SUCCESS;
754	}
755
756	/* Find subleaf insertion point. */
757	while ( i < cLeaves
758	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf)
759	i++;
760
761	/*
762	* If we've got an exactly matching leaf, replace it.
763	*/
764	if ( paLeaves[i].uLeaf == pNewLeaf->uLeaf
765	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
766	{
767	paLeaves[i] = *pNewLeaf;
768	return VINF_SUCCESS;
769	}
770	}
771
772	/*
773	* Adding a new leaf at 'i'.
774	*/
775	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
776	if (!paLeaves)
777	return VERR_NO_MEMORY;
778
779	if (i < cLeaves)
780	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
781	*pcLeaves += 1;
782	paLeaves[i] = *pNewLeaf;
783	return VINF_SUCCESS;
784	}
785
786
787	/**
788	* Removes a range of CPUID leaves.
789	*
790	* This will not reallocate the array.
791	*
792	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
793	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
794	* @param uFirst The first leaf.
795	* @param uLast The last leaf.
796	*/
797	void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
798	{
799	uint32_t cLeaves = *pcLeaves;
800
801	Assert(uFirst <= uLast);
802
803	/*
804	* Find the first one.
805	*/
806	uint32_t iFirst = 0;
807	while ( iFirst < cLeaves
808	&& paLeaves[iFirst].uLeaf < uFirst)
809	iFirst++;
810
811	/*
812	* Find the end (last + 1).
813	*/
814	uint32_t iEnd = iFirst;
815	while ( iEnd < cLeaves
816	&& paLeaves[iEnd].uLeaf <= uLast)
817	iEnd++;
818
819	/*
820	* Adjust the array if anything needs removing.
821	*/
822	if (iFirst < iEnd)
823	{
824	if (iEnd < cLeaves)
825	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
826	*pcLeaves = cLeaves -= (iEnd - iFirst);
827	}
828	}
829
830
831
832	/**
833	* Checks if ECX make a difference when reading a given CPUID leaf.
834	*
835	* @returns @c true if it does, @c false if it doesn't.
836	* @param uLeaf The leaf we're reading.
837	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
838	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
839	* final sub-leaf.
840	*/
841	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
842	{
843	*pfFinalEcxUnchanged = false;
844
845	uint32_t auCur[4];
846	uint32_t auPrev[4];
847	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
848
849	/* Look for sub-leaves. */
850	uint32_t uSubLeaf = 1;
851	for (;;)
852	{
853	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
854	if (memcmp(auCur, auPrev, sizeof(auCur)))
855	break;
856
857	/* Advance / give up. */
858	uSubLeaf++;
859	if (uSubLeaf >= 64)
860	{
861	*pcSubLeaves = 1;
862	return false;
863	}
864	}
865
866	/* Count sub-leaves. */
867	uint32_t cRepeats = 0;
868	uSubLeaf = 0;
869	for (;;)
870	{
871	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
872
873	/* Figuring out when to stop isn't entirely straight forward as we need
874	to cover undocumented behavior up to a point and implementation shortcuts. */
875
876	/* 1. Look for zero values. */
877	if ( auCur[0] == 0
878	&& auCur[1] == 0
879	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
880	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */) )
881	break;
882
883	/* 2. Look for more than 4 repeating value sets. */
884	if ( auCur[0] == auPrev[0]
885	&& auCur[1] == auPrev[1]
886	&& ( auCur[2] == auPrev[2]
887	\|\| ( auCur[2] == uSubLeaf
888	&& auPrev[2] == uSubLeaf - 1) )
889	&& auCur[3] == auPrev[3])
890	{
891	cRepeats++;
892	if (cRepeats > 4)
893	break;
894	}
895	else
896	cRepeats = 0;
897
898	/* 3. Leaf 0xb level type 0 check. */
899	if ( uLeaf == 0xb
900	&& (auCur[3] & 0xff00) == 0
901	&& (auPrev[3] & 0xff00) == 0)
902	break;
903
904	/* 99. Give up. */
905	if (uSubLeaf >= 128)
906	{
907	#ifndef IN_VBOX_CPU_REPORT
908	/* Ok, limit it according to the documentation if possible just to
909	avoid annoying users with these detection issues. */
910	uint32_t cDocLimit = UINT32_MAX;
911	if (uLeaf == 0x4)
912	cDocLimit = 4;
913	else if (uLeaf == 0x7)
914	cDocLimit = 1;
915	else if (uLeaf == 0xf)
916	cDocLimit = 2;
917	if (cDocLimit != UINT32_MAX)
918	{
919	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf;
920	*pcSubLeaves = cDocLimit + 3;
921	return true;
922	}
923	#endif
924	*pcSubLeaves = UINT32_MAX;
925	return true;
926	}
927
928	/* Advance. */
929	uSubLeaf++;
930	memcpy(auPrev, auCur, sizeof(auCur));
931	}
932
933	/* Standard exit. */
934	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf;
935	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
936	return true;
937	}
938
939
940	/**
941	* Inserts a CPU ID leaf, replacing any existing ones.
942	*
943	* @returns VBox status code.
944	* @param pVM Pointer to the VM.
945	* @param pNewLeaf Pointer to the leaf being inserted.
946	*/
947	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
948	{
949	/*
950	* Validate parameters.
951	*/
952	AssertReturn(pVM, VERR_INVALID_PARAMETER);
953	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
954
955	/*
956	* Disallow replacing CPU ID leaves that this API currently cannot manage. .
957	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
958	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature(). .
959	*/
960	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
961	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
962	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000)) /* Centaur */
963	{
964	return VERR_NOT_SUPPORTED;
965	}
966
967	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
968	}
969
970
971	/**
972	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
973	*
974	* @returns VBox status code.
975	* @param ppaLeaves Where to return the array pointer on success.
976	* Use RTMemFree to release.
977	* @param pcLeaves Where to return the size of the array on
978	* success.
979	*/
980	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
981	{
982	*ppaLeaves = NULL;
983	*pcLeaves = 0;
984
985	/*
986	* Try out various candidates. This must be sorted!
987	*/
988	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
989	{
990	{ UINT32_C(0x00000000), false },
991	{ UINT32_C(0x10000000), false },
992	{ UINT32_C(0x20000000), false },
993	{ UINT32_C(0x30000000), false },
994	{ UINT32_C(0x40000000), false },
995	{ UINT32_C(0x50000000), false },
996	{ UINT32_C(0x60000000), false },
997	{ UINT32_C(0x70000000), false },
998	{ UINT32_C(0x80000000), false },
999	{ UINT32_C(0x80860000), false },
1000	{ UINT32_C(0x8ffffffe), true },
1001	{ UINT32_C(0x8fffffff), true },
1002	{ UINT32_C(0x90000000), false },
1003	{ UINT32_C(0xa0000000), false },
1004	{ UINT32_C(0xb0000000), false },
1005	{ UINT32_C(0xc0000000), false },
1006	{ UINT32_C(0xd0000000), false },
1007	{ UINT32_C(0xe0000000), false },
1008	{ UINT32_C(0xf0000000), false },
1009	};
1010
1011	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1012	{
1013	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1014	uint32_t uEax, uEbx, uEcx, uEdx;
1015	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1016
1017	/*
1018	* Does EAX look like a typical leaf count value?
1019	*/
1020	if ( uEax > uLeaf
1021	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1022	{
1023	/* Yes, dump them. */
1024	uint32_t cLeaves = uEax - uLeaf + 1;
1025	while (cLeaves-- > 0)
1026	{
1027	/* Check three times here to reduce the chance of CPU migration
1028	resulting in false positives with things like the APIC ID. */
1029	uint32_t cSubLeaves;
1030	bool fFinalEcxUnchanged;
1031	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1032	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1033	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1034	{
1035	if (cSubLeaves > 16)
1036	{
1037	/* This shouldn't happen. But in case it does, file all
1038	relevant details in the release log. */
1039	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1040	LogRel(("------------------ dump of problematic subleaves ------------------\n"));
1041	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1042	{
1043	uint32_t auTmp[4];
1044	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1045	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1046	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1047	}
1048	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1049	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1050	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1051	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1052	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1053	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1054	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1055	}
1056
1057	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1058	{
1059	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1060	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1061	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx,
1062	uSubLeaf + 1 == cSubLeaves && fFinalEcxUnchanged
1063	? CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED : 0);
1064	if (RT_FAILURE(rc))
1065	return rc;
1066	}
1067	}
1068	else
1069	{
1070	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1071	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1072	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1073	if (RT_FAILURE(rc))
1074	return rc;
1075	}
1076
1077	/* next */
1078	uLeaf++;
1079	}
1080	}
1081	/*
1082	* Special CPUIDs needs special handling as they don't follow the
1083	* leaf count principle used above.
1084	*/
1085	else if (s_aCandidates[iOuter].fSpecial)
1086	{
1087	bool fKeep = false;
1088	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1089	fKeep = true;
1090	else if ( uLeaf == 0x8fffffff
1091	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1092	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1093	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1094	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1095	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1096	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1097	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1098	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1099	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1100	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1101	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1102	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1103	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1104	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1105	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1106	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1107	fKeep = true;
1108	if (fKeep)
1109	{
1110	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1111	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1112	if (RT_FAILURE(rc))
1113	return rc;
1114	}
1115	}
1116	}
1117
1118	return VINF_SUCCESS;
1119	}
1120
1121
1122	/**
1123	* Determines the method the CPU uses to handle unknown CPUID leaves.
1124	*
1125	* @returns VBox status code.
1126	* @param penmUnknownMethod Where to return the method.
1127	* @param pDefUnknown Where to return default unknown values. This
1128	* will be set, even if the resulting method
1129	* doesn't actually needs it.
1130	*/
1131	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1132	{
1133	uint32_t uLastStd = ASMCpuId_EAX(0);
1134	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1135	if (!ASMIsValidExtRange(uLastExt))
1136	uLastExt = 0x80000000;
1137
1138	uint32_t auChecks[] =
1139	{
1140	uLastStd + 1,
1141	uLastStd + 5,
1142	uLastStd + 8,
1143	uLastStd + 32,
1144	uLastStd + 251,
1145	uLastExt + 1,
1146	uLastExt + 8,
1147	uLastExt + 15,
1148	uLastExt + 63,
1149	uLastExt + 255,
1150	0x7fbbffcc,
1151	0x833f7872,
1152	0xefff2353,
1153	0x35779456,
1154	0x1ef6d33e,
1155	};
1156
1157	static const uint32_t s_auValues[] =
1158	{
1159	0xa95d2156,
1160	0x00000001,
1161	0x00000002,
1162	0x00000008,
1163	0x00000000,
1164	0x55773399,
1165	0x93401769,
1166	0x12039587,
1167	};
1168
1169	/*
1170	* Simple method, all zeros.
1171	*/
1172	*penmUnknownMethod = CPUMUKNOWNCPUID_DEFAULTS;
1173	pDefUnknown->eax = 0;
1174	pDefUnknown->ebx = 0;
1175	pDefUnknown->ecx = 0;
1176	pDefUnknown->edx = 0;
1177
1178	/*
1179	* Intel has been observed returning the last standard leaf.
1180	*/
1181	uint32_t auLast[4];
1182	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1183
1184	uint32_t cChecks = RT_ELEMENTS(auChecks);
1185	while (cChecks > 0)
1186	{
1187	uint32_t auCur[4];
1188	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1189	if (memcmp(auCur, auLast, sizeof(auCur)))
1190	break;
1191	cChecks--;
1192	}
1193	if (cChecks == 0)
1194	{
1195	/* Now, what happens when the input changes? Esp. ECX. */
1196	uint32_t cTotal = 0;
1197	uint32_t cSame = 0;
1198	uint32_t cLastWithEcx = 0;
1199	uint32_t cNeither = 0;
1200	uint32_t cValues = RT_ELEMENTS(s_auValues);
1201	while (cValues > 0)
1202	{
1203	uint32_t uValue = s_auValues[cValues - 1];
1204	uint32_t auLastWithEcx[4];
1205	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1206	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1207
1208	cChecks = RT_ELEMENTS(auChecks);
1209	while (cChecks > 0)
1210	{
1211	uint32_t auCur[4];
1212	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1213	if (!memcmp(auCur, auLast, sizeof(auCur)))
1214	{
1215	cSame++;
1216	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1217	cLastWithEcx++;
1218	}
1219	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1220	cLastWithEcx++;
1221	else
1222	cNeither++;
1223	cTotal++;
1224	cChecks--;
1225	}
1226	cValues--;
1227	}
1228
1229	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1230	if (cSame == cTotal)
1231	*penmUnknownMethod = CPUMUKNOWNCPUID_LAST_STD_LEAF;
1232	else if (cLastWithEcx == cTotal)
1233	*penmUnknownMethod = CPUMUKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1234	else
1235	*penmUnknownMethod = CPUMUKNOWNCPUID_LAST_STD_LEAF;
1236	pDefUnknown->eax = auLast[0];
1237	pDefUnknown->ebx = auLast[1];
1238	pDefUnknown->ecx = auLast[2];
1239	pDefUnknown->edx = auLast[3];
1240	return VINF_SUCCESS;
1241	}
1242
1243	/*
1244	* Unchanged register values?
1245	*/
1246	cChecks = RT_ELEMENTS(auChecks);
1247	while (cChecks > 0)
1248	{
1249	uint32_t const uLeaf = auChecks[cChecks - 1];
1250	uint32_t cValues = RT_ELEMENTS(s_auValues);
1251	while (cValues > 0)
1252	{
1253	uint32_t uValue = s_auValues[cValues - 1];
1254	uint32_t auCur[4];
1255	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1256	if ( auCur[0] != uLeaf
1257	\|\| auCur[1] != uValue
1258	\|\| auCur[2] != uValue
1259	\|\| auCur[3] != uValue)
1260	break;
1261	cValues--;
1262	}
1263	if (cValues != 0)
1264	break;
1265	cChecks--;
1266	}
1267	if (cChecks == 0)
1268	{
1269	*penmUnknownMethod = CPUMUKNOWNCPUID_PASSTHRU;
1270	return VINF_SUCCESS;
1271	}
1272
1273	/*
1274	* Just go with the simple method.
1275	*/
1276	return VINF_SUCCESS;
1277	}
1278
1279
1280	/**
1281	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1282	*
1283	* @returns Read only name string.
1284	* @param enmUnknownMethod The method to translate.
1285	*/
1286	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUKNOWNCPUID enmUnknownMethod)
1287	{
1288	switch (enmUnknownMethod)
1289	{
1290	case CPUMUKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1291	case CPUMUKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1292	case CPUMUKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1293	case CPUMUKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1294
1295	case CPUMUKNOWNCPUID_INVALID:
1296	case CPUMUKNOWNCPUID_END:
1297	case CPUMUKNOWNCPUID_32BIT_HACK:
1298	break;
1299	}
1300	return "Invalid-unknown-CPUID-method";
1301	}
1302
1303
1304	/**
1305	* Detect the CPU vendor give n the
1306	*
1307	* @returns The vendor.
1308	* @param uEAX EAX from CPUID(0).
1309	* @param uEBX EBX from CPUID(0).
1310	* @param uECX ECX from CPUID(0).
1311	* @param uEDX EDX from CPUID(0).
1312	*/
1313	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1314	{
1315	if (ASMIsValidStdRange(uEAX))
1316	{
1317	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1318	return CPUMCPUVENDOR_AMD;
1319
1320	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1321	return CPUMCPUVENDOR_INTEL;
1322
1323	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1324	return CPUMCPUVENDOR_VIA;
1325
1326	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1327	&& uECX == UINT32_C(0x64616574)
1328	&& uEDX == UINT32_C(0x736E4978))
1329	return CPUMCPUVENDOR_CYRIX;
1330
1331	/* "Geode by NSC", example: family 5, model 9. */
1332
1333	/** @todo detect the other buggers... */
1334	}
1335
1336	return CPUMCPUVENDOR_UNKNOWN;
1337	}
1338
1339
1340	/**
1341	* Translates a CPU vendor enum value into the corresponding string constant.
1342	*
1343	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1344	* value name. This can be useful when generating code.
1345	*
1346	* @returns Read only name string.
1347	* @param enmVendor The CPU vendor value.
1348	*/
1349	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1350	{
1351	switch (enmVendor)
1352	{
1353	case CPUMCPUVENDOR_INTEL: return "INTEL";
1354	case CPUMCPUVENDOR_AMD: return "AMD";
1355	case CPUMCPUVENDOR_VIA: return "VIA";
1356	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1357	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1358
1359	case CPUMCPUVENDOR_INVALID:
1360	case CPUMCPUVENDOR_32BIT_HACK:
1361	break;
1362	}
1363	return "Invalid-cpu-vendor";
1364	}
1365
1366
1367	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1368	{
1369	/* Could do binary search, doing linear now because I'm lazy. */
1370	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1371	while (cLeaves-- > 0)
1372	{
1373	if (pLeaf->uLeaf == uLeaf)
1374	return pLeaf;
1375	pLeaf++;
1376	}
1377	return NULL;
1378	}
1379
1380
1381	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1382	{
1383	RT_ZERO(*pFeatures);
1384	if (cLeaves >= 2)
1385	{
1386	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1387	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1388
1389	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(paLeaves[0].uEax,
1390	paLeaves[0].uEbx,
1391	paLeaves[0].uEcx,
1392	paLeaves[0].uEdx);
1393	pFeatures->uFamily = ASMGetCpuFamily(paLeaves[1].uEax);
1394	pFeatures->uModel = ASMGetCpuModel(paLeaves[1].uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1395	pFeatures->uStepping = ASMGetCpuStepping(paLeaves[1].uEax);
1396	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1397	pFeatures->uFamily,
1398	pFeatures->uModel,
1399	pFeatures->uStepping);
1400
1401	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1402	if (pLeaf)
1403	pFeatures->cMaxPhysAddrWidth = pLeaf->uEax & 0xff;
1404	else if (paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1405	pFeatures->cMaxPhysAddrWidth = 36;
1406	else
1407	pFeatures->cMaxPhysAddrWidth = 32;
1408
1409	/* Standard features. */
1410	pFeatures->fMsr = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_MSR);
1411	pFeatures->fApic = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_APIC);
1412	pFeatures->fX2Apic = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1413	pFeatures->fPse = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE);
1414	pFeatures->fPse36 = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1415	pFeatures->fPae = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PAE);
1416	pFeatures->fPat = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PAT);
1417	pFeatures->fFxSaveRstor = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1418	pFeatures->fSysEnter = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_SEP);
1419	pFeatures->fHypervisorPresent = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_HVP);
1420	pFeatures->fMonitorMWait = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1421
1422	/* Extended features. */
1423	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1424	if (pExtLeaf)
1425	{
1426	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1427	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1428	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1429	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1430	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1431	}
1432
1433	if ( pExtLeaf
1434	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1435	{
1436	/* AMD features. */
1437	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1438	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1439	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1440	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1441	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1442	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1443	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1444	}
1445
1446	/*
1447	* Quirks.
1448	*/
1449	pFeatures->fLeakyFxSR = pExtLeaf
1450	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1451	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1452	&& pFeatures->uFamily >= 6 /* K7 and up */;
1453	}
1454	else
1455	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1456	return VINF_SUCCESS;
1457	}
1458

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 51574

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