VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId-armv8.cpp@ 101521

Last change on this file since 101521 was 101267, checked in by vboxsync, 14 months ago

VMM/CPUMR3CpuId-armv8: Dump the auxiliary feature registers 0 and 1 for fun and profit, bugref:10525
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 97.2 KB
Line 
1/* $Id: CPUMR3CpuId-armv8.cpp 101267 2023-09-26 12:20:33Z vboxsync $ */
2/** @file
3 * CPUM - CPU ID part for ARMv8 hypervisor.
4 */
5
6/*
7 * Copyright (C) 2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_CPUM
33#define CPUM_WITH_NONCONST_HOST_FEATURES /* required for initializing parts of the g_CpumHostFeatures structure here. */
34#include <VBox/vmm/cpum.h>
35#include <VBox/vmm/dbgf.h>
36#include <VBox/vmm/nem.h>
37#include <VBox/vmm/ssm.h>
38#include "CPUMInternal-armv8.h"
39#include <VBox/vmm/vmcc.h>
40
41#include <VBox/err.h>
42#include <iprt/ctype.h>
43#include <iprt/mem.h>
44#include <iprt/string.h>
45
46
47/*********************************************************************************************************************************
48* Defined Constants And Macros *
49*********************************************************************************************************************************/
50
51/*
52 *
53 * Init related code.
54 * Init related code.
55 * Init related code.
56 *
57 *
58 */
59
60/** @name Instruction Set Extension Options
61 * @{ */
62/** Configuration option type (extended boolean, really). */
63typedef uint8_t CPUMISAEXTCFG;
64/** Always disable the extension. */
65#define CPUMISAEXTCFG_DISABLED false
66/** Enable the extension if it's supported by the host CPU. */
67#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
68/** Enable the extension if it's supported by the host CPU, but don't let
69 * the portable CPUID feature disable it. */
70#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
71/** Always enable the extension. */
72#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
73/** @} */
74
75/**
76 * CPUID Configuration (from CFGM).
77 *
78 * @remarks The members aren't document since we would only be duplicating the
79 * \@cfgm entries in cpumR3CpuIdReadConfig.
80 */
81typedef struct CPUMCPUIDCONFIG
82{
83 CPUMISAEXTCFG enmAes;
84 CPUMISAEXTCFG enmPmull;
85 CPUMISAEXTCFG enmSha1;
86 CPUMISAEXTCFG enmSha256;
87 CPUMISAEXTCFG enmSha512;
88 CPUMISAEXTCFG enmCrc32;
89 CPUMISAEXTCFG enmSha3;
90
91 char szCpuName[128];
92} CPUMCPUIDCONFIG;
93/** Pointer to CPUID config (from CFGM). */
94typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
95
96
97/**
98 * Explode the CPU features from the given ID registers.
99 *
100 * @returns VBox status code.
101 * @param pIdRegs The ID registers to explode the features from.
102 * @param pFeatures Where to store the features to.
103 */
104static int cpumCpuIdExplodeFeatures(PCCPUMIDREGS pIdRegs, PCPUMFEATURES pFeatures)
105{
106 uint64_t u64IdReg = pIdRegs->u64RegIdAa64Mmfr0El1;
107
108 static uint8_t s_aPaRange[] = { 32, 36, 40, 42, 44, 48, 52 };
109 AssertLogRelMsgReturn(RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_PARANGE) < RT_ELEMENTS(s_aPaRange),
110 ("CPUM: Invalid/Unsupported PARange value in ID_AA64MMFR0_EL1 register: %u\n",
111 RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_PARANGE)),
112 VERR_CPUM_IPE_1);
113
114 pFeatures->cMaxPhysAddrWidth = s_aPaRange[RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_PARANGE)];
115 pFeatures->fTGran4K = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_TGRAN4) != ARMV8_ID_AA64MMFR0_EL1_TGRAN4_NOT_IMPL;
116 pFeatures->fTGran16K = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_TGRAN16) != ARMV8_ID_AA64MMFR0_EL1_TGRAN16_NOT_IMPL;
117 pFeatures->fTGran64K = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_TGRAN64) != ARMV8_ID_AA64MMFR0_EL1_TGRAN64_NOT_IMPL;
118
119 /* ID_AA64ISAR0_EL1 features. */
120 u64IdReg = pIdRegs->u64RegIdAa64Isar0El1;
121 pFeatures->fAes = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_AES) >= ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED;
122 pFeatures->fPmull = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_AES) >= ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED_PMULL;
123 pFeatures->fSha1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SHA1) >= ARMV8_ID_AA64ISAR0_EL1_SHA1_SUPPORTED;
124 pFeatures->fSha256 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SHA2) >= ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256;
125 pFeatures->fSha512 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SHA2) >= ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256_SHA512;
126 pFeatures->fCrc32 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_CRC32) >= ARMV8_ID_AA64ISAR0_EL1_CRC32_SUPPORTED;
127 pFeatures->fLse = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_ATOMIC) >= ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SUPPORTED;
128 pFeatures->fTme = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_TME) >= ARMV8_ID_AA64ISAR0_EL1_TME_SUPPORTED;
129 pFeatures->fRdm = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_RDM) >= ARMV8_ID_AA64ISAR0_EL1_RDM_SUPPORTED;
130 pFeatures->fSha3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SHA3) >= ARMV8_ID_AA64ISAR0_EL1_SHA3_SUPPORTED;
131 pFeatures->fSm3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SM3) >= ARMV8_ID_AA64ISAR0_EL1_SM3_SUPPORTED;
132 pFeatures->fSm4 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SM4) >= ARMV8_ID_AA64ISAR0_EL1_SM4_SUPPORTED;
133 pFeatures->fDotProd = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_DP) >= ARMV8_ID_AA64ISAR0_EL1_DP_SUPPORTED;
134 pFeatures->fFhm = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_FHM) >= ARMV8_ID_AA64ISAR0_EL1_FHM_SUPPORTED;
135 pFeatures->fFlagM = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_TS) >= ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED;
136 pFeatures->fFlagM2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_TS) >= ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED_2;
137 pFeatures->fTlbios = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_TLB) >= ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED;
138 pFeatures->fTlbirange = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_TLB) >= ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED_RANGE;
139 pFeatures->fRng = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_RNDR) >= ARMV8_ID_AA64ISAR0_EL1_RNDR_SUPPORTED;
140
141 /* ID_AA64ISAR1_EL1 features. */
142 u64IdReg = pIdRegs->u64RegIdAa64Isar1El1;
143 pFeatures->fDpb = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_DPB) >= ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED;
144 pFeatures->fDpb2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_DPB) >= ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED_2;
145
146 /* PAuth using QARMA5. */
147 pFeatures->fPacQarma5 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) != ARMV8_ID_AA64ISAR1_EL1_APA_NOT_IMPL;
148 if (pFeatures->fPacQarma5)
149 {
150 pFeatures->fPAuth = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) >= ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH;
151 pFeatures->fEpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) >= ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_EPAC;
152 pFeatures->fPAuth2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) >= ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH2;
153 pFeatures->fFpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) >= ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPAC;
154 pFeatures->fFpacCombine = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) >= ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPACCOMBINE;
155 }
156
157 /* PAuth using implementation defined algorithm. */
158 pFeatures->fPacImp = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) != ARMV8_ID_AA64ISAR1_EL1_API_NOT_IMPL;
159 if (pFeatures->fPacQarma5)
160 {
161 pFeatures->fPAuth = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) >= ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH;
162 pFeatures->fEpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) >= ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_EPAC;
163 pFeatures->fPAuth2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) >= ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH2;
164 pFeatures->fFpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) >= ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPAC;
165 pFeatures->fFpacCombine = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) >= ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPACCOMBINE;
166 }
167
168 pFeatures->fJscvt = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_FJCVTZS) >= ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SUPPORTED;
169 pFeatures->fFcma = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_FCMA) >= ARMV8_ID_AA64ISAR1_EL1_FCMA_SUPPORTED;
170 pFeatures->fLrcpc = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_LRCPC) >= ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED;
171 pFeatures->fLrcpc2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_LRCPC) >= ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED_2;
172 pFeatures->fFrintts = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_FRINTTS) >= ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED;
173 pFeatures->fSb = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_SB) >= ARMV8_ID_AA64ISAR1_EL1_SB_SUPPORTED;
174 pFeatures->fSpecres = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_SPECRES) >= ARMV8_ID_AA64ISAR1_EL1_SPECRES_SUPPORTED;
175 pFeatures->fBf16 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_BF16) >= ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_BF16;
176 pFeatures->fEbf16 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_BF16) >= ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_EBF16;
177 pFeatures->fDgh = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_DGH) >= ARMV8_ID_AA64ISAR1_EL1_DGH_SUPPORTED;
178 pFeatures->fI8mm = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_I8MM) >= ARMV8_ID_AA64ISAR1_EL1_I8MM_SUPPORTED;
179 pFeatures->fXs = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_XS) >= ARMV8_ID_AA64ISAR1_EL1_XS_SUPPORTED;
180 pFeatures->fLs64 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_LS64) >= ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED;
181 pFeatures->fLs64V = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_LS64) >= ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_V;
182 pFeatures->fLs64Accdata = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_LS64) >= ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_ACCDATA;
183
184 /* ID_AA64ISAR2_EL1 features. */
185 u64IdReg = pIdRegs->u64RegIdAa64Isar2El1;
186 pFeatures->fWfxt = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_WFXT) >= ARMV8_ID_AA64ISAR2_EL1_WFXT_SUPPORTED;
187 pFeatures->fRpres = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_RPRES) >= ARMV8_ID_AA64ISAR2_EL1_RPRES_SUPPORTED;
188
189 /* PAuth using QARMA3. */
190 pFeatures->fPacQarma3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_GPA3) >= ARMV8_ID_AA64ISAR2_EL1_GPA3_SUPPORTED;
191 pFeatures->fPacQarma3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) != ARMV8_ID_AA64ISAR2_EL1_APA3_NOT_IMPL;
192 if (pFeatures->fPacQarma5)
193 {
194 pFeatures->fPAuth = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) >= ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH;
195 pFeatures->fEpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) >= ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_EPAC;
196 pFeatures->fPAuth2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) >= ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH2;
197 pFeatures->fFpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) >= ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPAC;
198 pFeatures->fFpacCombine = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) >= ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPACCOMBINE;
199 }
200
201 pFeatures->fMops = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_MOPS) >= ARMV8_ID_AA64ISAR2_EL1_MOPS_SUPPORTED;
202 pFeatures->fHbc = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_BC) >= ARMV8_ID_AA64ISAR2_EL1_BC_SUPPORTED;
203 pFeatures->fConstPacField = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_PACFRAC) >= ARMV8_ID_AA64ISAR2_EL1_PACFRAC_TRUE;
204
205 /* ID_AA64PFR0_EL1 */
206 u64IdReg = pIdRegs->u64RegIdAa64Pfr0El1;
207 /* The FP and AdvSIMD field must have the same value. */
208 Assert(RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_FP) == RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_ADVSIMD));
209 pFeatures->fFp = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_FP) != ARMV8_ID_AA64PFR0_EL1_FP_NOT_IMPL;
210 pFeatures->fFp16 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_FP) == ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP_HP;
211 pFeatures->fAdvSimd = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_ADVSIMD) != ARMV8_ID_AA64PFR0_EL1_ADVSIMD_NOT_IMPL;
212 pFeatures->fFp16 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_ADVSIMD) == ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP_HP;
213 pFeatures->fRas = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_RAS) >= ARMV8_ID_AA64PFR0_EL1_RAS_SUPPORTED;
214 pFeatures->fRasV1p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_RAS) >= ARMV8_ID_AA64PFR0_EL1_RAS_V1P1;
215 pFeatures->fSve = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_SVE) >= ARMV8_ID_AA64PFR0_EL1_SVE_SUPPORTED;
216 pFeatures->fSecEl2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_SEL2) >= ARMV8_ID_AA64PFR0_EL1_SEL2_SUPPORTED;
217 pFeatures->fAmuV1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_AMU) >= ARMV8_ID_AA64PFR0_EL1_AMU_V1;
218 pFeatures->fAmuV1p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_AMU) >= ARMV8_ID_AA64PFR0_EL1_AMU_V1P1;
219 pFeatures->fDit = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_DIT) >= ARMV8_ID_AA64PFR0_EL1_DIT_SUPPORTED;
220 pFeatures->fRme = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_RME) >= ARMV8_ID_AA64PFR0_EL1_RME_SUPPORTED;
221 pFeatures->fCsv2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_CSV2) >= ARMV8_ID_AA64PFR0_EL1_CSV2_SUPPORTED;
222 pFeatures->fCsv2v3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_CSV2) >= ARMV8_ID_AA64PFR0_EL1_CSV2_3_SUPPORTED;
223
224 /* ID_AA64PFR1_EL1 */
225 u64IdReg = pIdRegs->u64RegIdAa64Pfr1El1;
226 pFeatures->fBti = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_BT) >= ARMV8_ID_AA64PFR1_EL1_BT_SUPPORTED;
227 pFeatures->fSsbs = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_SSBS) >= ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED;
228 pFeatures->fSsbs2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_SSBS) >= ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED_MSR_MRS;
229 pFeatures->fMte = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_MTE) >= ARMV8_ID_AA64PFR1_EL1_MTE_INSN_ONLY;
230 pFeatures->fMte2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_MTE) >= ARMV8_ID_AA64PFR1_EL1_MTE_FULL;
231 pFeatures->fMte3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_MTE) >= ARMV8_ID_AA64PFR1_EL1_MTE_FULL_ASYM_TAG_FAULT_CHK;
232 /** @todo RAS_frac, MPAM_frac, CSV2_frac. */
233 pFeatures->fSme = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_SME) >= ARMV8_ID_AA64PFR1_EL1_SME_SUPPORTED;
234 pFeatures->fSme2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_SME) >= ARMV8_ID_AA64PFR1_EL1_SME_SME2;
235 pFeatures->fRngTrap = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_RNDRTRAP) >= ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SUPPORTED;
236 pFeatures->fNmi = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_NMI) >= ARMV8_ID_AA64PFR1_EL1_NMI_SUPPORTED;
237
238 /* ID_AA64MMFR0_EL1 */
239 u64IdReg = pIdRegs->u64RegIdAa64Mmfr0El1;
240 pFeatures->fExs = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_EXS) >= ARMV8_ID_AA64MMFR0_EL1_EXS_SUPPORTED;
241 pFeatures->fFgt = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_FGT) >= ARMV8_ID_AA64MMFR0_EL1_FGT_SUPPORTED;
242 pFeatures->fEcv = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_ECV) >= ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED;
243
244 /* ID_AA64MMFR1_EL1 */
245 u64IdReg = pIdRegs->u64RegIdAa64Mmfr1El1;
246 pFeatures->fHafdbs = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_HAFDBS) >= ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SUPPORTED;
247 pFeatures->fVmid16 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_VMIDBITS) >= ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_16;
248 pFeatures->fVhe = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_VHE) >= ARMV8_ID_AA64MMFR1_EL1_VHE_SUPPORTED;
249 pFeatures->fHpds = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_HPDS) >= ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED;
250 pFeatures->fHpds2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_HPDS) >= ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED_2;
251 pFeatures->fLor = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_LO) >= ARMV8_ID_AA64MMFR1_EL1_LO_SUPPORTED;
252 pFeatures->fPan = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_PAN) >= ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED;
253 pFeatures->fPan2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_PAN) >= ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_2;
254 pFeatures->fPan3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_PAN) >= ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_3;
255 pFeatures->fXnx = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_XNX) >= ARMV8_ID_AA64MMFR1_EL1_XNX_SUPPORTED;
256 pFeatures->fTwed = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_TWED) >= ARMV8_ID_AA64MMFR1_EL1_TWED_SUPPORTED;
257 pFeatures->fEts2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_ETS) >= ARMV8_ID_AA64MMFR1_EL1_ETS_SUPPORTED;
258 pFeatures->fHcx = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_HCX) >= ARMV8_ID_AA64MMFR1_EL1_HCX_SUPPORTED;
259 pFeatures->fAfp = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_AFP) >= ARMV8_ID_AA64MMFR1_EL1_AFP_SUPPORTED;
260 pFeatures->fNTlbpa = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_NTLBPA) >= ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_COHERENT_ONLY;
261 pFeatures->fTidcp1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_TIDCP1) >= ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SUPPORTED;
262 pFeatures->fCmow = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_CMOW) >= ARMV8_ID_AA64MMFR1_EL1_CMOW_SUPPORTED;
263
264 /* ID_AA64MMFR2_EL1 */
265 u64IdReg = pIdRegs->u64RegIdAa64Mmfr2El1;
266 pFeatures->fTtcnp = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_CNP) >= ARMV8_ID_AA64MMFR2_EL1_CNP_SUPPORTED;
267 pFeatures->fUao = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_UAO) >= ARMV8_ID_AA64MMFR2_EL1_UAO_SUPPORTED;
268 pFeatures->fLsmaoc = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_LSM) >= ARMV8_ID_AA64MMFR2_EL1_LSM_SUPPORTED;
269 pFeatures->fIesb = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_IESB) >= ARMV8_ID_AA64MMFR2_EL1_IESB_SUPPORTED;
270 pFeatures->fLva = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_VARANGE) >= ARMV8_ID_AA64MMFR2_EL1_VARANGE_52BITS_64KB_GRAN;
271 pFeatures->fCcidx = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_CCIDX) >= ARMV8_ID_AA64MMFR2_EL1_CCIDX_64BIT;
272 pFeatures->fNv = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_NV) >= ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED;
273 pFeatures->fNv2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_NV) >= ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED_2;
274 pFeatures->fTtst = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_ST) >= ARMV8_ID_AA64MMFR2_EL1_ST_SUPPORTED;
275 pFeatures->fLse2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_AT) >= ARMV8_ID_AA64MMFR2_EL1_AT_SUPPORTED;
276 pFeatures->fIdst = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_IDS) >= ARMV8_ID_AA64MMFR2_EL1_IDS_EC_18H;
277 pFeatures->fS2Fwb = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_FWB) >= ARMV8_ID_AA64MMFR2_EL1_FWB_SUPPORTED;
278 pFeatures->fTtl = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_TTL) >= ARMV8_ID_AA64MMFR2_EL1_TTL_SUPPORTED;
279 pFeatures->fEvt = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_EVT) >= ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED;
280 pFeatures->fE0Pd = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_E0PD) >= ARMV8_ID_AA64MMFR2_EL1_E0PD_SUPPORTED;
281
282 /* ID_AA64DFR0_EL1 */
283 u64IdReg = pIdRegs->u64RegIdAa64Dfr0El1;
284 pFeatures->fDebugV8p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_DEBUGVER) >= ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8_VHE;
285 pFeatures->fDebugV8p2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_DEBUGVER) >= ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p2;
286 pFeatures->fDebugV8p4 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_DEBUGVER) >= ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p4;
287 pFeatures->fDebugV8p8 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_DEBUGVER) >= ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p8;
288 pFeatures->fPmuV3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3;
289 pFeatures->fPmuV3p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P1;
290 pFeatures->fPmuV3p4 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P4;
291 pFeatures->fPmuV3p5 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P5;
292 pFeatures->fPmuV3p7 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P7;
293 pFeatures->fPmuV3p8 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P8;
294 pFeatures->fSpe = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMSVER) >= ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED;
295 pFeatures->fSpeV1p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMSVER) >= ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P1;
296 pFeatures->fSpeV1p2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMSVER) >= ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P2;
297 pFeatures->fSpeV1p3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMSVER) >= ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P3;
298 pFeatures->fDoubleLock = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK) == ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SUPPORTED;
299 pFeatures->fTrf = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_TRACEFILT) >= ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SUPPORTED;
300 pFeatures->fTrbe = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER) >= ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SUPPORTED;
301 pFeatures->fMtPmu = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_MTPMU) == ARMV8_ID_AA64DFR0_EL1_MTPMU_SUPPORTED;
302 pFeatures->fBrbe = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_BRBE) >= ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED;
303 pFeatures->fBrbeV1p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_BRBE) >= ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED_V1P1;
304 pFeatures->fHpmn0 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_HPMN0) >= ARMV8_ID_AA64DFR0_EL1_HPMN0_SUPPORTED;
305
306 return VINF_SUCCESS;
307}
308
309
310/**
311 * Sanitizes and adjust the CPUID leaves.
312 *
313 * Drop features that aren't virtualized (or virtualizable). Adjust information
314 * and capabilities to fit the virtualized hardware. Remove information the
315 * guest shouldn't have (because it's wrong in the virtual world or because it
316 * gives away host details) or that we don't have documentation for and no idea
317 * what means.
318 *
319 * @returns VBox status code.
320 * @param pVM The cross context VM structure (for cCpus).
321 * @param pCpum The CPUM instance data.
322 * @param pConfig The CPUID configuration we've read from CFGM.
323 */
324static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
325{
326#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
327 if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
328 { \
329 LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
330 (a_pLeafReg) &= ~(uint32_t)(fMask); \
331 }
332#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
333 if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
334 { \
335 LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
336 (a_pLeafReg) &= ~(uint32_t)(fBitMask); \
337 }
338#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_IdReg, a_FeatNm, a_IdRegValCheck, enmConfig, a_IdRegValNotSup) \
339 if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
340 && (RT_BF_GET(a_IdReg, a_FeatNm) >= a_IdRegValCheck) \
341 && (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
342 { \
343 LogRel(("PortableCpuId: [" #a_FeatNm "]: 1 -> 0\n")); \
344 (a_IdReg) = RT_BF_SET(a_IdReg, a_FeatNm, a_IdRegValNotSup); \
345 }
346 //Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
347
348 /* The CPUID entries we start with here isn't necessarily the ones of the host, so we
349 must consult HostFeatures when processing CPUMISAEXTCFG variables. */
350 PCCPUMFEATURES pHstFeat = &pCpum->HostFeatures;
351#define PASSTHRU_FEATURE(a_IdReg, enmConfig, fHostFeature, a_IdRegNm, a_IdRegValSup, a_IdRegValNotSup) \
352 (a_IdReg) = ((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS || (fHostFeature)) \
353 ? RT_BF_SET(a_IdReg, a_IdRegNm, a_IdRegValSup) \
354 : RT_BF_SET(a_IdReg, a_IdRegNm, a_IdRegValNotSup))
355
356 /* ID_AA64ISAR0_EL1 */
357 uint64_t u64ValTmp = 0;
358 uint64_t u64IdReg = pVM->cpum.s.GuestIdRegs.u64RegIdAa64Isar0El1;
359
360 PASSTHRU_FEATURE(u64IdReg, pConfig->enmAes, pHstFeat->fAes, ARMV8_ID_AA64ISAR0_EL1_AES, ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED, ARMV8_ID_AA64ISAR0_EL1_AES_NOT_IMPL);
361 u64ValTmp = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_AES) == ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED ? ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED : ARMV8_ID_AA64ISAR0_EL1_AES_NOT_IMPL;
362 PASSTHRU_FEATURE(u64IdReg, pConfig->enmPmull, pHstFeat->fPmull, ARMV8_ID_AA64ISAR0_EL1_AES, ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED_PMULL, u64ValTmp);
363 PASSTHRU_FEATURE(u64IdReg, pConfig->enmSha1, pHstFeat->fSha1, ARMV8_ID_AA64ISAR0_EL1_SHA1, ARMV8_ID_AA64ISAR0_EL1_SHA1_SUPPORTED, ARMV8_ID_AA64ISAR0_EL1_SHA1_NOT_IMPL);
364 PASSTHRU_FEATURE(u64IdReg, pConfig->enmSha256, pHstFeat->fSha256, ARMV8_ID_AA64ISAR0_EL1_SHA2, ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256, ARMV8_ID_AA64ISAR0_EL1_SHA2_NOT_IMPL);
365 u64ValTmp = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SHA2) == ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256 ? ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256 : ARMV8_ID_AA64ISAR0_EL1_SHA2_NOT_IMPL;
366 PASSTHRU_FEATURE(u64IdReg, pConfig->enmSha512, pHstFeat->fSha512, ARMV8_ID_AA64ISAR0_EL1_SHA2, ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256_SHA512, u64ValTmp);
367 PASSTHRU_FEATURE(u64IdReg, pConfig->enmCrc32, pHstFeat->fCrc32, ARMV8_ID_AA64ISAR0_EL1_CRC32, ARMV8_ID_AA64ISAR0_EL1_CRC32_SUPPORTED, ARMV8_ID_AA64ISAR0_EL1_CRC32_NOT_IMPL);
368 PASSTHRU_FEATURE(u64IdReg, pConfig->enmSha3, pHstFeat->fSha3, ARMV8_ID_AA64ISAR0_EL1_SHA3, ARMV8_ID_AA64ISAR0_EL1_SHA3_SUPPORTED, ARMV8_ID_AA64ISAR0_EL1_SHA3_NOT_IMPL);
369
370 if (pCpum->u8PortableCpuIdLevel > 0)
371 {
372 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, u64IdReg, ARMV8_ID_AA64ISAR0_EL1_AES, ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED, pConfig->enmAes, ARMV8_ID_AA64ISAR0_EL1_AES_NOT_IMPL);
373 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, u64IdReg, ARMV8_ID_AA64ISAR0_EL1_AES, ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED_PMULL, pConfig->enmPmull, ARMV8_ID_AA64ISAR0_EL1_AES_NOT_IMPL);
374 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SHA1, ARMV8_ID_AA64ISAR0_EL1_SHA1_SUPPORTED, pConfig->enmSha1, ARMV8_ID_AA64ISAR0_EL1_SHA1_NOT_IMPL);
375 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SHA2, ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256, pConfig->enmSha256, ARMV8_ID_AA64ISAR0_EL1_SHA2_NOT_IMPL);
376 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SHA2, ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256_SHA512, pConfig->enmSha512, ARMV8_ID_AA64ISAR0_EL1_SHA2_NOT_IMPL);
377 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, u64IdReg, ARMV8_ID_AA64ISAR0_EL1_CRC32, ARMV8_ID_AA64ISAR0_EL1_CRC32_SUPPORTED, pConfig->enmCrc32, ARMV8_ID_AA64ISAR0_EL1_CRC32_NOT_IMPL);
378 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SHA3, ARMV8_ID_AA64ISAR0_EL1_SHA3_SUPPORTED, pConfig->enmSha3, ARMV8_ID_AA64ISAR0_EL1_SHA3_NOT_IMPL);
379 }
380
381 /* Write ID_AA64ISAR0_EL1 register back. */
382 pVM->cpum.s.GuestIdRegs.u64RegIdAa64Isar0El1 = u64IdReg;
383
384 /** @todo Other ID and feature registers. */
385
386 return VINF_SUCCESS;
387#undef PORTABLE_DISABLE_FEATURE_BIT
388#undef PORTABLE_CLEAR_BITS_WHEN
389}
390
391
392/**
393 * Reads a value in /CPUM/IsaExts/ node.
394 *
395 * @returns VBox status code (error message raised).
396 * @param pVM The cross context VM structure. (For errors.)
397 * @param pIsaExts The /CPUM/IsaExts node (can be NULL).
398 * @param pszValueName The value / extension name.
399 * @param penmValue Where to return the choice.
400 * @param enmDefault The default choice.
401 */
402static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
403 CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
404{
405 /*
406 * Try integer encoding first.
407 */
408 uint64_t uValue;
409 int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
410 if (RT_SUCCESS(rc))
411 switch (uValue)
412 {
413 case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
414 case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
415 case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
416 case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
417 default:
418 return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
419 "Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
420 pszValueName, uValue);
421 }
422 /*
423 * If missing, use default.
424 */
425 else if (rc == VERR_CFGM_VALUE_NOT_FOUND || rc == VERR_CFGM_NO_PARENT)
426 *penmValue = enmDefault;
427 else
428 {
429 if (rc == VERR_CFGM_NOT_INTEGER)
430 {
431 /*
432 * Not an integer, try read it as a string.
433 */
434 char szValue[32];
435 rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
436 if (RT_SUCCESS(rc))
437 {
438 RTStrToLower(szValue);
439 size_t cchValue = strlen(szValue);
440#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
441 if ( EQ("disabled") || EQ("disable") || EQ("off") || EQ("no"))
442 *penmValue = CPUMISAEXTCFG_DISABLED;
443 else if (EQ("enabled") || EQ("enable") || EQ("on") || EQ("yes"))
444 *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
445 else if (EQ("forced") || EQ("force") || EQ("always"))
446 *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
447 else if (EQ("portable"))
448 *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
449 else if (EQ("default") || EQ("def"))
450 *penmValue = enmDefault;
451 else
452 return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
453 "Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
454 pszValueName, uValue);
455#undef EQ
456 }
457 }
458 if (RT_FAILURE(rc))
459 return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
460 }
461 return VINF_SUCCESS;
462}
463
464
465#if 0
466/**
467 * Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
468 *
469 * @returns VBox status code (error message raised).
470 * @param pVM The cross context VM structure. (For errors.)
471 * @param pIsaExts The /CPUM/IsaExts node (can be NULL).
472 * @param pszValueName The value / extension name.
473 * @param penmValue Where to return the choice.
474 * @param enmDefault The default choice.
475 * @param fAllowed Allowed choice. Applied both to the result and to
476 * the default value.
477 */
478static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
479 CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
480{
481 int rc;
482 if (fAllowed)
483 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
484 else
485 {
486 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /*enmDefault*/);
487 if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
488 LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
489 *penmValue = CPUMISAEXTCFG_DISABLED;
490 }
491 return rc;
492}
493#endif
494
495static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg)
496{
497 /** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
498 * When non-zero CPUID features that could cause portability issues will be
499 * stripped. The higher the value the more features gets stripped. Higher
500 * values should only be used when older CPUs are involved since it may
501 * harm performance and maybe also cause problems with specific guests. */
502 int rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
503 AssertLogRelRCReturn(rc, rc);
504
505 /** @cfgm{/CPUM/GuestCpuName, string}
506 * The name of the CPU we're to emulate. The default is the host CPU.
507 * Note! CPUs other than "host" one is currently unsupported. */
508 rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
509 AssertLogRelRCReturn(rc, rc);
510
511 /*
512 * Instruction Set Architecture (ISA) Extensions.
513 */
514 PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
515 if (pIsaExts)
516 {
517 rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
518 "AES"
519 "|PMULL"
520 "|SHA1"
521 "|SHA256"
522 "|SHA512"
523 "|CRC32"
524 "|SHA3"
525 , "" /*pszValidNodes*/, "CPUM" /*pszWho*/, 0 /*uInstance*/);
526 if (RT_FAILURE(rc))
527 return rc;
528 }
529
530 /** @cfgm{/CPUM/IsaExts/AES, boolean, depends}
531 * Expose FEAT_AES instruction set extension to the guest.
532 */
533 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AES", &pConfig->enmAes, true /*enmDefault*/);
534 AssertLogRelRCReturn(rc, rc);
535
536 /** @cfgm{/CPUM/IsaExts/AES, boolean, depends}
537 * Expose FEAT_AES and FEAT_PMULL instruction set extension to the guest.
538 */
539 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PMULL", &pConfig->enmPmull, true /*enmDefault*/);
540 AssertLogRelRCReturn(rc, rc);
541
542 /** @cfgm{/CPUM/IsaExts/SHA1, boolean, depends}
543 * Expose FEAT_SHA1 instruction set extension to the guest.
544 */
545 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SHA1", &pConfig->enmSha1, true /*enmDefault*/);
546 AssertLogRelRCReturn(rc, rc);
547
548 /** @cfgm{/CPUM/IsaExts/SHA256, boolean, depends}
549 * Expose FEAT_SHA256 instruction set extension to the guest.
550 */
551 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SHA256", &pConfig->enmSha256, true /*enmDefault*/);
552 AssertLogRelRCReturn(rc, rc);
553
554 /** @cfgm{/CPUM/IsaExts/SHA512, boolean, depends}
555 * Expose FEAT_SHA256 and FEAT_SHA512 instruction set extension to the guest.
556 */
557 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SHA512", &pConfig->enmSha512, true /*enmDefault*/);
558 AssertLogRelRCReturn(rc, rc);
559
560 /** @cfgm{/CPUM/IsaExts/CRC32, boolean, depends}
561 * Expose FEAT_CRC32 instruction set extension to the guest.
562 */
563 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CRC32", &pConfig->enmCrc32, true /*enmDefault*/);
564 AssertLogRelRCReturn(rc, rc);
565
566 /** @cfgm{/CPUM/IsaExts/SHA3, boolean, depends}
567 * Expose FEAT_SHA3 instruction set extension to the guest.
568 */
569 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SHA3", &pConfig->enmSha3, true /*enmDefault*/);
570 AssertLogRelRCReturn(rc, rc);
571
572 /** @todo Add more options for other extensions. */
573
574 return VINF_SUCCESS;
575}
576
577
578/**
579 * Populates the host and guest features by the given ID registers.
580 *
581 * @returns VBox status code.
582 * @param pVM The cross context VM structure.
583 * @param pIdRegs Pointer to the ID register struct.
584 *
585 * @note Unlike on x86 there is no cross platform usermode accessible way to get at the CPU features.
586 * On ARM there are some ID_AA64*_EL1 system registers accessible by EL1 and higher only so we have to
587 * rely on the host/NEM backend to query those and hand them to CPUM where they will be parsed and modified based
588 * on the VM config.
589 */
590VMMR3DECL(int) CPUMR3PopulateFeaturesByIdRegisters(PVM pVM, PCCPUMIDREGS pIdRegs)
591{
592 /* Set the host features from the given ID registers. */
593 int rc = cpumCpuIdExplodeFeatures(pIdRegs, &g_CpumHostFeatures.s);
594 AssertRCReturn(rc, rc);
595
596 pVM->cpum.s.HostFeatures = g_CpumHostFeatures.s;
597 pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
598 pVM->cpum.s.HostIdRegs = *pIdRegs;
599 pVM->cpum.s.GuestIdRegs = *pIdRegs;
600
601 PCPUM pCpum = &pVM->cpum.s;
602 PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
603
604 /*
605 * Read the configuration.
606 */
607 CPUMCPUIDCONFIG Config;
608 RT_ZERO(Config);
609
610 rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg);
611 AssertRCReturn(rc, rc);
612
613#if 0
614 /*
615 * Get the guest CPU data from the database and/or the host.
616 *
617 * The CPUID and MSRs are currently living on the regular heap to avoid
618 * fragmenting the hyper heap (and because there isn't/wasn't any realloc
619 * API for the hyper heap). This means special cleanup considerations.
620 */
621 rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
622 if (RT_FAILURE(rc))
623 return rc == VERR_CPUM_DB_CPU_NOT_FOUND
624 ? VMSetError(pVM, rc, RT_SRC_POS,
625 "Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
626 : rc;
627#endif
628
629 /*
630 * Pre-explode the CPUID info.
631 */
632 if (RT_SUCCESS(rc))
633 rc = cpumCpuIdExplodeFeatures(pIdRegs, &pCpum->GuestFeatures);
634
635 /*
636 * Sanitize the cpuid information passed on to the guest.
637 */
638 if (RT_SUCCESS(rc))
639 rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
640
641 return rc;
642}
643
644
645/**
646 * Queries the pointer to the VM wide ID registers exposing configured features to the guest.
647 *
648 * @returns VBox status code.
649 * @param pVM The cross context VM structure.
650 * @param ppIdRegs Where to store the pointer to the guest ID register struct.
651 */
652VMMR3_INT_DECL(int) CPUMR3QueryGuestIdRegs(PVM pVM, PCCPUMIDREGS *ppIdRegs)
653{
654 AssertPtrReturn(ppIdRegs, VERR_INVALID_POINTER);
655
656 *ppIdRegs = &pVM->cpum.s.GuestIdRegs;
657 return VINF_SUCCESS;
658}
659
660
661/*
662 *
663 *
664 * Saved state related code.
665 * Saved state related code.
666 * Saved state related code.
667 *
668 *
669 */
670/** Saved state field descriptors for CPUMIDREGS. */
671static const SSMFIELD g_aCpumIdRegsFields[] =
672{
673 SSMFIELD_ENTRY(CPUMIDREGS, u64RegIdAa64Pfr0El1),
674 SSMFIELD_ENTRY(CPUMIDREGS, u64RegIdAa64Pfr1El1),
675 SSMFIELD_ENTRY(CPUMIDREGS, u64RegIdAa64Dfr0El1),
676 SSMFIELD_ENTRY(CPUMIDREGS, u64RegIdAa64Dfr1El1),
677 SSMFIELD_ENTRY(CPUMIDREGS, u64RegIdAa64Afr0El1),
678 SSMFIELD_ENTRY(CPUMIDREGS, u64RegIdAa64Afr1El1),
679 SSMFIELD_ENTRY(CPUMIDREGS, u64RegIdAa64Isar0El1),
680 SSMFIELD_ENTRY(CPUMIDREGS, u64RegIdAa64Isar1El1),
681 SSMFIELD_ENTRY(CPUMIDREGS, u64RegIdAa64Isar2El1),
682 SSMFIELD_ENTRY(CPUMIDREGS, u64RegIdAa64Mmfr0El1),
683 SSMFIELD_ENTRY(CPUMIDREGS, u64RegIdAa64Mmfr1El1),
684 SSMFIELD_ENTRY(CPUMIDREGS, u64RegIdAa64Mmfr2El1),
685 SSMFIELD_ENTRY(CPUMIDREGS, u64RegClidrEl1),
686 SSMFIELD_ENTRY(CPUMIDREGS, u64RegCtrEl0),
687 SSMFIELD_ENTRY(CPUMIDREGS, u64RegDczidEl0),
688 SSMFIELD_ENTRY_TERM()
689};
690
691
692/**
693 * Called both in pass 0 and the final pass.
694 *
695 * @param pVM The cross context VM structure.
696 * @param pSSM The saved state handle.
697 */
698void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
699{
700 /*
701 * Save all the CPU ID leaves.
702 */
703 SSMR3PutStructEx(pSSM, &pVM->cpum.s.GuestIdRegs, sizeof(pVM->cpum.s.GuestIdRegs), 0, g_aCpumIdRegsFields, NULL);
704}
705
706
707/**
708 * Loads the CPU ID leaves saved by pass 0, inner worker.
709 *
710 * @returns VBox status code.
711 * @param pVM The cross context VM structure.
712 * @param pSSM The saved state handle.
713 * @param uVersion The format version.
714 * @param pGuestIdRegs The guest ID register as loaded from the saved state.
715 */
716static int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMIDREGS pGuestIdRegs)
717{
718 /*
719 * This can be skipped.
720 */
721 bool fStrictCpuIdChecks;
722 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
723
724 /*
725 * Define a bunch of macros for simplifying the santizing/checking code below.
726 */
727 /* For checking guest features. */
728#define CPUID_GST_FEATURE_RET(a_IdReg, a_Field) \
729 do { \
730 if (RT_BF_GET(pGuestIdRegs->a_IdReg, a_Field) > RT_BF_GET(pVM->cpum.s.GuestIdRegs.a_IdReg, a_Field)) \
731 { \
732 if (fStrictCpuIdChecks) \
733 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
734 N_(#a_Field " is not supported by the host but has already exposed to the guest")); \
735 LogRel(("CPUM: " #a_Field " is not supported by the host but has already been exposed to the guest\n")); \
736 } \
737 } while (0)
738#define CPUID_GST_FEATURE_RET_NOT_IMPL(a_IdReg, a_Field, a_NotImpl) \
739 do { \
740 if ( ( RT_BF_GET(pGuestIdRegs->a_IdReg, a_Field) != (a_NotImpl) \
741 && RT_BF_GET(pVM->cpum.s.GuestIdRegs.a_IdReg, a_Field) == (a_NotImpl)) \
742 || RT_BF_GET(pGuestIdRegs->a_IdReg, a_Field) > RT_BF_GET(pVM->cpum.s.GuestIdRegs.a_IdReg, a_Field)) \
743 { \
744 if (fStrictCpuIdChecks) \
745 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
746 N_(#a_Field " is not supported by the host but has already exposed to the guest")); \
747 LogRel(("CPUM: " #a_Field " is not supported by the host but has already been exposed to the guest\n")); \
748 } \
749 } while (0)
750#define CPUID_GST_FEATURE_WRN(a_IdReg, a_Field) \
751 do { \
752 if (RT_BF_GET(pGuestIdRegs->a_IdReg, a_Field) > RT_BF_GET(pVM->cpum.s.GuestIdRegs.a_IdReg, a_Field)) \
753 LogRel(("CPUM: " #a_Field " is not supported by the host but has already been exposed to the guest\n")); \
754 } while (0)
755#define CPUID_GST_FEATURE_EMU(a_IdReg, a_Field) \
756 do { \
757 if (RT_BF_GET(pGuestIdRegs->a_IdReg, a_Field) > RT_BF_GET(pVM->cpum.s.GuestIdRegs.a_IdReg, a_Field)) \
758 LogRel(("CPUM: Warning - " #a_Field " is not supported by the host but has already been exposed to the guest. This may impact performance.\n")); \
759 } while (0)
760#define CPUID_GST_FEATURE_IGN(a_IdReg, a_Field) do { } while (0)
761
762 RT_NOREF(uVersion);
763 /*
764 * Verify that we can support the features already exposed to the guest on
765 * this host.
766 *
767 * Most of the features we're emulating requires intercepting instruction
768 * and doing it the slow way, so there is no need to warn when they aren't
769 * present in the host CPU. Thus we use IGN instead of EMU on these.
770 *
771 * Trailing comments:
772 * "EMU" - Possible to emulate, could be lots of work and very slow.
773 * "EMU?" - Can this be emulated?
774 */
775 /* ID_AA64ISAR0_EL1 */
776 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar0El1, ARMV8_ID_AA64ISAR0_EL1_AES);
777 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar0El1, ARMV8_ID_AA64ISAR0_EL1_SHA1);
778 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar0El1, ARMV8_ID_AA64ISAR0_EL1_SHA2);
779 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar0El1, ARMV8_ID_AA64ISAR0_EL1_CRC32);
780 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar0El1, ARMV8_ID_AA64ISAR0_EL1_ATOMIC);
781 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar0El1, ARMV8_ID_AA64ISAR0_EL1_TME);
782 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar0El1, ARMV8_ID_AA64ISAR0_EL1_RDM);
783 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar0El1, ARMV8_ID_AA64ISAR0_EL1_SHA3);
784 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar0El1, ARMV8_ID_AA64ISAR0_EL1_SM3);
785 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar0El1, ARMV8_ID_AA64ISAR0_EL1_SM4);
786 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar0El1, ARMV8_ID_AA64ISAR0_EL1_DP);
787 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar0El1, ARMV8_ID_AA64ISAR0_EL1_FHM);
788 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar0El1, ARMV8_ID_AA64ISAR0_EL1_TS);
789 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar0El1, ARMV8_ID_AA64ISAR0_EL1_TLB);
790 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar0El1, ARMV8_ID_AA64ISAR0_EL1_RNDR);
791
792 /* ID_AA64ISAR1_EL1 */
793 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar1El1, ARMV8_ID_AA64ISAR1_EL1_DPB);
794 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar1El1, ARMV8_ID_AA64ISAR1_EL1_APA);
795 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar1El1, ARMV8_ID_AA64ISAR1_EL1_API);
796 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar1El1, ARMV8_ID_AA64ISAR1_EL1_FJCVTZS);
797 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar1El1, ARMV8_ID_AA64ISAR1_EL1_LRCPC);
798 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar1El1, ARMV8_ID_AA64ISAR1_EL1_GPA);
799 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar1El1, ARMV8_ID_AA64ISAR1_EL1_GPI);
800 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar1El1, ARMV8_ID_AA64ISAR1_EL1_FRINTTS);
801 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar1El1, ARMV8_ID_AA64ISAR1_EL1_SB);
802 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar1El1, ARMV8_ID_AA64ISAR1_EL1_SPECRES);
803 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar1El1, ARMV8_ID_AA64ISAR1_EL1_BF16);
804 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar1El1, ARMV8_ID_AA64ISAR1_EL1_DGH);
805 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar1El1, ARMV8_ID_AA64ISAR1_EL1_I8MM);
806 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar1El1, ARMV8_ID_AA64ISAR1_EL1_XS);
807 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar1El1, ARMV8_ID_AA64ISAR1_EL1_LS64);
808
809 /* ID_AA64ISAR2_EL1 */
810 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar2El1, ARMV8_ID_AA64ISAR2_EL1_WFXT);
811 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar2El1, ARMV8_ID_AA64ISAR2_EL1_RPRES);
812 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar2El1, ARMV8_ID_AA64ISAR2_EL1_GPA3);
813 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar2El1, ARMV8_ID_AA64ISAR2_EL1_APA3);
814 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar2El1, ARMV8_ID_AA64ISAR2_EL1_MOPS);
815 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar2El1, ARMV8_ID_AA64ISAR2_EL1_BC);
816 CPUID_GST_FEATURE_RET(u64RegIdAa64Isar2El1, ARMV8_ID_AA64ISAR2_EL1_PACFRAC);
817
818 /* ID_AA64PFR0_EL1 */
819 CPUID_GST_FEATURE_RET(u64RegIdAa64Pfr0El1, ARMV8_ID_AA64PFR0_EL1_EL0);
820 CPUID_GST_FEATURE_RET(u64RegIdAa64Pfr0El1, ARMV8_ID_AA64PFR0_EL1_EL1);
821 CPUID_GST_FEATURE_RET(u64RegIdAa64Pfr0El1, ARMV8_ID_AA64PFR0_EL1_EL2);
822 CPUID_GST_FEATURE_RET(u64RegIdAa64Pfr0El1, ARMV8_ID_AA64PFR0_EL1_EL3);
823 CPUID_GST_FEATURE_RET_NOT_IMPL(u64RegIdAa64Pfr0El1, ARMV8_ID_AA64PFR0_EL1_FP, ARMV8_ID_AA64PFR0_EL1_FP_NOT_IMPL); /* Special not implemented value. */
824 CPUID_GST_FEATURE_RET_NOT_IMPL(u64RegIdAa64Pfr0El1, ARMV8_ID_AA64PFR0_EL1_ADVSIMD, ARMV8_ID_AA64PFR0_EL1_ADVSIMD_NOT_IMPL); /* Special not implemented value. */
825 CPUID_GST_FEATURE_IGN(u64RegIdAa64Pfr0El1, ARMV8_ID_AA64PFR0_EL1_GIC);
826 CPUID_GST_FEATURE_RET(u64RegIdAa64Pfr0El1, ARMV8_ID_AA64PFR0_EL1_RAS);
827 CPUID_GST_FEATURE_RET(u64RegIdAa64Pfr0El1, ARMV8_ID_AA64PFR0_EL1_SVE);
828 CPUID_GST_FEATURE_RET(u64RegIdAa64Pfr0El1, ARMV8_ID_AA64PFR0_EL1_SEL2);
829 /** @todo MPAM */
830 CPUID_GST_FEATURE_RET(u64RegIdAa64Pfr0El1, ARMV8_ID_AA64PFR0_EL1_AMU);
831 CPUID_GST_FEATURE_RET(u64RegIdAa64Pfr0El1, ARMV8_ID_AA64PFR0_EL1_DIT);
832 CPUID_GST_FEATURE_RET(u64RegIdAa64Pfr0El1, ARMV8_ID_AA64PFR0_EL1_RME);
833 CPUID_GST_FEATURE_RET(u64RegIdAa64Pfr0El1, ARMV8_ID_AA64PFR0_EL1_CSV2);
834 CPUID_GST_FEATURE_RET(u64RegIdAa64Pfr0El1, ARMV8_ID_AA64PFR0_EL1_CSV3);
835
836 /* ID_AA64PFR1_EL1 */
837 CPUID_GST_FEATURE_RET(u64RegIdAa64Pfr1El1, ARMV8_ID_AA64PFR1_EL1_BT);
838 CPUID_GST_FEATURE_RET(u64RegIdAa64Pfr1El1, ARMV8_ID_AA64PFR1_EL1_SSBS);
839 CPUID_GST_FEATURE_RET(u64RegIdAa64Pfr1El1, ARMV8_ID_AA64PFR1_EL1_MTE);
840 CPUID_GST_FEATURE_RET(u64RegIdAa64Pfr1El1, ARMV8_ID_AA64PFR1_EL1_RASFRAC);
841 /** @todo MPAM. */
842 CPUID_GST_FEATURE_RET(u64RegIdAa64Pfr1El1, ARMV8_ID_AA64PFR1_EL1_SME);
843 CPUID_GST_FEATURE_RET(u64RegIdAa64Pfr1El1, ARMV8_ID_AA64PFR1_EL1_RNDRTRAP);
844 CPUID_GST_FEATURE_RET(u64RegIdAa64Pfr1El1, ARMV8_ID_AA64PFR1_EL1_CSV2FRAC);
845 CPUID_GST_FEATURE_RET(u64RegIdAa64Pfr1El1, ARMV8_ID_AA64PFR1_EL1_NMI);
846
847 /* ID_AA64MMFR0_EL1 */
848 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr0El1, ARMV8_ID_AA64MMFR0_EL1_PARANGE);
849 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr0El1, ARMV8_ID_AA64MMFR0_EL1_ASIDBITS);
850 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr0El1, ARMV8_ID_AA64MMFR0_EL1_BIGEND);
851 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr0El1, ARMV8_ID_AA64MMFR0_EL1_SNSMEM);
852 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr0El1, ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0);
853 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr0El1, ARMV8_ID_AA64MMFR0_EL1_TGRAN16);
854 CPUID_GST_FEATURE_RET_NOT_IMPL(u64RegIdAa64Mmfr0El1, ARMV8_ID_AA64MMFR0_EL1_TGRAN64, ARMV8_ID_AA64MMFR0_EL1_TGRAN64_NOT_IMPL);
855 CPUID_GST_FEATURE_RET_NOT_IMPL(u64RegIdAa64Mmfr0El1, ARMV8_ID_AA64MMFR0_EL1_TGRAN4, ARMV8_ID_AA64MMFR0_EL1_TGRAN4_NOT_IMPL);
856 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr0El1, ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2);
857 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr0El1, ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2);
858 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr0El1, ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2);
859 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr0El1, ARMV8_ID_AA64MMFR0_EL1_EXS);
860 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr0El1, ARMV8_ID_AA64MMFR0_EL1_FGT);
861 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr0El1, ARMV8_ID_AA64MMFR0_EL1_ECV);
862
863 /* ID_AA64MMFR1_EL1 */
864 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr1El1, ARMV8_ID_AA64MMFR1_EL1_HAFDBS);
865 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr1El1, ARMV8_ID_AA64MMFR1_EL1_VMIDBITS);
866 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr1El1, ARMV8_ID_AA64MMFR1_EL1_VHE);
867 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr1El1, ARMV8_ID_AA64MMFR1_EL1_HPDS);
868 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr1El1, ARMV8_ID_AA64MMFR1_EL1_LO);
869 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr1El1, ARMV8_ID_AA64MMFR1_EL1_PAN);
870 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr1El1, ARMV8_ID_AA64MMFR1_EL1_SPECSEI);
871 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr1El1, ARMV8_ID_AA64MMFR1_EL1_XNX);
872 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr1El1, ARMV8_ID_AA64MMFR1_EL1_TWED);
873 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr1El1, ARMV8_ID_AA64MMFR1_EL1_ETS);
874 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr1El1, ARMV8_ID_AA64MMFR1_EL1_HCX);
875 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr1El1, ARMV8_ID_AA64MMFR1_EL1_AFP);
876 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr1El1, ARMV8_ID_AA64MMFR1_EL1_NTLBPA);
877 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr1El1, ARMV8_ID_AA64MMFR1_EL1_TIDCP1);
878 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr1El1, ARMV8_ID_AA64MMFR1_EL1_CMOW);
879
880 /* ID_AA64MMFR2_EL1 */
881 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr2El1, ARMV8_ID_AA64MMFR2_EL1_CNP);
882 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr2El1, ARMV8_ID_AA64MMFR2_EL1_UAO);
883 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr2El1, ARMV8_ID_AA64MMFR2_EL1_LSM);
884 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr2El1, ARMV8_ID_AA64MMFR2_EL1_IESB);
885 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr2El1, ARMV8_ID_AA64MMFR2_EL1_VARANGE);
886 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr2El1, ARMV8_ID_AA64MMFR2_EL1_CCIDX);
887 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr2El1, ARMV8_ID_AA64MMFR2_EL1_CNP);
888 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr2El1, ARMV8_ID_AA64MMFR2_EL1_NV);
889 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr2El1, ARMV8_ID_AA64MMFR2_EL1_ST);
890 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr2El1, ARMV8_ID_AA64MMFR2_EL1_AT);
891 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr2El1, ARMV8_ID_AA64MMFR2_EL1_IDS);
892 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr2El1, ARMV8_ID_AA64MMFR2_EL1_FWB);
893 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr2El1, ARMV8_ID_AA64MMFR2_EL1_TTL);
894 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr2El1, ARMV8_ID_AA64MMFR2_EL1_BBM);
895 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr2El1, ARMV8_ID_AA64MMFR2_EL1_EVT);
896 CPUID_GST_FEATURE_RET(u64RegIdAa64Mmfr2El1, ARMV8_ID_AA64MMFR2_EL1_E0PD);
897
898 /* ID_AA64DFR0_EL1 */
899 CPUID_GST_FEATURE_RET(u64RegIdAa64Dfr0El1, ARMV8_ID_AA64DFR0_EL1_DEBUGVER);
900 CPUID_GST_FEATURE_RET(u64RegIdAa64Dfr0El1, ARMV8_ID_AA64DFR0_EL1_TRACEVER);
901 CPUID_GST_FEATURE_RET(u64RegIdAa64Dfr0El1, ARMV8_ID_AA64DFR0_EL1_PMUVER);
902 CPUID_GST_FEATURE_RET(u64RegIdAa64Dfr0El1, ARMV8_ID_AA64DFR0_EL1_BRPS);
903 CPUID_GST_FEATURE_RET(u64RegIdAa64Dfr0El1, ARMV8_ID_AA64DFR0_EL1_WRPS);
904 CPUID_GST_FEATURE_RET(u64RegIdAa64Dfr0El1, ARMV8_ID_AA64DFR0_EL1_CTXCMPS);
905 CPUID_GST_FEATURE_RET(u64RegIdAa64Dfr0El1, ARMV8_ID_AA64DFR0_EL1_PMSVER);
906 CPUID_GST_FEATURE_RET(u64RegIdAa64Dfr0El1, ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK);
907 CPUID_GST_FEATURE_RET(u64RegIdAa64Dfr0El1, ARMV8_ID_AA64DFR0_EL1_TRACEFILT);
908 CPUID_GST_FEATURE_RET(u64RegIdAa64Dfr0El1, ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER);
909 CPUID_GST_FEATURE_RET(u64RegIdAa64Dfr0El1, ARMV8_ID_AA64DFR0_EL1_MTPMU);
910 CPUID_GST_FEATURE_RET(u64RegIdAa64Dfr0El1, ARMV8_ID_AA64DFR0_EL1_BRBE);
911 CPUID_GST_FEATURE_RET(u64RegIdAa64Dfr0El1, ARMV8_ID_AA64DFR0_EL1_HPMN0);
912
913#undef CPUID_GST_FEATURE_RET
914#undef CPUID_GST_FEATURE_RET_NOT_IMPL
915#undef CPUID_GST_FEATURE_WRN
916#undef CPUID_GST_FEATURE_EMU
917#undef CPUID_GST_FEATURE_IGN
918
919 /*
920 * We're good, commit the CPU ID registers.
921 */
922 pVM->cpum.s.GuestIdRegs = *pGuestIdRegs;
923 return VINF_SUCCESS;
924}
925
926
927/**
928 * Loads the CPU ID leaves saved by pass 0.
929 *
930 * @returns VBox status code.
931 * @param pVM The cross context VM structure.
932 * @param pSSM The saved state handle.
933 * @param uVersion The format version.
934 */
935int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
936{
937 CPUMIDREGS GuestIdRegs;
938 int rc = SSMR3GetStructEx(pSSM, &GuestIdRegs, sizeof(GuestIdRegs), 0, g_aCpumIdRegsFields, NULL);
939 AssertRCReturn(rc, rc);
940
941 return cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, &GuestIdRegs);
942}
943
944
945/*
946 *
947 *
948 * CPUID Info Handler.
949 * CPUID Info Handler.
950 * CPUID Info Handler.
951 *
952 *
953 */
954
955/** CLIDR_EL1 field descriptions. */
956static DBGFREGSUBFIELD const g_aClidrEl1Fields[] =
957{
958 DBGFREGSUBFIELD_RO("Ctype1\0" "Cache 1 type field", 0, 3, 0),
959 DBGFREGSUBFIELD_RO("Ctype2\0" "Cache 2 type field", 3, 3, 0),
960 DBGFREGSUBFIELD_RO("Ctype3\0" "Cache 3 type field", 6, 3, 0),
961 DBGFREGSUBFIELD_RO("Ctype4\0" "Cache 4 type field", 9, 3, 0),
962 DBGFREGSUBFIELD_RO("Ctype5\0" "Cache 5 type field", 12, 3, 0),
963 DBGFREGSUBFIELD_RO("Ctype6\0" "Cache 6 type field", 15, 3, 0),
964 DBGFREGSUBFIELD_RO("Ctype7\0" "Cache 7 type field", 18, 3, 0),
965 DBGFREGSUBFIELD_RO("LoUIS\0" "Level of Unification Inner Shareable", 21, 3, 0),
966 DBGFREGSUBFIELD_RO("LoC\0" "Level of Coherence for the cache hierarchy", 24, 3, 0),
967 DBGFREGSUBFIELD_RO("LoUU\0" "Level of Unification Uniprocessor", 27, 3, 0),
968 DBGFREGSUBFIELD_RO("ICB\0" "Inner cache boundary", 30, 3, 0),
969 DBGFREGSUBFIELD_RO("Ttype1\0" "Cache 1 - Tag cache type", 33, 2, 0),
970 DBGFREGSUBFIELD_RO("Ttype2\0" "Cache 2 - Tag cache type", 35, 2, 0),
971 DBGFREGSUBFIELD_RO("Ttype3\0" "Cache 3 - Tag cache type", 37, 2, 0),
972 DBGFREGSUBFIELD_RO("Ttype4\0" "Cache 4 - Tag cache type", 39, 2, 0),
973 DBGFREGSUBFIELD_RO("Ttype5\0" "Cache 5 - Tag cache type", 41, 2, 0),
974 DBGFREGSUBFIELD_RO("Ttype6\0" "Cache 6 - Tag cache type", 43, 2, 0),
975 DBGFREGSUBFIELD_RO("Ttype7\0" "Cache 7 - Tag cache type", 45, 2, 0),
976 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 47, 17, 0),
977 DBGFREGSUBFIELD_TERMINATOR()
978};
979
980
981/** ID_AA64PFR0_EL1 field descriptions. */
982static DBGFREGSUBFIELD const g_aIdAa64PfR0Fields[] =
983{
984 DBGFREGSUBFIELD_RO("EL0\0" "EL0 Exception level handling", 0, 4, 0),
985 DBGFREGSUBFIELD_RO("EL1\0" "EL1 Exception level handling", 4, 4, 0),
986 DBGFREGSUBFIELD_RO("EL2\0" "EL2 Exception level handling", 8, 4, 0),
987 DBGFREGSUBFIELD_RO("EL3\0" "EL3 Exception level handling", 12, 4, 0),
988 DBGFREGSUBFIELD_RO("FP\0" "Floating-point", 16, 4, 0),
989 DBGFREGSUBFIELD_RO("AdvSIMD\0" "Advanced SIMD", 20, 4, 0),
990 DBGFREGSUBFIELD_RO("GIC\0" "System register GIC CPU interface", 24, 4, 0),
991 DBGFREGSUBFIELD_RO("RAS\0" "RAS Extension version", 28, 4, 0),
992 DBGFREGSUBFIELD_RO("SVE\0" "Scalable Vector Extension", 32, 4, 0),
993 DBGFREGSUBFIELD_RO("SEL2\0" "Secure EL2", 36, 4, 0),
994 DBGFREGSUBFIELD_RO("MPAM\0" "MPAM Extension major version number", 40, 4, 0),
995 DBGFREGSUBFIELD_RO("AMU\0" "Activity Monitors Extension support", 44, 4, 0),
996 DBGFREGSUBFIELD_RO("DIT\0" "Data Independent Timing", 48, 4, 0),
997 DBGFREGSUBFIELD_RO("RME\0" "Realm Management Extension", 52, 4, 0),
998 DBGFREGSUBFIELD_RO("CSV2\0" "Speculative use of out of branch targets", 56, 4, 0),
999 DBGFREGSUBFIELD_RO("CSV3\0" "Speculative use of faulting data", 60, 4, 0),
1000 DBGFREGSUBFIELD_TERMINATOR()
1001};
1002
1003
1004/** ID_AA64PFR1_EL1 field descriptions. */
1005static DBGFREGSUBFIELD const g_aIdAa64PfR1Fields[] =
1006{
1007 DBGFREGSUBFIELD_RO("BT\0" "Branch Target Identification mechanism", 0, 4, 0),
1008 DBGFREGSUBFIELD_RO("SSBS\0" "Speculative Store Bypassing controls", 4, 4, 0),
1009 DBGFREGSUBFIELD_RO("MTE\0" "Memory Tagging Extension support", 8, 4, 0),
1010 DBGFREGSUBFIELD_RO("RAS_frac\0" "RAS Extension fractional field", 12, 4, 0),
1011 DBGFREGSUBFIELD_RO("MPAM_frac\0" "MPAM Extension minor version", 16, 4, 0),
1012 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 20, 4, 0),
1013 DBGFREGSUBFIELD_RO("SME\0" "Scalable Matrix Extension", 24, 4, 0),
1014 DBGFREGSUBFIELD_RO("RNDR_trap\0" "Random Number trap to EL3", 28, 4, 0),
1015 DBGFREGSUBFIELD_RO("CSV2_frac\0" "CSV2 fractional version field", 32, 4, 0),
1016 DBGFREGSUBFIELD_RO("NMI\0" "Non-maskable Interrupt support", 36, 4, 0),
1017 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 40, 4, 0),
1018 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 44, 4, 0),
1019 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 48, 4, 0),
1020 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 52, 4, 0),
1021 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 56, 4, 0),
1022 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 60, 4, 0),
1023 DBGFREGSUBFIELD_TERMINATOR()
1024};
1025
1026
1027/** ID_AA64ISAR0_EL1 field descriptions. */
1028static DBGFREGSUBFIELD const g_aIdAa64IsaR0Fields[] =
1029{
1030 DBGFREGSUBFIELD_RO("AES\0" "AES instruction support in AArch64", 4, 4, 0),
1031 DBGFREGSUBFIELD_RO("SHA1\0" "SHA1 instruction support in AArch64", 8, 4, 0),
1032 DBGFREGSUBFIELD_RO("SHA2\0" "SHA256/512 instruction support in AArch64", 12, 4, 0),
1033 DBGFREGSUBFIELD_RO("CRC32\0" "CRC32 instruction support in AArch64", 16, 4, 0),
1034 DBGFREGSUBFIELD_RO("ATOMIC\0" "Atomic instruction support in AArch64", 20, 4, 0),
1035 DBGFREGSUBFIELD_RO("TME\0" "TME instruction support in AArch64", 24, 4, 0),
1036 DBGFREGSUBFIELD_RO("RDM\0" "SQRDMLAH/SQRDMLSH instruction support in AArch64", 28, 4, 0),
1037 DBGFREGSUBFIELD_RO("SHA3\0" "SHA3 instruction support in AArch64", 32, 4, 0),
1038 DBGFREGSUBFIELD_RO("SM3\0" "SM3 instruction support in AArch64", 36, 4, 0),
1039 DBGFREGSUBFIELD_RO("SM4\0" "SM4 instruction support in AArch64", 40, 4, 0),
1040 DBGFREGSUBFIELD_RO("DP\0" "Dot Product instruction support in AArch64", 44, 4, 0),
1041 DBGFREGSUBFIELD_RO("FHM\0" "FMLAL/FMLSL instruction support in AArch64", 48, 4, 0),
1042 DBGFREGSUBFIELD_RO("TS\0" "Flag manipulation instruction support in AArch64", 52, 4, 0),
1043 DBGFREGSUBFIELD_RO("TLB\0" "TLB maintenance instruction support in AArch64", 56, 4, 0),
1044 DBGFREGSUBFIELD_RO("RNDR\0" "Random number instruction support in AArch64", 60, 4, 0),
1045 DBGFREGSUBFIELD_TERMINATOR()
1046};
1047
1048
1049/** ID_AA64ISAR1_EL1 field descriptions. */
1050static DBGFREGSUBFIELD const g_aIdAa64IsaR1Fields[] =
1051{
1052 DBGFREGSUBFIELD_RO("DPB\0" "Data Persistance writeback support in AArch64", 0, 4, 0),
1053 DBGFREGSUBFIELD_RO("APA\0" "QARMA5 PAuth support in AArch64", 4, 4, 0),
1054 DBGFREGSUBFIELD_RO("API\0" "Impl defined PAuth support in AArch64", 8, 4, 0),
1055 DBGFREGSUBFIELD_RO("JSCVT\0" "FJCVTZS instruction support in AArch64", 12, 4, 0),
1056 DBGFREGSUBFIELD_RO("FCMA\0" "FCMLA/FCADD instruction support in AArch64", 16, 4, 0),
1057 DBGFREGSUBFIELD_RO("LRCPC\0" "RCpc instruction support in AArch64", 20, 4, 0),
1058 DBGFREGSUBFIELD_RO("GPA\0" "QARMA5 code authentication support in AArch64", 24, 4, 0),
1059 DBGFREGSUBFIELD_RO("GPI\0" "Impl defined code authentication support in AArch64", 28, 4, 0),
1060 DBGFREGSUBFIELD_RO("FRINTTS\0" "FRINT{32,64}{Z,X} instruction support in AArch64", 32, 4, 0),
1061 DBGFREGSUBFIELD_RO("SB\0" "SB instruction support in AArch64", 36, 4, 0),
1062 DBGFREGSUBFIELD_RO("SPECRES\0" "Prediction invalidation support in AArch64", 40, 4, 0),
1063 DBGFREGSUBFIELD_RO("BF16\0" "BFloat16 support in AArch64", 44, 4, 0),
1064 DBGFREGSUBFIELD_RO("DGH\0" "Data Gathering Hint support in AArch64", 48, 4, 0),
1065 DBGFREGSUBFIELD_RO("I8MM\0" "Int8 matrix mul instruction support in AArch64", 52, 4, 0),
1066 DBGFREGSUBFIELD_RO("XS\0" "XS attribute support in AArch64", 56, 4, 0),
1067 DBGFREGSUBFIELD_RO("LS64\0" "LD64B and ST64B* instruction support in AArch64", 60, 4, 0),
1068 DBGFREGSUBFIELD_TERMINATOR()
1069};
1070
1071
1072/** ID_AA64ISAR2_EL1 field descriptions. */
1073static DBGFREGSUBFIELD const g_aIdAa64IsaR2Fields[] =
1074{
1075 DBGFREGSUBFIELD_RO("WFxT\0" "WFET/WFIT intruction support in AArch64", 0, 4, 0),
1076 DBGFREGSUBFIELD_RO("RPRES\0" "Reciprocal 12 bit mantissa support in AArch64", 4, 4, 0),
1077 DBGFREGSUBFIELD_RO("GPA3\0" "QARMA3 code authentication support in AArch64", 8, 4, 0),
1078 DBGFREGSUBFIELD_RO("APA3\0" "QARMA3 PAuth support in AArch64", 12, 4, 0),
1079 DBGFREGSUBFIELD_RO("MOPS\0" "Memory Copy and Set instruction support in AArch64", 16, 4, 0),
1080 DBGFREGSUBFIELD_RO("BC\0" "BC instruction support in AArch64", 20, 4, 0),
1081 DBGFREGSUBFIELD_RO("PAC_frac\0" "ConstPACField() returns TRUE", 24, 4, 0),
1082 DBGFREGSUBFIELD_TERMINATOR()
1083};
1084
1085
1086/** ID_AA64MMFR0_EL1 field descriptions. */
1087static DBGFREGSUBFIELD const g_aIdAa64MmfR0Fields[] =
1088{
1089 DBGFREGSUBFIELD_RO("PARange\0" "Physical address width", 0, 4, 0),
1090 DBGFREGSUBFIELD_RO("ASIDBits\0" "Number of ASID bits", 4, 4, 0),
1091 DBGFREGSUBFIELD_RO("BigEnd\0" "Mixed-endian configuration support", 8, 4, 0),
1092 DBGFREGSUBFIELD_RO("SNSMem\0" "Secure and Non-secure memory distinction", 12, 4, 0),
1093 DBGFREGSUBFIELD_RO("BigEndEL0\0" "Mixed-endian support in EL0 only", 16, 4, 0),
1094 DBGFREGSUBFIELD_RO("TGran16\0" "16KiB memory granule size", 20, 4, 0),
1095 DBGFREGSUBFIELD_RO("TGran64\0" "64KiB memory granule size", 24, 4, 0),
1096 DBGFREGSUBFIELD_RO("TGran4\0" "4KiB memory granule size", 28, 4, 0),
1097 DBGFREGSUBFIELD_RO("TGran16_2\0" "16KiB memory granule size at stage 2", 32, 4, 0),
1098 DBGFREGSUBFIELD_RO("TGran64_2\0" "64KiB memory granule size at stage 2", 36, 4, 0),
1099 DBGFREGSUBFIELD_RO("TGran4_2\0" "4KiB memory granule size at stage 2", 40, 4, 0),
1100 DBGFREGSUBFIELD_RO("ExS\0" "Disabling context synchronizing exception", 44, 4, 0),
1101 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 48, 4, 0),
1102 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 52, 4, 0),
1103 DBGFREGSUBFIELD_RO("FGT\0" "Fine-grained trap controls support", 56, 4, 0),
1104 DBGFREGSUBFIELD_RO("ECV\0" "Enhanced Counter Virtualization support", 60, 4, 0),
1105 DBGFREGSUBFIELD_TERMINATOR()
1106};
1107
1108
1109/** ID_AA64MMFR1_EL1 field descriptions. */
1110static DBGFREGSUBFIELD const g_aIdAa64MmfR1Fields[] =
1111{
1112 DBGFREGSUBFIELD_RO("HAFDBS\0" "Hardware updates to Access/Dirty state", 0, 4, 0),
1113 DBGFREGSUBFIELD_RO("VMIDBit\0" "Number of VMID bits", 4, 4, 0),
1114 DBGFREGSUBFIELD_RO("VH\0" "Virtualization Host Extensions", 8, 4, 0),
1115 DBGFREGSUBFIELD_RO("HPDS\0" "Hierarchical Permission Disables", 12, 4, 0),
1116 DBGFREGSUBFIELD_RO("LO\0" "LORegions support", 16, 4, 0),
1117 DBGFREGSUBFIELD_RO("PAN\0" "Privileged Access Never", 20, 4, 0),
1118 DBGFREGSUBFIELD_RO("SpecSEI\0" "SError interrupt exception for speculative reads", 24, 4, 0),
1119 DBGFREGSUBFIELD_RO("XNX\0" "Execute-never control support", 28, 4, 0),
1120 DBGFREGSUBFIELD_RO("TWED\0" "Configurable delayed WFE trapping", 32, 4, 0),
1121 DBGFREGSUBFIELD_RO("ETS\0" "Enhanced Translation Synchronization support", 36, 4, 0),
1122 DBGFREGSUBFIELD_RO("HCX\0" "HCRX_EL2 support", 40, 4, 0),
1123 DBGFREGSUBFIELD_RO("AFP\0" "FPCR.{AH,FIZ,NEP} support", 44, 4, 0),
1124 DBGFREGSUBFIELD_RO("nTLBPA\0" "Caching of translation table walks", 48, 4, 0),
1125 DBGFREGSUBFIELD_RO("TIDCP1\0" "FEAT_TIDCP1 support", 52, 4, 0),
1126 DBGFREGSUBFIELD_RO("CMOW\0" "Cache maintenance instruction permission", 56, 4, 0),
1127 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 60, 4, 0),
1128 DBGFREGSUBFIELD_TERMINATOR()
1129};
1130
1131
1132/** ID_AA64MMFR2_EL1 field descriptions. */
1133static DBGFREGSUBFIELD const g_aIdAa64MmfR2Fields[] =
1134{
1135 DBGFREGSUBFIELD_RO("CnP\0" "Common not Private translation support", 0, 4, 0),
1136 DBGFREGSUBFIELD_RO("UAO\0" "User Access Override", 4, 4, 0),
1137 DBGFREGSUBFIELD_RO("LSM\0" "LSMAOE/nTLSMD bit support", 8, 4, 0),
1138 DBGFREGSUBFIELD_RO("IESB\0" "IESB bit support in SCTLR_ELx", 12, 4, 0),
1139 DBGFREGSUBFIELD_RO("VARange\0" "Large virtual address space support", 16, 4, 0),
1140 DBGFREGSUBFIELD_RO("CCIDX\0" "64-bit CCSIDR_EL1 format", 20, 4, 0),
1141 DBGFREGSUBFIELD_RO("NV\0" "Nested Virtualization support", 24, 4, 0),
1142 DBGFREGSUBFIELD_RO("ST\0" "Small translation table support", 28, 4, 0),
1143 DBGFREGSUBFIELD_RO("AT\0" "Unaligned single-copy atomicity support", 32, 4, 0),
1144 DBGFREGSUBFIELD_RO("IDS\0" "FEAT_IDST support", 36, 4, 0),
1145 DBGFREGSUBFIELD_RO("FWB\0" "HCR_EL2.FWB support", 40, 4, 0),
1146 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 44, 4, 0),
1147 DBGFREGSUBFIELD_RO("TTL\0" "TTL field support in address operations", 48, 4, 0),
1148 DBGFREGSUBFIELD_RO("BBM\0" "FEAT_BBM support", 52, 4, 0),
1149 DBGFREGSUBFIELD_RO("EVT\0" "Enhanced Virtualization Traps support", 56, 4, 0),
1150 DBGFREGSUBFIELD_RO("E0PD\0" "E0PD mechanism support", 60, 4, 0),
1151 DBGFREGSUBFIELD_TERMINATOR()
1152};
1153
1154
1155/** ID_AA64DFR0_EL1 field descriptions. */
1156static DBGFREGSUBFIELD const g_aIdAa64DfR0Fields[] =
1157{
1158 DBGFREGSUBFIELD_RO("DebugVer\0" "Debug architecture version", 0, 4, 0),
1159 DBGFREGSUBFIELD_RO("TraceVer\0" "Trace support", 4, 4, 0),
1160 DBGFREGSUBFIELD_RO("PMUVer\0" "Performance Monitors Extension version", 8, 4, 0),
1161 DBGFREGSUBFIELD_RO("BRPs\0" "Number of breakpoints minus 1", 12, 4, 0),
1162 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 16, 4, 0),
1163 DBGFREGSUBFIELD_RO("WRPs\0" "Number of watchpoints minus 1", 20, 4, 0),
1164 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 24, 4, 0),
1165 DBGFREGSUBFIELD_RO("CTX_CMPs\0" "Number of context-aware breakpoints minus 1", 28, 4, 0),
1166 DBGFREGSUBFIELD_RO("PMSVer\0" "Statistical Profiling Extension version", 32, 4, 0),
1167 DBGFREGSUBFIELD_RO("DoubleLock\0" "OS Double Lock support", 36, 4, 0),
1168 DBGFREGSUBFIELD_RO("TraceFilt\0" "Armv8.4 Self-hosted Trace Extension version", 40, 4, 0),
1169 DBGFREGSUBFIELD_RO("TraceBuffer\0" "Trace Buffer Extension", 44, 4, 0),
1170 DBGFREGSUBFIELD_RO("MTPMU\0" "Multi-threaded PMU extension", 48, 4, 0),
1171 DBGFREGSUBFIELD_RO("BRBE\0" "Branch Record Buffer Extension", 52, 4, 0),
1172 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 56, 4, 0),
1173 DBGFREGSUBFIELD_RO("HPMN0\0" "Zero PMU event counters for guest", 60, 4, 0),
1174 DBGFREGSUBFIELD_TERMINATOR()
1175};
1176
1177
1178/** ID_AA64DFR1_EL1 field descriptions. */
1179static DBGFREGSUBFIELD const g_aIdAa64DfR1Fields[] =
1180{
1181 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 0, 4, 0),
1182 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 4, 4, 0),
1183 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 8, 4, 0),
1184 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 12, 4, 0),
1185 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 16, 4, 0),
1186 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 20, 4, 0),
1187 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 24, 4, 0),
1188 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 28, 4, 0),
1189 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 32, 4, 0),
1190 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 36, 4, 0),
1191 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 40, 4, 0),
1192 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 44, 4, 0),
1193 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 48, 4, 0),
1194 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 52, 4, 0),
1195 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 56, 4, 0),
1196 DBGFREGSUBFIELD_RO("Res0\0" "Reserved", 60, 4, 0),
1197 DBGFREGSUBFIELD_TERMINATOR()
1198};
1199
1200
1201/** ID_AA64AFR0_EL1 field descriptions. */
1202static DBGFREGSUBFIELD const g_aIdAa64AfR0Fields[] =
1203{
1204 DBGFREGSUBFIELD_RO("ImpDef\0" "Implementation defined", 0, 32, 0),
1205 DBGFREGSUBFIELD_TERMINATOR()
1206};
1207
1208
1209/** ID_AA64AFR1_EL1 field descriptions. */
1210static DBGFREGSUBFIELD const g_aIdAa64AfR1Fields[] =
1211{
1212 DBGFREGSUBFIELD_RO("ImpDef\0" "Implementation defined", 0, 32, 0),
1213 DBGFREGSUBFIELD_TERMINATOR()
1214};
1215
1216
1217static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
1218 const char *pszLeadIn, uint32_t cchWidth)
1219{
1220 if (pszLeadIn)
1221 pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
1222
1223 for (uint32_t iBit = 0; iBit < 64; iBit++)
1224 if (RT_BIT_64(iBit) & uVal)
1225 {
1226 while ( pDesc->pszName != NULL
1227 && iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
1228 pDesc++;
1229 if ( pDesc->pszName != NULL
1230 && iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
1231 {
1232 if (pDesc->cBits == 1)
1233 pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
1234 else
1235 {
1236 uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
1237 if (pDesc->cBits < 64)
1238 uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
1239 pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
1240 iBit = pDesc->iFirstBit + pDesc->cBits - 1;
1241 }
1242 }
1243 else
1244 pHlp->pfnPrintf(pHlp, " %u", iBit);
1245 }
1246 if (pszLeadIn)
1247 pHlp->pfnPrintf(pHlp, "\n");
1248}
1249
1250
1251static void cpumR3CpuIdInfoVerboseCompareListU64(PCDBGFINFOHLP pHlp, uint64_t uVal1, uint64_t uVal2, PCDBGFREGSUBFIELD pDesc,
1252 uint32_t cchWidth)
1253{
1254 uint32_t uCombined = uVal1 | uVal2;
1255 for (uint32_t iBit = 0; iBit < 64; iBit++)
1256 if ( (RT_BIT_64(iBit) & uCombined)
1257 || (iBit == pDesc->iFirstBit && pDesc->pszName) )
1258 {
1259 while ( pDesc->pszName != NULL
1260 && iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
1261 pDesc++;
1262
1263 if ( pDesc->pszName != NULL
1264 && iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
1265 {
1266 size_t cchMnemonic = strlen(pDesc->pszName);
1267 const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
1268 size_t cchDesc = strlen(pszDesc);
1269 uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
1270 uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
1271 if (pDesc->cBits < 64)
1272 {
1273 uFieldValue1 &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
1274 uFieldValue2 &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
1275 }
1276
1277 pHlp->pfnPrintf(pHlp, pDesc->cBits < 5 ? " %s - %s%*s= %u (%u)\n" : " %s - %s%*s= %#x (%#x)\n",
1278 pDesc->pszName, pszDesc,
1279 cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
1280 uFieldValue1, uFieldValue2);
1281
1282 iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
1283 pDesc++;
1284 }
1285 else
1286 pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
1287 RT_BOOL(uVal1 & RT_BIT_64(iBit)), RT_BOOL(uVal2 & RT_BIT_64(iBit)));
1288 }
1289}
1290
1291
1292/**
1293 * Produces a detailed summary of standard leaf 0x00000007.
1294 *
1295 * @param pHlp The info helper functions.
1296 * @param pszIdReg The ID register name.
1297 * @param u64IdRegHost The host value of the ID register.
1298 * @param u64IdRegGuest The guest value of the ID register.
1299 * @param pDesc The field descriptor.
1300 * @param fVerbose Whether to be very verbose or not.
1301 */
1302static void cpumR3CpuIdInfoIdRegDetails(PCDBGFINFOHLP pHlp, const char *pszIdReg, uint64_t u64IdRegHost, uint64_t u64IdRegGuest,
1303 PCDBGFREGSUBFIELD pDesc, bool fVerbose)
1304{
1305 pHlp->pfnPrintf(pHlp, "ID register %s: Host %#RX64 Guest %#RX64\n", pszIdReg, u64IdRegHost, u64IdRegGuest);
1306 if (fVerbose)
1307 {
1308 pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1309 cpumR3CpuIdInfoVerboseCompareListU64(pHlp, u64IdRegGuest, u64IdRegHost, pDesc, 56);
1310 }
1311 else
1312 cpumR3CpuIdInfoMnemonicListU64(pHlp, u64IdRegGuest, pDesc, "Features:", 36);
1313}
1314
1315
1316/**
1317 * Display the guest CpuId leaves.
1318 *
1319 * @param pVM The cross context VM structure.
1320 * @param pHlp The info helper functions.
1321 * @param pszArgs "terse", "default" or "verbose".
1322 */
1323DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1324{
1325 /*
1326 * Parse the argument.
1327 */
1328 unsigned iVerbosity = 1;
1329 if (pszArgs)
1330 {
1331 pszArgs = RTStrStripL(pszArgs);
1332 if (!strcmp(pszArgs, "terse"))
1333 iVerbosity--;
1334 else if (!strcmp(pszArgs, "verbose"))
1335 iVerbosity++;
1336 }
1337
1338 /** @todo MIDR_EL1. */
1339
1340 cpumR3CpuIdInfoIdRegDetails(pHlp, "CLIDR_EL1",
1341 pVM->cpum.s.HostIdRegs.u64RegClidrEl1,
1342 pVM->cpum.s.GuestIdRegs.u64RegClidrEl1,
1343 g_aClidrEl1Fields, iVerbosity > 1);
1344
1345 cpumR3CpuIdInfoIdRegDetails(pHlp, "ID_AA64PFR0_EL1",
1346 pVM->cpum.s.HostIdRegs.u64RegIdAa64Pfr0El1,
1347 pVM->cpum.s.GuestIdRegs.u64RegIdAa64Pfr0El1,
1348 g_aIdAa64PfR0Fields, iVerbosity > 1);
1349
1350 cpumR3CpuIdInfoIdRegDetails(pHlp, "ID_AA64PFR1_EL1",
1351 pVM->cpum.s.HostIdRegs.u64RegIdAa64Pfr1El1,
1352 pVM->cpum.s.GuestIdRegs.u64RegIdAa64Pfr1El1,
1353 g_aIdAa64PfR1Fields, iVerbosity > 1);
1354
1355 cpumR3CpuIdInfoIdRegDetails(pHlp, "ID_AA64ISAR0_EL1",
1356 pVM->cpum.s.HostIdRegs.u64RegIdAa64Isar0El1,
1357 pVM->cpum.s.GuestIdRegs.u64RegIdAa64Isar0El1,
1358 g_aIdAa64IsaR0Fields, iVerbosity > 1);
1359
1360 cpumR3CpuIdInfoIdRegDetails(pHlp, "ID_AA64ISAR1_EL1",
1361 pVM->cpum.s.HostIdRegs.u64RegIdAa64Isar1El1,
1362 pVM->cpum.s.GuestIdRegs.u64RegIdAa64Isar1El1,
1363 g_aIdAa64IsaR1Fields, iVerbosity > 1);
1364
1365 cpumR3CpuIdInfoIdRegDetails(pHlp, "ID_AA64ISAR2_EL1",
1366 pVM->cpum.s.HostIdRegs.u64RegIdAa64Isar2El1,
1367 pVM->cpum.s.GuestIdRegs.u64RegIdAa64Isar2El1,
1368 g_aIdAa64IsaR2Fields, iVerbosity > 1);
1369
1370 cpumR3CpuIdInfoIdRegDetails(pHlp, "ID_AA64MMFR0_EL1",
1371 pVM->cpum.s.HostIdRegs.u64RegIdAa64Mmfr0El1,
1372 pVM->cpum.s.GuestIdRegs.u64RegIdAa64Mmfr0El1,
1373 g_aIdAa64MmfR0Fields, iVerbosity > 1);
1374
1375 cpumR3CpuIdInfoIdRegDetails(pHlp, "ID_AA64MMFR1_EL1",
1376 pVM->cpum.s.HostIdRegs.u64RegIdAa64Mmfr1El1,
1377 pVM->cpum.s.GuestIdRegs.u64RegIdAa64Mmfr1El1,
1378 g_aIdAa64MmfR1Fields, iVerbosity > 1);
1379
1380 cpumR3CpuIdInfoIdRegDetails(pHlp, "ID_AA64MMFR2_EL1",
1381 pVM->cpum.s.HostIdRegs.u64RegIdAa64Mmfr2El1,
1382 pVM->cpum.s.GuestIdRegs.u64RegIdAa64Mmfr2El1,
1383 g_aIdAa64MmfR2Fields, iVerbosity > 1);
1384
1385 cpumR3CpuIdInfoIdRegDetails(pHlp, "ID_AA64DFR0_EL1",
1386 pVM->cpum.s.HostIdRegs.u64RegIdAa64Dfr0El1,
1387 pVM->cpum.s.GuestIdRegs.u64RegIdAa64Dfr0El1,
1388 g_aIdAa64DfR0Fields, iVerbosity > 1);
1389
1390 cpumR3CpuIdInfoIdRegDetails(pHlp, "ID_AA64DFR1_EL1",
1391 pVM->cpum.s.HostIdRegs.u64RegIdAa64Dfr1El1,
1392 pVM->cpum.s.GuestIdRegs.u64RegIdAa64Dfr1El1,
1393 g_aIdAa64DfR1Fields, iVerbosity > 1);
1394
1395 cpumR3CpuIdInfoIdRegDetails(pHlp, "ID_AA64AFR0_EL1",
1396 pVM->cpum.s.HostIdRegs.u64RegIdAa64Afr0El1,
1397 pVM->cpum.s.GuestIdRegs.u64RegIdAa64Afr0El1,
1398 g_aIdAa64AfR0Fields, iVerbosity > 1);
1399
1400 cpumR3CpuIdInfoIdRegDetails(pHlp, "ID_AA64AFR1_EL1",
1401 pVM->cpum.s.HostIdRegs.u64RegIdAa64Afr1El1,
1402 pVM->cpum.s.GuestIdRegs.u64RegIdAa64Afr1El1,
1403 g_aIdAa64AfR1Fields, iVerbosity > 1);
1404}
1405
1406
1407/**
1408 * Display the guest CPU features.
1409 *
1410 * @param pVM The cross context VM structure.
1411 * @param pHlp The info helper functions.
1412 * @param pszArgs "default" or "verbose".
1413 */
1414DECLCALLBACK(void) cpumR3CpuFeatInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1415{
1416 /*
1417 * Parse the argument.
1418 */
1419 bool fVerbose = false;
1420 if (pszArgs)
1421 {
1422 pszArgs = RTStrStripL(pszArgs);
1423 if (!strcmp(pszArgs, "verbose"))
1424 fVerbose = true;
1425 }
1426
1427 if (fVerbose)
1428 pHlp->pfnPrintf(pHlp, " Features = guest (host)\n");
1429 else
1430 pHlp->pfnPrintf(pHlp, " Features = guest\n");
1431
1432
1433#define LOG_CPU_FEATURE(a_FeatNm, a_Flag) \
1434 do { \
1435 if (fVerbose) \
1436 pHlp->pfnPrintf(pHlp, " %*s = %u (%u)\n", 41, #a_FeatNm, pVM->cpum.s.GuestFeatures.a_Flag, pVM->cpum.s.HostFeatures.a_Flag); \
1437 else \
1438 pHlp->pfnPrintf(pHlp, " %*s = %u\n", 41, #a_FeatNm, pVM->cpum.s.GuestFeatures.a_Flag); \
1439 } while (0)
1440
1441 /* Not really features. */
1442 LOG_CPU_FEATURE(FEAT_TGRAN4K, fTGran4K);
1443 LOG_CPU_FEATURE(FEAT_TGRAN16K, fTGran16K);
1444 LOG_CPU_FEATURE(FEAT_TGRAN64K, fTGran64K);
1445
1446 /* Offical ARM FEAT_* definitions start here. */
1447 LOG_CPU_FEATURE(FEAT_AdvSIMD, fAdvSimd);
1448 LOG_CPU_FEATURE(FEAT_AES, fAes);
1449 LOG_CPU_FEATURE(FEAT_PMULL, fPmull);
1450 LOG_CPU_FEATURE(FEAT_CP15DISABLE2, fCp15Disable2);
1451 LOG_CPU_FEATURE(FEAT_CSV2, fCsv2);
1452 LOG_CPU_FEATURE(FEAT_CSV2_1p1, fCsv21p1);
1453 LOG_CPU_FEATURE(FEAT_CSV2_1p2, fCsv21p2);
1454 LOG_CPU_FEATURE(FEAT_CSV3, fCsv3);
1455 LOG_CPU_FEATURE(FEAT_DGH, fDgh);
1456 LOG_CPU_FEATURE(FEAT_DOUBLELOCK, fDoubleLock);
1457 LOG_CPU_FEATURE(FEAT_ETS2, fEts2);
1458 LOG_CPU_FEATURE(FEAT_FP, fFp);
1459 LOG_CPU_FEATURE(FEAT_IVIPT, fIvipt);
1460 LOG_CPU_FEATURE(FEAT_PCSRv8, fPcsrV8);
1461 LOG_CPU_FEATURE(FEAT_SPECRES, fSpecres);
1462 LOG_CPU_FEATURE(FEAT_RAS, fRas);
1463 LOG_CPU_FEATURE(FEAT_SB, fSb);
1464 LOG_CPU_FEATURE(FEAT_SHA1, fSha1);
1465 LOG_CPU_FEATURE(FEAT_SHA256, fSha256);
1466 LOG_CPU_FEATURE(FEAT_SSBS, fSsbs);
1467 LOG_CPU_FEATURE(FEAT_SSBS2, fSsbs2);
1468 LOG_CPU_FEATURE(FEAT_CRC32, fCrc32);
1469 LOG_CPU_FEATURE(FEAT_nTLBPA, fNTlbpa);
1470 LOG_CPU_FEATURE(FEAT_Debugv8p1, fDebugV8p1);
1471 LOG_CPU_FEATURE(FEAT_HPDS, fHpds);
1472 LOG_CPU_FEATURE(FEAT_LOR, fLor);
1473 LOG_CPU_FEATURE(FEAT_LSE, fLse);
1474 LOG_CPU_FEATURE(FEAT_PAN, fPan);
1475 LOG_CPU_FEATURE(FEAT_PMUv3p1, fPmuV3p1);
1476 LOG_CPU_FEATURE(FEAT_RDM, fRdm);
1477 LOG_CPU_FEATURE(FEAT_HAFDBS, fHafdbs);
1478 LOG_CPU_FEATURE(FEAT_VHE, fVhe);
1479 LOG_CPU_FEATURE(FEAT_VMID16, fVmid16);
1480 LOG_CPU_FEATURE(FEAT_AA32BF16, fAa32Bf16);
1481 LOG_CPU_FEATURE(FEAT_AA32HPD, fAa32Hpd);
1482 LOG_CPU_FEATURE(FEAT_AA32I8MM, fAa32I8mm);
1483 LOG_CPU_FEATURE(FEAT_PAN2, fPan2);
1484 LOG_CPU_FEATURE(FEAT_BF16, fBf16);
1485 LOG_CPU_FEATURE(FEAT_DPB2, fDpb2);
1486 LOG_CPU_FEATURE(FEAT_DPB, fDpb);
1487 LOG_CPU_FEATURE(FEAT_Debugv8p2, fDebugV8p2);
1488 LOG_CPU_FEATURE(FEAT_DotProd, fDotProd);
1489 LOG_CPU_FEATURE(FEAT_EVT, fEvt);
1490 LOG_CPU_FEATURE(FEAT_F32MM, fF32mm);
1491 LOG_CPU_FEATURE(FEAT_F64MM, fF64mm);
1492 LOG_CPU_FEATURE(FEAT_FHM, fFhm);
1493 LOG_CPU_FEATURE(FEAT_FP16, fFp16);
1494 LOG_CPU_FEATURE(FEAT_I8MM, fI8mm);
1495 LOG_CPU_FEATURE(FEAT_IESB, fIesb);
1496 LOG_CPU_FEATURE(FEAT_LPA, fLpa);
1497 LOG_CPU_FEATURE(FEAT_LSMAOC, fLsmaoc);
1498 LOG_CPU_FEATURE(FEAT_LVA, fLva);
1499 LOG_CPU_FEATURE(FEAT_MPAM, fMpam);
1500 LOG_CPU_FEATURE(FEAT_PCSRv8p2, fPcsrV8p2);
1501 LOG_CPU_FEATURE(FEAT_SHA3, fSha3);
1502 LOG_CPU_FEATURE(FEAT_SHA512, fSha512);
1503 LOG_CPU_FEATURE(FEAT_SM3, fSm3);
1504 LOG_CPU_FEATURE(FEAT_SM4, fSm4);
1505 LOG_CPU_FEATURE(FEAT_SPE, fSpe);
1506 LOG_CPU_FEATURE(FEAT_SVE, fSve);
1507 LOG_CPU_FEATURE(FEAT_TTCNP, fTtcnp);
1508 LOG_CPU_FEATURE(FEAT_HPDS2, fHpds2);
1509 LOG_CPU_FEATURE(FEAT_XNX, fXnx);
1510 LOG_CPU_FEATURE(FEAT_UAO, fUao);
1511 LOG_CPU_FEATURE(FEAT_VPIPT, fVpipt);
1512 LOG_CPU_FEATURE(FEAT_CCIDX, fCcidx);
1513 LOG_CPU_FEATURE(FEAT_FCMA, fFcma);
1514 LOG_CPU_FEATURE(FEAT_DoPD, fDopd);
1515 LOG_CPU_FEATURE(FEAT_EPAC, fEpac);
1516 LOG_CPU_FEATURE(FEAT_FPAC, fFpac);
1517 LOG_CPU_FEATURE(FEAT_FPACCOMBINE, fFpacCombine);
1518 LOG_CPU_FEATURE(FEAT_JSCVT, fJscvt);
1519 LOG_CPU_FEATURE(FEAT_LRCPC, fLrcpc);
1520 LOG_CPU_FEATURE(FEAT_NV, fNv);
1521 LOG_CPU_FEATURE(FEAT_PACQARMA5, fPacQarma5);
1522 LOG_CPU_FEATURE(FEAT_PACIMP, fPacImp);
1523 LOG_CPU_FEATURE(FEAT_PAuth, fPAuth);
1524 LOG_CPU_FEATURE(FEAT_PAuth2, fPAuth2);
1525 LOG_CPU_FEATURE(FEAT_SPEv1p1, fSpeV1p1);
1526 LOG_CPU_FEATURE(FEAT_AMUv1, fAmuV1);
1527 LOG_CPU_FEATURE(FEAT_CNTSC, fCntsc);
1528 LOG_CPU_FEATURE(FEAT_Debugv8p4, fDebugV8p4);
1529 LOG_CPU_FEATURE(FEAT_DoubleFault, fDoubleFault);
1530 LOG_CPU_FEATURE(FEAT_DIT, fDit);
1531 LOG_CPU_FEATURE(FEAT_FlagM, fFlagM);
1532 LOG_CPU_FEATURE(FEAT_IDST, fIdst);
1533 LOG_CPU_FEATURE(FEAT_LRCPC2, fLrcpc2);
1534 LOG_CPU_FEATURE(FEAT_LSE2, fLse2);
1535 LOG_CPU_FEATURE(FEAT_NV2, fNv2);
1536 LOG_CPU_FEATURE(FEAT_PMUv3p4, fPmuV3p4);
1537 LOG_CPU_FEATURE(FEAT_RASv1p1, fRasV1p1);
1538 LOG_CPU_FEATURE(FEAT_RASSAv1p1, fRassaV1p1);
1539 LOG_CPU_FEATURE(FEAT_S2FWB, fS2Fwb);
1540 LOG_CPU_FEATURE(FEAT_SEL2, fSecEl2);
1541 LOG_CPU_FEATURE(FEAT_TLBIOS, fTlbios);
1542 LOG_CPU_FEATURE(FEAT_TLBIRANGE, fTlbirange);
1543 LOG_CPU_FEATURE(FEAT_TRF, fTrf);
1544 LOG_CPU_FEATURE(FEAT_TTL, fTtl);
1545 LOG_CPU_FEATURE(FEAT_BBM, fBbm);
1546 LOG_CPU_FEATURE(FEAT_TTST, fTtst);
1547 LOG_CPU_FEATURE(FEAT_BTI, fBti);
1548 LOG_CPU_FEATURE(FEAT_FlagM2, fFlagM2);
1549 LOG_CPU_FEATURE(FEAT_ExS, fExs);
1550 LOG_CPU_FEATURE(FEAT_E0PD, fE0Pd);
1551 LOG_CPU_FEATURE(FEAT_FRINTTS, fFrintts);
1552 LOG_CPU_FEATURE(FEAT_GTG, fGtg);
1553 LOG_CPU_FEATURE(FEAT_MTE, fMte);
1554 LOG_CPU_FEATURE(FEAT_MTE2, fMte2);
1555 LOG_CPU_FEATURE(FEAT_PMUv3p5, fPmuV3p5);
1556 LOG_CPU_FEATURE(FEAT_RNG, fRng);
1557 LOG_CPU_FEATURE(FEAT_AMUv1p1, fAmuV1p1);
1558 LOG_CPU_FEATURE(FEAT_ECV, fEcv);
1559 LOG_CPU_FEATURE(FEAT_FGT, fFgt);
1560 LOG_CPU_FEATURE(FEAT_MPAMv0p1, fMpamV0p1);
1561 LOG_CPU_FEATURE(FEAT_MPAMv1p1, fMpamV1p1);
1562 LOG_CPU_FEATURE(FEAT_MTPMU, fMtPmu);
1563 LOG_CPU_FEATURE(FEAT_TWED, fTwed);
1564 LOG_CPU_FEATURE(FEAT_ETMv4, fEtmV4);
1565 LOG_CPU_FEATURE(FEAT_ETMv4p1, fEtmV4p1);
1566 LOG_CPU_FEATURE(FEAT_ETMv4p2, fEtmV4p2);
1567 LOG_CPU_FEATURE(FEAT_ETMv4p3, fEtmV4p3);
1568 LOG_CPU_FEATURE(FEAT_ETMv4p4, fEtmV4p4);
1569 LOG_CPU_FEATURE(FEAT_ETMv4p5, fEtmV4p5);
1570 LOG_CPU_FEATURE(FEAT_ETMv4p6, fEtmV4p6);
1571 LOG_CPU_FEATURE(FEAT_GICv3, fGicV3);
1572 LOG_CPU_FEATURE(FEAT_GICv3p1, fGicV3p1);
1573 LOG_CPU_FEATURE(FEAT_GICv3_TDIR, fGicV3Tdir);
1574 LOG_CPU_FEATURE(FEAT_GICv4, fGicV4);
1575 LOG_CPU_FEATURE(FEAT_GICv4p1, fGicV4p1);
1576 LOG_CPU_FEATURE(FEAT_PMUv3, fPmuV3);
1577 LOG_CPU_FEATURE(FEAT_ETE, fEte);
1578 LOG_CPU_FEATURE(FEAT_ETEv1p1, fEteV1p1);
1579 LOG_CPU_FEATURE(FEAT_ETEv1p2, fEteV1p2);
1580 LOG_CPU_FEATURE(FEAT_SVE2, fSve2);
1581 LOG_CPU_FEATURE(FEAT_SVE_AES, fSveAes);
1582 LOG_CPU_FEATURE(FEAT_SVE_PMULL128, fSvePmull128);
1583 LOG_CPU_FEATURE(FEAT_SVE_BitPerm, fSveBitPerm);
1584 LOG_CPU_FEATURE(FEAT_SVE_SHA3, fSveSha3);
1585 LOG_CPU_FEATURE(FEAT_SVE_SM4, fSveSm4);
1586 LOG_CPU_FEATURE(FEAT_TME, fTme);
1587 LOG_CPU_FEATURE(FEAT_TRBE, fTrbe);
1588 LOG_CPU_FEATURE(FEAT_SME, fSme);
1589
1590 LOG_CPU_FEATURE(FEAT_AFP, fAfp);
1591 LOG_CPU_FEATURE(FEAT_HCX, fHcx);
1592 LOG_CPU_FEATURE(FEAT_LPA2, fLpa2);
1593 LOG_CPU_FEATURE(FEAT_LS64, fLs64);
1594 LOG_CPU_FEATURE(FEAT_LS64_V, fLs64V);
1595 LOG_CPU_FEATURE(FEAT_LS64_ACCDATA, fLs64Accdata);
1596 LOG_CPU_FEATURE(FEAT_MTE3, fMte3);
1597 LOG_CPU_FEATURE(FEAT_PAN3, fPan3);
1598 LOG_CPU_FEATURE(FEAT_PMUv3p7, fPmuV3p7);
1599 LOG_CPU_FEATURE(FEAT_RPRES, fRpres);
1600 LOG_CPU_FEATURE(FEAT_RME, fRme);
1601 LOG_CPU_FEATURE(FEAT_SME_FA64, fSmeFA64);
1602 LOG_CPU_FEATURE(FEAT_SME_F64F64, fSmeF64F64);
1603 LOG_CPU_FEATURE(FEAT_SME_I16I64, fSmeI16I64);
1604 LOG_CPU_FEATURE(FEAT_SPEv1p2, fSpeV1p2);
1605 LOG_CPU_FEATURE(FEAT_EBF16, fEbf16);
1606 LOG_CPU_FEATURE(FEAT_WFxT, fWfxt);
1607 LOG_CPU_FEATURE(FEAT_XS, fXs);
1608 LOG_CPU_FEATURE(FEAT_BRBE, fBrbe);
1609
1610 LOG_CPU_FEATURE(FEAT_CMOW, fCmow);
1611 LOG_CPU_FEATURE(FEAT_CONSTPACFIELD, fConstPacField);
1612 LOG_CPU_FEATURE(FEAT_Debugv8p8, fDebugV8p8);
1613 LOG_CPU_FEATURE(FEAT_HBC, fHbc);
1614 LOG_CPU_FEATURE(FEAT_HPMN0, fHpmn0);
1615 LOG_CPU_FEATURE(FEAT_NMI, fNmi);
1616 LOG_CPU_FEATURE(FEAT_GICv3_NMI, fGicV3Nmi);
1617 LOG_CPU_FEATURE(FEAT_MOPS, fMops);
1618 LOG_CPU_FEATURE(FEAT_PACQARMA3, fPacQarma3);
1619 LOG_CPU_FEATURE(FEAT_PMUv3_TH, fPmuV3Th);
1620 LOG_CPU_FEATURE(FEAT_PMUv3p8, fPmuV3p8);
1621 LOG_CPU_FEATURE(FEAT_PMUv3_EXT64, fPmuV3Ext64);
1622 LOG_CPU_FEATURE(FEAT_PMUv3_EXT32, fPmuV3Ext32);
1623 LOG_CPU_FEATURE(FEAT_PMUv3_EXT, fPmuV3Ext);
1624 LOG_CPU_FEATURE(FEAT_RNG_TRAP, fRngTrap);
1625 LOG_CPU_FEATURE(FEAT_SPEv1p3, fSpeV1p3);
1626 LOG_CPU_FEATURE(FEAT_TIDCP1, fTidcp1);
1627 LOG_CPU_FEATURE(FEAT_BRBEv1p1, fBrbeV1p1);
1628
1629 LOG_CPU_FEATURE(FEAT_ABLE, fAble);
1630 LOG_CPU_FEATURE(FEAT_ADERR, fAderr);
1631 LOG_CPU_FEATURE(FEAT_AIE, fAie);
1632 LOG_CPU_FEATURE(FEAT_ANERR, fAnerr);
1633 LOG_CPU_FEATURE(FEAT_BWE, fBwe);
1634 LOG_CPU_FEATURE(FEAT_CLRBHB, fClrBhb);
1635 LOG_CPU_FEATURE(FEAT_CHK, fChk);
1636 LOG_CPU_FEATURE(FEAT_CSSC, fCssc);
1637 LOG_CPU_FEATURE(FEAT_CSV2_3, fCsv2v3);
1638 LOG_CPU_FEATURE(FEAT_D128, fD128);
1639 LOG_CPU_FEATURE(FEAT_Debugv8p9, fDebugV8p9);
1640 LOG_CPU_FEATURE(FEAT_DoubleFault2, fDoubleFault2);
1641 LOG_CPU_FEATURE(FEAT_EBEP, fEbep);
1642 LOG_CPU_FEATURE(FEAT_ECBHB, fEcBhb);
1643 LOG_CPU_FEATURE(FEAT_EDHSR, fEdhsr);
1644 LOG_CPU_FEATURE(FEAT_ETEv1p3, fEteV1p3);
1645 LOG_CPU_FEATURE(FEAT_FGT2, fFgt2);
1646 LOG_CPU_FEATURE(FEAT_GCS, fGcs);
1647 LOG_CPU_FEATURE(FEAT_HAFT, fHaft);
1648 LOG_CPU_FEATURE(FEAT_ITE, fIte);
1649 LOG_CPU_FEATURE(FEAT_LRCPC3, fLrcpc3);
1650 LOG_CPU_FEATURE(FEAT_LSE128, fLse128);
1651 LOG_CPU_FEATURE(FEAT_LVA3, fLva3);
1652 LOG_CPU_FEATURE(FEAT_MEC, fMec);
1653 LOG_CPU_FEATURE(FEAT_MTE4, fMte4);
1654 LOG_CPU_FEATURE(FEAT_MTE_CANONICAL_TAGS, fMteCanonicalTags);
1655 LOG_CPU_FEATURE(FEAT_MTE_TAGGED_FAR, fMteTaggedFar);
1656 LOG_CPU_FEATURE(FEAT_MTE_STORE_ONLY, fMteStoreOnly);
1657 LOG_CPU_FEATURE(FEAT_MTE_NO_ADDRESS_TAGS, fMteNoAddressTags);
1658 LOG_CPU_FEATURE(FEAT_MTE_ASYM_FAULT, fMteAsymFault);
1659 LOG_CPU_FEATURE(FEAT_MTE_ASYNC, fMteAsync);
1660 LOG_CPU_FEATURE(FEAT_MTE_PERM_S1, fMtePermS1);
1661 LOG_CPU_FEATURE(FEAT_PCSRv8p9, fPcsrV8p9);
1662 LOG_CPU_FEATURE(FEAT_S1PIE, fS1Pie);
1663 LOG_CPU_FEATURE(FEAT_S2PIE, fS2Pie);
1664 LOG_CPU_FEATURE(FEAT_S1POE, fS1Poe);
1665 LOG_CPU_FEATURE(FEAT_S2POE, fS2Poe);
1666 LOG_CPU_FEATURE(FEAT_PFAR, fPfar);
1667 LOG_CPU_FEATURE(FEAT_PMUv3p9, fPmuV3p9);
1668 LOG_CPU_FEATURE(FEAT_PMUv3_EDGE, fPmuV3Edge);
1669 LOG_CPU_FEATURE(FEAT_PMUv3_ICNTR, fPmuV3Icntr);
1670 LOG_CPU_FEATURE(FEAT_PMUv3_SS, fPmuV3Ss);
1671 LOG_CPU_FEATURE(FEAT_PRFMSLC, fPrfmSlc);
1672 LOG_CPU_FEATURE(FEAT_RASv2, fRasV2);
1673 LOG_CPU_FEATURE(FEAT_RASSAv2, fRasSaV2);
1674 LOG_CPU_FEATURE(FEAT_RPRFM, fRprfm);
1675 LOG_CPU_FEATURE(FEAT_SCTLR2, fSctlr2);
1676 LOG_CPU_FEATURE(FEAT_SEBEP, fSebep);
1677 LOG_CPU_FEATURE(FEAT_SME_F16F16, fSmeF16F16);
1678 LOG_CPU_FEATURE(FEAT_SME2, fSme2);
1679 LOG_CPU_FEATURE(FEAT_SME2p1, fSme2p1);
1680 LOG_CPU_FEATURE(FEAT_SPECRES2, fSpecres2);
1681 LOG_CPU_FEATURE(FEAT_SPMU, fSpmu);
1682 LOG_CPU_FEATURE(FEAT_SPEv1p4, fSpeV1p4);
1683 LOG_CPU_FEATURE(FEAT_SPE_CRR, fSpeCrr);
1684 LOG_CPU_FEATURE(FEAT_SPE_FDS, fSpeFds);
1685 LOG_CPU_FEATURE(FEAT_SVE2p1, fSve2p1);
1686 LOG_CPU_FEATURE(FEAT_SVE_B16B16, fSveB16B16);
1687 LOG_CPU_FEATURE(FEAT_SYSINSTR128, fSysInstr128);
1688 LOG_CPU_FEATURE(FEAT_SYSREG128, fSysReg128);
1689 LOG_CPU_FEATURE(FEAT_TCR2, fTcr2);
1690 LOG_CPU_FEATURE(FEAT_THE, fThe);
1691 LOG_CPU_FEATURE(FEAT_TRBE_EXT, fTrbeExt);
1692 LOG_CPU_FEATURE(FEAT_TRBE_MPAM, fTrbeMpam);
1693#undef LOG_CPU_FEATURE
1694}
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette