VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp@ 97178

Last change on this file since 97178 was 96407, checked in by vboxsync, 2 years ago

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1/* $Id: CPUMDbg.cpp 96407 2022-08-22 17:43:14Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager, Debugger & Debugging APIs.
4 */
5
6/*
7 * Copyright (C) 2010-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DBGF
33#include <VBox/vmm/cpum.h>
34#include <VBox/vmm/dbgf.h>
35#include <VBox/vmm/apic.h>
36#include "CPUMInternal.h"
37#include <VBox/vmm/vm.h>
38#include <VBox/param.h>
39#include <VBox/err.h>
40#include <VBox/log.h>
41#include <iprt/thread.h>
42#include <iprt/string.h>
43#include <iprt/uint128.h>
44
45
46/**
47 * @interface_method_impl{DBGFREGDESC,pfnGet}
48 */
49static DECLCALLBACK(int) cpumR3RegGet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
50{
51 PVMCPU pVCpu = (PVMCPU)pvUser;
52 void const *pv = (uint8_t const *)&pVCpu->cpum + pDesc->offRegister;
53
54 VMCPU_ASSERT_EMT(pVCpu);
55
56 switch (pDesc->enmType)
57 {
58 case DBGFREGVALTYPE_U8: pValue->u8 = *(uint8_t const *)pv; return VINF_SUCCESS;
59 case DBGFREGVALTYPE_U16: pValue->u16 = *(uint16_t const *)pv; return VINF_SUCCESS;
60 case DBGFREGVALTYPE_U32: pValue->u32 = *(uint32_t const *)pv; return VINF_SUCCESS;
61 case DBGFREGVALTYPE_U64: pValue->u64 = *(uint64_t const *)pv; return VINF_SUCCESS;
62 case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS;
63 case DBGFREGVALTYPE_U256: pValue->u256 = *(PCRTUINT256U )pv; return VINF_SUCCESS;
64 case DBGFREGVALTYPE_U512: pValue->u512 = *(PCRTUINT512U )pv; return VINF_SUCCESS;
65 default:
66 AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
67 }
68}
69
70
71/**
72 * @interface_method_impl{DBGFREGDESC,pfnSet}
73 */
74static DECLCALLBACK(int) cpumR3RegSet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
75{
76 PVMCPU pVCpu = (PVMCPU)pvUser;
77 void *pv = (uint8_t *)&pVCpu->cpum + pDesc->offRegister;
78
79 VMCPU_ASSERT_EMT(pVCpu);
80
81 switch (pDesc->enmType)
82 {
83 case DBGFREGVALTYPE_U8:
84 *(uint8_t *)pv &= ~pfMask->u8;
85 *(uint8_t *)pv |= pValue->u8 & pfMask->u8;
86 return VINF_SUCCESS;
87
88 case DBGFREGVALTYPE_U16:
89 *(uint16_t *)pv &= ~pfMask->u16;
90 *(uint16_t *)pv |= pValue->u16 & pfMask->u16;
91 return VINF_SUCCESS;
92
93 case DBGFREGVALTYPE_U32:
94 *(uint32_t *)pv &= ~pfMask->u32;
95 *(uint32_t *)pv |= pValue->u32 & pfMask->u32;
96 return VINF_SUCCESS;
97
98 case DBGFREGVALTYPE_U64:
99 *(uint64_t *)pv &= ~pfMask->u64;
100 *(uint64_t *)pv |= pValue->u64 & pfMask->u64;
101 return VINF_SUCCESS;
102
103 case DBGFREGVALTYPE_U128:
104 {
105 RTUINT128U Val;
106 RTUInt128AssignAnd((PRTUINT128U)pv, RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u128)));
107 RTUInt128AssignOr((PRTUINT128U)pv, RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
108 return VINF_SUCCESS;
109 }
110
111 default:
112 AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
113 }
114}
115
116
117/**
118 * @interface_method_impl{DBGFREGDESC,pfnGet}
119 */
120static DECLCALLBACK(int) cpumR3RegGet_XStateGeneric(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
121{
122 PVMCPU pVCpu = (PVMCPU)pvUser;
123 void const *pv = (uint8_t const *)&pVCpu->cpum.s.Guest.XState + pDesc->offRegister;
124
125 VMCPU_ASSERT_EMT(pVCpu);
126
127 switch (pDesc->enmType)
128 {
129 case DBGFREGVALTYPE_U8: pValue->u8 = *(uint8_t const *)pv; return VINF_SUCCESS;
130 case DBGFREGVALTYPE_U16: pValue->u16 = *(uint16_t const *)pv; return VINF_SUCCESS;
131 case DBGFREGVALTYPE_U32: pValue->u32 = *(uint32_t const *)pv; return VINF_SUCCESS;
132 case DBGFREGVALTYPE_U64: pValue->u64 = *(uint64_t const *)pv; return VINF_SUCCESS;
133 case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS;
134 default:
135 AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
136 }
137}
138
139
140/**
141 * @interface_method_impl{DBGFREGDESC,pfnSet}
142 */
143static DECLCALLBACK(int) cpumR3RegSet_XStateGeneric(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
144{
145 PVMCPU pVCpu = (PVMCPU)pvUser;
146 void *pv = (uint8_t *)&pVCpu->cpum.s.Guest.XState + pDesc->offRegister;
147
148 VMCPU_ASSERT_EMT(pVCpu);
149
150 switch (pDesc->enmType)
151 {
152 case DBGFREGVALTYPE_U8:
153 *(uint8_t *)pv &= ~pfMask->u8;
154 *(uint8_t *)pv |= pValue->u8 & pfMask->u8;
155 return VINF_SUCCESS;
156
157 case DBGFREGVALTYPE_U16:
158 *(uint16_t *)pv &= ~pfMask->u16;
159 *(uint16_t *)pv |= pValue->u16 & pfMask->u16;
160 return VINF_SUCCESS;
161
162 case DBGFREGVALTYPE_U32:
163 *(uint32_t *)pv &= ~pfMask->u32;
164 *(uint32_t *)pv |= pValue->u32 & pfMask->u32;
165 return VINF_SUCCESS;
166
167 case DBGFREGVALTYPE_U64:
168 *(uint64_t *)pv &= ~pfMask->u64;
169 *(uint64_t *)pv |= pValue->u64 & pfMask->u64;
170 return VINF_SUCCESS;
171
172 case DBGFREGVALTYPE_U128:
173 {
174 RTUINT128U Val;
175 RTUInt128AssignAnd((PRTUINT128U)pv, RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u128)));
176 RTUInt128AssignOr((PRTUINT128U)pv, RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
177 return VINF_SUCCESS;
178 }
179
180 default:
181 AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
182 }
183}
184
185
186
187/**
188 * @interface_method_impl{DBGFREGDESC,pfnGet}
189 */
190static DECLCALLBACK(int) cpumR3RegSet_seg(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
191{
192 /** @todo perform a selector load, updating hidden selectors and stuff. */
193 NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
194 return VERR_NOT_IMPLEMENTED;
195}
196
197
198/**
199 * @interface_method_impl{DBGFREGDESC,pfnGet}
200 */
201static DECLCALLBACK(int) cpumR3RegGet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
202{
203 PVMCPU pVCpu = (PVMCPU)pvUser;
204 VBOXGDTR const *pGdtr = (VBOXGDTR const *)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
205
206 VMCPU_ASSERT_EMT(pVCpu);
207 Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
208
209 pValue->dtr.u32Limit = pGdtr->cbGdt;
210 pValue->dtr.u64Base = pGdtr->pGdt;
211 return VINF_SUCCESS;
212}
213
214
215/**
216 * @interface_method_impl{DBGFREGDESC,pfnGet}
217 */
218static DECLCALLBACK(int) cpumR3RegSet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
219{
220 RT_NOREF(pfMask);
221
222 PVMCPU pVCpu = (PVMCPU)pvUser;
223 VBOXGDTR *pGdtr = (VBOXGDTR *)((uint8_t *)&pVCpu->cpum + pDesc->offRegister);
224
225 VMCPU_ASSERT_EMT(pVCpu);
226 Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
227
228 pGdtr->cbGdt = pValue->dtr.u32Limit;
229 pGdtr->pGdt = pValue->dtr.u64Base;
230 return VINF_SUCCESS;
231}
232
233
234/**
235 * @interface_method_impl{DBGFREGDESC,pfnGet}
236 */
237static DECLCALLBACK(int) cpumR3RegGet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
238{
239 PVMCPU pVCpu = (PVMCPU)pvUser;
240 VBOXIDTR const *pIdtr = (VBOXIDTR const *)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
241
242 VMCPU_ASSERT_EMT(pVCpu);
243 Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
244
245 pValue->dtr.u32Limit = pIdtr->cbIdt;
246 pValue->dtr.u64Base = pIdtr->pIdt;
247 return VINF_SUCCESS;
248}
249
250
251/**
252 * @interface_method_impl{DBGFREGDESC,pfnGet}
253 */
254static DECLCALLBACK(int) cpumR3RegSet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
255{
256 RT_NOREF(pfMask);
257
258 PVMCPU pVCpu = (PVMCPU)pvUser;
259 VBOXIDTR *pIdtr = (VBOXIDTR *)((uint8_t *)&pVCpu->cpum + pDesc->offRegister);
260
261 VMCPU_ASSERT_EMT(pVCpu);
262 Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
263
264 pIdtr->cbIdt = pValue->dtr.u32Limit;
265 pIdtr->pIdt = pValue->dtr.u64Base;
266 return VINF_SUCCESS;
267}
268
269
270/**
271 * Determins the tag register value for a CPU register when the FPU state
272 * format is FXSAVE.
273 *
274 * @returns The tag register value.
275 * @param pFpu Pointer to the guest FPU.
276 * @param iReg The register number (0..7).
277 */
278DECLINLINE(uint16_t) cpumR3RegCalcFpuTagFromFxSave(PCX86FXSTATE pFpu, unsigned iReg)
279{
280 /*
281 * See table 11-1 in the AMD docs.
282 */
283 if (!(pFpu->FTW & RT_BIT_32(iReg)))
284 return 3; /* b11 - empty */
285
286 uint16_t const uExp = pFpu->aRegs[iReg].au16[4];
287 if (uExp == 0)
288 {
289 if (pFpu->aRegs[iReg].au64[0] == 0) /* J & M == 0 */
290 return 1; /* b01 - zero */
291 return 2; /* b10 - special */
292 }
293
294 if (uExp == UINT16_C(0xffff))
295 return 2; /* b10 - special */
296
297 if (!(pFpu->aRegs[iReg].au64[0] >> 63)) /* J == 0 */
298 return 2; /* b10 - special */
299
300 return 0; /* b00 - valid (normal) */
301}
302
303
304/**
305 * @interface_method_impl{DBGFREGDESC,pfnGet}
306 */
307static DECLCALLBACK(int) cpumR3RegGet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
308{
309 PVMCPU pVCpu = (PVMCPU)pvUser;
310 PCX86FXSTATE pFpu = (PCX86FXSTATE)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
311
312 VMCPU_ASSERT_EMT(pVCpu);
313 Assert(pDesc->enmType == DBGFREGVALTYPE_U16);
314
315 pValue->u16 = cpumR3RegCalcFpuTagFromFxSave(pFpu, 0)
316 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 1) << 2)
317 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 2) << 4)
318 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 3) << 6)
319 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 4) << 8)
320 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 5) << 10)
321 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 6) << 12)
322 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 7) << 14);
323 return VINF_SUCCESS;
324}
325
326
327/**
328 * @interface_method_impl{DBGFREGDESC,pfnGet}
329 */
330static DECLCALLBACK(int) cpumR3RegSet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
331{
332 NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
333 return VERR_DBGF_READ_ONLY_REGISTER;
334}
335
336#if 0 /* unused */
337
338/**
339 * @interface_method_impl{DBGFREGDESC,pfnGet}
340 */
341static DECLCALLBACK(int) cpumR3RegGet_Dummy(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
342{
343 RT_NOREF_PV(pvUser);
344 switch (pDesc->enmType)
345 {
346 case DBGFREGVALTYPE_U8: pValue->u8 = 0; return VINF_SUCCESS;
347 case DBGFREGVALTYPE_U16: pValue->u16 = 0; return VINF_SUCCESS;
348 case DBGFREGVALTYPE_U32: pValue->u32 = 0; return VINF_SUCCESS;
349 case DBGFREGVALTYPE_U64: pValue->u64 = 0; return VINF_SUCCESS;
350 case DBGFREGVALTYPE_U128:
351 RT_ZERO(pValue->u128);
352 return VINF_SUCCESS;
353 case DBGFREGVALTYPE_DTR:
354 pValue->dtr.u32Limit = 0;
355 pValue->dtr.u64Base = 0;
356 return VINF_SUCCESS;
357 case DBGFREGVALTYPE_R80:
358 RT_ZERO(pValue->r80Ex);
359 return VINF_SUCCESS;
360 default:
361 AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
362 }
363}
364
365
366/**
367 * @interface_method_impl{DBGFREGDESC,pfnSet}
368 */
369static DECLCALLBACK(int) cpumR3RegSet_Dummy(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
370{
371 NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
372 return VERR_DBGF_READ_ONLY_REGISTER;
373}
374
375#endif /* unused */
376
377/**
378 * @interface_method_impl{DBGFREGDESC,pfnGet}
379 */
380static DECLCALLBACK(int) cpumR3RegGet_ymm(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
381{
382 PVMCPU pVCpu = (PVMCPU)pvUser;
383 uint32_t iReg = pDesc->offRegister;
384
385 Assert(pDesc->enmType == DBGFREGVALTYPE_U256);
386 VMCPU_ASSERT_EMT(pVCpu);
387
388 if (iReg < 16)
389 {
390 pValue->u256.DQWords.dqw0 = pVCpu->cpum.s.Guest.XState.x87.aXMM[iReg].uXmm;
391 pValue->u256.DQWords.dqw1 = pVCpu->cpum.s.Guest.XState.u.YmmHi.aYmmHi[iReg].uXmm;
392 return VINF_SUCCESS;
393 }
394 return VERR_NOT_IMPLEMENTED;
395}
396
397
398/**
399 * @interface_method_impl{DBGFREGDESC,pfnSet}
400 */
401static DECLCALLBACK(int) cpumR3RegSet_ymm(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
402{
403 PVMCPU pVCpu = (PVMCPU)pvUser;
404 uint32_t iReg = pDesc->offRegister;
405
406 Assert(pDesc->enmType == DBGFREGVALTYPE_U256);
407 VMCPU_ASSERT_EMT(pVCpu);
408
409 if (iReg < 16)
410 {
411 RTUINT128U Val;
412 RTUInt128AssignAnd(&pVCpu->cpum.s.Guest.XState.x87.aXMM[iReg].uXmm,
413 RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u256.DQWords.dqw0)));
414 RTUInt128AssignOr(&pVCpu->cpum.s.Guest.XState.u.YmmHi.aYmmHi[iReg].uXmm,
415 RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
416
417 }
418 return VERR_NOT_IMPLEMENTED;
419}
420
421
422/*
423 *
424 * Guest register access functions.
425 *
426 */
427
428/**
429 * @interface_method_impl{DBGFREGDESC,pfnGet}
430 */
431static DECLCALLBACK(int) cpumR3RegGstGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
432{
433 PVMCPU pVCpu = (PVMCPU)pvUser;
434 VMCPU_ASSERT_EMT(pVCpu);
435
436 uint64_t u64Value;
437 int rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64Value);
438 if (rc == VERR_PDM_NO_APIC_INSTANCE) /* CR8 might not be available, see @bugref{8868}.*/
439 u64Value = 0;
440 else
441 AssertRCReturn(rc, rc);
442 switch (pDesc->enmType)
443 {
444 case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
445 case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
446 default:
447 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
448 }
449 return VINF_SUCCESS;
450}
451
452
453/**
454 * @interface_method_impl{DBGFREGDESC,pfnGet}
455 */
456static DECLCALLBACK(int) cpumR3RegGstSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
457{
458 int rc;
459 PVMCPU pVCpu = (PVMCPU)pvUser;
460
461 VMCPU_ASSERT_EMT(pVCpu);
462
463 /*
464 * Calculate the new value.
465 */
466 uint64_t u64Value;
467 uint64_t fMask;
468 uint64_t fMaskMax;
469 switch (pDesc->enmType)
470 {
471 case DBGFREGVALTYPE_U64:
472 u64Value = pValue->u64;
473 fMask = pfMask->u64;
474 fMaskMax = UINT64_MAX;
475 break;
476 case DBGFREGVALTYPE_U32:
477 u64Value = pValue->u32;
478 fMask = pfMask->u32;
479 fMaskMax = UINT32_MAX;
480 break;
481 default:
482 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
483 }
484 if (fMask != fMaskMax)
485 {
486 uint64_t u64FullValue;
487 rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64FullValue);
488 if (RT_FAILURE(rc))
489 return rc;
490 u64Value = (u64FullValue & ~fMask)
491 | (u64Value & fMask);
492 }
493
494 /*
495 * Perform the assignment.
496 */
497 switch (pDesc->offRegister)
498 {
499 case 0: rc = CPUMSetGuestCR0(pVCpu, u64Value); break;
500 case 2: rc = CPUMSetGuestCR2(pVCpu, u64Value); break;
501 case 3: rc = CPUMSetGuestCR3(pVCpu, u64Value); break;
502 case 4: rc = CPUMSetGuestCR4(pVCpu, u64Value); break;
503 case 8: rc = APICSetTpr(pVCpu, (uint8_t)(u64Value << 4)); break;
504 default:
505 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
506 }
507 return rc;
508}
509
510
511/**
512 * @interface_method_impl{DBGFREGDESC,pfnGet}
513 */
514static DECLCALLBACK(int) cpumR3RegGstGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
515{
516 PVMCPU pVCpu = (PVMCPU)pvUser;
517 VMCPU_ASSERT_EMT(pVCpu);
518
519 uint64_t u64Value;
520 int rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64Value);
521 AssertRCReturn(rc, rc);
522 switch (pDesc->enmType)
523 {
524 case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
525 case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
526 default:
527 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
528 }
529 return VINF_SUCCESS;
530}
531
532
533/**
534 * @interface_method_impl{DBGFREGDESC,pfnGet}
535 */
536static DECLCALLBACK(int) cpumR3RegGstSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
537{
538 int rc;
539 PVMCPU pVCpu = (PVMCPU)pvUser;
540
541 VMCPU_ASSERT_EMT(pVCpu);
542
543 /*
544 * Calculate the new value.
545 */
546 uint64_t u64Value;
547 uint64_t fMask;
548 uint64_t fMaskMax;
549 switch (pDesc->enmType)
550 {
551 case DBGFREGVALTYPE_U64:
552 u64Value = pValue->u64;
553 fMask = pfMask->u64;
554 fMaskMax = UINT64_MAX;
555 break;
556 case DBGFREGVALTYPE_U32:
557 u64Value = pValue->u32;
558 fMask = pfMask->u32;
559 fMaskMax = UINT32_MAX;
560 break;
561 default:
562 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
563 }
564 if (fMask != fMaskMax)
565 {
566 uint64_t u64FullValue;
567 rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64FullValue);
568 if (RT_FAILURE(rc))
569 return rc;
570 u64Value = (u64FullValue & ~fMask)
571 | (u64Value & fMask);
572 }
573
574 /*
575 * Perform the assignment.
576 */
577 return CPUMSetGuestDRx(pVCpu, pDesc->offRegister, u64Value);
578}
579
580
581/**
582 * @interface_method_impl{DBGFREGDESC,pfnGet}
583 */
584static DECLCALLBACK(int) cpumR3RegGstGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
585{
586 PVMCPU pVCpu = (PVMCPU)pvUser;
587 VMCPU_ASSERT_EMT(pVCpu);
588
589 uint64_t u64Value;
590 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64Value);
591 if (rcStrict == VINF_SUCCESS)
592 {
593 switch (pDesc->enmType)
594 {
595 case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
596 case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
597 case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break;
598 default:
599 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
600 }
601 return VBOXSTRICTRC_VAL(rcStrict);
602 }
603
604 /** @todo what to do about errors? */
605 Assert(RT_FAILURE_NP(rcStrict));
606 return VBOXSTRICTRC_VAL(rcStrict);
607}
608
609
610/**
611 * @interface_method_impl{DBGFREGDESC,pfnGet}
612 */
613static DECLCALLBACK(int) cpumR3RegGstSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
614{
615 PVMCPU pVCpu = (PVMCPU)pvUser;
616
617 VMCPU_ASSERT_EMT(pVCpu);
618
619 /*
620 * Calculate the new value.
621 */
622 uint64_t u64Value;
623 uint64_t fMask;
624 uint64_t fMaskMax;
625 switch (pDesc->enmType)
626 {
627 case DBGFREGVALTYPE_U64:
628 u64Value = pValue->u64;
629 fMask = pfMask->u64;
630 fMaskMax = UINT64_MAX;
631 break;
632 case DBGFREGVALTYPE_U32:
633 u64Value = pValue->u32;
634 fMask = pfMask->u32;
635 fMaskMax = UINT32_MAX;
636 break;
637 case DBGFREGVALTYPE_U16:
638 u64Value = pValue->u16;
639 fMask = pfMask->u16;
640 fMaskMax = UINT16_MAX;
641 break;
642 default:
643 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
644 }
645 if (fMask != fMaskMax)
646 {
647 uint64_t u64FullValue;
648 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64FullValue);
649 if (rcStrict != VINF_SUCCESS)
650 {
651 AssertRC(RT_FAILURE_NP(rcStrict));
652 return VBOXSTRICTRC_VAL(rcStrict);
653 }
654 u64Value = (u64FullValue & ~fMask)
655 | (u64Value & fMask);
656 }
657
658 /*
659 * Perform the assignment.
660 */
661 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pDesc->offRegister, u64Value);
662 if (rcStrict == VINF_SUCCESS)
663 return VINF_SUCCESS;
664 AssertRC(RT_FAILURE_NP(rcStrict));
665 return VBOXSTRICTRC_VAL(rcStrict);
666}
667
668
669/**
670 * @interface_method_impl{DBGFREGDESC,pfnGet}
671 */
672static DECLCALLBACK(int) cpumR3RegGstGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
673{
674 PVMCPU pVCpu = (PVMCPU)pvUser;
675 VMCPU_ASSERT_EMT(pVCpu);
676 Assert(pDesc->enmType == DBGFREGVALTYPE_R80);
677
678 PX86FXSTATE pFpuCtx = &pVCpu->cpum.s.Guest.XState.x87;
679 unsigned iReg = (pFpuCtx->FSW >> 11) & 7;
680 iReg += pDesc->offRegister;
681 iReg &= 7;
682 pValue->r80Ex = pFpuCtx->aRegs[iReg].r80Ex;
683
684 return VINF_SUCCESS;
685}
686
687
688/**
689 * @interface_method_impl{DBGFREGDESC,pfnGet}
690 */
691static DECLCALLBACK(int) cpumR3RegGstSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
692{
693 NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
694 return VERR_NOT_IMPLEMENTED;
695}
696
697
698
699/*
700 * Set up aliases.
701 */
702#define CPUMREGALIAS_STD(Name, psz32, psz16, psz8) \
703 static DBGFREGALIAS const g_aCpumRegAliases_##Name[] = \
704 { \
705 { psz32, DBGFREGVALTYPE_U32 }, \
706 { psz16, DBGFREGVALTYPE_U16 }, \
707 { psz8, DBGFREGVALTYPE_U8 }, \
708 { NULL, DBGFREGVALTYPE_INVALID } \
709 }
710CPUMREGALIAS_STD(rax, "eax", "ax", "al");
711CPUMREGALIAS_STD(rcx, "ecx", "cx", "cl");
712CPUMREGALIAS_STD(rdx, "edx", "dx", "dl");
713CPUMREGALIAS_STD(rbx, "ebx", "bx", "bl");
714CPUMREGALIAS_STD(rsp, "esp", "sp", NULL);
715CPUMREGALIAS_STD(rbp, "ebp", "bp", NULL);
716CPUMREGALIAS_STD(rsi, "esi", "si", "sil");
717CPUMREGALIAS_STD(rdi, "edi", "di", "dil");
718CPUMREGALIAS_STD(r8, "r8d", "r8w", "r8b");
719CPUMREGALIAS_STD(r9, "r9d", "r9w", "r9b");
720CPUMREGALIAS_STD(r10, "r10d", "r10w", "r10b");
721CPUMREGALIAS_STD(r11, "r11d", "r11w", "r11b");
722CPUMREGALIAS_STD(r12, "r12d", "r12w", "r12b");
723CPUMREGALIAS_STD(r13, "r13d", "r13w", "r13b");
724CPUMREGALIAS_STD(r14, "r14d", "r14w", "r14b");
725CPUMREGALIAS_STD(r15, "r15d", "r15w", "r15b");
726CPUMREGALIAS_STD(rip, "eip", "ip", NULL);
727CPUMREGALIAS_STD(rflags, "eflags", "flags", NULL);
728#undef CPUMREGALIAS_STD
729
730static DBGFREGALIAS const g_aCpumRegAliases_fpuip[] =
731{
732 { "fpuip16", DBGFREGVALTYPE_U16 },
733 { NULL, DBGFREGVALTYPE_INVALID }
734};
735
736static DBGFREGALIAS const g_aCpumRegAliases_fpudp[] =
737{
738 { "fpudp16", DBGFREGVALTYPE_U16 },
739 { NULL, DBGFREGVALTYPE_INVALID }
740};
741
742static DBGFREGALIAS const g_aCpumRegAliases_cr0[] =
743{
744 { "msw", DBGFREGVALTYPE_U16 },
745 { NULL, DBGFREGVALTYPE_INVALID }
746};
747
748/*
749 * Sub fields.
750 */
751/** Sub-fields for the (hidden) segment attribute register. */
752static DBGFREGSUBFIELD const g_aCpumRegFields_seg[] =
753{
754 DBGFREGSUBFIELD_RW("type", 0, 4, 0),
755 DBGFREGSUBFIELD_RW("s", 4, 1, 0),
756 DBGFREGSUBFIELD_RW("dpl", 5, 2, 0),
757 DBGFREGSUBFIELD_RW("p", 7, 1, 0),
758 DBGFREGSUBFIELD_RW("avl", 12, 1, 0),
759 DBGFREGSUBFIELD_RW("l", 13, 1, 0),
760 DBGFREGSUBFIELD_RW("d", 14, 1, 0),
761 DBGFREGSUBFIELD_RW("g", 15, 1, 0),
762 DBGFREGSUBFIELD_TERMINATOR()
763};
764
765/** Sub-fields for the flags register. */
766static DBGFREGSUBFIELD const g_aCpumRegFields_rflags[] =
767{
768 DBGFREGSUBFIELD_RW("cf", 0, 1, 0),
769 DBGFREGSUBFIELD_RW("pf", 2, 1, 0),
770 DBGFREGSUBFIELD_RW("af", 4, 1, 0),
771 DBGFREGSUBFIELD_RW("zf", 6, 1, 0),
772 DBGFREGSUBFIELD_RW("sf", 7, 1, 0),
773 DBGFREGSUBFIELD_RW("tf", 8, 1, 0),
774 DBGFREGSUBFIELD_RW("if", 9, 1, 0),
775 DBGFREGSUBFIELD_RW("df", 10, 1, 0),
776 DBGFREGSUBFIELD_RW("of", 11, 1, 0),
777 DBGFREGSUBFIELD_RW("iopl", 12, 2, 0),
778 DBGFREGSUBFIELD_RW("nt", 14, 1, 0),
779 DBGFREGSUBFIELD_RW("rf", 16, 1, 0),
780 DBGFREGSUBFIELD_RW("vm", 17, 1, 0),
781 DBGFREGSUBFIELD_RW("ac", 18, 1, 0),
782 DBGFREGSUBFIELD_RW("vif", 19, 1, 0),
783 DBGFREGSUBFIELD_RW("vip", 20, 1, 0),
784 DBGFREGSUBFIELD_RW("id", 21, 1, 0),
785 DBGFREGSUBFIELD_TERMINATOR()
786};
787
788/** Sub-fields for the FPU control word register. */
789static DBGFREGSUBFIELD const g_aCpumRegFields_fcw[] =
790{
791 DBGFREGSUBFIELD_RW("im", 1, 1, 0),
792 DBGFREGSUBFIELD_RW("dm", 2, 1, 0),
793 DBGFREGSUBFIELD_RW("zm", 3, 1, 0),
794 DBGFREGSUBFIELD_RW("om", 4, 1, 0),
795 DBGFREGSUBFIELD_RW("um", 5, 1, 0),
796 DBGFREGSUBFIELD_RW("pm", 6, 1, 0),
797 DBGFREGSUBFIELD_RW("pc", 8, 2, 0),
798 DBGFREGSUBFIELD_RW("rc", 10, 2, 0),
799 DBGFREGSUBFIELD_RW("x", 12, 1, 0),
800 DBGFREGSUBFIELD_TERMINATOR()
801};
802
803/** Sub-fields for the FPU status word register. */
804static DBGFREGSUBFIELD const g_aCpumRegFields_fsw[] =
805{
806 DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
807 DBGFREGSUBFIELD_RW("de", 1, 1, 0),
808 DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
809 DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
810 DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
811 DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
812 DBGFREGSUBFIELD_RW("se", 6, 1, 0),
813 DBGFREGSUBFIELD_RW("es", 7, 1, 0),
814 DBGFREGSUBFIELD_RW("c0", 8, 1, 0),
815 DBGFREGSUBFIELD_RW("c1", 9, 1, 0),
816 DBGFREGSUBFIELD_RW("c2", 10, 1, 0),
817 DBGFREGSUBFIELD_RW("top", 11, 3, 0),
818 DBGFREGSUBFIELD_RW("c3", 14, 1, 0),
819 DBGFREGSUBFIELD_RW("b", 15, 1, 0),
820 DBGFREGSUBFIELD_TERMINATOR()
821};
822
823/** Sub-fields for the FPU tag word register. */
824static DBGFREGSUBFIELD const g_aCpumRegFields_ftw[] =
825{
826 DBGFREGSUBFIELD_RW("tag0", 0, 2, 0),
827 DBGFREGSUBFIELD_RW("tag1", 2, 2, 0),
828 DBGFREGSUBFIELD_RW("tag2", 4, 2, 0),
829 DBGFREGSUBFIELD_RW("tag3", 6, 2, 0),
830 DBGFREGSUBFIELD_RW("tag4", 8, 2, 0),
831 DBGFREGSUBFIELD_RW("tag5", 10, 2, 0),
832 DBGFREGSUBFIELD_RW("tag6", 12, 2, 0),
833 DBGFREGSUBFIELD_RW("tag7", 14, 2, 0),
834 DBGFREGSUBFIELD_TERMINATOR()
835};
836
837/** Sub-fields for the Multimedia Extensions Control and Status Register. */
838static DBGFREGSUBFIELD const g_aCpumRegFields_mxcsr[] =
839{
840 DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
841 DBGFREGSUBFIELD_RW("de", 1, 1, 0),
842 DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
843 DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
844 DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
845 DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
846 DBGFREGSUBFIELD_RW("daz", 6, 1, 0),
847 DBGFREGSUBFIELD_RW("im", 7, 1, 0),
848 DBGFREGSUBFIELD_RW("dm", 8, 1, 0),
849 DBGFREGSUBFIELD_RW("zm", 9, 1, 0),
850 DBGFREGSUBFIELD_RW("om", 10, 1, 0),
851 DBGFREGSUBFIELD_RW("um", 11, 1, 0),
852 DBGFREGSUBFIELD_RW("pm", 12, 1, 0),
853 DBGFREGSUBFIELD_RW("rc", 13, 2, 0),
854 DBGFREGSUBFIELD_RW("fz", 14, 1, 0),
855 DBGFREGSUBFIELD_TERMINATOR()
856};
857
858/** Sub-fields for the FPU tag word register. */
859static DBGFREGSUBFIELD const g_aCpumRegFields_stN[] =
860{
861 DBGFREGSUBFIELD_RW("man", 0, 64, 0),
862 DBGFREGSUBFIELD_RW("exp", 64, 15, 0),
863 DBGFREGSUBFIELD_RW("sig", 79, 1, 0),
864 DBGFREGSUBFIELD_TERMINATOR()
865};
866
867/** Sub-fields for the MMX registers. */
868static DBGFREGSUBFIELD const g_aCpumRegFields_mmN[] =
869{
870 DBGFREGSUBFIELD_RW("dw0", 0, 32, 0),
871 DBGFREGSUBFIELD_RW("dw1", 32, 32, 0),
872 DBGFREGSUBFIELD_RW("w0", 0, 16, 0),
873 DBGFREGSUBFIELD_RW("w1", 16, 16, 0),
874 DBGFREGSUBFIELD_RW("w2", 32, 16, 0),
875 DBGFREGSUBFIELD_RW("w3", 48, 16, 0),
876 DBGFREGSUBFIELD_RW("b0", 0, 8, 0),
877 DBGFREGSUBFIELD_RW("b1", 8, 8, 0),
878 DBGFREGSUBFIELD_RW("b2", 16, 8, 0),
879 DBGFREGSUBFIELD_RW("b3", 24, 8, 0),
880 DBGFREGSUBFIELD_RW("b4", 32, 8, 0),
881 DBGFREGSUBFIELD_RW("b5", 40, 8, 0),
882 DBGFREGSUBFIELD_RW("b6", 48, 8, 0),
883 DBGFREGSUBFIELD_RW("b7", 56, 8, 0),
884 DBGFREGSUBFIELD_TERMINATOR()
885};
886
887/** Sub-fields for the XMM registers. */
888static DBGFREGSUBFIELD const g_aCpumRegFields_xmmN[] =
889{
890 DBGFREGSUBFIELD_RW("r0", 0, 32, 0),
891 DBGFREGSUBFIELD_RW("r0.man", 0+ 0, 23, 0),
892 DBGFREGSUBFIELD_RW("r0.exp", 0+23, 8, 0),
893 DBGFREGSUBFIELD_RW("r0.sig", 0+31, 1, 0),
894 DBGFREGSUBFIELD_RW("r1", 32, 32, 0),
895 DBGFREGSUBFIELD_RW("r1.man", 32+ 0, 23, 0),
896 DBGFREGSUBFIELD_RW("r1.exp", 32+23, 8, 0),
897 DBGFREGSUBFIELD_RW("r1.sig", 32+31, 1, 0),
898 DBGFREGSUBFIELD_RW("r2", 64, 32, 0),
899 DBGFREGSUBFIELD_RW("r2.man", 64+ 0, 23, 0),
900 DBGFREGSUBFIELD_RW("r2.exp", 64+23, 8, 0),
901 DBGFREGSUBFIELD_RW("r2.sig", 64+31, 1, 0),
902 DBGFREGSUBFIELD_RW("r3", 96, 32, 0),
903 DBGFREGSUBFIELD_RW("r3.man", 96+ 0, 23, 0),
904 DBGFREGSUBFIELD_RW("r3.exp", 96+23, 8, 0),
905 DBGFREGSUBFIELD_RW("r3.sig", 96+31, 1, 0),
906 DBGFREGSUBFIELD_TERMINATOR()
907};
908
909#if 0 /* needs special accessor, too lazy for that now. */
910/** Sub-fields for the YMM registers. */
911static DBGFREGSUBFIELD const g_aCpumRegFields_ymmN[] =
912{
913 DBGFREGSUBFIELD_RW("r0", 0, 32, 0),
914 DBGFREGSUBFIELD_RW("r0.man", 0+ 0, 23, 0),
915 DBGFREGSUBFIELD_RW("r0.exp", 0+23, 8, 0),
916 DBGFREGSUBFIELD_RW("r0.sig", 0+31, 1, 0),
917 DBGFREGSUBFIELD_RW("r1", 32, 32, 0),
918 DBGFREGSUBFIELD_RW("r1.man", 32+ 0, 23, 0),
919 DBGFREGSUBFIELD_RW("r1.exp", 32+23, 8, 0),
920 DBGFREGSUBFIELD_RW("r1.sig", 32+31, 1, 0),
921 DBGFREGSUBFIELD_RW("r2", 64, 32, 0),
922 DBGFREGSUBFIELD_RW("r2.man", 64+ 0, 23, 0),
923 DBGFREGSUBFIELD_RW("r2.exp", 64+23, 8, 0),
924 DBGFREGSUBFIELD_RW("r2.sig", 64+31, 1, 0),
925 DBGFREGSUBFIELD_RW("r3", 96, 32, 0),
926 DBGFREGSUBFIELD_RW("r3.man", 96+ 0, 23, 0),
927 DBGFREGSUBFIELD_RW("r3.exp", 96+23, 8, 0),
928 DBGFREGSUBFIELD_RW("r3.sig", 96+31, 1, 0),
929 DBGFREGSUBFIELD_RW("r4", 128, 32, 0),
930 DBGFREGSUBFIELD_RW("r4.man", 128+ 0, 23, 0),
931 DBGFREGSUBFIELD_RW("r4.exp", 128+23, 8, 0),
932 DBGFREGSUBFIELD_RW("r4.sig", 128+31, 1, 0),
933 DBGFREGSUBFIELD_RW("r5", 160, 32, 0),
934 DBGFREGSUBFIELD_RW("r5.man", 160+ 0, 23, 0),
935 DBGFREGSUBFIELD_RW("r5.exp", 160+23, 8, 0),
936 DBGFREGSUBFIELD_RW("r5.sig", 160+31, 1, 0),
937 DBGFREGSUBFIELD_RW("r6", 192, 32, 0),
938 DBGFREGSUBFIELD_RW("r6.man", 192+ 0, 23, 0),
939 DBGFREGSUBFIELD_RW("r6.exp", 192+23, 8, 0),
940 DBGFREGSUBFIELD_RW("r6.sig", 192+31, 1, 0),
941 DBGFREGSUBFIELD_RW("r7", 224, 32, 0),
942 DBGFREGSUBFIELD_RW("r7.man", 224+ 0, 23, 0),
943 DBGFREGSUBFIELD_RW("r7.exp", 224+23, 8, 0),
944 DBGFREGSUBFIELD_RW("r7.sig", 224+31, 1, 0),
945 DBGFREGSUBFIELD_TERMINATOR()
946};
947#endif
948
949/** Sub-fields for the CR0 register. */
950static DBGFREGSUBFIELD const g_aCpumRegFields_cr0[] =
951{
952 DBGFREGSUBFIELD_RW("pe", 0, 1, 0),
953 DBGFREGSUBFIELD_RW("mp", 1, 1, 0),
954 DBGFREGSUBFIELD_RW("em", 2, 1, 0),
955 DBGFREGSUBFIELD_RW("ts", 3, 1, 0),
956 DBGFREGSUBFIELD_RO("et", 4, 1, 0),
957 DBGFREGSUBFIELD_RW("ne", 5, 1, 0),
958 DBGFREGSUBFIELD_RW("wp", 16, 1, 0),
959 DBGFREGSUBFIELD_RW("am", 18, 1, 0),
960 DBGFREGSUBFIELD_RW("nw", 29, 1, 0),
961 DBGFREGSUBFIELD_RW("cd", 30, 1, 0),
962 DBGFREGSUBFIELD_RW("pg", 31, 1, 0),
963 DBGFREGSUBFIELD_TERMINATOR()
964};
965
966/** Sub-fields for the CR3 register. */
967static DBGFREGSUBFIELD const g_aCpumRegFields_cr3[] =
968{
969 DBGFREGSUBFIELD_RW("pwt", 3, 1, 0),
970 DBGFREGSUBFIELD_RW("pcd", 4, 1, 0),
971 DBGFREGSUBFIELD_TERMINATOR()
972};
973
974/** Sub-fields for the CR4 register. */
975static DBGFREGSUBFIELD const g_aCpumRegFields_cr4[] =
976{
977 DBGFREGSUBFIELD_RW("vme", 0, 1, 0),
978 DBGFREGSUBFIELD_RW("pvi", 1, 1, 0),
979 DBGFREGSUBFIELD_RW("tsd", 2, 1, 0),
980 DBGFREGSUBFIELD_RW("de", 3, 1, 0),
981 DBGFREGSUBFIELD_RW("pse", 4, 1, 0),
982 DBGFREGSUBFIELD_RW("pae", 5, 1, 0),
983 DBGFREGSUBFIELD_RW("mce", 6, 1, 0),
984 DBGFREGSUBFIELD_RW("pge", 7, 1, 0),
985 DBGFREGSUBFIELD_RW("pce", 8, 1, 0),
986 DBGFREGSUBFIELD_RW("osfxsr", 9, 1, 0),
987 DBGFREGSUBFIELD_RW("osxmmeexcpt", 10, 1, 0),
988 DBGFREGSUBFIELD_RW("vmxe", 13, 1, 0),
989 DBGFREGSUBFIELD_RW("smxe", 14, 1, 0),
990 DBGFREGSUBFIELD_RW("pcide", 17, 1, 0),
991 DBGFREGSUBFIELD_RW("osxsave", 18, 1, 0),
992 DBGFREGSUBFIELD_RW("smep", 20, 1, 0),
993 DBGFREGSUBFIELD_RW("smap", 21, 1, 0),
994 DBGFREGSUBFIELD_TERMINATOR()
995};
996
997/** Sub-fields for the DR6 register. */
998static DBGFREGSUBFIELD const g_aCpumRegFields_dr6[] =
999{
1000 DBGFREGSUBFIELD_RW("b0", 0, 1, 0),
1001 DBGFREGSUBFIELD_RW("b1", 1, 1, 0),
1002 DBGFREGSUBFIELD_RW("b2", 2, 1, 0),
1003 DBGFREGSUBFIELD_RW("b3", 3, 1, 0),
1004 DBGFREGSUBFIELD_RW("bd", 13, 1, 0),
1005 DBGFREGSUBFIELD_RW("bs", 14, 1, 0),
1006 DBGFREGSUBFIELD_RW("bt", 15, 1, 0),
1007 DBGFREGSUBFIELD_TERMINATOR()
1008};
1009
1010/** Sub-fields for the DR7 register. */
1011static DBGFREGSUBFIELD const g_aCpumRegFields_dr7[] =
1012{
1013 DBGFREGSUBFIELD_RW("l0", 0, 1, 0),
1014 DBGFREGSUBFIELD_RW("g0", 1, 1, 0),
1015 DBGFREGSUBFIELD_RW("l1", 2, 1, 0),
1016 DBGFREGSUBFIELD_RW("g1", 3, 1, 0),
1017 DBGFREGSUBFIELD_RW("l2", 4, 1, 0),
1018 DBGFREGSUBFIELD_RW("g2", 5, 1, 0),
1019 DBGFREGSUBFIELD_RW("l3", 6, 1, 0),
1020 DBGFREGSUBFIELD_RW("g3", 7, 1, 0),
1021 DBGFREGSUBFIELD_RW("le", 8, 1, 0),
1022 DBGFREGSUBFIELD_RW("ge", 9, 1, 0),
1023 DBGFREGSUBFIELD_RW("gd", 13, 1, 0),
1024 DBGFREGSUBFIELD_RW("rw0", 16, 2, 0),
1025 DBGFREGSUBFIELD_RW("len0", 18, 2, 0),
1026 DBGFREGSUBFIELD_RW("rw1", 20, 2, 0),
1027 DBGFREGSUBFIELD_RW("len1", 22, 2, 0),
1028 DBGFREGSUBFIELD_RW("rw2", 24, 2, 0),
1029 DBGFREGSUBFIELD_RW("len2", 26, 2, 0),
1030 DBGFREGSUBFIELD_RW("rw3", 28, 2, 0),
1031 DBGFREGSUBFIELD_RW("len3", 30, 2, 0),
1032 DBGFREGSUBFIELD_TERMINATOR()
1033};
1034
1035/** Sub-fields for the CR_PAT MSR. */
1036static DBGFREGSUBFIELD const g_aCpumRegFields_apic_base[] =
1037{
1038 DBGFREGSUBFIELD_RW("bsp", 8, 1, 0),
1039 DBGFREGSUBFIELD_RW("ge", 9, 1, 0),
1040 DBGFREGSUBFIELD_RW("base", 12, 20, 12),
1041 DBGFREGSUBFIELD_TERMINATOR()
1042};
1043
1044/** Sub-fields for the CR_PAT MSR. */
1045static DBGFREGSUBFIELD const g_aCpumRegFields_cr_pat[] =
1046{
1047 /** @todo */
1048 DBGFREGSUBFIELD_TERMINATOR()
1049};
1050
1051/** Sub-fields for the PERF_STATUS MSR. */
1052static DBGFREGSUBFIELD const g_aCpumRegFields_perf_status[] =
1053{
1054 /** @todo */
1055 DBGFREGSUBFIELD_TERMINATOR()
1056};
1057
1058/** Sub-fields for the EFER MSR. */
1059static DBGFREGSUBFIELD const g_aCpumRegFields_efer[] =
1060{
1061 /** @todo */
1062 DBGFREGSUBFIELD_TERMINATOR()
1063};
1064
1065/** Sub-fields for the STAR MSR. */
1066static DBGFREGSUBFIELD const g_aCpumRegFields_star[] =
1067{
1068 /** @todo */
1069 DBGFREGSUBFIELD_TERMINATOR()
1070};
1071
1072/** Sub-fields for the CSTAR MSR. */
1073static DBGFREGSUBFIELD const g_aCpumRegFields_cstar[] =
1074{
1075 /** @todo */
1076 DBGFREGSUBFIELD_TERMINATOR()
1077};
1078
1079/** Sub-fields for the LSTAR MSR. */
1080static DBGFREGSUBFIELD const g_aCpumRegFields_lstar[] =
1081{
1082 /** @todo */
1083 DBGFREGSUBFIELD_TERMINATOR()
1084};
1085
1086#if 0 /** @todo */
1087/** Sub-fields for the SF_MASK MSR. */
1088static DBGFREGSUBFIELD const g_aCpumRegFields_sf_mask[] =
1089{
1090 /** @todo */
1091 DBGFREGSUBFIELD_TERMINATOR()
1092};
1093#endif
1094
1095
1096/** @name Macros for producing register descriptor table entries.
1097 * @{ */
1098#define CPU_REG_EX_AS(a_szName, a_RegSuff, a_TypeSuff, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1099 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /*fFlags*/, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1100
1101#define CPU_REG_REG(UName, LName) \
1102 CPU_REG_RW_AS(#LName, UName, U64, LName, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_##LName, NULL)
1103
1104#define CPU_REG_SEG(UName, LName) \
1105 CPU_REG_RW_AS(#LName, UName, U16, LName.Sel, cpumR3RegGet_Generic, cpumR3RegSet_seg, NULL, NULL ), \
1106 CPU_REG_RW_AS(#LName "_attr", UName##_ATTR, U32, LName.Attr.u, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_seg), \
1107 CPU_REG_RW_AS(#LName "_base", UName##_BASE, U64, LName.u64Base, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), \
1108 CPU_REG_RW_AS(#LName "_lim", UName##_LIMIT, U32, LName.u32Limit, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL )
1109
1110#define CPU_REG_MM(n) \
1111 CPU_REG_XS_RW_AS("mm" #n, MM##n, U64, x87.aRegs[n].mmx, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_mmN)
1112
1113#define CPU_REG_XMM(n) \
1114 CPU_REG_XS_RW_AS("xmm" #n, XMM##n, U128, x87.aXMM[n].xmm, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_xmmN)
1115
1116#define CPU_REG_YMM(n) \
1117 { "ymm" #n, DBGFREG_YMM##n, DBGFREGVALTYPE_U256, 0 /*fFlags*/, n, cpumR3RegGet_ymm, cpumR3RegSet_ymm, NULL /*paAliases*/, NULL /*paSubFields*/ }
1118
1119/** @} */
1120
1121
1122/**
1123 * The guest register descriptors.
1124 */
1125static DBGFREGDESC const g_aCpumRegGstDescs[] =
1126{
1127#define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1128 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /*fFlags*/, (uint32_t)RT_UOFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1129#define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1130 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, (uint32_t)RT_UOFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1131#define CPU_REG_XS_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_XStateMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1132 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /*fFlags*/, (uint32_t)RT_UOFFSETOF(X86XSAVEAREA, a_XStateMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1133#define CPU_REG_XS_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_XStateMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1134 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, (uint32_t)RT_UOFFSETOF(X86XSAVEAREA, a_XStateMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1135#define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \
1136 CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegGstGet_msr, cpumR3RegGstSet_msr, NULL, a_paSubFields)
1137#define CPU_REG_ST(n) \
1138 CPU_REG_EX_AS("st" #n, ST##n, R80, n, cpumR3RegGstGet_stN, cpumR3RegGstSet_stN, NULL, g_aCpumRegFields_stN)
1139
1140 CPU_REG_REG(RAX, rax),
1141 CPU_REG_REG(RCX, rcx),
1142 CPU_REG_REG(RDX, rdx),
1143 CPU_REG_REG(RBX, rbx),
1144 CPU_REG_REG(RSP, rsp),
1145 CPU_REG_REG(RBP, rbp),
1146 CPU_REG_REG(RSI, rsi),
1147 CPU_REG_REG(RDI, rdi),
1148 CPU_REG_REG(R8, r8),
1149 CPU_REG_REG(R9, r9),
1150 CPU_REG_REG(R10, r10),
1151 CPU_REG_REG(R11, r11),
1152 CPU_REG_REG(R12, r12),
1153 CPU_REG_REG(R13, r13),
1154 CPU_REG_REG(R14, r14),
1155 CPU_REG_REG(R15, r15),
1156 CPU_REG_SEG(CS, cs),
1157 CPU_REG_SEG(DS, ds),
1158 CPU_REG_SEG(ES, es),
1159 CPU_REG_SEG(FS, fs),
1160 CPU_REG_SEG(GS, gs),
1161 CPU_REG_SEG(SS, ss),
1162 CPU_REG_REG(RIP, rip),
1163 CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ),
1164 CPU_REG_XS_RW_AS("fcw", FCW, U16, x87.FCW, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_fcw ),
1165 CPU_REG_XS_RW_AS("fsw", FSW, U16, x87.FSW, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_fsw ),
1166 CPU_REG_XS_RO_AS("ftw", FTW, U16, x87, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ),
1167 CPU_REG_XS_RW_AS("fop", FOP, U16, x87.FOP, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, NULL ),
1168 CPU_REG_XS_RW_AS("fpuip", FPUIP, U32, x87.FPUIP, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, g_aCpumRegAliases_fpuip, NULL ),
1169 CPU_REG_XS_RW_AS("fpucs", FPUCS, U16, x87.CS, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, NULL ),
1170 CPU_REG_XS_RW_AS("fpudp", FPUDP, U32, x87.FPUDP, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, g_aCpumRegAliases_fpudp, NULL ),
1171 CPU_REG_XS_RW_AS("fpuds", FPUDS, U16, x87.DS, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, NULL ),
1172 CPU_REG_XS_RW_AS("mxcsr", MXCSR, U32, x87.MXCSR, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_mxcsr ),
1173 CPU_REG_XS_RW_AS("mxcsr_mask", MXCSR_MASK, U32, x87.MXCSR_MASK, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_mxcsr ),
1174 CPU_REG_ST(0),
1175 CPU_REG_ST(1),
1176 CPU_REG_ST(2),
1177 CPU_REG_ST(3),
1178 CPU_REG_ST(4),
1179 CPU_REG_ST(5),
1180 CPU_REG_ST(6),
1181 CPU_REG_ST(7),
1182 CPU_REG_MM(0),
1183 CPU_REG_MM(1),
1184 CPU_REG_MM(2),
1185 CPU_REG_MM(3),
1186 CPU_REG_MM(4),
1187 CPU_REG_MM(5),
1188 CPU_REG_MM(6),
1189 CPU_REG_MM(7),
1190 CPU_REG_XMM(0),
1191 CPU_REG_XMM(1),
1192 CPU_REG_XMM(2),
1193 CPU_REG_XMM(3),
1194 CPU_REG_XMM(4),
1195 CPU_REG_XMM(5),
1196 CPU_REG_XMM(6),
1197 CPU_REG_XMM(7),
1198 CPU_REG_XMM(8),
1199 CPU_REG_XMM(9),
1200 CPU_REG_XMM(10),
1201 CPU_REG_XMM(11),
1202 CPU_REG_XMM(12),
1203 CPU_REG_XMM(13),
1204 CPU_REG_XMM(14),
1205 CPU_REG_XMM(15),
1206 CPU_REG_YMM(0),
1207 CPU_REG_YMM(1),
1208 CPU_REG_YMM(2),
1209 CPU_REG_YMM(3),
1210 CPU_REG_YMM(4),
1211 CPU_REG_YMM(5),
1212 CPU_REG_YMM(6),
1213 CPU_REG_YMM(7),
1214 CPU_REG_YMM(8),
1215 CPU_REG_YMM(9),
1216 CPU_REG_YMM(10),
1217 CPU_REG_YMM(11),
1218 CPU_REG_YMM(12),
1219 CPU_REG_YMM(13),
1220 CPU_REG_YMM(14),
1221 CPU_REG_YMM(15),
1222 CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1223 CPU_REG_RW_AS("gdtr_lim", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1224 CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1225 CPU_REG_RW_AS("idtr_lim", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1226 CPU_REG_SEG(LDTR, ldtr),
1227 CPU_REG_SEG(TR, tr),
1228 CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ),
1229 CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
1230 CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr3 ),
1231 CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr4 ),
1232 CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
1233 CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1234 CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1235 CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1236 CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1237 CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr6 ),
1238 CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr7 ),
1239 CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ),
1240 CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ),
1241 CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status),
1242 CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ),
1243 CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U64, NULL ),
1244 CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U64, NULL ),
1245 CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ),
1246 CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ),
1247 CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ),
1248 CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ),
1249 CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ),
1250 CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ),
1251 CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ),
1252 CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ),
1253 CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ),
1254 CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ),
1255 CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Guest.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1256 CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Guest.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1257 CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Guest.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1258 CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Guest.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1259 CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
1260 CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ),
1261 DBGFREGDESC_TERMINATOR()
1262
1263#undef CPU_REG_RW_AS
1264#undef CPU_REG_RO_AS
1265#undef CPU_REG_MSR
1266#undef CPU_REG_ST
1267};
1268
1269
1270/**
1271 * Initializes the debugger related sides of the CPUM component.
1272 *
1273 * Called by CPUMR3Init.
1274 *
1275 * @returns VBox status code.
1276 * @param pVM The cross context VM structure.
1277 */
1278int cpumR3DbgInit(PVM pVM)
1279{
1280 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1281 {
1282 int rc = DBGFR3RegRegisterCpu(pVM, pVM->apCpusR3[idCpu], g_aCpumRegGstDescs, true /*fGuestRegs*/);
1283 AssertLogRelRCReturn(rc, rc);
1284 }
1285
1286 return VINF_SUCCESS;
1287}
1288
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