CPUMDbg.cpp@ 81150

Last change on this file since 81150 was 80333, checked in by vboxsync, 5 years ago
VMM: Eliminating the VBOX_BUGREF_9217_PART_I preprocessor macro. bugref:9217
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File size: 47.4 KB

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1	/* $Id: CPUMDbg.cpp 80333 2019-08-16 20:28:38Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager, Debugger & Debugging APIs.
4	*/
5
6	/*
7	* Copyright (C) 2010-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DBGF
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/apic.h>
26	#include "CPUMInternal.h"
27	#include <VBox/vmm/vm.h>
28	#include <VBox/param.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/thread.h>
32	#include <iprt/string.h>
33	#include <iprt/uint128.h>
34
35
36	/**
37	* @interface_method_impl{DBGFREGDESC,pfnGet}
38	*/
39	static DECLCALLBACK(int) cpumR3RegGet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
40	{
41	PVMCPU pVCpu = (PVMCPU)pvUser;
42	void const pv = (uint8_t const )&pVCpu->cpum + pDesc->offRegister;
43
44	VMCPU_ASSERT_EMT(pVCpu);
45
46	switch (pDesc->enmType)
47	{
48	case DBGFREGVALTYPE_U8: pValue->u8 = (uint8_t const )pv; return VINF_SUCCESS;
49	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t const )pv; return VINF_SUCCESS;
50	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t const )pv; return VINF_SUCCESS;
51	case DBGFREGVALTYPE_U64: pValue->u64 = (uint64_t const )pv; return VINF_SUCCESS;
52	case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS;
53	case DBGFREGVALTYPE_U256: pValue->u256 = *(PCRTUINT256U )pv; return VINF_SUCCESS;
54	case DBGFREGVALTYPE_U512: pValue->u512 = *(PCRTUINT512U )pv; return VINF_SUCCESS;
55	default:
56	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
57	}
58	}
59
60
61	/**
62	* @interface_method_impl{DBGFREGDESC,pfnSet}
63	*/
64	static DECLCALLBACK(int) cpumR3RegSet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
65	{
66	PVMCPU pVCpu = (PVMCPU)pvUser;
67	void pv = (uint8_t )&pVCpu->cpum + pDesc->offRegister;
68
69	VMCPU_ASSERT_EMT(pVCpu);
70
71	switch (pDesc->enmType)
72	{
73	case DBGFREGVALTYPE_U8:
74	(uint8_t )pv &= ~pfMask->u8;
75	(uint8_t )pv \|= pValue->u8 & pfMask->u8;
76	return VINF_SUCCESS;
77
78	case DBGFREGVALTYPE_U16:
79	(uint16_t )pv &= ~pfMask->u16;
80	(uint16_t )pv \|= pValue->u16 & pfMask->u16;
81	return VINF_SUCCESS;
82
83	case DBGFREGVALTYPE_U32:
84	(uint32_t )pv &= ~pfMask->u32;
85	(uint32_t )pv \|= pValue->u32 & pfMask->u32;
86	return VINF_SUCCESS;
87
88	case DBGFREGVALTYPE_U64:
89	(uint64_t )pv &= ~pfMask->u64;
90	(uint64_t )pv \|= pValue->u64 & pfMask->u64;
91	return VINF_SUCCESS;
92
93	case DBGFREGVALTYPE_U128:
94	{
95	RTUINT128U Val;
96	RTUInt128AssignAnd((PRTUINT128U)pv, RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u128)));
97	RTUInt128AssignOr((PRTUINT128U)pv, RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
98	return VINF_SUCCESS;
99	}
100
101	default:
102	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
103	}
104	}
105
106
107	/**
108	* @interface_method_impl{DBGFREGDESC,pfnGet}
109	*/
110	static DECLCALLBACK(int) cpumR3RegGet_XStateGeneric(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
111	{
112	PVMCPU pVCpu = (PVMCPU)pvUser;
113	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest.pXStateR3 + pDesc->offRegister;
114
115	VMCPU_ASSERT_EMT(pVCpu);
116
117	switch (pDesc->enmType)
118	{
119	case DBGFREGVALTYPE_U8: pValue->u8 = (uint8_t const )pv; return VINF_SUCCESS;
120	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t const )pv; return VINF_SUCCESS;
121	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t const )pv; return VINF_SUCCESS;
122	case DBGFREGVALTYPE_U64: pValue->u64 = (uint64_t const )pv; return VINF_SUCCESS;
123	case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS;
124	default:
125	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
126	}
127	}
128
129
130	/**
131	* @interface_method_impl{DBGFREGDESC,pfnSet}
132	*/
133	static DECLCALLBACK(int) cpumR3RegSet_XStateGeneric(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
134	{
135	PVMCPU pVCpu = (PVMCPU)pvUser;
136	void pv = (uint8_t )&pVCpu->cpum.s.Guest.pXStateR3 + pDesc->offRegister;
137
138	VMCPU_ASSERT_EMT(pVCpu);
139
140	switch (pDesc->enmType)
141	{
142	case DBGFREGVALTYPE_U8:
143	(uint8_t )pv &= ~pfMask->u8;
144	(uint8_t )pv \|= pValue->u8 & pfMask->u8;
145	return VINF_SUCCESS;
146
147	case DBGFREGVALTYPE_U16:
148	(uint16_t )pv &= ~pfMask->u16;
149	(uint16_t )pv \|= pValue->u16 & pfMask->u16;
150	return VINF_SUCCESS;
151
152	case DBGFREGVALTYPE_U32:
153	(uint32_t )pv &= ~pfMask->u32;
154	(uint32_t )pv \|= pValue->u32 & pfMask->u32;
155	return VINF_SUCCESS;
156
157	case DBGFREGVALTYPE_U64:
158	(uint64_t )pv &= ~pfMask->u64;
159	(uint64_t )pv \|= pValue->u64 & pfMask->u64;
160	return VINF_SUCCESS;
161
162	case DBGFREGVALTYPE_U128:
163	{
164	RTUINT128U Val;
165	RTUInt128AssignAnd((PRTUINT128U)pv, RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u128)));
166	RTUInt128AssignOr((PRTUINT128U)pv, RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
167	return VINF_SUCCESS;
168	}
169
170	default:
171	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
172	}
173	}
174
175
176
177	/**
178	* @interface_method_impl{DBGFREGDESC,pfnGet}
179	*/
180	static DECLCALLBACK(int) cpumR3RegSet_seg(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
181	{
182	/** @todo perform a selector load, updating hidden selectors and stuff. */
183	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
184	return VERR_NOT_IMPLEMENTED;
185	}
186
187
188	/**
189	* @interface_method_impl{DBGFREGDESC,pfnGet}
190	*/
191	static DECLCALLBACK(int) cpumR3RegGet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
192	{
193	PVMCPU pVCpu = (PVMCPU)pvUser;
194	VBOXGDTR const pGdtr = (VBOXGDTR const )((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
195
196	VMCPU_ASSERT_EMT(pVCpu);
197	Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
198
199	pValue->dtr.u32Limit = pGdtr->cbGdt;
200	pValue->dtr.u64Base = pGdtr->pGdt;
201	return VINF_SUCCESS;
202	}
203
204
205	/**
206	* @interface_method_impl{DBGFREGDESC,pfnGet}
207	*/
208	static DECLCALLBACK(int) cpumR3RegSet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
209	{
210	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
211	return VERR_NOT_IMPLEMENTED;
212	}
213
214
215	/**
216	* @interface_method_impl{DBGFREGDESC,pfnGet}
217	*/
218	static DECLCALLBACK(int) cpumR3RegGet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
219	{
220	PVMCPU pVCpu = (PVMCPU)pvUser;
221	VBOXIDTR const pIdtr = (VBOXIDTR const )((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
222
223	VMCPU_ASSERT_EMT(pVCpu);
224	Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
225
226	pValue->dtr.u32Limit = pIdtr->cbIdt;
227	pValue->dtr.u64Base = pIdtr->pIdt;
228	return VINF_SUCCESS;
229	}
230
231
232	/**
233	* @interface_method_impl{DBGFREGDESC,pfnGet}
234	*/
235	static DECLCALLBACK(int) cpumR3RegSet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
236	{
237	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
238	return VERR_NOT_IMPLEMENTED;
239	}
240
241
242	/**
243	* Determins the tag register value for a CPU register when the FPU state
244	* format is FXSAVE.
245	*
246	* @returns The tag register value.
247	* @param pFpu Pointer to the guest FPU.
248	* @param iReg The register number (0..7).
249	*/
250	DECLINLINE(uint16_t) cpumR3RegCalcFpuTagFromFxSave(PCX86FXSTATE pFpu, unsigned iReg)
251	{
252	/*
253	* See table 11-1 in the AMD docs.
254	*/
255	if (!(pFpu->FTW & RT_BIT_32(iReg)))
256	return 3; /* b11 - empty */
257
258	uint16_t const uExp = pFpu->aRegs[iReg].au16[4];
259	if (uExp == 0)
260	{
261	if (pFpu->aRegs[iReg].au64[0] == 0) /* J & M == 0 */
262	return 1; /* b01 - zero */
263	return 2; /* b10 - special */
264	}
265
266	if (uExp == UINT16_C(0xffff))
267	return 2; /* b10 - special */
268
269	if (!(pFpu->aRegs[iReg].au64[0] >> 63)) /* J == 0 */
270	return 2; /* b10 - special */
271
272	return 0; /* b00 - valid (normal) */
273	}
274
275
276	/**
277	* @interface_method_impl{DBGFREGDESC,pfnGet}
278	*/
279	static DECLCALLBACK(int) cpumR3RegGet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
280	{
281	PVMCPU pVCpu = (PVMCPU)pvUser;
282	PCX86FXSTATE pFpu = (PCX86FXSTATE)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
283
284	VMCPU_ASSERT_EMT(pVCpu);
285	Assert(pDesc->enmType == DBGFREGVALTYPE_U16);
286
287	pValue->u16 = cpumR3RegCalcFpuTagFromFxSave(pFpu, 0)
288	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 1) << 2)
289	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 2) << 4)
290	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 3) << 6)
291	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 4) << 8)
292	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 5) << 10)
293	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 6) << 12)
294	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 7) << 14);
295	return VINF_SUCCESS;
296	}
297
298
299	/**
300	* @interface_method_impl{DBGFREGDESC,pfnGet}
301	*/
302	static DECLCALLBACK(int) cpumR3RegSet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
303	{
304	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
305	return VERR_DBGF_READ_ONLY_REGISTER;
306	}
307
308	#if 0 /* unused */
309
310	/**
311	* @interface_method_impl{DBGFREGDESC,pfnGet}
312	*/
313	static DECLCALLBACK(int) cpumR3RegGet_Dummy(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
314	{
315	RT_NOREF_PV(pvUser);
316	switch (pDesc->enmType)
317	{
318	case DBGFREGVALTYPE_U8: pValue->u8 = 0; return VINF_SUCCESS;
319	case DBGFREGVALTYPE_U16: pValue->u16 = 0; return VINF_SUCCESS;
320	case DBGFREGVALTYPE_U32: pValue->u32 = 0; return VINF_SUCCESS;
321	case DBGFREGVALTYPE_U64: pValue->u64 = 0; return VINF_SUCCESS;
322	case DBGFREGVALTYPE_U128:
323	RT_ZERO(pValue->u128);
324	return VINF_SUCCESS;
325	case DBGFREGVALTYPE_DTR:
326	pValue->dtr.u32Limit = 0;
327	pValue->dtr.u64Base = 0;
328	return VINF_SUCCESS;
329	case DBGFREGVALTYPE_R80:
330	RT_ZERO(pValue->r80Ex);
331	return VINF_SUCCESS;
332	default:
333	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
334	}
335	}
336
337
338	/**
339	* @interface_method_impl{DBGFREGDESC,pfnSet}
340	*/
341	static DECLCALLBACK(int) cpumR3RegSet_Dummy(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
342	{
343	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
344	return VERR_DBGF_READ_ONLY_REGISTER;
345	}
346
347	#endif /* unused */
348
349	/**
350	* @interface_method_impl{DBGFREGDESC,pfnGet}
351	*/
352	static DECLCALLBACK(int) cpumR3RegGet_ymm(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
353	{
354	PVMCPU pVCpu = (PVMCPU)pvUser;
355	uint32_t iReg = pDesc->offRegister;
356
357	Assert(pDesc->enmType == DBGFREGVALTYPE_U256);
358	VMCPU_ASSERT_EMT(pVCpu);
359
360	if (iReg < 16)
361	{
362	pValue->u256.DQWords.dqw0 = pVCpu->cpum.s.Guest.pXStateR3->x87.aXMM[iReg].uXmm;
363	pValue->u256.DQWords.dqw1 = pVCpu->cpum.s.Guest.pXStateR3->u.YmmHi.aYmmHi[iReg].uXmm;
364	return VINF_SUCCESS;
365	}
366	return VERR_NOT_IMPLEMENTED;
367	}
368
369
370	/**
371	* @interface_method_impl{DBGFREGDESC,pfnSet}
372	*/
373	static DECLCALLBACK(int) cpumR3RegSet_ymm(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
374	{
375	PVMCPU pVCpu = (PVMCPU)pvUser;
376	uint32_t iReg = pDesc->offRegister;
377
378	Assert(pDesc->enmType == DBGFREGVALTYPE_U256);
379	VMCPU_ASSERT_EMT(pVCpu);
380
381	if (iReg < 16)
382	{
383	RTUINT128U Val;
384	RTUInt128AssignAnd(&pVCpu->cpum.s.Guest.pXStateR3->x87.aXMM[iReg].uXmm,
385	RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u256.DQWords.dqw0)));
386	RTUInt128AssignOr(&pVCpu->cpum.s.Guest.pXStateR3->u.YmmHi.aYmmHi[iReg].uXmm,
387	RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
388
389	}
390	return VERR_NOT_IMPLEMENTED;
391	}
392
393
394	/*
395	*
396	* Guest register access functions.
397	*
398	*/
399
400	/**
401	* @interface_method_impl{DBGFREGDESC,pfnGet}
402	*/
403	static DECLCALLBACK(int) cpumR3RegGstGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
404	{
405	PVMCPU pVCpu = (PVMCPU)pvUser;
406	VMCPU_ASSERT_EMT(pVCpu);
407
408	uint64_t u64Value;
409	int rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64Value);
410	if (rc == VERR_PDM_NO_APIC_INSTANCE) /* CR8 might not be available, see @bugref{8868}.*/
411	u64Value = 0;
412	else
413	AssertRCReturn(rc, rc);
414	switch (pDesc->enmType)
415	{
416	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
417	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
418	default:
419	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
420	}
421	return VINF_SUCCESS;
422	}
423
424
425	/**
426	* @interface_method_impl{DBGFREGDESC,pfnGet}
427	*/
428	static DECLCALLBACK(int) cpumR3RegGstSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
429	{
430	int rc;
431	PVMCPU pVCpu = (PVMCPU)pvUser;
432
433	VMCPU_ASSERT_EMT(pVCpu);
434
435	/*
436	* Calculate the new value.
437	*/
438	uint64_t u64Value;
439	uint64_t fMask;
440	uint64_t fMaskMax;
441	switch (pDesc->enmType)
442	{
443	case DBGFREGVALTYPE_U64:
444	u64Value = pValue->u64;
445	fMask = pfMask->u64;
446	fMaskMax = UINT64_MAX;
447	break;
448	case DBGFREGVALTYPE_U32:
449	u64Value = pValue->u32;
450	fMask = pfMask->u32;
451	fMaskMax = UINT32_MAX;
452	break;
453	default:
454	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
455	}
456	if (fMask != fMaskMax)
457	{
458	uint64_t u64FullValue;
459	rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64FullValue);
460	if (RT_FAILURE(rc))
461	return rc;
462	u64Value = (u64FullValue & ~fMask)
463	\| (u64Value & fMask);
464	}
465
466	/*
467	* Perform the assignment.
468	*/
469	switch (pDesc->offRegister)
470	{
471	case 0: rc = CPUMSetGuestCR0(pVCpu, u64Value); break;
472	case 2: rc = CPUMSetGuestCR2(pVCpu, u64Value); break;
473	case 3: rc = CPUMSetGuestCR3(pVCpu, u64Value); break;
474	case 4: rc = CPUMSetGuestCR4(pVCpu, u64Value); break;
475	case 8: rc = APICSetTpr(pVCpu, (uint8_t)(u64Value << 4)); break;
476	default:
477	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
478	}
479	return rc;
480	}
481
482
483	/**
484	* @interface_method_impl{DBGFREGDESC,pfnGet}
485	*/
486	static DECLCALLBACK(int) cpumR3RegGstGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
487	{
488	PVMCPU pVCpu = (PVMCPU)pvUser;
489	VMCPU_ASSERT_EMT(pVCpu);
490
491	uint64_t u64Value;
492	int rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64Value);
493	AssertRCReturn(rc, rc);
494	switch (pDesc->enmType)
495	{
496	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
497	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
498	default:
499	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
500	}
501	return VINF_SUCCESS;
502	}
503
504
505	/**
506	* @interface_method_impl{DBGFREGDESC,pfnGet}
507	*/
508	static DECLCALLBACK(int) cpumR3RegGstSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
509	{
510	int rc;
511	PVMCPU pVCpu = (PVMCPU)pvUser;
512
513	VMCPU_ASSERT_EMT(pVCpu);
514
515	/*
516	* Calculate the new value.
517	*/
518	uint64_t u64Value;
519	uint64_t fMask;
520	uint64_t fMaskMax;
521	switch (pDesc->enmType)
522	{
523	case DBGFREGVALTYPE_U64:
524	u64Value = pValue->u64;
525	fMask = pfMask->u64;
526	fMaskMax = UINT64_MAX;
527	break;
528	case DBGFREGVALTYPE_U32:
529	u64Value = pValue->u32;
530	fMask = pfMask->u32;
531	fMaskMax = UINT32_MAX;
532	break;
533	default:
534	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
535	}
536	if (fMask != fMaskMax)
537	{
538	uint64_t u64FullValue;
539	rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64FullValue);
540	if (RT_FAILURE(rc))
541	return rc;
542	u64Value = (u64FullValue & ~fMask)
543	\| (u64Value & fMask);
544	}
545
546	/*
547	* Perform the assignment.
548	*/
549	return CPUMSetGuestDRx(pVCpu, pDesc->offRegister, u64Value);
550	}
551
552
553	/**
554	* @interface_method_impl{DBGFREGDESC,pfnGet}
555	*/
556	static DECLCALLBACK(int) cpumR3RegGstGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
557	{
558	PVMCPU pVCpu = (PVMCPU)pvUser;
559	VMCPU_ASSERT_EMT(pVCpu);
560
561	uint64_t u64Value;
562	VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64Value);
563	if (rcStrict == VINF_SUCCESS)
564	{
565	switch (pDesc->enmType)
566	{
567	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
568	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
569	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break;
570	default:
571	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
572	}
573	return VBOXSTRICTRC_VAL(rcStrict);
574	}
575
576	/** @todo what to do about errors? */
577	Assert(RT_FAILURE_NP(rcStrict));
578	return VBOXSTRICTRC_VAL(rcStrict);
579	}
580
581
582	/**
583	* @interface_method_impl{DBGFREGDESC,pfnGet}
584	*/
585	static DECLCALLBACK(int) cpumR3RegGstSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
586	{
587	PVMCPU pVCpu = (PVMCPU)pvUser;
588
589	VMCPU_ASSERT_EMT(pVCpu);
590
591	/*
592	* Calculate the new value.
593	*/
594	uint64_t u64Value;
595	uint64_t fMask;
596	uint64_t fMaskMax;
597	switch (pDesc->enmType)
598	{
599	case DBGFREGVALTYPE_U64:
600	u64Value = pValue->u64;
601	fMask = pfMask->u64;
602	fMaskMax = UINT64_MAX;
603	break;
604	case DBGFREGVALTYPE_U32:
605	u64Value = pValue->u32;
606	fMask = pfMask->u32;
607	fMaskMax = UINT32_MAX;
608	break;
609	case DBGFREGVALTYPE_U16:
610	u64Value = pValue->u16;
611	fMask = pfMask->u16;
612	fMaskMax = UINT16_MAX;
613	break;
614	default:
615	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
616	}
617	if (fMask != fMaskMax)
618	{
619	uint64_t u64FullValue;
620	VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64FullValue);
621	if (rcStrict != VINF_SUCCESS)
622	{
623	AssertRC(RT_FAILURE_NP(rcStrict));
624	return VBOXSTRICTRC_VAL(rcStrict);
625	}
626	u64Value = (u64FullValue & ~fMask)
627	\| (u64Value & fMask);
628	}
629
630	/*
631	* Perform the assignment.
632	*/
633	VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pDesc->offRegister, u64Value);
634	if (rcStrict == VINF_SUCCESS)
635	return VINF_SUCCESS;
636	AssertRC(RT_FAILURE_NP(rcStrict));
637	return VBOXSTRICTRC_VAL(rcStrict);
638	}
639
640
641	/**
642	* @interface_method_impl{DBGFREGDESC,pfnGet}
643	*/
644	static DECLCALLBACK(int) cpumR3RegGstGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
645	{
646	PVMCPU pVCpu = (PVMCPU)pvUser;
647	VMCPU_ASSERT_EMT(pVCpu);
648	Assert(pDesc->enmType == DBGFREGVALTYPE_R80);
649
650	PX86FXSTATE pFpuCtx = &pVCpu->cpum.s.Guest.CTX_SUFF(pXState)->x87;
651	unsigned iReg = (pFpuCtx->FSW >> 11) & 7;
652	iReg += pDesc->offRegister;
653	iReg &= 7;
654	pValue->r80Ex = pFpuCtx->aRegs[iReg].r80Ex;
655
656	return VINF_SUCCESS;
657	}
658
659
660	/**
661	* @interface_method_impl{DBGFREGDESC,pfnGet}
662	*/
663	static DECLCALLBACK(int) cpumR3RegGstSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
664	{
665	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
666	return VERR_NOT_IMPLEMENTED;
667	}
668
669
670
671	/*
672	* Set up aliases.
673	*/
674	#define CPUMREGALIAS_STD(Name, psz32, psz16, psz8) \
675	static DBGFREGALIAS const g_aCpumRegAliases_##Name[] = \
676	{ \
677	{ psz32, DBGFREGVALTYPE_U32 }, \
678	{ psz16, DBGFREGVALTYPE_U16 }, \
679	{ psz8, DBGFREGVALTYPE_U8 }, \
680	{ NULL, DBGFREGVALTYPE_INVALID } \
681	}
682	CPUMREGALIAS_STD(rax, "eax", "ax", "al");
683	CPUMREGALIAS_STD(rcx, "ecx", "cx", "cl");
684	CPUMREGALIAS_STD(rdx, "edx", "dx", "dl");
685	CPUMREGALIAS_STD(rbx, "ebx", "bx", "bl");
686	CPUMREGALIAS_STD(rsp, "esp", "sp", NULL);
687	CPUMREGALIAS_STD(rbp, "ebp", "bp", NULL);
688	CPUMREGALIAS_STD(rsi, "esi", "si", "sil");
689	CPUMREGALIAS_STD(rdi, "edi", "di", "dil");
690	CPUMREGALIAS_STD(r8, "r8d", "r8w", "r8b");
691	CPUMREGALIAS_STD(r9, "r9d", "r9w", "r9b");
692	CPUMREGALIAS_STD(r10, "r10d", "r10w", "r10b");
693	CPUMREGALIAS_STD(r11, "r11d", "r11w", "r11b");
694	CPUMREGALIAS_STD(r12, "r12d", "r12w", "r12b");
695	CPUMREGALIAS_STD(r13, "r13d", "r13w", "r13b");
696	CPUMREGALIAS_STD(r14, "r14d", "r14w", "r14b");
697	CPUMREGALIAS_STD(r15, "r15d", "r15w", "r15b");
698	CPUMREGALIAS_STD(rip, "eip", "ip", NULL);
699	CPUMREGALIAS_STD(rflags, "eflags", "flags", NULL);
700	#undef CPUMREGALIAS_STD
701
702	static DBGFREGALIAS const g_aCpumRegAliases_fpuip[] =
703	{
704	{ "fpuip16", DBGFREGVALTYPE_U16 },
705	{ NULL, DBGFREGVALTYPE_INVALID }
706	};
707
708	static DBGFREGALIAS const g_aCpumRegAliases_fpudp[] =
709	{
710	{ "fpudp16", DBGFREGVALTYPE_U16 },
711	{ NULL, DBGFREGVALTYPE_INVALID }
712	};
713
714	static DBGFREGALIAS const g_aCpumRegAliases_cr0[] =
715	{
716	{ "msw", DBGFREGVALTYPE_U16 },
717	{ NULL, DBGFREGVALTYPE_INVALID }
718	};
719
720	/*
721	* Sub fields.
722	*/
723	/** Sub-fields for the (hidden) segment attribute register. */
724	static DBGFREGSUBFIELD const g_aCpumRegFields_seg[] =
725	{
726	DBGFREGSUBFIELD_RW("type", 0, 4, 0),
727	DBGFREGSUBFIELD_RW("s", 4, 1, 0),
728	DBGFREGSUBFIELD_RW("dpl", 5, 2, 0),
729	DBGFREGSUBFIELD_RW("p", 7, 1, 0),
730	DBGFREGSUBFIELD_RW("avl", 12, 1, 0),
731	DBGFREGSUBFIELD_RW("l", 13, 1, 0),
732	DBGFREGSUBFIELD_RW("d", 14, 1, 0),
733	DBGFREGSUBFIELD_RW("g", 15, 1, 0),
734	DBGFREGSUBFIELD_TERMINATOR()
735	};
736
737	/** Sub-fields for the flags register. */
738	static DBGFREGSUBFIELD const g_aCpumRegFields_rflags[] =
739	{
740	DBGFREGSUBFIELD_RW("cf", 0, 1, 0),
741	DBGFREGSUBFIELD_RW("pf", 2, 1, 0),
742	DBGFREGSUBFIELD_RW("af", 4, 1, 0),
743	DBGFREGSUBFIELD_RW("zf", 6, 1, 0),
744	DBGFREGSUBFIELD_RW("sf", 7, 1, 0),
745	DBGFREGSUBFIELD_RW("tf", 8, 1, 0),
746	DBGFREGSUBFIELD_RW("if", 9, 1, 0),
747	DBGFREGSUBFIELD_RW("df", 10, 1, 0),
748	DBGFREGSUBFIELD_RW("of", 11, 1, 0),
749	DBGFREGSUBFIELD_RW("iopl", 12, 2, 0),
750	DBGFREGSUBFIELD_RW("nt", 14, 1, 0),
751	DBGFREGSUBFIELD_RW("rf", 16, 1, 0),
752	DBGFREGSUBFIELD_RW("vm", 17, 1, 0),
753	DBGFREGSUBFIELD_RW("ac", 18, 1, 0),
754	DBGFREGSUBFIELD_RW("vif", 19, 1, 0),
755	DBGFREGSUBFIELD_RW("vip", 20, 1, 0),
756	DBGFREGSUBFIELD_RW("id", 21, 1, 0),
757	DBGFREGSUBFIELD_TERMINATOR()
758	};
759
760	/** Sub-fields for the FPU control word register. */
761	static DBGFREGSUBFIELD const g_aCpumRegFields_fcw[] =
762	{
763	DBGFREGSUBFIELD_RW("im", 1, 1, 0),
764	DBGFREGSUBFIELD_RW("dm", 2, 1, 0),
765	DBGFREGSUBFIELD_RW("zm", 3, 1, 0),
766	DBGFREGSUBFIELD_RW("om", 4, 1, 0),
767	DBGFREGSUBFIELD_RW("um", 5, 1, 0),
768	DBGFREGSUBFIELD_RW("pm", 6, 1, 0),
769	DBGFREGSUBFIELD_RW("pc", 8, 2, 0),
770	DBGFREGSUBFIELD_RW("rc", 10, 2, 0),
771	DBGFREGSUBFIELD_RW("x", 12, 1, 0),
772	DBGFREGSUBFIELD_TERMINATOR()
773	};
774
775	/** Sub-fields for the FPU status word register. */
776	static DBGFREGSUBFIELD const g_aCpumRegFields_fsw[] =
777	{
778	DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
779	DBGFREGSUBFIELD_RW("de", 1, 1, 0),
780	DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
781	DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
782	DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
783	DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
784	DBGFREGSUBFIELD_RW("se", 6, 1, 0),
785	DBGFREGSUBFIELD_RW("es", 7, 1, 0),
786	DBGFREGSUBFIELD_RW("c0", 8, 1, 0),
787	DBGFREGSUBFIELD_RW("c1", 9, 1, 0),
788	DBGFREGSUBFIELD_RW("c2", 10, 1, 0),
789	DBGFREGSUBFIELD_RW("top", 11, 3, 0),
790	DBGFREGSUBFIELD_RW("c3", 14, 1, 0),
791	DBGFREGSUBFIELD_RW("b", 15, 1, 0),
792	DBGFREGSUBFIELD_TERMINATOR()
793	};
794
795	/** Sub-fields for the FPU tag word register. */
796	static DBGFREGSUBFIELD const g_aCpumRegFields_ftw[] =
797	{
798	DBGFREGSUBFIELD_RW("tag0", 0, 2, 0),
799	DBGFREGSUBFIELD_RW("tag1", 2, 2, 0),
800	DBGFREGSUBFIELD_RW("tag2", 4, 2, 0),
801	DBGFREGSUBFIELD_RW("tag3", 6, 2, 0),
802	DBGFREGSUBFIELD_RW("tag4", 8, 2, 0),
803	DBGFREGSUBFIELD_RW("tag5", 10, 2, 0),
804	DBGFREGSUBFIELD_RW("tag6", 12, 2, 0),
805	DBGFREGSUBFIELD_RW("tag7", 14, 2, 0),
806	DBGFREGSUBFIELD_TERMINATOR()
807	};
808
809	/** Sub-fields for the Multimedia Extensions Control and Status Register. */
810	static DBGFREGSUBFIELD const g_aCpumRegFields_mxcsr[] =
811	{
812	DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
813	DBGFREGSUBFIELD_RW("de", 1, 1, 0),
814	DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
815	DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
816	DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
817	DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
818	DBGFREGSUBFIELD_RW("daz", 6, 1, 0),
819	DBGFREGSUBFIELD_RW("im", 7, 1, 0),
820	DBGFREGSUBFIELD_RW("dm", 8, 1, 0),
821	DBGFREGSUBFIELD_RW("zm", 9, 1, 0),
822	DBGFREGSUBFIELD_RW("om", 10, 1, 0),
823	DBGFREGSUBFIELD_RW("um", 11, 1, 0),
824	DBGFREGSUBFIELD_RW("pm", 12, 1, 0),
825	DBGFREGSUBFIELD_RW("rc", 13, 2, 0),
826	DBGFREGSUBFIELD_RW("fz", 14, 1, 0),
827	DBGFREGSUBFIELD_TERMINATOR()
828	};
829
830	/** Sub-fields for the FPU tag word register. */
831	static DBGFREGSUBFIELD const g_aCpumRegFields_stN[] =
832	{
833	DBGFREGSUBFIELD_RW("man", 0, 64, 0),
834	DBGFREGSUBFIELD_RW("exp", 64, 15, 0),
835	DBGFREGSUBFIELD_RW("sig", 79, 1, 0),
836	DBGFREGSUBFIELD_TERMINATOR()
837	};
838
839	/** Sub-fields for the MMX registers. */
840	static DBGFREGSUBFIELD const g_aCpumRegFields_mmN[] =
841	{
842	DBGFREGSUBFIELD_RW("dw0", 0, 32, 0),
843	DBGFREGSUBFIELD_RW("dw1", 32, 32, 0),
844	DBGFREGSUBFIELD_RW("w0", 0, 16, 0),
845	DBGFREGSUBFIELD_RW("w1", 16, 16, 0),
846	DBGFREGSUBFIELD_RW("w2", 32, 16, 0),
847	DBGFREGSUBFIELD_RW("w3", 48, 16, 0),
848	DBGFREGSUBFIELD_RW("b0", 0, 8, 0),
849	DBGFREGSUBFIELD_RW("b1", 8, 8, 0),
850	DBGFREGSUBFIELD_RW("b2", 16, 8, 0),
851	DBGFREGSUBFIELD_RW("b3", 24, 8, 0),
852	DBGFREGSUBFIELD_RW("b4", 32, 8, 0),
853	DBGFREGSUBFIELD_RW("b5", 40, 8, 0),
854	DBGFREGSUBFIELD_RW("b6", 48, 8, 0),
855	DBGFREGSUBFIELD_RW("b7", 56, 8, 0),
856	DBGFREGSUBFIELD_TERMINATOR()
857	};
858
859	/** Sub-fields for the XMM registers. */
860	static DBGFREGSUBFIELD const g_aCpumRegFields_xmmN[] =
861	{
862	DBGFREGSUBFIELD_RW("r0", 0, 32, 0),
863	DBGFREGSUBFIELD_RW("r0.man", 0+ 0, 23, 0),
864	DBGFREGSUBFIELD_RW("r0.exp", 0+23, 8, 0),
865	DBGFREGSUBFIELD_RW("r0.sig", 0+31, 1, 0),
866	DBGFREGSUBFIELD_RW("r1", 32, 32, 0),
867	DBGFREGSUBFIELD_RW("r1.man", 32+ 0, 23, 0),
868	DBGFREGSUBFIELD_RW("r1.exp", 32+23, 8, 0),
869	DBGFREGSUBFIELD_RW("r1.sig", 32+31, 1, 0),
870	DBGFREGSUBFIELD_RW("r2", 64, 32, 0),
871	DBGFREGSUBFIELD_RW("r2.man", 64+ 0, 23, 0),
872	DBGFREGSUBFIELD_RW("r2.exp", 64+23, 8, 0),
873	DBGFREGSUBFIELD_RW("r2.sig", 64+31, 1, 0),
874	DBGFREGSUBFIELD_RW("r3", 96, 32, 0),
875	DBGFREGSUBFIELD_RW("r3.man", 96+ 0, 23, 0),
876	DBGFREGSUBFIELD_RW("r3.exp", 96+23, 8, 0),
877	DBGFREGSUBFIELD_RW("r3.sig", 96+31, 1, 0),
878	DBGFREGSUBFIELD_TERMINATOR()
879	};
880
881	#if 0 /* needs special accessor, too lazy for that now. */
882	/** Sub-fields for the YMM registers. */
883	static DBGFREGSUBFIELD const g_aCpumRegFields_ymmN[] =
884	{
885	DBGFREGSUBFIELD_RW("r0", 0, 32, 0),
886	DBGFREGSUBFIELD_RW("r0.man", 0+ 0, 23, 0),
887	DBGFREGSUBFIELD_RW("r0.exp", 0+23, 8, 0),
888	DBGFREGSUBFIELD_RW("r0.sig", 0+31, 1, 0),
889	DBGFREGSUBFIELD_RW("r1", 32, 32, 0),
890	DBGFREGSUBFIELD_RW("r1.man", 32+ 0, 23, 0),
891	DBGFREGSUBFIELD_RW("r1.exp", 32+23, 8, 0),
892	DBGFREGSUBFIELD_RW("r1.sig", 32+31, 1, 0),
893	DBGFREGSUBFIELD_RW("r2", 64, 32, 0),
894	DBGFREGSUBFIELD_RW("r2.man", 64+ 0, 23, 0),
895	DBGFREGSUBFIELD_RW("r2.exp", 64+23, 8, 0),
896	DBGFREGSUBFIELD_RW("r2.sig", 64+31, 1, 0),
897	DBGFREGSUBFIELD_RW("r3", 96, 32, 0),
898	DBGFREGSUBFIELD_RW("r3.man", 96+ 0, 23, 0),
899	DBGFREGSUBFIELD_RW("r3.exp", 96+23, 8, 0),
900	DBGFREGSUBFIELD_RW("r3.sig", 96+31, 1, 0),
901	DBGFREGSUBFIELD_RW("r4", 128, 32, 0),
902	DBGFREGSUBFIELD_RW("r4.man", 128+ 0, 23, 0),
903	DBGFREGSUBFIELD_RW("r4.exp", 128+23, 8, 0),
904	DBGFREGSUBFIELD_RW("r4.sig", 128+31, 1, 0),
905	DBGFREGSUBFIELD_RW("r5", 160, 32, 0),
906	DBGFREGSUBFIELD_RW("r5.man", 160+ 0, 23, 0),
907	DBGFREGSUBFIELD_RW("r5.exp", 160+23, 8, 0),
908	DBGFREGSUBFIELD_RW("r5.sig", 160+31, 1, 0),
909	DBGFREGSUBFIELD_RW("r6", 192, 32, 0),
910	DBGFREGSUBFIELD_RW("r6.man", 192+ 0, 23, 0),
911	DBGFREGSUBFIELD_RW("r6.exp", 192+23, 8, 0),
912	DBGFREGSUBFIELD_RW("r6.sig", 192+31, 1, 0),
913	DBGFREGSUBFIELD_RW("r7", 224, 32, 0),
914	DBGFREGSUBFIELD_RW("r7.man", 224+ 0, 23, 0),
915	DBGFREGSUBFIELD_RW("r7.exp", 224+23, 8, 0),
916	DBGFREGSUBFIELD_RW("r7.sig", 224+31, 1, 0),
917	DBGFREGSUBFIELD_TERMINATOR()
918	};
919	#endif
920
921	/** Sub-fields for the CR0 register. */
922	static DBGFREGSUBFIELD const g_aCpumRegFields_cr0[] =
923	{
924	DBGFREGSUBFIELD_RW("pe", 0, 1, 0),
925	DBGFREGSUBFIELD_RW("mp", 1, 1, 0),
926	DBGFREGSUBFIELD_RW("em", 2, 1, 0),
927	DBGFREGSUBFIELD_RW("ts", 3, 1, 0),
928	DBGFREGSUBFIELD_RO("et", 4, 1, 0),
929	DBGFREGSUBFIELD_RW("ne", 5, 1, 0),
930	DBGFREGSUBFIELD_RW("wp", 16, 1, 0),
931	DBGFREGSUBFIELD_RW("am", 18, 1, 0),
932	DBGFREGSUBFIELD_RW("nw", 29, 1, 0),
933	DBGFREGSUBFIELD_RW("cd", 30, 1, 0),
934	DBGFREGSUBFIELD_RW("pg", 31, 1, 0),
935	DBGFREGSUBFIELD_TERMINATOR()
936	};
937
938	/** Sub-fields for the CR3 register. */
939	static DBGFREGSUBFIELD const g_aCpumRegFields_cr3[] =
940	{
941	DBGFREGSUBFIELD_RW("pwt", 3, 1, 0),
942	DBGFREGSUBFIELD_RW("pcd", 4, 1, 0),
943	DBGFREGSUBFIELD_TERMINATOR()
944	};
945
946	/** Sub-fields for the CR4 register. */
947	static DBGFREGSUBFIELD const g_aCpumRegFields_cr4[] =
948	{
949	DBGFREGSUBFIELD_RW("vme", 0, 1, 0),
950	DBGFREGSUBFIELD_RW("pvi", 1, 1, 0),
951	DBGFREGSUBFIELD_RW("tsd", 2, 1, 0),
952	DBGFREGSUBFIELD_RW("de", 3, 1, 0),
953	DBGFREGSUBFIELD_RW("pse", 4, 1, 0),
954	DBGFREGSUBFIELD_RW("pae", 5, 1, 0),
955	DBGFREGSUBFIELD_RW("mce", 6, 1, 0),
956	DBGFREGSUBFIELD_RW("pge", 7, 1, 0),
957	DBGFREGSUBFIELD_RW("pce", 8, 1, 0),
958	DBGFREGSUBFIELD_RW("osfxsr", 9, 1, 0),
959	DBGFREGSUBFIELD_RW("osxmmeexcpt", 10, 1, 0),
960	DBGFREGSUBFIELD_RW("vmxe", 13, 1, 0),
961	DBGFREGSUBFIELD_RW("smxe", 14, 1, 0),
962	DBGFREGSUBFIELD_RW("pcide", 17, 1, 0),
963	DBGFREGSUBFIELD_RW("osxsave", 18, 1, 0),
964	DBGFREGSUBFIELD_RW("smep", 20, 1, 0),
965	DBGFREGSUBFIELD_RW("smap", 21, 1, 0),
966	DBGFREGSUBFIELD_TERMINATOR()
967	};
968
969	/** Sub-fields for the DR6 register. */
970	static DBGFREGSUBFIELD const g_aCpumRegFields_dr6[] =
971	{
972	DBGFREGSUBFIELD_RW("b0", 0, 1, 0),
973	DBGFREGSUBFIELD_RW("b1", 1, 1, 0),
974	DBGFREGSUBFIELD_RW("b2", 2, 1, 0),
975	DBGFREGSUBFIELD_RW("b3", 3, 1, 0),
976	DBGFREGSUBFIELD_RW("bd", 13, 1, 0),
977	DBGFREGSUBFIELD_RW("bs", 14, 1, 0),
978	DBGFREGSUBFIELD_RW("bt", 15, 1, 0),
979	DBGFREGSUBFIELD_TERMINATOR()
980	};
981
982	/** Sub-fields for the DR7 register. */
983	static DBGFREGSUBFIELD const g_aCpumRegFields_dr7[] =
984	{
985	DBGFREGSUBFIELD_RW("l0", 0, 1, 0),
986	DBGFREGSUBFIELD_RW("g0", 1, 1, 0),
987	DBGFREGSUBFIELD_RW("l1", 2, 1, 0),
988	DBGFREGSUBFIELD_RW("g1", 3, 1, 0),
989	DBGFREGSUBFIELD_RW("l2", 4, 1, 0),
990	DBGFREGSUBFIELD_RW("g2", 5, 1, 0),
991	DBGFREGSUBFIELD_RW("l3", 6, 1, 0),
992	DBGFREGSUBFIELD_RW("g3", 7, 1, 0),
993	DBGFREGSUBFIELD_RW("le", 8, 1, 0),
994	DBGFREGSUBFIELD_RW("ge", 9, 1, 0),
995	DBGFREGSUBFIELD_RW("gd", 13, 1, 0),
996	DBGFREGSUBFIELD_RW("rw0", 16, 2, 0),
997	DBGFREGSUBFIELD_RW("len0", 18, 2, 0),
998	DBGFREGSUBFIELD_RW("rw1", 20, 2, 0),
999	DBGFREGSUBFIELD_RW("len1", 22, 2, 0),
1000	DBGFREGSUBFIELD_RW("rw2", 24, 2, 0),
1001	DBGFREGSUBFIELD_RW("len2", 26, 2, 0),
1002	DBGFREGSUBFIELD_RW("rw3", 28, 2, 0),
1003	DBGFREGSUBFIELD_RW("len3", 30, 2, 0),
1004	DBGFREGSUBFIELD_TERMINATOR()
1005	};
1006
1007	/** Sub-fields for the CR_PAT MSR. */
1008	static DBGFREGSUBFIELD const g_aCpumRegFields_apic_base[] =
1009	{
1010	DBGFREGSUBFIELD_RW("bsp", 8, 1, 0),
1011	DBGFREGSUBFIELD_RW("ge", 9, 1, 0),
1012	DBGFREGSUBFIELD_RW("base", 12, 20, 12),
1013	DBGFREGSUBFIELD_TERMINATOR()
1014	};
1015
1016	/** Sub-fields for the CR_PAT MSR. */
1017	static DBGFREGSUBFIELD const g_aCpumRegFields_cr_pat[] =
1018	{
1019	/** @todo */
1020	DBGFREGSUBFIELD_TERMINATOR()
1021	};
1022
1023	/** Sub-fields for the PERF_STATUS MSR. */
1024	static DBGFREGSUBFIELD const g_aCpumRegFields_perf_status[] =
1025	{
1026	/** @todo */
1027	DBGFREGSUBFIELD_TERMINATOR()
1028	};
1029
1030	/** Sub-fields for the EFER MSR. */
1031	static DBGFREGSUBFIELD const g_aCpumRegFields_efer[] =
1032	{
1033	/** @todo */
1034	DBGFREGSUBFIELD_TERMINATOR()
1035	};
1036
1037	/** Sub-fields for the STAR MSR. */
1038	static DBGFREGSUBFIELD const g_aCpumRegFields_star[] =
1039	{
1040	/** @todo */
1041	DBGFREGSUBFIELD_TERMINATOR()
1042	};
1043
1044	/** Sub-fields for the CSTAR MSR. */
1045	static DBGFREGSUBFIELD const g_aCpumRegFields_cstar[] =
1046	{
1047	/** @todo */
1048	DBGFREGSUBFIELD_TERMINATOR()
1049	};
1050
1051	/** Sub-fields for the LSTAR MSR. */
1052	static DBGFREGSUBFIELD const g_aCpumRegFields_lstar[] =
1053	{
1054	/** @todo */
1055	DBGFREGSUBFIELD_TERMINATOR()
1056	};
1057
1058	#if 0 /** @todo */
1059	/** Sub-fields for the SF_MASK MSR. */
1060	static DBGFREGSUBFIELD const g_aCpumRegFields_sf_mask[] =
1061	{
1062	/** @todo */
1063	DBGFREGSUBFIELD_TERMINATOR()
1064	};
1065	#endif
1066
1067
1068	/** @name Macros for producing register descriptor table entries.
1069	* @{ */
1070	#define CPU_REG_EX_AS(a_szName, a_RegSuff, a_TypeSuff, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1071	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1072
1073	#define CPU_REG_REG(UName, LName) \
1074	CPU_REG_RW_AS(#LName, UName, U64, LName, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_##LName, NULL)
1075
1076	#define CPU_REG_SEG(UName, LName) \
1077	CPU_REG_RW_AS(#LName, UName, U16, LName.Sel, cpumR3RegGet_Generic, cpumR3RegSet_seg, NULL, NULL ), \
1078	CPU_REG_RW_AS(#LName "_attr", UName##_ATTR, U32, LName.Attr.u, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_seg), \
1079	CPU_REG_RW_AS(#LName "_base", UName##_BASE, U64, LName.u64Base, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), \
1080	CPU_REG_RW_AS(#LName "_lim", UName##_LIMIT, U32, LName.u32Limit, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL )
1081
1082	#define CPU_REG_MM(n) \
1083	CPU_REG_XS_RW_AS("mm" #n, MM##n, U64, x87.aRegs[n].mmx, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_mmN)
1084
1085	#define CPU_REG_XMM(n) \
1086	CPU_REG_XS_RW_AS("xmm" #n, XMM##n, U128, x87.aXMM[n].xmm, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_xmmN)
1087
1088	#define CPU_REG_YMM(n) \
1089	{ "ymm" #n, DBGFREG_YMM##n, DBGFREGVALTYPE_U256, 0 /fFlags/, n, cpumR3RegGet_ymm, cpumR3RegSet_ymm, NULL /paAliases/, NULL /paSubFields/ }
1090
1091	/** @} */
1092
1093
1094	/**
1095	* The guest register descriptors.
1096	*/
1097	static DBGFREGDESC const g_aCpumRegGstDescs[] =
1098	{
1099	#define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1100	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1101	#define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1102	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1103	#define CPU_REG_XS_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_XStateMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1104	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, RT_OFFSETOF(X86XSAVEAREA, a_XStateMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1105	#define CPU_REG_XS_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_XStateMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1106	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(X86XSAVEAREA, a_XStateMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1107	#define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \
1108	CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegGstGet_msr, cpumR3RegGstSet_msr, NULL, a_paSubFields)
1109	#define CPU_REG_ST(n) \
1110	CPU_REG_EX_AS("st" #n, ST##n, R80, n, cpumR3RegGstGet_stN, cpumR3RegGstSet_stN, NULL, g_aCpumRegFields_stN)
1111
1112	CPU_REG_REG(RAX, rax),
1113	CPU_REG_REG(RCX, rcx),
1114	CPU_REG_REG(RDX, rdx),
1115	CPU_REG_REG(RBX, rbx),
1116	CPU_REG_REG(RSP, rsp),
1117	CPU_REG_REG(RBP, rbp),
1118	CPU_REG_REG(RSI, rsi),
1119	CPU_REG_REG(RDI, rdi),
1120	CPU_REG_REG(R8, r8),
1121	CPU_REG_REG(R9, r9),
1122	CPU_REG_REG(R10, r10),
1123	CPU_REG_REG(R11, r11),
1124	CPU_REG_REG(R12, r12),
1125	CPU_REG_REG(R13, r13),
1126	CPU_REG_REG(R14, r14),
1127	CPU_REG_REG(R15, r15),
1128	CPU_REG_SEG(CS, cs),
1129	CPU_REG_SEG(DS, ds),
1130	CPU_REG_SEG(ES, es),
1131	CPU_REG_SEG(FS, fs),
1132	CPU_REG_SEG(GS, gs),
1133	CPU_REG_SEG(SS, ss),
1134	CPU_REG_REG(RIP, rip),
1135	CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ),
1136	CPU_REG_XS_RW_AS("fcw", FCW, U16, x87.FCW, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_fcw ),
1137	CPU_REG_XS_RW_AS("fsw", FSW, U16, x87.FSW, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_fsw ),
1138	CPU_REG_XS_RO_AS("ftw", FTW, U16, x87, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ),
1139	CPU_REG_XS_RW_AS("fop", FOP, U16, x87.FOP, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, NULL ),
1140	CPU_REG_XS_RW_AS("fpuip", FPUIP, U32, x87.FPUIP, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, g_aCpumRegAliases_fpuip, NULL ),
1141	CPU_REG_XS_RW_AS("fpucs", FPUCS, U16, x87.CS, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, NULL ),
1142	CPU_REG_XS_RW_AS("fpudp", FPUDP, U32, x87.FPUDP, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, g_aCpumRegAliases_fpudp, NULL ),
1143	CPU_REG_XS_RW_AS("fpuds", FPUDS, U16, x87.DS, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, NULL ),
1144	CPU_REG_XS_RW_AS("mxcsr", MXCSR, U32, x87.MXCSR, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_mxcsr ),
1145	CPU_REG_XS_RW_AS("mxcsr_mask", MXCSR_MASK, U32, x87.MXCSR_MASK, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_mxcsr ),
1146	CPU_REG_ST(0),
1147	CPU_REG_ST(1),
1148	CPU_REG_ST(2),
1149	CPU_REG_ST(3),
1150	CPU_REG_ST(4),
1151	CPU_REG_ST(5),
1152	CPU_REG_ST(6),
1153	CPU_REG_ST(7),
1154	CPU_REG_MM(0),
1155	CPU_REG_MM(1),
1156	CPU_REG_MM(2),
1157	CPU_REG_MM(3),
1158	CPU_REG_MM(4),
1159	CPU_REG_MM(5),
1160	CPU_REG_MM(6),
1161	CPU_REG_MM(7),
1162	CPU_REG_XMM(0),
1163	CPU_REG_XMM(1),
1164	CPU_REG_XMM(2),
1165	CPU_REG_XMM(3),
1166	CPU_REG_XMM(4),
1167	CPU_REG_XMM(5),
1168	CPU_REG_XMM(6),
1169	CPU_REG_XMM(7),
1170	CPU_REG_XMM(8),
1171	CPU_REG_XMM(9),
1172	CPU_REG_XMM(10),
1173	CPU_REG_XMM(11),
1174	CPU_REG_XMM(12),
1175	CPU_REG_XMM(13),
1176	CPU_REG_XMM(14),
1177	CPU_REG_XMM(15),
1178	CPU_REG_YMM(0),
1179	CPU_REG_YMM(1),
1180	CPU_REG_YMM(2),
1181	CPU_REG_YMM(3),
1182	CPU_REG_YMM(4),
1183	CPU_REG_YMM(5),
1184	CPU_REG_YMM(6),
1185	CPU_REG_YMM(7),
1186	CPU_REG_YMM(8),
1187	CPU_REG_YMM(9),
1188	CPU_REG_YMM(10),
1189	CPU_REG_YMM(11),
1190	CPU_REG_YMM(12),
1191	CPU_REG_YMM(13),
1192	CPU_REG_YMM(14),
1193	CPU_REG_YMM(15),
1194	CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1195	CPU_REG_RW_AS("gdtr_lim", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1196	CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1197	CPU_REG_RW_AS("idtr_lim", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1198	CPU_REG_SEG(LDTR, ldtr),
1199	CPU_REG_SEG(TR, tr),
1200	CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ),
1201	CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
1202	CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr3 ),
1203	CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr4 ),
1204	CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
1205	CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1206	CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1207	CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1208	CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1209	CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr6 ),
1210	CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr7 ),
1211	CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ),
1212	CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ),
1213	CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status),
1214	CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ),
1215	CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ),
1216	CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ),
1217	CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ),
1218	CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ),
1219	CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ),
1220	CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ),
1221	CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ),
1222	CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ),
1223	CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ),
1224	CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ),
1225	CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ),
1226	CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ),
1227	CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Guest.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1228	CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Guest.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1229	CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Guest.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1230	CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Guest.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1231	CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
1232	CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ),
1233	DBGFREGDESC_TERMINATOR()
1234
1235	#undef CPU_REG_RW_AS
1236	#undef CPU_REG_RO_AS
1237	#undef CPU_REG_MSR
1238	#undef CPU_REG_ST
1239	};
1240
1241
1242	/**
1243	* Initializes the debugger related sides of the CPUM component.
1244	*
1245	* Called by CPUMR3Init.
1246	*
1247	* @returns VBox status code.
1248	* @param pVM The cross context VM structure.
1249	*/
1250	int cpumR3DbgInit(PVM pVM)
1251	{
1252	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1253	{
1254	int rc = DBGFR3RegRegisterCpu(pVM, pVM->apCpusR3[idCpu], g_aCpumRegGstDescs, true /fGuestRegs/);
1255	AssertLogRelRCReturn(rc, rc);
1256	}
1257
1258	return VINF_SUCCESS;
1259	}
1260

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp@ 81150

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