VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp@ 80191

Last change on this file since 80191 was 80191, checked in by vboxsync, 6 years ago

VMM/r3: Refactored VMCPU enumeration in preparation that aCpus will be replaced with a pointer array. Removed two raw-mode offset members from the CPUM and CPUMCPU sub-structures. bugref:9217 bugref:9517
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1/* $Id: CPUMDbg.cpp 80191 2019-08-08 00:36:57Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager, Debugger & Debugging APIs.
4 */
5
6/*
7 * Copyright (C) 2010-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define VBOX_BUGREF_9217_PART_I
23#define LOG_GROUP LOG_GROUP_DBGF
24#include <VBox/vmm/cpum.h>
25#include <VBox/vmm/dbgf.h>
26#include <VBox/vmm/apic.h>
27#include "CPUMInternal.h"
28#include <VBox/vmm/vm.h>
29#include <VBox/param.h>
30#include <VBox/err.h>
31#include <VBox/log.h>
32#include <iprt/thread.h>
33#include <iprt/string.h>
34#include <iprt/uint128.h>
35
36
37/**
38 * @interface_method_impl{DBGFREGDESC,pfnGet}
39 */
40static DECLCALLBACK(int) cpumR3RegGet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
41{
42 PVMCPU pVCpu = (PVMCPU)pvUser;
43 void const *pv = (uint8_t const *)&pVCpu->cpum + pDesc->offRegister;
44
45 VMCPU_ASSERT_EMT(pVCpu);
46
47 switch (pDesc->enmType)
48 {
49 case DBGFREGVALTYPE_U8: pValue->u8 = *(uint8_t const *)pv; return VINF_SUCCESS;
50 case DBGFREGVALTYPE_U16: pValue->u16 = *(uint16_t const *)pv; return VINF_SUCCESS;
51 case DBGFREGVALTYPE_U32: pValue->u32 = *(uint32_t const *)pv; return VINF_SUCCESS;
52 case DBGFREGVALTYPE_U64: pValue->u64 = *(uint64_t const *)pv; return VINF_SUCCESS;
53 case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS;
54 case DBGFREGVALTYPE_U256: pValue->u256 = *(PCRTUINT256U )pv; return VINF_SUCCESS;
55 case DBGFREGVALTYPE_U512: pValue->u512 = *(PCRTUINT512U )pv; return VINF_SUCCESS;
56 default:
57 AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
58 }
59}
60
61
62/**
63 * @interface_method_impl{DBGFREGDESC,pfnSet}
64 */
65static DECLCALLBACK(int) cpumR3RegSet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
66{
67 PVMCPU pVCpu = (PVMCPU)pvUser;
68 void *pv = (uint8_t *)&pVCpu->cpum + pDesc->offRegister;
69
70 VMCPU_ASSERT_EMT(pVCpu);
71
72 switch (pDesc->enmType)
73 {
74 case DBGFREGVALTYPE_U8:
75 *(uint8_t *)pv &= ~pfMask->u8;
76 *(uint8_t *)pv |= pValue->u8 & pfMask->u8;
77 return VINF_SUCCESS;
78
79 case DBGFREGVALTYPE_U16:
80 *(uint16_t *)pv &= ~pfMask->u16;
81 *(uint16_t *)pv |= pValue->u16 & pfMask->u16;
82 return VINF_SUCCESS;
83
84 case DBGFREGVALTYPE_U32:
85 *(uint32_t *)pv &= ~pfMask->u32;
86 *(uint32_t *)pv |= pValue->u32 & pfMask->u32;
87 return VINF_SUCCESS;
88
89 case DBGFREGVALTYPE_U64:
90 *(uint64_t *)pv &= ~pfMask->u64;
91 *(uint64_t *)pv |= pValue->u64 & pfMask->u64;
92 return VINF_SUCCESS;
93
94 case DBGFREGVALTYPE_U128:
95 {
96 RTUINT128U Val;
97 RTUInt128AssignAnd((PRTUINT128U)pv, RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u128)));
98 RTUInt128AssignOr((PRTUINT128U)pv, RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
99 return VINF_SUCCESS;
100 }
101
102 default:
103 AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
104 }
105}
106
107
108/**
109 * @interface_method_impl{DBGFREGDESC,pfnGet}
110 */
111static DECLCALLBACK(int) cpumR3RegGet_XStateGeneric(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
112{
113 PVMCPU pVCpu = (PVMCPU)pvUser;
114 void const *pv = (uint8_t const *)&pVCpu->cpum.s.Guest.pXStateR3 + pDesc->offRegister;
115
116 VMCPU_ASSERT_EMT(pVCpu);
117
118 switch (pDesc->enmType)
119 {
120 case DBGFREGVALTYPE_U8: pValue->u8 = *(uint8_t const *)pv; return VINF_SUCCESS;
121 case DBGFREGVALTYPE_U16: pValue->u16 = *(uint16_t const *)pv; return VINF_SUCCESS;
122 case DBGFREGVALTYPE_U32: pValue->u32 = *(uint32_t const *)pv; return VINF_SUCCESS;
123 case DBGFREGVALTYPE_U64: pValue->u64 = *(uint64_t const *)pv; return VINF_SUCCESS;
124 case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS;
125 default:
126 AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
127 }
128}
129
130
131/**
132 * @interface_method_impl{DBGFREGDESC,pfnSet}
133 */
134static DECLCALLBACK(int) cpumR3RegSet_XStateGeneric(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
135{
136 PVMCPU pVCpu = (PVMCPU)pvUser;
137 void *pv = (uint8_t *)&pVCpu->cpum.s.Guest.pXStateR3 + pDesc->offRegister;
138
139 VMCPU_ASSERT_EMT(pVCpu);
140
141 switch (pDesc->enmType)
142 {
143 case DBGFREGVALTYPE_U8:
144 *(uint8_t *)pv &= ~pfMask->u8;
145 *(uint8_t *)pv |= pValue->u8 & pfMask->u8;
146 return VINF_SUCCESS;
147
148 case DBGFREGVALTYPE_U16:
149 *(uint16_t *)pv &= ~pfMask->u16;
150 *(uint16_t *)pv |= pValue->u16 & pfMask->u16;
151 return VINF_SUCCESS;
152
153 case DBGFREGVALTYPE_U32:
154 *(uint32_t *)pv &= ~pfMask->u32;
155 *(uint32_t *)pv |= pValue->u32 & pfMask->u32;
156 return VINF_SUCCESS;
157
158 case DBGFREGVALTYPE_U64:
159 *(uint64_t *)pv &= ~pfMask->u64;
160 *(uint64_t *)pv |= pValue->u64 & pfMask->u64;
161 return VINF_SUCCESS;
162
163 case DBGFREGVALTYPE_U128:
164 {
165 RTUINT128U Val;
166 RTUInt128AssignAnd((PRTUINT128U)pv, RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u128)));
167 RTUInt128AssignOr((PRTUINT128U)pv, RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
168 return VINF_SUCCESS;
169 }
170
171 default:
172 AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
173 }
174}
175
176
177
178/**
179 * @interface_method_impl{DBGFREGDESC,pfnGet}
180 */
181static DECLCALLBACK(int) cpumR3RegSet_seg(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
182{
183 /** @todo perform a selector load, updating hidden selectors and stuff. */
184 NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
185 return VERR_NOT_IMPLEMENTED;
186}
187
188
189/**
190 * @interface_method_impl{DBGFREGDESC,pfnGet}
191 */
192static DECLCALLBACK(int) cpumR3RegGet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
193{
194 PVMCPU pVCpu = (PVMCPU)pvUser;
195 VBOXGDTR const *pGdtr = (VBOXGDTR const *)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
196
197 VMCPU_ASSERT_EMT(pVCpu);
198 Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
199
200 pValue->dtr.u32Limit = pGdtr->cbGdt;
201 pValue->dtr.u64Base = pGdtr->pGdt;
202 return VINF_SUCCESS;
203}
204
205
206/**
207 * @interface_method_impl{DBGFREGDESC,pfnGet}
208 */
209static DECLCALLBACK(int) cpumR3RegSet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
210{
211 NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
212 return VERR_NOT_IMPLEMENTED;
213}
214
215
216/**
217 * @interface_method_impl{DBGFREGDESC,pfnGet}
218 */
219static DECLCALLBACK(int) cpumR3RegGet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
220{
221 PVMCPU pVCpu = (PVMCPU)pvUser;
222 VBOXIDTR const *pIdtr = (VBOXIDTR const *)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
223
224 VMCPU_ASSERT_EMT(pVCpu);
225 Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
226
227 pValue->dtr.u32Limit = pIdtr->cbIdt;
228 pValue->dtr.u64Base = pIdtr->pIdt;
229 return VINF_SUCCESS;
230}
231
232
233/**
234 * @interface_method_impl{DBGFREGDESC,pfnGet}
235 */
236static DECLCALLBACK(int) cpumR3RegSet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
237{
238 NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
239 return VERR_NOT_IMPLEMENTED;
240}
241
242
243/**
244 * Determins the tag register value for a CPU register when the FPU state
245 * format is FXSAVE.
246 *
247 * @returns The tag register value.
248 * @param pFpu Pointer to the guest FPU.
249 * @param iReg The register number (0..7).
250 */
251DECLINLINE(uint16_t) cpumR3RegCalcFpuTagFromFxSave(PCX86FXSTATE pFpu, unsigned iReg)
252{
253 /*
254 * See table 11-1 in the AMD docs.
255 */
256 if (!(pFpu->FTW & RT_BIT_32(iReg)))
257 return 3; /* b11 - empty */
258
259 uint16_t const uExp = pFpu->aRegs[iReg].au16[4];
260 if (uExp == 0)
261 {
262 if (pFpu->aRegs[iReg].au64[0] == 0) /* J & M == 0 */
263 return 1; /* b01 - zero */
264 return 2; /* b10 - special */
265 }
266
267 if (uExp == UINT16_C(0xffff))
268 return 2; /* b10 - special */
269
270 if (!(pFpu->aRegs[iReg].au64[0] >> 63)) /* J == 0 */
271 return 2; /* b10 - special */
272
273 return 0; /* b00 - valid (normal) */
274}
275
276
277/**
278 * @interface_method_impl{DBGFREGDESC,pfnGet}
279 */
280static DECLCALLBACK(int) cpumR3RegGet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
281{
282 PVMCPU pVCpu = (PVMCPU)pvUser;
283 PCX86FXSTATE pFpu = (PCX86FXSTATE)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
284
285 VMCPU_ASSERT_EMT(pVCpu);
286 Assert(pDesc->enmType == DBGFREGVALTYPE_U16);
287
288 pValue->u16 = cpumR3RegCalcFpuTagFromFxSave(pFpu, 0)
289 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 1) << 2)
290 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 2) << 4)
291 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 3) << 6)
292 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 4) << 8)
293 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 5) << 10)
294 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 6) << 12)
295 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 7) << 14);
296 return VINF_SUCCESS;
297}
298
299
300/**
301 * @interface_method_impl{DBGFREGDESC,pfnGet}
302 */
303static DECLCALLBACK(int) cpumR3RegSet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
304{
305 NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
306 return VERR_DBGF_READ_ONLY_REGISTER;
307}
308
309#if 0 /* unused */
310
311/**
312 * @interface_method_impl{DBGFREGDESC,pfnGet}
313 */
314static DECLCALLBACK(int) cpumR3RegGet_Dummy(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
315{
316 RT_NOREF_PV(pvUser);
317 switch (pDesc->enmType)
318 {
319 case DBGFREGVALTYPE_U8: pValue->u8 = 0; return VINF_SUCCESS;
320 case DBGFREGVALTYPE_U16: pValue->u16 = 0; return VINF_SUCCESS;
321 case DBGFREGVALTYPE_U32: pValue->u32 = 0; return VINF_SUCCESS;
322 case DBGFREGVALTYPE_U64: pValue->u64 = 0; return VINF_SUCCESS;
323 case DBGFREGVALTYPE_U128:
324 RT_ZERO(pValue->u128);
325 return VINF_SUCCESS;
326 case DBGFREGVALTYPE_DTR:
327 pValue->dtr.u32Limit = 0;
328 pValue->dtr.u64Base = 0;
329 return VINF_SUCCESS;
330 case DBGFREGVALTYPE_R80:
331 RT_ZERO(pValue->r80Ex);
332 return VINF_SUCCESS;
333 default:
334 AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
335 }
336}
337
338
339/**
340 * @interface_method_impl{DBGFREGDESC,pfnSet}
341 */
342static DECLCALLBACK(int) cpumR3RegSet_Dummy(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
343{
344 NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
345 return VERR_DBGF_READ_ONLY_REGISTER;
346}
347
348#endif /* unused */
349
350/**
351 * @interface_method_impl{DBGFREGDESC,pfnGet}
352 */
353static DECLCALLBACK(int) cpumR3RegGet_ymm(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
354{
355 PVMCPU pVCpu = (PVMCPU)pvUser;
356 uint32_t iReg = pDesc->offRegister;
357
358 Assert(pDesc->enmType == DBGFREGVALTYPE_U256);
359 VMCPU_ASSERT_EMT(pVCpu);
360
361 if (iReg < 16)
362 {
363 pValue->u256.DQWords.dqw0 = pVCpu->cpum.s.Guest.pXStateR3->x87.aXMM[iReg].uXmm;
364 pValue->u256.DQWords.dqw1 = pVCpu->cpum.s.Guest.pXStateR3->u.YmmHi.aYmmHi[iReg].uXmm;
365 return VINF_SUCCESS;
366 }
367 return VERR_NOT_IMPLEMENTED;
368}
369
370
371/**
372 * @interface_method_impl{DBGFREGDESC,pfnSet}
373 */
374static DECLCALLBACK(int) cpumR3RegSet_ymm(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
375{
376 PVMCPU pVCpu = (PVMCPU)pvUser;
377 uint32_t iReg = pDesc->offRegister;
378
379 Assert(pDesc->enmType == DBGFREGVALTYPE_U256);
380 VMCPU_ASSERT_EMT(pVCpu);
381
382 if (iReg < 16)
383 {
384 RTUINT128U Val;
385 RTUInt128AssignAnd(&pVCpu->cpum.s.Guest.pXStateR3->x87.aXMM[iReg].uXmm,
386 RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u256.DQWords.dqw0)));
387 RTUInt128AssignOr(&pVCpu->cpum.s.Guest.pXStateR3->u.YmmHi.aYmmHi[iReg].uXmm,
388 RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
389
390 }
391 return VERR_NOT_IMPLEMENTED;
392}
393
394
395/*
396 *
397 * Guest register access functions.
398 *
399 */
400
401/**
402 * @interface_method_impl{DBGFREGDESC,pfnGet}
403 */
404static DECLCALLBACK(int) cpumR3RegGstGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
405{
406 PVMCPU pVCpu = (PVMCPU)pvUser;
407 VMCPU_ASSERT_EMT(pVCpu);
408
409 uint64_t u64Value;
410 int rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64Value);
411 if (rc == VERR_PDM_NO_APIC_INSTANCE) /* CR8 might not be available, see @bugref{8868}.*/
412 u64Value = 0;
413 else
414 AssertRCReturn(rc, rc);
415 switch (pDesc->enmType)
416 {
417 case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
418 case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
419 default:
420 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
421 }
422 return VINF_SUCCESS;
423}
424
425
426/**
427 * @interface_method_impl{DBGFREGDESC,pfnGet}
428 */
429static DECLCALLBACK(int) cpumR3RegGstSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
430{
431 int rc;
432 PVMCPU pVCpu = (PVMCPU)pvUser;
433
434 VMCPU_ASSERT_EMT(pVCpu);
435
436 /*
437 * Calculate the new value.
438 */
439 uint64_t u64Value;
440 uint64_t fMask;
441 uint64_t fMaskMax;
442 switch (pDesc->enmType)
443 {
444 case DBGFREGVALTYPE_U64:
445 u64Value = pValue->u64;
446 fMask = pfMask->u64;
447 fMaskMax = UINT64_MAX;
448 break;
449 case DBGFREGVALTYPE_U32:
450 u64Value = pValue->u32;
451 fMask = pfMask->u32;
452 fMaskMax = UINT32_MAX;
453 break;
454 default:
455 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
456 }
457 if (fMask != fMaskMax)
458 {
459 uint64_t u64FullValue;
460 rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64FullValue);
461 if (RT_FAILURE(rc))
462 return rc;
463 u64Value = (u64FullValue & ~fMask)
464 | (u64Value & fMask);
465 }
466
467 /*
468 * Perform the assignment.
469 */
470 switch (pDesc->offRegister)
471 {
472 case 0: rc = CPUMSetGuestCR0(pVCpu, u64Value); break;
473 case 2: rc = CPUMSetGuestCR2(pVCpu, u64Value); break;
474 case 3: rc = CPUMSetGuestCR3(pVCpu, u64Value); break;
475 case 4: rc = CPUMSetGuestCR4(pVCpu, u64Value); break;
476 case 8: rc = APICSetTpr(pVCpu, (uint8_t)(u64Value << 4)); break;
477 default:
478 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
479 }
480 return rc;
481}
482
483
484/**
485 * @interface_method_impl{DBGFREGDESC,pfnGet}
486 */
487static DECLCALLBACK(int) cpumR3RegGstGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
488{
489 PVMCPU pVCpu = (PVMCPU)pvUser;
490 VMCPU_ASSERT_EMT(pVCpu);
491
492 uint64_t u64Value;
493 int rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64Value);
494 AssertRCReturn(rc, rc);
495 switch (pDesc->enmType)
496 {
497 case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
498 case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
499 default:
500 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
501 }
502 return VINF_SUCCESS;
503}
504
505
506/**
507 * @interface_method_impl{DBGFREGDESC,pfnGet}
508 */
509static DECLCALLBACK(int) cpumR3RegGstSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
510{
511 int rc;
512 PVMCPU pVCpu = (PVMCPU)pvUser;
513
514 VMCPU_ASSERT_EMT(pVCpu);
515
516 /*
517 * Calculate the new value.
518 */
519 uint64_t u64Value;
520 uint64_t fMask;
521 uint64_t fMaskMax;
522 switch (pDesc->enmType)
523 {
524 case DBGFREGVALTYPE_U64:
525 u64Value = pValue->u64;
526 fMask = pfMask->u64;
527 fMaskMax = UINT64_MAX;
528 break;
529 case DBGFREGVALTYPE_U32:
530 u64Value = pValue->u32;
531 fMask = pfMask->u32;
532 fMaskMax = UINT32_MAX;
533 break;
534 default:
535 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
536 }
537 if (fMask != fMaskMax)
538 {
539 uint64_t u64FullValue;
540 rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64FullValue);
541 if (RT_FAILURE(rc))
542 return rc;
543 u64Value = (u64FullValue & ~fMask)
544 | (u64Value & fMask);
545 }
546
547 /*
548 * Perform the assignment.
549 */
550 return CPUMSetGuestDRx(pVCpu, pDesc->offRegister, u64Value);
551}
552
553
554/**
555 * @interface_method_impl{DBGFREGDESC,pfnGet}
556 */
557static DECLCALLBACK(int) cpumR3RegGstGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
558{
559 PVMCPU pVCpu = (PVMCPU)pvUser;
560 VMCPU_ASSERT_EMT(pVCpu);
561
562 uint64_t u64Value;
563 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64Value);
564 if (rcStrict == VINF_SUCCESS)
565 {
566 switch (pDesc->enmType)
567 {
568 case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
569 case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
570 case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break;
571 default:
572 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
573 }
574 return VBOXSTRICTRC_VAL(rcStrict);
575 }
576
577 /** @todo what to do about errors? */
578 Assert(RT_FAILURE_NP(rcStrict));
579 return VBOXSTRICTRC_VAL(rcStrict);
580}
581
582
583/**
584 * @interface_method_impl{DBGFREGDESC,pfnGet}
585 */
586static DECLCALLBACK(int) cpumR3RegGstSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
587{
588 PVMCPU pVCpu = (PVMCPU)pvUser;
589
590 VMCPU_ASSERT_EMT(pVCpu);
591
592 /*
593 * Calculate the new value.
594 */
595 uint64_t u64Value;
596 uint64_t fMask;
597 uint64_t fMaskMax;
598 switch (pDesc->enmType)
599 {
600 case DBGFREGVALTYPE_U64:
601 u64Value = pValue->u64;
602 fMask = pfMask->u64;
603 fMaskMax = UINT64_MAX;
604 break;
605 case DBGFREGVALTYPE_U32:
606 u64Value = pValue->u32;
607 fMask = pfMask->u32;
608 fMaskMax = UINT32_MAX;
609 break;
610 case DBGFREGVALTYPE_U16:
611 u64Value = pValue->u16;
612 fMask = pfMask->u16;
613 fMaskMax = UINT16_MAX;
614 break;
615 default:
616 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
617 }
618 if (fMask != fMaskMax)
619 {
620 uint64_t u64FullValue;
621 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64FullValue);
622 if (rcStrict != VINF_SUCCESS)
623 {
624 AssertRC(RT_FAILURE_NP(rcStrict));
625 return VBOXSTRICTRC_VAL(rcStrict);
626 }
627 u64Value = (u64FullValue & ~fMask)
628 | (u64Value & fMask);
629 }
630
631 /*
632 * Perform the assignment.
633 */
634 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pDesc->offRegister, u64Value);
635 if (rcStrict == VINF_SUCCESS)
636 return VINF_SUCCESS;
637 AssertRC(RT_FAILURE_NP(rcStrict));
638 return VBOXSTRICTRC_VAL(rcStrict);
639}
640
641
642/**
643 * @interface_method_impl{DBGFREGDESC,pfnGet}
644 */
645static DECLCALLBACK(int) cpumR3RegGstGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
646{
647 PVMCPU pVCpu = (PVMCPU)pvUser;
648 VMCPU_ASSERT_EMT(pVCpu);
649 Assert(pDesc->enmType == DBGFREGVALTYPE_R80);
650
651 PX86FXSTATE pFpuCtx = &pVCpu->cpum.s.Guest.CTX_SUFF(pXState)->x87;
652 unsigned iReg = (pFpuCtx->FSW >> 11) & 7;
653 iReg += pDesc->offRegister;
654 iReg &= 7;
655 pValue->r80Ex = pFpuCtx->aRegs[iReg].r80Ex;
656
657 return VINF_SUCCESS;
658}
659
660
661/**
662 * @interface_method_impl{DBGFREGDESC,pfnGet}
663 */
664static DECLCALLBACK(int) cpumR3RegGstSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
665{
666 NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
667 return VERR_NOT_IMPLEMENTED;
668}
669
670
671
672/*
673 * Set up aliases.
674 */
675#define CPUMREGALIAS_STD(Name, psz32, psz16, psz8) \
676 static DBGFREGALIAS const g_aCpumRegAliases_##Name[] = \
677 { \
678 { psz32, DBGFREGVALTYPE_U32 }, \
679 { psz16, DBGFREGVALTYPE_U16 }, \
680 { psz8, DBGFREGVALTYPE_U8 }, \
681 { NULL, DBGFREGVALTYPE_INVALID } \
682 }
683CPUMREGALIAS_STD(rax, "eax", "ax", "al");
684CPUMREGALIAS_STD(rcx, "ecx", "cx", "cl");
685CPUMREGALIAS_STD(rdx, "edx", "dx", "dl");
686CPUMREGALIAS_STD(rbx, "ebx", "bx", "bl");
687CPUMREGALIAS_STD(rsp, "esp", "sp", NULL);
688CPUMREGALIAS_STD(rbp, "ebp", "bp", NULL);
689CPUMREGALIAS_STD(rsi, "esi", "si", "sil");
690CPUMREGALIAS_STD(rdi, "edi", "di", "dil");
691CPUMREGALIAS_STD(r8, "r8d", "r8w", "r8b");
692CPUMREGALIAS_STD(r9, "r9d", "r9w", "r9b");
693CPUMREGALIAS_STD(r10, "r10d", "r10w", "r10b");
694CPUMREGALIAS_STD(r11, "r11d", "r11w", "r11b");
695CPUMREGALIAS_STD(r12, "r12d", "r12w", "r12b");
696CPUMREGALIAS_STD(r13, "r13d", "r13w", "r13b");
697CPUMREGALIAS_STD(r14, "r14d", "r14w", "r14b");
698CPUMREGALIAS_STD(r15, "r15d", "r15w", "r15b");
699CPUMREGALIAS_STD(rip, "eip", "ip", NULL);
700CPUMREGALIAS_STD(rflags, "eflags", "flags", NULL);
701#undef CPUMREGALIAS_STD
702
703static DBGFREGALIAS const g_aCpumRegAliases_fpuip[] =
704{
705 { "fpuip16", DBGFREGVALTYPE_U16 },
706 { NULL, DBGFREGVALTYPE_INVALID }
707};
708
709static DBGFREGALIAS const g_aCpumRegAliases_fpudp[] =
710{
711 { "fpudp16", DBGFREGVALTYPE_U16 },
712 { NULL, DBGFREGVALTYPE_INVALID }
713};
714
715static DBGFREGALIAS const g_aCpumRegAliases_cr0[] =
716{
717 { "msw", DBGFREGVALTYPE_U16 },
718 { NULL, DBGFREGVALTYPE_INVALID }
719};
720
721/*
722 * Sub fields.
723 */
724/** Sub-fields for the (hidden) segment attribute register. */
725static DBGFREGSUBFIELD const g_aCpumRegFields_seg[] =
726{
727 DBGFREGSUBFIELD_RW("type", 0, 4, 0),
728 DBGFREGSUBFIELD_RW("s", 4, 1, 0),
729 DBGFREGSUBFIELD_RW("dpl", 5, 2, 0),
730 DBGFREGSUBFIELD_RW("p", 7, 1, 0),
731 DBGFREGSUBFIELD_RW("avl", 12, 1, 0),
732 DBGFREGSUBFIELD_RW("l", 13, 1, 0),
733 DBGFREGSUBFIELD_RW("d", 14, 1, 0),
734 DBGFREGSUBFIELD_RW("g", 15, 1, 0),
735 DBGFREGSUBFIELD_TERMINATOR()
736};
737
738/** Sub-fields for the flags register. */
739static DBGFREGSUBFIELD const g_aCpumRegFields_rflags[] =
740{
741 DBGFREGSUBFIELD_RW("cf", 0, 1, 0),
742 DBGFREGSUBFIELD_RW("pf", 2, 1, 0),
743 DBGFREGSUBFIELD_RW("af", 4, 1, 0),
744 DBGFREGSUBFIELD_RW("zf", 6, 1, 0),
745 DBGFREGSUBFIELD_RW("sf", 7, 1, 0),
746 DBGFREGSUBFIELD_RW("tf", 8, 1, 0),
747 DBGFREGSUBFIELD_RW("if", 9, 1, 0),
748 DBGFREGSUBFIELD_RW("df", 10, 1, 0),
749 DBGFREGSUBFIELD_RW("of", 11, 1, 0),
750 DBGFREGSUBFIELD_RW("iopl", 12, 2, 0),
751 DBGFREGSUBFIELD_RW("nt", 14, 1, 0),
752 DBGFREGSUBFIELD_RW("rf", 16, 1, 0),
753 DBGFREGSUBFIELD_RW("vm", 17, 1, 0),
754 DBGFREGSUBFIELD_RW("ac", 18, 1, 0),
755 DBGFREGSUBFIELD_RW("vif", 19, 1, 0),
756 DBGFREGSUBFIELD_RW("vip", 20, 1, 0),
757 DBGFREGSUBFIELD_RW("id", 21, 1, 0),
758 DBGFREGSUBFIELD_TERMINATOR()
759};
760
761/** Sub-fields for the FPU control word register. */
762static DBGFREGSUBFIELD const g_aCpumRegFields_fcw[] =
763{
764 DBGFREGSUBFIELD_RW("im", 1, 1, 0),
765 DBGFREGSUBFIELD_RW("dm", 2, 1, 0),
766 DBGFREGSUBFIELD_RW("zm", 3, 1, 0),
767 DBGFREGSUBFIELD_RW("om", 4, 1, 0),
768 DBGFREGSUBFIELD_RW("um", 5, 1, 0),
769 DBGFREGSUBFIELD_RW("pm", 6, 1, 0),
770 DBGFREGSUBFIELD_RW("pc", 8, 2, 0),
771 DBGFREGSUBFIELD_RW("rc", 10, 2, 0),
772 DBGFREGSUBFIELD_RW("x", 12, 1, 0),
773 DBGFREGSUBFIELD_TERMINATOR()
774};
775
776/** Sub-fields for the FPU status word register. */
777static DBGFREGSUBFIELD const g_aCpumRegFields_fsw[] =
778{
779 DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
780 DBGFREGSUBFIELD_RW("de", 1, 1, 0),
781 DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
782 DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
783 DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
784 DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
785 DBGFREGSUBFIELD_RW("se", 6, 1, 0),
786 DBGFREGSUBFIELD_RW("es", 7, 1, 0),
787 DBGFREGSUBFIELD_RW("c0", 8, 1, 0),
788 DBGFREGSUBFIELD_RW("c1", 9, 1, 0),
789 DBGFREGSUBFIELD_RW("c2", 10, 1, 0),
790 DBGFREGSUBFIELD_RW("top", 11, 3, 0),
791 DBGFREGSUBFIELD_RW("c3", 14, 1, 0),
792 DBGFREGSUBFIELD_RW("b", 15, 1, 0),
793 DBGFREGSUBFIELD_TERMINATOR()
794};
795
796/** Sub-fields for the FPU tag word register. */
797static DBGFREGSUBFIELD const g_aCpumRegFields_ftw[] =
798{
799 DBGFREGSUBFIELD_RW("tag0", 0, 2, 0),
800 DBGFREGSUBFIELD_RW("tag1", 2, 2, 0),
801 DBGFREGSUBFIELD_RW("tag2", 4, 2, 0),
802 DBGFREGSUBFIELD_RW("tag3", 6, 2, 0),
803 DBGFREGSUBFIELD_RW("tag4", 8, 2, 0),
804 DBGFREGSUBFIELD_RW("tag5", 10, 2, 0),
805 DBGFREGSUBFIELD_RW("tag6", 12, 2, 0),
806 DBGFREGSUBFIELD_RW("tag7", 14, 2, 0),
807 DBGFREGSUBFIELD_TERMINATOR()
808};
809
810/** Sub-fields for the Multimedia Extensions Control and Status Register. */
811static DBGFREGSUBFIELD const g_aCpumRegFields_mxcsr[] =
812{
813 DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
814 DBGFREGSUBFIELD_RW("de", 1, 1, 0),
815 DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
816 DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
817 DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
818 DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
819 DBGFREGSUBFIELD_RW("daz", 6, 1, 0),
820 DBGFREGSUBFIELD_RW("im", 7, 1, 0),
821 DBGFREGSUBFIELD_RW("dm", 8, 1, 0),
822 DBGFREGSUBFIELD_RW("zm", 9, 1, 0),
823 DBGFREGSUBFIELD_RW("om", 10, 1, 0),
824 DBGFREGSUBFIELD_RW("um", 11, 1, 0),
825 DBGFREGSUBFIELD_RW("pm", 12, 1, 0),
826 DBGFREGSUBFIELD_RW("rc", 13, 2, 0),
827 DBGFREGSUBFIELD_RW("fz", 14, 1, 0),
828 DBGFREGSUBFIELD_TERMINATOR()
829};
830
831/** Sub-fields for the FPU tag word register. */
832static DBGFREGSUBFIELD const g_aCpumRegFields_stN[] =
833{
834 DBGFREGSUBFIELD_RW("man", 0, 64, 0),
835 DBGFREGSUBFIELD_RW("exp", 64, 15, 0),
836 DBGFREGSUBFIELD_RW("sig", 79, 1, 0),
837 DBGFREGSUBFIELD_TERMINATOR()
838};
839
840/** Sub-fields for the MMX registers. */
841static DBGFREGSUBFIELD const g_aCpumRegFields_mmN[] =
842{
843 DBGFREGSUBFIELD_RW("dw0", 0, 32, 0),
844 DBGFREGSUBFIELD_RW("dw1", 32, 32, 0),
845 DBGFREGSUBFIELD_RW("w0", 0, 16, 0),
846 DBGFREGSUBFIELD_RW("w1", 16, 16, 0),
847 DBGFREGSUBFIELD_RW("w2", 32, 16, 0),
848 DBGFREGSUBFIELD_RW("w3", 48, 16, 0),
849 DBGFREGSUBFIELD_RW("b0", 0, 8, 0),
850 DBGFREGSUBFIELD_RW("b1", 8, 8, 0),
851 DBGFREGSUBFIELD_RW("b2", 16, 8, 0),
852 DBGFREGSUBFIELD_RW("b3", 24, 8, 0),
853 DBGFREGSUBFIELD_RW("b4", 32, 8, 0),
854 DBGFREGSUBFIELD_RW("b5", 40, 8, 0),
855 DBGFREGSUBFIELD_RW("b6", 48, 8, 0),
856 DBGFREGSUBFIELD_RW("b7", 56, 8, 0),
857 DBGFREGSUBFIELD_TERMINATOR()
858};
859
860/** Sub-fields for the XMM registers. */
861static DBGFREGSUBFIELD const g_aCpumRegFields_xmmN[] =
862{
863 DBGFREGSUBFIELD_RW("r0", 0, 32, 0),
864 DBGFREGSUBFIELD_RW("r0.man", 0+ 0, 23, 0),
865 DBGFREGSUBFIELD_RW("r0.exp", 0+23, 8, 0),
866 DBGFREGSUBFIELD_RW("r0.sig", 0+31, 1, 0),
867 DBGFREGSUBFIELD_RW("r1", 32, 32, 0),
868 DBGFREGSUBFIELD_RW("r1.man", 32+ 0, 23, 0),
869 DBGFREGSUBFIELD_RW("r1.exp", 32+23, 8, 0),
870 DBGFREGSUBFIELD_RW("r1.sig", 32+31, 1, 0),
871 DBGFREGSUBFIELD_RW("r2", 64, 32, 0),
872 DBGFREGSUBFIELD_RW("r2.man", 64+ 0, 23, 0),
873 DBGFREGSUBFIELD_RW("r2.exp", 64+23, 8, 0),
874 DBGFREGSUBFIELD_RW("r2.sig", 64+31, 1, 0),
875 DBGFREGSUBFIELD_RW("r3", 96, 32, 0),
876 DBGFREGSUBFIELD_RW("r3.man", 96+ 0, 23, 0),
877 DBGFREGSUBFIELD_RW("r3.exp", 96+23, 8, 0),
878 DBGFREGSUBFIELD_RW("r3.sig", 96+31, 1, 0),
879 DBGFREGSUBFIELD_TERMINATOR()
880};
881
882#if 0 /* needs special accessor, too lazy for that now. */
883/** Sub-fields for the YMM registers. */
884static DBGFREGSUBFIELD const g_aCpumRegFields_ymmN[] =
885{
886 DBGFREGSUBFIELD_RW("r0", 0, 32, 0),
887 DBGFREGSUBFIELD_RW("r0.man", 0+ 0, 23, 0),
888 DBGFREGSUBFIELD_RW("r0.exp", 0+23, 8, 0),
889 DBGFREGSUBFIELD_RW("r0.sig", 0+31, 1, 0),
890 DBGFREGSUBFIELD_RW("r1", 32, 32, 0),
891 DBGFREGSUBFIELD_RW("r1.man", 32+ 0, 23, 0),
892 DBGFREGSUBFIELD_RW("r1.exp", 32+23, 8, 0),
893 DBGFREGSUBFIELD_RW("r1.sig", 32+31, 1, 0),
894 DBGFREGSUBFIELD_RW("r2", 64, 32, 0),
895 DBGFREGSUBFIELD_RW("r2.man", 64+ 0, 23, 0),
896 DBGFREGSUBFIELD_RW("r2.exp", 64+23, 8, 0),
897 DBGFREGSUBFIELD_RW("r2.sig", 64+31, 1, 0),
898 DBGFREGSUBFIELD_RW("r3", 96, 32, 0),
899 DBGFREGSUBFIELD_RW("r3.man", 96+ 0, 23, 0),
900 DBGFREGSUBFIELD_RW("r3.exp", 96+23, 8, 0),
901 DBGFREGSUBFIELD_RW("r3.sig", 96+31, 1, 0),
902 DBGFREGSUBFIELD_RW("r4", 128, 32, 0),
903 DBGFREGSUBFIELD_RW("r4.man", 128+ 0, 23, 0),
904 DBGFREGSUBFIELD_RW("r4.exp", 128+23, 8, 0),
905 DBGFREGSUBFIELD_RW("r4.sig", 128+31, 1, 0),
906 DBGFREGSUBFIELD_RW("r5", 160, 32, 0),
907 DBGFREGSUBFIELD_RW("r5.man", 160+ 0, 23, 0),
908 DBGFREGSUBFIELD_RW("r5.exp", 160+23, 8, 0),
909 DBGFREGSUBFIELD_RW("r5.sig", 160+31, 1, 0),
910 DBGFREGSUBFIELD_RW("r6", 192, 32, 0),
911 DBGFREGSUBFIELD_RW("r6.man", 192+ 0, 23, 0),
912 DBGFREGSUBFIELD_RW("r6.exp", 192+23, 8, 0),
913 DBGFREGSUBFIELD_RW("r6.sig", 192+31, 1, 0),
914 DBGFREGSUBFIELD_RW("r7", 224, 32, 0),
915 DBGFREGSUBFIELD_RW("r7.man", 224+ 0, 23, 0),
916 DBGFREGSUBFIELD_RW("r7.exp", 224+23, 8, 0),
917 DBGFREGSUBFIELD_RW("r7.sig", 224+31, 1, 0),
918 DBGFREGSUBFIELD_TERMINATOR()
919};
920#endif
921
922/** Sub-fields for the CR0 register. */
923static DBGFREGSUBFIELD const g_aCpumRegFields_cr0[] =
924{
925 DBGFREGSUBFIELD_RW("pe", 0, 1, 0),
926 DBGFREGSUBFIELD_RW("mp", 1, 1, 0),
927 DBGFREGSUBFIELD_RW("em", 2, 1, 0),
928 DBGFREGSUBFIELD_RW("ts", 3, 1, 0),
929 DBGFREGSUBFIELD_RO("et", 4, 1, 0),
930 DBGFREGSUBFIELD_RW("ne", 5, 1, 0),
931 DBGFREGSUBFIELD_RW("wp", 16, 1, 0),
932 DBGFREGSUBFIELD_RW("am", 18, 1, 0),
933 DBGFREGSUBFIELD_RW("nw", 29, 1, 0),
934 DBGFREGSUBFIELD_RW("cd", 30, 1, 0),
935 DBGFREGSUBFIELD_RW("pg", 31, 1, 0),
936 DBGFREGSUBFIELD_TERMINATOR()
937};
938
939/** Sub-fields for the CR3 register. */
940static DBGFREGSUBFIELD const g_aCpumRegFields_cr3[] =
941{
942 DBGFREGSUBFIELD_RW("pwt", 3, 1, 0),
943 DBGFREGSUBFIELD_RW("pcd", 4, 1, 0),
944 DBGFREGSUBFIELD_TERMINATOR()
945};
946
947/** Sub-fields for the CR4 register. */
948static DBGFREGSUBFIELD const g_aCpumRegFields_cr4[] =
949{
950 DBGFREGSUBFIELD_RW("vme", 0, 1, 0),
951 DBGFREGSUBFIELD_RW("pvi", 1, 1, 0),
952 DBGFREGSUBFIELD_RW("tsd", 2, 1, 0),
953 DBGFREGSUBFIELD_RW("de", 3, 1, 0),
954 DBGFREGSUBFIELD_RW("pse", 4, 1, 0),
955 DBGFREGSUBFIELD_RW("pae", 5, 1, 0),
956 DBGFREGSUBFIELD_RW("mce", 6, 1, 0),
957 DBGFREGSUBFIELD_RW("pge", 7, 1, 0),
958 DBGFREGSUBFIELD_RW("pce", 8, 1, 0),
959 DBGFREGSUBFIELD_RW("osfxsr", 9, 1, 0),
960 DBGFREGSUBFIELD_RW("osxmmeexcpt", 10, 1, 0),
961 DBGFREGSUBFIELD_RW("vmxe", 13, 1, 0),
962 DBGFREGSUBFIELD_RW("smxe", 14, 1, 0),
963 DBGFREGSUBFIELD_RW("pcide", 17, 1, 0),
964 DBGFREGSUBFIELD_RW("osxsave", 18, 1, 0),
965 DBGFREGSUBFIELD_RW("smep", 20, 1, 0),
966 DBGFREGSUBFIELD_RW("smap", 21, 1, 0),
967 DBGFREGSUBFIELD_TERMINATOR()
968};
969
970/** Sub-fields for the DR6 register. */
971static DBGFREGSUBFIELD const g_aCpumRegFields_dr6[] =
972{
973 DBGFREGSUBFIELD_RW("b0", 0, 1, 0),
974 DBGFREGSUBFIELD_RW("b1", 1, 1, 0),
975 DBGFREGSUBFIELD_RW("b2", 2, 1, 0),
976 DBGFREGSUBFIELD_RW("b3", 3, 1, 0),
977 DBGFREGSUBFIELD_RW("bd", 13, 1, 0),
978 DBGFREGSUBFIELD_RW("bs", 14, 1, 0),
979 DBGFREGSUBFIELD_RW("bt", 15, 1, 0),
980 DBGFREGSUBFIELD_TERMINATOR()
981};
982
983/** Sub-fields for the DR7 register. */
984static DBGFREGSUBFIELD const g_aCpumRegFields_dr7[] =
985{
986 DBGFREGSUBFIELD_RW("l0", 0, 1, 0),
987 DBGFREGSUBFIELD_RW("g0", 1, 1, 0),
988 DBGFREGSUBFIELD_RW("l1", 2, 1, 0),
989 DBGFREGSUBFIELD_RW("g1", 3, 1, 0),
990 DBGFREGSUBFIELD_RW("l2", 4, 1, 0),
991 DBGFREGSUBFIELD_RW("g2", 5, 1, 0),
992 DBGFREGSUBFIELD_RW("l3", 6, 1, 0),
993 DBGFREGSUBFIELD_RW("g3", 7, 1, 0),
994 DBGFREGSUBFIELD_RW("le", 8, 1, 0),
995 DBGFREGSUBFIELD_RW("ge", 9, 1, 0),
996 DBGFREGSUBFIELD_RW("gd", 13, 1, 0),
997 DBGFREGSUBFIELD_RW("rw0", 16, 2, 0),
998 DBGFREGSUBFIELD_RW("len0", 18, 2, 0),
999 DBGFREGSUBFIELD_RW("rw1", 20, 2, 0),
1000 DBGFREGSUBFIELD_RW("len1", 22, 2, 0),
1001 DBGFREGSUBFIELD_RW("rw2", 24, 2, 0),
1002 DBGFREGSUBFIELD_RW("len2", 26, 2, 0),
1003 DBGFREGSUBFIELD_RW("rw3", 28, 2, 0),
1004 DBGFREGSUBFIELD_RW("len3", 30, 2, 0),
1005 DBGFREGSUBFIELD_TERMINATOR()
1006};
1007
1008/** Sub-fields for the CR_PAT MSR. */
1009static DBGFREGSUBFIELD const g_aCpumRegFields_apic_base[] =
1010{
1011 DBGFREGSUBFIELD_RW("bsp", 8, 1, 0),
1012 DBGFREGSUBFIELD_RW("ge", 9, 1, 0),
1013 DBGFREGSUBFIELD_RW("base", 12, 20, 12),
1014 DBGFREGSUBFIELD_TERMINATOR()
1015};
1016
1017/** Sub-fields for the CR_PAT MSR. */
1018static DBGFREGSUBFIELD const g_aCpumRegFields_cr_pat[] =
1019{
1020 /** @todo */
1021 DBGFREGSUBFIELD_TERMINATOR()
1022};
1023
1024/** Sub-fields for the PERF_STATUS MSR. */
1025static DBGFREGSUBFIELD const g_aCpumRegFields_perf_status[] =
1026{
1027 /** @todo */
1028 DBGFREGSUBFIELD_TERMINATOR()
1029};
1030
1031/** Sub-fields for the EFER MSR. */
1032static DBGFREGSUBFIELD const g_aCpumRegFields_efer[] =
1033{
1034 /** @todo */
1035 DBGFREGSUBFIELD_TERMINATOR()
1036};
1037
1038/** Sub-fields for the STAR MSR. */
1039static DBGFREGSUBFIELD const g_aCpumRegFields_star[] =
1040{
1041 /** @todo */
1042 DBGFREGSUBFIELD_TERMINATOR()
1043};
1044
1045/** Sub-fields for the CSTAR MSR. */
1046static DBGFREGSUBFIELD const g_aCpumRegFields_cstar[] =
1047{
1048 /** @todo */
1049 DBGFREGSUBFIELD_TERMINATOR()
1050};
1051
1052/** Sub-fields for the LSTAR MSR. */
1053static DBGFREGSUBFIELD const g_aCpumRegFields_lstar[] =
1054{
1055 /** @todo */
1056 DBGFREGSUBFIELD_TERMINATOR()
1057};
1058
1059#if 0 /** @todo */
1060/** Sub-fields for the SF_MASK MSR. */
1061static DBGFREGSUBFIELD const g_aCpumRegFields_sf_mask[] =
1062{
1063 /** @todo */
1064 DBGFREGSUBFIELD_TERMINATOR()
1065};
1066#endif
1067
1068
1069/** @name Macros for producing register descriptor table entries.
1070 * @{ */
1071#define CPU_REG_EX_AS(a_szName, a_RegSuff, a_TypeSuff, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1072 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /*fFlags*/, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1073
1074#define CPU_REG_REG(UName, LName) \
1075 CPU_REG_RW_AS(#LName, UName, U64, LName, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_##LName, NULL)
1076
1077#define CPU_REG_SEG(UName, LName) \
1078 CPU_REG_RW_AS(#LName, UName, U16, LName.Sel, cpumR3RegGet_Generic, cpumR3RegSet_seg, NULL, NULL ), \
1079 CPU_REG_RW_AS(#LName "_attr", UName##_ATTR, U32, LName.Attr.u, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_seg), \
1080 CPU_REG_RW_AS(#LName "_base", UName##_BASE, U64, LName.u64Base, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), \
1081 CPU_REG_RW_AS(#LName "_lim", UName##_LIMIT, U32, LName.u32Limit, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL )
1082
1083#define CPU_REG_MM(n) \
1084 CPU_REG_XS_RW_AS("mm" #n, MM##n, U64, x87.aRegs[n].mmx, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_mmN)
1085
1086#define CPU_REG_XMM(n) \
1087 CPU_REG_XS_RW_AS("xmm" #n, XMM##n, U128, x87.aXMM[n].xmm, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_xmmN)
1088
1089#define CPU_REG_YMM(n) \
1090 { "ymm" #n, DBGFREG_YMM##n, DBGFREGVALTYPE_U256, 0 /*fFlags*/, n, cpumR3RegGet_ymm, cpumR3RegSet_ymm, NULL /*paAliases*/, NULL /*paSubFields*/ }
1091
1092/** @} */
1093
1094
1095/**
1096 * The guest register descriptors.
1097 */
1098static DBGFREGDESC const g_aCpumRegGstDescs[] =
1099{
1100#define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1101 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /*fFlags*/, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1102#define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1103 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1104#define CPU_REG_XS_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_XStateMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1105 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /*fFlags*/, RT_OFFSETOF(X86XSAVEAREA, a_XStateMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1106#define CPU_REG_XS_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_XStateMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1107 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(X86XSAVEAREA, a_XStateMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1108#define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \
1109 CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegGstGet_msr, cpumR3RegGstSet_msr, NULL, a_paSubFields)
1110#define CPU_REG_ST(n) \
1111 CPU_REG_EX_AS("st" #n, ST##n, R80, n, cpumR3RegGstGet_stN, cpumR3RegGstSet_stN, NULL, g_aCpumRegFields_stN)
1112
1113 CPU_REG_REG(RAX, rax),
1114 CPU_REG_REG(RCX, rcx),
1115 CPU_REG_REG(RDX, rdx),
1116 CPU_REG_REG(RBX, rbx),
1117 CPU_REG_REG(RSP, rsp),
1118 CPU_REG_REG(RBP, rbp),
1119 CPU_REG_REG(RSI, rsi),
1120 CPU_REG_REG(RDI, rdi),
1121 CPU_REG_REG(R8, r8),
1122 CPU_REG_REG(R9, r9),
1123 CPU_REG_REG(R10, r10),
1124 CPU_REG_REG(R11, r11),
1125 CPU_REG_REG(R12, r12),
1126 CPU_REG_REG(R13, r13),
1127 CPU_REG_REG(R14, r14),
1128 CPU_REG_REG(R15, r15),
1129 CPU_REG_SEG(CS, cs),
1130 CPU_REG_SEG(DS, ds),
1131 CPU_REG_SEG(ES, es),
1132 CPU_REG_SEG(FS, fs),
1133 CPU_REG_SEG(GS, gs),
1134 CPU_REG_SEG(SS, ss),
1135 CPU_REG_REG(RIP, rip),
1136 CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ),
1137 CPU_REG_XS_RW_AS("fcw", FCW, U16, x87.FCW, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_fcw ),
1138 CPU_REG_XS_RW_AS("fsw", FSW, U16, x87.FSW, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_fsw ),
1139 CPU_REG_XS_RO_AS("ftw", FTW, U16, x87, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ),
1140 CPU_REG_XS_RW_AS("fop", FOP, U16, x87.FOP, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, NULL ),
1141 CPU_REG_XS_RW_AS("fpuip", FPUIP, U32, x87.FPUIP, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, g_aCpumRegAliases_fpuip, NULL ),
1142 CPU_REG_XS_RW_AS("fpucs", FPUCS, U16, x87.CS, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, NULL ),
1143 CPU_REG_XS_RW_AS("fpudp", FPUDP, U32, x87.FPUDP, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, g_aCpumRegAliases_fpudp, NULL ),
1144 CPU_REG_XS_RW_AS("fpuds", FPUDS, U16, x87.DS, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, NULL ),
1145 CPU_REG_XS_RW_AS("mxcsr", MXCSR, U32, x87.MXCSR, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_mxcsr ),
1146 CPU_REG_XS_RW_AS("mxcsr_mask", MXCSR_MASK, U32, x87.MXCSR_MASK, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_mxcsr ),
1147 CPU_REG_ST(0),
1148 CPU_REG_ST(1),
1149 CPU_REG_ST(2),
1150 CPU_REG_ST(3),
1151 CPU_REG_ST(4),
1152 CPU_REG_ST(5),
1153 CPU_REG_ST(6),
1154 CPU_REG_ST(7),
1155 CPU_REG_MM(0),
1156 CPU_REG_MM(1),
1157 CPU_REG_MM(2),
1158 CPU_REG_MM(3),
1159 CPU_REG_MM(4),
1160 CPU_REG_MM(5),
1161 CPU_REG_MM(6),
1162 CPU_REG_MM(7),
1163 CPU_REG_XMM(0),
1164 CPU_REG_XMM(1),
1165 CPU_REG_XMM(2),
1166 CPU_REG_XMM(3),
1167 CPU_REG_XMM(4),
1168 CPU_REG_XMM(5),
1169 CPU_REG_XMM(6),
1170 CPU_REG_XMM(7),
1171 CPU_REG_XMM(8),
1172 CPU_REG_XMM(9),
1173 CPU_REG_XMM(10),
1174 CPU_REG_XMM(11),
1175 CPU_REG_XMM(12),
1176 CPU_REG_XMM(13),
1177 CPU_REG_XMM(14),
1178 CPU_REG_XMM(15),
1179 CPU_REG_YMM(0),
1180 CPU_REG_YMM(1),
1181 CPU_REG_YMM(2),
1182 CPU_REG_YMM(3),
1183 CPU_REG_YMM(4),
1184 CPU_REG_YMM(5),
1185 CPU_REG_YMM(6),
1186 CPU_REG_YMM(7),
1187 CPU_REG_YMM(8),
1188 CPU_REG_YMM(9),
1189 CPU_REG_YMM(10),
1190 CPU_REG_YMM(11),
1191 CPU_REG_YMM(12),
1192 CPU_REG_YMM(13),
1193 CPU_REG_YMM(14),
1194 CPU_REG_YMM(15),
1195 CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1196 CPU_REG_RW_AS("gdtr_lim", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1197 CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1198 CPU_REG_RW_AS("idtr_lim", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1199 CPU_REG_SEG(LDTR, ldtr),
1200 CPU_REG_SEG(TR, tr),
1201 CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ),
1202 CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
1203 CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr3 ),
1204 CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr4 ),
1205 CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
1206 CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1207 CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1208 CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1209 CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1210 CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr6 ),
1211 CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr7 ),
1212 CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ),
1213 CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ),
1214 CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status),
1215 CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ),
1216 CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ),
1217 CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ),
1218 CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ),
1219 CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ),
1220 CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ),
1221 CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ),
1222 CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ),
1223 CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ),
1224 CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ),
1225 CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ),
1226 CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ),
1227 CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ),
1228 CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Guest.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1229 CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Guest.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1230 CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Guest.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1231 CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Guest.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1232 CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
1233 CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ),
1234 DBGFREGDESC_TERMINATOR()
1235
1236#undef CPU_REG_RW_AS
1237#undef CPU_REG_RO_AS
1238#undef CPU_REG_MSR
1239#undef CPU_REG_ST
1240};
1241
1242
1243/**
1244 * Initializes the debugger related sides of the CPUM component.
1245 *
1246 * Called by CPUMR3Init.
1247 *
1248 * @returns VBox status code.
1249 * @param pVM The cross context VM structure.
1250 */
1251int cpumR3DbgInit(PVM pVM)
1252{
1253 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1254 {
1255 int rc = DBGFR3RegRegisterCpu(pVM, pVM->apCpusR3[idCpu], g_aCpumRegGstDescs, true /*fGuestRegs*/);
1256 AssertLogRelRCReturn(rc, rc);
1257 }
1258
1259 return VINF_SUCCESS;
1260}
1261
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