CPUMDbg.cpp@ 62639

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1	/* $Id: CPUMDbg.cpp 62637 2016-07-28 17:12:17Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager, Debugger & Debugging APIs.
4	*/
5
6	/*
7	* Copyright (C) 2010-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DBGF
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/pdmapi.h>
26	#include "CPUMInternal.h"
27	#include <VBox/vmm/vm.h>
28	#include <VBox/param.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/thread.h>
32	#include <iprt/string.h>
33	#include <iprt/uint128.h>
34
35
36	/**
37	* @interface_method_impl{DBGFREGDESC,pfnGet}
38	*/
39	static DECLCALLBACK(int) cpumR3RegGet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
40	{
41	PVMCPU pVCpu = (PVMCPU)pvUser;
42	void const pv = (uint8_t const )&pVCpu->cpum + pDesc->offRegister;
43
44	VMCPU_ASSERT_EMT(pVCpu);
45
46	switch (pDesc->enmType)
47	{
48	case DBGFREGVALTYPE_U8: pValue->u8 = (uint8_t const )pv; return VINF_SUCCESS;
49	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t const )pv; return VINF_SUCCESS;
50	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t const )pv; return VINF_SUCCESS;
51	case DBGFREGVALTYPE_U64: pValue->u64 = (uint64_t const )pv; return VINF_SUCCESS;
52	case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS;
53	default:
54	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
55	}
56	}
57
58
59	/**
60	* @interface_method_impl{DBGFREGDESC,pfnSet}
61	*/
62	static DECLCALLBACK(int) cpumR3RegSet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
63	{
64	PVMCPU pVCpu = (PVMCPU)pvUser;
65	void pv = (uint8_t )&pVCpu->cpum + pDesc->offRegister;
66
67	VMCPU_ASSERT_EMT(pVCpu);
68
69	switch (pDesc->enmType)
70	{
71	case DBGFREGVALTYPE_U8:
72	(uint8_t )pv &= ~pfMask->u8;
73	(uint8_t )pv \|= pValue->u8 & pfMask->u8;
74	return VINF_SUCCESS;
75
76	case DBGFREGVALTYPE_U16:
77	(uint16_t )pv &= ~pfMask->u16;
78	(uint16_t )pv \|= pValue->u16 & pfMask->u16;
79	return VINF_SUCCESS;
80
81	case DBGFREGVALTYPE_U32:
82	(uint32_t )pv &= ~pfMask->u32;
83	(uint32_t )pv \|= pValue->u32 & pfMask->u32;
84	return VINF_SUCCESS;
85
86	case DBGFREGVALTYPE_U64:
87	(uint64_t )pv &= ~pfMask->u64;
88	(uint64_t )pv \|= pValue->u64 & pfMask->u64;
89	return VINF_SUCCESS;
90
91	case DBGFREGVALTYPE_U128:
92	{
93	RTUINT128U Val;
94	RTUInt128AssignAnd((PRTUINT128U)pv, RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u128)));
95	RTUInt128AssignOr((PRTUINT128U)pv, RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
96	return VINF_SUCCESS;
97	}
98
99	default:
100	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
101	}
102	}
103
104
105	/**
106	* @interface_method_impl{DBGFREGDESC,pfnGet}
107	*/
108	static DECLCALLBACK(int) cpumR3RegGet_XStateGeneric(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
109	{
110	PVMCPU pVCpu = (PVMCPU)pvUser;
111	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest.pXStateR3 + pDesc->offRegister;
112
113	VMCPU_ASSERT_EMT(pVCpu);
114
115	switch (pDesc->enmType)
116	{
117	case DBGFREGVALTYPE_U8: pValue->u8 = (uint8_t const )pv; return VINF_SUCCESS;
118	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t const )pv; return VINF_SUCCESS;
119	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t const )pv; return VINF_SUCCESS;
120	case DBGFREGVALTYPE_U64: pValue->u64 = (uint64_t const )pv; return VINF_SUCCESS;
121	case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS;
122	default:
123	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
124	}
125	}
126
127
128	/**
129	* @interface_method_impl{DBGFREGDESC,pfnSet}
130	*/
131	static DECLCALLBACK(int) cpumR3RegSet_XStateGeneric(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
132	{
133	PVMCPU pVCpu = (PVMCPU)pvUser;
134	void pv = (uint8_t )&pVCpu->cpum.s.Guest.pXStateR3 + pDesc->offRegister;
135
136	VMCPU_ASSERT_EMT(pVCpu);
137
138	switch (pDesc->enmType)
139	{
140	case DBGFREGVALTYPE_U8:
141	(uint8_t )pv &= ~pfMask->u8;
142	(uint8_t )pv \|= pValue->u8 & pfMask->u8;
143	return VINF_SUCCESS;
144
145	case DBGFREGVALTYPE_U16:
146	(uint16_t )pv &= ~pfMask->u16;
147	(uint16_t )pv \|= pValue->u16 & pfMask->u16;
148	return VINF_SUCCESS;
149
150	case DBGFREGVALTYPE_U32:
151	(uint32_t )pv &= ~pfMask->u32;
152	(uint32_t )pv \|= pValue->u32 & pfMask->u32;
153	return VINF_SUCCESS;
154
155	case DBGFREGVALTYPE_U64:
156	(uint64_t )pv &= ~pfMask->u64;
157	(uint64_t )pv \|= pValue->u64 & pfMask->u64;
158	return VINF_SUCCESS;
159
160	case DBGFREGVALTYPE_U128:
161	{
162	RTUINT128U Val;
163	RTUInt128AssignAnd((PRTUINT128U)pv, RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u128)));
164	RTUInt128AssignOr((PRTUINT128U)pv, RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
165	return VINF_SUCCESS;
166	}
167
168	default:
169	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
170	}
171	}
172
173
174
175	/**
176	* @interface_method_impl{DBGFREGDESC,pfnGet}
177	*/
178	static DECLCALLBACK(int) cpumR3RegSet_seg(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
179	{
180	/** @todo perform a selector load, updating hidden selectors and stuff. */
181	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
182	return VERR_NOT_IMPLEMENTED;
183	}
184
185
186	/**
187	* @interface_method_impl{DBGFREGDESC,pfnGet}
188	*/
189	static DECLCALLBACK(int) cpumR3RegGet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
190	{
191	PVMCPU pVCpu = (PVMCPU)pvUser;
192	VBOXGDTR const pGdtr = (VBOXGDTR const )((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
193
194	VMCPU_ASSERT_EMT(pVCpu);
195	Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
196
197	pValue->dtr.u32Limit = pGdtr->cbGdt;
198	pValue->dtr.u64Base = pGdtr->pGdt;
199	return VINF_SUCCESS;
200	}
201
202
203	/**
204	* @interface_method_impl{DBGFREGDESC,pfnGet}
205	*/
206	static DECLCALLBACK(int) cpumR3RegSet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
207	{
208	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
209	return VERR_NOT_IMPLEMENTED;
210	}
211
212
213	/**
214	* @interface_method_impl{DBGFREGDESC,pfnGet}
215	*/
216	static DECLCALLBACK(int) cpumR3RegGet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
217	{
218	PVMCPU pVCpu = (PVMCPU)pvUser;
219	VBOXIDTR const pIdtr = (VBOXIDTR const )((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
220
221	VMCPU_ASSERT_EMT(pVCpu);
222	Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
223
224	pValue->dtr.u32Limit = pIdtr->cbIdt;
225	pValue->dtr.u64Base = pIdtr->pIdt;
226	return VINF_SUCCESS;
227	}
228
229
230	/**
231	* @interface_method_impl{DBGFREGDESC,pfnGet}
232	*/
233	static DECLCALLBACK(int) cpumR3RegSet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
234	{
235	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
236	return VERR_NOT_IMPLEMENTED;
237	}
238
239
240	/**
241	* Determins the tag register value for a CPU register when the FPU state
242	* format is FXSAVE.
243	*
244	* @returns The tag register value.
245	* @param pFpu Pointer to the guest FPU.
246	* @param iReg The register number (0..7).
247	*/
248	DECLINLINE(uint16_t) cpumR3RegCalcFpuTagFromFxSave(PCX86FXSTATE pFpu, unsigned iReg)
249	{
250	/*
251	* See table 11-1 in the AMD docs.
252	*/
253	if (!(pFpu->FTW & RT_BIT_32(iReg)))
254	return 3; /* b11 - empty */
255
256	uint16_t const uExp = pFpu->aRegs[iReg].au16[4];
257	if (uExp == 0)
258	{
259	if (pFpu->aRegs[iReg].au64[0] == 0) /* J & M == 0 */
260	return 1; /* b01 - zero */
261	return 2; /* b10 - special */
262	}
263
264	if (uExp == UINT16_C(0xffff))
265	return 2; /* b10 - special */
266
267	if (!(pFpu->aRegs[iReg].au64[0] >> 63)) /* J == 0 */
268	return 2; /* b10 - special */
269
270	return 0; /* b00 - valid (normal) */
271	}
272
273
274	/**
275	* @interface_method_impl{DBGFREGDESC,pfnGet}
276	*/
277	static DECLCALLBACK(int) cpumR3RegGet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
278	{
279	PVMCPU pVCpu = (PVMCPU)pvUser;
280	PCX86FXSTATE pFpu = (PCX86FXSTATE)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
281
282	VMCPU_ASSERT_EMT(pVCpu);
283	Assert(pDesc->enmType == DBGFREGVALTYPE_U16);
284
285	pValue->u16 = cpumR3RegCalcFpuTagFromFxSave(pFpu, 0)
286	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 1) << 2)
287	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 2) << 4)
288	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 3) << 6)
289	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 4) << 8)
290	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 5) << 10)
291	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 6) << 12)
292	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 7) << 14);
293	return VINF_SUCCESS;
294	}
295
296
297	/**
298	* @interface_method_impl{DBGFREGDESC,pfnGet}
299	*/
300	static DECLCALLBACK(int) cpumR3RegSet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
301	{
302	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
303	return VERR_DBGF_READ_ONLY_REGISTER;
304	}
305
306
307	/**
308	* @interface_method_impl{DBGFREGDESC,pfnGet}
309	*/
310	static DECLCALLBACK(int) cpumR3RegGet_Dummy(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
311	{
312	RT_NOREF_PV(pvUser);
313	switch (pDesc->enmType)
314	{
315	case DBGFREGVALTYPE_U8: pValue->u8 = 0; return VINF_SUCCESS;
316	case DBGFREGVALTYPE_U16: pValue->u16 = 0; return VINF_SUCCESS;
317	case DBGFREGVALTYPE_U32: pValue->u32 = 0; return VINF_SUCCESS;
318	case DBGFREGVALTYPE_U64: pValue->u64 = 0; return VINF_SUCCESS;
319	case DBGFREGVALTYPE_U128:
320	RT_ZERO(pValue->u128);
321	return VINF_SUCCESS;
322	case DBGFREGVALTYPE_DTR:
323	pValue->dtr.u32Limit = 0;
324	pValue->dtr.u64Base = 0;
325	return VINF_SUCCESS;
326	case DBGFREGVALTYPE_R80:
327	RT_ZERO(pValue->r80Ex);
328	return VINF_SUCCESS;
329	default:
330	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
331	}
332	}
333
334
335	/**
336	* @interface_method_impl{DBGFREGDESC,pfnSet}
337	*/
338	static DECLCALLBACK(int) cpumR3RegSet_Dummy(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
339	{
340	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
341	return VERR_DBGF_READ_ONLY_REGISTER;
342	}
343
344
345
346	/*
347	*
348	* Guest register access functions.
349	*
350	*/
351
352	/**
353	* @interface_method_impl{DBGFREGDESC,pfnGet}
354	*/
355	static DECLCALLBACK(int) cpumR3RegGstGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
356	{
357	PVMCPU pVCpu = (PVMCPU)pvUser;
358	VMCPU_ASSERT_EMT(pVCpu);
359
360	uint64_t u64Value;
361	int rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64Value);
362	AssertRCReturn(rc, rc);
363	switch (pDesc->enmType)
364	{
365	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
366	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
367	default:
368	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
369	}
370	return VINF_SUCCESS;
371	}
372
373
374	/**
375	* @interface_method_impl{DBGFREGDESC,pfnGet}
376	*/
377	static DECLCALLBACK(int) cpumR3RegGstSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
378	{
379	int rc;
380	PVMCPU pVCpu = (PVMCPU)pvUser;
381
382	VMCPU_ASSERT_EMT(pVCpu);
383
384	/*
385	* Calculate the new value.
386	*/
387	uint64_t u64Value;
388	uint64_t fMask;
389	uint64_t fMaskMax;
390	switch (pDesc->enmType)
391	{
392	case DBGFREGVALTYPE_U64:
393	u64Value = pValue->u64;
394	fMask = pfMask->u64;
395	fMaskMax = UINT64_MAX;
396	break;
397	case DBGFREGVALTYPE_U32:
398	u64Value = pValue->u32;
399	fMask = pfMask->u32;
400	fMaskMax = UINT32_MAX;
401	break;
402	default:
403	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
404	}
405	if (fMask != fMaskMax)
406	{
407	uint64_t u64FullValue;
408	rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64FullValue);
409	if (RT_FAILURE(rc))
410	return rc;
411	u64Value = (u64FullValue & ~fMask)
412	\| (u64Value & fMask);
413	}
414
415	/*
416	* Perform the assignment.
417	*/
418	switch (pDesc->offRegister)
419	{
420	case 0: rc = CPUMSetGuestCR0(pVCpu, u64Value); break;
421	case 2: rc = CPUMSetGuestCR2(pVCpu, u64Value); break;
422	case 3: rc = CPUMSetGuestCR3(pVCpu, u64Value); break;
423	case 4: rc = CPUMSetGuestCR4(pVCpu, u64Value); break;
424	case 8: rc = PDMApicSetTPR(pVCpu, (uint8_t)(u64Value << 4)); break;
425	default:
426	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
427	}
428	return rc;
429	}
430
431
432	/**
433	* @interface_method_impl{DBGFREGDESC,pfnGet}
434	*/
435	static DECLCALLBACK(int) cpumR3RegGstGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
436	{
437	PVMCPU pVCpu = (PVMCPU)pvUser;
438	VMCPU_ASSERT_EMT(pVCpu);
439
440	uint64_t u64Value;
441	int rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64Value);
442	AssertRCReturn(rc, rc);
443	switch (pDesc->enmType)
444	{
445	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
446	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
447	default:
448	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
449	}
450	return VINF_SUCCESS;
451	}
452
453
454	/**
455	* @interface_method_impl{DBGFREGDESC,pfnGet}
456	*/
457	static DECLCALLBACK(int) cpumR3RegGstSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
458	{
459	int rc;
460	PVMCPU pVCpu = (PVMCPU)pvUser;
461
462	VMCPU_ASSERT_EMT(pVCpu);
463
464	/*
465	* Calculate the new value.
466	*/
467	uint64_t u64Value;
468	uint64_t fMask;
469	uint64_t fMaskMax;
470	switch (pDesc->enmType)
471	{
472	case DBGFREGVALTYPE_U64:
473	u64Value = pValue->u64;
474	fMask = pfMask->u64;
475	fMaskMax = UINT64_MAX;
476	break;
477	case DBGFREGVALTYPE_U32:
478	u64Value = pValue->u32;
479	fMask = pfMask->u32;
480	fMaskMax = UINT32_MAX;
481	break;
482	default:
483	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
484	}
485	if (fMask != fMaskMax)
486	{
487	uint64_t u64FullValue;
488	rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64FullValue);
489	if (RT_FAILURE(rc))
490	return rc;
491	u64Value = (u64FullValue & ~fMask)
492	\| (u64Value & fMask);
493	}
494
495	/*
496	* Perform the assignment.
497	*/
498	return CPUMSetGuestDRx(pVCpu, pDesc->offRegister, u64Value);
499	}
500
501
502	/**
503	* @interface_method_impl{DBGFREGDESC,pfnGet}
504	*/
505	static DECLCALLBACK(int) cpumR3RegGstGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
506	{
507	PVMCPU pVCpu = (PVMCPU)pvUser;
508	VMCPU_ASSERT_EMT(pVCpu);
509
510	uint64_t u64Value;
511	VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64Value);
512	if (rcStrict == VINF_SUCCESS)
513	{
514	switch (pDesc->enmType)
515	{
516	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
517	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
518	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break;
519	default:
520	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
521	}
522	return VBOXSTRICTRC_VAL(rcStrict);
523	}
524
525	/** @todo what to do about errors? */
526	Assert(RT_FAILURE_NP(rcStrict));
527	return VBOXSTRICTRC_VAL(rcStrict);
528	}
529
530
531	/**
532	* @interface_method_impl{DBGFREGDESC,pfnGet}
533	*/
534	static DECLCALLBACK(int) cpumR3RegGstSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
535	{
536	PVMCPU pVCpu = (PVMCPU)pvUser;
537
538	VMCPU_ASSERT_EMT(pVCpu);
539
540	/*
541	* Calculate the new value.
542	*/
543	uint64_t u64Value;
544	uint64_t fMask;
545	uint64_t fMaskMax;
546	switch (pDesc->enmType)
547	{
548	case DBGFREGVALTYPE_U64:
549	u64Value = pValue->u64;
550	fMask = pfMask->u64;
551	fMaskMax = UINT64_MAX;
552	break;
553	case DBGFREGVALTYPE_U32:
554	u64Value = pValue->u32;
555	fMask = pfMask->u32;
556	fMaskMax = UINT32_MAX;
557	break;
558	case DBGFREGVALTYPE_U16:
559	u64Value = pValue->u16;
560	fMask = pfMask->u16;
561	fMaskMax = UINT16_MAX;
562	break;
563	default:
564	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
565	}
566	if (fMask != fMaskMax)
567	{
568	uint64_t u64FullValue;
569	VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64FullValue);
570	if (rcStrict != VINF_SUCCESS)
571	{
572	AssertRC(RT_FAILURE_NP(rcStrict));
573	return VBOXSTRICTRC_VAL(rcStrict);
574	}
575	u64Value = (u64FullValue & ~fMask)
576	\| (u64Value & fMask);
577	}
578
579	/*
580	* Perform the assignment.
581	*/
582	VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pDesc->offRegister, u64Value);
583	if (rcStrict == VINF_SUCCESS)
584	return VINF_SUCCESS;
585	AssertRC(RT_FAILURE_NP(rcStrict));
586	return VBOXSTRICTRC_VAL(rcStrict);
587	}
588
589
590	/**
591	* @interface_method_impl{DBGFREGDESC,pfnGet}
592	*/
593	static DECLCALLBACK(int) cpumR3RegGstGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
594	{
595	PVMCPU pVCpu = (PVMCPU)pvUser;
596	VMCPU_ASSERT_EMT(pVCpu);
597	Assert(pDesc->enmType == DBGFREGVALTYPE_R80);
598
599	PX86FXSTATE pFpuCtx = &pVCpu->cpum.s.Guest.CTX_SUFF(pXState)->x87;
600	unsigned iReg = (pFpuCtx->FSW >> 11) & 7;
601	iReg += pDesc->offRegister;
602	iReg &= 7;
603	pValue->r80Ex = pFpuCtx->aRegs[iReg].r80Ex;
604
605	return VINF_SUCCESS;
606	}
607
608
609	/**
610	* @interface_method_impl{DBGFREGDESC,pfnGet}
611	*/
612	static DECLCALLBACK(int) cpumR3RegGstSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
613	{
614	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
615	return VERR_NOT_IMPLEMENTED;
616	}
617
618
619
620	/*
621	*
622	* Hypervisor register access functions.
623	*
624	*/
625
626	/**
627	* @interface_method_impl{DBGFREGDESC,pfnGet}
628	*/
629	static DECLCALLBACK(int) cpumR3RegHyperGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
630	{
631	PVMCPU pVCpu = (PVMCPU)pvUser;
632	VMCPU_ASSERT_EMT(pVCpu);
633
634	uint64_t u64Value;
635	switch (pDesc->offRegister)
636	{
637	case 0: u64Value = UINT64_MAX; break;
638	case 2: u64Value = UINT64_MAX; break;
639	case 3: u64Value = CPUMGetHyperCR3(pVCpu); break;
640	case 4: u64Value = UINT64_MAX; break;
641	case 8: u64Value = UINT64_MAX; break;
642	default:
643	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
644	}
645	switch (pDesc->enmType)
646	{
647	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
648	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
649	default:
650	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
651	}
652	return VINF_SUCCESS;
653	}
654
655
656	/**
657	* @interface_method_impl{DBGFREGDESC,pfnGet}
658	*/
659	static DECLCALLBACK(int) cpumR3RegHyperSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
660	{
661	/* Not settable, prevents killing your host. */
662	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
663	return VERR_ACCESS_DENIED;
664	}
665
666
667	/**
668	* @interface_method_impl{DBGFREGDESC,pfnGet}
669	*/
670	static DECLCALLBACK(int) cpumR3RegHyperGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
671	{
672	PVMCPU pVCpu = (PVMCPU)pvUser;
673	VMCPU_ASSERT_EMT(pVCpu);
674
675	uint64_t u64Value;
676	switch (pDesc->offRegister)
677	{
678	case 0: u64Value = CPUMGetHyperDR0(pVCpu); break;
679	case 1: u64Value = CPUMGetHyperDR1(pVCpu); break;
680	case 2: u64Value = CPUMGetHyperDR2(pVCpu); break;
681	case 3: u64Value = CPUMGetHyperDR3(pVCpu); break;
682	case 6: u64Value = CPUMGetHyperDR6(pVCpu); break;
683	case 7: u64Value = CPUMGetHyperDR7(pVCpu); break;
684	default:
685	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
686	}
687	switch (pDesc->enmType)
688	{
689	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
690	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
691	default:
692	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
693	}
694	return VINF_SUCCESS;
695	}
696
697
698	/**
699	* @interface_method_impl{DBGFREGDESC,pfnGet}
700	*/
701	static DECLCALLBACK(int) cpumR3RegHyperSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
702	{
703	/* Not settable, prevents killing your host. */
704	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
705	return VERR_ACCESS_DENIED;
706	}
707
708
709	/**
710	* @interface_method_impl{DBGFREGDESC,pfnGet}
711	*/
712	static DECLCALLBACK(int) cpumR3RegHyperGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
713	{
714	NOREF(pvUser);
715
716	/* Not availble at present, return all FFs to keep things quiet */
717	uint64_t u64Value = UINT64_MAX;
718	switch (pDesc->enmType)
719	{
720	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
721	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
722	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break;
723	default:
724	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
725	}
726	return VINF_SUCCESS;
727	}
728
729
730	/**
731	* @interface_method_impl{DBGFREGDESC,pfnGet}
732	*/
733	static DECLCALLBACK(int) cpumR3RegHyperSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
734	{
735	/* Not settable, return failure. */
736	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
737	return VERR_ACCESS_DENIED;
738	}
739
740
741	/*
742	* Set up aliases.
743	*/
744	#define CPUMREGALIAS_STD(Name, psz32, psz16, psz8) \
745	static DBGFREGALIAS const g_aCpumRegAliases_##Name[] = \
746	{ \
747	{ psz32, DBGFREGVALTYPE_U32 }, \
748	{ psz16, DBGFREGVALTYPE_U16 }, \
749	{ psz8, DBGFREGVALTYPE_U8 }, \
750	{ NULL, DBGFREGVALTYPE_INVALID } \
751	}
752	CPUMREGALIAS_STD(rax, "eax", "ax", "al");
753	CPUMREGALIAS_STD(rcx, "ecx", "cx", "cl");
754	CPUMREGALIAS_STD(rdx, "edx", "dx", "dl");
755	CPUMREGALIAS_STD(rbx, "ebx", "bx", "bl");
756	CPUMREGALIAS_STD(rsp, "esp", "sp", NULL);
757	CPUMREGALIAS_STD(rbp, "ebp", "bp", NULL);
758	CPUMREGALIAS_STD(rsi, "esi", "si", "sil");
759	CPUMREGALIAS_STD(rdi, "edi", "di", "dil");
760	CPUMREGALIAS_STD(r8, "r8d", "r8w", "r8b");
761	CPUMREGALIAS_STD(r9, "r9d", "r9w", "r9b");
762	CPUMREGALIAS_STD(r10, "r10d", "r10w", "r10b");
763	CPUMREGALIAS_STD(r11, "r11d", "r11w", "r11b");
764	CPUMREGALIAS_STD(r12, "r12d", "r12w", "r12b");
765	CPUMREGALIAS_STD(r13, "r13d", "r13w", "r13b");
766	CPUMREGALIAS_STD(r14, "r14d", "r14w", "r14b");
767	CPUMREGALIAS_STD(r15, "r15d", "r15w", "r15b");
768	CPUMREGALIAS_STD(rip, "eip", "ip", NULL);
769	CPUMREGALIAS_STD(rflags, "eflags", "flags", NULL);
770	#undef CPUMREGALIAS_STD
771
772	static DBGFREGALIAS const g_aCpumRegAliases_fpuip[] =
773	{
774	{ "fpuip16", DBGFREGVALTYPE_U16 },
775	{ NULL, DBGFREGVALTYPE_INVALID }
776	};
777
778	static DBGFREGALIAS const g_aCpumRegAliases_fpudp[] =
779	{
780	{ "fpudp16", DBGFREGVALTYPE_U16 },
781	{ NULL, DBGFREGVALTYPE_INVALID }
782	};
783
784	static DBGFREGALIAS const g_aCpumRegAliases_cr0[] =
785	{
786	{ "msw", DBGFREGVALTYPE_U16 },
787	{ NULL, DBGFREGVALTYPE_INVALID }
788	};
789
790	/*
791	* Sub fields.
792	*/
793	/** Sub-fields for the (hidden) segment attribute register. */
794	static DBGFREGSUBFIELD const g_aCpumRegFields_seg[] =
795	{
796	DBGFREGSUBFIELD_RW("type", 0, 4, 0),
797	DBGFREGSUBFIELD_RW("s", 4, 1, 0),
798	DBGFREGSUBFIELD_RW("dpl", 5, 2, 0),
799	DBGFREGSUBFIELD_RW("p", 7, 1, 0),
800	DBGFREGSUBFIELD_RW("avl", 12, 1, 0),
801	DBGFREGSUBFIELD_RW("l", 13, 1, 0),
802	DBGFREGSUBFIELD_RW("d", 14, 1, 0),
803	DBGFREGSUBFIELD_RW("g", 15, 1, 0),
804	DBGFREGSUBFIELD_TERMINATOR()
805	};
806
807	/** Sub-fields for the flags register. */
808	static DBGFREGSUBFIELD const g_aCpumRegFields_rflags[] =
809	{
810	DBGFREGSUBFIELD_RW("cf", 0, 1, 0),
811	DBGFREGSUBFIELD_RW("pf", 2, 1, 0),
812	DBGFREGSUBFIELD_RW("af", 4, 1, 0),
813	DBGFREGSUBFIELD_RW("zf", 6, 1, 0),
814	DBGFREGSUBFIELD_RW("sf", 7, 1, 0),
815	DBGFREGSUBFIELD_RW("tf", 8, 1, 0),
816	DBGFREGSUBFIELD_RW("if", 9, 1, 0),
817	DBGFREGSUBFIELD_RW("df", 10, 1, 0),
818	DBGFREGSUBFIELD_RW("of", 11, 1, 0),
819	DBGFREGSUBFIELD_RW("iopl", 12, 2, 0),
820	DBGFREGSUBFIELD_RW("nt", 14, 1, 0),
821	DBGFREGSUBFIELD_RW("rf", 16, 1, 0),
822	DBGFREGSUBFIELD_RW("vm", 17, 1, 0),
823	DBGFREGSUBFIELD_RW("ac", 18, 1, 0),
824	DBGFREGSUBFIELD_RW("vif", 19, 1, 0),
825	DBGFREGSUBFIELD_RW("vip", 20, 1, 0),
826	DBGFREGSUBFIELD_RW("id", 21, 1, 0),
827	DBGFREGSUBFIELD_TERMINATOR()
828	};
829
830	/** Sub-fields for the FPU control word register. */
831	static DBGFREGSUBFIELD const g_aCpumRegFields_fcw[] =
832	{
833	DBGFREGSUBFIELD_RW("im", 1, 1, 0),
834	DBGFREGSUBFIELD_RW("dm", 2, 1, 0),
835	DBGFREGSUBFIELD_RW("zm", 3, 1, 0),
836	DBGFREGSUBFIELD_RW("om", 4, 1, 0),
837	DBGFREGSUBFIELD_RW("um", 5, 1, 0),
838	DBGFREGSUBFIELD_RW("pm", 6, 1, 0),
839	DBGFREGSUBFIELD_RW("pc", 8, 2, 0),
840	DBGFREGSUBFIELD_RW("rc", 10, 2, 0),
841	DBGFREGSUBFIELD_RW("x", 12, 1, 0),
842	DBGFREGSUBFIELD_TERMINATOR()
843	};
844
845	/** Sub-fields for the FPU status word register. */
846	static DBGFREGSUBFIELD const g_aCpumRegFields_fsw[] =
847	{
848	DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
849	DBGFREGSUBFIELD_RW("de", 1, 1, 0),
850	DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
851	DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
852	DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
853	DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
854	DBGFREGSUBFIELD_RW("se", 6, 1, 0),
855	DBGFREGSUBFIELD_RW("es", 7, 1, 0),
856	DBGFREGSUBFIELD_RW("c0", 8, 1, 0),
857	DBGFREGSUBFIELD_RW("c1", 9, 1, 0),
858	DBGFREGSUBFIELD_RW("c2", 10, 1, 0),
859	DBGFREGSUBFIELD_RW("top", 11, 3, 0),
860	DBGFREGSUBFIELD_RW("c3", 14, 1, 0),
861	DBGFREGSUBFIELD_RW("b", 15, 1, 0),
862	DBGFREGSUBFIELD_TERMINATOR()
863	};
864
865	/** Sub-fields for the FPU tag word register. */
866	static DBGFREGSUBFIELD const g_aCpumRegFields_ftw[] =
867	{
868	DBGFREGSUBFIELD_RW("tag0", 0, 2, 0),
869	DBGFREGSUBFIELD_RW("tag1", 2, 2, 0),
870	DBGFREGSUBFIELD_RW("tag2", 4, 2, 0),
871	DBGFREGSUBFIELD_RW("tag3", 6, 2, 0),
872	DBGFREGSUBFIELD_RW("tag4", 8, 2, 0),
873	DBGFREGSUBFIELD_RW("tag5", 10, 2, 0),
874	DBGFREGSUBFIELD_RW("tag6", 12, 2, 0),
875	DBGFREGSUBFIELD_RW("tag7", 14, 2, 0),
876	DBGFREGSUBFIELD_TERMINATOR()
877	};
878
879	/** Sub-fields for the Multimedia Extensions Control and Status Register. */
880	static DBGFREGSUBFIELD const g_aCpumRegFields_mxcsr[] =
881	{
882	DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
883	DBGFREGSUBFIELD_RW("de", 1, 1, 0),
884	DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
885	DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
886	DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
887	DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
888	DBGFREGSUBFIELD_RW("daz", 6, 1, 0),
889	DBGFREGSUBFIELD_RW("im", 7, 1, 0),
890	DBGFREGSUBFIELD_RW("dm", 8, 1, 0),
891	DBGFREGSUBFIELD_RW("zm", 9, 1, 0),
892	DBGFREGSUBFIELD_RW("om", 10, 1, 0),
893	DBGFREGSUBFIELD_RW("um", 11, 1, 0),
894	DBGFREGSUBFIELD_RW("pm", 12, 1, 0),
895	DBGFREGSUBFIELD_RW("rc", 13, 2, 0),
896	DBGFREGSUBFIELD_RW("fz", 14, 1, 0),
897	DBGFREGSUBFIELD_TERMINATOR()
898	};
899
900	/** Sub-fields for the FPU tag word register. */
901	static DBGFREGSUBFIELD const g_aCpumRegFields_stN[] =
902	{
903	DBGFREGSUBFIELD_RW("man", 0, 64, 0),
904	DBGFREGSUBFIELD_RW("exp", 64, 15, 0),
905	DBGFREGSUBFIELD_RW("sig", 79, 1, 0),
906	DBGFREGSUBFIELD_TERMINATOR()
907	};
908
909	/** Sub-fields for the MMX registers. */
910	static DBGFREGSUBFIELD const g_aCpumRegFields_mmN[] =
911	{
912	DBGFREGSUBFIELD_RW("dw0", 0, 32, 0),
913	DBGFREGSUBFIELD_RW("dw1", 32, 32, 0),
914	DBGFREGSUBFIELD_RW("w0", 0, 16, 0),
915	DBGFREGSUBFIELD_RW("w1", 16, 16, 0),
916	DBGFREGSUBFIELD_RW("w2", 32, 16, 0),
917	DBGFREGSUBFIELD_RW("w3", 48, 16, 0),
918	DBGFREGSUBFIELD_RW("b0", 0, 8, 0),
919	DBGFREGSUBFIELD_RW("b1", 8, 8, 0),
920	DBGFREGSUBFIELD_RW("b2", 16, 8, 0),
921	DBGFREGSUBFIELD_RW("b3", 24, 8, 0),
922	DBGFREGSUBFIELD_RW("b4", 32, 8, 0),
923	DBGFREGSUBFIELD_RW("b5", 40, 8, 0),
924	DBGFREGSUBFIELD_RW("b6", 48, 8, 0),
925	DBGFREGSUBFIELD_RW("b7", 56, 8, 0),
926	DBGFREGSUBFIELD_TERMINATOR()
927	};
928
929	/** Sub-fields for the XMM registers. */
930	static DBGFREGSUBFIELD const g_aCpumRegFields_xmmN[] =
931	{
932	DBGFREGSUBFIELD_RW("r0", 0, 32, 0),
933	DBGFREGSUBFIELD_RW("r0.man", 0+ 0, 23, 0),
934	DBGFREGSUBFIELD_RW("r0.exp", 0+23, 8, 0),
935	DBGFREGSUBFIELD_RW("r0.sig", 0+31, 1, 0),
936	DBGFREGSUBFIELD_RW("r1", 32, 32, 0),
937	DBGFREGSUBFIELD_RW("r1.man", 32+ 0, 23, 0),
938	DBGFREGSUBFIELD_RW("r1.exp", 32+23, 8, 0),
939	DBGFREGSUBFIELD_RW("r1.sig", 32+31, 1, 0),
940	DBGFREGSUBFIELD_RW("r2", 64, 32, 0),
941	DBGFREGSUBFIELD_RW("r2.man", 64+ 0, 23, 0),
942	DBGFREGSUBFIELD_RW("r2.exp", 64+23, 8, 0),
943	DBGFREGSUBFIELD_RW("r2.sig", 64+31, 1, 0),
944	DBGFREGSUBFIELD_RW("r3", 96, 32, 0),
945	DBGFREGSUBFIELD_RW("r3.man", 96+ 0, 23, 0),
946	DBGFREGSUBFIELD_RW("r3.exp", 96+23, 8, 0),
947	DBGFREGSUBFIELD_RW("r3.sig", 96+31, 1, 0),
948	DBGFREGSUBFIELD_TERMINATOR()
949	};
950
951	/** Sub-fields for the CR0 register. */
952	static DBGFREGSUBFIELD const g_aCpumRegFields_cr0[] =
953	{
954	DBGFREGSUBFIELD_RW("pe", 0, 1, 0),
955	DBGFREGSUBFIELD_RW("mp", 1, 1, 0),
956	DBGFREGSUBFIELD_RW("em", 2, 1, 0),
957	DBGFREGSUBFIELD_RW("ts", 3, 1, 0),
958	DBGFREGSUBFIELD_RO("et", 4, 1, 0),
959	DBGFREGSUBFIELD_RW("ne", 5, 1, 0),
960	DBGFREGSUBFIELD_RW("wp", 16, 1, 0),
961	DBGFREGSUBFIELD_RW("am", 18, 1, 0),
962	DBGFREGSUBFIELD_RW("nw", 29, 1, 0),
963	DBGFREGSUBFIELD_RW("cd", 30, 1, 0),
964	DBGFREGSUBFIELD_RW("pg", 31, 1, 0),
965	DBGFREGSUBFIELD_TERMINATOR()
966	};
967
968	/** Sub-fields for the CR3 register. */
969	static DBGFREGSUBFIELD const g_aCpumRegFields_cr3[] =
970	{
971	DBGFREGSUBFIELD_RW("pwt", 3, 1, 0),
972	DBGFREGSUBFIELD_RW("pcd", 4, 1, 0),
973	DBGFREGSUBFIELD_TERMINATOR()
974	};
975
976	/** Sub-fields for the CR4 register. */
977	static DBGFREGSUBFIELD const g_aCpumRegFields_cr4[] =
978	{
979	DBGFREGSUBFIELD_RW("vme", 0, 1, 0),
980	DBGFREGSUBFIELD_RW("pvi", 1, 1, 0),
981	DBGFREGSUBFIELD_RW("tsd", 2, 1, 0),
982	DBGFREGSUBFIELD_RW("de", 3, 1, 0),
983	DBGFREGSUBFIELD_RW("pse", 4, 1, 0),
984	DBGFREGSUBFIELD_RW("pae", 5, 1, 0),
985	DBGFREGSUBFIELD_RW("mce", 6, 1, 0),
986	DBGFREGSUBFIELD_RW("pge", 7, 1, 0),
987	DBGFREGSUBFIELD_RW("pce", 8, 1, 0),
988	DBGFREGSUBFIELD_RW("osfxsr", 9, 1, 0),
989	DBGFREGSUBFIELD_RW("osxmmeexcpt", 10, 1, 0),
990	DBGFREGSUBFIELD_RW("vmxe", 13, 1, 0),
991	DBGFREGSUBFIELD_RW("smxe", 14, 1, 0),
992	DBGFREGSUBFIELD_RW("pcide", 17, 1, 0),
993	DBGFREGSUBFIELD_RW("osxsave", 18, 1, 0),
994	DBGFREGSUBFIELD_RW("smep", 20, 1, 0),
995	DBGFREGSUBFIELD_RW("smap", 21, 1, 0),
996	DBGFREGSUBFIELD_TERMINATOR()
997	};
998
999	/** Sub-fields for the DR6 register. */
1000	static DBGFREGSUBFIELD const g_aCpumRegFields_dr6[] =
1001	{
1002	DBGFREGSUBFIELD_RW("b0", 0, 1, 0),
1003	DBGFREGSUBFIELD_RW("b1", 1, 1, 0),
1004	DBGFREGSUBFIELD_RW("b2", 2, 1, 0),
1005	DBGFREGSUBFIELD_RW("b3", 3, 1, 0),
1006	DBGFREGSUBFIELD_RW("bd", 13, 1, 0),
1007	DBGFREGSUBFIELD_RW("bs", 14, 1, 0),
1008	DBGFREGSUBFIELD_RW("bt", 15, 1, 0),
1009	DBGFREGSUBFIELD_TERMINATOR()
1010	};
1011
1012	/** Sub-fields for the DR7 register. */
1013	static DBGFREGSUBFIELD const g_aCpumRegFields_dr7[] =
1014	{
1015	DBGFREGSUBFIELD_RW("l0", 0, 1, 0),
1016	DBGFREGSUBFIELD_RW("g0", 1, 1, 0),
1017	DBGFREGSUBFIELD_RW("l1", 2, 1, 0),
1018	DBGFREGSUBFIELD_RW("g1", 3, 1, 0),
1019	DBGFREGSUBFIELD_RW("l2", 4, 1, 0),
1020	DBGFREGSUBFIELD_RW("g2", 5, 1, 0),
1021	DBGFREGSUBFIELD_RW("l3", 6, 1, 0),
1022	DBGFREGSUBFIELD_RW("g3", 7, 1, 0),
1023	DBGFREGSUBFIELD_RW("le", 8, 1, 0),
1024	DBGFREGSUBFIELD_RW("ge", 9, 1, 0),
1025	DBGFREGSUBFIELD_RW("gd", 13, 1, 0),
1026	DBGFREGSUBFIELD_RW("rw0", 16, 2, 0),
1027	DBGFREGSUBFIELD_RW("len0", 18, 2, 0),
1028	DBGFREGSUBFIELD_RW("rw1", 20, 2, 0),
1029	DBGFREGSUBFIELD_RW("len1", 22, 2, 0),
1030	DBGFREGSUBFIELD_RW("rw2", 24, 2, 0),
1031	DBGFREGSUBFIELD_RW("len2", 26, 2, 0),
1032	DBGFREGSUBFIELD_RW("rw3", 28, 2, 0),
1033	DBGFREGSUBFIELD_RW("len3", 30, 2, 0),
1034	DBGFREGSUBFIELD_TERMINATOR()
1035	};
1036
1037	/** Sub-fields for the CR_PAT MSR. */
1038	static DBGFREGSUBFIELD const g_aCpumRegFields_apic_base[] =
1039	{
1040	DBGFREGSUBFIELD_RW("bsp", 8, 1, 0),
1041	DBGFREGSUBFIELD_RW("ge", 9, 1, 0),
1042	DBGFREGSUBFIELD_RW("base", 12, 20, 12),
1043	DBGFREGSUBFIELD_TERMINATOR()
1044	};
1045
1046	/** Sub-fields for the CR_PAT MSR. */
1047	static DBGFREGSUBFIELD const g_aCpumRegFields_cr_pat[] =
1048	{
1049	/** @todo */
1050	DBGFREGSUBFIELD_TERMINATOR()
1051	};
1052
1053	/** Sub-fields for the PERF_STATUS MSR. */
1054	static DBGFREGSUBFIELD const g_aCpumRegFields_perf_status[] =
1055	{
1056	/** @todo */
1057	DBGFREGSUBFIELD_TERMINATOR()
1058	};
1059
1060	/** Sub-fields for the EFER MSR. */
1061	static DBGFREGSUBFIELD const g_aCpumRegFields_efer[] =
1062	{
1063	/** @todo */
1064	DBGFREGSUBFIELD_TERMINATOR()
1065	};
1066
1067	/** Sub-fields for the STAR MSR. */
1068	static DBGFREGSUBFIELD const g_aCpumRegFields_star[] =
1069	{
1070	/** @todo */
1071	DBGFREGSUBFIELD_TERMINATOR()
1072	};
1073
1074	/** Sub-fields for the CSTAR MSR. */
1075	static DBGFREGSUBFIELD const g_aCpumRegFields_cstar[] =
1076	{
1077	/** @todo */
1078	DBGFREGSUBFIELD_TERMINATOR()
1079	};
1080
1081	/** Sub-fields for the LSTAR MSR. */
1082	static DBGFREGSUBFIELD const g_aCpumRegFields_lstar[] =
1083	{
1084	/** @todo */
1085	DBGFREGSUBFIELD_TERMINATOR()
1086	};
1087
1088	/** Sub-fields for the SF_MASK MSR. */
1089	static DBGFREGSUBFIELD const g_aCpumRegFields_sf_mask[] =
1090	{
1091	/** @todo */
1092	DBGFREGSUBFIELD_TERMINATOR()
1093	};
1094
1095
1096	/** @name Macros for producing register descriptor table entries.
1097	* @{ */
1098	#define CPU_REG_EX_AS(a_szName, a_RegSuff, a_TypeSuff, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1099	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1100
1101	#define CPU_REG_REG(UName, LName) \
1102	CPU_REG_RW_AS(#LName, UName, U64, LName, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_##LName, NULL)
1103
1104	#define CPU_REG_SEG(UName, LName) \
1105	CPU_REG_RW_AS(#LName, UName, U16, LName.Sel, cpumR3RegGet_Generic, cpumR3RegSet_seg, NULL, NULL ), \
1106	CPU_REG_RW_AS(#LName "_attr", UName##_ATTR, U32, LName.Attr.u, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_seg), \
1107	CPU_REG_RW_AS(#LName "_base", UName##_BASE, U64, LName.u64Base, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), \
1108	CPU_REG_RW_AS(#LName "_lim", UName##_LIMIT, U32, LName.u32Limit, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL )
1109
1110	#define CPU_REG_MM(n) \
1111	CPU_REG_XS_RW_AS("mm" #n, MM##n, U64, x87.aRegs[n].mmx, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_mmN)
1112
1113	#define CPU_REG_XMM(n) \
1114	CPU_REG_XS_RW_AS("xmm" #n, XMM##n, U128, x87.aXMM[n].xmm, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_xmmN)
1115	/** @} */
1116
1117
1118	/**
1119	* The guest register descriptors.
1120	*/
1121	static DBGFREGDESC const g_aCpumRegGstDescs[] =
1122	{
1123	#define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1124	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1125	#define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1126	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1127	#define CPU_REG_XS_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_XStateMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1128	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, RT_OFFSETOF(X86XSAVEAREA, a_XStateMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1129	#define CPU_REG_XS_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_XStateMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1130	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(X86XSAVEAREA, a_XStateMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1131	#define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \
1132	CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegGstGet_msr, cpumR3RegGstSet_msr, NULL, a_paSubFields)
1133	#define CPU_REG_ST(n) \
1134	CPU_REG_EX_AS("st" #n, ST##n, R80, n, cpumR3RegGstGet_stN, cpumR3RegGstSet_stN, NULL, g_aCpumRegFields_stN)
1135
1136	CPU_REG_REG(RAX, rax),
1137	CPU_REG_REG(RCX, rcx),
1138	CPU_REG_REG(RDX, rdx),
1139	CPU_REG_REG(RBX, rbx),
1140	CPU_REG_REG(RSP, rsp),
1141	CPU_REG_REG(RBP, rbp),
1142	CPU_REG_REG(RSI, rsi),
1143	CPU_REG_REG(RDI, rdi),
1144	CPU_REG_REG(R8, r8),
1145	CPU_REG_REG(R9, r9),
1146	CPU_REG_REG(R10, r10),
1147	CPU_REG_REG(R11, r11),
1148	CPU_REG_REG(R12, r12),
1149	CPU_REG_REG(R13, r13),
1150	CPU_REG_REG(R14, r14),
1151	CPU_REG_REG(R15, r15),
1152	CPU_REG_SEG(CS, cs),
1153	CPU_REG_SEG(DS, ds),
1154	CPU_REG_SEG(ES, es),
1155	CPU_REG_SEG(FS, fs),
1156	CPU_REG_SEG(GS, gs),
1157	CPU_REG_SEG(SS, ss),
1158	CPU_REG_REG(RIP, rip),
1159	CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ),
1160	CPU_REG_XS_RW_AS("fcw", FCW, U16, x87.FCW, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_fcw ),
1161	CPU_REG_XS_RW_AS("fsw", FSW, U16, x87.FSW, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_fsw ),
1162	CPU_REG_XS_RO_AS("ftw", FTW, U16, x87, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ),
1163	CPU_REG_XS_RW_AS("fop", FOP, U16, x87.FOP, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, NULL ),
1164	CPU_REG_XS_RW_AS("fpuip", FPUIP, U32, x87.FPUIP, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, g_aCpumRegAliases_fpuip, NULL ),
1165	CPU_REG_XS_RW_AS("fpucs", FPUCS, U16, x87.CS, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, NULL ),
1166	CPU_REG_XS_RW_AS("fpudp", FPUDP, U32, x87.FPUDP, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, g_aCpumRegAliases_fpudp, NULL ),
1167	CPU_REG_XS_RW_AS("fpuds", FPUDS, U16, x87.DS, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, NULL ),
1168	CPU_REG_XS_RW_AS("mxcsr", MXCSR, U32, x87.MXCSR, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_mxcsr ),
1169	CPU_REG_XS_RW_AS("mxcsr_mask", MXCSR_MASK, U32, x87.MXCSR_MASK, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_mxcsr ),
1170	CPU_REG_ST(0),
1171	CPU_REG_ST(1),
1172	CPU_REG_ST(2),
1173	CPU_REG_ST(3),
1174	CPU_REG_ST(4),
1175	CPU_REG_ST(5),
1176	CPU_REG_ST(6),
1177	CPU_REG_ST(7),
1178	CPU_REG_MM(0),
1179	CPU_REG_MM(1),
1180	CPU_REG_MM(2),
1181	CPU_REG_MM(3),
1182	CPU_REG_MM(4),
1183	CPU_REG_MM(5),
1184	CPU_REG_MM(6),
1185	CPU_REG_MM(7),
1186	CPU_REG_XMM(0),
1187	CPU_REG_XMM(1),
1188	CPU_REG_XMM(2),
1189	CPU_REG_XMM(3),
1190	CPU_REG_XMM(4),
1191	CPU_REG_XMM(5),
1192	CPU_REG_XMM(6),
1193	CPU_REG_XMM(7),
1194	CPU_REG_XMM(8),
1195	CPU_REG_XMM(9),
1196	CPU_REG_XMM(10),
1197	CPU_REG_XMM(11),
1198	CPU_REG_XMM(12),
1199	CPU_REG_XMM(13),
1200	CPU_REG_XMM(14),
1201	CPU_REG_XMM(15),
1202	CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1203	CPU_REG_RW_AS("gdtr_lim", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1204	CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1205	CPU_REG_RW_AS("idtr_lim", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1206	CPU_REG_SEG(LDTR, ldtr),
1207	CPU_REG_SEG(TR, tr),
1208	CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ),
1209	CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
1210	CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr3 ),
1211	CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr4 ),
1212	CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
1213	CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1214	CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1215	CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1216	CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1217	CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr6 ),
1218	CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr7 ),
1219	CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ),
1220	CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ),
1221	CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status),
1222	CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ),
1223	CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ),
1224	CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ),
1225	CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ),
1226	CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ),
1227	CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ),
1228	CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ),
1229	CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ),
1230	CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ),
1231	CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ),
1232	CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ),
1233	CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ),
1234	CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ),
1235	CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Guest.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1236	CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Guest.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1237	CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Guest.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1238	CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Guest.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1239	CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
1240	CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ),
1241	DBGFREGDESC_TERMINATOR()
1242
1243	#undef CPU_REG_RW_AS
1244	#undef CPU_REG_RO_AS
1245	#undef CPU_REG_MSR
1246	#undef CPU_REG_ST
1247	};
1248
1249
1250	/**
1251	* The hypervisor (raw-mode) register descriptors.
1252	*/
1253	static DBGFREGDESC const g_aCpumRegHyperDescs[] =
1254	{
1255	#define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1256	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, RT_OFFSETOF(CPUMCPU, Hyper.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1257	#define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1258	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCPU, Hyper.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1259	#define CPU_REG_DUMMY(a_szName, a_RegSuff, a_TypeSuff) \
1260	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, 0, cpumR3RegGet_Dummy, cpumR3RegSet_Dummy, NULL, NULL}
1261	#define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \
1262	CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegHyperGet_msr, cpumR3RegHyperSet_msr, NULL, a_paSubFields)
1263
1264	CPU_REG_REG(RAX, rax),
1265	CPU_REG_REG(RCX, rcx),
1266	CPU_REG_REG(RDX, rdx),
1267	CPU_REG_REG(RBX, rbx),
1268	CPU_REG_REG(RSP, rsp),
1269	CPU_REG_REG(RBP, rbp),
1270	CPU_REG_REG(RSI, rsi),
1271	CPU_REG_REG(RDI, rdi),
1272	CPU_REG_REG(R8, r8),
1273	CPU_REG_REG(R9, r9),
1274	CPU_REG_REG(R10, r10),
1275	CPU_REG_REG(R11, r11),
1276	CPU_REG_REG(R12, r12),
1277	CPU_REG_REG(R13, r13),
1278	CPU_REG_REG(R14, r14),
1279	CPU_REG_REG(R15, r15),
1280	CPU_REG_SEG(CS, cs),
1281	CPU_REG_SEG(DS, ds),
1282	CPU_REG_SEG(ES, es),
1283	CPU_REG_SEG(FS, fs),
1284	CPU_REG_SEG(GS, gs),
1285	CPU_REG_SEG(SS, ss),
1286	CPU_REG_REG(RIP, rip),
1287	CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ),
1288	CPU_REG_DUMMY("fcw", FCW, U16),
1289	CPU_REG_DUMMY("fsw", FSW, U16),
1290	CPU_REG_DUMMY("ftw", FTW, U16),
1291	CPU_REG_DUMMY("fop", FOP, U16),
1292	CPU_REG_DUMMY("fpuip", FPUIP, U32),
1293	CPU_REG_DUMMY("fpucs", FPUCS, U16),
1294	CPU_REG_DUMMY("fpudp", FPUDP, U32),
1295	CPU_REG_DUMMY("fpuds", FPUDS, U16),
1296	CPU_REG_DUMMY("mxcsr", MXCSR, U32),
1297	CPU_REG_DUMMY("mxcsr_mask", MXCSR_MASK, U32),
1298	CPU_REG_DUMMY("st0", ST0, R80),
1299	CPU_REG_DUMMY("st1", ST1, R80),
1300	CPU_REG_DUMMY("st2", ST2, R80),
1301	CPU_REG_DUMMY("st3", ST3, R80),
1302	CPU_REG_DUMMY("st4", ST4, R80),
1303	CPU_REG_DUMMY("st5", ST5, R80),
1304	CPU_REG_DUMMY("st6", ST6, R80),
1305	CPU_REG_DUMMY("st7", ST7, R80),
1306	CPU_REG_DUMMY("mm0", MM0, U64),
1307	CPU_REG_DUMMY("mm1", MM1, U64),
1308	CPU_REG_DUMMY("mm2", MM2, U64),
1309	CPU_REG_DUMMY("mm3", MM3, U64),
1310	CPU_REG_DUMMY("mm4", MM4, U64),
1311	CPU_REG_DUMMY("mm5", MM5, U64),
1312	CPU_REG_DUMMY("mm6", MM6, U64),
1313	CPU_REG_DUMMY("mm7", MM7, U64),
1314	CPU_REG_DUMMY("xmm0", XMM0, U128),
1315	CPU_REG_DUMMY("xmm1", XMM1, U128),
1316	CPU_REG_DUMMY("xmm2", XMM2, U128),
1317	CPU_REG_DUMMY("xmm3", XMM3, U128),
1318	CPU_REG_DUMMY("xmm4", XMM4, U128),
1319	CPU_REG_DUMMY("xmm5", XMM5, U128),
1320	CPU_REG_DUMMY("xmm6", XMM6, U128),
1321	CPU_REG_DUMMY("xmm7", XMM7, U128),
1322	CPU_REG_DUMMY("xmm8", XMM8, U128),
1323	CPU_REG_DUMMY("xmm9", XMM9, U128),
1324	CPU_REG_DUMMY("xmm10", XMM10, U128),
1325	CPU_REG_DUMMY("xmm11", XMM11, U128),
1326	CPU_REG_DUMMY("xmm12", XMM12, U128),
1327	CPU_REG_DUMMY("xmm13", XMM13, U128),
1328	CPU_REG_DUMMY("xmm14", XMM14, U128),
1329	CPU_REG_DUMMY("xmm15", XMM15, U128),
1330	CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1331	CPU_REG_RW_AS("gdtr_lim", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1332	CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1333	CPU_REG_RW_AS("idtr_lim", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1334	CPU_REG_SEG(LDTR, ldtr),
1335	CPU_REG_SEG(TR, tr),
1336	CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ),
1337	CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, NULL ),
1338	CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, g_aCpumRegFields_cr3 ),
1339	CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, g_aCpumRegFields_cr4 ),
1340	CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, NULL ),
1341	CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1342	CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1343	CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1344	CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1345	CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, g_aCpumRegFields_dr6 ),
1346	CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, g_aCpumRegFields_dr7 ),
1347	CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ),
1348	CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ),
1349	CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status),
1350	CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ),
1351	CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ),
1352	CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ),
1353	CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ),
1354	CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ),
1355	CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ),
1356	CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ),
1357	CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ),
1358	CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ),
1359	CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ),
1360	CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ),
1361	CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ),
1362	CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ),
1363	CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1364	CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1365	CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1366	CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1367	CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
1368	CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ),
1369	DBGFREGDESC_TERMINATOR()
1370	#undef CPU_REG_RW_AS
1371	#undef CPU_REG_RO_AS
1372	#undef CPU_REG_MSR
1373	#undef CPU_REG_ST
1374	};
1375
1376
1377	/**
1378	* Initializes the debugger related sides of the CPUM component.
1379	*
1380	* Called by CPUMR3Init.
1381	*
1382	* @returns VBox status code.
1383	* @param pVM The cross context VM structure.
1384	*/
1385	int cpumR3DbgInit(PVM pVM)
1386	{
1387	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1388	{
1389	int rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegGstDescs, true /fGuestRegs/);
1390	AssertLogRelRCReturn(rc, rc);
1391	rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegHyperDescs, false /fGuestRegs/);
1392	AssertLogRelRCReturn(rc, rc);
1393	}
1394
1395	return VINF_SUCCESS;
1396	}
1397

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp@ 62639

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