VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMDbg-armv8.cpp@ 106842

Last change on this file since 106842 was 106365, checked in by vboxsync, 2 months ago

VMM/DBGFReg/CMM/CPUM: Correct CPU state register sorting and make the register querying methos using DBGFREG_XXX as an input work on ARMv8, bugref:10393
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 17.7 KB
Line 
1/* $Id: CPUMDbg-armv8.cpp 106365 2024-10-16 13:11:39Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager, Debugger & Debugging APIs.
4 */
5
6/*
7 * Copyright (C) 2010-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DBGF
33#include <VBox/vmm/cpum.h>
34#include <VBox/vmm/dbgf.h>
35#include <VBox/vmm/apic.h>
36#include "CPUMInternal-armv8.h"
37#include <VBox/vmm/vm.h>
38#include <VBox/param.h>
39#include <VBox/err.h>
40#include <VBox/log.h>
41#include <iprt/thread.h>
42#include <iprt/string.h>
43#include <iprt/uint128.h>
44
45
46/**
47 * @interface_method_impl{DBGFREGDESC,pfnGet}
48 */
49static DECLCALLBACK(int) cpumR3RegGet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
50{
51 PVMCPU pVCpu = (PVMCPU)pvUser;
52 void const *pv = (uint8_t const *)&pVCpu->cpum + pDesc->offRegister;
53
54 VMCPU_ASSERT_EMT(pVCpu);
55
56 switch (pDesc->enmType)
57 {
58 case DBGFREGVALTYPE_U8: pValue->u8 = *(uint8_t const *)pv; return VINF_SUCCESS;
59 case DBGFREGVALTYPE_U16: pValue->u16 = *(uint16_t const *)pv; return VINF_SUCCESS;
60 case DBGFREGVALTYPE_U32: pValue->u32 = *(uint32_t const *)pv; return VINF_SUCCESS;
61 case DBGFREGVALTYPE_U64: pValue->u64 = *(uint64_t const *)pv; return VINF_SUCCESS;
62 case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS;
63 case DBGFREGVALTYPE_U256: pValue->u256 = *(PCRTUINT256U )pv; return VINF_SUCCESS;
64 case DBGFREGVALTYPE_U512: pValue->u512 = *(PCRTUINT512U )pv; return VINF_SUCCESS;
65 default:
66 AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
67 }
68}
69
70
71/**
72 * @interface_method_impl{DBGFREGDESC,pfnSet}
73 */
74static DECLCALLBACK(int) cpumR3RegSet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
75{
76 PVMCPU pVCpu = (PVMCPU)pvUser;
77 void *pv = (uint8_t *)&pVCpu->cpum + pDesc->offRegister;
78
79 VMCPU_ASSERT_EMT(pVCpu);
80
81 switch (pDesc->enmType)
82 {
83 case DBGFREGVALTYPE_U8:
84 *(uint8_t *)pv &= ~pfMask->u8;
85 *(uint8_t *)pv |= pValue->u8 & pfMask->u8;
86 return VINF_SUCCESS;
87
88 case DBGFREGVALTYPE_U16:
89 *(uint16_t *)pv &= ~pfMask->u16;
90 *(uint16_t *)pv |= pValue->u16 & pfMask->u16;
91 return VINF_SUCCESS;
92
93 case DBGFREGVALTYPE_U32:
94 *(uint32_t *)pv &= ~pfMask->u32;
95 *(uint32_t *)pv |= pValue->u32 & pfMask->u32;
96 return VINF_SUCCESS;
97
98 case DBGFREGVALTYPE_U64:
99 *(uint64_t *)pv &= ~pfMask->u64;
100 *(uint64_t *)pv |= pValue->u64 & pfMask->u64;
101 return VINF_SUCCESS;
102
103 case DBGFREGVALTYPE_U128:
104 {
105 RTUINT128U Val;
106 RTUInt128AssignAnd((PRTUINT128U)pv, RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u128)));
107 RTUInt128AssignOr((PRTUINT128U)pv, RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
108 return VINF_SUCCESS;
109 }
110
111 default:
112 AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
113 }
114}
115
116
117/*
118 * Set up aliases.
119 */
120#define CPUMREGALIAS_STD(Name, psz32) \
121 static DBGFREGALIAS const g_aCpumRegAliases_##Name[] = \
122 { \
123 { psz32, DBGFREGVALTYPE_U32 }, \
124 { NULL, DBGFREGVALTYPE_INVALID } \
125 }
126CPUMREGALIAS_STD(x0, "w0");
127CPUMREGALIAS_STD(x1, "w1");
128CPUMREGALIAS_STD(x2, "w2");
129CPUMREGALIAS_STD(x3, "w3");
130CPUMREGALIAS_STD(x4, "w4");
131CPUMREGALIAS_STD(x5, "w5");
132CPUMREGALIAS_STD(x6, "w6");
133CPUMREGALIAS_STD(x7, "w7");
134CPUMREGALIAS_STD(x8, "w8");
135CPUMREGALIAS_STD(x9, "w9");
136CPUMREGALIAS_STD(x10, "w10");
137CPUMREGALIAS_STD(x11, "w11");
138CPUMREGALIAS_STD(x12, "w12");
139CPUMREGALIAS_STD(x13, "w13");
140CPUMREGALIAS_STD(x14, "w14");
141CPUMREGALIAS_STD(x15, "w15");
142CPUMREGALIAS_STD(x16, "w16");
143CPUMREGALIAS_STD(x17, "w17");
144CPUMREGALIAS_STD(x18, "w18");
145CPUMREGALIAS_STD(x19, "w19");
146CPUMREGALIAS_STD(x20, "w20");
147CPUMREGALIAS_STD(x21, "w21");
148CPUMREGALIAS_STD(x22, "w22");
149CPUMREGALIAS_STD(x23, "w23");
150CPUMREGALIAS_STD(x24, "w24");
151CPUMREGALIAS_STD(x25, "w25");
152CPUMREGALIAS_STD(x26, "w26");
153CPUMREGALIAS_STD(x27, "w27");
154CPUMREGALIAS_STD(x28, "w28");
155CPUMREGALIAS_STD(x29, "w29");
156CPUMREGALIAS_STD(x30, "w30");
157#undef CPUMREGALIAS_STD
158
159
160/*
161 * Sub fields.
162 */
163/** Sub-fields for the SPSR_EL2/PSTATE register. */
164static DBGFREGSUBFIELD const g_aCpumRegFields_pstate[] =
165{
166 DBGFREGSUBFIELD_RW("sp", 0, 1, 0),
167 DBGFREGSUBFIELD_RW("el", 2, 2, 0),
168 DBGFREGSUBFIELD_RW("m4", 4, 1, 0),
169 DBGFREGSUBFIELD_RW("f", 6, 1, 0),
170 DBGFREGSUBFIELD_RW("i", 7, 1, 0),
171 DBGFREGSUBFIELD_RW("a", 8, 1, 0),
172 DBGFREGSUBFIELD_RW("d", 9, 1, 0),
173 DBGFREGSUBFIELD_RW("btype", 10, 2, 0),
174 DBGFREGSUBFIELD_RW("ssbs", 12, 1, 0),
175 DBGFREGSUBFIELD_RW("allint", 13, 1, 0),
176 DBGFREGSUBFIELD_RW("il", 20, 1, 0),
177 DBGFREGSUBFIELD_RW("ss", 21, 1, 0),
178 DBGFREGSUBFIELD_RW("pan", 22, 1, 0),
179 DBGFREGSUBFIELD_RW("uao", 23, 1, 0),
180 DBGFREGSUBFIELD_RW("dit", 24, 1, 0),
181 DBGFREGSUBFIELD_RW("tco", 25, 1, 0),
182 DBGFREGSUBFIELD_RW("v", 28, 1, 0),
183 DBGFREGSUBFIELD_RW("c", 29, 1, 0),
184 DBGFREGSUBFIELD_RW("z", 30, 1, 0),
185 DBGFREGSUBFIELD_RW("n", 31, 1, 0),
186 DBGFREGSUBFIELD_TERMINATOR()
187};
188
189/** Sub-fields for the v<n> registers. */
190static DBGFREGSUBFIELD const g_aCpumRegFields_vN[] =
191{
192 DBGFREGSUBFIELD_RW("r0", 0, 32, 0),
193 DBGFREGSUBFIELD_RW("r0.man", 0+ 0, 23, 0),
194 DBGFREGSUBFIELD_RW("r0.exp", 0+23, 8, 0),
195 DBGFREGSUBFIELD_RW("r0.sig", 0+31, 1, 0),
196 DBGFREGSUBFIELD_RW("r1", 32, 32, 0),
197 DBGFREGSUBFIELD_RW("r1.man", 32+ 0, 23, 0),
198 DBGFREGSUBFIELD_RW("r1.exp", 32+23, 8, 0),
199 DBGFREGSUBFIELD_RW("r1.sig", 32+31, 1, 0),
200 DBGFREGSUBFIELD_RW("r2", 64, 32, 0),
201 DBGFREGSUBFIELD_RW("r2.man", 64+ 0, 23, 0),
202 DBGFREGSUBFIELD_RW("r2.exp", 64+23, 8, 0),
203 DBGFREGSUBFIELD_RW("r2.sig", 64+31, 1, 0),
204 DBGFREGSUBFIELD_RW("r3", 96, 32, 0),
205 DBGFREGSUBFIELD_RW("r3.man", 96+ 0, 23, 0),
206 DBGFREGSUBFIELD_RW("r3.exp", 96+23, 8, 0),
207 DBGFREGSUBFIELD_RW("r3.sig", 96+31, 1, 0),
208 DBGFREGSUBFIELD_TERMINATOR()
209};
210
211/** @name Macros for producing register descriptor table entries.
212 * @{ */
213#define CPU_REG_EX_AS(a_szName, a_RegSuff, a_TypeSuff, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
214 { a_szName, DBGFREG_ARMV8_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /*fFlags*/, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
215
216#define CPU_GREG_REG(n) \
217 CPU_REG_RW_AS("x" #n, GREG_X##n, U64, aGRegs[n], cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_x##n, NULL)
218
219#define CPU_VREG_REG(n) \
220 CPU_REG_RW_AS("v" #n, VREG_V##n, U128, aVRegs[n], cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_vN)
221
222/** @} */
223
224
225/**
226 * The guest register descriptors.
227 */
228static DBGFREGDESC const g_aCpumRegGstDescs[] =
229{
230#define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
231 { a_szName, DBGFREG_ARMV8_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /*fFlags*/, (uint32_t)RT_UOFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
232#define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
233 { a_szName, DBGFREG_ARMV8_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, (uint32_t)RT_UOFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
234
235 CPU_GREG_REG(0),
236 CPU_GREG_REG(1),
237 CPU_GREG_REG(2),
238 CPU_GREG_REG(3),
239 CPU_GREG_REG(4),
240 CPU_GREG_REG(5),
241 CPU_GREG_REG(6),
242 CPU_GREG_REG(7),
243 CPU_GREG_REG(8),
244 CPU_GREG_REG(9),
245 CPU_GREG_REG(10),
246 CPU_GREG_REG(11),
247 CPU_GREG_REG(12),
248 CPU_GREG_REG(13),
249 CPU_GREG_REG(14),
250 CPU_GREG_REG(15),
251 CPU_GREG_REG(16),
252 CPU_GREG_REG(17),
253 CPU_GREG_REG(18),
254 CPU_GREG_REG(19),
255 CPU_GREG_REG(20),
256 CPU_GREG_REG(21),
257 CPU_GREG_REG(22),
258 CPU_GREG_REG(23),
259 CPU_GREG_REG(24),
260 CPU_GREG_REG(25),
261 CPU_GREG_REG(26),
262 CPU_GREG_REG(27),
263 CPU_GREG_REG(28),
264 CPU_GREG_REG(29),
265 CPU_GREG_REG(30),
266
267 CPU_REG_RW_AS("pc", PC, U64, Pc, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
268
269 CPU_VREG_REG(0),
270 CPU_VREG_REG(1),
271 CPU_VREG_REG(2),
272 CPU_VREG_REG(3),
273 CPU_VREG_REG(4),
274 CPU_VREG_REG(5),
275 CPU_VREG_REG(6),
276 CPU_VREG_REG(7),
277 CPU_VREG_REG(8),
278 CPU_VREG_REG(9),
279 CPU_VREG_REG(10),
280 CPU_VREG_REG(11),
281 CPU_VREG_REG(12),
282 CPU_VREG_REG(13),
283 CPU_VREG_REG(14),
284 CPU_VREG_REG(15),
285 CPU_VREG_REG(16),
286 CPU_VREG_REG(17),
287 CPU_VREG_REG(18),
288 CPU_VREG_REG(19),
289 CPU_VREG_REG(20),
290 CPU_VREG_REG(21),
291 CPU_VREG_REG(22),
292 CPU_VREG_REG(23),
293 CPU_VREG_REG(24),
294 CPU_VREG_REG(25),
295 CPU_VREG_REG(26),
296 CPU_VREG_REG(27),
297 CPU_VREG_REG(28),
298 CPU_VREG_REG(29),
299 CPU_VREG_REG(30),
300 CPU_VREG_REG(31),
301
302 CPU_REG_RW_AS("fpcr", FPCR, U64, fpcr, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
303 CPU_REG_RW_AS("fpsr", FPSR, U64, fpsr, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
304
305 CPU_REG_RW_AS("sp_el0", SP_EL0, U64, aSpReg[0], cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
306 CPU_REG_RW_AS("sp_el1", SP_EL1, U64, aSpReg[1], cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
307 CPU_REG_RW_AS("spsr_el1", SPSR_EL1, U64, Spsr, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
308 CPU_REG_RW_AS("pstate", PSTATE, U64, fPState, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_pstate ),
309 CPU_REG_RW_AS("sctlr_el1", SCTLR_EL1, U64, Sctlr, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
310 CPU_REG_RW_AS("tcr_el1", TCR_EL1, U64, Tcr, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
311 CPU_REG_RW_AS("ttbr0_el1", TTBR0_EL1, U64, Ttbr0, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
312 CPU_REG_RW_AS("ttbr1_el1", TTBR1_EL1, U64, Ttbr1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
313 CPU_REG_RW_AS("elr_el1", ELR_EL1, U64, Elr, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
314 CPU_REG_RW_AS("vbar_el1", VBAR_EL1, U64, VBar, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
315
316 CPU_REG_RW_AS("cnthctl_el2", CNTHCTL_EL2, U64, CntHCtlEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
317 CPU_REG_RW_AS("cnthp_ctl_el2", CNTHP_CTL_EL2, U64, CntHpCtlEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
318 CPU_REG_RW_AS("cnthp_cval_el2", CNTHP_CVAL_EL2, U64, CntHpCValEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
319 CPU_REG_RW_AS("cnthp_tval_el2", CNTHP_TVAL_EL2, U64, CntHpTValEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
320 CPU_REG_RW_AS("cntvoff_el2", CNTVOFF_EL2, U64, CntVOffEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
321 CPU_REG_RW_AS("cptr_el2", CPTR_EL2, U64, CptrEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
322 CPU_REG_RW_AS("elr_el2", ELR_EL2, U64, ElrEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
323 CPU_REG_RW_AS("esr_el2", ESR_EL2, U64, EsrEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
324 CPU_REG_RW_AS("far_el2", FAR_EL2, U64, FarEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
325 CPU_REG_RW_AS("hcr_el2", HCR_EL2, U64, HcrEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
326 CPU_REG_RW_AS("hpfar_el2", HPFAR_EL2, U64, HpFarEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
327 CPU_REG_RW_AS("mair_el2", MAIR_EL2, U64, MairEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
328 CPU_REG_RW_AS("mdcr_el2", MDCR_EL2, U64, MdcrEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
329 CPU_REG_RW_AS("sctlr_el2", SCTLR_EL2, U64, SctlrEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
330 CPU_REG_RW_AS("spsr_el2", SPSR_EL2, U64, SpsrEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
331 CPU_REG_RW_AS("sp_el2", SP_EL2, U64, SpEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
332 CPU_REG_RW_AS("tcr_el2", TCR_EL2, U64, TcrEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
333 CPU_REG_RW_AS("tpidr_el2", TPIDR_EL2, U64, TpidrEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
334 CPU_REG_RW_AS("ttbr0_el2", TTBR0_EL2, U64, Ttbr0El2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
335 CPU_REG_RW_AS("ttbr1_el2", TTBR1_EL2, U64, Ttbr1El2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
336 CPU_REG_RW_AS("vbar_el2", VBAR_EL2, U64, VBarEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
337 CPU_REG_RW_AS("vmpidr_el2", VMPIDR_EL2, U64, VMpidrEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
338 CPU_REG_RW_AS("vpidr_el2", VPIDR_EL2, U64, VPidrEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
339 CPU_REG_RW_AS("vtcr_el2", VTCR_EL2, U64, VTcrEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
340 CPU_REG_RW_AS("vttbr_el2", VTTBR_EL2, U64, VTtbrEl2, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
341
342 DBGFREGDESC_TERMINATOR()
343
344#undef CPU_REG_RW_AS
345#undef CPU_REG_RO_AS
346};
347
348
349/**
350 * Initializes the debugger related sides of the CPUM component.
351 *
352 * Called by CPUMR3Init.
353 *
354 * @returns VBox status code.
355 * @param pVM The cross context VM structure.
356 */
357DECLHIDDEN(int) cpumR3DbgInit(PVM pVM)
358{
359 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
360 {
361 int rc = DBGFR3RegRegisterCpu(pVM, pVM->apCpusR3[idCpu], g_aCpumRegGstDescs, true /*fGuestRegs*/);
362 AssertLogRelRCReturn(rc, rc);
363 }
364
365 return VINF_SUCCESS;
366}
367
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette