CPUM.cpp@ 97178

Last change on this file since 97178 was 97178, checked in by vboxsync, 2 years ago
VMM/CPUM,EM,HM,IEM,++: Moved VMCPU_FF_INHIBIT_INTERRUPTS and VMCPU_FF_BLOCK_NMIS to CPUMCTX::fInhibit. Moved ldtr and tr up to the CPUMCTXCORE area in hope for better cache alignment of rip, rflags and crX register fields. bugref:9941
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File size: 243.8 KB

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1	/* $Id: CPUM.cpp 97178 2022-10-17 21:06:03Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	/** @page pg_cpum CPUM - CPU Monitor / Manager
29	*
30	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
31	* also responsible for lazy FPU handling and some of the context loading
32	* in raw mode.
33	*
34	* There are three CPU contexts, the most important one is the guest one (GC).
35	* When running in raw-mode (RC) there is a special hyper context for the VMM
36	* part that floats around inside the guest address space. When running in
37	* raw-mode, CPUM also maintains a host context for saving and restoring
38	* registers across world switches. This latter is done in cooperation with the
39	* world switcher (@see pg_vmm).
40	*
41	* @see grp_cpum
42	*
43	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
44	*
45	* TODO: proper write up, currently just some notes.
46	*
47	* The ring-0 FPU handling per OS:
48	*
49	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
50	* convention (Visual C++ doesn't seem to have a way to disable
51	* generating such code either), so CR0.TS/EM are always zero from what I
52	* can tell. We are also forced to always load/save the guest XMM0-XMM15
53	* registers when entering/leaving guest context. Interrupt handlers
54	* using FPU/SSE will offically have call save and restore functions
55	* exported by the kernel, if the really really have to use the state.
56	*
57	* - 32-bit windows does lazy FPU handling, I think, probably including
58	* lazying saving. The Windows Internals book states that it's a bad
59	* idea to use the FPU in kernel space. However, it looks like it will
60	* restore the FPU state of the current thread in case of a kernel \#NM.
61	* Interrupt handlers should be same as for 64-bit.
62	*
63	* - Darwin allows taking \#NM in kernel space, restoring current thread's
64	* state if I read the code correctly. It saves the FPU state of the
65	* outgoing thread, and uses CR0.TS to lazily load the state of the
66	* incoming one. No idea yet how the FPU is treated by interrupt
67	* handlers, i.e. whether they are allowed to disable the state or
68	* something.
69	*
70	* - Linux also allows \#NM in kernel space (don't know since when), and
71	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
72	* loads the incoming unless configured to agressivly load it. Interrupt
73	* handlers can ask whether they're allowed to use the FPU, and may
74	* freely trash the state if Linux thinks it has saved the thread's state
75	* already. This is a problem.
76	*
77	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
78	* context. When switching threads, the kernel will save the state of
79	* the outgoing thread and lazy load the incoming one using CR0.TS.
80	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
81	* to do stuff, HAT are among the users. The routines there will
82	* manually clear CR0.TS and save the XMM registers they use only if
83	* CR0.TS was zero upon entry. They will skip it when not, because as
84	* mentioned above, the FPU state is saved when switching away from a
85	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
86	* preserve. This is a problem if we restore CR0.TS to 1 after loading
87	* the guest state.
88	*
89	* - FreeBSD - no idea yet.
90	*
91	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
92	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
93	* FPU states.
94	*
95	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
96	* saving and restoring the host and guest states. The motivation for this
97	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
98	*
99	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
100	* state and only restore it once we've restore the host FPU state. This has the
101	* accidental side effect of triggering Solaris to preserve XMM registers in
102	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
103	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
104	*
105	*
106	* @section sec_cpum_logging Logging Level Assignments.
107	*
108	* Following log level assignments:
109	* - Log6 is used for FPU state management.
110	* - Log7 is used for FPU state actualization.
111	*
112	*/
113
114
115	/*********************************************************************************************************************************
116	* Header Files *
117	*********************************************************************************************************************************/
118	#define LOG_GROUP LOG_GROUP_CPUM
119	#define CPUM_WITH_NONCONST_HOST_FEATURES
120	#include <VBox/vmm/cpum.h>
121	#include <VBox/vmm/cpumdis.h>
122	#include <VBox/vmm/cpumctx-v1_6.h>
123	#include <VBox/vmm/pgm.h>
124	#include <VBox/vmm/apic.h>
125	#include <VBox/vmm/mm.h>
126	#include <VBox/vmm/em.h>
127	#include <VBox/vmm/iem.h>
128	#include <VBox/vmm/selm.h>
129	#include <VBox/vmm/dbgf.h>
130	#include <VBox/vmm/hm.h>
131	#include <VBox/vmm/hmvmxinline.h>
132	#include <VBox/vmm/ssm.h>
133	#include "CPUMInternal.h"
134	#include <VBox/vmm/vm.h>
135
136	#include <VBox/param.h>
137	#include <VBox/dis.h>
138	#include <VBox/err.h>
139	#include <VBox/log.h>
140	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
141	# include <iprt/asm-amd64-x86.h>
142	#endif
143	#include <iprt/assert.h>
144	#include <iprt/cpuset.h>
145	#include <iprt/mem.h>
146	#include <iprt/mp.h>
147	#include <iprt/string.h>
148
149
150	/*********************************************************************************************************************************
151	* Defined Constants And Macros *
152	*********************************************************************************************************************************/
153	/**
154	* This was used in the saved state up to the early life of version 14.
155	*
156	* It indicates that we may have some out-of-sync hidden segement registers.
157	* It is only relevant for raw-mode.
158	*/
159	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
160
161
162	/** For saved state only: Block injection of non-maskable interrupts to the guest.
163	* @note This flag was moved to CPUMCTX::fInhibit in v7.0.2. */
164	#define CPUM_OLD_VMCPU_FF_BLOCK_NMIS RT_BIT_64(25)
165
166
167	/*********************************************************************************************************************************
168	* Structures and Typedefs *
169	*********************************************************************************************************************************/
170
171	/**
172	* What kind of cpu info dump to perform.
173	*/
174	typedef enum CPUMDUMPTYPE
175	{
176	CPUMDUMPTYPE_TERSE,
177	CPUMDUMPTYPE_DEFAULT,
178	CPUMDUMPTYPE_VERBOSE
179	} CPUMDUMPTYPE;
180	/** Pointer to a cpu info dump type. */
181	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
182
183
184	/*********************************************************************************************************************************
185	* Internal Functions *
186	*********************************************************************************************************************************/
187	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
188	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
189	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
190	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
191	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
192	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
193	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
194	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
195	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
196	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
197	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
198
199
200	/*********************************************************************************************************************************
201	* Global Variables *
202	*********************************************************************************************************************************/
203	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
204	/** Host CPU features. */
205	DECL_HIDDEN_DATA(CPUHOSTFEATURES) g_CpumHostFeatures;
206	#endif
207
208	/** Saved state field descriptors for CPUMCTX. */
209	static const SSMFIELD g_aCpumCtxFields[] =
210	{
211	SSMFIELD_ENTRY( CPUMCTX, rdi),
212	SSMFIELD_ENTRY( CPUMCTX, rsi),
213	SSMFIELD_ENTRY( CPUMCTX, rbp),
214	SSMFIELD_ENTRY( CPUMCTX, rax),
215	SSMFIELD_ENTRY( CPUMCTX, rbx),
216	SSMFIELD_ENTRY( CPUMCTX, rdx),
217	SSMFIELD_ENTRY( CPUMCTX, rcx),
218	SSMFIELD_ENTRY( CPUMCTX, rsp),
219	SSMFIELD_ENTRY( CPUMCTX, rflags),
220	SSMFIELD_ENTRY( CPUMCTX, rip),
221	SSMFIELD_ENTRY( CPUMCTX, r8),
222	SSMFIELD_ENTRY( CPUMCTX, r9),
223	SSMFIELD_ENTRY( CPUMCTX, r10),
224	SSMFIELD_ENTRY( CPUMCTX, r11),
225	SSMFIELD_ENTRY( CPUMCTX, r12),
226	SSMFIELD_ENTRY( CPUMCTX, r13),
227	SSMFIELD_ENTRY( CPUMCTX, r14),
228	SSMFIELD_ENTRY( CPUMCTX, r15),
229	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
230	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
231	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
232	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
233	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
234	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
235	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
236	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
237	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
238	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
239	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
240	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
241	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
242	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
243	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
244	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
245	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
246	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
247	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
248	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
249	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
250	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
251	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
252	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
253	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
254	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
255	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
256	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
257	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
258	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
259	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
260	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
261	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
262	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
263	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
264	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
265	SSMFIELD_ENTRY( CPUMCTX, cr0),
266	SSMFIELD_ENTRY( CPUMCTX, cr2),
267	SSMFIELD_ENTRY( CPUMCTX, cr3),
268	SSMFIELD_ENTRY( CPUMCTX, cr4),
269	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
270	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
271	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
272	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
273	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
274	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
275	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
276	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
277	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
278	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
279	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
280	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
281	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
282	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
283	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
284	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
285	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
286	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
287	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
288	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
289	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
290	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
291	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
292	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
293	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
294	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
295	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
296	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
297	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
298	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
299	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
300	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
301	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
302	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
303	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
304	SSMFIELD_ENTRY_TERM()
305	};
306
307	/** Saved state field descriptors for SVM nested hardware-virtualization
308	* Host State. */
309	static const SSMFIELD g_aSvmHwvirtHostState[] =
310	{
311	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
312	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
313	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
314	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
315	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
316	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
317	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
318	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
319	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
320	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
321	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
322	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
323	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
324	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
325	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
326	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
327	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
328	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
329	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
330	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
331	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
332	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
333	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
334	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
335	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
336	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
337	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
338	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
339	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
340	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
341	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
342	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
343	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
344	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
345	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
346	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
347	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
348	SSMFIELD_ENTRY_TERM()
349	};
350
351	/** Saved state field descriptors for VMX nested hardware-virtualization
352	* VMCS. */
353	static const SSMFIELD g_aVmxHwvirtVmcs[] =
354	{
355	SSMFIELD_ENTRY( VMXVVMCS, u32VmcsRevId),
356	SSMFIELD_ENTRY( VMXVVMCS, enmVmxAbort),
357	SSMFIELD_ENTRY( VMXVVMCS, fVmcsState),
358	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au8Padding0),
359	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved0),
360
361	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, u16Reserved0),
362
363	SSMFIELD_ENTRY( VMXVVMCS, u32RoVmInstrError),
364	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitReason),
365	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntInfo),
366	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntErrCode),
367	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringInfo),
368	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringErrCode),
369	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrLen),
370	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrInfo),
371	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32RoReserved2),
372
373	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestPhysAddr),
374	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved1),
375
376	SSMFIELD_ENTRY( VMXVVMCS, u64RoExitQual),
377	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRcx),
378	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRsi),
379	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRdi),
380	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRip),
381	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestLinearAddr),
382	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved5),
383
384	SSMFIELD_ENTRY( VMXVVMCS, u16Vpid),
385	SSMFIELD_ENTRY( VMXVVMCS, u16PostIntNotifyVector),
386	SSMFIELD_ENTRY( VMXVVMCS, u16EptpIndex),
387	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved0),
388
389	SSMFIELD_ENTRY( VMXVVMCS, u32PinCtls),
390	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls),
391	SSMFIELD_ENTRY( VMXVVMCS, u32XcptBitmap),
392	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMask),
393	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMatch),
394	SSMFIELD_ENTRY( VMXVVMCS, u32Cr3TargetCount),
395	SSMFIELD_ENTRY( VMXVVMCS, u32ExitCtls),
396	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrStoreCount),
397	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrLoadCount),
398	SSMFIELD_ENTRY( VMXVVMCS, u32EntryCtls),
399	SSMFIELD_ENTRY( VMXVVMCS, u32EntryMsrLoadCount),
400	SSMFIELD_ENTRY( VMXVVMCS, u32EntryIntInfo),
401	SSMFIELD_ENTRY( VMXVVMCS, u32EntryXcptErrCode),
402	SSMFIELD_ENTRY( VMXVVMCS, u32EntryInstrLen),
403	SSMFIELD_ENTRY( VMXVVMCS, u32TprThreshold),
404	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls2),
405	SSMFIELD_ENTRY( VMXVVMCS, u32PleGap),
406	SSMFIELD_ENTRY( VMXVVMCS, u32PleWindow),
407	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved1),
408
409	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapA),
410	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapB),
411	SSMFIELD_ENTRY( VMXVVMCS, u64AddrMsrBitmap),
412	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrStore),
413	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrLoad),
414	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEntryMsrLoad),
415	SSMFIELD_ENTRY( VMXVVMCS, u64ExecVmcsPtr),
416	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPml),
417	SSMFIELD_ENTRY( VMXVVMCS, u64TscOffset),
418	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVirtApic),
419	SSMFIELD_ENTRY( VMXVVMCS, u64AddrApicAccess),
420	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPostedIntDesc),
421	SSMFIELD_ENTRY( VMXVVMCS, u64VmFuncCtls),
422	SSMFIELD_ENTRY( VMXVVMCS, u64EptPtr),
423	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap0),
424	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap1),
425	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap2),
426	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap3),
427	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEptpList),
428	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmreadBitmap),
429	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmwriteBitmap),
430	SSMFIELD_ENTRY( VMXVVMCS, u64AddrXcptVeInfo),
431	SSMFIELD_ENTRY( VMXVVMCS, u64XssExitBitmap),
432	SSMFIELD_ENTRY( VMXVVMCS, u64EnclsExitBitmap),
433	SSMFIELD_ENTRY( VMXVVMCS, u64SppTablePtr),
434	SSMFIELD_ENTRY( VMXVVMCS, u64TscMultiplier),
435	SSMFIELD_ENTRY_VER( VMXVVMCS, u64ProcCtls3, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
436	SSMFIELD_ENTRY_VER( VMXVVMCS, u64EnclvExitBitmap, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
437	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved0),
438
439	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0Mask),
440	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4Mask),
441	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0ReadShadow),
442	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4ReadShadow),
443	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target0),
444	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target1),
445	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target2),
446	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target3),
447	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved4),
448
449	SSMFIELD_ENTRY( VMXVVMCS, HostEs),
450	SSMFIELD_ENTRY( VMXVVMCS, HostCs),
451	SSMFIELD_ENTRY( VMXVVMCS, HostSs),
452	SSMFIELD_ENTRY( VMXVVMCS, HostDs),
453	SSMFIELD_ENTRY( VMXVVMCS, HostFs),
454	SSMFIELD_ENTRY( VMXVVMCS, HostGs),
455	SSMFIELD_ENTRY( VMXVVMCS, HostTr),
456	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved2),
457
458	SSMFIELD_ENTRY( VMXVVMCS, u32HostSysenterCs),
459	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved4),
460
461	SSMFIELD_ENTRY( VMXVVMCS, u64HostPatMsr),
462	SSMFIELD_ENTRY( VMXVVMCS, u64HostEferMsr),
463	SSMFIELD_ENTRY( VMXVVMCS, u64HostPerfGlobalCtlMsr),
464	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
465	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved3),
466
467	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr0),
468	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr3),
469	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr4),
470	SSMFIELD_ENTRY( VMXVVMCS, u64HostFsBase),
471	SSMFIELD_ENTRY( VMXVVMCS, u64HostGsBase),
472	SSMFIELD_ENTRY( VMXVVMCS, u64HostTrBase),
473	SSMFIELD_ENTRY( VMXVVMCS, u64HostGdtrBase),
474	SSMFIELD_ENTRY( VMXVVMCS, u64HostIdtrBase),
475	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEsp),
476	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEip),
477	SSMFIELD_ENTRY( VMXVVMCS, u64HostRsp),
478	SSMFIELD_ENTRY( VMXVVMCS, u64HostRip),
479	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
480	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
481	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
482	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved7),
483
484	SSMFIELD_ENTRY( VMXVVMCS, GuestEs),
485	SSMFIELD_ENTRY( VMXVVMCS, GuestCs),
486	SSMFIELD_ENTRY( VMXVVMCS, GuestSs),
487	SSMFIELD_ENTRY( VMXVVMCS, GuestDs),
488	SSMFIELD_ENTRY( VMXVVMCS, GuestFs),
489	SSMFIELD_ENTRY( VMXVVMCS, GuestGs),
490	SSMFIELD_ENTRY( VMXVVMCS, GuestLdtr),
491	SSMFIELD_ENTRY( VMXVVMCS, GuestTr),
492	SSMFIELD_ENTRY( VMXVVMCS, u16GuestIntStatus),
493	SSMFIELD_ENTRY( VMXVVMCS, u16PmlIndex),
494	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved1),
495
496	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsLimit),
497	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsLimit),
498	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsLimit),
499	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsLimit),
500	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsLimit),
501	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsLimit),
502	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrLimit),
503	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrLimit),
504	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGdtrLimit),
505	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIdtrLimit),
506	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsAttr),
507	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsAttr),
508	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsAttr),
509	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsAttr),
510	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsAttr),
511	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsAttr),
512	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrAttr),
513	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrAttr),
514	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIntrState),
515	SSMFIELD_ENTRY( VMXVVMCS, u32GuestActivityState),
516	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSmBase),
517	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSysenterCS),
518	SSMFIELD_ENTRY( VMXVVMCS, u32PreemptTimer),
519	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved3),
520
521	SSMFIELD_ENTRY( VMXVVMCS, u64VmcsLinkPtr),
522	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDebugCtlMsr),
523	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPatMsr),
524	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEferMsr),
525	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPerfGlobalCtlMsr),
526	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte0),
527	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte1),
528	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte2),
529	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte3),
530	SSMFIELD_ENTRY( VMXVVMCS, u64GuestBndcfgsMsr),
531	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRtitCtlMsr),
532	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
533	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved2),
534
535	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr0),
536	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr3),
537	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr4),
538	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEsBase),
539	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCsBase),
540	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSsBase),
541	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDsBase),
542	SSMFIELD_ENTRY( VMXVVMCS, u64GuestFsBase),
543	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGsBase),
544	SSMFIELD_ENTRY( VMXVVMCS, u64GuestLdtrBase),
545	SSMFIELD_ENTRY( VMXVVMCS, u64GuestTrBase),
546	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGdtrBase),
547	SSMFIELD_ENTRY( VMXVVMCS, u64GuestIdtrBase),
548	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDr7),
549	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRsp),
550	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRip),
551	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRFlags),
552	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPendingDbgXcpts),
553	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEsp),
554	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEip),
555	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
556	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
557	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
558	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved6),
559
560	SSMFIELD_ENTRY_TERM()
561	};
562
563	/** Saved state field descriptors for CPUMCTX. */
564	static const SSMFIELD g_aCpumX87Fields[] =
565	{
566	SSMFIELD_ENTRY( X86FXSTATE, FCW),
567	SSMFIELD_ENTRY( X86FXSTATE, FSW),
568	SSMFIELD_ENTRY( X86FXSTATE, FTW),
569	SSMFIELD_ENTRY( X86FXSTATE, FOP),
570	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
571	SSMFIELD_ENTRY( X86FXSTATE, CS),
572	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
573	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
574	SSMFIELD_ENTRY( X86FXSTATE, DS),
575	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
576	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
577	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
578	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
579	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
580	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
581	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
582	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
583	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
584	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
585	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
586	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
587	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
588	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
589	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
590	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
591	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
592	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
593	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
594	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
595	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
596	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
597	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
598	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
599	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
600	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
601	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
602	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
603	SSMFIELD_ENTRY_TERM()
604	};
605
606	/** Saved state field descriptors for X86XSAVEHDR. */
607	static const SSMFIELD g_aCpumXSaveHdrFields[] =
608	{
609	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
610	SSMFIELD_ENTRY_TERM()
611	};
612
613	/** Saved state field descriptors for X86XSAVEYMMHI. */
614	static const SSMFIELD g_aCpumYmmHiFields[] =
615	{
616	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
617	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
618	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
619	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
620	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
621	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
622	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
623	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
624	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
625	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
626	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
627	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
628	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
629	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
630	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
631	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
632	SSMFIELD_ENTRY_TERM()
633	};
634
635	/** Saved state field descriptors for X86XSAVEBNDREGS. */
636	static const SSMFIELD g_aCpumBndRegsFields[] =
637	{
638	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
639	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
640	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
641	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
642	SSMFIELD_ENTRY_TERM()
643	};
644
645	/** Saved state field descriptors for X86XSAVEBNDCFG. */
646	static const SSMFIELD g_aCpumBndCfgFields[] =
647	{
648	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
649	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
650	SSMFIELD_ENTRY_TERM()
651	};
652
653	#if 0 /** @todo */
654	/** Saved state field descriptors for X86XSAVEOPMASK. */
655	static const SSMFIELD g_aCpumOpmaskFields[] =
656	{
657	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
658	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
659	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
660	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
661	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
662	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
663	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
664	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
665	SSMFIELD_ENTRY_TERM()
666	};
667	#endif
668
669	/** Saved state field descriptors for X86XSAVEZMMHI256. */
670	static const SSMFIELD g_aCpumZmmHi256Fields[] =
671	{
672	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
673	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
674	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
675	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
676	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
677	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
678	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
679	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
680	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
681	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
682	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
683	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
684	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
685	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
686	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
687	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
688	SSMFIELD_ENTRY_TERM()
689	};
690
691	/** Saved state field descriptors for X86XSAVEZMM16HI. */
692	static const SSMFIELD g_aCpumZmm16HiFields[] =
693	{
694	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
695	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
696	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
697	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
698	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
699	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
700	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
701	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
702	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
703	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
704	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
705	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
706	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
707	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
708	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
709	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
710	SSMFIELD_ENTRY_TERM()
711	};
712
713
714
715	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
716	* registeres changed. */
717	static const SSMFIELD g_aCpumX87FieldsMem[] =
718	{
719	SSMFIELD_ENTRY( X86FXSTATE, FCW),
720	SSMFIELD_ENTRY( X86FXSTATE, FSW),
721	SSMFIELD_ENTRY( X86FXSTATE, FTW),
722	SSMFIELD_ENTRY( X86FXSTATE, FOP),
723	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
724	SSMFIELD_ENTRY( X86FXSTATE, CS),
725	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
726	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
727	SSMFIELD_ENTRY( X86FXSTATE, DS),
728	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
729	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
730	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
731	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
732	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
733	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
734	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
735	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
736	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
737	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
738	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
739	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
740	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
741	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
742	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
743	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
744	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
745	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
746	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
747	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
748	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
749	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
750	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
751	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
752	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
753	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
754	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
755	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
756	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
757	};
758
759	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
760	* registeres changed. */
761	static const SSMFIELD g_aCpumCtxFieldsMem[] =
762	{
763	SSMFIELD_ENTRY( CPUMCTX, rdi),
764	SSMFIELD_ENTRY( CPUMCTX, rsi),
765	SSMFIELD_ENTRY( CPUMCTX, rbp),
766	SSMFIELD_ENTRY( CPUMCTX, rax),
767	SSMFIELD_ENTRY( CPUMCTX, rbx),
768	SSMFIELD_ENTRY( CPUMCTX, rdx),
769	SSMFIELD_ENTRY( CPUMCTX, rcx),
770	SSMFIELD_ENTRY( CPUMCTX, rsp),
771	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
772	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
773	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
774	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
775	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
776	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
777	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
778	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
779	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
780	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
781	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
782	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
783	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
784	SSMFIELD_ENTRY( CPUMCTX, rflags),
785	SSMFIELD_ENTRY( CPUMCTX, rip),
786	SSMFIELD_ENTRY( CPUMCTX, r8),
787	SSMFIELD_ENTRY( CPUMCTX, r9),
788	SSMFIELD_ENTRY( CPUMCTX, r10),
789	SSMFIELD_ENTRY( CPUMCTX, r11),
790	SSMFIELD_ENTRY( CPUMCTX, r12),
791	SSMFIELD_ENTRY( CPUMCTX, r13),
792	SSMFIELD_ENTRY( CPUMCTX, r14),
793	SSMFIELD_ENTRY( CPUMCTX, r15),
794	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
795	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
796	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
797	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
798	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
799	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
800	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
801	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
802	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
803	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
804	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
805	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
806	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
807	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
808	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
809	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
810	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
811	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
812	SSMFIELD_ENTRY( CPUMCTX, cr0),
813	SSMFIELD_ENTRY( CPUMCTX, cr2),
814	SSMFIELD_ENTRY( CPUMCTX, cr3),
815	SSMFIELD_ENTRY( CPUMCTX, cr4),
816	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
817	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
818	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
819	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
820	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
821	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
822	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
823	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
824	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
825	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
826	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
827	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
828	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
829	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
830	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
831	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
832	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
833	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
834	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
835	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
836	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
837	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
838	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
839	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
840	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
841	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
842	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
843	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
844	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
845	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
846	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
847	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
848	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
849	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
850	SSMFIELD_ENTRY_TERM()
851	};
852
853	/** Saved state field descriptors for CPUMCTX_VER1_6. */
854	static const SSMFIELD g_aCpumX87FieldsV16[] =
855	{
856	SSMFIELD_ENTRY( X86FXSTATE, FCW),
857	SSMFIELD_ENTRY( X86FXSTATE, FSW),
858	SSMFIELD_ENTRY( X86FXSTATE, FTW),
859	SSMFIELD_ENTRY( X86FXSTATE, FOP),
860	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
861	SSMFIELD_ENTRY( X86FXSTATE, CS),
862	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
863	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
864	SSMFIELD_ENTRY( X86FXSTATE, DS),
865	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
866	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
867	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
868	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
869	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
870	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
871	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
872	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
873	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
874	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
875	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
876	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
877	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
878	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
879	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
880	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
881	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
882	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
883	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
884	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
885	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
886	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
887	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
888	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
889	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
890	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
891	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
892	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
893	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
894	SSMFIELD_ENTRY_TERM()
895	};
896
897	/** Saved state field descriptors for CPUMCTX_VER1_6. */
898	static const SSMFIELD g_aCpumCtxFieldsV16[] =
899	{
900	SSMFIELD_ENTRY( CPUMCTX, rdi),
901	SSMFIELD_ENTRY( CPUMCTX, rsi),
902	SSMFIELD_ENTRY( CPUMCTX, rbp),
903	SSMFIELD_ENTRY( CPUMCTX, rax),
904	SSMFIELD_ENTRY( CPUMCTX, rbx),
905	SSMFIELD_ENTRY( CPUMCTX, rdx),
906	SSMFIELD_ENTRY( CPUMCTX, rcx),
907	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
908	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
909	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
910	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
911	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
912	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
913	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
914	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
915	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
916	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
917	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
918	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
919	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
920	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
921	SSMFIELD_ENTRY( CPUMCTX, rflags),
922	SSMFIELD_ENTRY( CPUMCTX, rip),
923	SSMFIELD_ENTRY( CPUMCTX, r8),
924	SSMFIELD_ENTRY( CPUMCTX, r9),
925	SSMFIELD_ENTRY( CPUMCTX, r10),
926	SSMFIELD_ENTRY( CPUMCTX, r11),
927	SSMFIELD_ENTRY( CPUMCTX, r12),
928	SSMFIELD_ENTRY( CPUMCTX, r13),
929	SSMFIELD_ENTRY( CPUMCTX, r14),
930	SSMFIELD_ENTRY( CPUMCTX, r15),
931	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
932	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
933	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
934	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
935	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
936	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
937	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
938	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
939	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
940	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
941	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
942	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
943	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
944	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
945	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
946	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
947	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
948	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
949	SSMFIELD_ENTRY( CPUMCTX, cr0),
950	SSMFIELD_ENTRY( CPUMCTX, cr2),
951	SSMFIELD_ENTRY( CPUMCTX, cr3),
952	SSMFIELD_ENTRY( CPUMCTX, cr4),
953	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
954	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
955	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
956	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
957	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
958	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
959	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
960	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
961	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
962	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
963	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
964	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
965	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
966	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
967	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
968	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
969	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
970	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
971	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
972	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
973	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
974	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
975	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
976	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
977	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
978	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
979	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
980	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
981	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
982	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
983	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
984	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
985	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
986	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
987	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
988	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
989	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
990	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
991	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
992	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
993	SSMFIELD_ENTRY_TERM()
994	};
995
996
997	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
998	/**
999	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
1000	*
1001	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
1002	* (last instruction pointer, last data pointer, last opcode) except when the ES
1003	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
1004	* clear these registers there is potential, local FPU leakage from a process
1005	* using the FPU to another.
1006	*
1007	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
1008	*
1009	* @param pVM The cross context VM structure.
1010	*/
1011	static void cpumR3CheckLeakyFpu(PVM pVM)
1012	{
1013	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
1014	uint32_t const u32Family = u32CpuVersion >> 8;
1015	if ( u32Family >= 6 /* K7 and higher */
1016	&& (ASMIsAmdCpu() \|\| ASMIsHygonCpu()) )
1017	{
1018	uint32_t cExt = ASMCpuId_EAX(0x80000000);
1019	if (RTX86IsValidExtRange(cExt))
1020	{
1021	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
1022	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1023	{
1024	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1025	{
1026	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1027	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
1028	}
1029	Log(("CPUM: Host CPU has leaky fxsave/fxrstor behaviour\n"));
1030	}
1031	}
1032	}
1033	}
1034	#endif
1035
1036
1037	/**
1038	* Initialize the SVM hardware virtualization state.
1039	*
1040	* @param pVM The cross context VM structure.
1041	*/
1042	static void cpumR3InitSvmHwVirtState(PVM pVM)
1043	{
1044	LogRel(("CPUM: AMD-V nested-guest init\n"));
1045	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1046	{
1047	PVMCPU pVCpu = pVM->apCpusR3[i];
1048	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1049
1050	/* Initialize that SVM hardware virtualization is available. */
1051	pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
1052
1053	AssertCompile(sizeof(pCtx->hwvirt.svm.Vmcb) == SVM_VMCB_PAGES * X86_PAGE_SIZE);
1054	AssertCompile(sizeof(pCtx->hwvirt.svm.abMsrBitmap) == SVM_MSRPM_PAGES * X86_PAGE_SIZE);
1055	AssertCompile(sizeof(pCtx->hwvirt.svm.abIoBitmap) == SVM_IOPM_PAGES * X86_PAGE_SIZE);
1056
1057	/* Initialize non-zero values. */
1058	pCtx->hwvirt.svm.GCPhysVmcb = NIL_RTGCPHYS;
1059	}
1060	}
1061
1062
1063	/**
1064	* Resets per-VCPU SVM hardware virtualization state.
1065	*
1066	* @param pVCpu The cross context virtual CPU structure.
1067	*/
1068	DECLINLINE(void) cpumR3ResetSvmHwVirtState(PVMCPU pVCpu)
1069	{
1070	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1071	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1072
1073	RT_ZERO(pCtx->hwvirt.svm.Vmcb);
1074	RT_ZERO(pCtx->hwvirt.svm.HostState);
1075	RT_ZERO(pCtx->hwvirt.svm.abMsrBitmap);
1076	RT_ZERO(pCtx->hwvirt.svm.abIoBitmap);
1077
1078	pCtx->hwvirt.svm.uMsrHSavePa = 0;
1079	pCtx->hwvirt.svm.uPrevPauseTick = 0;
1080	pCtx->hwvirt.svm.GCPhysVmcb = NIL_RTGCPHYS;
1081	pCtx->hwvirt.svm.cPauseFilter = 0;
1082	pCtx->hwvirt.svm.cPauseFilterThreshold = 0;
1083	pCtx->hwvirt.svm.fInterceptEvents = false;
1084	}
1085
1086
1087	/**
1088	* Initializes the VMX hardware virtualization state.
1089	*
1090	* @param pVM The cross context VM structure.
1091	*/
1092	static void cpumR3InitVmxHwVirtState(PVM pVM)
1093	{
1094	LogRel(("CPUM: VT-x nested-guest init\n"));
1095	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1096	{
1097	PVMCPU pVCpu = pVM->apCpusR3[i];
1098	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1099
1100	/* Initialize that VMX hardware virtualization is available. */
1101	pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
1102
1103	AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_PAGES * X86_PAGE_SIZE);
1104	AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_SIZE);
1105	AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_PAGES * X86_PAGE_SIZE);
1106	AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_SIZE);
1107	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1108	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1109	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1110	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1111	AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1112	AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1113	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1114	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_SIZE);
1115	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1116	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1117	AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_PAGES * X86_PAGE_SIZE);
1118	AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_SIZE);
1119	AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == (VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES) * X86_PAGE_SIZE);
1120	AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
1121
1122	/* Initialize non-zero values. */
1123	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1124	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1125	pCtx->hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS;
1126	}
1127	}
1128
1129
1130	/**
1131	* Resets per-VCPU VMX hardware virtualization state.
1132	*
1133	* @param pVCpu The cross context virtual CPU structure.
1134	*/
1135	DECLINLINE(void) cpumR3ResetVmxHwVirtState(PVMCPU pVCpu)
1136	{
1137	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1138	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1139
1140	RT_ZERO(pCtx->hwvirt.vmx.Vmcs);
1141	RT_ZERO(pCtx->hwvirt.vmx.ShadowVmcs);
1142	RT_ZERO(pCtx->hwvirt.vmx.abVmreadBitmap);
1143	RT_ZERO(pCtx->hwvirt.vmx.abVmwriteBitmap);
1144	RT_ZERO(pCtx->hwvirt.vmx.aEntryMsrLoadArea);
1145	RT_ZERO(pCtx->hwvirt.vmx.aExitMsrStoreArea);
1146	RT_ZERO(pCtx->hwvirt.vmx.aExitMsrLoadArea);
1147	RT_ZERO(pCtx->hwvirt.vmx.abMsrBitmap);
1148	RT_ZERO(pCtx->hwvirt.vmx.abIoBitmap);
1149
1150	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1151	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1152	pCtx->hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS;
1153	pCtx->hwvirt.vmx.fInVmxRootMode = false;
1154	pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1155	/* Don't reset diagnostics here. */
1156
1157	pCtx->hwvirt.vmx.fInterceptEvents = false;
1158	pCtx->hwvirt.vmx.fNmiUnblockingIret = false;
1159	pCtx->hwvirt.vmx.uFirstPauseLoopTick = 0;
1160	pCtx->hwvirt.vmx.uPrevPauseTick = 0;
1161	pCtx->hwvirt.vmx.uEntryTick = 0;
1162	pCtx->hwvirt.vmx.offVirtApicWrite = 0;
1163	pCtx->hwvirt.vmx.fVirtNmiBlocking = false;
1164
1165	/* Stop any VMX-preemption timer. */
1166	CPUMStopGuestVmxPremptTimer(pVCpu);
1167
1168	/* Clear all nested-guest FFs. */
1169	VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
1170	}
1171
1172
1173	/**
1174	* Displays the host and guest VMX features.
1175	*
1176	* @param pVM The cross context VM structure.
1177	* @param pHlp The info helper functions.
1178	* @param pszArgs "terse", "default" or "verbose".
1179	*/
1180	DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1181	{
1182	RT_NOREF(pszArgs);
1183	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
1184	PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
1185	if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
1186	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA
1187	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_SHANGHAI)
1188	{
1189	#define VMXFEATDUMP(a_szDesc, a_Var) \
1190	pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
1191
1192	pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
1193	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1194	VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
1195	/* Basic. */
1196	VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
1197
1198	/* Pin-based controls. */
1199	VMXFEATDUMP("ExtIntExit - External interrupt exiting ", fVmxExtIntExit);
1200	VMXFEATDUMP("NmiExit - NMI exiting ", fVmxNmiExit);
1201	VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
1202	VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
1203	VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
1204
1205	/* Processor-based controls. */
1206	VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
1207	VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
1208	VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
1209	VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
1210	VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
1211	VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
1212	VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
1213	VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1214	VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1215	VMXFEATDUMP("TertiaryExecCtls - Activate tertiary controls ", fVmxTertiaryExecCtls);
1216	VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1217	VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1218	VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1219	VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1220	VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1221	VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1222	VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1223	VMXFEATDUMP("MonitorTrapFlag - Monitor Trap Flag ", fVmxMonitorTrapFlag);
1224	VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1225	VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1226	VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1227	VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1228
1229	/* Secondary processor-based controls. */
1230	VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1231	VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1232	VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1233	VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1234	VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
1235	VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1236	VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1237	VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1238	VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1239	VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1240	VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1241	VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1242	VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1243	VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1244	VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1245	VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1246	VMXFEATDUMP("PML - Page-Modification Log (PML) ", fVmxPml);
1247	VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1248	VMXFEATDUMP("ConcealVmxFromPt - Conceal VMX from Processor Trace ", fVmxConcealVmxFromPt);
1249	VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1250	VMXFEATDUMP("ModeBasedExecuteEpt - Mode-based execute permissions ", fVmxModeBasedExecuteEpt);
1251	VMXFEATDUMP("SppEpt - Sub-page page write permissions for EPT ", fVmxSppEpt);
1252	VMXFEATDUMP("PtEpt - Processor Trace address' translatable by EPT ", fVmxPtEpt);
1253	VMXFEATDUMP("UseTscScaling - Use TSC scaling ", fVmxUseTscScaling);
1254	VMXFEATDUMP("UserWaitPause - Enable TPAUSE, UMONITOR and UMWAIT ", fVmxUserWaitPause);
1255	VMXFEATDUMP("EnclvExit - ENCLV exiting ", fVmxEnclvExit);
1256
1257	/* Tertiary processor-based controls. */
1258	VMXFEATDUMP("LoadIwKeyExit - LOADIWKEY exiting ", fVmxLoadIwKeyExit);
1259
1260	/* VM-entry controls. */
1261	VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1262	VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1263	VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER MSR on VM-entry ", fVmxEntryLoadEferMsr);
1264	VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT MSR on VM-entry ", fVmxEntryLoadPatMsr);
1265
1266	/* VM-exit controls. */
1267	VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1268	VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1269	VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1270	VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT MSR on VM-exit ", fVmxExitSavePatMsr);
1271	VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT MSR on VM-exit ", fVmxExitLoadPatMsr);
1272	VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER MSR on VM-exit ", fVmxExitSaveEferMsr);
1273	VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER MSR on VM-exit ", fVmxExitLoadEferMsr);
1274	VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1275
1276	/* Miscellaneous data. */
1277	VMXFEATDUMP("ExitSaveEferLma - Save IA32_EFER.LMA on VM-exit ", fVmxExitSaveEferLma);
1278	VMXFEATDUMP("IntelPt - Intel PT (Processor Trace) in VMX operation ", fVmxPt);
1279	VMXFEATDUMP("VmwriteAll - VMWRITE to any supported VMCS field ", fVmxVmwriteAll);
1280	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1281	#undef VMXFEATDUMP
1282	}
1283	else
1284	pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1285	}
1286
1287
1288	/**
1289	* Checks whether nested-guest execution using hardware-assisted VMX (e.g, using HM
1290	* or NEM) is allowed.
1291	*
1292	* @returns @c true if hardware-assisted nested-guest execution is allowed, @c false
1293	* otherwise.
1294	* @param pVM The cross context VM structure.
1295	*/
1296	static bool cpumR3IsHwAssistNstGstExecAllowed(PVM pVM)
1297	{
1298	AssertMsg(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET, ("Calling this function too early!\n"));
1299	#ifndef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
1300	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT
1301	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1302	return true;
1303	#else
1304	NOREF(pVM);
1305	#endif
1306	return false;
1307	}
1308
1309
1310	/**
1311	* Initializes the VMX guest MSRs from guest CPU features based on the host MSRs.
1312	*
1313	* @param pVM The cross context VM structure.
1314	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1315	* and no hardware-assisted nested-guest execution is
1316	* possible for this VM.
1317	* @param pGuestFeatures The guest features to use (only VMX features are
1318	* accessed).
1319	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1320	*
1321	* @remarks This function ASSUMES the VMX guest-features are already exploded!
1322	*/
1323	static void cpumR3InitVmxGuestMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PCCPUMFEATURES pGuestFeatures, PVMXMSRS pGuestVmxMsrs)
1324	{
1325	bool const fIsNstGstHwExecAllowed = cpumR3IsHwAssistNstGstExecAllowed(pVM);
1326
1327	Assert(!fIsNstGstHwExecAllowed \|\| pHostVmxMsrs);
1328	Assert(pGuestFeatures->fVmx);
1329
1330	/* Basic information. */
1331	uint8_t const fTrueVmxMsrs = 1;
1332	{
1333	uint64_t const u64Basic = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1334	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1335	\| RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, !pGuestFeatures->fLongMode )
1336	\| RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1337	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1338	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1339	\| RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, fTrueVmxMsrs );
1340	pGuestVmxMsrs->u64Basic = u64Basic;
1341	}
1342
1343	/* Pin-based VM-execution controls. */
1344	{
1345	uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1346	\| (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1347	\| (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1348	\| (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1349	\| (pGuestFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1350	uint32_t const fAllowed0 = VMX_PIN_CTLS_DEFAULT1;
1351	uint32_t const fAllowed1 = fFeatures \| VMX_PIN_CTLS_DEFAULT1;
1352	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n",
1353	fAllowed0, fAllowed1, fFeatures));
1354	pGuestVmxMsrs->PinCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1355
1356	/* True pin-based VM-execution controls. */
1357	if (fTrueVmxMsrs)
1358	{
1359	/* VMX_PIN_CTLS_DEFAULT1 contains MB1 reserved bits and must be reserved MB1 in true pin-based controls as well. */
1360	pGuestVmxMsrs->TruePinCtls.u = pGuestVmxMsrs->PinCtls.u;
1361	}
1362	}
1363
1364	/* Processor-based VM-execution controls. */
1365	{
1366	uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1367	\| (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1368	\| (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1369	\| (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1370	\| (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1371	\| (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1372	\| (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1373	\| (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1374	\| (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1375	\| (pGuestFeatures->fVmxTertiaryExecCtls << VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_SHIFT )
1376	\| (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1377	\| (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1378	\| (pGuestFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1379	\| (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1380	\| (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1381	\| (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1382	\| (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1383	\| (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1384	\| (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1385	\| (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1386	\| (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1387	\| (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1388	uint32_t const fAllowed0 = VMX_PROC_CTLS_DEFAULT1;
1389	uint32_t const fAllowed1 = fFeatures \| VMX_PROC_CTLS_DEFAULT1;
1390	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1391	fAllowed1, fFeatures));
1392	pGuestVmxMsrs->ProcCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1393
1394	/* True processor-based VM-execution controls. */
1395	if (fTrueVmxMsrs)
1396	{
1397	/* VMX_PROC_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved. */
1398	uint32_t const fTrueAllowed0 = VMX_PROC_CTLS_DEFAULT1 & ~( VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK
1399	\| VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK);
1400	uint32_t const fTrueAllowed1 = fFeatures \| fTrueAllowed0;
1401	pGuestVmxMsrs->TrueProcCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1402	}
1403	}
1404
1405	/* Secondary processor-based VM-execution controls. */
1406	if (pGuestFeatures->fVmxSecondaryExecCtls)
1407	{
1408	uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1409	\| (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1410	\| (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1411	\| (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1412	\| (pGuestFeatures->fVmxVirtX2ApicMode << VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT )
1413	\| (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1414	\| (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1415	\| (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT )
1416	\| (pGuestFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1417	\| (pGuestFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1418	\| (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1419	\| (pGuestFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1420	\| (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1421	\| (pGuestFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1422	\| (pGuestFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1423	\| (pGuestFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1424	\| (pGuestFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1425	\| (pGuestFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1426	\| (pGuestFeatures->fVmxConcealVmxFromPt << VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT)
1427	\| (pGuestFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1428	\| (pGuestFeatures->fVmxModeBasedExecuteEpt << VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT)
1429	\| (pGuestFeatures->fVmxSppEpt << VMX_BF_PROC_CTLS2_SPP_EPT_SHIFT )
1430	\| (pGuestFeatures->fVmxPtEpt << VMX_BF_PROC_CTLS2_PT_EPT_SHIFT )
1431	\| (pGuestFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT )
1432	\| (pGuestFeatures->fVmxUserWaitPause << VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT )
1433	\| (pGuestFeatures->fVmxEnclvExit << VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT );
1434	uint32_t const fAllowed0 = 0;
1435	uint32_t const fAllowed1 = fFeatures;
1436	pGuestVmxMsrs->ProcCtls2.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1437	}
1438
1439	/* Tertiary processor-based VM-execution controls. */
1440	if (pGuestFeatures->fVmxTertiaryExecCtls)
1441	{
1442	pGuestVmxMsrs->u64ProcCtls3 = (pGuestFeatures->fVmxLoadIwKeyExit << VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_SHIFT);
1443	}
1444
1445	/* VM-exit controls. */
1446	{
1447	uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1448	\| (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1449	\| (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1450	\| (pGuestFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1451	\| (pGuestFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1452	\| (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1453	\| (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1454	\| (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT );
1455	/* Set the default1 class bits. See Intel spec. A.4 "VM-exit Controls". */
1456	uint32_t const fAllowed0 = VMX_EXIT_CTLS_DEFAULT1;
1457	uint32_t const fAllowed1 = fFeatures \| VMX_EXIT_CTLS_DEFAULT1;
1458	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1459	fAllowed1, fFeatures));
1460	pGuestVmxMsrs->ExitCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1461
1462	/* True VM-exit controls. */
1463	if (fTrueVmxMsrs)
1464	{
1465	/* VMX_EXIT_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved */
1466	uint32_t const fTrueAllowed0 = VMX_EXIT_CTLS_DEFAULT1 & ~VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK;
1467	uint32_t const fTrueAllowed1 = fFeatures \| fTrueAllowed0;
1468	pGuestVmxMsrs->TrueExitCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1469	}
1470	}
1471
1472	/* VM-entry controls. */
1473	{
1474	uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1475	\| (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1476	\| (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1477	\| (pGuestFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1478	uint32_t const fAllowed0 = VMX_ENTRY_CTLS_DEFAULT1;
1479	uint32_t const fAllowed1 = fFeatures \| VMX_ENTRY_CTLS_DEFAULT1;
1480	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed0=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1481	fAllowed1, fFeatures));
1482	pGuestVmxMsrs->EntryCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1483
1484	/* True VM-entry controls. */
1485	if (fTrueVmxMsrs)
1486	{
1487	/* VMX_ENTRY_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved */
1488	uint32_t const fTrueAllowed0 = VMX_ENTRY_CTLS_DEFAULT1 & ~( VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK
1489	\| VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK
1490	\| VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK
1491	\| VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK);
1492	uint32_t const fTrueAllowed1 = fFeatures \| fTrueAllowed0;
1493	pGuestVmxMsrs->TrueEntryCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1494	}
1495	}
1496
1497	/* Miscellaneous data. */
1498	{
1499	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Misc : 0;
1500
1501	uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_AUTOMSR_COUNT_MAX);
1502	uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK;
1503	pGuestVmxMsrs->u64Misc = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1504	\| RT_BF_MAKE(VMX_BF_MISC_EXIT_SAVE_EFER_LMA, pGuestFeatures->fVmxExitSaveEferLma )
1505	\| RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState )
1506	\| RT_BF_MAKE(VMX_BF_MISC_INTEL_PT, pGuestFeatures->fVmxPt )
1507	\| RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1508	\| RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1509	\| RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1510	\| RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1511	\| RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pGuestFeatures->fVmxVmwriteAll )
1512	\| RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pGuestFeatures->fVmxEntryInjectSoftInt)
1513	\| RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1514	}
1515
1516	/* CR0 Fixed-0 (we report this fixed value regardless of whether UX is supported as it does on real hardware). */
1517	pGuestVmxMsrs->u64Cr0Fixed0 = VMX_V_CR0_FIXED0;
1518
1519	/* CR0 Fixed-1. */
1520	{
1521	/*
1522	* All CPUs I've looked at so far report CR0 fixed-1 bits as 0xffffffff.
1523	* This is different from CR4 fixed-1 bits which are reported as per the
1524	* CPU features and/or micro-architecture/generation. Why? Ask Intel.
1525	*/
1526	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr0Fixed1 : VMX_V_CR0_FIXED1;
1527	pGuestVmxMsrs->u64Cr0Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr0Fixed0; /* Make sure the CR0 MB1 bits are not clear. */
1528	}
1529
1530	/* CR4 Fixed-0. */
1531	pGuestVmxMsrs->u64Cr4Fixed0 = VMX_V_CR4_FIXED0;
1532
1533	/* CR4 Fixed-1. */
1534	{
1535	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr4Fixed1 : CPUMGetGuestCR4ValidMask(pVM);
1536	pGuestVmxMsrs->u64Cr4Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr4Fixed0; /* Make sure the CR4 MB1 bits are not clear. */
1537	}
1538
1539	/* VMCS Enumeration. */
1540	pGuestVmxMsrs->u64VmcsEnum = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1541
1542	/* VPID and EPT Capabilities. */
1543	if (pGuestFeatures->fVmxEpt)
1544	{
1545	/*
1546	* INVVPID instruction always causes a VM-exit unconditionally, so we are free to fake
1547	* and emulate any INVVPID flush type. However, it only makes sense to expose the types
1548	* when INVVPID instruction is supported just to be more compatible with guest
1549	* hypervisors that may make assumptions by only looking at this MSR even though they
1550	* are technically supposed to refer to VMX_PROC_CTLS2_VPID first.
1551	*
1552	* See Intel spec. 25.1.2 "Instructions That Cause VM Exits Unconditionally".
1553	* See Intel spec. 30.3 "VMX Instructions".
1554	*/
1555	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64EptVpidCaps : UINT64_MAX;
1556	uint8_t const fVpid = pGuestFeatures->fVmxVpid;
1557
1558	uint8_t const fExecOnly = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EXEC_ONLY);
1559	uint8_t const fPml4 = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1560	uint8_t const fMemTypeUc = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC);
1561	uint8_t const fMemTypeWb = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB);
1562	uint8_t const f2MPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDE_2M);
1563	uint8_t const fInvept = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT);
1564	/** @todo Nested VMX: Support accessed/dirty bits, see @bugref{10092#c25}. */
1565	/* uint8_t const fAccessDirty = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY); */
1566	uint8_t const fEptSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
1567	uint8_t const fEptAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
1568	uint8_t const fVpidIndiv = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1569	uint8_t const fVpidSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
1570	uint8_t const fVpidAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
1571	uint8_t const fVpidSingleGlobal = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
1572	pGuestVmxMsrs->u64EptVpidCaps = RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_EXEC_ONLY, fExecOnly)
1573	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4, fPml4)
1574	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_UC, fMemTypeUc)
1575	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_WB, fMemTypeWb)
1576	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDE_2M, f2MPage)
1577	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDPTE_1G, 0)
1578	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT, fInvept)
1579	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY, 0)
1580	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION, 0)
1581	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK, 0)
1582	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX, fEptSingle)
1583	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX, fEptAll)
1584	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID, fVpid)
1585	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR, fVpid & fVpidIndiv)
1586	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX, fVpid & fVpidSingle)
1587	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX, fVpid & fVpidAll)
1588	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS, fVpid & fVpidSingleGlobal);
1589	}
1590
1591	/* VM Functions. */
1592	if (pGuestFeatures->fVmxVmFunc)
1593	pGuestVmxMsrs->u64VmFunc = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1594	}
1595
1596
1597	/**
1598	* Checks whether the given guest CPU VMX features are compatible with the provided
1599	* base features.
1600	*
1601	* @returns @c true if compatible, @c false otherwise.
1602	* @param pVM The cross context VM structure.
1603	* @param pBase The base VMX CPU features.
1604	* @param pGst The guest VMX CPU features.
1605	*
1606	* @remarks Only VMX feature bits are examined.
1607	*/
1608	static bool cpumR3AreVmxCpuFeaturesCompatible(PVM pVM, PCCPUMFEATURES pBase, PCCPUMFEATURES pGst)
1609	{
1610	if (!cpumR3IsHwAssistNstGstExecAllowed(pVM))
1611	return false;
1612
1613	#define CPUM_VMX_FEAT_SHIFT(a_pFeat, a_FeatName, a_cShift) ((uint64_t)(a_pFeat->a_FeatName) << (a_cShift))
1614	#define CPUM_VMX_MAKE_FEATURES_1(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInsOutInfo , 0) \
1615	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExtIntExit , 1) \
1616	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiExit , 2) \
1617	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtNmi , 3) \
1618	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPreemptTimer , 4) \
1619	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPostedInt , 5) \
1620	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIntWindowExit , 6) \
1621	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTscOffsetting , 7) \
1622	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHltExit , 8) \
1623	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvlpgExit , 9) \
1624	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMwaitExit , 10) \
1625	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdpmcExit , 12) \
1626	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscExit , 13) \
1627	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3LoadExit , 14) \
1628	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3StoreExit , 15) \
1629	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTertiaryExecCtls , 16) \
1630	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8LoadExit , 17) \
1631	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8StoreExit , 18) \
1632	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTprShadow , 19) \
1633	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiWindowExit , 20) \
1634	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMovDRxExit , 21) \
1635	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUncondIoExit , 22) \
1636	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseIoBitmaps , 23) \
1637	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorTrapFlag , 24) \
1638	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseMsrBitmaps , 25) \
1639	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorExit , 26) \
1640	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseExit , 27) \
1641	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSecondaryExecCtls , 28) \
1642	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtApicAccess , 29) \
1643	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEpt , 30) \
1644	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxDescTableExit , 31) \
1645	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscp , 32) \
1646	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtX2ApicMode , 33) \
1647	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVpid , 34) \
1648	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxWbinvdExit , 35) \
1649	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUnrestrictedGuest , 36) \
1650	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxApicRegVirt , 37) \
1651	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtIntDelivery , 38) \
1652	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseLoopExit , 39) \
1653	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdrandExit , 40) \
1654	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvpcid , 41) \
1655	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmFunc , 42) \
1656	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmcsShadowing , 43) \
1657	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdseedExit , 44) \
1658	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPml , 45) \
1659	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEptXcptVe , 46) \
1660	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxConcealVmxFromPt , 47) \
1661	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxXsavesXrstors , 48) \
1662	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxModeBasedExecuteEpt, 49) \
1663	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSppEpt , 50) \
1664	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPtEpt , 51) \
1665	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTscScaling , 52) \
1666	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUserWaitPause , 53) \
1667	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEnclvExit , 54) \
1668	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxLoadIwKeyExit , 55) \
1669	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadDebugCtls , 56) \
1670	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIa32eModeGuest , 57) \
1671	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadEferMsr , 58) \
1672	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadPatMsr , 59) \
1673	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveDebugCtls , 60) \
1674	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHostAddrSpaceSize , 61) \
1675	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitAckExtInt , 62) \
1676	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSavePatMsr , 63))
1677
1678	#define CPUM_VMX_MAKE_FEATURES_2(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadPatMsr , 0) \
1679	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferMsr , 1) \
1680	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadEferMsr , 2) \
1681	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSavePreemptTimer , 3) \
1682	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferLma , 4) \
1683	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPt , 5) \
1684	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmwriteAll , 6) \
1685	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryInjectSoftInt , 7))
1686
1687	/* Check first set of feature bits. */
1688	{
1689	uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_1(pBase);
1690	uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_1(pGst);
1691	if ((fBase \| fGst) != fBase)
1692	{
1693	uint64_t const fDiff = fBase ^ fGst;
1694	LogRel(("CPUM: VMX features (1) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1695	fBase, fGst, fDiff));
1696	return false;
1697	}
1698	}
1699
1700	/* Check second set of feature bits. */
1701	{
1702	uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_2(pBase);
1703	uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_2(pGst);
1704	if ((fBase \| fGst) != fBase)
1705	{
1706	uint64_t const fDiff = fBase ^ fGst;
1707	LogRel(("CPUM: VMX features (2) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1708	fBase, fGst, fDiff));
1709	return false;
1710	}
1711	}
1712	#undef CPUM_VMX_FEAT_SHIFT
1713	#undef CPUM_VMX_MAKE_FEATURES_1
1714	#undef CPUM_VMX_MAKE_FEATURES_2
1715
1716	return true;
1717	}
1718
1719
1720	/**
1721	* Initializes VMX guest features and MSRs.
1722	*
1723	* @param pVM The cross context VM structure.
1724	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1725	* and no hardware-assisted nested-guest execution is
1726	* possible for this VM.
1727	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1728	*/
1729	void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs)
1730	{
1731	Assert(pVM);
1732	Assert(pGuestVmxMsrs);
1733
1734	/*
1735	* While it would be nice to check this earlier while initializing
1736	* fNestedVmxEpt but we would not have enumearted host features then, so do
1737	* it at least now.
1738	*/
1739	/** @todo r=bird: Why don't we just ditch the fNestedVmxEpt and
1740	* fNestedVmxUnrestrictedGuest state members and read the CFGM stuff
1741	* here? Neither of them have any purpose beyond keeping the two value
1742	* read in cpumR3CpuIdReadConfig for use here. They aren't even
1743	* necessarily correct after the feature merging has taken place. */
1744	if (pVM->cpum.s.fNestedVmxEpt)
1745	{
1746	const char *pszWhy = NULL;
1747	if (!VM_IS_HM_ENABLED(pVM) && !VM_IS_EXEC_ENGINE_IEM(pVM))
1748	pszWhy = "execution engine is neither HM nor IEM";
1749	else if (VM_IS_HM_ENABLED(pVM) && !HMIsNestedPagingActive(pVM))
1750	pszWhy = "nested paging is not enabled for the VM or it is not supported by the host";
1751	else if (VM_IS_HM_ENABLED(pVM) && !pVM->cpum.s.HostFeatures.fNoExecute)
1752	pszWhy = "NX is not available on the host";
1753	if (pszWhy)
1754	{
1755	LogRel(("CPUM: Warning! EPT not exposed to the guest because %s.\n", pszWhy));
1756	pVM->cpum.s.fNestedVmxEpt = false;
1757	}
1758	}
1759	if ( pVM->cpum.s.fNestedVmxUnrestrictedGuest
1760	&& !pVM->cpum.s.fNestedVmxEpt)
1761	{
1762	LogRel(("CPUM: Warning! Can't expose \"Unrestricted Guest\" to the guest when EPT is not exposed!\n"));
1763	pVM->cpum.s.fNestedVmxUnrestrictedGuest = false;
1764	}
1765
1766	/*
1767	* Initialize the set of VMX features we emulate.
1768	*
1769	* Note! Some bits might be reported as 1 always if they fall under the
1770	* default1 class bits (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1771	*/
1772	CPUMFEATURES EmuFeat;
1773	RT_ZERO(EmuFeat);
1774	EmuFeat.fVmx = 1;
1775	EmuFeat.fVmxInsOutInfo = 1;
1776	EmuFeat.fVmxExtIntExit = 1;
1777	EmuFeat.fVmxNmiExit = 1;
1778	EmuFeat.fVmxVirtNmi = 1;
1779	EmuFeat.fVmxPreemptTimer = pVM->cpum.s.fNestedVmxPreemptTimer;
1780	EmuFeat.fVmxPostedInt = 0;
1781	EmuFeat.fVmxIntWindowExit = 1;
1782	EmuFeat.fVmxTscOffsetting = 1;
1783	EmuFeat.fVmxHltExit = 1;
1784	EmuFeat.fVmxInvlpgExit = 1;
1785	EmuFeat.fVmxMwaitExit = 1;
1786	EmuFeat.fVmxRdpmcExit = 1;
1787	EmuFeat.fVmxRdtscExit = 1;
1788	EmuFeat.fVmxCr3LoadExit = 1;
1789	EmuFeat.fVmxCr3StoreExit = 1;
1790	EmuFeat.fVmxTertiaryExecCtls = 0;
1791	EmuFeat.fVmxCr8LoadExit = 1;
1792	EmuFeat.fVmxCr8StoreExit = 1;
1793	EmuFeat.fVmxUseTprShadow = 1;
1794	EmuFeat.fVmxNmiWindowExit = 0;
1795	EmuFeat.fVmxMovDRxExit = 1;
1796	EmuFeat.fVmxUncondIoExit = 1;
1797	EmuFeat.fVmxUseIoBitmaps = 1;
1798	EmuFeat.fVmxMonitorTrapFlag = 0;
1799	EmuFeat.fVmxUseMsrBitmaps = 1;
1800	EmuFeat.fVmxMonitorExit = 1;
1801	EmuFeat.fVmxPauseExit = 1;
1802	EmuFeat.fVmxSecondaryExecCtls = 1;
1803	EmuFeat.fVmxVirtApicAccess = 1;
1804	EmuFeat.fVmxEpt = pVM->cpum.s.fNestedVmxEpt;
1805	EmuFeat.fVmxDescTableExit = 1;
1806	EmuFeat.fVmxRdtscp = 1;
1807	EmuFeat.fVmxVirtX2ApicMode = 0;
1808	EmuFeat.fVmxVpid = 0; /** @todo Consider enabling this when EPT works. */
1809	EmuFeat.fVmxWbinvdExit = 1;
1810	EmuFeat.fVmxUnrestrictedGuest = pVM->cpum.s.fNestedVmxUnrestrictedGuest;
1811	EmuFeat.fVmxApicRegVirt = 0;
1812	EmuFeat.fVmxVirtIntDelivery = 0;
1813	EmuFeat.fVmxPauseLoopExit = 0;
1814	EmuFeat.fVmxRdrandExit = 0;
1815	EmuFeat.fVmxInvpcid = 1;
1816	EmuFeat.fVmxVmFunc = 0;
1817	EmuFeat.fVmxVmcsShadowing = 0;
1818	EmuFeat.fVmxRdseedExit = 0;
1819	EmuFeat.fVmxPml = 0;
1820	EmuFeat.fVmxEptXcptVe = 0;
1821	EmuFeat.fVmxConcealVmxFromPt = 0;
1822	EmuFeat.fVmxXsavesXrstors = 0;
1823	EmuFeat.fVmxModeBasedExecuteEpt = 0;
1824	EmuFeat.fVmxSppEpt = 0;
1825	EmuFeat.fVmxPtEpt = 0;
1826	EmuFeat.fVmxUseTscScaling = 0;
1827	EmuFeat.fVmxUserWaitPause = 0;
1828	EmuFeat.fVmxEnclvExit = 0;
1829	EmuFeat.fVmxLoadIwKeyExit = 0;
1830	EmuFeat.fVmxEntryLoadDebugCtls = 1;
1831	EmuFeat.fVmxIa32eModeGuest = 1;
1832	EmuFeat.fVmxEntryLoadEferMsr = 1;
1833	EmuFeat.fVmxEntryLoadPatMsr = 0;
1834	EmuFeat.fVmxExitSaveDebugCtls = 1;
1835	EmuFeat.fVmxHostAddrSpaceSize = 1;
1836	EmuFeat.fVmxExitAckExtInt = 1;
1837	EmuFeat.fVmxExitSavePatMsr = 0;
1838	EmuFeat.fVmxExitLoadPatMsr = 0;
1839	EmuFeat.fVmxExitSaveEferMsr = 1;
1840	EmuFeat.fVmxExitLoadEferMsr = 1;
1841	EmuFeat.fVmxSavePreemptTimer = 0; /* Cannot be enabled if VMX-preemption timer is disabled. */
1842	EmuFeat.fVmxExitSaveEferLma = 1; /* Cannot be disabled if unrestricted guest is enabled. */
1843	EmuFeat.fVmxPt = 0;
1844	EmuFeat.fVmxVmwriteAll = 0; /** @todo NSTVMX: enable this when nested VMCS shadowing is enabled. */
1845	EmuFeat.fVmxEntryInjectSoftInt = 1;
1846
1847	/*
1848	* Merge guest features.
1849	*
1850	* When hardware-assisted VMX may be used, any feature we emulate must also be supported
1851	* by the hardware, hence we merge our emulated features with the host features below.
1852	*/
1853	PCCPUMFEATURES pBaseFeat = cpumR3IsHwAssistNstGstExecAllowed(pVM) ? &pVM->cpum.s.HostFeatures : &EmuFeat;
1854	PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1855	Assert(pBaseFeat->fVmx);
1856	pGuestFeat->fVmxInsOutInfo = (pBaseFeat->fVmxInsOutInfo & EmuFeat.fVmxInsOutInfo );
1857	pGuestFeat->fVmxExtIntExit = (pBaseFeat->fVmxExtIntExit & EmuFeat.fVmxExtIntExit );
1858	pGuestFeat->fVmxNmiExit = (pBaseFeat->fVmxNmiExit & EmuFeat.fVmxNmiExit );
1859	pGuestFeat->fVmxVirtNmi = (pBaseFeat->fVmxVirtNmi & EmuFeat.fVmxVirtNmi );
1860	pGuestFeat->fVmxPreemptTimer = (pBaseFeat->fVmxPreemptTimer & EmuFeat.fVmxPreemptTimer );
1861	pGuestFeat->fVmxPostedInt = (pBaseFeat->fVmxPostedInt & EmuFeat.fVmxPostedInt );
1862	pGuestFeat->fVmxIntWindowExit = (pBaseFeat->fVmxIntWindowExit & EmuFeat.fVmxIntWindowExit );
1863	pGuestFeat->fVmxTscOffsetting = (pBaseFeat->fVmxTscOffsetting & EmuFeat.fVmxTscOffsetting );
1864	pGuestFeat->fVmxHltExit = (pBaseFeat->fVmxHltExit & EmuFeat.fVmxHltExit );
1865	pGuestFeat->fVmxInvlpgExit = (pBaseFeat->fVmxInvlpgExit & EmuFeat.fVmxInvlpgExit );
1866	pGuestFeat->fVmxMwaitExit = (pBaseFeat->fVmxMwaitExit & EmuFeat.fVmxMwaitExit );
1867	pGuestFeat->fVmxRdpmcExit = (pBaseFeat->fVmxRdpmcExit & EmuFeat.fVmxRdpmcExit );
1868	pGuestFeat->fVmxRdtscExit = (pBaseFeat->fVmxRdtscExit & EmuFeat.fVmxRdtscExit );
1869	pGuestFeat->fVmxCr3LoadExit = (pBaseFeat->fVmxCr3LoadExit & EmuFeat.fVmxCr3LoadExit );
1870	pGuestFeat->fVmxCr3StoreExit = (pBaseFeat->fVmxCr3StoreExit & EmuFeat.fVmxCr3StoreExit );
1871	pGuestFeat->fVmxTertiaryExecCtls = (pBaseFeat->fVmxTertiaryExecCtls & EmuFeat.fVmxTertiaryExecCtls );
1872	pGuestFeat->fVmxCr8LoadExit = (pBaseFeat->fVmxCr8LoadExit & EmuFeat.fVmxCr8LoadExit );
1873	pGuestFeat->fVmxCr8StoreExit = (pBaseFeat->fVmxCr8StoreExit & EmuFeat.fVmxCr8StoreExit );
1874	pGuestFeat->fVmxUseTprShadow = (pBaseFeat->fVmxUseTprShadow & EmuFeat.fVmxUseTprShadow );
1875	pGuestFeat->fVmxNmiWindowExit = (pBaseFeat->fVmxNmiWindowExit & EmuFeat.fVmxNmiWindowExit );
1876	pGuestFeat->fVmxMovDRxExit = (pBaseFeat->fVmxMovDRxExit & EmuFeat.fVmxMovDRxExit );
1877	pGuestFeat->fVmxUncondIoExit = (pBaseFeat->fVmxUncondIoExit & EmuFeat.fVmxUncondIoExit );
1878	pGuestFeat->fVmxUseIoBitmaps = (pBaseFeat->fVmxUseIoBitmaps & EmuFeat.fVmxUseIoBitmaps );
1879	pGuestFeat->fVmxMonitorTrapFlag = (pBaseFeat->fVmxMonitorTrapFlag & EmuFeat.fVmxMonitorTrapFlag );
1880	pGuestFeat->fVmxUseMsrBitmaps = (pBaseFeat->fVmxUseMsrBitmaps & EmuFeat.fVmxUseMsrBitmaps );
1881	pGuestFeat->fVmxMonitorExit = (pBaseFeat->fVmxMonitorExit & EmuFeat.fVmxMonitorExit );
1882	pGuestFeat->fVmxPauseExit = (pBaseFeat->fVmxPauseExit & EmuFeat.fVmxPauseExit );
1883	pGuestFeat->fVmxSecondaryExecCtls = (pBaseFeat->fVmxSecondaryExecCtls & EmuFeat.fVmxSecondaryExecCtls );
1884	pGuestFeat->fVmxVirtApicAccess = (pBaseFeat->fVmxVirtApicAccess & EmuFeat.fVmxVirtApicAccess );
1885	pGuestFeat->fVmxEpt = (pBaseFeat->fVmxEpt & EmuFeat.fVmxEpt );
1886	pGuestFeat->fVmxDescTableExit = (pBaseFeat->fVmxDescTableExit & EmuFeat.fVmxDescTableExit );
1887	pGuestFeat->fVmxRdtscp = (pBaseFeat->fVmxRdtscp & EmuFeat.fVmxRdtscp );
1888	pGuestFeat->fVmxVirtX2ApicMode = (pBaseFeat->fVmxVirtX2ApicMode & EmuFeat.fVmxVirtX2ApicMode );
1889	pGuestFeat->fVmxVpid = (pBaseFeat->fVmxVpid & EmuFeat.fVmxVpid );
1890	pGuestFeat->fVmxWbinvdExit = (pBaseFeat->fVmxWbinvdExit & EmuFeat.fVmxWbinvdExit );
1891	pGuestFeat->fVmxUnrestrictedGuest = (pBaseFeat->fVmxUnrestrictedGuest & EmuFeat.fVmxUnrestrictedGuest );
1892	pGuestFeat->fVmxApicRegVirt = (pBaseFeat->fVmxApicRegVirt & EmuFeat.fVmxApicRegVirt );
1893	pGuestFeat->fVmxVirtIntDelivery = (pBaseFeat->fVmxVirtIntDelivery & EmuFeat.fVmxVirtIntDelivery );
1894	pGuestFeat->fVmxPauseLoopExit = (pBaseFeat->fVmxPauseLoopExit & EmuFeat.fVmxPauseLoopExit );
1895	pGuestFeat->fVmxRdrandExit = (pBaseFeat->fVmxRdrandExit & EmuFeat.fVmxRdrandExit );
1896	pGuestFeat->fVmxInvpcid = (pBaseFeat->fVmxInvpcid & EmuFeat.fVmxInvpcid );
1897	pGuestFeat->fVmxVmFunc = (pBaseFeat->fVmxVmFunc & EmuFeat.fVmxVmFunc );
1898	pGuestFeat->fVmxVmcsShadowing = (pBaseFeat->fVmxVmcsShadowing & EmuFeat.fVmxVmcsShadowing );
1899	pGuestFeat->fVmxRdseedExit = (pBaseFeat->fVmxRdseedExit & EmuFeat.fVmxRdseedExit );
1900	pGuestFeat->fVmxPml = (pBaseFeat->fVmxPml & EmuFeat.fVmxPml );
1901	pGuestFeat->fVmxEptXcptVe = (pBaseFeat->fVmxEptXcptVe & EmuFeat.fVmxEptXcptVe );
1902	pGuestFeat->fVmxConcealVmxFromPt = (pBaseFeat->fVmxConcealVmxFromPt & EmuFeat.fVmxConcealVmxFromPt );
1903	pGuestFeat->fVmxXsavesXrstors = (pBaseFeat->fVmxXsavesXrstors & EmuFeat.fVmxXsavesXrstors );
1904	pGuestFeat->fVmxModeBasedExecuteEpt = (pBaseFeat->fVmxModeBasedExecuteEpt & EmuFeat.fVmxModeBasedExecuteEpt );
1905	pGuestFeat->fVmxSppEpt = (pBaseFeat->fVmxSppEpt & EmuFeat.fVmxSppEpt );
1906	pGuestFeat->fVmxPtEpt = (pBaseFeat->fVmxPtEpt & EmuFeat.fVmxPtEpt );
1907	pGuestFeat->fVmxUseTscScaling = (pBaseFeat->fVmxUseTscScaling & EmuFeat.fVmxUseTscScaling );
1908	pGuestFeat->fVmxUserWaitPause = (pBaseFeat->fVmxUserWaitPause & EmuFeat.fVmxUserWaitPause );
1909	pGuestFeat->fVmxEnclvExit = (pBaseFeat->fVmxEnclvExit & EmuFeat.fVmxEnclvExit );
1910	pGuestFeat->fVmxLoadIwKeyExit = (pBaseFeat->fVmxLoadIwKeyExit & EmuFeat.fVmxLoadIwKeyExit );
1911	pGuestFeat->fVmxEntryLoadDebugCtls = (pBaseFeat->fVmxEntryLoadDebugCtls & EmuFeat.fVmxEntryLoadDebugCtls );
1912	pGuestFeat->fVmxIa32eModeGuest = (pBaseFeat->fVmxIa32eModeGuest & EmuFeat.fVmxIa32eModeGuest );
1913	pGuestFeat->fVmxEntryLoadEferMsr = (pBaseFeat->fVmxEntryLoadEferMsr & EmuFeat.fVmxEntryLoadEferMsr );
1914	pGuestFeat->fVmxEntryLoadPatMsr = (pBaseFeat->fVmxEntryLoadPatMsr & EmuFeat.fVmxEntryLoadPatMsr );
1915	pGuestFeat->fVmxExitSaveDebugCtls = (pBaseFeat->fVmxExitSaveDebugCtls & EmuFeat.fVmxExitSaveDebugCtls );
1916	pGuestFeat->fVmxHostAddrSpaceSize = (pBaseFeat->fVmxHostAddrSpaceSize & EmuFeat.fVmxHostAddrSpaceSize );
1917	pGuestFeat->fVmxExitAckExtInt = (pBaseFeat->fVmxExitAckExtInt & EmuFeat.fVmxExitAckExtInt );
1918	pGuestFeat->fVmxExitSavePatMsr = (pBaseFeat->fVmxExitSavePatMsr & EmuFeat.fVmxExitSavePatMsr );
1919	pGuestFeat->fVmxExitLoadPatMsr = (pBaseFeat->fVmxExitLoadPatMsr & EmuFeat.fVmxExitLoadPatMsr );
1920	pGuestFeat->fVmxExitSaveEferMsr = (pBaseFeat->fVmxExitSaveEferMsr & EmuFeat.fVmxExitSaveEferMsr );
1921	pGuestFeat->fVmxExitLoadEferMsr = (pBaseFeat->fVmxExitLoadEferMsr & EmuFeat.fVmxExitLoadEferMsr );
1922	pGuestFeat->fVmxSavePreemptTimer = (pBaseFeat->fVmxSavePreemptTimer & EmuFeat.fVmxSavePreemptTimer );
1923	pGuestFeat->fVmxExitSaveEferLma = (pBaseFeat->fVmxExitSaveEferLma & EmuFeat.fVmxExitSaveEferLma );
1924	pGuestFeat->fVmxPt = (pBaseFeat->fVmxPt & EmuFeat.fVmxPt );
1925	pGuestFeat->fVmxVmwriteAll = (pBaseFeat->fVmxVmwriteAll & EmuFeat.fVmxVmwriteAll );
1926	pGuestFeat->fVmxEntryInjectSoftInt = (pBaseFeat->fVmxEntryInjectSoftInt & EmuFeat.fVmxEntryInjectSoftInt );
1927
1928	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1929	/* Don't expose VMX preemption timer if host is subject to VMX-preemption timer erratum. */
1930	if ( pGuestFeat->fVmxPreemptTimer
1931	&& HMIsSubjectToVmxPreemptTimerErratum())
1932	{
1933	LogRel(("CPUM: Warning! VMX-preemption timer not exposed to guest due to host CPU erratum.\n"));
1934	pGuestFeat->fVmxPreemptTimer = 0;
1935	pGuestFeat->fVmxSavePreemptTimer = 0;
1936	}
1937	#endif
1938
1939	/* Sanity checking. */
1940	if (!pGuestFeat->fVmxSecondaryExecCtls)
1941	{
1942	Assert(!pGuestFeat->fVmxVirtApicAccess);
1943	Assert(!pGuestFeat->fVmxEpt);
1944	Assert(!pGuestFeat->fVmxDescTableExit);
1945	Assert(!pGuestFeat->fVmxRdtscp);
1946	Assert(!pGuestFeat->fVmxVirtX2ApicMode);
1947	Assert(!pGuestFeat->fVmxVpid);
1948	Assert(!pGuestFeat->fVmxWbinvdExit);
1949	Assert(!pGuestFeat->fVmxUnrestrictedGuest);
1950	Assert(!pGuestFeat->fVmxApicRegVirt);
1951	Assert(!pGuestFeat->fVmxVirtIntDelivery);
1952	Assert(!pGuestFeat->fVmxPauseLoopExit);
1953	Assert(!pGuestFeat->fVmxRdrandExit);
1954	Assert(!pGuestFeat->fVmxInvpcid);
1955	Assert(!pGuestFeat->fVmxVmFunc);
1956	Assert(!pGuestFeat->fVmxVmcsShadowing);
1957	Assert(!pGuestFeat->fVmxRdseedExit);
1958	Assert(!pGuestFeat->fVmxPml);
1959	Assert(!pGuestFeat->fVmxEptXcptVe);
1960	Assert(!pGuestFeat->fVmxConcealVmxFromPt);
1961	Assert(!pGuestFeat->fVmxXsavesXrstors);
1962	Assert(!pGuestFeat->fVmxModeBasedExecuteEpt);
1963	Assert(!pGuestFeat->fVmxSppEpt);
1964	Assert(!pGuestFeat->fVmxPtEpt);
1965	Assert(!pGuestFeat->fVmxUseTscScaling);
1966	Assert(!pGuestFeat->fVmxUserWaitPause);
1967	Assert(!pGuestFeat->fVmxEnclvExit);
1968	}
1969	else if (pGuestFeat->fVmxUnrestrictedGuest)
1970	{
1971	/* See footnote in Intel spec. 27.2 "Recording VM-Exit Information And Updating VM-entry Control Fields". */
1972	Assert(pGuestFeat->fVmxExitSaveEferLma);
1973	/* Unrestricted guest execution requires EPT. See Intel spec. 25.2.1.1 "VM-Execution Control Fields". */
1974	Assert(pGuestFeat->fVmxEpt);
1975	}
1976
1977	if (!pGuestFeat->fVmxTertiaryExecCtls)
1978	Assert(!pGuestFeat->fVmxLoadIwKeyExit);
1979
1980	/*
1981	* Finally initialize the VMX guest MSRs.
1982	*/
1983	cpumR3InitVmxGuestMsrs(pVM, pHostVmxMsrs, pGuestFeat, pGuestVmxMsrs);
1984	}
1985
1986
1987	/**
1988	* Gets the host hardware-virtualization MSRs.
1989	*
1990	* @returns VBox status code.
1991	* @param pMsrs Where to store the MSRs.
1992	*/
1993	static int cpumR3GetHostHwvirtMsrs(PCPUMMSRS pMsrs)
1994	{
1995	Assert(pMsrs);
1996
1997	uint32_t fCaps = 0;
1998	int rc = SUPR3QueryVTCaps(&fCaps);
1999	if (RT_SUCCESS(rc))
2000	{
2001	if (fCaps & (SUPVTCAPS_VT_X \| SUPVTCAPS_AMD_V))
2002	{
2003	SUPHWVIRTMSRS HwvirtMsrs;
2004	rc = SUPR3GetHwvirtMsrs(&HwvirtMsrs, false /* fForceRequery */);
2005	if (RT_SUCCESS(rc))
2006	{
2007	if (fCaps & SUPVTCAPS_VT_X)
2008	HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.vmx);
2009	else
2010	HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.svm);
2011	return VINF_SUCCESS;
2012	}
2013
2014	LogRel(("CPUM: Querying hardware-virtualization MSRs failed. rc=%Rrc\n", rc));
2015	return rc;
2016	}
2017
2018	LogRel(("CPUM: Querying hardware-virtualization capability succeeded but did not find VT-x or AMD-V\n"));
2019	return VERR_INTERNAL_ERROR_5;
2020	}
2021	LogRel(("CPUM: No hardware-virtualization capability detected\n"));
2022	return VINF_SUCCESS;
2023	}
2024
2025
2026	/**
2027	* @callback_method_impl{FNTMTIMERINT,
2028	* Callback that fires when the nested VMX-preemption timer expired.}
2029	*/
2030	static DECLCALLBACK(void) cpumR3VmxPreemptTimerCallback(PVM pVM, TMTIMERHANDLE hTimer, void *pvUser)
2031	{
2032	RT_NOREF(pVM, hTimer);
2033	PVMCPU pVCpu = (PVMCPUR3)pvUser;
2034	AssertPtr(pVCpu);
2035	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
2036	}
2037
2038
2039	/**
2040	* Initializes the CPUM.
2041	*
2042	* @returns VBox status code.
2043	* @param pVM The cross context VM structure.
2044	*/
2045	VMMR3DECL(int) CPUMR3Init(PVM pVM)
2046	{
2047	LogFlow(("CPUMR3Init\n"));
2048
2049	/*
2050	* Assert alignment, sizes and tables.
2051	*/
2052	AssertCompileMemberAlignment(VM, cpum.s, 32);
2053	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
2054	AssertCompileSizeAlignment(CPUMCTX, 64);
2055	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
2056	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
2057	AssertCompileMemberAlignment(VM, cpum, 64);
2058	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
2059	#ifdef VBOX_STRICT
2060	int rc2 = cpumR3MsrStrictInitChecks();
2061	AssertRCReturn(rc2, rc2);
2062	#endif
2063
2064	/*
2065	* Gather info about the host CPU.
2066	*/
2067	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2068	if (!ASMHasCpuId())
2069	{
2070	LogRel(("The CPU doesn't support CPUID!\n"));
2071	return VERR_UNSUPPORTED_CPU;
2072	}
2073
2074	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
2075	#endif
2076
2077	CPUMMSRS HostMsrs;
2078	RT_ZERO(HostMsrs);
2079	int rc = cpumR3GetHostHwvirtMsrs(&HostMsrs);
2080	AssertLogRelRCReturn(rc, rc);
2081
2082	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2083	/* Use the host features detected by CPUMR0ModuleInit if available. */
2084	if (pVM->cpum.s.HostFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID)
2085	g_CpumHostFeatures.s = pVM->cpum.s.HostFeatures;
2086	else
2087	{
2088	PCPUMCPUIDLEAF paLeaves;
2089	uint32_t cLeaves;
2090	rc = CPUMCpuIdCollectLeavesX86(&paLeaves, &cLeaves);
2091	AssertLogRelRCReturn(rc, rc);
2092
2093	rc = cpumCpuIdExplodeFeaturesX86(paLeaves, cLeaves, &HostMsrs, &g_CpumHostFeatures.s);
2094	RTMemFree(paLeaves);
2095	AssertLogRelRCReturn(rc, rc);
2096	}
2097	pVM->cpum.s.HostFeatures = g_CpumHostFeatures.s;
2098	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
2099	#endif
2100
2101	/*
2102	* Check that the CPU supports the minimum features we require.
2103	*/
2104	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
2105	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
2106	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
2107	if (!pVM->cpum.s.HostFeatures.fMmx)
2108	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
2109	if (!pVM->cpum.s.HostFeatures.fTsc)
2110	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
2111	#endif
2112
2113	/*
2114	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
2115	*/
2116	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
2117	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
2118
2119	/*
2120	* Figure out which XSAVE/XRSTOR features are available on the host.
2121	*/
2122	uint64_t fXcr0Host = 0;
2123	uint64_t fXStateHostMask = 0;
2124	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2125	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
2126	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
2127	{
2128	fXStateHostMask = fXcr0Host = ASMGetXcr0();
2129	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
2130	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2131	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
2132	}
2133	#endif
2134	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
2135	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
2136	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
2137
2138	/*
2139	* Initialize the host XSAVE/XRSTOR mask.
2140	*/
2141	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2142	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
2143	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
2144	AssertLogRelReturn( pVM->cpum.s.HostFeatures.cbMaxExtendedState >= sizeof(X86FXSTATE)
2145	&& pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Host.XState)
2146	&& pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Guest.XState)
2147	, VERR_CPUM_IPE_2);
2148	#endif
2149
2150	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2151	{
2152	PVMCPU pVCpu = pVM->apCpusR3[i];
2153
2154	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
2155	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2156	}
2157
2158	/*
2159	* Register saved state data item.
2160	*/
2161	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
2162	NULL, cpumR3LiveExec, NULL,
2163	NULL, cpumR3SaveExec, NULL,
2164	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
2165	if (RT_FAILURE(rc))
2166	return rc;
2167
2168	/*
2169	* Register info handlers and registers with the debugger facility.
2170	*/
2171	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
2172	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
2173	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
2174	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
2175	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
2176	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
2177	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
2178	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
2179	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
2180	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
2181	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
2182	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
2183	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.",
2184	&cpumR3CpuIdInfo);
2185	DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
2186	&cpumR3InfoVmxFeatures);
2187
2188	rc = cpumR3DbgInit(pVM);
2189	if (RT_FAILURE(rc))
2190	return rc;
2191
2192	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2193	/*
2194	* Check if we need to workaround partial/leaky FPU handling.
2195	*/
2196	cpumR3CheckLeakyFpu(pVM);
2197	#endif
2198
2199	/*
2200	* Initialize the Guest CPUID and MSR states.
2201	*/
2202	rc = cpumR3InitCpuIdAndMsrs(pVM, &HostMsrs);
2203	if (RT_FAILURE(rc))
2204	return rc;
2205
2206	/*
2207	* Init the VMX/SVM state.
2208	*
2209	* This must be done after initializing CPUID/MSR features as we access the
2210	* the VMX/SVM guest features below.
2211	*
2212	* In the case of nested VT-x, we also need to create the per-VCPU
2213	* VMX preemption timers.
2214	*/
2215	if (pVM->cpum.s.GuestFeatures.fVmx)
2216	cpumR3InitVmxHwVirtState(pVM);
2217	else if (pVM->cpum.s.GuestFeatures.fSvm)
2218	cpumR3InitSvmHwVirtState(pVM);
2219	else
2220	Assert(pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
2221
2222	CPUMR3Reset(pVM);
2223	return VINF_SUCCESS;
2224	}
2225
2226
2227	/**
2228	* Applies relocations to data and code managed by this
2229	* component. This function will be called at init and
2230	* whenever the VMM need to relocate it self inside the GC.
2231	*
2232	* The CPUM will update the addresses used by the switcher.
2233	*
2234	* @param pVM The cross context VM structure.
2235	*/
2236	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
2237	{
2238	RT_NOREF(pVM);
2239	}
2240
2241
2242	/**
2243	* Terminates the CPUM.
2244	*
2245	* Termination means cleaning up and freeing all resources,
2246	* the VM it self is at this point powered off or suspended.
2247	*
2248	* @returns VBox status code.
2249	* @param pVM The cross context VM structure.
2250	*/
2251	VMMR3DECL(int) CPUMR3Term(PVM pVM)
2252	{
2253	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2254	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2255	{
2256	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2257	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
2258	pVCpu->cpum.s.uMagic = 0;
2259	pvCpu->cpum.s.Guest.dr[5] = 0;
2260	}
2261	#endif
2262
2263	if (pVM->cpum.s.GuestFeatures.fVmx)
2264	{
2265	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2266	{
2267	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2268	if (pVCpu->cpum.s.hNestedVmxPreemptTimer != NIL_TMTIMERHANDLE)
2269	{
2270	int rc = TMR3TimerDestroy(pVM, pVCpu->cpum.s.hNestedVmxPreemptTimer); AssertRC(rc);
2271	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2272	}
2273	}
2274	}
2275	return VINF_SUCCESS;
2276	}
2277
2278
2279	/**
2280	* Resets a virtual CPU.
2281	*
2282	* Used by CPUMR3Reset and CPU hot plugging.
2283	*
2284	* @param pVM The cross context VM structure.
2285	* @param pVCpu The cross context virtual CPU structure of the CPU that is
2286	* being reset. This may differ from the current EMT.
2287	*/
2288	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2289	{
2290	/** @todo anything different for VCPU > 0? */
2291	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2292
2293	/*
2294	* Initialize everything to ZERO first.
2295	*/
2296	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
2297
2298	RT_BZERO(pCtx, RT_UOFFSETOF(CPUMCTX, aoffXState));
2299
2300	pVCpu->cpum.s.fUseFlags = fUseFlags;
2301
2302	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
2303	pCtx->eip = 0x0000fff0;
2304	pCtx->edx = 0x00000600; /* P6 processor */
2305	pCtx->eflags.Bits.u1Reserved0 = 1;
2306
2307	pCtx->cs.Sel = 0xf000;
2308	pCtx->cs.ValidSel = 0xf000;
2309	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2310	pCtx->cs.u64Base = UINT64_C(0xffff0000);
2311	pCtx->cs.u32Limit = 0x0000ffff;
2312	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
2313	pCtx->cs.Attr.n.u1Present = 1;
2314	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
2315
2316	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
2317	pCtx->ds.u32Limit = 0x0000ffff;
2318	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
2319	pCtx->ds.Attr.n.u1Present = 1;
2320	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2321
2322	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
2323	pCtx->es.u32Limit = 0x0000ffff;
2324	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
2325	pCtx->es.Attr.n.u1Present = 1;
2326	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2327
2328	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
2329	pCtx->fs.u32Limit = 0x0000ffff;
2330	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
2331	pCtx->fs.Attr.n.u1Present = 1;
2332	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2333
2334	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
2335	pCtx->gs.u32Limit = 0x0000ffff;
2336	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
2337	pCtx->gs.Attr.n.u1Present = 1;
2338	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2339
2340	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2341	pCtx->ss.u32Limit = 0x0000ffff;
2342	pCtx->ss.Attr.n.u1Present = 1;
2343	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
2344	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2345
2346	pCtx->idtr.cbIdt = 0xffff;
2347	pCtx->gdtr.cbGdt = 0xffff;
2348
2349	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2350	pCtx->ldtr.u32Limit = 0xffff;
2351	pCtx->ldtr.Attr.n.u1Present = 1;
2352	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
2353
2354	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2355	pCtx->tr.u32Limit = 0xffff;
2356	pCtx->tr.Attr.n.u1Present = 1;
2357	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
2358
2359	pCtx->dr[6] = X86_DR6_INIT_VAL;
2360	pCtx->dr[7] = X86_DR7_INIT_VAL;
2361
2362	PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
2363	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
2364	pFpuCtx->FCW = 0x37f;
2365
2366	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
2367	IA-32 Processor States Following Power-up, Reset, or INIT */
2368	pFpuCtx->MXCSR = 0x1F80;
2369	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
2370
2371	pCtx->aXcr[0] = XSAVE_C_X87;
2372	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
2373	{
2374	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
2375	as we don't know what happened before. (Bother optimize later?) */
2376	pCtx->XState.Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
2377	}
2378
2379	/*
2380	* MSRs.
2381	*/
2382	/* Init PAT MSR */
2383	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
2384
2385	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
2386	* The Intel docs don't mention it. */
2387	Assert(!pCtx->msrEFER);
2388
2389	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
2390	is supposed to be here, just trying provide useful/sensible values. */
2391	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
2392	if (pRange)
2393	{
2394	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2395	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
2396	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
2397	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
2398	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2399	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
2400	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
2401	}
2402
2403	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
2404
2405	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
2406	* called from each EMT while we're getting called by CPUMR3Reset()
2407	* iteratively on the same thread. Fix later. */
2408	#if 0 /** @todo r=bird: This we will do in TM, not here. */
2409	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
2410	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
2411	#endif
2412
2413
2414	/* C-state control. Guesses. */
2415	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
2416	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
2417	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
2418	* functionality. The default value must be different due to incompatible write mask.
2419	*/
2420	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
2421	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
2422	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
2423	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
2424
2425	/*
2426	* Hardware virtualization state.
2427	*/
2428	CPUMSetGuestGif(pCtx, true);
2429	Assert(!pVM->cpum.s.GuestFeatures.fVmx \|\| !pVM->cpum.s.GuestFeatures.fSvm); /* Paranoia. */
2430	if (pVM->cpum.s.GuestFeatures.fVmx)
2431	cpumR3ResetVmxHwVirtState(pVCpu);
2432	else if (pVM->cpum.s.GuestFeatures.fSvm)
2433	cpumR3ResetSvmHwVirtState(pVCpu);
2434	}
2435
2436
2437	/**
2438	* Resets the CPU.
2439	*
2440	* @returns VINF_SUCCESS.
2441	* @param pVM The cross context VM structure.
2442	*/
2443	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
2444	{
2445	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2446	{
2447	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2448	CPUMR3ResetCpu(pVM, pVCpu);
2449
2450	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2451
2452	/* Magic marker for searching in crash dumps. */
2453	strcpy((char *)pVCpu->.cpum.s.aMagic, "CPUMCPU Magic");
2454	pVCpu->cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2455	pVCpu->cpum.s.Guest->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2456	#endif
2457	}
2458	}
2459
2460
2461
2462
2463	/**
2464	* Pass 0 live exec callback.
2465	*
2466	* @returns VINF_SSM_DONT_CALL_AGAIN.
2467	* @param pVM The cross context VM structure.
2468	* @param pSSM The saved state handle.
2469	* @param uPass The pass (0).
2470	*/
2471	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2472	{
2473	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2474	cpumR3SaveCpuId(pVM, pSSM);
2475	return VINF_SSM_DONT_CALL_AGAIN;
2476	}
2477
2478
2479	/**
2480	* Execute state save operation.
2481	*
2482	* @returns VBox status code.
2483	* @param pVM The cross context VM structure.
2484	* @param pSSM SSM operation handle.
2485	*/
2486	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2487	{
2488	/*
2489	* Save.
2490	*/
2491	SSMR3PutU32(pSSM, pVM->cCpus);
2492	SSMR3PutU32(pSSM, sizeof(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr));
2493	CPUMCTX DummyHyperCtx;
2494	RT_ZERO(DummyHyperCtx);
2495	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2496	{
2497	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2498
2499	SSMR3PutStructEx(pSSM, &DummyHyperCtx, sizeof(DummyHyperCtx), 0, g_aCpumCtxFields, NULL);
2500
2501	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2502	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2503	SSMR3PutStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2504	if (pGstCtx->fXStateMask != 0)
2505	SSMR3PutStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr), 0, g_aCpumXSaveHdrFields, NULL);
2506	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2507	{
2508	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2509	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2510	}
2511	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2512	{
2513	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2514	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2515	}
2516	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2517	{
2518	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2519	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2520	}
2521	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2522	{
2523	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2524	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2525	}
2526	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2527	{
2528	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2529	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2530	}
2531	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[0].u);
2532	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[1].u);
2533	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[2].u);
2534	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[3].u);
2535	if (pVM->cpum.s.GuestFeatures.fSvm)
2536	{
2537	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2538	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2539	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2540	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2541	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2542	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2543	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2544	g_aSvmHwvirtHostState, NULL /* pvUser */);
2545	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2546	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2547	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2548	/* This is saved in the old VMCPUM_FF format. Change if more flags are added. */
2549	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fSavedInhibit & CPUMCTX_INHIBIT_NMI ? CPUM_OLD_VMCPU_FF_BLOCK_NMIS : 0);
2550	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2551	}
2552	if (pVM->cpum.s.GuestFeatures.fVmx)
2553	{
2554	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmxon);
2555	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmcs);
2556	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2557	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxRootMode);
2558	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2559	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInterceptEvents);
2560	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2561	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs), 0, g_aVmxHwvirtVmcs, NULL);
2562	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2563	0, g_aVmxHwvirtVmcs, NULL);
2564	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2565	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2566	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2567	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2568	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2569	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2570	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2571	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2572	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uPrevPauseTick);
2573	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uEntryTick);
2574	SSMR3PutU16(pSSM, pGstCtx->hwvirt.vmx.offVirtApicWrite);
2575	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2576	SSMR3PutU64(pSSM, MSR_IA32_FEATURE_CONTROL_LOCK \| MSR_IA32_FEATURE_CONTROL_VMXON); /* Deprecated since 2021/09/22. Value kept backwards compatibile with 6.1.26. */
2577	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2578	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2579	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2580	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2581	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2582	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2583	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2584	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2585	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2586	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2587	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2588	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2589	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2590	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2591	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2592	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2593	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2594	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2595	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2596	}
2597	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2598	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2599	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2600	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2601	}
2602
2603	cpumR3SaveCpuId(pVM, pSSM);
2604	return VINF_SUCCESS;
2605	}
2606
2607
2608	/**
2609	* @callback_method_impl{FNSSMINTLOADPREP}
2610	*/
2611	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2612	{
2613	NOREF(pSSM);
2614	pVM->cpum.s.fPendingRestore = true;
2615	return VINF_SUCCESS;
2616	}
2617
2618
2619	/**
2620	* @callback_method_impl{FNSSMINTLOADEXEC}
2621	*/
2622	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2623	{
2624	int rc; /* Only for AssertRCReturn use. */
2625
2626	/*
2627	* Validate version.
2628	*/
2629	if ( uVersion != CPUM_SAVED_STATE_VERSION_PAE_PDPES
2630	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2
2631	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX
2632	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2633	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2634	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2635	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2636	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2637	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
2638	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2639	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2640	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2641	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2642	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2643	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2644	{
2645	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2646	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2647	}
2648
2649	if (uPass == SSM_PASS_FINAL)
2650	{
2651	/*
2652	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2653	* really old SSM file versions.)
2654	*/
2655	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2656	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2657	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2658	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR));
2659
2660	/*
2661	* Figure x86 and ctx field definitions to use for older states.
2662	*/
2663	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2664	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2665	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2666	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2667	{
2668	paCpumCtx1Fields = g_aCpumX87FieldsV16;
2669	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2670	}
2671	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2672	{
2673	paCpumCtx1Fields = g_aCpumX87FieldsMem;
2674	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2675	}
2676
2677	/*
2678	* The hyper state used to preceed the CPU count. Starting with
2679	* XSAVE it was moved down till after we've got the count.
2680	*/
2681	CPUMCTX HyperCtxIgnored;
2682	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2683	{
2684	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2685	{
2686	X86FXSTATE Ign;
2687	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2688	SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored),
2689	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2690	}
2691	}
2692
2693	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2694	{
2695	uint32_t cCpus;
2696	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2697	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2698	VERR_SSM_UNEXPECTED_DATA);
2699	}
2700	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2701	\|\| pVM->cCpus == 1,
2702	("cCpus=%u\n", pVM->cCpus),
2703	VERR_SSM_UNEXPECTED_DATA);
2704
2705	uint32_t cbMsrs = 0;
2706	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2707	{
2708	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2709	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2710	VERR_SSM_UNEXPECTED_DATA);
2711	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2712	VERR_SSM_UNEXPECTED_DATA);
2713	}
2714
2715	/*
2716	* Do the per-CPU restoring.
2717	*/
2718	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2719	{
2720	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2721	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2722
2723	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2724	{
2725	/*
2726	* The XSAVE saved state layout moved the hyper state down here.
2727	*/
2728	rc = SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored), 0, g_aCpumCtxFields, NULL);
2729	AssertRCReturn(rc, rc);
2730
2731	/*
2732	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2733	*/
2734	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2735	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2736	AssertRCReturn(rc, rc);
2737
2738	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2739	if (pGstCtx->fXStateMask != 0)
2740	{
2741	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2742	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2743	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2744	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2745	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2746	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2747	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2748	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2749	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2750	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2751	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2752	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2753	}
2754
2755	/* Check that the XCR0 mask is valid (invalid results in #GP). */
2756	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2757	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2758	{
2759	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
2760	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2761	VERR_CPUM_INVALID_XCR0);
2762	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2763	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2764	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2765	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2766	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2767	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2768	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2769	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2770	}
2771
2772	/* Check that the XCR1 is zero, as we don't implement it yet. */
2773	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2774
2775	/*
2776	* Restore the individual extended state components we support.
2777	*/
2778	if (pGstCtx->fXStateMask != 0)
2779	{
2780	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr),
2781	0, g_aCpumXSaveHdrFields, NULL);
2782	AssertRCReturn(rc, rc);
2783	AssertLogRelMsgReturn(!(pGstCtx->XState.Hdr.bmXState & ~pGstCtx->fXStateMask),
2784	("bmXState=%#RX64 fXStateMask=%#RX64\n",
2785	pGstCtx->XState.Hdr.bmXState, pGstCtx->fXStateMask),
2786	VERR_CPUM_INVALID_XSAVE_HDR);
2787	}
2788	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2789	{
2790	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2791	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2792	}
2793	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2794	{
2795	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2796	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2797	}
2798	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2799	{
2800	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2801	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2802	}
2803	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2804	{
2805	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2806	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2807	}
2808	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2809	{
2810	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2811	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2812	}
2813	if (uVersion >= CPUM_SAVED_STATE_VERSION_PAE_PDPES)
2814	{
2815	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[0].u);
2816	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[1].u);
2817	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[2].u);
2818	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[3].u);
2819	}
2820	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2821	{
2822	if (pVM->cpum.s.GuestFeatures.fSvm)
2823	{
2824	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2825	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2826	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2827	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2828	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2829	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2830	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2831	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
2832	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2833	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2834	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2835
2836	uint32_t fSavedLocalFFs = 0;
2837	rc = SSMR3GetU32(pSSM, &fSavedLocalFFs);
2838	AssertRCReturn(rc, rc);
2839	Assert(fSavedLocalFFs == 0 \|\| fSavedLocalFFs == CPUM_OLD_VMCPU_FF_BLOCK_NMIS);
2840	pGstCtx->hwvirt.fSavedInhibit = fSavedLocalFFs & CPUM_OLD_VMCPU_FF_BLOCK_NMIS ? CPUMCTX_INHIBIT_NMI : 0;
2841
2842	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2843	}
2844	}
2845	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX)
2846	{
2847	if (pVM->cpum.s.GuestFeatures.fVmx)
2848	{
2849	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmxon);
2850	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmcs);
2851	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2852	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxRootMode);
2853	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2854	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInterceptEvents);
2855	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2856	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs),
2857	0, g_aVmxHwvirtVmcs, NULL);
2858	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2859	0, g_aVmxHwvirtVmcs, NULL);
2860	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2861	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2862	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2863	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2864	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2865	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2866	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2867	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2868	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uPrevPauseTick);
2869	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uEntryTick);
2870	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.vmx.offVirtApicWrite);
2871	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2872	SSMR3Skip(pSSM, sizeof(uint64_t)); /* Unused - used to be IA32_FEATURE_CONTROL, see @bugref{10106}. */
2873	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2874	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2875	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2876	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2877	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2878	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2879	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2880	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2881	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2882	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2883	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2884	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2885	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2886	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2887	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2888	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2889	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2890	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2891	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2)
2892	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2893	}
2894	}
2895	}
2896	else
2897	{
2898	/*
2899	* Pre XSAVE saved state.
2900	*/
2901	SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87),
2902	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2903	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2904	}
2905
2906	/*
2907	* Restore a couple of flags and the MSRs.
2908	*/
2909	uint32_t fIgnoredUsedFlags = 0;
2910	rc = SSMR3GetU32(pSSM, &fIgnoredUsedFlags); /* we're recalc the two relevant flags after loading state. */
2911	AssertRCReturn(rc, rc);
2912	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2913
2914	rc = VINF_SUCCESS;
2915	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2916	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2917	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2918	{
2919	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2920	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2921	}
2922	AssertRCReturn(rc, rc);
2923
2924	/* REM and other may have cleared must-be-one fields in DR6 and
2925	DR7, fix these. */
2926	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
2927	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
2928	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
2929	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
2930	}
2931
2932	/* Older states does not have the internal selector register flags
2933	and valid selector value. Supply those. */
2934	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2935	{
2936	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2937	{
2938	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2939	bool const fValid = true /!VM_IS_RAW_MODE_ENABLED(pVM)/
2940	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2941	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2942	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2943	if (fValid)
2944	{
2945	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2946	{
2947	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2948	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2949	}
2950
2951	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2952	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2953	}
2954	else
2955	{
2956	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2957	{
2958	paSelReg[iSelReg].fFlags = 0;
2959	paSelReg[iSelReg].ValidSel = 0;
2960	}
2961
2962	/* This might not be 104% correct, but I think it's close
2963	enough for all practical purposes... (REM always loaded
2964	LDTR registers.) */
2965	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2966	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2967	}
2968	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2969	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2970	}
2971	}
2972
2973	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2974	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2975	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2976	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2977	{
2978	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2979	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2980	}
2981
2982	/*
2983	* A quick sanity check.
2984	*/
2985	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2986	{
2987	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2988	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2989	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2990	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2991	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2992	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2993	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2994	}
2995	}
2996
2997	pVM->cpum.s.fPendingRestore = false;
2998
2999	/*
3000	* Guest CPUIDs (and VMX MSR features).
3001	*/
3002	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
3003	{
3004	CPUMMSRS GuestMsrs;
3005	RT_ZERO(GuestMsrs);
3006
3007	CPUMFEATURES BaseFeatures;
3008	bool const fVmxGstFeat = pVM->cpum.s.GuestFeatures.fVmx;
3009	if (fVmxGstFeat)
3010	{
3011	/*
3012	* At this point the MSRs in the guest CPU-context are loaded with the guest VMX MSRs from the saved state.
3013	* However the VMX sub-features have not been exploded yet. So cache the base (host derived) VMX features
3014	* here so we can compare them for compatibility after exploding guest features.
3015	*/
3016	BaseFeatures = pVM->cpum.s.GuestFeatures;
3017
3018	/* Use the VMX MSR features from the saved state while exploding guest features. */
3019	GuestMsrs.hwvirt.vmx = pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.vmx.Msrs;
3020	}
3021
3022	/* Load CPUID and explode guest features. */
3023	rc = cpumR3LoadCpuId(pVM, pSSM, uVersion, &GuestMsrs);
3024	if (fVmxGstFeat)
3025	{
3026	/*
3027	* Check if the exploded VMX features from the saved state are compatible with the host-derived features
3028	* we cached earlier (above). The is required if we use hardware-assisted nested-guest execution with
3029	* VMX features presented to the guest.
3030	*/
3031	bool const fIsCompat = cpumR3AreVmxCpuFeaturesCompatible(pVM, &BaseFeatures, &pVM->cpum.s.GuestFeatures);
3032	if (!fIsCompat)
3033	return VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO;
3034	}
3035	return rc;
3036	}
3037	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
3038	}
3039
3040
3041	/**
3042	* @callback_method_impl{FNSSMINTLOADDONE}
3043	*/
3044	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
3045	{
3046	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
3047	return VINF_SUCCESS;
3048
3049	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
3050	if (pVM->cpum.s.fPendingRestore)
3051	{
3052	LogRel(("CPUM: Missing state!\n"));
3053	return VERR_INTERNAL_ERROR_2;
3054	}
3055
3056	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
3057	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3058	{
3059	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3060
3061	/* Notify PGM of the NXE states in case they've changed. */
3062	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
3063
3064	/* During init. this is done in CPUMR3InitCompleted(). */
3065	if (fSupportsLongMode)
3066	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
3067
3068	/* Recalc the CPUM_USE_DEBUG_REGS_HYPER value. */
3069	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX);
3070	}
3071	return VINF_SUCCESS;
3072	}
3073
3074
3075	/**
3076	* Checks if the CPUM state restore is still pending.
3077	*
3078	* @returns true / false.
3079	* @param pVM The cross context VM structure.
3080	*/
3081	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
3082	{
3083	return pVM->cpum.s.fPendingRestore;
3084	}
3085
3086
3087	/**
3088	* Formats the EFLAGS value into mnemonics.
3089	*
3090	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
3091	* @param efl The EFLAGS value.
3092	*/
3093	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
3094	{
3095	/*
3096	* Format the flags.
3097	*/
3098	static const struct
3099	{
3100	const char pszSet; const char pszClear; uint32_t fFlag;
3101	} s_aFlags[] =
3102	{
3103	{ "vip",NULL, X86_EFL_VIP },
3104	{ "vif",NULL, X86_EFL_VIF },
3105	{ "ac", NULL, X86_EFL_AC },
3106	{ "vm", NULL, X86_EFL_VM },
3107	{ "rf", NULL, X86_EFL_RF },
3108	{ "nt", NULL, X86_EFL_NT },
3109	{ "ov", "nv", X86_EFL_OF },
3110	{ "dn", "up", X86_EFL_DF },
3111	{ "ei", "di", X86_EFL_IF },
3112	{ "tf", NULL, X86_EFL_TF },
3113	{ "nt", "pl", X86_EFL_SF },
3114	{ "nz", "zr", X86_EFL_ZF },
3115	{ "ac", "na", X86_EFL_AF },
3116	{ "po", "pe", X86_EFL_PF },
3117	{ "cy", "nc", X86_EFL_CF },
3118	};
3119	char *psz = pszEFlags;
3120	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
3121	{
3122	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
3123	if (pszAdd)
3124	{
3125	strcpy(psz, pszAdd);
3126	psz += strlen(pszAdd);
3127	*psz++ = ' ';
3128	}
3129	}
3130	psz[-1] = '\0';
3131	}
3132
3133
3134	/**
3135	* Formats a full register dump.
3136	*
3137	* @param pVM The cross context VM structure.
3138	* @param pCtx The context to format.
3139	* @param pCtxCore The context core to format.
3140	* @param pHlp Output functions.
3141	* @param enmType The dump type.
3142	* @param pszPrefix Register name prefix.
3143	*/
3144	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
3145	const char *pszPrefix)
3146	{
3147	NOREF(pVM);
3148
3149	/*
3150	* Format the EFLAGS.
3151	*/
3152	uint32_t efl = pCtxCore->eflags.u32;
3153	char szEFlags[80];
3154	cpumR3InfoFormatFlags(&szEFlags[0], efl);
3155
3156	/*
3157	* Format the registers.
3158	*/
3159	switch (enmType)
3160	{
3161	case CPUMDUMPTYPE_TERSE:
3162	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3163	pHlp->pfnPrintf(pHlp,
3164	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3165	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3166	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3167	"%sr14=%016RX64 %sr15=%016RX64\n"
3168	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3169	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3170	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3171	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3172	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3173	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3174	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3175	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3176	else
3177	pHlp->pfnPrintf(pHlp,
3178	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3179	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3180	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3181	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3182	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3183	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3184	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3185	break;
3186
3187	case CPUMDUMPTYPE_DEFAULT:
3188	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3189	pHlp->pfnPrintf(pHlp,
3190	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3191	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3192	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3193	"%sr14=%016RX64 %sr15=%016RX64\n"
3194	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3195	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3196	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
3197	,
3198	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3199	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3200	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3201	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3202	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3203	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3204	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3205	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3206	else
3207	pHlp->pfnPrintf(pHlp,
3208	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3209	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3210	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3211	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
3212	,
3213	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3214	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3215	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3216	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3217	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3218	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3219	break;
3220
3221	case CPUMDUMPTYPE_VERBOSE:
3222	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3223	pHlp->pfnPrintf(pHlp,
3224	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3225	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3226	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3227	"%sr14=%016RX64 %sr15=%016RX64\n"
3228	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3229	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3230	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3231	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3232	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3233	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3234	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3235	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
3236	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
3237	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
3238	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3239	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3240	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3241	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
3242	,
3243	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3244	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3245	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3246	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3247	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
3248	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
3249	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
3250	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
3251	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
3252	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
3253	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3254	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3255	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3256	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3257	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3258	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3259	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3260	else
3261	pHlp->pfnPrintf(pHlp,
3262	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3263	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3264	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3265	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3266	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3267	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3268	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3269	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3270	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3271	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3272	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3273	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3274	,
3275	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3276	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3277	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3278	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3279	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3280	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3281	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3282	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3283	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3284	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3285	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3286	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3287
3288	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
3289	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
3290	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
3291	{
3292	PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
3293	pHlp->pfnPrintf(pHlp,
3294	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3295	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3296	,
3297	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
3298	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
3299	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
3300	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
3301	);
3302	/*
3303	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
3304	* not (FP)R0-7 as Intel SDM suggests.
3305	*/
3306	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
3307	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
3308	{
3309	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
3310	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
3311	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
3312	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
3313	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
3314	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
3315	iExponent -= 16383; /* subtract bias */
3316	/** @todo This isn't entirenly correct and needs more work! */
3317	pHlp->pfnPrintf(pHlp,
3318	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
3319	pszPrefix, iST, pszPrefix, iFPR,
3320	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
3321	uTag, chSign, iInteger, u64Fraction, iExponent);
3322	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
3323	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3324	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
3325	else
3326	pHlp->pfnPrintf(pHlp, "\n");
3327	}
3328
3329	/* XMM/YMM/ZMM registers. */
3330	if (pCtx->fXStateMask & XSAVE_C_YMM)
3331	{
3332	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
3333	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
3334	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3335	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3336	pszPrefix, i, i < 10 ? " " : "",
3337	pYmmHiCtx->aYmmHi[i].au32[3],
3338	pYmmHiCtx->aYmmHi[i].au32[2],
3339	pYmmHiCtx->aYmmHi[i].au32[1],
3340	pYmmHiCtx->aYmmHi[i].au32[0],
3341	pFpuCtx->aXMM[i].au32[3],
3342	pFpuCtx->aXMM[i].au32[2],
3343	pFpuCtx->aXMM[i].au32[1],
3344	pFpuCtx->aXMM[i].au32[0]);
3345	else
3346	{
3347	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
3348	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3349	pHlp->pfnPrintf(pHlp,
3350	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3351	pszPrefix, i, i < 10 ? " " : "",
3352	pZmmHi256->aHi256Regs[i].au32[7],
3353	pZmmHi256->aHi256Regs[i].au32[6],
3354	pZmmHi256->aHi256Regs[i].au32[5],
3355	pZmmHi256->aHi256Regs[i].au32[4],
3356	pZmmHi256->aHi256Regs[i].au32[3],
3357	pZmmHi256->aHi256Regs[i].au32[2],
3358	pZmmHi256->aHi256Regs[i].au32[1],
3359	pZmmHi256->aHi256Regs[i].au32[0],
3360	pYmmHiCtx->aYmmHi[i].au32[3],
3361	pYmmHiCtx->aYmmHi[i].au32[2],
3362	pYmmHiCtx->aYmmHi[i].au32[1],
3363	pYmmHiCtx->aYmmHi[i].au32[0],
3364	pFpuCtx->aXMM[i].au32[3],
3365	pFpuCtx->aXMM[i].au32[2],
3366	pFpuCtx->aXMM[i].au32[1],
3367	pFpuCtx->aXMM[i].au32[0]);
3368
3369	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
3370	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
3371	pHlp->pfnPrintf(pHlp,
3372	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3373	pszPrefix, i + 16,
3374	pZmm16Hi->aRegs[i].au32[15],
3375	pZmm16Hi->aRegs[i].au32[14],
3376	pZmm16Hi->aRegs[i].au32[13],
3377	pZmm16Hi->aRegs[i].au32[12],
3378	pZmm16Hi->aRegs[i].au32[11],
3379	pZmm16Hi->aRegs[i].au32[10],
3380	pZmm16Hi->aRegs[i].au32[9],
3381	pZmm16Hi->aRegs[i].au32[8],
3382	pZmm16Hi->aRegs[i].au32[7],
3383	pZmm16Hi->aRegs[i].au32[6],
3384	pZmm16Hi->aRegs[i].au32[5],
3385	pZmm16Hi->aRegs[i].au32[4],
3386	pZmm16Hi->aRegs[i].au32[3],
3387	pZmm16Hi->aRegs[i].au32[2],
3388	pZmm16Hi->aRegs[i].au32[1],
3389	pZmm16Hi->aRegs[i].au32[0]);
3390	}
3391	}
3392	else
3393	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3394	pHlp->pfnPrintf(pHlp,
3395	i & 1
3396	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3397	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3398	pszPrefix, i, i < 10 ? " " : "",
3399	pFpuCtx->aXMM[i].au32[3],
3400	pFpuCtx->aXMM[i].au32[2],
3401	pFpuCtx->aXMM[i].au32[1],
3402	pFpuCtx->aXMM[i].au32[0]);
3403
3404	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
3405	{
3406	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
3407	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
3408	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
3409	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
3410	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
3411	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
3412	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
3413	}
3414
3415	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
3416	{
3417	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
3418	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
3419	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
3420	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
3421	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
3422	}
3423
3424	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
3425	{
3426	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
3427	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
3428	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
3429	}
3430
3431	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
3432	if (pFpuCtx->au32RsrvdRest[i])
3433	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
3434	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
3435	}
3436
3437	pHlp->pfnPrintf(pHlp,
3438	"%sEFER =%016RX64\n"
3439	"%sPAT =%016RX64\n"
3440	"%sSTAR =%016RX64\n"
3441	"%sCSTAR =%016RX64\n"
3442	"%sLSTAR =%016RX64\n"
3443	"%sSFMASK =%016RX64\n"
3444	"%sKERNELGSBASE =%016RX64\n",
3445	pszPrefix, pCtx->msrEFER,
3446	pszPrefix, pCtx->msrPAT,
3447	pszPrefix, pCtx->msrSTAR,
3448	pszPrefix, pCtx->msrCSTAR,
3449	pszPrefix, pCtx->msrLSTAR,
3450	pszPrefix, pCtx->msrSFMASK,
3451	pszPrefix, pCtx->msrKERNELGSBASE);
3452
3453	if (CPUMIsGuestInPAEModeEx(pCtx))
3454	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aPaePdpes); i++)
3455	pHlp->pfnPrintf(pHlp, "%sPAE PDPTE %u =%016RX64\n", pszPrefix, i, pCtx->aPaePdpes[i]);
3456	break;
3457	}
3458	}
3459
3460
3461	/**
3462	* Display all cpu states and any other cpum info.
3463	*
3464	* @param pVM The cross context VM structure.
3465	* @param pHlp The info helper functions.
3466	* @param pszArgs Arguments, ignored.
3467	*/
3468	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3469	{
3470	cpumR3InfoGuest(pVM, pHlp, pszArgs);
3471	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3472	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
3473	cpumR3InfoHyper(pVM, pHlp, pszArgs);
3474	cpumR3InfoHost(pVM, pHlp, pszArgs);
3475	}
3476
3477
3478	/**
3479	* Parses the info argument.
3480	*
3481	* The argument starts with 'verbose', 'terse' or 'default' and then
3482	* continues with the comment string.
3483	*
3484	* @param pszArgs The pointer to the argument string.
3485	* @param penmType Where to store the dump type request.
3486	* @param ppszComment Where to store the pointer to the comment string.
3487	*/
3488	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
3489	{
3490	if (!pszArgs)
3491	{
3492	*penmType = CPUMDUMPTYPE_DEFAULT;
3493	*ppszComment = "";
3494	}
3495	else
3496	{
3497	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3498	{
3499	pszArgs += 7;
3500	*penmType = CPUMDUMPTYPE_VERBOSE;
3501	}
3502	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3503	{
3504	pszArgs += 5;
3505	*penmType = CPUMDUMPTYPE_TERSE;
3506	}
3507	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3508	{
3509	pszArgs += 7;
3510	*penmType = CPUMDUMPTYPE_DEFAULT;
3511	}
3512	else
3513	*penmType = CPUMDUMPTYPE_DEFAULT;
3514	*ppszComment = RTStrStripL(pszArgs);
3515	}
3516	}
3517
3518
3519	/**
3520	* Display the guest cpu state.
3521	*
3522	* @param pVM The cross context VM structure.
3523	* @param pHlp The info helper functions.
3524	* @param pszArgs Arguments.
3525	*/
3526	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3527	{
3528	CPUMDUMPTYPE enmType;
3529	const char *pszComment;
3530	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3531
3532	PVMCPU pVCpu = VMMGetCpu(pVM);
3533	if (!pVCpu)
3534	pVCpu = pVM->apCpusR3[0];
3535
3536	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3537
3538	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3539	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3540	}
3541
3542
3543	/**
3544	* Displays an SVM VMCB control area.
3545	*
3546	* @param pHlp The info helper functions.
3547	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
3548	* @param pszPrefix Caller specified string prefix.
3549	*/
3550	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
3551	{
3552	AssertReturnVoid(pHlp);
3553	AssertReturnVoid(pVmcbCtrl);
3554
3555	pHlp->pfnPrintf(pHlp, "%sCRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
3556	pHlp->pfnPrintf(pHlp, "%sCRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
3557	pHlp->pfnPrintf(pHlp, "%sDRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
3558	pHlp->pfnPrintf(pHlp, "%sDRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
3559	pHlp->pfnPrintf(pHlp, "%sException intercepts = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
3560	pHlp->pfnPrintf(pHlp, "%sControl intercepts = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
3561	pHlp->pfnPrintf(pHlp, "%sPause-filter threshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
3562	pHlp->pfnPrintf(pHlp, "%sPause-filter count = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
3563	pHlp->pfnPrintf(pHlp, "%sIOPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
3564	pHlp->pfnPrintf(pHlp, "%sMSRPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
3565	pHlp->pfnPrintf(pHlp, "%sTSC offset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
3566	pHlp->pfnPrintf(pHlp, "%sTLB Control\n", pszPrefix);
3567	pHlp->pfnPrintf(pHlp, " %sASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
3568	pHlp->pfnPrintf(pHlp, " %sTLB-flush type = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
3569	pHlp->pfnPrintf(pHlp, "%sInterrupt Control\n", pszPrefix);
3570	pHlp->pfnPrintf(pHlp, " %sVTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
3571	pHlp->pfnPrintf(pHlp, " %sVIRQ (Pending) = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
3572	pHlp->pfnPrintf(pHlp, " %sVINTR vector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
3573	pHlp->pfnPrintf(pHlp, " %sVGIF = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
3574	pHlp->pfnPrintf(pHlp, " %sVINTR priority = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
3575	pHlp->pfnPrintf(pHlp, " %sIgnore TPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
3576	pHlp->pfnPrintf(pHlp, " %sVINTR masking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
3577	pHlp->pfnPrintf(pHlp, " %sVGIF enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
3578	pHlp->pfnPrintf(pHlp, " %sAVIC enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
3579	pHlp->pfnPrintf(pHlp, "%sInterrupt Shadow\n", pszPrefix);
3580	pHlp->pfnPrintf(pHlp, " %sInterrupt shadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
3581	pHlp->pfnPrintf(pHlp, " %sGuest-interrupt Mask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
3582	pHlp->pfnPrintf(pHlp, "%sExit Code = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
3583	pHlp->pfnPrintf(pHlp, "%sEXITINFO1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
3584	pHlp->pfnPrintf(pHlp, "%sEXITINFO2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
3585	pHlp->pfnPrintf(pHlp, "%sExit Interrupt Info\n", pszPrefix);
3586	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
3587	pHlp->pfnPrintf(pHlp, " %sVector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
3588	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
3589	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
3590	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
3591	pHlp->pfnPrintf(pHlp, "%sNested paging and SEV\n", pszPrefix);
3592	pHlp->pfnPrintf(pHlp, " %sNested paging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
3593	pHlp->pfnPrintf(pHlp, " %sSEV (Secure Encrypted VM) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
3594	pHlp->pfnPrintf(pHlp, " %sSEV-ES (Encrypted State) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
3595	pHlp->pfnPrintf(pHlp, "%sEvent Inject\n", pszPrefix);
3596	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
3597	pHlp->pfnPrintf(pHlp, " %sVector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
3598	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
3599	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
3600	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
3601	pHlp->pfnPrintf(pHlp, "%sNested-paging CR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
3602	pHlp->pfnPrintf(pHlp, "%sLBR Virtualization\n", pszPrefix);
3603	pHlp->pfnPrintf(pHlp, " %sLBR virt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
3604	pHlp->pfnPrintf(pHlp, " %sVirt. VMSAVE/VMLOAD = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
3605	pHlp->pfnPrintf(pHlp, "%sVMCB Clean Bits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
3606	pHlp->pfnPrintf(pHlp, "%sNext-RIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
3607	pHlp->pfnPrintf(pHlp, "%sInstruction bytes fetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
3608	pHlp->pfnPrintf(pHlp, "%sInstruction bytes = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
3609	pHlp->pfnPrintf(pHlp, "%sAVIC\n", pszPrefix);
3610	pHlp->pfnPrintf(pHlp, " %sBar addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
3611	pHlp->pfnPrintf(pHlp, " %sBacking page addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
3612	pHlp->pfnPrintf(pHlp, " %sLogical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
3613	pHlp->pfnPrintf(pHlp, " %sPhysical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
3614	pHlp->pfnPrintf(pHlp, " %sLast guest core Id = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
3615	}
3616
3617
3618	/**
3619	* Helper for dumping the SVM VMCB selector registers.
3620	*
3621	* @param pHlp The info helper functions.
3622	* @param pSel Pointer to the SVM selector register.
3623	* @param pszName Name of the selector.
3624	* @param pszPrefix Caller specified string prefix.
3625	*/
3626	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
3627	{
3628	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
3629	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
3630	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
3631	}
3632
3633
3634	/**
3635	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
3636	*
3637	* @param pHlp The info helper functions.
3638	* @param pXdtr Pointer to the descriptor table register.
3639	* @param pszName Name of the descriptor table register.
3640	* @param pszPrefix Caller specified string prefix.
3641	*/
3642	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
3643	{
3644	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
3645	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
3646	}
3647
3648
3649	/**
3650	* Displays an SVM VMCB state-save area.
3651	*
3652	* @param pHlp The info helper functions.
3653	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
3654	* @param pszPrefix Caller specified string prefix.
3655	*/
3656	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
3657	{
3658	AssertReturnVoid(pHlp);
3659	AssertReturnVoid(pVmcbStateSave);
3660
3661	char szEFlags[80];
3662	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
3663
3664	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
3665	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
3666	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
3667	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
3668	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
3669	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
3670	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
3671	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
3672	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
3673	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
3674	pHlp->pfnPrintf(pHlp, "%sCPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
3675	pHlp->pfnPrintf(pHlp, "%sEFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
3676	pHlp->pfnPrintf(pHlp, "%sCR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
3677	pHlp->pfnPrintf(pHlp, "%sCR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
3678	pHlp->pfnPrintf(pHlp, "%sCR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
3679	pHlp->pfnPrintf(pHlp, "%sDR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
3680	pHlp->pfnPrintf(pHlp, "%sDR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
3681	pHlp->pfnPrintf(pHlp, "%sRFLAGS = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
3682	pHlp->pfnPrintf(pHlp, "%sRIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
3683	pHlp->pfnPrintf(pHlp, "%sRSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
3684	pHlp->pfnPrintf(pHlp, "%sRAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
3685	pHlp->pfnPrintf(pHlp, "%sSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
3686	pHlp->pfnPrintf(pHlp, "%sLSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
3687	pHlp->pfnPrintf(pHlp, "%sCSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
3688	pHlp->pfnPrintf(pHlp, "%sSFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
3689	pHlp->pfnPrintf(pHlp, "%sKERNELGSBASE = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
3690	pHlp->pfnPrintf(pHlp, "%sSysEnter CS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
3691	pHlp->pfnPrintf(pHlp, "%sSysEnter EIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
3692	pHlp->pfnPrintf(pHlp, "%sSysEnter ESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
3693	pHlp->pfnPrintf(pHlp, "%sCR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
3694	pHlp->pfnPrintf(pHlp, "%sPAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
3695	pHlp->pfnPrintf(pHlp, "%sDBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
3696	pHlp->pfnPrintf(pHlp, "%sBR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
3697	pHlp->pfnPrintf(pHlp, "%sBR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
3698	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
3699	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
3700	}
3701
3702
3703	/**
3704	* Displays a virtual-VMCS.
3705	*
3706	* @param pVCpu The cross context virtual CPU structure.
3707	* @param pHlp The info helper functions.
3708	* @param pVmcs Pointer to a virtual VMCS.
3709	* @param pszPrefix Caller specified string prefix.
3710	*/
3711	static void cpumR3InfoVmxVmcs(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, PCVMXVVMCS pVmcs, const char *pszPrefix)
3712	{
3713	AssertReturnVoid(pHlp);
3714	AssertReturnVoid(pVmcs);
3715
3716	/* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
3717	#define CPUMVMX_DUMP_HOST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3718	do { \
3719	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64}\n", \
3720	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u); \
3721	} while (0)
3722
3723	#define CPUMVMX_DUMP_HOST_FS_GS_TR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3724	do { \
3725	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64}\n", \
3726	(a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u); \
3727	} while (0)
3728
3729	#define CPUMVMX_DUMP_GUEST_SEGREG(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3730	do { \
3731	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
3732	(a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
3733	(a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr); \
3734	} while (0)
3735
3736	#define CPUMVMX_DUMP_GUEST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3737	do { \
3738	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64 limit=%08x}\n", \
3739	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit); \
3740	} while (0)
3741
3742	/* Header. */
3743	{
3744	pHlp->pfnPrintf(pHlp, "%sHeader:\n", pszPrefix);
3745	pHlp->pfnPrintf(pHlp, " %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId);
3746	pHlp->pfnPrintf(pHlp, " %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, VMXGetAbortDesc(pVmcs->enmVmxAbort));
3747	pHlp->pfnPrintf(pHlp, " %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, VMXGetVmcsStateDesc(pVmcs->fVmcsState));
3748	}
3749
3750	/* Control fields. */
3751	{
3752	/* 16-bit. */
3753	pHlp->pfnPrintf(pHlp, "%sControl:\n", pszPrefix);
3754	pHlp->pfnPrintf(pHlp, " %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid);
3755	pHlp->pfnPrintf(pHlp, " %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector);
3756	pHlp->pfnPrintf(pHlp, " %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex);
3757
3758	/* 32-bit. */
3759	pHlp->pfnPrintf(pHlp, " %sPin ctls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls);
3760	pHlp->pfnPrintf(pHlp, " %sProcessor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls);
3761	pHlp->pfnPrintf(pHlp, " %sSecondary processor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2);
3762	pHlp->pfnPrintf(pHlp, " %sVM-exit ctls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls);
3763	pHlp->pfnPrintf(pHlp, " %sVM-entry ctls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls);
3764	pHlp->pfnPrintf(pHlp, " %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap);
3765	pHlp->pfnPrintf(pHlp, " %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask);
3766	pHlp->pfnPrintf(pHlp, " %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch);
3767	pHlp->pfnPrintf(pHlp, " %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount);
3768	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount);
3769	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount);
3770	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount);
3771	pHlp->pfnPrintf(pHlp, " %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo);
3772	{
3773	uint32_t const fInfo = pVmcs->u32EntryIntInfo;
3774	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
3775	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo));
3776	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetEntryIntInfoTypeDesc(uType));
3777	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo));
3778	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3779	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3780	}
3781	pHlp->pfnPrintf(pHlp, " %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode);
3782	pHlp->pfnPrintf(pHlp, " %sVM-entry instr length = %u byte(s)\n", pszPrefix, pVmcs->u32EntryInstrLen);
3783	pHlp->pfnPrintf(pHlp, " %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold);
3784	pHlp->pfnPrintf(pHlp, " %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap);
3785	pHlp->pfnPrintf(pHlp, " %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow);
3786
3787	/* 64-bit. */
3788	pHlp->pfnPrintf(pHlp, " %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u);
3789	pHlp->pfnPrintf(pHlp, " %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u);
3790	pHlp->pfnPrintf(pHlp, " %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u);
3791	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u);
3792	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u);
3793	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u);
3794	pHlp->pfnPrintf(pHlp, " %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u);
3795	pHlp->pfnPrintf(pHlp, " %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u);
3796	pHlp->pfnPrintf(pHlp, " %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u);
3797	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u);
3798	pHlp->pfnPrintf(pHlp, " %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u);
3799	pHlp->pfnPrintf(pHlp, " %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u);
3800	pHlp->pfnPrintf(pHlp, " %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u);
3801	pHlp->pfnPrintf(pHlp, " %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptPtr.u);
3802	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 0 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u);
3803	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 1 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u);
3804	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 2 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u);
3805	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 3 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u);
3806	pHlp->pfnPrintf(pHlp, " %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u);
3807	pHlp->pfnPrintf(pHlp, " %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u);
3808	pHlp->pfnPrintf(pHlp, " %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u);
3809	pHlp->pfnPrintf(pHlp, " %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u);
3810	pHlp->pfnPrintf(pHlp, " %sXSS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssExitBitmap.u);
3811	pHlp->pfnPrintf(pHlp, " %sENCLS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclsExitBitmap.u);
3812	pHlp->pfnPrintf(pHlp, " %sSPP-table ptr = %#RX64\n", pszPrefix, pVmcs->u64SppTablePtr.u);
3813	pHlp->pfnPrintf(pHlp, " %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u);
3814	pHlp->pfnPrintf(pHlp, " %sTertiary processor ctls = %#RX64\n", pszPrefix, pVmcs->u64ProcCtls3.u);
3815	pHlp->pfnPrintf(pHlp, " %sENCLV-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclvExitBitmap.u);
3816
3817	/* Natural width. */
3818	pHlp->pfnPrintf(pHlp, " %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u);
3819	pHlp->pfnPrintf(pHlp, " %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u);
3820	pHlp->pfnPrintf(pHlp, " %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u);
3821	pHlp->pfnPrintf(pHlp, " %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u);
3822	pHlp->pfnPrintf(pHlp, " %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u);
3823	pHlp->pfnPrintf(pHlp, " %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u);
3824	pHlp->pfnPrintf(pHlp, " %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u);
3825	pHlp->pfnPrintf(pHlp, " %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u);
3826	}
3827
3828	/* Guest state. */
3829	{
3830	char szEFlags[80];
3831	cpumR3InfoFormatFlags(&szEFlags[0], pVmcs->u64GuestRFlags.u);
3832	pHlp->pfnPrintf(pHlp, "%sGuest state:\n", pszPrefix);
3833
3834	/* 16-bit. */
3835	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Cs, "CS", pszPrefix);
3836	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ss, "SS", pszPrefix);
3837	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Es, "ES", pszPrefix);
3838	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ds, "DS", pszPrefix);
3839	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Fs, "FS", pszPrefix);
3840	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Gs, "GS", pszPrefix);
3841	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ldtr, "LDTR", pszPrefix);
3842	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Tr, "TR", pszPrefix);
3843	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
3844	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
3845	pHlp->pfnPrintf(pHlp, " %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus);
3846	pHlp->pfnPrintf(pHlp, " %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex);
3847
3848	/* 32-bit. */
3849	pHlp->pfnPrintf(pHlp, " %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState);
3850	pHlp->pfnPrintf(pHlp, " %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState);
3851	pHlp->pfnPrintf(pHlp, " %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase);
3852	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS);
3853	pHlp->pfnPrintf(pHlp, " %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer);
3854
3855	/* 64-bit. */
3856	pHlp->pfnPrintf(pHlp, " %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u);
3857	pHlp->pfnPrintf(pHlp, " %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u);
3858	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u);
3859	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u);
3860	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u);
3861	pHlp->pfnPrintf(pHlp, " %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u);
3862	pHlp->pfnPrintf(pHlp, " %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u);
3863	pHlp->pfnPrintf(pHlp, " %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u);
3864	pHlp->pfnPrintf(pHlp, " %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u);
3865	pHlp->pfnPrintf(pHlp, " %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u);
3866	pHlp->pfnPrintf(pHlp, " %sRTIT_CTL = %#RX64\n", pszPrefix, pVmcs->u64GuestRtitCtlMsr.u);
3867	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64GuestPkrsMsr.u);
3868
3869	/* Natural width. */
3870	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u);
3871	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u);
3872	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u);
3873	pHlp->pfnPrintf(pHlp, " %sDR7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u);
3874	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u);
3875	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u);
3876	pHlp->pfnPrintf(pHlp, " %sRFLAGS = %#RX64 %31s\n",pszPrefix, pVmcs->u64GuestRFlags.u, szEFlags);
3877	pHlp->pfnPrintf(pHlp, " %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpts.u);
3878	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u);
3879	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u);
3880	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64GuestSCetMsr.u);
3881	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64GuestSsp.u);
3882	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64GuestIntrSspTableAddrMsr.u);
3883	}
3884
3885	/* Host state. */
3886	{
3887	pHlp->pfnPrintf(pHlp, "%sHost state:\n", pszPrefix);
3888
3889	/* 16-bit. */
3890	pHlp->pfnPrintf(pHlp, " %sCS = %#RX16\n", pszPrefix, pVmcs->HostCs);
3891	pHlp->pfnPrintf(pHlp, " %sSS = %#RX16\n", pszPrefix, pVmcs->HostSs);
3892	pHlp->pfnPrintf(pHlp, " %sDS = %#RX16\n", pszPrefix, pVmcs->HostDs);
3893	pHlp->pfnPrintf(pHlp, " %sES = %#RX16\n", pszPrefix, pVmcs->HostEs);
3894	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Fs, "FS", pszPrefix);
3895	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Gs, "GS", pszPrefix);
3896	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Tr, "TR", pszPrefix);
3897	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
3898	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
3899
3900	/* 32-bit. */
3901	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs);
3902
3903	/* 64-bit. */
3904	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u);
3905	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u);
3906	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u);
3907	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64HostPkrsMsr.u);
3908
3909	/* Natural width. */
3910	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u);
3911	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u);
3912	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u);
3913	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u);
3914	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u);
3915	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u);
3916	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u);
3917	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64HostSCetMsr.u);
3918	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64HostSsp.u);
3919	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64HostIntrSspTableAddrMsr.u);
3920
3921	}
3922
3923	/* Read-only fields. */
3924	{
3925	pHlp->pfnPrintf(pHlp, "%sRead-only data fields:\n", pszPrefix);
3926
3927	/* 16-bit (none currently). */
3928
3929	/* 32-bit. */
3930	pHlp->pfnPrintf(pHlp, " %sExit reason = %u (%s)\n", pszPrefix, pVmcs->u32RoExitReason, HMGetVmxExitName(pVmcs->u32RoExitReason));
3931	pHlp->pfnPrintf(pHlp, " %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u);
3932	pHlp->pfnPrintf(pHlp, " %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError);
3933	pHlp->pfnPrintf(pHlp, " %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo);
3934	{
3935	uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
3936	uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
3937	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo));
3938	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetExitIntInfoTypeDesc(uType));
3939	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo));
3940	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3941	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3942	}
3943	pHlp->pfnPrintf(pHlp, " %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode);
3944	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo);
3945	{
3946	uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
3947	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
3948	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo));
3949	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetIdtVectoringInfoTypeDesc(uType));
3950	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo));
3951	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo));
3952	}
3953	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode);
3954	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction length = %u byte(s)\n", pszPrefix, pVmcs->u32RoExitInstrLen);
3955	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo);
3956
3957	/* 64-bit. */
3958	pHlp->pfnPrintf(pHlp, " %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u);
3959
3960	/* Natural width. */
3961	pHlp->pfnPrintf(pHlp, " %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u);
3962	pHlp->pfnPrintf(pHlp, " %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u);
3963	pHlp->pfnPrintf(pHlp, " %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u);
3964	pHlp->pfnPrintf(pHlp, " %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u);
3965	pHlp->pfnPrintf(pHlp, " %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u);
3966	}
3967
3968	#ifdef DEBUG_ramshankar
3969	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
3970	{
3971	void *pvPage = RTMemTmpAllocZ(VMX_V_VIRT_APIC_SIZE);
3972	Assert(pvPage);
3973	RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3974	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pvPage, GCPhysVirtApic, VMX_V_VIRT_APIC_SIZE);
3975	if (RT_SUCCESS(rc))
3976	{
3977	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC page\n", pszPrefix);
3978	pHlp->pfnPrintf(pHlp, "%.*Rhxs\n", VMX_V_VIRT_APIC_SIZE, pvPage);
3979	pHlp->pfnPrintf(pHlp, "\n");
3980	}
3981	RTMemTmpFree(pvPage);
3982	}
3983	#else
3984	NOREF(pVCpu);
3985	#endif
3986
3987	#undef CPUMVMX_DUMP_HOST_XDTR
3988	#undef CPUMVMX_DUMP_HOST_FS_GS_TR
3989	#undef CPUMVMX_DUMP_GUEST_SEGREG
3990	#undef CPUMVMX_DUMP_GUEST_XDTR
3991	}
3992
3993
3994	/**
3995	* Display the guest's hardware-virtualization cpu state.
3996	*
3997	* @param pVM The cross context VM structure.
3998	* @param pHlp The info helper functions.
3999	* @param pszArgs Arguments, ignored.
4000	*/
4001	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4002	{
4003	RT_NOREF(pszArgs);
4004
4005	PVMCPU pVCpu = VMMGetCpu(pVM);
4006	if (!pVCpu)
4007	pVCpu = pVM->apCpusR3[0];
4008
4009	PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4010	bool const fSvm = pVM->cpum.s.GuestFeatures.fSvm;
4011	bool const fVmx = pVM->cpum.s.GuestFeatures.fVmx;
4012
4013	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
4014	pHlp->pfnPrintf(pHlp, "fSavedInhibit = %#RX32\n", pCtx->hwvirt.fSavedInhibit);
4015	pHlp->pfnPrintf(pHlp, "In nested-guest hwvirt mode = %RTbool\n", CPUMIsGuestInNestedHwvirtMode(pCtx));
4016
4017	if (fSvm)
4018	{
4019	pHlp->pfnPrintf(pHlp, "SVM hwvirt state:\n");
4020	pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
4021
4022	char szEFlags[80];
4023	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
4024	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
4025	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
4026	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
4027	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.Vmcb.ctrl, " " /* pszPrefix */);
4028	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
4029	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.Vmcb.guest, " " /* pszPrefix */);
4030	pHlp->pfnPrintf(pHlp, " HostState:\n");
4031	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
4032	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
4033	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
4034	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
4035	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
4036	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
4037	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
4038	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
4039	PCCPUMSELREG pSelEs = &pCtx->hwvirt.svm.HostState.es;
4040	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4041	pSelEs->Sel, pSelEs->u64Base, pSelEs->u32Limit, pSelEs->Attr.u);
4042	PCCPUMSELREG pSelCs = &pCtx->hwvirt.svm.HostState.cs;
4043	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4044	pSelCs->Sel, pSelCs->u64Base, pSelCs->u32Limit, pSelCs->Attr.u);
4045	PCCPUMSELREG pSelSs = &pCtx->hwvirt.svm.HostState.ss;
4046	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4047	pSelSs->Sel, pSelSs->u64Base, pSelSs->u32Limit, pSelSs->Attr.u);
4048	PCCPUMSELREG pSelDs = &pCtx->hwvirt.svm.HostState.ds;
4049	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4050	pSelDs->Sel, pSelDs->u64Base, pSelDs->u32Limit, pSelDs->Attr.u);
4051	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
4052	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
4053	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
4054	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
4055	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
4056	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
4057	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
4058	}
4059	else if (fVmx)
4060	{
4061	pHlp->pfnPrintf(pHlp, "VMX hwvirt state:\n");
4062	pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
4063	pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
4064	pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
4065	pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag));
4066	pHlp->pfnPrintf(pHlp, " uDiagAux = %#RX64\n", pCtx->hwvirt.vmx.uDiagAux);
4067	pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, VMXGetAbortDesc(pCtx->hwvirt.vmx.enmAbort));
4068	pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
4069	pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
4070	pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
4071	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
4072	pHlp->pfnPrintf(pHlp, " fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret);
4073	pHlp->pfnPrintf(pHlp, " uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick);
4074	pHlp->pfnPrintf(pHlp, " uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick);
4075	pHlp->pfnPrintf(pHlp, " uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick);
4076	pHlp->pfnPrintf(pHlp, " offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite);
4077	pHlp->pfnPrintf(pHlp, " fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking);
4078	pHlp->pfnPrintf(pHlp, " VMCS cache:\n");
4079	cpumR3InfoVmxVmcs(pVCpu, pHlp, &pCtx->hwvirt.vmx.Vmcs, " " /* pszPrefix */);
4080	}
4081	else
4082	pHlp->pfnPrintf(pHlp, "Hwvirt state disabled.\n");
4083
4084	#undef CPUMHWVIRTDUMP_NONE
4085	#undef CPUMHWVIRTDUMP_COMMON
4086	#undef CPUMHWVIRTDUMP_SVM
4087	#undef CPUMHWVIRTDUMP_VMX
4088	#undef CPUMHWVIRTDUMP_LAST
4089	#undef CPUMHWVIRTDUMP_ALL
4090	}
4091
4092	/**
4093	* Display the current guest instruction
4094	*
4095	* @param pVM The cross context VM structure.
4096	* @param pHlp The info helper functions.
4097	* @param pszArgs Arguments, ignored.
4098	*/
4099	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4100	{
4101	NOREF(pszArgs);
4102
4103	PVMCPU pVCpu = VMMGetCpu(pVM);
4104	if (!pVCpu)
4105	pVCpu = pVM->apCpusR3[0];
4106
4107	char szInstruction[256];
4108	szInstruction[0] = '\0';
4109	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
4110	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
4111	}
4112
4113
4114	/**
4115	* Display the hypervisor cpu state.
4116	*
4117	* @param pVM The cross context VM structure.
4118	* @param pHlp The info helper functions.
4119	* @param pszArgs Arguments, ignored.
4120	*/
4121	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4122	{
4123	PVMCPU pVCpu = VMMGetCpu(pVM);
4124	if (!pVCpu)
4125	pVCpu = pVM->apCpusR3[0];
4126
4127	CPUMDUMPTYPE enmType;
4128	const char *pszComment;
4129	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4130	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
4131
4132	pHlp->pfnPrintf(pHlp,
4133	".dr0=%016RX64 .dr1=%016RX64 .dr2=%016RX64 .dr3=%016RX64\n"
4134	".dr4=%016RX64 .dr5=%016RX64 .dr6=%016RX64 .dr7=%016RX64\n",
4135	pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1], pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3],
4136	pVCpu->cpum.s.Hyper.dr[4], pVCpu->cpum.s.Hyper.dr[5], pVCpu->cpum.s.Hyper.dr[6], pVCpu->cpum.s.Hyper.dr[7]);
4137	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
4138	}
4139
4140
4141	/**
4142	* Display the host cpu state.
4143	*
4144	* @param pVM The cross context VM structure.
4145	* @param pHlp The info helper functions.
4146	* @param pszArgs Arguments, ignored.
4147	*/
4148	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4149	{
4150	CPUMDUMPTYPE enmType;
4151	const char *pszComment;
4152	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4153	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
4154
4155	PVMCPU pVCpu = VMMGetCpu(pVM);
4156	if (!pVCpu)
4157	pVCpu = pVM->apCpusR3[0];
4158	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
4159
4160	/*
4161	* Format the EFLAGS.
4162	*/
4163	uint64_t efl = pCtx->rflags;
4164	char szEFlags[80];
4165	cpumR3InfoFormatFlags(&szEFlags[0], efl);
4166
4167	/*
4168	* Format the registers.
4169	*/
4170	pHlp->pfnPrintf(pHlp,
4171	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
4172	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
4173	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
4174	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
4175	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
4176	"r14=%016RX64 r15=%016RX64\n"
4177	"iopl=%d %31s\n"
4178	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
4179	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
4180	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
4181	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
4182	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
4183	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
4184	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
4185	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
4186	,
4187	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
4188	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
4189	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
4190	/pCtx->r8, pCtx->r9,/ pCtx->r10,
4191	pCtx->r11, pCtx->r12, pCtx->r13,
4192	pCtx->r14, pCtx->r15,
4193	X86_EFL_GET_IOPL(efl), szEFlags,
4194	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
4195	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
4196	pCtx->cr4, pCtx->ldtr, pCtx->tr,
4197	pCtx->dr0, pCtx->dr1, pCtx->dr2,
4198	pCtx->dr3, pCtx->dr6, pCtx->dr7,
4199	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
4200	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
4201	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
4202	}
4203
4204	/**
4205	* Structure used when disassembling and instructions in DBGF.
4206	* This is used so the reader function can get the stuff it needs.
4207	*/
4208	typedef struct CPUMDISASSTATE
4209	{
4210	/** Pointer to the CPU structure. */
4211	PDISCPUSTATE pCpu;
4212	/** Pointer to the VM. */
4213	PVM pVM;
4214	/** Pointer to the VMCPU. */
4215	PVMCPU pVCpu;
4216	/** Pointer to the first byte in the segment. */
4217	RTGCUINTPTR GCPtrSegBase;
4218	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
4219	RTGCUINTPTR GCPtrSegEnd;
4220	/** The size of the segment minus 1. */
4221	RTGCUINTPTR cbSegLimit;
4222	/** Pointer to the current page - R3 Ptr. */
4223	void const *pvPageR3;
4224	/** Pointer to the current page - GC Ptr. */
4225	RTGCPTR pvPageGC;
4226	/** The lock information that PGMPhysReleasePageMappingLock needs. */
4227	PGMPAGEMAPLOCK PageMapLock;
4228	/** Whether the PageMapLock is valid or not. */
4229	bool fLocked;
4230	/** 64 bits mode or not. */
4231	bool f64Bits;
4232	} CPUMDISASSTATE, *PCPUMDISASSTATE;
4233
4234
4235	/**
4236	* @callback_method_impl{FNDISREADBYTES}
4237	*/
4238	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4239	{
4240	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4241	for (;;)
4242	{
4243	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4244
4245	/*
4246	* Need to update the page translation?
4247	*/
4248	if ( !pState->pvPageR3
4249	\|\| (GCPtr >> GUEST_PAGE_SHIFT) != (pState->pvPageGC >> GUEST_PAGE_SHIFT))
4250	{
4251	/* translate the address */
4252	pState->pvPageGC = GCPtr & ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
4253
4254	/* Release mapping lock previously acquired. */
4255	if (pState->fLocked)
4256	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4257	int rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4258	if (RT_SUCCESS(rc))
4259	pState->fLocked = true;
4260	else
4261	{
4262	pState->fLocked = false;
4263	pState->pvPageR3 = NULL;
4264	return rc;
4265	}
4266	}
4267
4268	/*
4269	* Check the segment limit.
4270	*/
4271	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4272	return VERR_OUT_OF_SELECTOR_BOUNDS;
4273
4274	/*
4275	* Calc how much we can read.
4276	*/
4277	uint32_t cb = GUEST_PAGE_SIZE - (GCPtr & GUEST_PAGE_OFFSET_MASK);
4278	if (!pState->f64Bits)
4279	{
4280	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4281	if (cb > cbSeg && cbSeg)
4282	cb = cbSeg;
4283	}
4284	if (cb > cbMaxRead)
4285	cb = cbMaxRead;
4286
4287	/*
4288	* Read and advance or exit.
4289	*/
4290	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & GUEST_PAGE_OFFSET_MASK), cb);
4291	offInstr += (uint8_t)cb;
4292	if (cb >= cbMinRead)
4293	{
4294	pDis->cbCachedInstr = offInstr;
4295	return VINF_SUCCESS;
4296	}
4297	cbMinRead -= (uint8_t)cb;
4298	cbMaxRead -= (uint8_t)cb;
4299	}
4300	}
4301
4302
4303	/**
4304	* Disassemble an instruction and return the information in the provided structure.
4305	*
4306	* @returns VBox status code.
4307	* @param pVM The cross context VM structure.
4308	* @param pVCpu The cross context virtual CPU structure.
4309	* @param pCtx Pointer to the guest CPU context.
4310	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
4311	* @param pCpu Disassembly state.
4312	* @param pszPrefix String prefix for logging (debug only).
4313	*
4314	*/
4315	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
4316	const char *pszPrefix)
4317	{
4318	CPUMDISASSTATE State;
4319	int rc;
4320
4321	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4322	State.pCpu = pCpu;
4323	State.pvPageGC = 0;
4324	State.pvPageR3 = NULL;
4325	State.pVM = pVM;
4326	State.pVCpu = pVCpu;
4327	State.fLocked = false;
4328	State.f64Bits = false;
4329
4330	/*
4331	* Get selector information.
4332	*/
4333	DISCPUMODE enmDisCpuMode;
4334	if ( (pCtx->cr0 & X86_CR0_PE)
4335	&& pCtx->eflags.Bits.u1VM == 0)
4336	{
4337	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4338	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4339	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4340	State.GCPtrSegBase = pCtx->cs.u64Base;
4341	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4342	State.cbSegLimit = pCtx->cs.u32Limit;
4343	enmDisCpuMode = (State.f64Bits)
4344	? DISCPUMODE_64BIT
4345	: pCtx->cs.Attr.n.u1DefBig
4346	? DISCPUMODE_32BIT
4347	: DISCPUMODE_16BIT;
4348	}
4349	else
4350	{
4351	/* real or V86 mode */
4352	enmDisCpuMode = DISCPUMODE_16BIT;
4353	State.GCPtrSegBase = pCtx->cs.Sel * 16;
4354	State.GCPtrSegEnd = 0xFFFFFFFF;
4355	State.cbSegLimit = 0xFFFFFFFF;
4356	}
4357
4358	/*
4359	* Disassemble the instruction.
4360	*/
4361	uint32_t cbInstr;
4362	#ifndef LOG_ENABLED
4363	RT_NOREF_PV(pszPrefix);
4364	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4365	if (RT_SUCCESS(rc))
4366	{
4367	#else
4368	char szOutput[160];
4369	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4370	pCpu, &cbInstr, szOutput, sizeof(szOutput));
4371	if (RT_SUCCESS(rc))
4372	{
4373	/* log it */
4374	if (pszPrefix)
4375	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4376	else
4377	Log(("%s", szOutput));
4378	#endif
4379	rc = VINF_SUCCESS;
4380	}
4381	else
4382	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4383
4384	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
4385	if (State.fLocked)
4386	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4387
4388	return rc;
4389	}
4390
4391
4392
4393	/**
4394	* API for controlling a few of the CPU features found in CR4.
4395	*
4396	* Currently only X86_CR4_TSD is accepted as input.
4397	*
4398	* @returns VBox status code.
4399	*
4400	* @param pVM The cross context VM structure.
4401	* @param fOr The CR4 OR mask.
4402	* @param fAnd The CR4 AND mask.
4403	*/
4404	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4405	{
4406	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4407	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4408
4409	pVM->cpum.s.CR4.OrMask &= fAnd;
4410	pVM->cpum.s.CR4.OrMask \|= fOr;
4411
4412	return VINF_SUCCESS;
4413	}
4414
4415
4416	/**
4417	* Called when the ring-3 init phase completes.
4418	*
4419	* @returns VBox status code.
4420	* @param pVM The cross context VM structure.
4421	* @param enmWhat Which init phase.
4422	*/
4423	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
4424	{
4425	switch (enmWhat)
4426	{
4427	case VMINITCOMPLETED_RING3:
4428	{
4429	/*
4430	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
4431	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
4432	*/
4433	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
4434	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4435	{
4436	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4437
4438	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
4439	if (fSupportsLongMode)
4440	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
4441	}
4442
4443	/* Register statistic counters for MSRs. */
4444	cpumR3MsrRegStats(pVM);
4445
4446	/* There shouldn't be any more calls to CPUMR3SetGuestCpuIdFeature and
4447	CPUMR3ClearGuestCpuIdFeature now, so do some final CPUID polishing (NX). */
4448	cpumR3CpuIdRing3InitDone(pVM);
4449
4450	/* Create VMX-preemption timer for nested guests if required. Must be
4451	done here as CPUM is initialized before TM. */
4452	if (pVM->cpum.s.GuestFeatures.fVmx)
4453	{
4454	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4455	{
4456	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4457	char szName[32];
4458	RTStrPrintf(szName, sizeof(szName), "Nested VMX-preemption %u", idCpu);
4459	int rc = TMR3TimerCreate(pVM, TMCLOCK_VIRTUAL_SYNC, cpumR3VmxPreemptTimerCallback, pVCpu,
4460	TMTIMER_FLAGS_RING0, szName, &pVCpu->cpum.s.hNestedVmxPreemptTimer);
4461	AssertLogRelRCReturn(rc, rc);
4462	}
4463	}
4464	break;
4465	}
4466
4467	default:
4468	break;
4469	}
4470	return VINF_SUCCESS;
4471	}
4472
4473
4474	/**
4475	* Called when the ring-0 init phases completed.
4476	*
4477	* @param pVM The cross context VM structure.
4478	*/
4479	VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
4480	{
4481	/*
4482	* Enable log buffering as we're going to log a lot of lines.
4483	*/
4484	bool const fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
4485
4486	/*
4487	* Log the cpuid.
4488	*/
4489	RTCPUSET OnlineSet;
4490	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4491	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4492	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4493	RTCPUID cCores = RTMpGetCoreCount();
4494	if (cCores)
4495	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
4496	LogRel(("*********************** CPUID dump **********************\n"));
4497	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4498	LogRel(("\n"));
4499	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
4500	LogRel(("****************** End of CPUID dump ********************\n"));
4501
4502	/*
4503	* Log VT-x extended features.
4504	*
4505	* SVM features are currently all covered under CPUID so there is nothing
4506	* to do here for SVM.
4507	*/
4508	if (pVM->cpum.s.HostFeatures.fVmx)
4509	{
4510	LogRel(("********************* VT-x features *********************\n"));
4511	DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
4512	LogRel(("\n"));
4513	LogRel(("***************** End of VT-x features ******************\n"));
4514	}
4515
4516	/*
4517	* Restore the log buffering state to what it was previously.
4518	*/
4519	RTLogRelSetBuffering(fOldBuffered);
4520	}
4521
4522
4523	/**
4524	* Marks the guest debug state as active.
4525	*
4526	* @returns nothing.
4527	* @param pVCpu The cross context virtual CPU structure.
4528	*
4529	* @note This is used solely by NEM (hence the name) to set the correct flags here
4530	* without loading the host's DRx registers, which is not possible from ring-3 anyway.
4531	* The specific NEM backends have to make sure to load the correct values.
4532	*/
4533	VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu)
4534	{
4535	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HYPER);
4536	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
4537	}
4538
4539
4540	/**
4541	* Marks the hyper debug state as active.
4542	*
4543	* @returns nothing.
4544	* @param pVCpu The cross context virtual CPU structure.
4545	*
4546	* @note This is used solely by NEM (hence the name) to set the correct flags here
4547	* without loading the host's DRx registers, which is not possible from ring-3 anyway.
4548	* The specific NEM backends have to make sure to load the correct values.
4549	*/
4550	VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu)
4551	{
4552	/*
4553	* Make sure the hypervisor values are up to date.
4554	*/
4555	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */);
4556
4557	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_GUEST);
4558	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
4559	}

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 97178

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