VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 93223

Last change on this file since 93223 was 93223, checked in by vboxsync, 3 years ago

VMM: Nested VMX: bugref:10092 When Unrestricted Guest is supported by the CPU, the CPU still reports PE and PG bits as MB1 in IA32_VMX_CR0_FIXED0. It's just VMX instructions ignores them.
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1/* $Id: CPUM.cpp 93223 2022-01-13 12:07:19Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 *
33 * @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34 *
35 * TODO: proper write up, currently just some notes.
36 *
37 * The ring-0 FPU handling per OS:
38 *
39 * - 64-bit Windows uses XMM registers in the kernel as part of the calling
40 * convention (Visual C++ doesn't seem to have a way to disable
41 * generating such code either), so CR0.TS/EM are always zero from what I
42 * can tell. We are also forced to always load/save the guest XMM0-XMM15
43 * registers when entering/leaving guest context. Interrupt handlers
44 * using FPU/SSE will offically have call save and restore functions
45 * exported by the kernel, if the really really have to use the state.
46 *
47 * - 32-bit windows does lazy FPU handling, I think, probably including
48 * lazying saving. The Windows Internals book states that it's a bad
49 * idea to use the FPU in kernel space. However, it looks like it will
50 * restore the FPU state of the current thread in case of a kernel \#NM.
51 * Interrupt handlers should be same as for 64-bit.
52 *
53 * - Darwin allows taking \#NM in kernel space, restoring current thread's
54 * state if I read the code correctly. It saves the FPU state of the
55 * outgoing thread, and uses CR0.TS to lazily load the state of the
56 * incoming one. No idea yet how the FPU is treated by interrupt
57 * handlers, i.e. whether they are allowed to disable the state or
58 * something.
59 *
60 * - Linux also allows \#NM in kernel space (don't know since when), and
61 * uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62 * loads the incoming unless configured to agressivly load it. Interrupt
63 * handlers can ask whether they're allowed to use the FPU, and may
64 * freely trash the state if Linux thinks it has saved the thread's state
65 * already. This is a problem.
66 *
67 * - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68 * context. When switching threads, the kernel will save the state of
69 * the outgoing thread and lazy load the incoming one using CR0.TS.
70 * There are a few routines in seeblk.s which uses the SSE unit in ring-0
71 * to do stuff, HAT are among the users. The routines there will
72 * manually clear CR0.TS and save the XMM registers they use only if
73 * CR0.TS was zero upon entry. They will skip it when not, because as
74 * mentioned above, the FPU state is saved when switching away from a
75 * thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76 * preserve. This is a problem if we restore CR0.TS to 1 after loading
77 * the guest state.
78 *
79 * - FreeBSD - no idea yet.
80 *
81 * - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82 * possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83 * FPU states.
84 *
85 * Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86 * saving and restoring the host and guest states. The motivation for this
87 * change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88 *
89 * Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90 * state and only restore it once we've restore the host FPU state. This has the
91 * accidental side effect of triggering Solaris to preserve XMM registers in
92 * sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93 * the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94 *
95 *
96 * @section sec_cpum_logging Logging Level Assignments.
97 *
98 * Following log level assignments:
99 * - Log6 is used for FPU state management.
100 * - Log7 is used for FPU state actualization.
101 *
102 */
103
104
105/*********************************************************************************************************************************
106* Header Files *
107*********************************************************************************************************************************/
108#define LOG_GROUP LOG_GROUP_CPUM
109#include <VBox/vmm/cpum.h>
110#include <VBox/vmm/cpumdis.h>
111#include <VBox/vmm/cpumctx-v1_6.h>
112#include <VBox/vmm/pgm.h>
113#include <VBox/vmm/apic.h>
114#include <VBox/vmm/mm.h>
115#include <VBox/vmm/em.h>
116#include <VBox/vmm/iem.h>
117#include <VBox/vmm/selm.h>
118#include <VBox/vmm/dbgf.h>
119#include <VBox/vmm/hm.h>
120#include <VBox/vmm/hmvmxinline.h>
121#include <VBox/vmm/ssm.h>
122#include "CPUMInternal.h"
123#include <VBox/vmm/vm.h>
124
125#include <VBox/param.h>
126#include <VBox/dis.h>
127#include <VBox/err.h>
128#include <VBox/log.h>
129#include <iprt/asm-amd64-x86.h>
130#include <iprt/assert.h>
131#include <iprt/cpuset.h>
132#include <iprt/mem.h>
133#include <iprt/mp.h>
134#include <iprt/string.h>
135
136
137/*********************************************************************************************************************************
138* Defined Constants And Macros *
139*********************************************************************************************************************************/
140/**
141 * This was used in the saved state up to the early life of version 14.
142 *
143 * It indicates that we may have some out-of-sync hidden segement registers.
144 * It is only relevant for raw-mode.
145 */
146#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
147
148
149/*********************************************************************************************************************************
150* Structures and Typedefs *
151*********************************************************************************************************************************/
152
153/**
154 * What kind of cpu info dump to perform.
155 */
156typedef enum CPUMDUMPTYPE
157{
158 CPUMDUMPTYPE_TERSE,
159 CPUMDUMPTYPE_DEFAULT,
160 CPUMDUMPTYPE_VERBOSE
161} CPUMDUMPTYPE;
162/** Pointer to a cpu info dump type. */
163typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
164
165
166/*********************************************************************************************************************************
167* Internal Functions *
168*********************************************************************************************************************************/
169static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
170static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
171static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
172static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
173static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
174static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
179static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
180
181
182/*********************************************************************************************************************************
183* Global Variables *
184*********************************************************************************************************************************/
185/** Saved state field descriptors for CPUMCTX. */
186static const SSMFIELD g_aCpumCtxFields[] =
187{
188 SSMFIELD_ENTRY( CPUMCTX, rdi),
189 SSMFIELD_ENTRY( CPUMCTX, rsi),
190 SSMFIELD_ENTRY( CPUMCTX, rbp),
191 SSMFIELD_ENTRY( CPUMCTX, rax),
192 SSMFIELD_ENTRY( CPUMCTX, rbx),
193 SSMFIELD_ENTRY( CPUMCTX, rdx),
194 SSMFIELD_ENTRY( CPUMCTX, rcx),
195 SSMFIELD_ENTRY( CPUMCTX, rsp),
196 SSMFIELD_ENTRY( CPUMCTX, rflags),
197 SSMFIELD_ENTRY( CPUMCTX, rip),
198 SSMFIELD_ENTRY( CPUMCTX, r8),
199 SSMFIELD_ENTRY( CPUMCTX, r9),
200 SSMFIELD_ENTRY( CPUMCTX, r10),
201 SSMFIELD_ENTRY( CPUMCTX, r11),
202 SSMFIELD_ENTRY( CPUMCTX, r12),
203 SSMFIELD_ENTRY( CPUMCTX, r13),
204 SSMFIELD_ENTRY( CPUMCTX, r14),
205 SSMFIELD_ENTRY( CPUMCTX, r15),
206 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
207 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
208 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
209 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
210 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
211 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
212 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
213 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
214 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
215 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
216 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
217 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
218 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
219 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
220 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
221 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
222 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
223 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
224 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
225 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
226 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
227 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
228 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
229 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
230 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
231 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
232 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
233 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
234 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
235 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
236 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
237 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
238 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
239 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
240 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
241 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
242 SSMFIELD_ENTRY( CPUMCTX, cr0),
243 SSMFIELD_ENTRY( CPUMCTX, cr2),
244 SSMFIELD_ENTRY( CPUMCTX, cr3),
245 SSMFIELD_ENTRY( CPUMCTX, cr4),
246 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
247 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
248 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
249 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
250 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
251 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
252 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
253 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
254 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
255 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
256 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
257 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
258 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
259 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
260 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
261 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
262 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
263 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
264 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
265 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
266 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
267 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
268 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
269 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
270 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
271 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
272 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
273 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
274 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
275 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
276 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
277 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
278 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
279 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
280 SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
281 SSMFIELD_ENTRY_TERM()
282};
283
284/** Saved state field descriptors for SVM nested hardware-virtualization
285 * Host State. */
286static const SSMFIELD g_aSvmHwvirtHostState[] =
287{
288 SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
289 SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
290 SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
291 SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
292 SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
293 SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
294 SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
295 SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
296 SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
297 SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
298 SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
299 SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
300 SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
301 SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
302 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
303 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
304 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
305 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
306 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
307 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
308 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
309 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
310 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
311 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
312 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
313 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
314 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
315 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
316 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
317 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
318 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
319 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
320 SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
321 SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
322 SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
323 SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
324 SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
325 SSMFIELD_ENTRY_TERM()
326};
327
328/** Saved state field descriptors for VMX nested hardware-virtualization
329 * VMCS. */
330static const SSMFIELD g_aVmxHwvirtVmcs[] =
331{
332 SSMFIELD_ENTRY( VMXVVMCS, u32VmcsRevId),
333 SSMFIELD_ENTRY( VMXVVMCS, enmVmxAbort),
334 SSMFIELD_ENTRY( VMXVVMCS, fVmcsState),
335 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au8Padding0),
336 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved0),
337
338 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, u16Reserved0),
339
340 SSMFIELD_ENTRY( VMXVVMCS, u32RoVmInstrError),
341 SSMFIELD_ENTRY( VMXVVMCS, u32RoExitReason),
342 SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntInfo),
343 SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntErrCode),
344 SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringInfo),
345 SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringErrCode),
346 SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrLen),
347 SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrInfo),
348 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32RoReserved2),
349
350 SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestPhysAddr),
351 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved1),
352
353 SSMFIELD_ENTRY( VMXVVMCS, u64RoExitQual),
354 SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRcx),
355 SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRsi),
356 SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRdi),
357 SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRip),
358 SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestLinearAddr),
359 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved5),
360
361 SSMFIELD_ENTRY( VMXVVMCS, u16Vpid),
362 SSMFIELD_ENTRY( VMXVVMCS, u16PostIntNotifyVector),
363 SSMFIELD_ENTRY( VMXVVMCS, u16EptpIndex),
364 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved0),
365
366 SSMFIELD_ENTRY( VMXVVMCS, u32PinCtls),
367 SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls),
368 SSMFIELD_ENTRY( VMXVVMCS, u32XcptBitmap),
369 SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMask),
370 SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMatch),
371 SSMFIELD_ENTRY( VMXVVMCS, u32Cr3TargetCount),
372 SSMFIELD_ENTRY( VMXVVMCS, u32ExitCtls),
373 SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrStoreCount),
374 SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrLoadCount),
375 SSMFIELD_ENTRY( VMXVVMCS, u32EntryCtls),
376 SSMFIELD_ENTRY( VMXVVMCS, u32EntryMsrLoadCount),
377 SSMFIELD_ENTRY( VMXVVMCS, u32EntryIntInfo),
378 SSMFIELD_ENTRY( VMXVVMCS, u32EntryXcptErrCode),
379 SSMFIELD_ENTRY( VMXVVMCS, u32EntryInstrLen),
380 SSMFIELD_ENTRY( VMXVVMCS, u32TprThreshold),
381 SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls2),
382 SSMFIELD_ENTRY( VMXVVMCS, u32PleGap),
383 SSMFIELD_ENTRY( VMXVVMCS, u32PleWindow),
384 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved1),
385
386 SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapA),
387 SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapB),
388 SSMFIELD_ENTRY( VMXVVMCS, u64AddrMsrBitmap),
389 SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrStore),
390 SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrLoad),
391 SSMFIELD_ENTRY( VMXVVMCS, u64AddrEntryMsrLoad),
392 SSMFIELD_ENTRY( VMXVVMCS, u64ExecVmcsPtr),
393 SSMFIELD_ENTRY( VMXVVMCS, u64AddrPml),
394 SSMFIELD_ENTRY( VMXVVMCS, u64TscOffset),
395 SSMFIELD_ENTRY( VMXVVMCS, u64AddrVirtApic),
396 SSMFIELD_ENTRY( VMXVVMCS, u64AddrApicAccess),
397 SSMFIELD_ENTRY( VMXVVMCS, u64AddrPostedIntDesc),
398 SSMFIELD_ENTRY( VMXVVMCS, u64VmFuncCtls),
399 SSMFIELD_ENTRY( VMXVVMCS, u64EptPtr),
400 SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap0),
401 SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap1),
402 SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap2),
403 SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap3),
404 SSMFIELD_ENTRY( VMXVVMCS, u64AddrEptpList),
405 SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmreadBitmap),
406 SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmwriteBitmap),
407 SSMFIELD_ENTRY( VMXVVMCS, u64AddrXcptVeInfo),
408 SSMFIELD_ENTRY( VMXVVMCS, u64XssExitBitmap),
409 SSMFIELD_ENTRY( VMXVVMCS, u64EnclsExitBitmap),
410 SSMFIELD_ENTRY( VMXVVMCS, u64SppTablePtr),
411 SSMFIELD_ENTRY( VMXVVMCS, u64TscMultiplier),
412 SSMFIELD_ENTRY_VER( VMXVVMCS, u64ProcCtls3, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
413 SSMFIELD_ENTRY_VER( VMXVVMCS, u64EnclvExitBitmap, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
414 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved0),
415
416 SSMFIELD_ENTRY( VMXVVMCS, u64Cr0Mask),
417 SSMFIELD_ENTRY( VMXVVMCS, u64Cr4Mask),
418 SSMFIELD_ENTRY( VMXVVMCS, u64Cr0ReadShadow),
419 SSMFIELD_ENTRY( VMXVVMCS, u64Cr4ReadShadow),
420 SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target0),
421 SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target1),
422 SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target2),
423 SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target3),
424 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved4),
425
426 SSMFIELD_ENTRY( VMXVVMCS, HostEs),
427 SSMFIELD_ENTRY( VMXVVMCS, HostCs),
428 SSMFIELD_ENTRY( VMXVVMCS, HostSs),
429 SSMFIELD_ENTRY( VMXVVMCS, HostDs),
430 SSMFIELD_ENTRY( VMXVVMCS, HostFs),
431 SSMFIELD_ENTRY( VMXVVMCS, HostGs),
432 SSMFIELD_ENTRY( VMXVVMCS, HostTr),
433 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved2),
434
435 SSMFIELD_ENTRY( VMXVVMCS, u32HostSysenterCs),
436 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved4),
437
438 SSMFIELD_ENTRY( VMXVVMCS, u64HostPatMsr),
439 SSMFIELD_ENTRY( VMXVVMCS, u64HostEferMsr),
440 SSMFIELD_ENTRY( VMXVVMCS, u64HostPerfGlobalCtlMsr),
441 SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
442 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved3),
443
444 SSMFIELD_ENTRY( VMXVVMCS, u64HostCr0),
445 SSMFIELD_ENTRY( VMXVVMCS, u64HostCr3),
446 SSMFIELD_ENTRY( VMXVVMCS, u64HostCr4),
447 SSMFIELD_ENTRY( VMXVVMCS, u64HostFsBase),
448 SSMFIELD_ENTRY( VMXVVMCS, u64HostGsBase),
449 SSMFIELD_ENTRY( VMXVVMCS, u64HostTrBase),
450 SSMFIELD_ENTRY( VMXVVMCS, u64HostGdtrBase),
451 SSMFIELD_ENTRY( VMXVVMCS, u64HostIdtrBase),
452 SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEsp),
453 SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEip),
454 SSMFIELD_ENTRY( VMXVVMCS, u64HostRsp),
455 SSMFIELD_ENTRY( VMXVVMCS, u64HostRip),
456 SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
457 SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
458 SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
459 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved7),
460
461 SSMFIELD_ENTRY( VMXVVMCS, GuestEs),
462 SSMFIELD_ENTRY( VMXVVMCS, GuestCs),
463 SSMFIELD_ENTRY( VMXVVMCS, GuestSs),
464 SSMFIELD_ENTRY( VMXVVMCS, GuestDs),
465 SSMFIELD_ENTRY( VMXVVMCS, GuestFs),
466 SSMFIELD_ENTRY( VMXVVMCS, GuestGs),
467 SSMFIELD_ENTRY( VMXVVMCS, GuestLdtr),
468 SSMFIELD_ENTRY( VMXVVMCS, GuestTr),
469 SSMFIELD_ENTRY( VMXVVMCS, u16GuestIntStatus),
470 SSMFIELD_ENTRY( VMXVVMCS, u16PmlIndex),
471 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved1),
472
473 SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsLimit),
474 SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsLimit),
475 SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsLimit),
476 SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsLimit),
477 SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsLimit),
478 SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsLimit),
479 SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrLimit),
480 SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrLimit),
481 SSMFIELD_ENTRY( VMXVVMCS, u32GuestGdtrLimit),
482 SSMFIELD_ENTRY( VMXVVMCS, u32GuestIdtrLimit),
483 SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsAttr),
484 SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsAttr),
485 SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsAttr),
486 SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsAttr),
487 SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsAttr),
488 SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsAttr),
489 SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrAttr),
490 SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrAttr),
491 SSMFIELD_ENTRY( VMXVVMCS, u32GuestIntrState),
492 SSMFIELD_ENTRY( VMXVVMCS, u32GuestActivityState),
493 SSMFIELD_ENTRY( VMXVVMCS, u32GuestSmBase),
494 SSMFIELD_ENTRY( VMXVVMCS, u32GuestSysenterCS),
495 SSMFIELD_ENTRY( VMXVVMCS, u32PreemptTimer),
496 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved3),
497
498 SSMFIELD_ENTRY( VMXVVMCS, u64VmcsLinkPtr),
499 SSMFIELD_ENTRY( VMXVVMCS, u64GuestDebugCtlMsr),
500 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPatMsr),
501 SSMFIELD_ENTRY( VMXVVMCS, u64GuestEferMsr),
502 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPerfGlobalCtlMsr),
503 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte0),
504 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte1),
505 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte2),
506 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte3),
507 SSMFIELD_ENTRY( VMXVVMCS, u64GuestBndcfgsMsr),
508 SSMFIELD_ENTRY( VMXVVMCS, u64GuestRtitCtlMsr),
509 SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
510 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved2),
511
512 SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr0),
513 SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr3),
514 SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr4),
515 SSMFIELD_ENTRY( VMXVVMCS, u64GuestEsBase),
516 SSMFIELD_ENTRY( VMXVVMCS, u64GuestCsBase),
517 SSMFIELD_ENTRY( VMXVVMCS, u64GuestSsBase),
518 SSMFIELD_ENTRY( VMXVVMCS, u64GuestDsBase),
519 SSMFIELD_ENTRY( VMXVVMCS, u64GuestFsBase),
520 SSMFIELD_ENTRY( VMXVVMCS, u64GuestGsBase),
521 SSMFIELD_ENTRY( VMXVVMCS, u64GuestLdtrBase),
522 SSMFIELD_ENTRY( VMXVVMCS, u64GuestTrBase),
523 SSMFIELD_ENTRY( VMXVVMCS, u64GuestGdtrBase),
524 SSMFIELD_ENTRY( VMXVVMCS, u64GuestIdtrBase),
525 SSMFIELD_ENTRY( VMXVVMCS, u64GuestDr7),
526 SSMFIELD_ENTRY( VMXVVMCS, u64GuestRsp),
527 SSMFIELD_ENTRY( VMXVVMCS, u64GuestRip),
528 SSMFIELD_ENTRY( VMXVVMCS, u64GuestRFlags),
529 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPendingDbgXcpts),
530 SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEsp),
531 SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEip),
532 SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
533 SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
534 SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
535 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved6),
536
537 SSMFIELD_ENTRY_TERM()
538};
539
540/** Saved state field descriptors for CPUMCTX. */
541static const SSMFIELD g_aCpumX87Fields[] =
542{
543 SSMFIELD_ENTRY( X86FXSTATE, FCW),
544 SSMFIELD_ENTRY( X86FXSTATE, FSW),
545 SSMFIELD_ENTRY( X86FXSTATE, FTW),
546 SSMFIELD_ENTRY( X86FXSTATE, FOP),
547 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
548 SSMFIELD_ENTRY( X86FXSTATE, CS),
549 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
550 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
551 SSMFIELD_ENTRY( X86FXSTATE, DS),
552 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
553 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
554 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
555 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
556 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
557 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
558 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
559 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
560 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
561 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
562 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
563 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
564 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
565 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
566 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
567 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
568 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
569 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
570 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
571 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
572 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
573 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
574 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
575 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
576 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
577 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
578 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
579 SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
580 SSMFIELD_ENTRY_TERM()
581};
582
583/** Saved state field descriptors for X86XSAVEHDR. */
584static const SSMFIELD g_aCpumXSaveHdrFields[] =
585{
586 SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
587 SSMFIELD_ENTRY_TERM()
588};
589
590/** Saved state field descriptors for X86XSAVEYMMHI. */
591static const SSMFIELD g_aCpumYmmHiFields[] =
592{
593 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
594 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
595 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
596 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
597 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
598 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
599 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
600 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
601 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
602 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
603 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
604 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
605 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
606 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
607 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
608 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
609 SSMFIELD_ENTRY_TERM()
610};
611
612/** Saved state field descriptors for X86XSAVEBNDREGS. */
613static const SSMFIELD g_aCpumBndRegsFields[] =
614{
615 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
616 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
617 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
618 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
619 SSMFIELD_ENTRY_TERM()
620};
621
622/** Saved state field descriptors for X86XSAVEBNDCFG. */
623static const SSMFIELD g_aCpumBndCfgFields[] =
624{
625 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
626 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
627 SSMFIELD_ENTRY_TERM()
628};
629
630#if 0 /** @todo */
631/** Saved state field descriptors for X86XSAVEOPMASK. */
632static const SSMFIELD g_aCpumOpmaskFields[] =
633{
634 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
635 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
636 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
637 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
638 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
639 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
640 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
641 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
642 SSMFIELD_ENTRY_TERM()
643};
644#endif
645
646/** Saved state field descriptors for X86XSAVEZMMHI256. */
647static const SSMFIELD g_aCpumZmmHi256Fields[] =
648{
649 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
650 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
651 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
652 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
653 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
654 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
655 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
656 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
657 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
658 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
659 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
660 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
661 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
662 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
663 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
664 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
665 SSMFIELD_ENTRY_TERM()
666};
667
668/** Saved state field descriptors for X86XSAVEZMM16HI. */
669static const SSMFIELD g_aCpumZmm16HiFields[] =
670{
671 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
672 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
673 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
674 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
675 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
676 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
677 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
678 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
679 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
680 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
681 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
682 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
683 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
684 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
685 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
686 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
687 SSMFIELD_ENTRY_TERM()
688};
689
690
691
692/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
693 * registeres changed. */
694static const SSMFIELD g_aCpumX87FieldsMem[] =
695{
696 SSMFIELD_ENTRY( X86FXSTATE, FCW),
697 SSMFIELD_ENTRY( X86FXSTATE, FSW),
698 SSMFIELD_ENTRY( X86FXSTATE, FTW),
699 SSMFIELD_ENTRY( X86FXSTATE, FOP),
700 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
701 SSMFIELD_ENTRY( X86FXSTATE, CS),
702 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
703 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
704 SSMFIELD_ENTRY( X86FXSTATE, DS),
705 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
706 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
707 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
708 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
709 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
710 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
711 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
712 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
713 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
714 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
715 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
716 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
717 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
718 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
719 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
720 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
721 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
722 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
723 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
724 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
725 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
726 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
727 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
728 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
729 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
730 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
731 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
732 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
733 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
734};
735
736/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
737 * registeres changed. */
738static const SSMFIELD g_aCpumCtxFieldsMem[] =
739{
740 SSMFIELD_ENTRY( CPUMCTX, rdi),
741 SSMFIELD_ENTRY( CPUMCTX, rsi),
742 SSMFIELD_ENTRY( CPUMCTX, rbp),
743 SSMFIELD_ENTRY( CPUMCTX, rax),
744 SSMFIELD_ENTRY( CPUMCTX, rbx),
745 SSMFIELD_ENTRY( CPUMCTX, rdx),
746 SSMFIELD_ENTRY( CPUMCTX, rcx),
747 SSMFIELD_ENTRY( CPUMCTX, rsp),
748 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
749 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
750 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
751 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
752 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
753 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
754 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
755 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
756 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
757 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
758 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
759 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
760 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
761 SSMFIELD_ENTRY( CPUMCTX, rflags),
762 SSMFIELD_ENTRY( CPUMCTX, rip),
763 SSMFIELD_ENTRY( CPUMCTX, r8),
764 SSMFIELD_ENTRY( CPUMCTX, r9),
765 SSMFIELD_ENTRY( CPUMCTX, r10),
766 SSMFIELD_ENTRY( CPUMCTX, r11),
767 SSMFIELD_ENTRY( CPUMCTX, r12),
768 SSMFIELD_ENTRY( CPUMCTX, r13),
769 SSMFIELD_ENTRY( CPUMCTX, r14),
770 SSMFIELD_ENTRY( CPUMCTX, r15),
771 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
772 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
773 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
774 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
775 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
776 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
777 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
778 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
779 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
780 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
781 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
782 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
783 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
784 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
785 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
786 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
787 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
788 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
789 SSMFIELD_ENTRY( CPUMCTX, cr0),
790 SSMFIELD_ENTRY( CPUMCTX, cr2),
791 SSMFIELD_ENTRY( CPUMCTX, cr3),
792 SSMFIELD_ENTRY( CPUMCTX, cr4),
793 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
794 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
795 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
796 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
797 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
798 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
799 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
800 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
801 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
802 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
803 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
804 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
805 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
806 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
807 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
808 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
809 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
810 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
811 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
812 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
813 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
814 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
815 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
816 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
817 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
818 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
819 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
820 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
821 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
822 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
823 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
824 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
825 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
826 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
827 SSMFIELD_ENTRY_TERM()
828};
829
830/** Saved state field descriptors for CPUMCTX_VER1_6. */
831static const SSMFIELD g_aCpumX87FieldsV16[] =
832{
833 SSMFIELD_ENTRY( X86FXSTATE, FCW),
834 SSMFIELD_ENTRY( X86FXSTATE, FSW),
835 SSMFIELD_ENTRY( X86FXSTATE, FTW),
836 SSMFIELD_ENTRY( X86FXSTATE, FOP),
837 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
838 SSMFIELD_ENTRY( X86FXSTATE, CS),
839 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
840 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
841 SSMFIELD_ENTRY( X86FXSTATE, DS),
842 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
843 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
844 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
845 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
846 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
847 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
848 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
849 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
850 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
851 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
852 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
853 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
854 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
855 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
856 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
857 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
858 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
859 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
860 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
861 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
862 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
863 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
864 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
865 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
866 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
867 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
868 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
869 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
870 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
871 SSMFIELD_ENTRY_TERM()
872};
873
874/** Saved state field descriptors for CPUMCTX_VER1_6. */
875static const SSMFIELD g_aCpumCtxFieldsV16[] =
876{
877 SSMFIELD_ENTRY( CPUMCTX, rdi),
878 SSMFIELD_ENTRY( CPUMCTX, rsi),
879 SSMFIELD_ENTRY( CPUMCTX, rbp),
880 SSMFIELD_ENTRY( CPUMCTX, rax),
881 SSMFIELD_ENTRY( CPUMCTX, rbx),
882 SSMFIELD_ENTRY( CPUMCTX, rdx),
883 SSMFIELD_ENTRY( CPUMCTX, rcx),
884 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
885 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
886 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
887 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
888 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
889 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
890 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
891 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
892 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
893 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
894 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
895 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
896 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
897 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
898 SSMFIELD_ENTRY( CPUMCTX, rflags),
899 SSMFIELD_ENTRY( CPUMCTX, rip),
900 SSMFIELD_ENTRY( CPUMCTX, r8),
901 SSMFIELD_ENTRY( CPUMCTX, r9),
902 SSMFIELD_ENTRY( CPUMCTX, r10),
903 SSMFIELD_ENTRY( CPUMCTX, r11),
904 SSMFIELD_ENTRY( CPUMCTX, r12),
905 SSMFIELD_ENTRY( CPUMCTX, r13),
906 SSMFIELD_ENTRY( CPUMCTX, r14),
907 SSMFIELD_ENTRY( CPUMCTX, r15),
908 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
909 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
910 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
911 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
912 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
913 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
914 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
915 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
916 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
917 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
918 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
919 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
920 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
921 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
922 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
923 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
924 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
925 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
926 SSMFIELD_ENTRY( CPUMCTX, cr0),
927 SSMFIELD_ENTRY( CPUMCTX, cr2),
928 SSMFIELD_ENTRY( CPUMCTX, cr3),
929 SSMFIELD_ENTRY( CPUMCTX, cr4),
930 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
931 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
932 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
933 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
934 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
935 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
936 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
937 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
938 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
939 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
940 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
941 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
942 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
943 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
944 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
945 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
946 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
947 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
948 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
949 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
950 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
951 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
952 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
953 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
954 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
955 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
956 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
957 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
958 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
959 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
960 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
961 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
962 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
963 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
964 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
965 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
966 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
967 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
968 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
969 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
970 SSMFIELD_ENTRY_TERM()
971};
972
973
974/**
975 * Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
976 *
977 * AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
978 * (last instruction pointer, last data pointer, last opcode) except when the ES
979 * bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
980 * clear these registers there is potential, local FPU leakage from a process
981 * using the FPU to another.
982 *
983 * See AMD Instruction Reference for FXSAVE, FXRSTOR.
984 *
985 * @param pVM The cross context VM structure.
986 */
987static void cpumR3CheckLeakyFpu(PVM pVM)
988{
989 uint32_t u32CpuVersion = ASMCpuId_EAX(1);
990 uint32_t const u32Family = u32CpuVersion >> 8;
991 if ( u32Family >= 6 /* K7 and higher */
992 && (ASMIsAmdCpu() || ASMIsHygonCpu()) )
993 {
994 uint32_t cExt = ASMCpuId_EAX(0x80000000);
995 if (ASMIsValidExtRange(cExt))
996 {
997 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
998 if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
999 {
1000 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1001 {
1002 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1003 pVCpu->cpum.s.fUseFlags |= CPUM_USE_FFXSR_LEAKY;
1004 }
1005 Log(("CPUM: Host CPU has leaky fxsave/fxrstor behaviour\n"));
1006 }
1007 }
1008 }
1009}
1010
1011
1012/**
1013 * Initialize SVM hardware virtualization state (used to allocate it).
1014 *
1015 * @param pVM The cross context VM structure.
1016 */
1017static void cpumR3InitSvmHwVirtState(PVM pVM)
1018{
1019 Assert(pVM->cpum.s.GuestFeatures.fSvm);
1020
1021 LogRel(("CPUM: AMD-V nested-guest init\n"));
1022 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1023 {
1024 PVMCPU pVCpu = pVM->apCpusR3[i];
1025 pVCpu->cpum.s.Guest.hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
1026
1027 AssertCompile(SVM_VMCB_PAGES * X86_PAGE_SIZE == sizeof(pVCpu->cpum.s.Guest.hwvirt.svm.Vmcb));
1028 AssertCompile(SVM_MSRPM_PAGES * X86_PAGE_SIZE == sizeof(pVCpu->cpum.s.Guest.hwvirt.svm.abMsrBitmap));
1029 AssertCompile(SVM_IOPM_PAGES * X86_PAGE_SIZE == sizeof(pVCpu->cpum.s.Guest.hwvirt.svm.abIoBitmap));
1030 }
1031}
1032
1033
1034/**
1035 * Resets per-VCPU SVM hardware virtualization state.
1036 *
1037 * @param pVCpu The cross context virtual CPU structure.
1038 */
1039DECLINLINE(void) cpumR3ResetSvmHwVirtState(PVMCPU pVCpu)
1040{
1041 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1042 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1043
1044 RT_ZERO(pCtx->hwvirt.svm.Vmcb);
1045 pCtx->hwvirt.svm.uMsrHSavePa = 0;
1046 pCtx->hwvirt.svm.uPrevPauseTick = 0;
1047}
1048
1049
1050/**
1051 * Allocates memory for the VMX hardware virtualization state.
1052 *
1053 * @param pVM The cross context VM structure.
1054 */
1055static void cpumR3InitVmxHwVirtState(PVM pVM)
1056{
1057 LogRel(("CPUM: VT-x nested-guest init\n"));
1058 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1059 {
1060 PVMCPU pVCpu = pVM->apCpusR3[i];
1061 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1062
1063 pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
1064
1065 AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_PAGES * X86_PAGE_SIZE);
1066 AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_SIZE);
1067 AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_PAGES * X86_PAGE_SIZE);
1068 AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_SIZE);
1069 AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1070 AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1071 AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1072 AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1073 AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1074 AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1075 AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1076 AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_SIZE);
1077 AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1078 AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1079 AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_PAGES * X86_PAGE_SIZE);
1080 AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_SIZE);
1081 AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == (VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES) * X86_PAGE_SIZE);
1082 AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
1083 AssertCompile(sizeof(pCtx->hwvirt.vmx.abVirtApicPage) == VMX_V_VIRT_APIC_PAGES * X86_PAGE_SIZE);
1084 AssertCompile(sizeof(pCtx->hwvirt.vmx.abVirtApicPage) == VMX_V_VIRT_APIC_SIZE);
1085
1086 /*
1087 * Zero out all allocated pages (should compress well for saved-state).
1088 */
1089 /** @todo r=bird: this is and always was unnecessary - they are already zeroed. */
1090 RT_ZERO(pCtx->hwvirt.vmx.Vmcs);
1091 RT_ZERO(pCtx->hwvirt.vmx.ShadowVmcs);
1092 RT_ZERO(pCtx->hwvirt.vmx.abVmreadBitmap);
1093 RT_ZERO(pCtx->hwvirt.vmx.abVmwriteBitmap);
1094 RT_ZERO(pCtx->hwvirt.vmx.aEntryMsrLoadArea);
1095 RT_ZERO(pCtx->hwvirt.vmx.aExitMsrStoreArea);
1096 RT_ZERO(pCtx->hwvirt.vmx.aExitMsrLoadArea);
1097 RT_ZERO(pCtx->hwvirt.vmx.abMsrBitmap);
1098 RT_ZERO(pCtx->hwvirt.vmx.abIoBitmap);
1099 RT_ZERO(pCtx->hwvirt.vmx.abVirtApicPage);
1100 }
1101}
1102
1103
1104/**
1105 * Resets per-VCPU VMX hardware virtualization state.
1106 *
1107 * @param pVCpu The cross context virtual CPU structure.
1108 */
1109DECLINLINE(void) cpumR3ResetVmxHwVirtState(PVMCPU pVCpu)
1110{
1111 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1112 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1113
1114 RT_ZERO(pCtx->hwvirt.vmx.Vmcs);
1115 RT_ZERO(pCtx->hwvirt.vmx.ShadowVmcs);
1116 pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1117 pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1118 pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1119 pCtx->hwvirt.vmx.fInVmxRootMode = false;
1120 pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1121 /* Don't reset diagnostics here. */
1122
1123 /* Stop any VMX-preemption timer. */
1124 CPUMStopGuestVmxPremptTimer(pVCpu);
1125
1126 /* Clear all nested-guest FFs. */
1127 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
1128}
1129
1130
1131/**
1132 * Displays the host and guest VMX features.
1133 *
1134 * @param pVM The cross context VM structure.
1135 * @param pHlp The info helper functions.
1136 * @param pszArgs "terse", "default" or "verbose".
1137 */
1138DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1139{
1140 RT_NOREF(pszArgs);
1141 PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
1142 PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
1143 if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
1144 || pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA
1145 || pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_SHANGHAI)
1146 {
1147#define VMXFEATDUMP(a_szDesc, a_Var) \
1148 pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
1149
1150 pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
1151 pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1152 VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
1153 /* Basic. */
1154 VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
1155
1156 /* Pin-based controls. */
1157 VMXFEATDUMP("ExtIntExit - External interrupt exiting ", fVmxExtIntExit);
1158 VMXFEATDUMP("NmiExit - NMI exiting ", fVmxNmiExit);
1159 VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
1160 VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
1161 VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
1162
1163 /* Processor-based controls. */
1164 VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
1165 VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
1166 VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
1167 VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
1168 VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
1169 VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
1170 VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
1171 VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1172 VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1173 VMXFEATDUMP("TertiaryExecCtls - Activate tertiary controls ", fVmxTertiaryExecCtls);
1174 VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1175 VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1176 VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1177 VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1178 VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1179 VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1180 VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1181 VMXFEATDUMP("MonitorTrapFlag - Monitor Trap Flag ", fVmxMonitorTrapFlag);
1182 VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1183 VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1184 VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1185 VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1186
1187 /* Secondary processor-based controls. */
1188 VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1189 VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1190 VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1191 VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1192 VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
1193 VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1194 VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1195 VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1196 VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1197 VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1198 VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1199 VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1200 VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1201 VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1202 VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1203 VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1204 VMXFEATDUMP("PML - Page-Modification Log (PML) ", fVmxPml);
1205 VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1206 VMXFEATDUMP("ConcealVmxFromPt - Conceal VMX from Processor Trace ", fVmxConcealVmxFromPt);
1207 VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1208 VMXFEATDUMP("ModeBasedExecuteEpt - Mode-based execute permissions ", fVmxModeBasedExecuteEpt);
1209 VMXFEATDUMP("SppEpt - Sub-page page write permissions for EPT ", fVmxSppEpt);
1210 VMXFEATDUMP("PtEpt - Processor Trace address' translatable by EPT ", fVmxPtEpt);
1211 VMXFEATDUMP("UseTscScaling - Use TSC scaling ", fVmxUseTscScaling);
1212 VMXFEATDUMP("UserWaitPause - Enable TPAUSE, UMONITOR and UMWAIT ", fVmxUserWaitPause);
1213 VMXFEATDUMP("EnclvExit - ENCLV exiting ", fVmxEnclvExit);
1214
1215 /* Tertiary processor-based controls. */
1216 VMXFEATDUMP("LoadIwKeyExit - LOADIWKEY exiting ", fVmxLoadIwKeyExit);
1217
1218 /* VM-entry controls. */
1219 VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1220 VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1221 VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER MSR on VM-entry ", fVmxEntryLoadEferMsr);
1222 VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT MSR on VM-entry ", fVmxEntryLoadPatMsr);
1223
1224 /* VM-exit controls. */
1225 VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1226 VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1227 VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1228 VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT MSR on VM-exit ", fVmxExitSavePatMsr);
1229 VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT MSR on VM-exit ", fVmxExitLoadPatMsr);
1230 VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER MSR on VM-exit ", fVmxExitSaveEferMsr);
1231 VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER MSR on VM-exit ", fVmxExitLoadEferMsr);
1232 VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1233
1234 /* Miscellaneous data. */
1235 VMXFEATDUMP("ExitSaveEferLma - Save IA32_EFER.LMA on VM-exit ", fVmxExitSaveEferLma);
1236 VMXFEATDUMP("IntelPt - Intel PT (Processor Trace) in VMX operation ", fVmxPt);
1237 VMXFEATDUMP("VmwriteAll - VMWRITE to any supported VMCS field ", fVmxVmwriteAll);
1238 VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1239#undef VMXFEATDUMP
1240 }
1241 else
1242 pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1243}
1244
1245
1246/**
1247 * Checks whether nested-guest execution using hardware-assisted VMX (e.g, using HM
1248 * or NEM) is allowed.
1249 *
1250 * @returns @c true if hardware-assisted nested-guest execution is allowed, @c false
1251 * otherwise.
1252 * @param pVM The cross context VM structure.
1253 */
1254static bool cpumR3IsHwAssistNstGstExecAllowed(PVM pVM)
1255{
1256 AssertMsg(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET, ("Calling this function too early!\n"));
1257#ifndef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
1258 if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT
1259 || pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1260 return true;
1261#else
1262 NOREF(pVM);
1263#endif
1264 return false;
1265}
1266
1267
1268/**
1269 * Initializes the VMX guest MSRs from guest CPU features based on the host MSRs.
1270 *
1271 * @param pVM The cross context VM structure.
1272 * @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1273 * and no hardware-assisted nested-guest execution is
1274 * possible for this VM.
1275 * @param pGuestFeatures The guest features to use (only VMX features are
1276 * accessed).
1277 * @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1278 *
1279 * @remarks This function ASSUMES the VMX guest-features are already exploded!
1280 */
1281static void cpumR3InitVmxGuestMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PCCPUMFEATURES pGuestFeatures, PVMXMSRS pGuestVmxMsrs)
1282{
1283 bool const fIsNstGstHwExecAllowed = cpumR3IsHwAssistNstGstExecAllowed(pVM);
1284
1285 Assert(!fIsNstGstHwExecAllowed || pHostVmxMsrs);
1286 Assert(pGuestFeatures->fVmx);
1287
1288 /*
1289 * We don't support the following MSRs yet:
1290 * - True Pin-based VM-execution controls.
1291 * - True Processor-based VM-execution controls.
1292 * - True VM-entry VM-execution controls.
1293 * - True VM-exit VM-execution controls.
1294 */
1295
1296 /* Basic information. */
1297 {
1298 uint64_t const u64Basic = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1299 | RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1300 | RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, !pGuestFeatures->fLongMode )
1301 | RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1302 | RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1303 | RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1304 | RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, 0 );
1305 pGuestVmxMsrs->u64Basic = u64Basic;
1306 }
1307
1308 /* Pin-based VM-execution controls. */
1309 {
1310 uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1311 | (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1312 | (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1313 | (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1314 | (pGuestFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1315 uint32_t const fAllowed0 = VMX_PIN_CTLS_DEFAULT1;
1316 uint32_t const fAllowed1 = fFeatures | VMX_PIN_CTLS_DEFAULT1;
1317 AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n",
1318 fAllowed0, fAllowed1, fFeatures));
1319 pGuestVmxMsrs->PinCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1320 }
1321
1322 /* Processor-based VM-execution controls. */
1323 {
1324 uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1325 | (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1326 | (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1327 | (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1328 | (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1329 | (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1330 | (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1331 | (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1332 | (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1333 | (pGuestFeatures->fVmxTertiaryExecCtls << VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_SHIFT )
1334 | (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1335 | (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1336 | (pGuestFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1337 | (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1338 | (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1339 | (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1340 | (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1341 | (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1342 | (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1343 | (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1344 | (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1345 | (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1346 uint32_t const fAllowed0 = VMX_PROC_CTLS_DEFAULT1;
1347 uint32_t const fAllowed1 = fFeatures | VMX_PROC_CTLS_DEFAULT1;
1348 AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1349 fAllowed1, fFeatures));
1350 pGuestVmxMsrs->ProcCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1351 }
1352
1353 /* Secondary processor-based VM-execution controls. */
1354 if (pGuestFeatures->fVmxSecondaryExecCtls)
1355 {
1356 uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1357 | (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1358 | (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1359 | (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1360 | (pGuestFeatures->fVmxVirtX2ApicMode << VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT )
1361 | (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1362 | (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1363 | (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT )
1364 | (pGuestFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1365 | (pGuestFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1366 | (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1367 | (pGuestFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1368 | (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1369 | (pGuestFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1370 | (pGuestFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1371 | (pGuestFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1372 | (pGuestFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1373 | (pGuestFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1374 | (pGuestFeatures->fVmxConcealVmxFromPt << VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT)
1375 | (pGuestFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1376 | (pGuestFeatures->fVmxModeBasedExecuteEpt << VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT)
1377 | (pGuestFeatures->fVmxSppEpt << VMX_BF_PROC_CTLS2_SPP_EPT_SHIFT )
1378 | (pGuestFeatures->fVmxPtEpt << VMX_BF_PROC_CTLS2_PT_EPT_SHIFT )
1379 | (pGuestFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT )
1380 | (pGuestFeatures->fVmxUserWaitPause << VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT )
1381 | (pGuestFeatures->fVmxEnclvExit << VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT );
1382 uint32_t const fAllowed0 = 0;
1383 uint32_t const fAllowed1 = fFeatures;
1384 pGuestVmxMsrs->ProcCtls2.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1385 }
1386
1387 /* Tertiary processor-based VM-execution controls. */
1388 if (pGuestFeatures->fVmxTertiaryExecCtls)
1389 {
1390 pGuestVmxMsrs->u64ProcCtls3 = (pGuestFeatures->fVmxLoadIwKeyExit << VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_SHIFT);
1391 }
1392
1393 /* VM-exit controls. */
1394 {
1395 uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1396 | (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1397 | (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1398 | (pGuestFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1399 | (pGuestFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1400 | (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1401 | (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1402 | (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT );
1403 /* Set the default1 class bits. See Intel spec. A.4 "VM-exit Controls". */
1404 uint32_t const fAllowed0 = VMX_EXIT_CTLS_DEFAULT1;
1405 uint32_t const fAllowed1 = fFeatures | VMX_EXIT_CTLS_DEFAULT1;
1406 AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1407 fAllowed1, fFeatures));
1408 pGuestVmxMsrs->ExitCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1409 }
1410
1411 /* VM-entry controls. */
1412 {
1413 uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1414 | (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1415 | (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1416 | (pGuestFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1417 uint32_t const fAllowed0 = VMX_ENTRY_CTLS_DEFAULT1;
1418 uint32_t const fAllowed1 = fFeatures | VMX_ENTRY_CTLS_DEFAULT1;
1419 AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed0=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1420 fAllowed1, fFeatures));
1421 pGuestVmxMsrs->EntryCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1422 }
1423
1424 /* Miscellaneous data. */
1425 {
1426 uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Misc : 0;
1427
1428 uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_AUTOMSR_COUNT_MAX);
1429 uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK;
1430 pGuestVmxMsrs->u64Misc = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1431 | RT_BF_MAKE(VMX_BF_MISC_EXIT_SAVE_EFER_LMA, pGuestFeatures->fVmxExitSaveEferLma )
1432 | RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState )
1433 | RT_BF_MAKE(VMX_BF_MISC_INTEL_PT, pGuestFeatures->fVmxPt )
1434 | RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1435 | RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1436 | RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1437 | RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1438 | RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pGuestFeatures->fVmxVmwriteAll )
1439 | RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pGuestFeatures->fVmxEntryInjectSoftInt)
1440 | RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1441 }
1442
1443 /* CR0 Fixed-0. */
1444 pGuestVmxMsrs->u64Cr0Fixed0 = VMX_V_CR0_FIXED0;
1445
1446 /* CR0 Fixed-1. */
1447 {
1448 /*
1449 * All CPUs I've looked at so far report CR0 fixed-1 bits as 0xffffffff.
1450 * This is different from CR4 fixed-1 bits which are reported as per the
1451 * CPU features and/or micro-architecture/generation. Why? Ask Intel.
1452 */
1453 uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr0Fixed1 : 0xffffffff;
1454 pGuestVmxMsrs->u64Cr0Fixed1 = uHostMsr | pGuestVmxMsrs->u64Cr0Fixed0; /* Make sure the CR0 MB1 bits are not clear. */
1455 }
1456
1457 /* CR4 Fixed-0. */
1458 pGuestVmxMsrs->u64Cr4Fixed0 = VMX_V_CR4_FIXED0;
1459
1460 /* CR4 Fixed-1. */
1461 {
1462 uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr4Fixed1 : CPUMGetGuestCR4ValidMask(pVM);
1463 pGuestVmxMsrs->u64Cr4Fixed1 = uHostMsr | pGuestVmxMsrs->u64Cr4Fixed0; /* Make sure the CR4 MB1 bits are not clear. */
1464 }
1465
1466 /* VMCS Enumeration. */
1467 pGuestVmxMsrs->u64VmcsEnum = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1468
1469 /* VPID and EPT Capabilities. */
1470 if (pGuestFeatures->fVmxEpt)
1471 {
1472 /*
1473 * INVVPID instruction always causes a VM-exit unconditionally, so we are free to fake
1474 * and emulate any INVVPID flush type. However, it only makes sense to expose the types
1475 * when INVVPID instruction is supported just to be more compatible with guest
1476 * hypervisors that may make assumptions by only looking at this MSR even though they
1477 * are technically supposed to refer to VMX_PROC_CTLS2_VPID first.
1478 *
1479 * See Intel spec. 25.1.2 "Instructions That Cause VM Exits Unconditionally".
1480 * See Intel spec. 30.3 "VMX Instructions".
1481 */
1482 uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64EptVpidCaps : UINT64_MAX;
1483 uint8_t const fVpid = pGuestFeatures->fVmxVpid;
1484
1485 uint8_t const fExecOnly = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EXEC_ONLY);
1486 uint8_t const fPml4 = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1487 uint8_t const fMemTypeUc = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC);
1488 uint8_t const fMemTypeWb = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB);
1489 uint8_t const f2MPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDE_2M);
1490 uint8_t const f1GPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDPTE_1G);
1491 uint8_t const fInvept = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT);
1492 /** @todo Nested VMX: Support accessed/dirty bits, see @bugref{10092#c25}. */
1493 /* uint8_t const fAccessDirty = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY); */
1494 uint8_t const fEptSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
1495 uint8_t const fEptAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
1496 uint8_t const fVpidIndiv = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1497 uint8_t const fVpidSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
1498 uint8_t const fVpidAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
1499 uint8_t const fVpidSingleGlobal = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
1500 pGuestVmxMsrs->u64EptVpidCaps = RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_EXEC_ONLY, fExecOnly)
1501 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4, fPml4)
1502 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_UC, fMemTypeUc)
1503 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_WB, fMemTypeWb)
1504 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDE_2M, f2MPage)
1505 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDPTE_1G, f1GPage)
1506 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT, fInvept)
1507 //| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY, 0)
1508 //| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION, 0)
1509 //| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK, 0)
1510 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX, fEptSingle)
1511 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX, fEptAll)
1512 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID, fVpid)
1513 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR, fVpid & fVpidIndiv)
1514 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX, fVpid & fVpidSingle)
1515 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX, fVpid & fVpidAll)
1516 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS, fVpid & fVpidSingleGlobal);
1517 }
1518
1519 /* VM Functions. */
1520 if (pGuestFeatures->fVmxVmFunc)
1521 pGuestVmxMsrs->u64VmFunc = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1522}
1523
1524
1525/**
1526 * Checks whether the given guest CPU VMX features are compatible with the provided
1527 * base features.
1528 *
1529 * @returns @c true if compatible, @c false otherwise.
1530 * @param pVM The cross context VM structure.
1531 * @param pBase The base VMX CPU features.
1532 * @param pGst The guest VMX CPU features.
1533 *
1534 * @remarks Only VMX feature bits are examined.
1535 */
1536static bool cpumR3AreVmxCpuFeaturesCompatible(PVM pVM, PCCPUMFEATURES pBase, PCCPUMFEATURES pGst)
1537{
1538 if (!cpumR3IsHwAssistNstGstExecAllowed(pVM))
1539 return false;
1540
1541#define CPUM_VMX_FEAT_SHIFT(a_pFeat, a_FeatName, a_cShift) ((uint64_t)(a_pFeat->a_FeatName) << (a_cShift))
1542#define CPUM_VMX_MAKE_FEATURES_1(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInsOutInfo , 0) \
1543 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExtIntExit , 1) \
1544 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiExit , 2) \
1545 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtNmi , 3) \
1546 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPreemptTimer , 4) \
1547 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPostedInt , 5) \
1548 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIntWindowExit , 6) \
1549 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTscOffsetting , 7) \
1550 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHltExit , 8) \
1551 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvlpgExit , 9) \
1552 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMwaitExit , 10) \
1553 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdpmcExit , 12) \
1554 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscExit , 13) \
1555 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3LoadExit , 14) \
1556 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3StoreExit , 15) \
1557 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTertiaryExecCtls , 16) \
1558 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8LoadExit , 17) \
1559 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8StoreExit , 18) \
1560 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTprShadow , 19) \
1561 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiWindowExit , 20) \
1562 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMovDRxExit , 21) \
1563 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUncondIoExit , 22) \
1564 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseIoBitmaps , 23) \
1565 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorTrapFlag , 24) \
1566 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseMsrBitmaps , 25) \
1567 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorExit , 26) \
1568 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseExit , 27) \
1569 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSecondaryExecCtls , 28) \
1570 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtApicAccess , 29) \
1571 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEpt , 30) \
1572 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxDescTableExit , 31) \
1573 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscp , 32) \
1574 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtX2ApicMode , 33) \
1575 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVpid , 34) \
1576 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxWbinvdExit , 35) \
1577 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUnrestrictedGuest , 36) \
1578 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxApicRegVirt , 37) \
1579 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtIntDelivery , 38) \
1580 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseLoopExit , 39) \
1581 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdrandExit , 40) \
1582 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvpcid , 41) \
1583 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmFunc , 42) \
1584 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmcsShadowing , 43) \
1585 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdseedExit , 44) \
1586 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPml , 45) \
1587 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEptXcptVe , 46) \
1588 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxConcealVmxFromPt , 47) \
1589 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxXsavesXrstors , 48) \
1590 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxModeBasedExecuteEpt, 49) \
1591 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSppEpt , 50) \
1592 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPtEpt , 51) \
1593 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTscScaling , 52) \
1594 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUserWaitPause , 53) \
1595 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEnclvExit , 54) \
1596 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxLoadIwKeyExit , 55) \
1597 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadDebugCtls , 56) \
1598 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIa32eModeGuest , 57) \
1599 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadEferMsr , 58) \
1600 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadPatMsr , 59) \
1601 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveDebugCtls , 60) \
1602 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHostAddrSpaceSize , 61) \
1603 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitAckExtInt , 62) \
1604 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSavePatMsr , 63))
1605
1606#define CPUM_VMX_MAKE_FEATURES_2(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadPatMsr , 0) \
1607 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferMsr , 1) \
1608 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadEferMsr , 2) \
1609 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSavePreemptTimer , 3) \
1610 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferLma , 4) \
1611 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPt , 5) \
1612 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmwriteAll , 6) \
1613 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryInjectSoftInt , 7))
1614
1615 /* Check first set of feature bits. */
1616 {
1617 uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_1(pBase);
1618 uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_1(pGst);
1619 if ((fBase | fGst) != fBase)
1620 {
1621 uint64_t const fDiff = fBase ^ fGst;
1622 LogRel(("CPUM: VMX features (1) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1623 fBase, fGst, fDiff));
1624 return false;
1625 }
1626 }
1627
1628 /* Check second set of feature bits. */
1629 {
1630 uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_2(pBase);
1631 uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_2(pGst);
1632 if ((fBase | fGst) != fBase)
1633 {
1634 uint64_t const fDiff = fBase ^ fGst;
1635 LogRel(("CPUM: VMX features (2) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1636 fBase, fGst, fDiff));
1637 return false;
1638 }
1639 }
1640#undef CPUM_VMX_FEAT_SHIFT
1641#undef CPUM_VMX_MAKE_FEATURES_1
1642#undef CPUM_VMX_MAKE_FEATURES_2
1643
1644 return true;
1645}
1646
1647
1648/**
1649 * Initializes VMX guest features and MSRs.
1650 *
1651 * @param pVM The cross context VM structure.
1652 * @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1653 * and no hardware-assisted nested-guest execution is
1654 * possible for this VM.
1655 * @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1656 */
1657void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs)
1658{
1659 Assert(pVM);
1660 Assert(pGuestVmxMsrs);
1661
1662 /*
1663 * While it would be nice to check this earlier while initializing fNestedVmxEpt
1664 * but we would not have enumearted host features then, so do it at least now.
1665 */
1666 if ( !pVM->cpum.s.HostFeatures.fNoExecute
1667 && pVM->cpum.s.fNestedVmxEpt)
1668 {
1669 LogRel(("CPUM: Warning! EPT not exposed to the guest since NX isn't available on the host.\n"));
1670 pVM->cpum.s.fNestedVmxEpt = false;
1671 pVM->cpum.s.fNestedVmxUnrestrictedGuest = false;
1672 }
1673
1674 /*
1675 * Initialize the set of VMX features we emulate.
1676 *
1677 * Note! Some bits might be reported as 1 always if they fall under the
1678 * default1 class bits (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1679 */
1680 CPUMFEATURES EmuFeat;
1681 RT_ZERO(EmuFeat);
1682 EmuFeat.fVmx = 1;
1683 EmuFeat.fVmxInsOutInfo = 1;
1684 EmuFeat.fVmxExtIntExit = 1;
1685 EmuFeat.fVmxNmiExit = 1;
1686 EmuFeat.fVmxVirtNmi = 1;
1687 EmuFeat.fVmxPreemptTimer = pVM->cpum.s.fNestedVmxPreemptTimer;
1688 EmuFeat.fVmxPostedInt = 0;
1689 EmuFeat.fVmxIntWindowExit = 1;
1690 EmuFeat.fVmxTscOffsetting = 1;
1691 EmuFeat.fVmxHltExit = 1;
1692 EmuFeat.fVmxInvlpgExit = 1;
1693 EmuFeat.fVmxMwaitExit = 1;
1694 EmuFeat.fVmxRdpmcExit = 1;
1695 EmuFeat.fVmxRdtscExit = 1;
1696 EmuFeat.fVmxCr3LoadExit = 1;
1697 EmuFeat.fVmxCr3StoreExit = 1;
1698 EmuFeat.fVmxTertiaryExecCtls = 0;
1699 EmuFeat.fVmxCr8LoadExit = 1;
1700 EmuFeat.fVmxCr8StoreExit = 1;
1701 EmuFeat.fVmxUseTprShadow = 1;
1702 EmuFeat.fVmxNmiWindowExit = 0;
1703 EmuFeat.fVmxMovDRxExit = 1;
1704 EmuFeat.fVmxUncondIoExit = 1;
1705 EmuFeat.fVmxUseIoBitmaps = 1;
1706 EmuFeat.fVmxMonitorTrapFlag = 0;
1707 EmuFeat.fVmxUseMsrBitmaps = 1;
1708 EmuFeat.fVmxMonitorExit = 1;
1709 EmuFeat.fVmxPauseExit = 1;
1710 EmuFeat.fVmxSecondaryExecCtls = 1;
1711 EmuFeat.fVmxVirtApicAccess = 1;
1712 EmuFeat.fVmxEpt = pVM->cpum.s.fNestedVmxEpt;
1713 EmuFeat.fVmxDescTableExit = 1;
1714 EmuFeat.fVmxRdtscp = 1;
1715 EmuFeat.fVmxVirtX2ApicMode = 0;
1716 EmuFeat.fVmxVpid = 0; /** @todo Consider enabling this when EPT works. */
1717 EmuFeat.fVmxWbinvdExit = 1;
1718 EmuFeat.fVmxUnrestrictedGuest = pVM->cpum.s.fNestedVmxUnrestrictedGuest;
1719 EmuFeat.fVmxApicRegVirt = 0;
1720 EmuFeat.fVmxVirtIntDelivery = 0;
1721 EmuFeat.fVmxPauseLoopExit = 0;
1722 EmuFeat.fVmxRdrandExit = 0;
1723 EmuFeat.fVmxInvpcid = 1;
1724 EmuFeat.fVmxVmFunc = 0;
1725 EmuFeat.fVmxVmcsShadowing = 0;
1726 EmuFeat.fVmxRdseedExit = 0;
1727 EmuFeat.fVmxPml = 0;
1728 EmuFeat.fVmxEptXcptVe = 0;
1729 EmuFeat.fVmxConcealVmxFromPt = 0;
1730 EmuFeat.fVmxXsavesXrstors = 0;
1731 EmuFeat.fVmxModeBasedExecuteEpt = 0;
1732 EmuFeat.fVmxSppEpt = 0;
1733 EmuFeat.fVmxPtEpt = 0;
1734 EmuFeat.fVmxUseTscScaling = 0;
1735 EmuFeat.fVmxUserWaitPause = 0;
1736 EmuFeat.fVmxEnclvExit = 0;
1737 EmuFeat.fVmxLoadIwKeyExit = 0;
1738 EmuFeat.fVmxEntryLoadDebugCtls = 1;
1739 EmuFeat.fVmxIa32eModeGuest = 1;
1740 EmuFeat.fVmxEntryLoadEferMsr = 1;
1741 EmuFeat.fVmxEntryLoadPatMsr = 0;
1742 EmuFeat.fVmxExitSaveDebugCtls = 1;
1743 EmuFeat.fVmxHostAddrSpaceSize = 1;
1744 EmuFeat.fVmxExitAckExtInt = 1;
1745 EmuFeat.fVmxExitSavePatMsr = 0;
1746 EmuFeat.fVmxExitLoadPatMsr = 0;
1747 EmuFeat.fVmxExitSaveEferMsr = 1;
1748 EmuFeat.fVmxExitLoadEferMsr = 1;
1749 EmuFeat.fVmxSavePreemptTimer = 0; /* Cannot be enabled if VMX-preemption timer is disabled. */
1750 EmuFeat.fVmxExitSaveEferLma = 1; /* Cannot be disabled if unrestricted guest is enabled. */
1751 EmuFeat.fVmxPt = 0;
1752 EmuFeat.fVmxVmwriteAll = 0; /** @todo NSTVMX: enable this when nested VMCS shadowing is enabled. */
1753 EmuFeat.fVmxEntryInjectSoftInt = 1;
1754
1755 /*
1756 * Merge guest features.
1757 *
1758 * When hardware-assisted VMX may be used, any feature we emulate must also be supported
1759 * by the hardware, hence we merge our emulated features with the host features below.
1760 */
1761 PCCPUMFEATURES pBaseFeat = cpumR3IsHwAssistNstGstExecAllowed(pVM) ? &pVM->cpum.s.HostFeatures : &EmuFeat;
1762 PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1763 Assert(pBaseFeat->fVmx);
1764 pGuestFeat->fVmxInsOutInfo = (pBaseFeat->fVmxInsOutInfo & EmuFeat.fVmxInsOutInfo );
1765 pGuestFeat->fVmxExtIntExit = (pBaseFeat->fVmxExtIntExit & EmuFeat.fVmxExtIntExit );
1766 pGuestFeat->fVmxNmiExit = (pBaseFeat->fVmxNmiExit & EmuFeat.fVmxNmiExit );
1767 pGuestFeat->fVmxVirtNmi = (pBaseFeat->fVmxVirtNmi & EmuFeat.fVmxVirtNmi );
1768 pGuestFeat->fVmxPreemptTimer = (pBaseFeat->fVmxPreemptTimer & EmuFeat.fVmxPreemptTimer );
1769 pGuestFeat->fVmxPostedInt = (pBaseFeat->fVmxPostedInt & EmuFeat.fVmxPostedInt );
1770 pGuestFeat->fVmxIntWindowExit = (pBaseFeat->fVmxIntWindowExit & EmuFeat.fVmxIntWindowExit );
1771 pGuestFeat->fVmxTscOffsetting = (pBaseFeat->fVmxTscOffsetting & EmuFeat.fVmxTscOffsetting );
1772 pGuestFeat->fVmxHltExit = (pBaseFeat->fVmxHltExit & EmuFeat.fVmxHltExit );
1773 pGuestFeat->fVmxInvlpgExit = (pBaseFeat->fVmxInvlpgExit & EmuFeat.fVmxInvlpgExit );
1774 pGuestFeat->fVmxMwaitExit = (pBaseFeat->fVmxMwaitExit & EmuFeat.fVmxMwaitExit );
1775 pGuestFeat->fVmxRdpmcExit = (pBaseFeat->fVmxRdpmcExit & EmuFeat.fVmxRdpmcExit );
1776 pGuestFeat->fVmxRdtscExit = (pBaseFeat->fVmxRdtscExit & EmuFeat.fVmxRdtscExit );
1777 pGuestFeat->fVmxCr3LoadExit = (pBaseFeat->fVmxCr3LoadExit & EmuFeat.fVmxCr3LoadExit );
1778 pGuestFeat->fVmxCr3StoreExit = (pBaseFeat->fVmxCr3StoreExit & EmuFeat.fVmxCr3StoreExit );
1779 pGuestFeat->fVmxTertiaryExecCtls = (pBaseFeat->fVmxTertiaryExecCtls & EmuFeat.fVmxTertiaryExecCtls );
1780 pGuestFeat->fVmxCr8LoadExit = (pBaseFeat->fVmxCr8LoadExit & EmuFeat.fVmxCr8LoadExit );
1781 pGuestFeat->fVmxCr8StoreExit = (pBaseFeat->fVmxCr8StoreExit & EmuFeat.fVmxCr8StoreExit );
1782 pGuestFeat->fVmxUseTprShadow = (pBaseFeat->fVmxUseTprShadow & EmuFeat.fVmxUseTprShadow );
1783 pGuestFeat->fVmxNmiWindowExit = (pBaseFeat->fVmxNmiWindowExit & EmuFeat.fVmxNmiWindowExit );
1784 pGuestFeat->fVmxMovDRxExit = (pBaseFeat->fVmxMovDRxExit & EmuFeat.fVmxMovDRxExit );
1785 pGuestFeat->fVmxUncondIoExit = (pBaseFeat->fVmxUncondIoExit & EmuFeat.fVmxUncondIoExit );
1786 pGuestFeat->fVmxUseIoBitmaps = (pBaseFeat->fVmxUseIoBitmaps & EmuFeat.fVmxUseIoBitmaps );
1787 pGuestFeat->fVmxMonitorTrapFlag = (pBaseFeat->fVmxMonitorTrapFlag & EmuFeat.fVmxMonitorTrapFlag );
1788 pGuestFeat->fVmxUseMsrBitmaps = (pBaseFeat->fVmxUseMsrBitmaps & EmuFeat.fVmxUseMsrBitmaps );
1789 pGuestFeat->fVmxMonitorExit = (pBaseFeat->fVmxMonitorExit & EmuFeat.fVmxMonitorExit );
1790 pGuestFeat->fVmxPauseExit = (pBaseFeat->fVmxPauseExit & EmuFeat.fVmxPauseExit );
1791 pGuestFeat->fVmxSecondaryExecCtls = (pBaseFeat->fVmxSecondaryExecCtls & EmuFeat.fVmxSecondaryExecCtls );
1792 pGuestFeat->fVmxVirtApicAccess = (pBaseFeat->fVmxVirtApicAccess & EmuFeat.fVmxVirtApicAccess );
1793 pGuestFeat->fVmxEpt = (pBaseFeat->fVmxEpt & EmuFeat.fVmxEpt );
1794 pGuestFeat->fVmxDescTableExit = (pBaseFeat->fVmxDescTableExit & EmuFeat.fVmxDescTableExit );
1795 pGuestFeat->fVmxRdtscp = (pBaseFeat->fVmxRdtscp & EmuFeat.fVmxRdtscp );
1796 pGuestFeat->fVmxVirtX2ApicMode = (pBaseFeat->fVmxVirtX2ApicMode & EmuFeat.fVmxVirtX2ApicMode );
1797 pGuestFeat->fVmxVpid = (pBaseFeat->fVmxVpid & EmuFeat.fVmxVpid );
1798 pGuestFeat->fVmxWbinvdExit = (pBaseFeat->fVmxWbinvdExit & EmuFeat.fVmxWbinvdExit );
1799 pGuestFeat->fVmxUnrestrictedGuest = (pBaseFeat->fVmxUnrestrictedGuest & EmuFeat.fVmxUnrestrictedGuest );
1800 pGuestFeat->fVmxApicRegVirt = (pBaseFeat->fVmxApicRegVirt & EmuFeat.fVmxApicRegVirt );
1801 pGuestFeat->fVmxVirtIntDelivery = (pBaseFeat->fVmxVirtIntDelivery & EmuFeat.fVmxVirtIntDelivery );
1802 pGuestFeat->fVmxPauseLoopExit = (pBaseFeat->fVmxPauseLoopExit & EmuFeat.fVmxPauseLoopExit );
1803 pGuestFeat->fVmxRdrandExit = (pBaseFeat->fVmxRdrandExit & EmuFeat.fVmxRdrandExit );
1804 pGuestFeat->fVmxInvpcid = (pBaseFeat->fVmxInvpcid & EmuFeat.fVmxInvpcid );
1805 pGuestFeat->fVmxVmFunc = (pBaseFeat->fVmxVmFunc & EmuFeat.fVmxVmFunc );
1806 pGuestFeat->fVmxVmcsShadowing = (pBaseFeat->fVmxVmcsShadowing & EmuFeat.fVmxVmcsShadowing );
1807 pGuestFeat->fVmxRdseedExit = (pBaseFeat->fVmxRdseedExit & EmuFeat.fVmxRdseedExit );
1808 pGuestFeat->fVmxPml = (pBaseFeat->fVmxPml & EmuFeat.fVmxPml );
1809 pGuestFeat->fVmxEptXcptVe = (pBaseFeat->fVmxEptXcptVe & EmuFeat.fVmxEptXcptVe );
1810 pGuestFeat->fVmxConcealVmxFromPt = (pBaseFeat->fVmxConcealVmxFromPt & EmuFeat.fVmxConcealVmxFromPt );
1811 pGuestFeat->fVmxXsavesXrstors = (pBaseFeat->fVmxXsavesXrstors & EmuFeat.fVmxXsavesXrstors );
1812 pGuestFeat->fVmxModeBasedExecuteEpt = (pBaseFeat->fVmxModeBasedExecuteEpt & EmuFeat.fVmxModeBasedExecuteEpt );
1813 pGuestFeat->fVmxSppEpt = (pBaseFeat->fVmxSppEpt & EmuFeat.fVmxSppEpt );
1814 pGuestFeat->fVmxPtEpt = (pBaseFeat->fVmxPtEpt & EmuFeat.fVmxPtEpt );
1815 pGuestFeat->fVmxUseTscScaling = (pBaseFeat->fVmxUseTscScaling & EmuFeat.fVmxUseTscScaling );
1816 pGuestFeat->fVmxUserWaitPause = (pBaseFeat->fVmxUserWaitPause & EmuFeat.fVmxUserWaitPause );
1817 pGuestFeat->fVmxEnclvExit = (pBaseFeat->fVmxEnclvExit & EmuFeat.fVmxEnclvExit );
1818 pGuestFeat->fVmxLoadIwKeyExit = (pBaseFeat->fVmxLoadIwKeyExit & EmuFeat.fVmxLoadIwKeyExit );
1819 pGuestFeat->fVmxEntryLoadDebugCtls = (pBaseFeat->fVmxEntryLoadDebugCtls & EmuFeat.fVmxEntryLoadDebugCtls );
1820 pGuestFeat->fVmxIa32eModeGuest = (pBaseFeat->fVmxIa32eModeGuest & EmuFeat.fVmxIa32eModeGuest );
1821 pGuestFeat->fVmxEntryLoadEferMsr = (pBaseFeat->fVmxEntryLoadEferMsr & EmuFeat.fVmxEntryLoadEferMsr );
1822 pGuestFeat->fVmxEntryLoadPatMsr = (pBaseFeat->fVmxEntryLoadPatMsr & EmuFeat.fVmxEntryLoadPatMsr );
1823 pGuestFeat->fVmxExitSaveDebugCtls = (pBaseFeat->fVmxExitSaveDebugCtls & EmuFeat.fVmxExitSaveDebugCtls );
1824 pGuestFeat->fVmxHostAddrSpaceSize = (pBaseFeat->fVmxHostAddrSpaceSize & EmuFeat.fVmxHostAddrSpaceSize );
1825 pGuestFeat->fVmxExitAckExtInt = (pBaseFeat->fVmxExitAckExtInt & EmuFeat.fVmxExitAckExtInt );
1826 pGuestFeat->fVmxExitSavePatMsr = (pBaseFeat->fVmxExitSavePatMsr & EmuFeat.fVmxExitSavePatMsr );
1827 pGuestFeat->fVmxExitLoadPatMsr = (pBaseFeat->fVmxExitLoadPatMsr & EmuFeat.fVmxExitLoadPatMsr );
1828 pGuestFeat->fVmxExitSaveEferMsr = (pBaseFeat->fVmxExitSaveEferMsr & EmuFeat.fVmxExitSaveEferMsr );
1829 pGuestFeat->fVmxExitLoadEferMsr = (pBaseFeat->fVmxExitLoadEferMsr & EmuFeat.fVmxExitLoadEferMsr );
1830 pGuestFeat->fVmxSavePreemptTimer = (pBaseFeat->fVmxSavePreemptTimer & EmuFeat.fVmxSavePreemptTimer );
1831 pGuestFeat->fVmxExitSaveEferLma = (pBaseFeat->fVmxExitSaveEferLma & EmuFeat.fVmxExitSaveEferLma );
1832 pGuestFeat->fVmxPt = (pBaseFeat->fVmxPt & EmuFeat.fVmxPt );
1833 pGuestFeat->fVmxVmwriteAll = (pBaseFeat->fVmxVmwriteAll & EmuFeat.fVmxVmwriteAll );
1834 pGuestFeat->fVmxEntryInjectSoftInt = (pBaseFeat->fVmxEntryInjectSoftInt & EmuFeat.fVmxEntryInjectSoftInt );
1835
1836 /* Don't expose VMX preemption timer if host is subject to VMX-preemption timer erratum. */
1837 if ( pGuestFeat->fVmxPreemptTimer
1838 && HMIsSubjectToVmxPreemptTimerErratum())
1839 {
1840 LogRel(("CPUM: Warning! VMX-preemption timer not exposed to guest due to host CPU erratum.\n"));
1841 pGuestFeat->fVmxPreemptTimer = 0;
1842 pGuestFeat->fVmxSavePreemptTimer = 0;
1843 }
1844
1845 /* Sanity checking. */
1846 if (!pGuestFeat->fVmxSecondaryExecCtls)
1847 {
1848 Assert(!pGuestFeat->fVmxVirtApicAccess);
1849 Assert(!pGuestFeat->fVmxEpt);
1850 Assert(!pGuestFeat->fVmxDescTableExit);
1851 Assert(!pGuestFeat->fVmxRdtscp);
1852 Assert(!pGuestFeat->fVmxVirtX2ApicMode);
1853 Assert(!pGuestFeat->fVmxVpid);
1854 Assert(!pGuestFeat->fVmxWbinvdExit);
1855 Assert(!pGuestFeat->fVmxUnrestrictedGuest);
1856 Assert(!pGuestFeat->fVmxApicRegVirt);
1857 Assert(!pGuestFeat->fVmxVirtIntDelivery);
1858 Assert(!pGuestFeat->fVmxPauseLoopExit);
1859 Assert(!pGuestFeat->fVmxRdrandExit);
1860 Assert(!pGuestFeat->fVmxInvpcid);
1861 Assert(!pGuestFeat->fVmxVmFunc);
1862 Assert(!pGuestFeat->fVmxVmcsShadowing);
1863 Assert(!pGuestFeat->fVmxRdseedExit);
1864 Assert(!pGuestFeat->fVmxPml);
1865 Assert(!pGuestFeat->fVmxEptXcptVe);
1866 Assert(!pGuestFeat->fVmxConcealVmxFromPt);
1867 Assert(!pGuestFeat->fVmxXsavesXrstors);
1868 Assert(!pGuestFeat->fVmxModeBasedExecuteEpt);
1869 Assert(!pGuestFeat->fVmxSppEpt);
1870 Assert(!pGuestFeat->fVmxPtEpt);
1871 Assert(!pGuestFeat->fVmxUseTscScaling);
1872 Assert(!pGuestFeat->fVmxUserWaitPause);
1873 Assert(!pGuestFeat->fVmxEnclvExit);
1874 }
1875 else if (pGuestFeat->fVmxUnrestrictedGuest)
1876 {
1877 /* See footnote in Intel spec. 27.2 "Recording VM-Exit Information And Updating VM-entry Control Fields". */
1878 Assert(pGuestFeat->fVmxExitSaveEferLma);
1879 /* Unrestricted guest execution requires EPT. See Intel spec. 25.2.1.1 "VM-Execution Control Fields". */
1880 Assert(pGuestFeat->fVmxEpt);
1881 }
1882
1883 if (!pGuestFeat->fVmxTertiaryExecCtls)
1884 Assert(!pGuestFeat->fVmxLoadIwKeyExit);
1885
1886 /*
1887 * Finally initialize the VMX guest MSRs.
1888 */
1889 cpumR3InitVmxGuestMsrs(pVM, pHostVmxMsrs, pGuestFeat, pGuestVmxMsrs);
1890}
1891
1892
1893/**
1894 * Gets the host hardware-virtualization MSRs.
1895 *
1896 * @returns VBox status code.
1897 * @param pMsrs Where to store the MSRs.
1898 */
1899static int cpumR3GetHostHwvirtMsrs(PCPUMMSRS pMsrs)
1900{
1901 Assert(pMsrs);
1902
1903 uint32_t fCaps = 0;
1904 int rc = SUPR3QueryVTCaps(&fCaps);
1905 if (RT_SUCCESS(rc))
1906 {
1907 if (fCaps & (SUPVTCAPS_VT_X | SUPVTCAPS_AMD_V))
1908 {
1909 SUPHWVIRTMSRS HwvirtMsrs;
1910 rc = SUPR3GetHwvirtMsrs(&HwvirtMsrs, false /* fForceRequery */);
1911 if (RT_SUCCESS(rc))
1912 {
1913 if (fCaps & SUPVTCAPS_VT_X)
1914 HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.vmx);
1915 else
1916 HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.svm);
1917 return VINF_SUCCESS;
1918 }
1919
1920 LogRel(("CPUM: Querying hardware-virtualization MSRs failed. rc=%Rrc\n", rc));
1921 return rc;
1922 }
1923
1924 LogRel(("CPUM: Querying hardware-virtualization capability succeeded but did not find VT-x or AMD-V\n"));
1925 return VERR_INTERNAL_ERROR_5;
1926 }
1927 LogRel(("CPUM: No hardware-virtualization capability detected\n"));
1928 return VINF_SUCCESS;
1929}
1930
1931
1932/**
1933 * @callback_method_impl{FNTMTIMERINT,
1934 * Callback that fires when the nested VMX-preemption timer expired.}
1935 */
1936static DECLCALLBACK(void) cpumR3VmxPreemptTimerCallback(PVM pVM, TMTIMERHANDLE hTimer, void *pvUser)
1937{
1938 RT_NOREF(pVM, hTimer);
1939 PVMCPU pVCpu = (PVMCPUR3)pvUser;
1940 AssertPtr(pVCpu);
1941 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
1942}
1943
1944
1945/**
1946 * Initializes the CPUM.
1947 *
1948 * @returns VBox status code.
1949 * @param pVM The cross context VM structure.
1950 */
1951VMMR3DECL(int) CPUMR3Init(PVM pVM)
1952{
1953 LogFlow(("CPUMR3Init\n"));
1954
1955 /*
1956 * Assert alignment, sizes and tables.
1957 */
1958 AssertCompileMemberAlignment(VM, cpum.s, 32);
1959 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
1960 AssertCompileSizeAlignment(CPUMCTX, 64);
1961 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
1962 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
1963 AssertCompileMemberAlignment(VM, cpum, 64);
1964 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
1965#ifdef VBOX_STRICT
1966 int rc2 = cpumR3MsrStrictInitChecks();
1967 AssertRCReturn(rc2, rc2);
1968#endif
1969
1970 /*
1971 * Gather info about the host CPU.
1972 */
1973 if (!ASMHasCpuId())
1974 {
1975 LogRel(("The CPU doesn't support CPUID!\n"));
1976 return VERR_UNSUPPORTED_CPU;
1977 }
1978
1979 pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
1980
1981 CPUMMSRS HostMsrs;
1982 RT_ZERO(HostMsrs);
1983 int rc = cpumR3GetHostHwvirtMsrs(&HostMsrs);
1984 AssertLogRelRCReturn(rc, rc);
1985
1986 PCPUMCPUIDLEAF paLeaves;
1987 uint32_t cLeaves;
1988 rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
1989 AssertLogRelRCReturn(rc, rc);
1990
1991 rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &HostMsrs, &pVM->cpum.s.HostFeatures);
1992 RTMemFree(paLeaves);
1993 AssertLogRelRCReturn(rc, rc);
1994 pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
1995
1996 /*
1997 * Check that the CPU supports the minimum features we require.
1998 */
1999 if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
2000 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
2001 if (!pVM->cpum.s.HostFeatures.fMmx)
2002 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
2003 if (!pVM->cpum.s.HostFeatures.fTsc)
2004 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
2005
2006 /*
2007 * Setup the CR4 AND and OR masks used in the raw-mode switcher.
2008 */
2009 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
2010 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
2011
2012 /*
2013 * Figure out which XSAVE/XRSTOR features are available on the host.
2014 */
2015 uint64_t fXcr0Host = 0;
2016 uint64_t fXStateHostMask = 0;
2017 if ( pVM->cpum.s.HostFeatures.fXSaveRstor
2018 && pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
2019 {
2020 fXStateHostMask = fXcr0Host = ASMGetXcr0();
2021 fXStateHostMask &= XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI;
2022 AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 | XSAVE_C_SSE)) == (XSAVE_C_X87 | XSAVE_C_SSE),
2023 ("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
2024 }
2025 pVM->cpum.s.fXStateHostMask = fXStateHostMask;
2026 LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
2027 pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
2028
2029 /*
2030 * Initialize the host XSAVE/XRSTOR mask.
2031 */
2032 uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
2033 cbMaxXState = RT_ALIGN(cbMaxXState, 128);
2034 AssertLogRelReturn( pVM->cpum.s.HostFeatures.cbMaxExtendedState >= sizeof(X86FXSTATE)
2035 && pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Host.XState)
2036 && pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Guest.XState)
2037 , VERR_CPUM_IPE_2);
2038
2039 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2040 {
2041 PVMCPU pVCpu = pVM->apCpusR3[i];
2042
2043 pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
2044 pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2045 }
2046
2047 /*
2048 * Register saved state data item.
2049 */
2050 rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
2051 NULL, cpumR3LiveExec, NULL,
2052 NULL, cpumR3SaveExec, NULL,
2053 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
2054 if (RT_FAILURE(rc))
2055 return rc;
2056
2057 /*
2058 * Register info handlers and registers with the debugger facility.
2059 */
2060 DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
2061 &cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
2062 DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
2063 &cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
2064 DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
2065 &cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
2066 DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
2067 &cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
2068 DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
2069 &cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
2070 DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
2071 &cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
2072 DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
2073 DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
2074 &cpumR3InfoVmxFeatures);
2075
2076 rc = cpumR3DbgInit(pVM);
2077 if (RT_FAILURE(rc))
2078 return rc;
2079
2080 /*
2081 * Check if we need to workaround partial/leaky FPU handling.
2082 */
2083 cpumR3CheckLeakyFpu(pVM);
2084
2085 /*
2086 * Initialize the Guest CPUID and MSR states.
2087 */
2088 rc = cpumR3InitCpuIdAndMsrs(pVM, &HostMsrs);
2089 if (RT_FAILURE(rc))
2090 return rc;
2091
2092 /*
2093 * Init the VMX/SVM state.
2094 *
2095 * This must be done after initializing CPUID/MSR features as we access the
2096 * the VMX/SVM guest features below.
2097 *
2098 * In the case of nested VT-x, we also need to create the per-VCPU
2099 * VMX preemption timers.
2100 */
2101 if (pVM->cpum.s.GuestFeatures.fVmx)
2102 cpumR3InitVmxHwVirtState(pVM);
2103 else if (pVM->cpum.s.GuestFeatures.fSvm)
2104 cpumR3InitSvmHwVirtState(pVM);
2105 else
2106 Assert(pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
2107
2108 CPUMR3Reset(pVM);
2109 return VINF_SUCCESS;
2110}
2111
2112
2113/**
2114 * Applies relocations to data and code managed by this
2115 * component. This function will be called at init and
2116 * whenever the VMM need to relocate it self inside the GC.
2117 *
2118 * The CPUM will update the addresses used by the switcher.
2119 *
2120 * @param pVM The cross context VM structure.
2121 */
2122VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
2123{
2124 RT_NOREF(pVM);
2125}
2126
2127
2128/**
2129 * Terminates the CPUM.
2130 *
2131 * Termination means cleaning up and freeing all resources,
2132 * the VM it self is at this point powered off or suspended.
2133 *
2134 * @returns VBox status code.
2135 * @param pVM The cross context VM structure.
2136 */
2137VMMR3DECL(int) CPUMR3Term(PVM pVM)
2138{
2139#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2140 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2141 {
2142 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2143 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
2144 pVCpu->cpum.s.uMagic = 0;
2145 pvCpu->cpum.s.Guest.dr[5] = 0;
2146 }
2147#endif
2148
2149 if (pVM->cpum.s.GuestFeatures.fVmx)
2150 {
2151 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2152 {
2153 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2154 if (pVCpu->cpum.s.hNestedVmxPreemptTimer != NIL_TMTIMERHANDLE)
2155 {
2156 int rc = TMR3TimerDestroy(pVM, pVCpu->cpum.s.hNestedVmxPreemptTimer); AssertRC(rc);
2157 pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2158 }
2159 }
2160 }
2161 return VINF_SUCCESS;
2162}
2163
2164
2165/**
2166 * Resets a virtual CPU.
2167 *
2168 * Used by CPUMR3Reset and CPU hot plugging.
2169 *
2170 * @param pVM The cross context VM structure.
2171 * @param pVCpu The cross context virtual CPU structure of the CPU that is
2172 * being reset. This may differ from the current EMT.
2173 */
2174VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2175{
2176 /** @todo anything different for VCPU > 0? */
2177 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2178
2179 /*
2180 * Initialize everything to ZERO first.
2181 */
2182 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
2183
2184 RT_BZERO(pCtx, RT_UOFFSETOF(CPUMCTX, aoffXState));
2185
2186 pVCpu->cpum.s.fUseFlags = fUseFlags;
2187
2188 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
2189 pCtx->eip = 0x0000fff0;
2190 pCtx->edx = 0x00000600; /* P6 processor */
2191 pCtx->eflags.Bits.u1Reserved0 = 1;
2192
2193 pCtx->cs.Sel = 0xf000;
2194 pCtx->cs.ValidSel = 0xf000;
2195 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2196 pCtx->cs.u64Base = UINT64_C(0xffff0000);
2197 pCtx->cs.u32Limit = 0x0000ffff;
2198 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
2199 pCtx->cs.Attr.n.u1Present = 1;
2200 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
2201
2202 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
2203 pCtx->ds.u32Limit = 0x0000ffff;
2204 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
2205 pCtx->ds.Attr.n.u1Present = 1;
2206 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2207
2208 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
2209 pCtx->es.u32Limit = 0x0000ffff;
2210 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
2211 pCtx->es.Attr.n.u1Present = 1;
2212 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2213
2214 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
2215 pCtx->fs.u32Limit = 0x0000ffff;
2216 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
2217 pCtx->fs.Attr.n.u1Present = 1;
2218 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2219
2220 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
2221 pCtx->gs.u32Limit = 0x0000ffff;
2222 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
2223 pCtx->gs.Attr.n.u1Present = 1;
2224 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2225
2226 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2227 pCtx->ss.u32Limit = 0x0000ffff;
2228 pCtx->ss.Attr.n.u1Present = 1;
2229 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
2230 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2231
2232 pCtx->idtr.cbIdt = 0xffff;
2233 pCtx->gdtr.cbGdt = 0xffff;
2234
2235 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2236 pCtx->ldtr.u32Limit = 0xffff;
2237 pCtx->ldtr.Attr.n.u1Present = 1;
2238 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
2239
2240 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2241 pCtx->tr.u32Limit = 0xffff;
2242 pCtx->tr.Attr.n.u1Present = 1;
2243 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
2244
2245 pCtx->dr[6] = X86_DR6_INIT_VAL;
2246 pCtx->dr[7] = X86_DR7_INIT_VAL;
2247
2248 PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
2249 pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
2250 pFpuCtx->FCW = 0x37f;
2251
2252 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
2253 IA-32 Processor States Following Power-up, Reset, or INIT */
2254 pFpuCtx->MXCSR = 0x1F80;
2255 pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
2256
2257 pCtx->aXcr[0] = XSAVE_C_X87;
2258 if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
2259 {
2260 /* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
2261 as we don't know what happened before. (Bother optimize later?) */
2262 pCtx->XState.Hdr.bmXState = XSAVE_C_X87 | XSAVE_C_SSE;
2263 }
2264
2265 /*
2266 * MSRs.
2267 */
2268 /* Init PAT MSR */
2269 pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
2270
2271 /* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
2272 * The Intel docs don't mention it. */
2273 Assert(!pCtx->msrEFER);
2274
2275 /* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
2276 is supposed to be here, just trying provide useful/sensible values. */
2277 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
2278 if (pRange)
2279 {
2280 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2281 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
2282 | (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
2283 | MSR_IA32_MISC_ENABLE_FAST_STRINGS;
2284 pRange->fWrIgnMask |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2285 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
2286 pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
2287 }
2288
2289 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
2290
2291 /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
2292 * called from each EMT while we're getting called by CPUMR3Reset()
2293 * iteratively on the same thread. Fix later. */
2294#if 0 /** @todo r=bird: This we will do in TM, not here. */
2295 /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
2296 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
2297#endif
2298
2299
2300 /* C-state control. Guesses. */
2301 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
2302 /* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
2303 * it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
2304 * functionality. The default value must be different due to incompatible write mask.
2305 */
2306 if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
2307 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
2308 else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
2309 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
2310
2311 /*
2312 * Hardware virtualization state.
2313 */
2314 CPUMSetGuestGif(pCtx, true);
2315 Assert(!pVM->cpum.s.GuestFeatures.fVmx || !pVM->cpum.s.GuestFeatures.fSvm); /* Paranoia. */
2316 if (pVM->cpum.s.GuestFeatures.fVmx)
2317 cpumR3ResetVmxHwVirtState(pVCpu);
2318 else if (pVM->cpum.s.GuestFeatures.fSvm)
2319 cpumR3ResetSvmHwVirtState(pVCpu);
2320}
2321
2322
2323/**
2324 * Resets the CPU.
2325 *
2326 * @returns VINF_SUCCESS.
2327 * @param pVM The cross context VM structure.
2328 */
2329VMMR3DECL(void) CPUMR3Reset(PVM pVM)
2330{
2331 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2332 {
2333 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2334 CPUMR3ResetCpu(pVM, pVCpu);
2335
2336#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2337
2338 /* Magic marker for searching in crash dumps. */
2339 strcpy((char *)pVCpu->.cpum.s.aMagic, "CPUMCPU Magic");
2340 pVCpu->cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2341 pVCpu->cpum.s.Guest->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2342#endif
2343 }
2344}
2345
2346
2347
2348
2349/**
2350 * Pass 0 live exec callback.
2351 *
2352 * @returns VINF_SSM_DONT_CALL_AGAIN.
2353 * @param pVM The cross context VM structure.
2354 * @param pSSM The saved state handle.
2355 * @param uPass The pass (0).
2356 */
2357static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2358{
2359 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2360 cpumR3SaveCpuId(pVM, pSSM);
2361 return VINF_SSM_DONT_CALL_AGAIN;
2362}
2363
2364
2365/**
2366 * Execute state save operation.
2367 *
2368 * @returns VBox status code.
2369 * @param pVM The cross context VM structure.
2370 * @param pSSM SSM operation handle.
2371 */
2372static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2373{
2374 /*
2375 * Save.
2376 */
2377 SSMR3PutU32(pSSM, pVM->cCpus);
2378 SSMR3PutU32(pSSM, sizeof(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr));
2379 CPUMCTX DummyHyperCtx;
2380 RT_ZERO(DummyHyperCtx);
2381 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2382 {
2383 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2384
2385 SSMR3PutStructEx(pSSM, &DummyHyperCtx, sizeof(DummyHyperCtx), 0, g_aCpumCtxFields, NULL);
2386
2387 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2388 SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2389 SSMR3PutStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2390 if (pGstCtx->fXStateMask != 0)
2391 SSMR3PutStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr), 0, g_aCpumXSaveHdrFields, NULL);
2392 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2393 {
2394 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2395 SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2396 }
2397 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2398 {
2399 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2400 SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2401 }
2402 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2403 {
2404 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2405 SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2406 }
2407 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2408 {
2409 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2410 SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2411 }
2412 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2413 {
2414 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2415 SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2416 }
2417 SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[0].u);
2418 SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[1].u);
2419 SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[2].u);
2420 SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[3].u);
2421 if (pVM->cpum.s.GuestFeatures.fSvm)
2422 {
2423 SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2424 SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2425 SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2426 SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2427 SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2428 SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2429 SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2430 g_aSvmHwvirtHostState, NULL /* pvUser */);
2431 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2432 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2433 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2434 SSMR3PutU32(pSSM, pGstCtx->hwvirt.fLocalForcedActions);
2435 SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2436 }
2437 if (pVM->cpum.s.GuestFeatures.fVmx)
2438 {
2439 SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmxon);
2440 SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmcs);
2441 SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2442 SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxRootMode);
2443 SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2444 SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInterceptEvents);
2445 SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2446 SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs), 0, g_aVmxHwvirtVmcs, NULL);
2447 SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2448 0, g_aVmxHwvirtVmcs, NULL);
2449 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2450 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2451 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2452 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2453 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2454 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2455 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2456 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2457 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uPrevPauseTick);
2458 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uEntryTick);
2459 SSMR3PutU16(pSSM, pGstCtx->hwvirt.vmx.offVirtApicWrite);
2460 SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2461 SSMR3PutU64(pSSM, MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON); /* Deprecated since 2021/09/22. Value kept backwards compatibile with 6.1.26. */
2462 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2463 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2464 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2465 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2466 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2467 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2468 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2469 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2470 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2471 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2472 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2473 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2474 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2475 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2476 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2477 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2478 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2479 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2480 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2481 }
2482 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2483 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2484 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2485 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2486 }
2487
2488 cpumR3SaveCpuId(pVM, pSSM);
2489 return VINF_SUCCESS;
2490}
2491
2492
2493/**
2494 * @callback_method_impl{FNSSMINTLOADPREP}
2495 */
2496static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2497{
2498 NOREF(pSSM);
2499 pVM->cpum.s.fPendingRestore = true;
2500 return VINF_SUCCESS;
2501}
2502
2503
2504/**
2505 * @callback_method_impl{FNSSMINTLOADEXEC}
2506 */
2507static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2508{
2509 int rc; /* Only for AssertRCReturn use. */
2510
2511 /*
2512 * Validate version.
2513 */
2514 if ( uVersion != CPUM_SAVED_STATE_VERSION_PAE_PDPES
2515 && uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2
2516 && uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX
2517 && uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2518 && uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2519 && uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2520 && uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2521 && uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2522 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
2523 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2524 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2525 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2526 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2527 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2528 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2529 {
2530 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2531 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2532 }
2533
2534 if (uPass == SSM_PASS_FINAL)
2535 {
2536 /*
2537 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2538 * really old SSM file versions.)
2539 */
2540 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2541 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2542 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2543 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR));
2544
2545 /*
2546 * Figure x86 and ctx field definitions to use for older states.
2547 */
2548 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2549 PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2550 PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2551 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2552 {
2553 paCpumCtx1Fields = g_aCpumX87FieldsV16;
2554 paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2555 }
2556 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2557 {
2558 paCpumCtx1Fields = g_aCpumX87FieldsMem;
2559 paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2560 }
2561
2562 /*
2563 * The hyper state used to preceed the CPU count. Starting with
2564 * XSAVE it was moved down till after we've got the count.
2565 */
2566 CPUMCTX HyperCtxIgnored;
2567 if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2568 {
2569 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2570 {
2571 X86FXSTATE Ign;
2572 SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2573 SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored),
2574 fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2575 }
2576 }
2577
2578 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2579 {
2580 uint32_t cCpus;
2581 rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2582 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2583 VERR_SSM_UNEXPECTED_DATA);
2584 }
2585 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2586 || pVM->cCpus == 1,
2587 ("cCpus=%u\n", pVM->cCpus),
2588 VERR_SSM_UNEXPECTED_DATA);
2589
2590 uint32_t cbMsrs = 0;
2591 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2592 {
2593 rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2594 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2595 VERR_SSM_UNEXPECTED_DATA);
2596 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2597 VERR_SSM_UNEXPECTED_DATA);
2598 }
2599
2600 /*
2601 * Do the per-CPU restoring.
2602 */
2603 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2604 {
2605 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2606 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2607
2608 if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2609 {
2610 /*
2611 * The XSAVE saved state layout moved the hyper state down here.
2612 */
2613 rc = SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored), 0, g_aCpumCtxFields, NULL);
2614 AssertRCReturn(rc, rc);
2615
2616 /*
2617 * Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2618 */
2619 rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2620 rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2621 AssertRCReturn(rc, rc);
2622
2623 /* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2624 if (pGstCtx->fXStateMask != 0)
2625 {
2626 AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2627 ("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2628 pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2629 VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2630 AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2631 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2632 AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
2633 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2634 AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
2635 || (pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
2636 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
2637 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2638 }
2639
2640 /* Check that the XCR0 mask is valid (invalid results in #GP). */
2641 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2642 if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2643 {
2644 AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask | XSAVE_C_X87)),
2645 ("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2646 VERR_CPUM_INVALID_XCR0);
2647 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2648 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2649 AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
2650 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2651 AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
2652 || (pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
2653 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
2654 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2655 }
2656
2657 /* Check that the XCR1 is zero, as we don't implement it yet. */
2658 AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2659
2660 /*
2661 * Restore the individual extended state components we support.
2662 */
2663 if (pGstCtx->fXStateMask != 0)
2664 {
2665 rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr),
2666 0, g_aCpumXSaveHdrFields, NULL);
2667 AssertRCReturn(rc, rc);
2668 AssertLogRelMsgReturn(!(pGstCtx->XState.Hdr.bmXState & ~pGstCtx->fXStateMask),
2669 ("bmXState=%#RX64 fXStateMask=%#RX64\n",
2670 pGstCtx->XState.Hdr.bmXState, pGstCtx->fXStateMask),
2671 VERR_CPUM_INVALID_XSAVE_HDR);
2672 }
2673 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2674 {
2675 PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2676 SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2677 }
2678 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2679 {
2680 PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2681 SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2682 }
2683 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2684 {
2685 PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2686 SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2687 }
2688 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2689 {
2690 PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2691 SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2692 }
2693 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2694 {
2695 PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2696 SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2697 }
2698 if (uVersion >= CPUM_SAVED_STATE_VERSION_PAE_PDPES)
2699 {
2700 SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[0].u);
2701 SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[1].u);
2702 SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[2].u);
2703 SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[3].u);
2704 }
2705 if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2706 {
2707 if (pVM->cpum.s.GuestFeatures.fSvm)
2708 {
2709 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2710 SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2711 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2712 SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2713 SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2714 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2715 SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2716 0 /* fFlags */, g_aSvmHwvirtHostState, NULL /* pvUser */);
2717 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2718 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2719 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2720 SSMR3GetU32(pSSM, &pGstCtx->hwvirt.fLocalForcedActions);
2721 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2722 }
2723 }
2724 if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX)
2725 {
2726 if (pVM->cpum.s.GuestFeatures.fVmx)
2727 {
2728 SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmxon);
2729 SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmcs);
2730 SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2731 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxRootMode);
2732 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2733 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInterceptEvents);
2734 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2735 SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs),
2736 0, g_aVmxHwvirtVmcs, NULL);
2737 SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2738 0, g_aVmxHwvirtVmcs, NULL);
2739 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2740 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2741 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2742 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2743 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2744 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2745 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2746 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2747 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uPrevPauseTick);
2748 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uEntryTick);
2749 SSMR3GetU16(pSSM, &pGstCtx->hwvirt.vmx.offVirtApicWrite);
2750 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2751 SSMR3Skip(pSSM, sizeof(uint64_t)); /* Unused - used to be IA32_FEATURE_CONTROL, see @bugref{10106}. */
2752 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2753 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2754 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2755 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2756 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2757 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2758 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2759 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2760 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2761 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2762 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2763 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2764 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2765 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2766 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2767 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2768 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2769 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2770 if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2)
2771 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2772 }
2773 }
2774 }
2775 else
2776 {
2777 /*
2778 * Pre XSAVE saved state.
2779 */
2780 SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87),
2781 fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2782 SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2783 }
2784
2785 /*
2786 * Restore a couple of flags and the MSRs.
2787 */
2788 uint32_t fIgnoredUsedFlags = 0;
2789 rc = SSMR3GetU32(pSSM, &fIgnoredUsedFlags); /* we're recalc the two relevant flags after loading state. */
2790 AssertRCReturn(rc, rc);
2791 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2792
2793 rc = VINF_SUCCESS;
2794 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2795 rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2796 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2797 {
2798 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2799 rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2800 }
2801 AssertRCReturn(rc, rc);
2802
2803 /* REM and other may have cleared must-be-one fields in DR6 and
2804 DR7, fix these. */
2805 pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
2806 pGstCtx->dr[6] |= X86_DR6_RA1_MASK;
2807 pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
2808 pGstCtx->dr[7] |= X86_DR7_RA1_MASK;
2809 }
2810
2811 /* Older states does not have the internal selector register flags
2812 and valid selector value. Supply those. */
2813 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2814 {
2815 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2816 {
2817 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2818 bool const fValid = true /*!VM_IS_RAW_MODE_ENABLED(pVM)*/
2819 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2820 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2821 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2822 if (fValid)
2823 {
2824 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2825 {
2826 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2827 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2828 }
2829
2830 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2831 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2832 }
2833 else
2834 {
2835 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2836 {
2837 paSelReg[iSelReg].fFlags = 0;
2838 paSelReg[iSelReg].ValidSel = 0;
2839 }
2840
2841 /* This might not be 104% correct, but I think it's close
2842 enough for all practical purposes... (REM always loaded
2843 LDTR registers.) */
2844 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2845 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2846 }
2847 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2848 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2849 }
2850 }
2851
2852 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2853 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2854 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2855 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2856 {
2857 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2858 pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2859 }
2860
2861 /*
2862 * A quick sanity check.
2863 */
2864 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2865 {
2866 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2867 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2868 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2869 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2870 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2871 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2872 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2873 }
2874 }
2875
2876 pVM->cpum.s.fPendingRestore = false;
2877
2878 /*
2879 * Guest CPUIDs (and VMX MSR features).
2880 */
2881 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
2882 {
2883 CPUMMSRS GuestMsrs;
2884 RT_ZERO(GuestMsrs);
2885
2886 CPUMFEATURES BaseFeatures;
2887 bool const fVmxGstFeat = pVM->cpum.s.GuestFeatures.fVmx;
2888 if (fVmxGstFeat)
2889 {
2890 /*
2891 * At this point the MSRs in the guest CPU-context are loaded with the guest VMX MSRs from the saved state.
2892 * However the VMX sub-features have not been exploded yet. So cache the base (host derived) VMX features
2893 * here so we can compare them for compatibility after exploding guest features.
2894 */
2895 BaseFeatures = pVM->cpum.s.GuestFeatures;
2896
2897 /* Use the VMX MSR features from the saved state while exploding guest features. */
2898 GuestMsrs.hwvirt.vmx = pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.vmx.Msrs;
2899 }
2900
2901 /* Load CPUID and explode guest features. */
2902 rc = cpumR3LoadCpuId(pVM, pSSM, uVersion, &GuestMsrs);
2903 if (fVmxGstFeat)
2904 {
2905 /*
2906 * Check if the exploded VMX features from the saved state are compatible with the host-derived features
2907 * we cached earlier (above). The is required if we use hardware-assisted nested-guest execution with
2908 * VMX features presented to the guest.
2909 */
2910 bool const fIsCompat = cpumR3AreVmxCpuFeaturesCompatible(pVM, &BaseFeatures, &pVM->cpum.s.GuestFeatures);
2911 if (!fIsCompat)
2912 return VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO;
2913 }
2914 return rc;
2915 }
2916 return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
2917}
2918
2919
2920/**
2921 * @callback_method_impl{FNSSMINTLOADDONE}
2922 */
2923static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2924{
2925 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2926 return VINF_SUCCESS;
2927
2928 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2929 if (pVM->cpum.s.fPendingRestore)
2930 {
2931 LogRel(("CPUM: Missing state!\n"));
2932 return VERR_INTERNAL_ERROR_2;
2933 }
2934
2935 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2936 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2937 {
2938 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2939
2940 /* Notify PGM of the NXE states in case they've changed. */
2941 PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2942
2943 /* During init. this is done in CPUMR3InitCompleted(). */
2944 if (fSupportsLongMode)
2945 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
2946
2947 /* Recalc the CPUM_USE_DEBUG_REGS_HYPER value. */
2948 CPUMRecalcHyperDRx(pVCpu, UINT8_MAX);
2949 }
2950 return VINF_SUCCESS;
2951}
2952
2953
2954/**
2955 * Checks if the CPUM state restore is still pending.
2956 *
2957 * @returns true / false.
2958 * @param pVM The cross context VM structure.
2959 */
2960VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2961{
2962 return pVM->cpum.s.fPendingRestore;
2963}
2964
2965
2966/**
2967 * Formats the EFLAGS value into mnemonics.
2968 *
2969 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2970 * @param efl The EFLAGS value.
2971 */
2972static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2973{
2974 /*
2975 * Format the flags.
2976 */
2977 static const struct
2978 {
2979 const char *pszSet; const char *pszClear; uint32_t fFlag;
2980 } s_aFlags[] =
2981 {
2982 { "vip",NULL, X86_EFL_VIP },
2983 { "vif",NULL, X86_EFL_VIF },
2984 { "ac", NULL, X86_EFL_AC },
2985 { "vm", NULL, X86_EFL_VM },
2986 { "rf", NULL, X86_EFL_RF },
2987 { "nt", NULL, X86_EFL_NT },
2988 { "ov", "nv", X86_EFL_OF },
2989 { "dn", "up", X86_EFL_DF },
2990 { "ei", "di", X86_EFL_IF },
2991 { "tf", NULL, X86_EFL_TF },
2992 { "nt", "pl", X86_EFL_SF },
2993 { "nz", "zr", X86_EFL_ZF },
2994 { "ac", "na", X86_EFL_AF },
2995 { "po", "pe", X86_EFL_PF },
2996 { "cy", "nc", X86_EFL_CF },
2997 };
2998 char *psz = pszEFlags;
2999 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
3000 {
3001 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
3002 if (pszAdd)
3003 {
3004 strcpy(psz, pszAdd);
3005 psz += strlen(pszAdd);
3006 *psz++ = ' ';
3007 }
3008 }
3009 psz[-1] = '\0';
3010}
3011
3012
3013/**
3014 * Formats a full register dump.
3015 *
3016 * @param pVM The cross context VM structure.
3017 * @param pCtx The context to format.
3018 * @param pCtxCore The context core to format.
3019 * @param pHlp Output functions.
3020 * @param enmType The dump type.
3021 * @param pszPrefix Register name prefix.
3022 */
3023static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
3024 const char *pszPrefix)
3025{
3026 NOREF(pVM);
3027
3028 /*
3029 * Format the EFLAGS.
3030 */
3031 uint32_t efl = pCtxCore->eflags.u32;
3032 char szEFlags[80];
3033 cpumR3InfoFormatFlags(&szEFlags[0], efl);
3034
3035 /*
3036 * Format the registers.
3037 */
3038 switch (enmType)
3039 {
3040 case CPUMDUMPTYPE_TERSE:
3041 if (CPUMIsGuestIn64BitCodeEx(pCtx))
3042 pHlp->pfnPrintf(pHlp,
3043 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3044 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3045 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3046 "%sr14=%016RX64 %sr15=%016RX64\n"
3047 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3048 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3049 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3050 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3051 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3052 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3053 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3054 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3055 else
3056 pHlp->pfnPrintf(pHlp,
3057 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3058 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3059 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3060 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3061 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3062 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3063 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3064 break;
3065
3066 case CPUMDUMPTYPE_DEFAULT:
3067 if (CPUMIsGuestIn64BitCodeEx(pCtx))
3068 pHlp->pfnPrintf(pHlp,
3069 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3070 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3071 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3072 "%sr14=%016RX64 %sr15=%016RX64\n"
3073 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3074 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3075 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
3076 ,
3077 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3078 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3079 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3080 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3081 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3082 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3083 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3084 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3085 else
3086 pHlp->pfnPrintf(pHlp,
3087 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3088 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3089 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3090 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
3091 ,
3092 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3093 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3094 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3095 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3096 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3097 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3098 break;
3099
3100 case CPUMDUMPTYPE_VERBOSE:
3101 if (CPUMIsGuestIn64BitCodeEx(pCtx))
3102 pHlp->pfnPrintf(pHlp,
3103 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3104 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3105 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3106 "%sr14=%016RX64 %sr15=%016RX64\n"
3107 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3108 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3109 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3110 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3111 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3112 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3113 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3114 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
3115 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
3116 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
3117 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3118 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3119 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3120 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
3121 ,
3122 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3123 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3124 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3125 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3126 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
3127 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
3128 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
3129 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
3130 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
3131 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
3132 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3133 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3134 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3135 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3136 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3137 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3138 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3139 else
3140 pHlp->pfnPrintf(pHlp,
3141 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3142 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3143 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3144 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3145 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3146 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3147 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3148 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3149 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3150 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3151 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3152 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3153 ,
3154 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3155 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3156 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3157 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3158 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3159 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3160 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3161 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3162 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3163 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3164 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3165 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3166
3167 pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
3168 pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
3169 pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
3170 {
3171 PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
3172 pHlp->pfnPrintf(pHlp,
3173 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3174 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3175 ,
3176 pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
3177 pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
3178 pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
3179 pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
3180 );
3181 /*
3182 * The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
3183 * not (FP)R0-7 as Intel SDM suggests.
3184 */
3185 unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
3186 for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
3187 {
3188 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
3189 unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
3190 char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
3191 unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
3192 uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
3193 int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
3194 iExponent -= 16383; /* subtract bias */
3195 /** @todo This isn't entirenly correct and needs more work! */
3196 pHlp->pfnPrintf(pHlp,
3197 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
3198 pszPrefix, iST, pszPrefix, iFPR,
3199 pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
3200 uTag, chSign, iInteger, u64Fraction, iExponent);
3201 if (pFpuCtx->aRegs[iST].au16[5] || pFpuCtx->aRegs[iST].au16[6] || pFpuCtx->aRegs[iST].au16[7])
3202 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3203 pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
3204 else
3205 pHlp->pfnPrintf(pHlp, "\n");
3206 }
3207
3208 /* XMM/YMM/ZMM registers. */
3209 if (pCtx->fXStateMask & XSAVE_C_YMM)
3210 {
3211 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
3212 if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
3213 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3214 pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3215 pszPrefix, i, i < 10 ? " " : "",
3216 pYmmHiCtx->aYmmHi[i].au32[3],
3217 pYmmHiCtx->aYmmHi[i].au32[2],
3218 pYmmHiCtx->aYmmHi[i].au32[1],
3219 pYmmHiCtx->aYmmHi[i].au32[0],
3220 pFpuCtx->aXMM[i].au32[3],
3221 pFpuCtx->aXMM[i].au32[2],
3222 pFpuCtx->aXMM[i].au32[1],
3223 pFpuCtx->aXMM[i].au32[0]);
3224 else
3225 {
3226 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
3227 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3228 pHlp->pfnPrintf(pHlp,
3229 "%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3230 pszPrefix, i, i < 10 ? " " : "",
3231 pZmmHi256->aHi256Regs[i].au32[7],
3232 pZmmHi256->aHi256Regs[i].au32[6],
3233 pZmmHi256->aHi256Regs[i].au32[5],
3234 pZmmHi256->aHi256Regs[i].au32[4],
3235 pZmmHi256->aHi256Regs[i].au32[3],
3236 pZmmHi256->aHi256Regs[i].au32[2],
3237 pZmmHi256->aHi256Regs[i].au32[1],
3238 pZmmHi256->aHi256Regs[i].au32[0],
3239 pYmmHiCtx->aYmmHi[i].au32[3],
3240 pYmmHiCtx->aYmmHi[i].au32[2],
3241 pYmmHiCtx->aYmmHi[i].au32[1],
3242 pYmmHiCtx->aYmmHi[i].au32[0],
3243 pFpuCtx->aXMM[i].au32[3],
3244 pFpuCtx->aXMM[i].au32[2],
3245 pFpuCtx->aXMM[i].au32[1],
3246 pFpuCtx->aXMM[i].au32[0]);
3247
3248 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
3249 for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
3250 pHlp->pfnPrintf(pHlp,
3251 "%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3252 pszPrefix, i + 16,
3253 pZmm16Hi->aRegs[i].au32[15],
3254 pZmm16Hi->aRegs[i].au32[14],
3255 pZmm16Hi->aRegs[i].au32[13],
3256 pZmm16Hi->aRegs[i].au32[12],
3257 pZmm16Hi->aRegs[i].au32[11],
3258 pZmm16Hi->aRegs[i].au32[10],
3259 pZmm16Hi->aRegs[i].au32[9],
3260 pZmm16Hi->aRegs[i].au32[8],
3261 pZmm16Hi->aRegs[i].au32[7],
3262 pZmm16Hi->aRegs[i].au32[6],
3263 pZmm16Hi->aRegs[i].au32[5],
3264 pZmm16Hi->aRegs[i].au32[4],
3265 pZmm16Hi->aRegs[i].au32[3],
3266 pZmm16Hi->aRegs[i].au32[2],
3267 pZmm16Hi->aRegs[i].au32[1],
3268 pZmm16Hi->aRegs[i].au32[0]);
3269 }
3270 }
3271 else
3272 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3273 pHlp->pfnPrintf(pHlp,
3274 i & 1
3275 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3276 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3277 pszPrefix, i, i < 10 ? " " : "",
3278 pFpuCtx->aXMM[i].au32[3],
3279 pFpuCtx->aXMM[i].au32[2],
3280 pFpuCtx->aXMM[i].au32[1],
3281 pFpuCtx->aXMM[i].au32[0]);
3282
3283 if (pCtx->fXStateMask & XSAVE_C_OPMASK)
3284 {
3285 PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
3286 for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
3287 pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
3288 pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
3289 pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
3290 pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
3291 pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
3292 }
3293
3294 if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
3295 {
3296 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
3297 for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
3298 pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
3299 pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
3300 pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
3301 }
3302
3303 if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
3304 {
3305 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
3306 pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
3307 pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
3308 }
3309
3310 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
3311 if (pFpuCtx->au32RsrvdRest[i])
3312 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
3313 pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
3314 }
3315
3316 pHlp->pfnPrintf(pHlp,
3317 "%sEFER =%016RX64\n"
3318 "%sPAT =%016RX64\n"
3319 "%sSTAR =%016RX64\n"
3320 "%sCSTAR =%016RX64\n"
3321 "%sLSTAR =%016RX64\n"
3322 "%sSFMASK =%016RX64\n"
3323 "%sKERNELGSBASE =%016RX64\n",
3324 pszPrefix, pCtx->msrEFER,
3325 pszPrefix, pCtx->msrPAT,
3326 pszPrefix, pCtx->msrSTAR,
3327 pszPrefix, pCtx->msrCSTAR,
3328 pszPrefix, pCtx->msrLSTAR,
3329 pszPrefix, pCtx->msrSFMASK,
3330 pszPrefix, pCtx->msrKERNELGSBASE);
3331
3332 if (CPUMIsGuestInPAEModeEx(pCtx))
3333 for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aPaePdpes); i++)
3334 pHlp->pfnPrintf(pHlp, "%sPAE PDPTE %u =%016RX64\n", pszPrefix, i, pCtx->aPaePdpes[i]);
3335 break;
3336 }
3337}
3338
3339
3340/**
3341 * Display all cpu states and any other cpum info.
3342 *
3343 * @param pVM The cross context VM structure.
3344 * @param pHlp The info helper functions.
3345 * @param pszArgs Arguments, ignored.
3346 */
3347static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3348{
3349 cpumR3InfoGuest(pVM, pHlp, pszArgs);
3350 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3351 cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
3352 cpumR3InfoHyper(pVM, pHlp, pszArgs);
3353 cpumR3InfoHost(pVM, pHlp, pszArgs);
3354}
3355
3356
3357/**
3358 * Parses the info argument.
3359 *
3360 * The argument starts with 'verbose', 'terse' or 'default' and then
3361 * continues with the comment string.
3362 *
3363 * @param pszArgs The pointer to the argument string.
3364 * @param penmType Where to store the dump type request.
3365 * @param ppszComment Where to store the pointer to the comment string.
3366 */
3367static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
3368{
3369 if (!pszArgs)
3370 {
3371 *penmType = CPUMDUMPTYPE_DEFAULT;
3372 *ppszComment = "";
3373 }
3374 else
3375 {
3376 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3377 {
3378 pszArgs += 7;
3379 *penmType = CPUMDUMPTYPE_VERBOSE;
3380 }
3381 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3382 {
3383 pszArgs += 5;
3384 *penmType = CPUMDUMPTYPE_TERSE;
3385 }
3386 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3387 {
3388 pszArgs += 7;
3389 *penmType = CPUMDUMPTYPE_DEFAULT;
3390 }
3391 else
3392 *penmType = CPUMDUMPTYPE_DEFAULT;
3393 *ppszComment = RTStrStripL(pszArgs);
3394 }
3395}
3396
3397
3398/**
3399 * Display the guest cpu state.
3400 *
3401 * @param pVM The cross context VM structure.
3402 * @param pHlp The info helper functions.
3403 * @param pszArgs Arguments.
3404 */
3405static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3406{
3407 CPUMDUMPTYPE enmType;
3408 const char *pszComment;
3409 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3410
3411 PVMCPU pVCpu = VMMGetCpu(pVM);
3412 if (!pVCpu)
3413 pVCpu = pVM->apCpusR3[0];
3414
3415 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3416
3417 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3418 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3419}
3420
3421
3422/**
3423 * Displays an SVM VMCB control area.
3424 *
3425 * @param pHlp The info helper functions.
3426 * @param pVmcbCtrl Pointer to a SVM VMCB controls area.
3427 * @param pszPrefix Caller specified string prefix.
3428 */
3429static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
3430{
3431 AssertReturnVoid(pHlp);
3432 AssertReturnVoid(pVmcbCtrl);
3433
3434 pHlp->pfnPrintf(pHlp, "%sCRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
3435 pHlp->pfnPrintf(pHlp, "%sCRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
3436 pHlp->pfnPrintf(pHlp, "%sDRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
3437 pHlp->pfnPrintf(pHlp, "%sDRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
3438 pHlp->pfnPrintf(pHlp, "%sException intercepts = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
3439 pHlp->pfnPrintf(pHlp, "%sControl intercepts = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
3440 pHlp->pfnPrintf(pHlp, "%sPause-filter threshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
3441 pHlp->pfnPrintf(pHlp, "%sPause-filter count = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
3442 pHlp->pfnPrintf(pHlp, "%sIOPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
3443 pHlp->pfnPrintf(pHlp, "%sMSRPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
3444 pHlp->pfnPrintf(pHlp, "%sTSC offset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
3445 pHlp->pfnPrintf(pHlp, "%sTLB Control\n", pszPrefix);
3446 pHlp->pfnPrintf(pHlp, " %sASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
3447 pHlp->pfnPrintf(pHlp, " %sTLB-flush type = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
3448 pHlp->pfnPrintf(pHlp, "%sInterrupt Control\n", pszPrefix);
3449 pHlp->pfnPrintf(pHlp, " %sVTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
3450 pHlp->pfnPrintf(pHlp, " %sVIRQ (Pending) = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
3451 pHlp->pfnPrintf(pHlp, " %sVINTR vector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
3452 pHlp->pfnPrintf(pHlp, " %sVGIF = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
3453 pHlp->pfnPrintf(pHlp, " %sVINTR priority = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
3454 pHlp->pfnPrintf(pHlp, " %sIgnore TPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
3455 pHlp->pfnPrintf(pHlp, " %sVINTR masking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
3456 pHlp->pfnPrintf(pHlp, " %sVGIF enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
3457 pHlp->pfnPrintf(pHlp, " %sAVIC enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
3458 pHlp->pfnPrintf(pHlp, "%sInterrupt Shadow\n", pszPrefix);
3459 pHlp->pfnPrintf(pHlp, " %sInterrupt shadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
3460 pHlp->pfnPrintf(pHlp, " %sGuest-interrupt Mask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
3461 pHlp->pfnPrintf(pHlp, "%sExit Code = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
3462 pHlp->pfnPrintf(pHlp, "%sEXITINFO1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
3463 pHlp->pfnPrintf(pHlp, "%sEXITINFO2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
3464 pHlp->pfnPrintf(pHlp, "%sExit Interrupt Info\n", pszPrefix);
3465 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
3466 pHlp->pfnPrintf(pHlp, " %sVector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
3467 pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
3468 pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
3469 pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
3470 pHlp->pfnPrintf(pHlp, "%sNested paging and SEV\n", pszPrefix);
3471 pHlp->pfnPrintf(pHlp, " %sNested paging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
3472 pHlp->pfnPrintf(pHlp, " %sSEV (Secure Encrypted VM) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
3473 pHlp->pfnPrintf(pHlp, " %sSEV-ES (Encrypted State) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
3474 pHlp->pfnPrintf(pHlp, "%sEvent Inject\n", pszPrefix);
3475 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
3476 pHlp->pfnPrintf(pHlp, " %sVector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
3477 pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
3478 pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
3479 pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
3480 pHlp->pfnPrintf(pHlp, "%sNested-paging CR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
3481 pHlp->pfnPrintf(pHlp, "%sLBR Virtualization\n", pszPrefix);
3482 pHlp->pfnPrintf(pHlp, " %sLBR virt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
3483 pHlp->pfnPrintf(pHlp, " %sVirt. VMSAVE/VMLOAD = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
3484 pHlp->pfnPrintf(pHlp, "%sVMCB Clean Bits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
3485 pHlp->pfnPrintf(pHlp, "%sNext-RIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
3486 pHlp->pfnPrintf(pHlp, "%sInstruction bytes fetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
3487 pHlp->pfnPrintf(pHlp, "%sInstruction bytes = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
3488 pHlp->pfnPrintf(pHlp, "%sAVIC\n", pszPrefix);
3489 pHlp->pfnPrintf(pHlp, " %sBar addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
3490 pHlp->pfnPrintf(pHlp, " %sBacking page addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
3491 pHlp->pfnPrintf(pHlp, " %sLogical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
3492 pHlp->pfnPrintf(pHlp, " %sPhysical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
3493 pHlp->pfnPrintf(pHlp, " %sLast guest core Id = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
3494}
3495
3496
3497/**
3498 * Helper for dumping the SVM VMCB selector registers.
3499 *
3500 * @param pHlp The info helper functions.
3501 * @param pSel Pointer to the SVM selector register.
3502 * @param pszName Name of the selector.
3503 * @param pszPrefix Caller specified string prefix.
3504 */
3505DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char *pszName, const char *pszPrefix)
3506{
3507 /* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
3508 pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
3509 pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
3510}
3511
3512
3513/**
3514 * Helper for dumping the SVM VMCB GDTR/IDTR registers.
3515 *
3516 * @param pHlp The info helper functions.
3517 * @param pXdtr Pointer to the descriptor table register.
3518 * @param pszName Name of the descriptor table register.
3519 * @param pszPrefix Caller specified string prefix.
3520 */
3521DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char *pszName, const char *pszPrefix)
3522{
3523 /* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
3524 pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
3525}
3526
3527
3528/**
3529 * Displays an SVM VMCB state-save area.
3530 *
3531 * @param pHlp The info helper functions.
3532 * @param pVmcbStateSave Pointer to a SVM VMCB controls area.
3533 * @param pszPrefix Caller specified string prefix.
3534 */
3535static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
3536{
3537 AssertReturnVoid(pHlp);
3538 AssertReturnVoid(pVmcbStateSave);
3539
3540 char szEFlags[80];
3541 cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
3542
3543 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
3544 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
3545 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
3546 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
3547 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
3548 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
3549 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
3550 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
3551 cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
3552 cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
3553 pHlp->pfnPrintf(pHlp, "%sCPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
3554 pHlp->pfnPrintf(pHlp, "%sEFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
3555 pHlp->pfnPrintf(pHlp, "%sCR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
3556 pHlp->pfnPrintf(pHlp, "%sCR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
3557 pHlp->pfnPrintf(pHlp, "%sCR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
3558 pHlp->pfnPrintf(pHlp, "%sDR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
3559 pHlp->pfnPrintf(pHlp, "%sDR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
3560 pHlp->pfnPrintf(pHlp, "%sRFLAGS = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
3561 pHlp->pfnPrintf(pHlp, "%sRIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
3562 pHlp->pfnPrintf(pHlp, "%sRSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
3563 pHlp->pfnPrintf(pHlp, "%sRAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
3564 pHlp->pfnPrintf(pHlp, "%sSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
3565 pHlp->pfnPrintf(pHlp, "%sLSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
3566 pHlp->pfnPrintf(pHlp, "%sCSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
3567 pHlp->pfnPrintf(pHlp, "%sSFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
3568 pHlp->pfnPrintf(pHlp, "%sKERNELGSBASE = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
3569 pHlp->pfnPrintf(pHlp, "%sSysEnter CS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
3570 pHlp->pfnPrintf(pHlp, "%sSysEnter EIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
3571 pHlp->pfnPrintf(pHlp, "%sSysEnter ESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
3572 pHlp->pfnPrintf(pHlp, "%sCR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
3573 pHlp->pfnPrintf(pHlp, "%sPAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
3574 pHlp->pfnPrintf(pHlp, "%sDBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
3575 pHlp->pfnPrintf(pHlp, "%sBR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
3576 pHlp->pfnPrintf(pHlp, "%sBR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
3577 pHlp->pfnPrintf(pHlp, "%sLASTXCPT_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
3578 pHlp->pfnPrintf(pHlp, "%sLASTXCPT_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
3579}
3580
3581
3582/**
3583 * Displays a virtual-VMCS.
3584 *
3585 * @param pVCpu The cross context virtual CPU structure.
3586 * @param pHlp The info helper functions.
3587 * @param pVmcs Pointer to a virtual VMCS.
3588 * @param pszPrefix Caller specified string prefix.
3589 */
3590static void cpumR3InfoVmxVmcs(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, PCVMXVVMCS pVmcs, const char *pszPrefix)
3591{
3592 AssertReturnVoid(pHlp);
3593 AssertReturnVoid(pVmcs);
3594
3595 /* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
3596#define CPUMVMX_DUMP_HOST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3597 do { \
3598 (a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64}\n", \
3599 (a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u); \
3600 } while (0)
3601
3602#define CPUMVMX_DUMP_HOST_FS_GS_TR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3603 do { \
3604 (a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64}\n", \
3605 (a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u); \
3606 } while (0)
3607
3608#define CPUMVMX_DUMP_GUEST_SEGREG(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3609 do { \
3610 (a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
3611 (a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
3612 (a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr); \
3613 } while (0)
3614
3615#define CPUMVMX_DUMP_GUEST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3616 do { \
3617 (a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64 limit=%08x}\n", \
3618 (a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit); \
3619 } while (0)
3620
3621 /* Header. */
3622 {
3623 pHlp->pfnPrintf(pHlp, "%sHeader:\n", pszPrefix);
3624 pHlp->pfnPrintf(pHlp, " %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId);
3625 pHlp->pfnPrintf(pHlp, " %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, VMXGetAbortDesc(pVmcs->enmVmxAbort));
3626 pHlp->pfnPrintf(pHlp, " %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, VMXGetVmcsStateDesc(pVmcs->fVmcsState));
3627 }
3628
3629 /* Control fields. */
3630 {
3631 /* 16-bit. */
3632 pHlp->pfnPrintf(pHlp, "%sControl:\n", pszPrefix);
3633 pHlp->pfnPrintf(pHlp, " %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid);
3634 pHlp->pfnPrintf(pHlp, " %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector);
3635 pHlp->pfnPrintf(pHlp, " %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex);
3636
3637 /* 32-bit. */
3638 pHlp->pfnPrintf(pHlp, " %sPin ctls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls);
3639 pHlp->pfnPrintf(pHlp, " %sProcessor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls);
3640 pHlp->pfnPrintf(pHlp, " %sSecondary processor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2);
3641 pHlp->pfnPrintf(pHlp, " %sVM-exit ctls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls);
3642 pHlp->pfnPrintf(pHlp, " %sVM-entry ctls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls);
3643 pHlp->pfnPrintf(pHlp, " %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap);
3644 pHlp->pfnPrintf(pHlp, " %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask);
3645 pHlp->pfnPrintf(pHlp, " %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch);
3646 pHlp->pfnPrintf(pHlp, " %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount);
3647 pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount);
3648 pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount);
3649 pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount);
3650 pHlp->pfnPrintf(pHlp, " %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo);
3651 {
3652 uint32_t const fInfo = pVmcs->u32EntryIntInfo;
3653 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
3654 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo));
3655 pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetEntryIntInfoTypeDesc(uType));
3656 pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo));
3657 pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3658 pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3659 }
3660 pHlp->pfnPrintf(pHlp, " %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode);
3661 pHlp->pfnPrintf(pHlp, " %sVM-entry instr length = %u byte(s)\n", pszPrefix, pVmcs->u32EntryInstrLen);
3662 pHlp->pfnPrintf(pHlp, " %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold);
3663 pHlp->pfnPrintf(pHlp, " %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap);
3664 pHlp->pfnPrintf(pHlp, " %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow);
3665
3666 /* 64-bit. */
3667 pHlp->pfnPrintf(pHlp, " %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u);
3668 pHlp->pfnPrintf(pHlp, " %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u);
3669 pHlp->pfnPrintf(pHlp, " %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u);
3670 pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u);
3671 pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u);
3672 pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u);
3673 pHlp->pfnPrintf(pHlp, " %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u);
3674 pHlp->pfnPrintf(pHlp, " %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u);
3675 pHlp->pfnPrintf(pHlp, " %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u);
3676 pHlp->pfnPrintf(pHlp, " %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u);
3677 pHlp->pfnPrintf(pHlp, " %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u);
3678 pHlp->pfnPrintf(pHlp, " %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u);
3679 pHlp->pfnPrintf(pHlp, " %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u);
3680 pHlp->pfnPrintf(pHlp, " %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptPtr.u);
3681 pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 0 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u);
3682 pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 1 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u);
3683 pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 2 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u);
3684 pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 3 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u);
3685 pHlp->pfnPrintf(pHlp, " %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u);
3686 pHlp->pfnPrintf(pHlp, " %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u);
3687 pHlp->pfnPrintf(pHlp, " %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u);
3688 pHlp->pfnPrintf(pHlp, " %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u);
3689 pHlp->pfnPrintf(pHlp, " %sXSS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssExitBitmap.u);
3690 pHlp->pfnPrintf(pHlp, " %sENCLS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclsExitBitmap.u);
3691 pHlp->pfnPrintf(pHlp, " %sSPP-table ptr = %#RX64\n", pszPrefix, pVmcs->u64SppTablePtr.u);
3692 pHlp->pfnPrintf(pHlp, " %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u);
3693 pHlp->pfnPrintf(pHlp, " %sTertiary processor ctls = %#RX64\n", pszPrefix, pVmcs->u64ProcCtls3.u);
3694 pHlp->pfnPrintf(pHlp, " %sENCLV-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclvExitBitmap.u);
3695
3696 /* Natural width. */
3697 pHlp->pfnPrintf(pHlp, " %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u);
3698 pHlp->pfnPrintf(pHlp, " %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u);
3699 pHlp->pfnPrintf(pHlp, " %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u);
3700 pHlp->pfnPrintf(pHlp, " %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u);
3701 pHlp->pfnPrintf(pHlp, " %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u);
3702 pHlp->pfnPrintf(pHlp, " %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u);
3703 pHlp->pfnPrintf(pHlp, " %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u);
3704 pHlp->pfnPrintf(pHlp, " %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u);
3705 }
3706
3707 /* Guest state. */
3708 {
3709 char szEFlags[80];
3710 cpumR3InfoFormatFlags(&szEFlags[0], pVmcs->u64GuestRFlags.u);
3711 pHlp->pfnPrintf(pHlp, "%sGuest state:\n", pszPrefix);
3712
3713 /* 16-bit. */
3714 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Cs, "CS", pszPrefix);
3715 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ss, "SS", pszPrefix);
3716 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Es, "ES", pszPrefix);
3717 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ds, "DS", pszPrefix);
3718 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Fs, "FS", pszPrefix);
3719 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Gs, "GS", pszPrefix);
3720 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ldtr, "LDTR", pszPrefix);
3721 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Tr, "TR", pszPrefix);
3722 CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
3723 CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
3724 pHlp->pfnPrintf(pHlp, " %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus);
3725 pHlp->pfnPrintf(pHlp, " %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex);
3726
3727 /* 32-bit. */
3728 pHlp->pfnPrintf(pHlp, " %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState);
3729 pHlp->pfnPrintf(pHlp, " %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState);
3730 pHlp->pfnPrintf(pHlp, " %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase);
3731 pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS);
3732 pHlp->pfnPrintf(pHlp, " %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer);
3733
3734 /* 64-bit. */
3735 pHlp->pfnPrintf(pHlp, " %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u);
3736 pHlp->pfnPrintf(pHlp, " %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u);
3737 pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u);
3738 pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u);
3739 pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u);
3740 pHlp->pfnPrintf(pHlp, " %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u);
3741 pHlp->pfnPrintf(pHlp, " %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u);
3742 pHlp->pfnPrintf(pHlp, " %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u);
3743 pHlp->pfnPrintf(pHlp, " %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u);
3744 pHlp->pfnPrintf(pHlp, " %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u);
3745 pHlp->pfnPrintf(pHlp, " %sRTIT_CTL = %#RX64\n", pszPrefix, pVmcs->u64GuestRtitCtlMsr.u);
3746 pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64GuestPkrsMsr.u);
3747
3748 /* Natural width. */
3749 pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u);
3750 pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u);
3751 pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u);
3752 pHlp->pfnPrintf(pHlp, " %sDR7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u);
3753 pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u);
3754 pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u);
3755 pHlp->pfnPrintf(pHlp, " %sRFLAGS = %#RX64 %31s\n",pszPrefix, pVmcs->u64GuestRFlags.u, szEFlags);
3756 pHlp->pfnPrintf(pHlp, " %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpts.u);
3757 pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u);
3758 pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u);
3759 pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64GuestSCetMsr.u);
3760 pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64GuestSsp.u);
3761 pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64GuestIntrSspTableAddrMsr.u);
3762 }
3763
3764 /* Host state. */
3765 {
3766 pHlp->pfnPrintf(pHlp, "%sHost state:\n", pszPrefix);
3767
3768 /* 16-bit. */
3769 pHlp->pfnPrintf(pHlp, " %sCS = %#RX16\n", pszPrefix, pVmcs->HostCs);
3770 pHlp->pfnPrintf(pHlp, " %sSS = %#RX16\n", pszPrefix, pVmcs->HostSs);
3771 pHlp->pfnPrintf(pHlp, " %sDS = %#RX16\n", pszPrefix, pVmcs->HostDs);
3772 pHlp->pfnPrintf(pHlp, " %sES = %#RX16\n", pszPrefix, pVmcs->HostEs);
3773 CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Fs, "FS", pszPrefix);
3774 CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Gs, "GS", pszPrefix);
3775 CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Tr, "TR", pszPrefix);
3776 CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
3777 CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
3778
3779 /* 32-bit. */
3780 pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs);
3781
3782 /* 64-bit. */
3783 pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u);
3784 pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u);
3785 pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u);
3786 pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64HostPkrsMsr.u);
3787
3788 /* Natural width. */
3789 pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u);
3790 pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u);
3791 pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u);
3792 pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u);
3793 pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u);
3794 pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u);
3795 pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u);
3796 pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64HostSCetMsr.u);
3797 pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64HostSsp.u);
3798 pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64HostIntrSspTableAddrMsr.u);
3799
3800 }
3801
3802 /* Read-only fields. */
3803 {
3804 pHlp->pfnPrintf(pHlp, "%sRead-only data fields:\n", pszPrefix);
3805
3806 /* 16-bit (none currently). */
3807
3808 /* 32-bit. */
3809 pHlp->pfnPrintf(pHlp, " %sExit reason = %u (%s)\n", pszPrefix, pVmcs->u32RoExitReason, HMGetVmxExitName(pVmcs->u32RoExitReason));
3810 pHlp->pfnPrintf(pHlp, " %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u);
3811 pHlp->pfnPrintf(pHlp, " %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError);
3812 pHlp->pfnPrintf(pHlp, " %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo);
3813 {
3814 uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
3815 uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
3816 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo));
3817 pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetExitIntInfoTypeDesc(uType));
3818 pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo));
3819 pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3820 pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3821 }
3822 pHlp->pfnPrintf(pHlp, " %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode);
3823 pHlp->pfnPrintf(pHlp, " %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo);
3824 {
3825 uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
3826 uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
3827 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo));
3828 pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetIdtVectoringInfoTypeDesc(uType));
3829 pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo));
3830 pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo));
3831 }
3832 pHlp->pfnPrintf(pHlp, " %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode);
3833 pHlp->pfnPrintf(pHlp, " %sVM-exit instruction length = %u byte(s)\n", pszPrefix, pVmcs->u32RoExitInstrLen);
3834 pHlp->pfnPrintf(pHlp, " %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo);
3835
3836 /* 64-bit. */
3837 pHlp->pfnPrintf(pHlp, " %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u);
3838
3839 /* Natural width. */
3840 pHlp->pfnPrintf(pHlp, " %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u);
3841 pHlp->pfnPrintf(pHlp, " %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u);
3842 pHlp->pfnPrintf(pHlp, " %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u);
3843 pHlp->pfnPrintf(pHlp, " %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u);
3844 pHlp->pfnPrintf(pHlp, " %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u);
3845 }
3846
3847#ifdef DEBUG_ramshankar
3848 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
3849 {
3850 void *pvPage = RTMemTmpAllocZ(VMX_V_VIRT_APIC_SIZE);
3851 Assert(pvPage);
3852 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3853 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pvPage, GCPhysVirtApic, VMX_V_VIRT_APIC_SIZE);
3854 if (RT_SUCCESS(rc))
3855 {
3856 pHlp->pfnPrintf(pHlp, " %sVirtual-APIC page\n", pszPrefix);
3857 pHlp->pfnPrintf(pHlp, "%.*Rhxs\n", VMX_V_VIRT_APIC_SIZE, pvPage);
3858 pHlp->pfnPrintf(pHlp, "\n");
3859 }
3860 RTMemTmpFree(pvPage);
3861 }
3862#else
3863 NOREF(pVCpu);
3864#endif
3865
3866#undef CPUMVMX_DUMP_HOST_XDTR
3867#undef CPUMVMX_DUMP_HOST_FS_GS_TR
3868#undef CPUMVMX_DUMP_GUEST_SEGREG
3869#undef CPUMVMX_DUMP_GUEST_XDTR
3870}
3871
3872
3873/**
3874 * Display the guest's hardware-virtualization cpu state.
3875 *
3876 * @param pVM The cross context VM structure.
3877 * @param pHlp The info helper functions.
3878 * @param pszArgs Arguments, ignored.
3879 */
3880static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3881{
3882 RT_NOREF(pszArgs);
3883
3884 PVMCPU pVCpu = VMMGetCpu(pVM);
3885 if (!pVCpu)
3886 pVCpu = pVM->apCpusR3[0];
3887
3888 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3889 bool const fSvm = pVM->cpum.s.GuestFeatures.fSvm;
3890 bool const fVmx = pVM->cpum.s.GuestFeatures.fVmx;
3891
3892 pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
3893 pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
3894 pHlp->pfnPrintf(pHlp, "In nested-guest hwvirt mode = %RTbool\n", CPUMIsGuestInNestedHwvirtMode(pCtx));
3895
3896 if (fSvm)
3897 {
3898 pHlp->pfnPrintf(pHlp, "SVM hwvirt state:\n");
3899 pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
3900
3901 char szEFlags[80];
3902 cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
3903 pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
3904 pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
3905 pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
3906 cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.Vmcb.ctrl, " " /* pszPrefix */);
3907 pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
3908 cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.Vmcb.guest, " " /* pszPrefix */);
3909 pHlp->pfnPrintf(pHlp, " HostState:\n");
3910 pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
3911 pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
3912 pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
3913 pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
3914 pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
3915 pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
3916 pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
3917 pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
3918 PCCPUMSELREG pSelEs = &pCtx->hwvirt.svm.HostState.es;
3919 pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3920 pSelEs->Sel, pSelEs->u64Base, pSelEs->u32Limit, pSelEs->Attr.u);
3921 PCCPUMSELREG pSelCs = &pCtx->hwvirt.svm.HostState.cs;
3922 pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3923 pSelCs->Sel, pSelCs->u64Base, pSelCs->u32Limit, pSelCs->Attr.u);
3924 PCCPUMSELREG pSelSs = &pCtx->hwvirt.svm.HostState.ss;
3925 pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3926 pSelSs->Sel, pSelSs->u64Base, pSelSs->u32Limit, pSelSs->Attr.u);
3927 PCCPUMSELREG pSelDs = &pCtx->hwvirt.svm.HostState.ds;
3928 pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3929 pSelDs->Sel, pSelDs->u64Base, pSelDs->u32Limit, pSelDs->Attr.u);
3930 pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
3931 pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
3932 pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
3933 pCtx->hwvirt.svm.HostState.idtr.cbIdt);
3934 pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
3935 pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
3936 pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
3937 }
3938 else if (fVmx)
3939 {
3940 pHlp->pfnPrintf(pHlp, "VMX hwvirt state:\n");
3941 pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
3942 pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
3943 pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
3944 pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag));
3945 pHlp->pfnPrintf(pHlp, " uDiagAux = %#RX64\n", pCtx->hwvirt.vmx.uDiagAux);
3946 pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, VMXGetAbortDesc(pCtx->hwvirt.vmx.enmAbort));
3947 pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
3948 pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
3949 pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
3950 pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
3951 pHlp->pfnPrintf(pHlp, " fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret);
3952 pHlp->pfnPrintf(pHlp, " uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick);
3953 pHlp->pfnPrintf(pHlp, " uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick);
3954 pHlp->pfnPrintf(pHlp, " uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick);
3955 pHlp->pfnPrintf(pHlp, " offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite);
3956 pHlp->pfnPrintf(pHlp, " fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking);
3957 pHlp->pfnPrintf(pHlp, " VMCS cache:\n");
3958 cpumR3InfoVmxVmcs(pVCpu, pHlp, &pCtx->hwvirt.vmx.Vmcs, " " /* pszPrefix */);
3959 }
3960 else
3961 pHlp->pfnPrintf(pHlp, "Hwvirt state disabled.\n");
3962
3963#undef CPUMHWVIRTDUMP_NONE
3964#undef CPUMHWVIRTDUMP_COMMON
3965#undef CPUMHWVIRTDUMP_SVM
3966#undef CPUMHWVIRTDUMP_VMX
3967#undef CPUMHWVIRTDUMP_LAST
3968#undef CPUMHWVIRTDUMP_ALL
3969}
3970
3971/**
3972 * Display the current guest instruction
3973 *
3974 * @param pVM The cross context VM structure.
3975 * @param pHlp The info helper functions.
3976 * @param pszArgs Arguments, ignored.
3977 */
3978static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3979{
3980 NOREF(pszArgs);
3981
3982 PVMCPU pVCpu = VMMGetCpu(pVM);
3983 if (!pVCpu)
3984 pVCpu = pVM->apCpusR3[0];
3985
3986 char szInstruction[256];
3987 szInstruction[0] = '\0';
3988 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
3989 pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
3990}
3991
3992
3993/**
3994 * Display the hypervisor cpu state.
3995 *
3996 * @param pVM The cross context VM structure.
3997 * @param pHlp The info helper functions.
3998 * @param pszArgs Arguments, ignored.
3999 */
4000static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4001{
4002 PVMCPU pVCpu = VMMGetCpu(pVM);
4003 if (!pVCpu)
4004 pVCpu = pVM->apCpusR3[0];
4005
4006 CPUMDUMPTYPE enmType;
4007 const char *pszComment;
4008 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4009 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
4010
4011 pHlp->pfnPrintf(pHlp,
4012 ".dr0=%016RX64 .dr1=%016RX64 .dr2=%016RX64 .dr3=%016RX64\n"
4013 ".dr4=%016RX64 .dr5=%016RX64 .dr6=%016RX64 .dr7=%016RX64\n",
4014 pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1], pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3],
4015 pVCpu->cpum.s.Hyper.dr[4], pVCpu->cpum.s.Hyper.dr[5], pVCpu->cpum.s.Hyper.dr[6], pVCpu->cpum.s.Hyper.dr[7]);
4016 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
4017}
4018
4019
4020/**
4021 * Display the host cpu state.
4022 *
4023 * @param pVM The cross context VM structure.
4024 * @param pHlp The info helper functions.
4025 * @param pszArgs Arguments, ignored.
4026 */
4027static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4028{
4029 CPUMDUMPTYPE enmType;
4030 const char *pszComment;
4031 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4032 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
4033
4034 PVMCPU pVCpu = VMMGetCpu(pVM);
4035 if (!pVCpu)
4036 pVCpu = pVM->apCpusR3[0];
4037 PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
4038
4039 /*
4040 * Format the EFLAGS.
4041 */
4042 uint64_t efl = pCtx->rflags;
4043 char szEFlags[80];
4044 cpumR3InfoFormatFlags(&szEFlags[0], efl);
4045
4046 /*
4047 * Format the registers.
4048 */
4049 pHlp->pfnPrintf(pHlp,
4050 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
4051 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
4052 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
4053 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
4054 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
4055 "r14=%016RX64 r15=%016RX64\n"
4056 "iopl=%d %31s\n"
4057 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
4058 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
4059 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
4060 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
4061 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
4062 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
4063 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
4064 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
4065 ,
4066 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
4067 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
4068 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
4069 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
4070 pCtx->r11, pCtx->r12, pCtx->r13,
4071 pCtx->r14, pCtx->r15,
4072 X86_EFL_GET_IOPL(efl), szEFlags,
4073 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
4074 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
4075 pCtx->cr4, pCtx->ldtr, pCtx->tr,
4076 pCtx->dr0, pCtx->dr1, pCtx->dr2,
4077 pCtx->dr3, pCtx->dr6, pCtx->dr7,
4078 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
4079 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
4080 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
4081}
4082
4083/**
4084 * Structure used when disassembling and instructions in DBGF.
4085 * This is used so the reader function can get the stuff it needs.
4086 */
4087typedef struct CPUMDISASSTATE
4088{
4089 /** Pointer to the CPU structure. */
4090 PDISCPUSTATE pCpu;
4091 /** Pointer to the VM. */
4092 PVM pVM;
4093 /** Pointer to the VMCPU. */
4094 PVMCPU pVCpu;
4095 /** Pointer to the first byte in the segment. */
4096 RTGCUINTPTR GCPtrSegBase;
4097 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
4098 RTGCUINTPTR GCPtrSegEnd;
4099 /** The size of the segment minus 1. */
4100 RTGCUINTPTR cbSegLimit;
4101 /** Pointer to the current page - R3 Ptr. */
4102 void const *pvPageR3;
4103 /** Pointer to the current page - GC Ptr. */
4104 RTGCPTR pvPageGC;
4105 /** The lock information that PGMPhysReleasePageMappingLock needs. */
4106 PGMPAGEMAPLOCK PageMapLock;
4107 /** Whether the PageMapLock is valid or not. */
4108 bool fLocked;
4109 /** 64 bits mode or not. */
4110 bool f64Bits;
4111} CPUMDISASSTATE, *PCPUMDISASSTATE;
4112
4113
4114/**
4115 * @callback_method_impl{FNDISREADBYTES}
4116 */
4117static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4118{
4119 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4120 for (;;)
4121 {
4122 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4123
4124 /*
4125 * Need to update the page translation?
4126 */
4127 if ( !pState->pvPageR3
4128 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
4129 {
4130 /* translate the address */
4131 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
4132
4133 /* Release mapping lock previously acquired. */
4134 if (pState->fLocked)
4135 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4136 int rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4137 if (RT_SUCCESS(rc))
4138 pState->fLocked = true;
4139 else
4140 {
4141 pState->fLocked = false;
4142 pState->pvPageR3 = NULL;
4143 return rc;
4144 }
4145 }
4146
4147 /*
4148 * Check the segment limit.
4149 */
4150 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4151 return VERR_OUT_OF_SELECTOR_BOUNDS;
4152
4153 /*
4154 * Calc how much we can read.
4155 */
4156 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
4157 if (!pState->f64Bits)
4158 {
4159 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4160 if (cb > cbSeg && cbSeg)
4161 cb = cbSeg;
4162 }
4163 if (cb > cbMaxRead)
4164 cb = cbMaxRead;
4165
4166 /*
4167 * Read and advance or exit.
4168 */
4169 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
4170 offInstr += (uint8_t)cb;
4171 if (cb >= cbMinRead)
4172 {
4173 pDis->cbCachedInstr = offInstr;
4174 return VINF_SUCCESS;
4175 }
4176 cbMinRead -= (uint8_t)cb;
4177 cbMaxRead -= (uint8_t)cb;
4178 }
4179}
4180
4181
4182/**
4183 * Disassemble an instruction and return the information in the provided structure.
4184 *
4185 * @returns VBox status code.
4186 * @param pVM The cross context VM structure.
4187 * @param pVCpu The cross context virtual CPU structure.
4188 * @param pCtx Pointer to the guest CPU context.
4189 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
4190 * @param pCpu Disassembly state.
4191 * @param pszPrefix String prefix for logging (debug only).
4192 *
4193 */
4194VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
4195 const char *pszPrefix)
4196{
4197 CPUMDISASSTATE State;
4198 int rc;
4199
4200 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4201 State.pCpu = pCpu;
4202 State.pvPageGC = 0;
4203 State.pvPageR3 = NULL;
4204 State.pVM = pVM;
4205 State.pVCpu = pVCpu;
4206 State.fLocked = false;
4207 State.f64Bits = false;
4208
4209 /*
4210 * Get selector information.
4211 */
4212 DISCPUMODE enmDisCpuMode;
4213 if ( (pCtx->cr0 & X86_CR0_PE)
4214 && pCtx->eflags.Bits.u1VM == 0)
4215 {
4216 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4217 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4218 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4219 State.GCPtrSegBase = pCtx->cs.u64Base;
4220 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4221 State.cbSegLimit = pCtx->cs.u32Limit;
4222 enmDisCpuMode = (State.f64Bits)
4223 ? DISCPUMODE_64BIT
4224 : pCtx->cs.Attr.n.u1DefBig
4225 ? DISCPUMODE_32BIT
4226 : DISCPUMODE_16BIT;
4227 }
4228 else
4229 {
4230 /* real or V86 mode */
4231 enmDisCpuMode = DISCPUMODE_16BIT;
4232 State.GCPtrSegBase = pCtx->cs.Sel * 16;
4233 State.GCPtrSegEnd = 0xFFFFFFFF;
4234 State.cbSegLimit = 0xFFFFFFFF;
4235 }
4236
4237 /*
4238 * Disassemble the instruction.
4239 */
4240 uint32_t cbInstr;
4241#ifndef LOG_ENABLED
4242 RT_NOREF_PV(pszPrefix);
4243 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4244 if (RT_SUCCESS(rc))
4245 {
4246#else
4247 char szOutput[160];
4248 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4249 pCpu, &cbInstr, szOutput, sizeof(szOutput));
4250 if (RT_SUCCESS(rc))
4251 {
4252 /* log it */
4253 if (pszPrefix)
4254 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4255 else
4256 Log(("%s", szOutput));
4257#endif
4258 rc = VINF_SUCCESS;
4259 }
4260 else
4261 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4262
4263 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
4264 if (State.fLocked)
4265 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4266
4267 return rc;
4268}
4269
4270
4271
4272/**
4273 * API for controlling a few of the CPU features found in CR4.
4274 *
4275 * Currently only X86_CR4_TSD is accepted as input.
4276 *
4277 * @returns VBox status code.
4278 *
4279 * @param pVM The cross context VM structure.
4280 * @param fOr The CR4 OR mask.
4281 * @param fAnd The CR4 AND mask.
4282 */
4283VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4284{
4285 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4286 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4287
4288 pVM->cpum.s.CR4.OrMask &= fAnd;
4289 pVM->cpum.s.CR4.OrMask |= fOr;
4290
4291 return VINF_SUCCESS;
4292}
4293
4294
4295/**
4296 * Called when the ring-3 init phase completes.
4297 *
4298 * @returns VBox status code.
4299 * @param pVM The cross context VM structure.
4300 * @param enmWhat Which init phase.
4301 */
4302VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
4303{
4304 switch (enmWhat)
4305 {
4306 case VMINITCOMPLETED_RING3:
4307 {
4308 /*
4309 * Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
4310 * Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
4311 */
4312 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
4313 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4314 {
4315 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4316
4317 /* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
4318 if (fSupportsLongMode)
4319 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
4320 }
4321
4322 /* Register statistic counters for MSRs. */
4323 cpumR3MsrRegStats(pVM);
4324
4325 /* Create VMX-preemption timer for nested guests if required. Must be
4326 done here as CPUM is initialized before TM. */
4327 if (pVM->cpum.s.GuestFeatures.fVmx)
4328 {
4329 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4330 {
4331 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4332 char szName[32];
4333 RTStrPrintf(szName, sizeof(szName), "Nested VMX-preemption %u", idCpu);
4334 int rc = TMR3TimerCreate(pVM, TMCLOCK_VIRTUAL_SYNC, cpumR3VmxPreemptTimerCallback, pVCpu,
4335 TMTIMER_FLAGS_RING0, szName, &pVCpu->cpum.s.hNestedVmxPreemptTimer);
4336 AssertLogRelRCReturn(rc, rc);
4337 }
4338 }
4339 break;
4340 }
4341
4342 default:
4343 break;
4344 }
4345 return VINF_SUCCESS;
4346}
4347
4348
4349/**
4350 * Called when the ring-0 init phases completed.
4351 *
4352 * @param pVM The cross context VM structure.
4353 */
4354VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
4355{
4356 /*
4357 * Enable log buffering as we're going to log a lot of lines.
4358 */
4359 bool const fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
4360
4361 /*
4362 * Log the cpuid.
4363 */
4364 RTCPUSET OnlineSet;
4365 LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4366 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4367 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4368 RTCPUID cCores = RTMpGetCoreCount();
4369 if (cCores)
4370 LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
4371 LogRel(("************************* CPUID dump ************************\n"));
4372 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4373 LogRel(("\n"));
4374 DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
4375 LogRel(("******************** End of CPUID dump **********************\n"));
4376
4377 /*
4378 * Log VT-x extended features.
4379 *
4380 * SVM features are currently all covered under CPUID so there is nothing
4381 * to do here for SVM.
4382 */
4383 if (pVM->cpum.s.HostFeatures.fVmx)
4384 {
4385 LogRel(("*********************** VT-x features ***********************\n"));
4386 DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
4387 LogRel(("\n"));
4388 LogRel(("******************* End of VT-x features ********************\n"));
4389 }
4390
4391 /*
4392 * Restore the log buffering state to what it was previously.
4393 */
4394 RTLogRelSetBuffering(fOldBuffered);
4395}
4396
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