CPUM.cpp@ 73494

Last change on this file since 73494 was 73389, checked in by vboxsync, 6 years ago
VMM, SUPDrv: Nested VMX: bugref:9180 Implement some of the VMX MSRs.
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1	/* $Id: CPUM.cpp 73389 2018-07-28 07:03:03Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*
33	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34	*
35	* TODO: proper write up, currently just some notes.
36	*
37	* The ring-0 FPU handling per OS:
38	*
39	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
40	* convention (Visual C++ doesn't seem to have a way to disable
41	* generating such code either), so CR0.TS/EM are always zero from what I
42	* can tell. We are also forced to always load/save the guest XMM0-XMM15
43	* registers when entering/leaving guest context. Interrupt handlers
44	* using FPU/SSE will offically have call save and restore functions
45	* exported by the kernel, if the really really have to use the state.
46	*
47	* - 32-bit windows does lazy FPU handling, I think, probably including
48	* lazying saving. The Windows Internals book states that it's a bad
49	* idea to use the FPU in kernel space. However, it looks like it will
50	* restore the FPU state of the current thread in case of a kernel \#NM.
51	* Interrupt handlers should be same as for 64-bit.
52	*
53	* - Darwin allows taking \#NM in kernel space, restoring current thread's
54	* state if I read the code correctly. It saves the FPU state of the
55	* outgoing thread, and uses CR0.TS to lazily load the state of the
56	* incoming one. No idea yet how the FPU is treated by interrupt
57	* handlers, i.e. whether they are allowed to disable the state or
58	* something.
59	*
60	* - Linux also allows \#NM in kernel space (don't know since when), and
61	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62	* loads the incoming unless configured to agressivly load it. Interrupt
63	* handlers can ask whether they're allowed to use the FPU, and may
64	* freely trash the state if Linux thinks it has saved the thread's state
65	* already. This is a problem.
66	*
67	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68	* context. When switching threads, the kernel will save the state of
69	* the outgoing thread and lazy load the incoming one using CR0.TS.
70	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
71	* to do stuff, HAT are among the users. The routines there will
72	* manually clear CR0.TS and save the XMM registers they use only if
73	* CR0.TS was zero upon entry. They will skip it when not, because as
74	* mentioned above, the FPU state is saved when switching away from a
75	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76	* preserve. This is a problem if we restore CR0.TS to 1 after loading
77	* the guest state.
78	*
79	* - FreeBSD - no idea yet.
80	*
81	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83	* FPU states.
84	*
85	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86	* saving and restoring the host and guest states. The motivation for this
87	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88	*
89	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90	* state and only restore it once we've restore the host FPU state. This has the
91	* accidental side effect of triggering Solaris to preserve XMM registers in
92	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94	*
95	*
96	* @section sec_cpum_logging Logging Level Assignments.
97	*
98	* Following log level assignments:
99	* - Log6 is used for FPU state management.
100	* - Log7 is used for FPU state actualization.
101	*
102	*/
103
104
105	/*********************************************************************************************************************************
106	* Header Files *
107	*********************************************************************************************************************************/
108	#define LOG_GROUP LOG_GROUP_CPUM
109	#include <VBox/vmm/cpum.h>
110	#include <VBox/vmm/cpumdis.h>
111	#include <VBox/vmm/cpumctx-v1_6.h>
112	#include <VBox/vmm/pgm.h>
113	#include <VBox/vmm/apic.h>
114	#include <VBox/vmm/mm.h>
115	#include <VBox/vmm/em.h>
116	#include <VBox/vmm/iem.h>
117	#include <VBox/vmm/selm.h>
118	#include <VBox/vmm/dbgf.h>
119	#include <VBox/vmm/patm.h>
120	#include <VBox/vmm/hm.h>
121	#include <VBox/vmm/ssm.h>
122	#include "CPUMInternal.h"
123	#include <VBox/vmm/vm.h>
124
125	#include <VBox/param.h>
126	#include <VBox/dis.h>
127	#include <VBox/err.h>
128	#include <VBox/log.h>
129	#include <iprt/asm-amd64-x86.h>
130	#include <iprt/assert.h>
131	#include <iprt/cpuset.h>
132	#include <iprt/mem.h>
133	#include <iprt/mp.h>
134	#include <iprt/string.h>
135
136
137	/*********************************************************************************************************************************
138	* Defined Constants And Macros *
139	*********************************************************************************************************************************/
140	/**
141	* This was used in the saved state up to the early life of version 14.
142	*
143	* It indicates that we may have some out-of-sync hidden segement registers.
144	* It is only relevant for raw-mode.
145	*/
146	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
147
148
149	/*********************************************************************************************************************************
150	* Structures and Typedefs *
151	*********************************************************************************************************************************/
152
153	/**
154	* What kind of cpu info dump to perform.
155	*/
156	typedef enum CPUMDUMPTYPE
157	{
158	CPUMDUMPTYPE_TERSE,
159	CPUMDUMPTYPE_DEFAULT,
160	CPUMDUMPTYPE_VERBOSE
161	} CPUMDUMPTYPE;
162	/** Pointer to a cpu info dump type. */
163	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
164
165
166	/*********************************************************************************************************************************
167	* Internal Functions *
168	*********************************************************************************************************************************/
169	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
170	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
171	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
172	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
173	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
174	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
179	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
180
181
182	/*********************************************************************************************************************************
183	* Global Variables *
184	*********************************************************************************************************************************/
185	/** Saved state field descriptors for CPUMCTX. */
186	static const SSMFIELD g_aCpumCtxFields[] =
187	{
188	SSMFIELD_ENTRY( CPUMCTX, rdi),
189	SSMFIELD_ENTRY( CPUMCTX, rsi),
190	SSMFIELD_ENTRY( CPUMCTX, rbp),
191	SSMFIELD_ENTRY( CPUMCTX, rax),
192	SSMFIELD_ENTRY( CPUMCTX, rbx),
193	SSMFIELD_ENTRY( CPUMCTX, rdx),
194	SSMFIELD_ENTRY( CPUMCTX, rcx),
195	SSMFIELD_ENTRY( CPUMCTX, rsp),
196	SSMFIELD_ENTRY( CPUMCTX, rflags),
197	SSMFIELD_ENTRY( CPUMCTX, rip),
198	SSMFIELD_ENTRY( CPUMCTX, r8),
199	SSMFIELD_ENTRY( CPUMCTX, r9),
200	SSMFIELD_ENTRY( CPUMCTX, r10),
201	SSMFIELD_ENTRY( CPUMCTX, r11),
202	SSMFIELD_ENTRY( CPUMCTX, r12),
203	SSMFIELD_ENTRY( CPUMCTX, r13),
204	SSMFIELD_ENTRY( CPUMCTX, r14),
205	SSMFIELD_ENTRY( CPUMCTX, r15),
206	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
207	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
208	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
209	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
210	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
211	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
212	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
213	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
214	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
215	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
216	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
217	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
218	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
219	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
220	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
221	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
222	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
223	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
224	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
225	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
226	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
227	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
228	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
229	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
230	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, cr0),
243	SSMFIELD_ENTRY( CPUMCTX, cr2),
244	SSMFIELD_ENTRY( CPUMCTX, cr3),
245	SSMFIELD_ENTRY( CPUMCTX, cr4),
246	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
247	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
248	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
249	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
250	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
251	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
252	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
253	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
254	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
255	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
256	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
257	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
258	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
259	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
260	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
261	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
262	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
263	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
264	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
265	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
266	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
267	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
268	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
269	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
270	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
271	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
272	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
273	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
274	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
275	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
276	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
277	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
278	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
279	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
280	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
281	SSMFIELD_ENTRY_TERM()
282	};
283
284	/** Saved state field descriptors for SVM nested hardware-virtualization
285	* Host State. */
286	static const SSMFIELD g_aSvmHwvirtHostState[] =
287	{
288	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
289	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
290	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
291	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
292	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
293	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
294	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
295	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
296	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
297	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
298	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
299	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
300	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
301	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
302	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
303	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
304	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
305	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
306	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
307	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
308	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
309	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
310	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
311	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
312	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
313	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
314	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
315	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
316	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
317	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
318	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
319	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
320	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
321	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
322	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
323	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
324	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
325	SSMFIELD_ENTRY_TERM()
326	};
327
328	/** Saved state field descriptors for CPUMCTX. */
329	static const SSMFIELD g_aCpumX87Fields[] =
330	{
331	SSMFIELD_ENTRY( X86FXSTATE, FCW),
332	SSMFIELD_ENTRY( X86FXSTATE, FSW),
333	SSMFIELD_ENTRY( X86FXSTATE, FTW),
334	SSMFIELD_ENTRY( X86FXSTATE, FOP),
335	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
336	SSMFIELD_ENTRY( X86FXSTATE, CS),
337	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
338	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
339	SSMFIELD_ENTRY( X86FXSTATE, DS),
340	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
341	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
342	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
343	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
344	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
345	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
346	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
347	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
348	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
349	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
350	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
351	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
352	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
353	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
354	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
355	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
356	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
357	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
358	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
359	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
360	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
361	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
362	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
363	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
364	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
365	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
366	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
367	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
368	SSMFIELD_ENTRY_TERM()
369	};
370
371	/** Saved state field descriptors for X86XSAVEHDR. */
372	static const SSMFIELD g_aCpumXSaveHdrFields[] =
373	{
374	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
375	SSMFIELD_ENTRY_TERM()
376	};
377
378	/** Saved state field descriptors for X86XSAVEYMMHI. */
379	static const SSMFIELD g_aCpumYmmHiFields[] =
380	{
381	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
382	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
383	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
384	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
385	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
386	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
387	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
388	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
389	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
390	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
391	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
392	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
393	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
394	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
395	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
396	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
397	SSMFIELD_ENTRY_TERM()
398	};
399
400	/** Saved state field descriptors for X86XSAVEBNDREGS. */
401	static const SSMFIELD g_aCpumBndRegsFields[] =
402	{
403	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
404	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
405	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
406	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
407	SSMFIELD_ENTRY_TERM()
408	};
409
410	/** Saved state field descriptors for X86XSAVEBNDCFG. */
411	static const SSMFIELD g_aCpumBndCfgFields[] =
412	{
413	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
414	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
415	SSMFIELD_ENTRY_TERM()
416	};
417
418	#if 0 /** @todo */
419	/** Saved state field descriptors for X86XSAVEOPMASK. */
420	static const SSMFIELD g_aCpumOpmaskFields[] =
421	{
422	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
423	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
424	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
425	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
426	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
427	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
428	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
429	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
430	SSMFIELD_ENTRY_TERM()
431	};
432	#endif
433
434	/** Saved state field descriptors for X86XSAVEZMMHI256. */
435	static const SSMFIELD g_aCpumZmmHi256Fields[] =
436	{
437	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
438	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
439	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
440	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
441	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
442	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
443	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
444	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
445	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
446	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
447	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
448	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
449	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
450	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
451	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
452	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
453	SSMFIELD_ENTRY_TERM()
454	};
455
456	/** Saved state field descriptors for X86XSAVEZMM16HI. */
457	static const SSMFIELD g_aCpumZmm16HiFields[] =
458	{
459	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
460	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
461	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
462	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
463	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
464	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
465	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
466	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
467	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
468	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
469	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
470	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
471	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
472	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
473	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
474	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
475	SSMFIELD_ENTRY_TERM()
476	};
477
478
479
480	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
481	* registeres changed. */
482	static const SSMFIELD g_aCpumX87FieldsMem[] =
483	{
484	SSMFIELD_ENTRY( X86FXSTATE, FCW),
485	SSMFIELD_ENTRY( X86FXSTATE, FSW),
486	SSMFIELD_ENTRY( X86FXSTATE, FTW),
487	SSMFIELD_ENTRY( X86FXSTATE, FOP),
488	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
489	SSMFIELD_ENTRY( X86FXSTATE, CS),
490	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
491	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
492	SSMFIELD_ENTRY( X86FXSTATE, DS),
493	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
494	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
495	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
496	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
497	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
498	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
499	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
500	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
501	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
502	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
503	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
504	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
505	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
506	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
507	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
508	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
509	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
510	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
511	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
512	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
513	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
514	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
515	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
516	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
517	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
518	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
519	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
520	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
521	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
522	};
523
524	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
525	* registeres changed. */
526	static const SSMFIELD g_aCpumCtxFieldsMem[] =
527	{
528	SSMFIELD_ENTRY( CPUMCTX, rdi),
529	SSMFIELD_ENTRY( CPUMCTX, rsi),
530	SSMFIELD_ENTRY( CPUMCTX, rbp),
531	SSMFIELD_ENTRY( CPUMCTX, rax),
532	SSMFIELD_ENTRY( CPUMCTX, rbx),
533	SSMFIELD_ENTRY( CPUMCTX, rdx),
534	SSMFIELD_ENTRY( CPUMCTX, rcx),
535	SSMFIELD_ENTRY( CPUMCTX, rsp),
536	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
537	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
538	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
539	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
540	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
541	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
542	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
543	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
544	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
545	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
546	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
547	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
548	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
549	SSMFIELD_ENTRY( CPUMCTX, rflags),
550	SSMFIELD_ENTRY( CPUMCTX, rip),
551	SSMFIELD_ENTRY( CPUMCTX, r8),
552	SSMFIELD_ENTRY( CPUMCTX, r9),
553	SSMFIELD_ENTRY( CPUMCTX, r10),
554	SSMFIELD_ENTRY( CPUMCTX, r11),
555	SSMFIELD_ENTRY( CPUMCTX, r12),
556	SSMFIELD_ENTRY( CPUMCTX, r13),
557	SSMFIELD_ENTRY( CPUMCTX, r14),
558	SSMFIELD_ENTRY( CPUMCTX, r15),
559	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
560	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
561	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
562	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
563	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
564	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
565	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
566	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
567	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
568	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
569	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
570	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
571	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
572	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
573	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
574	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
575	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
576	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
577	SSMFIELD_ENTRY( CPUMCTX, cr0),
578	SSMFIELD_ENTRY( CPUMCTX, cr2),
579	SSMFIELD_ENTRY( CPUMCTX, cr3),
580	SSMFIELD_ENTRY( CPUMCTX, cr4),
581	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
582	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
583	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
584	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
585	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
586	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
587	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
588	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
589	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
590	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
591	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
592	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
593	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
594	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
595	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
596	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
597	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
598	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
599	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
600	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
601	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
602	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
603	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
604	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
605	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
606	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
607	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
608	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
609	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
610	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
611	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
612	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
613	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
614	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
615	SSMFIELD_ENTRY_TERM()
616	};
617
618	/** Saved state field descriptors for CPUMCTX_VER1_6. */
619	static const SSMFIELD g_aCpumX87FieldsV16[] =
620	{
621	SSMFIELD_ENTRY( X86FXSTATE, FCW),
622	SSMFIELD_ENTRY( X86FXSTATE, FSW),
623	SSMFIELD_ENTRY( X86FXSTATE, FTW),
624	SSMFIELD_ENTRY( X86FXSTATE, FOP),
625	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
626	SSMFIELD_ENTRY( X86FXSTATE, CS),
627	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
628	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
629	SSMFIELD_ENTRY( X86FXSTATE, DS),
630	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
631	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
632	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
633	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
634	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
635	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
636	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
637	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
638	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
639	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
640	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
641	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
642	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
643	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
644	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
645	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
646	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
647	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
648	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
649	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
650	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
651	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
652	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
653	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
654	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
655	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
656	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
657	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
658	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
659	SSMFIELD_ENTRY_TERM()
660	};
661
662	/** Saved state field descriptors for CPUMCTX_VER1_6. */
663	static const SSMFIELD g_aCpumCtxFieldsV16[] =
664	{
665	SSMFIELD_ENTRY( CPUMCTX, rdi),
666	SSMFIELD_ENTRY( CPUMCTX, rsi),
667	SSMFIELD_ENTRY( CPUMCTX, rbp),
668	SSMFIELD_ENTRY( CPUMCTX, rax),
669	SSMFIELD_ENTRY( CPUMCTX, rbx),
670	SSMFIELD_ENTRY( CPUMCTX, rdx),
671	SSMFIELD_ENTRY( CPUMCTX, rcx),
672	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
673	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
674	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
675	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
676	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
677	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
678	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
679	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
680	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
681	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
682	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
683	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
684	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
685	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
686	SSMFIELD_ENTRY( CPUMCTX, rflags),
687	SSMFIELD_ENTRY( CPUMCTX, rip),
688	SSMFIELD_ENTRY( CPUMCTX, r8),
689	SSMFIELD_ENTRY( CPUMCTX, r9),
690	SSMFIELD_ENTRY( CPUMCTX, r10),
691	SSMFIELD_ENTRY( CPUMCTX, r11),
692	SSMFIELD_ENTRY( CPUMCTX, r12),
693	SSMFIELD_ENTRY( CPUMCTX, r13),
694	SSMFIELD_ENTRY( CPUMCTX, r14),
695	SSMFIELD_ENTRY( CPUMCTX, r15),
696	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
697	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
698	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
699	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
700	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
701	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
702	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
703	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
704	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
705	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
706	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
707	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
708	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
709	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
710	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
711	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
712	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
713	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
714	SSMFIELD_ENTRY( CPUMCTX, cr0),
715	SSMFIELD_ENTRY( CPUMCTX, cr2),
716	SSMFIELD_ENTRY( CPUMCTX, cr3),
717	SSMFIELD_ENTRY( CPUMCTX, cr4),
718	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
719	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
720	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
721	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
722	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
723	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
724	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
725	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
726	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
727	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
728	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
729	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
730	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
731	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
732	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
733	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
734	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
735	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
736	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
737	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
738	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
739	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
740	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
741	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
742	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
743	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
744	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
745	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
746	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
747	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
748	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
749	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
750	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
751	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
752	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
753	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
754	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
755	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
756	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
757	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
758	SSMFIELD_ENTRY_TERM()
759	};
760
761
762	/**
763	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
764	*
765	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
766	* (last instruction pointer, last data pointer, last opcode) except when the ES
767	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
768	* clear these registers there is potential, local FPU leakage from a process
769	* using the FPU to another.
770	*
771	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
772	*
773	* @param pVM The cross context VM structure.
774	*/
775	static void cpumR3CheckLeakyFpu(PVM pVM)
776	{
777	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
778	uint32_t const u32Family = u32CpuVersion >> 8;
779	if ( u32Family >= 6 /* K7 and higher */
780	&& ASMIsAmdCpu())
781	{
782	uint32_t cExt = ASMCpuId_EAX(0x80000000);
783	if (ASMIsValidExtRange(cExt))
784	{
785	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
786	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
787	{
788	for (VMCPUID i = 0; i < pVM->cCpus; i++)
789	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
790	Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
791	}
792	}
793	}
794	}
795
796
797	/**
798	* Frees memory allocated for the SVM hardware virtualization state.
799	*
800	* @param pVM The cross context VM structure.
801	*/
802	static void cpumR3FreeSvmHwVirtState(PVM pVM)
803	{
804	Assert(pVM->cpum.ro.GuestFeatures.fSvm);
805	for (VMCPUID i = 0; i < pVM->cCpus; i++)
806	{
807	PVMCPU pVCpu = &pVM->aCpus[i];
808	if (pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3)
809	{
810	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES);
811	pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3 = NULL;
812	}
813	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = NIL_RTHCPHYS;
814
815	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3)
816	{
817	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES);
818	pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3 = NULL;
819	}
820
821	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3)
822	{
823	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES);
824	pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3 = NULL;
825	}
826	}
827	}
828
829
830	/**
831	* Allocates memory for the SVM hardware virtualization state.
832	*
833	* @returns VBox status code.
834	* @param pVM The cross context VM structure.
835	*/
836	static int cpumR3AllocSvmHwVirtState(PVM pVM)
837	{
838	Assert(pVM->cpum.ro.GuestFeatures.fSvm);
839
840	int rc = VINF_SUCCESS;
841	LogRel(("CPUM: Allocating %u pages for the nested-guest SVM MSR and IO permission bitmaps\n",
842	pVM->cCpus * (SVM_MSRPM_PAGES + SVM_IOPM_PAGES)));
843	for (VMCPUID i = 0; i < pVM->cCpus; i++)
844	{
845	PVMCPU pVCpu = &pVM->aCpus[i];
846
847	/*
848	* Allocate the nested-guest VMCB.
849	*/
850	SUPPAGE SupNstGstVmcbPage;
851	RT_ZERO(SupNstGstVmcbPage);
852	SupNstGstVmcbPage.Phys = NIL_RTHCPHYS;
853	Assert(SVM_VMCB_PAGES == 1);
854	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
855	rc = SUPR3PageAllocEx(SVM_VMCB_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3,
856	&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR0, &SupNstGstVmcbPage);
857	if (RT_FAILURE(rc))
858	{
859	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
860	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCB\n", pVCpu->idCpu, SVM_VMCB_PAGES));
861	break;
862	}
863	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = SupNstGstVmcbPage.Phys;
864
865	/*
866	* Allocate the MSRPM (MSR Permission bitmap).
867	*/
868	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
869	rc = SUPR3PageAllocEx(SVM_MSRPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3,
870	&pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR0, NULL /* paPages */);
871	if (RT_FAILURE(rc))
872	{
873	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
874	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR permission bitmap\n", pVCpu->idCpu,
875	SVM_MSRPM_PAGES));
876	break;
877	}
878
879	/*
880	* Allocate the IOPM (IO Permission bitmap).
881	*/
882	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
883	rc = SUPR3PageAllocEx(SVM_IOPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3,
884	&pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR0, NULL /* paPages */);
885	if (RT_FAILURE(rc))
886	{
887	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
888	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's IO permission bitmap\n", pVCpu->idCpu,
889	SVM_IOPM_PAGES));
890	break;
891	}
892	}
893
894	/* On any failure, cleanup. */
895	if (RT_FAILURE(rc))
896	cpumR3FreeSvmHwVirtState(pVM);
897
898	return rc;
899	}
900
901
902	/**
903	* Displays the host and guest VMX features.
904	*
905	* @param pVM The cross context VM structure.
906	* @param pHlp The info helper functions.
907	* @param pszArgs "terse", "default" or "verbose".
908	*/
909	DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
910	{
911	RT_NOREF(pszArgs);
912	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
913	PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
914	if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
915	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA)
916	{
917	#define VMXFEATDUMP(a_szDesc, a_Var) \
918	pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
919
920	pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
921	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
922	VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
923	/* Basic. */
924	VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
925	/* Pin-based controls. */
926	VMXFEATDUMP("ExtIntExit - External interrupt VM-exit ", fVmxExtIntExit);
927	VMXFEATDUMP("NmiExit - NMI VM-exit ", fVmxNmiExit);
928	VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
929	VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
930	/* Processor-based controls. */
931	VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
932	VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
933	VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
934	VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
935	VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
936	VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
937	VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
938	VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
939	VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
940	VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
941	VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
942	VMXFEATDUMP("TprShadow - TPR shadow ", fVmxTprShadow);
943	VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
944	VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
945	VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
946	VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
947	VMXFEATDUMP("MonitorTrapFlag - Monitor trap flag ", fVmxMonitorTrapFlag);
948	VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
949	VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
950	VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
951	VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
952	/* Secondary processor-based controls. */
953	VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
954	VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
955	VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
956	VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
957	VMXFEATDUMP("VirtX2Apic - Virtualize-x2APIC accesses ", fVmxVirtX2ApicAccess);
958	VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
959	VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
960	VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
961	VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
962	VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
963	/* VM-entry controls. */
964	VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
965	VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
966	VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER on VM-entry ", fVmxEntryLoadEferMsr);
967	/* VM-exit controls. */
968	VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
969	VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
970	VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
971	VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER on VM-exit ", fVmxExitSaveEferMsr);
972	VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER on VM-exit ", fVmxExitLoadEferMsr);
973	VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
974	VMXFEATDUMP("ExitStoreEferLma - Store EFER.LMA on VM-exit ", fVmxExitStoreEferLma);
975	VMXFEATDUMP("VmwriteAll - VMWRITE to any VMCS field ", fVmxVmwriteAll);
976	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
977	#undef VMXFEATDUMP
978	}
979	else
980	pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
981	}
982
983
984	/**
985	* Initializes VMX host and guest features.
986	*
987	* @param pVM The cross context VM structure.
988	*
989	* @remarks This must be called only after HM has fully initialized since it calls
990	* into HM to retrieve VMX and related MSRs.
991	*/
992	static void cpumR3InitVmxCpuFeatures(PVM pVM)
993	{
994	/*
995	* Init. host features.
996	*/
997	PCPUMFEATURES pHostFeat = &pVM->cpum.s.HostFeatures;
998	VMXMSRS VmxMsrs;
999	int rc = HMVmxGetHostMsrs(pVM, &VmxMsrs);
1000	if (RT_SUCCESS(rc))
1001	{
1002	/* Basic information. */
1003	pHostFeat->fVmxInsOutInfo = RT_BF_GET(VmxMsrs.u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1004
1005	/* Pin-based VM-execution controls. */
1006	uint32_t const fPinCtls = VmxMsrs.PinCtls.n.allowed1;
1007	pHostFeat->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1008	pHostFeat->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1009	pHostFeat->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1010	pHostFeat->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1011
1012	/* Processor-based VM-execution controls. */
1013	uint32_t const fProcCtls = VmxMsrs.ProcCtls.n.allowed1;
1014	pHostFeat->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1015	pHostFeat->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1016	pHostFeat->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1017	pHostFeat->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1018	pHostFeat->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1019	pHostFeat->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1020	pHostFeat->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1021	pHostFeat->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1022	pHostFeat->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1023	pHostFeat->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1024	pHostFeat->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1025	pHostFeat->fVmxTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1026	pHostFeat->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1027	pHostFeat->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1028	pHostFeat->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1029	pHostFeat->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1030	pHostFeat->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1031	pHostFeat->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1032	pHostFeat->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1033	pHostFeat->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1034	pHostFeat->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1035
1036	/* Secondary processor-based VM-execution controls. */
1037	if (pHostFeat->fVmxSecondaryExecCtls)
1038	{
1039	uint32_t const fProcCtls2 = VmxMsrs.ProcCtls2.n.allowed1;
1040	pHostFeat->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1041	pHostFeat->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1042	pHostFeat->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1043	pHostFeat->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1044	pHostFeat->fVmxVirtX2ApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_ACCESS);
1045	pHostFeat->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1046	pHostFeat->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1047	pHostFeat->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1048	pHostFeat->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1049	pHostFeat->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1050	}
1051
1052	/* VM-entry controls. */
1053	uint32_t const fEntryCtls = VmxMsrs.EntryCtls.n.allowed1;
1054	pHostFeat->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1055	pHostFeat->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1056	pHostFeat->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1057
1058	/* VM-exit controls. */
1059	uint32_t const fExitCtls = VmxMsrs.ExitCtls.n.allowed1;
1060	pHostFeat->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1061	pHostFeat->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1062	pHostFeat->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1063	pHostFeat->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1064	pHostFeat->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1065	pHostFeat->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_VMX_PREEMPT_TIMER);
1066
1067	/* Miscellaneous data. */
1068	uint32_t const fMiscData = VmxMsrs.u64Misc;
1069	pHostFeat->fVmxExitStoreEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_STORE_EFER_LMA);
1070	pHostFeat->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1071	pHostFeat->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1072	}
1073
1074	/*
1075	* Initialize the set of VMX features we emulate.
1076	* Note! Some bits might be reported as 1 always if they fall under the default1 class bits
1077	* (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1078	*/
1079	CPUMFEATURES EmuFeat;
1080	RT_ZERO(EmuFeat);
1081	EmuFeat.fVmx = 1;
1082	EmuFeat.fVmxInsOutInfo = 0;
1083	EmuFeat.fVmxExtIntExit = 1;
1084	EmuFeat.fVmxNmiExit = 1;
1085	EmuFeat.fVmxVirtNmi = 0;
1086	EmuFeat.fVmxPreemptTimer = 0;
1087	EmuFeat.fVmxIntWindowExit = 1;
1088	EmuFeat.fVmxTscOffsetting = 1;
1089	EmuFeat.fVmxHltExit = 1;
1090	EmuFeat.fVmxInvlpgExit = 1;
1091	EmuFeat.fVmxMwaitExit = 1;
1092	EmuFeat.fVmxRdpmcExit = 1;
1093	EmuFeat.fVmxRdtscExit = 1;
1094	EmuFeat.fVmxCr3LoadExit = 1;
1095	EmuFeat.fVmxCr3StoreExit = 1;
1096	EmuFeat.fVmxCr8LoadExit = 1;
1097	EmuFeat.fVmxCr8StoreExit = 1;
1098	EmuFeat.fVmxTprShadow = 0;
1099	EmuFeat.fVmxNmiWindowExit = 0;
1100	EmuFeat.fVmxMovDRxExit = 1;
1101	EmuFeat.fVmxUncondIoExit = 1;
1102	EmuFeat.fVmxUseIoBitmaps = 1;
1103	EmuFeat.fVmxMonitorTrapFlag = 0;
1104	EmuFeat.fVmxUseMsrBitmaps = 0;
1105	EmuFeat.fVmxMonitorExit = 1;
1106	EmuFeat.fVmxPauseExit = 1;
1107	EmuFeat.fVmxSecondaryExecCtls = 1;
1108	EmuFeat.fVmxVirtApicAccess = 0;
1109	EmuFeat.fVmxEpt = 0;
1110	EmuFeat.fVmxDescTableExit = 1;
1111	EmuFeat.fVmxRdtscp = 1;
1112	EmuFeat.fVmxVirtX2ApicAccess = 0;
1113	EmuFeat.fVmxVpid = 0;
1114	EmuFeat.fVmxWbinvdExit = 1;
1115	EmuFeat.fVmxUnrestrictedGuest = 0;
1116	EmuFeat.fVmxPauseLoopExit = 0;
1117	EmuFeat.fVmxInvpcid = 1;
1118	EmuFeat.fVmxEntryLoadDebugCtls = 1;
1119	EmuFeat.fVmxIa32eModeGuest = 1;
1120	EmuFeat.fVmxEntryLoadEferMsr = 1;
1121	EmuFeat.fVmxExitSaveDebugCtls = 1;
1122	EmuFeat.fVmxHostAddrSpaceSize = 1;
1123	EmuFeat.fVmxExitAckExtInt = 0;
1124	EmuFeat.fVmxExitSaveEferMsr = 1;
1125	EmuFeat.fVmxExitLoadEferMsr = 1;
1126	EmuFeat.fVmxSavePreemptTimer = 0;
1127	EmuFeat.fVmxExitStoreEferLma = 1;
1128	EmuFeat.fVmxVmwriteAll = 0;
1129	EmuFeat.fVmxEntryInjectSoftInt = 0;
1130
1131	/*
1132	* Explode guest features.
1133	*
1134	* When hardware-assisted VMX may be used, any feature we emulate must also be supported
1135	* by the hardware, hence we merge our emulated features with the host features below.
1136	*/
1137	bool const fHostSupportsVmx = pHostFeat->fVmx;
1138	AssertLogRelReturnVoid(!fHostSupportsVmx \|\| HMIsVmxSupported(pVM));
1139	PCCPUMFEATURES pBaseFeat = fHostSupportsVmx ? pHostFeat : &EmuFeat;
1140	PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1141	pGuestFeat->fVmx = (pBaseFeat->fVmx & EmuFeat.fVmx );
1142	pGuestFeat->fVmxInsOutInfo = (pBaseFeat->fVmxInsOutInfo & EmuFeat.fVmxInsOutInfo );
1143	pGuestFeat->fVmxExtIntExit = (pBaseFeat->fVmxExtIntExit & EmuFeat.fVmxExtIntExit );
1144	pGuestFeat->fVmxNmiExit = (pBaseFeat->fVmxNmiExit & EmuFeat.fVmxNmiExit );
1145	pGuestFeat->fVmxVirtNmi = (pBaseFeat->fVmxVirtNmi & EmuFeat.fVmxVirtNmi );
1146	pGuestFeat->fVmxPreemptTimer = (pBaseFeat->fVmxPreemptTimer & EmuFeat.fVmxPreemptTimer );
1147	pGuestFeat->fVmxIntWindowExit = (pBaseFeat->fVmxIntWindowExit & EmuFeat.fVmxIntWindowExit );
1148	pGuestFeat->fVmxTscOffsetting = (pBaseFeat->fVmxTscOffsetting & EmuFeat.fVmxTscOffsetting );
1149	pGuestFeat->fVmxHltExit = (pBaseFeat->fVmxHltExit & EmuFeat.fVmxHltExit );
1150	pGuestFeat->fVmxInvlpgExit = (pBaseFeat->fVmxInvlpgExit & EmuFeat.fVmxInvlpgExit );
1151	pGuestFeat->fVmxMwaitExit = (pBaseFeat->fVmxMwaitExit & EmuFeat.fVmxMwaitExit );
1152	pGuestFeat->fVmxRdpmcExit = (pBaseFeat->fVmxRdpmcExit & EmuFeat.fVmxRdpmcExit );
1153	pGuestFeat->fVmxRdtscExit = (pBaseFeat->fVmxRdtscExit & EmuFeat.fVmxRdtscExit );
1154	pGuestFeat->fVmxCr3LoadExit = (pBaseFeat->fVmxCr3LoadExit & EmuFeat.fVmxCr3LoadExit );
1155	pGuestFeat->fVmxCr3StoreExit = (pBaseFeat->fVmxCr3StoreExit & EmuFeat.fVmxCr3StoreExit );
1156	pGuestFeat->fVmxCr8LoadExit = (pBaseFeat->fVmxCr8LoadExit & EmuFeat.fVmxCr8LoadExit );
1157	pGuestFeat->fVmxCr8StoreExit = (pBaseFeat->fVmxCr8StoreExit & EmuFeat.fVmxCr8StoreExit );
1158	pGuestFeat->fVmxTprShadow = (pBaseFeat->fVmxTprShadow & EmuFeat.fVmxTprShadow );
1159	pGuestFeat->fVmxNmiWindowExit = (pBaseFeat->fVmxNmiWindowExit & EmuFeat.fVmxNmiWindowExit );
1160	pGuestFeat->fVmxMovDRxExit = (pBaseFeat->fVmxMovDRxExit & EmuFeat.fVmxMovDRxExit );
1161	pGuestFeat->fVmxUncondIoExit = (pBaseFeat->fVmxUncondIoExit & EmuFeat.fVmxUncondIoExit );
1162	pGuestFeat->fVmxUseIoBitmaps = (pBaseFeat->fVmxUseIoBitmaps & EmuFeat.fVmxUseIoBitmaps );
1163	pGuestFeat->fVmxMonitorTrapFlag = (pBaseFeat->fVmxMonitorTrapFlag & EmuFeat.fVmxMonitorTrapFlag );
1164	pGuestFeat->fVmxUseMsrBitmaps = (pBaseFeat->fVmxUseMsrBitmaps & EmuFeat.fVmxUseMsrBitmaps );
1165	pGuestFeat->fVmxMonitorExit = (pBaseFeat->fVmxMonitorExit & EmuFeat.fVmxMonitorExit );
1166	pGuestFeat->fVmxPauseExit = (pBaseFeat->fVmxPauseExit & EmuFeat.fVmxPauseExit );
1167	pGuestFeat->fVmxSecondaryExecCtls = (pBaseFeat->fVmxSecondaryExecCtls & EmuFeat.fVmxSecondaryExecCtls );
1168	pGuestFeat->fVmxVirtApicAccess = (pBaseFeat->fVmxVirtApicAccess & EmuFeat.fVmxVirtApicAccess );
1169	pGuestFeat->fVmxEpt = (pBaseFeat->fVmxEpt & EmuFeat.fVmxEpt );
1170	pGuestFeat->fVmxDescTableExit = (pBaseFeat->fVmxDescTableExit & EmuFeat.fVmxDescTableExit );
1171	pGuestFeat->fVmxRdtscp = (pBaseFeat->fVmxRdtscp & EmuFeat.fVmxRdtscp );
1172	pGuestFeat->fVmxVirtX2ApicAccess = (pBaseFeat->fVmxVirtX2ApicAccess & EmuFeat.fVmxVirtX2ApicAccess );
1173	pGuestFeat->fVmxVpid = (pBaseFeat->fVmxVpid & EmuFeat.fVmxVpid );
1174	pGuestFeat->fVmxWbinvdExit = (pBaseFeat->fVmxWbinvdExit & EmuFeat.fVmxWbinvdExit );
1175	pGuestFeat->fVmxUnrestrictedGuest = (pBaseFeat->fVmxUnrestrictedGuest & EmuFeat.fVmxUnrestrictedGuest );
1176	pGuestFeat->fVmxPauseLoopExit = (pBaseFeat->fVmxPauseLoopExit & EmuFeat.fVmxPauseLoopExit );
1177	pGuestFeat->fVmxInvpcid = (pBaseFeat->fVmxInvpcid & EmuFeat.fVmxInvpcid );
1178	pGuestFeat->fVmxEntryLoadDebugCtls = (pBaseFeat->fVmxEntryLoadDebugCtls & EmuFeat.fVmxEntryLoadDebugCtls );
1179	pGuestFeat->fVmxIa32eModeGuest = (pBaseFeat->fVmxIa32eModeGuest & EmuFeat.fVmxIa32eModeGuest );
1180	pGuestFeat->fVmxEntryLoadEferMsr = (pBaseFeat->fVmxEntryLoadEferMsr & EmuFeat.fVmxEntryLoadEferMsr);
1181	pGuestFeat->fVmxExitSaveDebugCtls = (pBaseFeat->fVmxExitSaveDebugCtls & EmuFeat.fVmxExitSaveDebugCtls );
1182	pGuestFeat->fVmxHostAddrSpaceSize = (pBaseFeat->fVmxHostAddrSpaceSize & EmuFeat.fVmxHostAddrSpaceSize );
1183	pGuestFeat->fVmxExitAckExtInt = (pBaseFeat->fVmxExitAckExtInt & EmuFeat.fVmxExitAckExtInt );
1184	pGuestFeat->fVmxExitSaveEferMsr = (pBaseFeat->fVmxExitSaveEferMsr & EmuFeat.fVmxExitSaveEferMsr );
1185	pGuestFeat->fVmxExitLoadEferMsr = (pBaseFeat->fVmxExitLoadEferMsr & EmuFeat.fVmxExitLoadEferMsr );
1186	pGuestFeat->fVmxSavePreemptTimer = (pBaseFeat->fVmxSavePreemptTimer & EmuFeat.fVmxSavePreemptTimer );
1187	pGuestFeat->fVmxExitStoreEferLma = (pBaseFeat->fVmxExitStoreEferLma & EmuFeat.fVmxExitStoreEferLma );
1188	pGuestFeat->fVmxVmwriteAll = (pBaseFeat->fVmxVmwriteAll & EmuFeat.fVmxVmwriteAll );
1189	pGuestFeat->fVmxEntryInjectSoftInt = (pBaseFeat->fVmxEntryInjectSoftInt & EmuFeat.fVmxEntryInjectSoftInt );
1190	}
1191
1192
1193	/**
1194	* Initializes the CPUM.
1195	*
1196	* @returns VBox status code.
1197	* @param pVM The cross context VM structure.
1198	*/
1199	VMMR3DECL(int) CPUMR3Init(PVM pVM)
1200	{
1201	LogFlow(("CPUMR3Init\n"));
1202
1203	/*
1204	* Assert alignment, sizes and tables.
1205	*/
1206	AssertCompileMemberAlignment(VM, cpum.s, 32);
1207	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
1208	AssertCompileSizeAlignment(CPUMCTX, 64);
1209	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
1210	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
1211	AssertCompileMemberAlignment(VM, cpum, 64);
1212	AssertCompileMemberAlignment(VM, aCpus, 64);
1213	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
1214	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
1215	#ifdef VBOX_STRICT
1216	int rc2 = cpumR3MsrStrictInitChecks();
1217	AssertRCReturn(rc2, rc2);
1218	#endif
1219
1220	/*
1221	* Initialize offsets.
1222	*/
1223
1224	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
1225	pVM->cpum.s.offCPUMCPU0 = RT_UOFFSETOF(VM, aCpus[0].cpum) - RT_UOFFSETOF(VM, cpum);
1226	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
1227
1228
1229	/* Calculate the offset from CPUMCPU to CPUM. */
1230	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1231	{
1232	PVMCPU pVCpu = &pVM->aCpus[i];
1233
1234	pVCpu->cpum.s.offCPUM = RT_UOFFSETOF_DYN(VM, aCpus[i].cpum) - RT_UOFFSETOF(VM, cpum);
1235	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
1236	}
1237
1238	/*
1239	* Gather info about the host CPU.
1240	*/
1241	if (!ASMHasCpuId())
1242	{
1243	Log(("The CPU doesn't support CPUID!\n"));
1244	return VERR_UNSUPPORTED_CPU;
1245	}
1246
1247	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
1248
1249	PCPUMCPUIDLEAF paLeaves;
1250	uint32_t cLeaves;
1251	int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
1252	AssertLogRelRCReturn(rc, rc);
1253
1254	rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
1255	RTMemFree(paLeaves);
1256	AssertLogRelRCReturn(rc, rc);
1257	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
1258
1259	/*
1260	* Check that the CPU supports the minimum features we require.
1261	*/
1262	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
1263	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
1264	if (!pVM->cpum.s.HostFeatures.fMmx)
1265	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
1266	if (!pVM->cpum.s.HostFeatures.fTsc)
1267	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
1268
1269	/*
1270	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
1271	*/
1272	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
1273	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
1274
1275	/*
1276	* Figure out which XSAVE/XRSTOR features are available on the host.
1277	*/
1278	uint64_t fXcr0Host = 0;
1279	uint64_t fXStateHostMask = 0;
1280	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
1281	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
1282	{
1283	fXStateHostMask = fXcr0Host = ASMGetXcr0();
1284	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
1285	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
1286	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
1287	}
1288	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
1289	if (VM_IS_RAW_MODE_ENABLED(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
1290	fXStateHostMask = 0;
1291	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
1292	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
1293
1294	/*
1295	* Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
1296	*/
1297	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
1298	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
1299	AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
1300
1301	uint8_t *pbXStates;
1302	rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
1303	MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
1304	AssertLogRelRCReturn(rc, rc);
1305
1306	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1307	{
1308	PVMCPU pVCpu = &pVM->aCpus[i];
1309
1310	pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
1311	pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
1312	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
1313	pbXStates += cbMaxXState;
1314
1315	pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
1316	pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
1317	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
1318	pbXStates += cbMaxXState;
1319
1320	pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
1321	pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
1322	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
1323	pbXStates += cbMaxXState;
1324
1325	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
1326	}
1327
1328	/*
1329	* Register saved state data item.
1330	*/
1331	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
1332	NULL, cpumR3LiveExec, NULL,
1333	NULL, cpumR3SaveExec, NULL,
1334	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
1335	if (RT_FAILURE(rc))
1336	return rc;
1337
1338	/*
1339	* Register info handlers and registers with the debugger facility.
1340	*/
1341	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
1342	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
1343	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
1344	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
1345	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
1346	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
1347	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
1348	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
1349	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
1350	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
1351	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
1352	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
1353	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
1354	DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
1355	&cpumR3InfoVmxFeatures);
1356
1357	rc = cpumR3DbgInit(pVM);
1358	if (RT_FAILURE(rc))
1359	return rc;
1360
1361	/*
1362	* Check if we need to workaround partial/leaky FPU handling.
1363	*/
1364	cpumR3CheckLeakyFpu(pVM);
1365
1366	/*
1367	* Initialize the Guest CPUID and MSR states.
1368	*/
1369	rc = cpumR3InitCpuIdAndMsrs(pVM);
1370	if (RT_FAILURE(rc))
1371	return rc;
1372
1373	/*
1374	* Allocate memory required by the guest hardware virtualization state.
1375	*/
1376	if (pVM->cpum.ro.GuestFeatures.fSvm)
1377	{
1378	rc = cpumR3AllocSvmHwVirtState(pVM);
1379	if (RT_FAILURE(rc))
1380	return rc;
1381	}
1382
1383	/*
1384	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
1385	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1386	* of processors from (cpuid(4).eax >> 26) + 1.
1387	*
1388	* Note: this code is obsolete, but let's keep it here for reference.
1389	* Purpose is valid when we artificially cap the max std id to less than 4.
1390	*
1391	* Note: This used to be a separate function CPUMR3SetHwVirt that was called
1392	* after VMINITCOMPLETED_HM.
1393	*/
1394	if (VM_IS_RAW_MODE_ENABLED(pVM))
1395	{
1396	Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
1397	\|\| pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
1398	pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
1399	}
1400
1401	CPUMR3Reset(pVM);
1402	return VINF_SUCCESS;
1403	}
1404
1405
1406	/**
1407	* Applies relocations to data and code managed by this
1408	* component. This function will be called at init and
1409	* whenever the VMM need to relocate it self inside the GC.
1410	*
1411	* The CPUM will update the addresses used by the switcher.
1412	*
1413	* @param pVM The cross context VM structure.
1414	*/
1415	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
1416	{
1417	LogFlow(("CPUMR3Relocate\n"));
1418
1419	pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
1420	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
1421
1422	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1423	{
1424	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1425	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
1426	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
1427	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
1428
1429	/* Recheck the guest DRx values in raw-mode. */
1430	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
1431	}
1432	}
1433
1434
1435	/**
1436	* Terminates the CPUM.
1437	*
1438	* Termination means cleaning up and freeing all resources,
1439	* the VM it self is at this point powered off or suspended.
1440	*
1441	* @returns VBox status code.
1442	* @param pVM The cross context VM structure.
1443	*/
1444	VMMR3DECL(int) CPUMR3Term(PVM pVM)
1445	{
1446	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1447	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1448	{
1449	PVMCPU pVCpu = &pVM->aCpus[i];
1450	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1451
1452	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1453	pVCpu->cpum.s.uMagic = 0;
1454	pCtx->dr[5] = 0;
1455	}
1456	#endif
1457
1458	if (pVM->cpum.ro.GuestFeatures.fSvm)
1459	cpumR3FreeSvmHwVirtState(pVM);
1460	return VINF_SUCCESS;
1461	}
1462
1463
1464	/**
1465	* Resets a virtual CPU.
1466	*
1467	* Used by CPUMR3Reset and CPU hot plugging.
1468	*
1469	* @param pVM The cross context VM structure.
1470	* @param pVCpu The cross context virtual CPU structure of the CPU that is
1471	* being reset. This may differ from the current EMT.
1472	*/
1473	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
1474	{
1475	/** @todo anything different for VCPU > 0? */
1476	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1477
1478	/*
1479	* Initialize everything to ZERO first.
1480	*/
1481	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1482
1483	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
1484	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
1485	memset(pCtx, 0, RT_UOFFSETOF(CPUMCTX, pXStateR0));
1486
1487	pVCpu->cpum.s.fUseFlags = fUseFlags;
1488
1489	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
1490	pCtx->eip = 0x0000fff0;
1491	pCtx->edx = 0x00000600; /* P6 processor */
1492	pCtx->eflags.Bits.u1Reserved0 = 1;
1493
1494	pCtx->cs.Sel = 0xf000;
1495	pCtx->cs.ValidSel = 0xf000;
1496	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1497	pCtx->cs.u64Base = UINT64_C(0xffff0000);
1498	pCtx->cs.u32Limit = 0x0000ffff;
1499	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1500	pCtx->cs.Attr.n.u1Present = 1;
1501	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1502
1503	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1504	pCtx->ds.u32Limit = 0x0000ffff;
1505	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1506	pCtx->ds.Attr.n.u1Present = 1;
1507	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1508
1509	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1510	pCtx->es.u32Limit = 0x0000ffff;
1511	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1512	pCtx->es.Attr.n.u1Present = 1;
1513	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1514
1515	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1516	pCtx->fs.u32Limit = 0x0000ffff;
1517	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1518	pCtx->fs.Attr.n.u1Present = 1;
1519	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1520
1521	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1522	pCtx->gs.u32Limit = 0x0000ffff;
1523	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1524	pCtx->gs.Attr.n.u1Present = 1;
1525	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1526
1527	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1528	pCtx->ss.u32Limit = 0x0000ffff;
1529	pCtx->ss.Attr.n.u1Present = 1;
1530	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1531	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1532
1533	pCtx->idtr.cbIdt = 0xffff;
1534	pCtx->gdtr.cbGdt = 0xffff;
1535
1536	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1537	pCtx->ldtr.u32Limit = 0xffff;
1538	pCtx->ldtr.Attr.n.u1Present = 1;
1539	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1540
1541	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1542	pCtx->tr.u32Limit = 0xffff;
1543	pCtx->tr.Attr.n.u1Present = 1;
1544	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1545
1546	pCtx->dr[6] = X86_DR6_INIT_VAL;
1547	pCtx->dr[7] = X86_DR7_INIT_VAL;
1548
1549	PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
1550	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
1551	pFpuCtx->FCW = 0x37f;
1552
1553	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1554	IA-32 Processor States Following Power-up, Reset, or INIT */
1555	pFpuCtx->MXCSR = 0x1F80;
1556	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
1557
1558	pCtx->aXcr[0] = XSAVE_C_X87;
1559	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
1560	{
1561	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
1562	as we don't know what happened before. (Bother optimize later?) */
1563	pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
1564	}
1565
1566	/*
1567	* MSRs.
1568	*/
1569	/* Init PAT MSR */
1570	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
1571
1572	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1573	* The Intel docs don't mention it. */
1574	Assert(!pCtx->msrEFER);
1575
1576	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
1577	is supposed to be here, just trying provide useful/sensible values. */
1578	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
1579	if (pRange)
1580	{
1581	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1582	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1583	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
1584	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
1585	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1586	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
1587	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1588	}
1589
1590	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1591
1592	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1593	* called from each EMT while we're getting called by CPUMR3Reset()
1594	* iteratively on the same thread. Fix later. */
1595	#if 0 /** @todo r=bird: This we will do in TM, not here. */
1596	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1597	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1598	#endif
1599
1600
1601	/* C-state control. Guesses. */
1602	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
1603	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
1604	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
1605	* functionality. The default value must be different due to incompatible write mask.
1606	*/
1607	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
1608	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
1609	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
1610	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
1611
1612	/*
1613	* Hardware virtualization state.
1614	*/
1615	pCtx->hwvirt.fGif = true;
1616
1617	/* SVM. */
1618	if (pCtx->hwvirt.svm.CTX_SUFF(pVmcb))
1619	{
1620	memset(pCtx->hwvirt.svm.CTX_SUFF(pVmcb), 0, SVM_VMCB_PAGES << PAGE_SHIFT);
1621	pCtx->hwvirt.svm.uMsrHSavePa = 0;
1622	pCtx->hwvirt.svm.uPrevPauseTick = 0;
1623	}
1624	}
1625
1626
1627	/**
1628	* Resets the CPU.
1629	*
1630	* @returns VINF_SUCCESS.
1631	* @param pVM The cross context VM structure.
1632	*/
1633	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1634	{
1635	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1636	{
1637	CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
1638
1639	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1640	PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1641
1642	/* Magic marker for searching in crash dumps. */
1643	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1644	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1645	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1646	#endif
1647	}
1648	}
1649
1650
1651
1652
1653	/**
1654	* Pass 0 live exec callback.
1655	*
1656	* @returns VINF_SSM_DONT_CALL_AGAIN.
1657	* @param pVM The cross context VM structure.
1658	* @param pSSM The saved state handle.
1659	* @param uPass The pass (0).
1660	*/
1661	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1662	{
1663	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
1664	cpumR3SaveCpuId(pVM, pSSM);
1665	return VINF_SSM_DONT_CALL_AGAIN;
1666	}
1667
1668
1669	/**
1670	* Execute state save operation.
1671	*
1672	* @returns VBox status code.
1673	* @param pVM The cross context VM structure.
1674	* @param pSSM SSM operation handle.
1675	*/
1676	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1677	{
1678	/*
1679	* Save.
1680	*/
1681	SSMR3PutU32(pSSM, pVM->cCpus);
1682	SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
1683	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1684	{
1685	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1686
1687	SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1688
1689	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1690	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1691	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1692	if (pGstCtx->fXStateMask != 0)
1693	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
1694	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1695	{
1696	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1697	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1698	}
1699	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1700	{
1701	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1702	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1703	}
1704	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1705	{
1706	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1707	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1708	}
1709	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1710	{
1711	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1712	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1713	}
1714	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1715	{
1716	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1717	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1718	}
1719	if (pVM->cpum.ro.GuestFeatures.fSvm)
1720	{
1721	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
1722	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
1723	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
1724	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
1725	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
1726	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
1727	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
1728	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
1729	g_aSvmHwvirtHostState, NULL /* pvUser */);
1730	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
1731	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1732	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
1733	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fLocalForcedActions);
1734	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
1735	}
1736	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1737	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1738	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
1739	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
1740	}
1741
1742	cpumR3SaveCpuId(pVM, pSSM);
1743	return VINF_SUCCESS;
1744	}
1745
1746
1747	/**
1748	* @callback_method_impl{FNSSMINTLOADPREP}
1749	*/
1750	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1751	{
1752	NOREF(pSSM);
1753	pVM->cpum.s.fPendingRestore = true;
1754	return VINF_SUCCESS;
1755	}
1756
1757
1758	/**
1759	* @callback_method_impl{FNSSMINTLOADEXEC}
1760	*/
1761	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1762	{
1763	int rc; /* Only for AssertRCReturn use. */
1764
1765	/*
1766	* Validate version.
1767	*/
1768	if ( uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
1769	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
1770	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
1771	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
1772	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
1773	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
1774	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
1775	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
1776	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1777	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1778	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1779	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1780	{
1781	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1782	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1783	}
1784
1785	if (uPass == SSM_PASS_FINAL)
1786	{
1787	/*
1788	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1789	* really old SSM file versions.)
1790	*/
1791	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1792	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1793	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1794	SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1795
1796	/*
1797	* Figure x86 and ctx field definitions to use for older states.
1798	*/
1799	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
1800	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
1801	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
1802	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1803	{
1804	paCpumCtx1Fields = g_aCpumX87FieldsV16;
1805	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
1806	}
1807	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1808	{
1809	paCpumCtx1Fields = g_aCpumX87FieldsMem;
1810	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
1811	}
1812
1813	/*
1814	* The hyper state used to preceed the CPU count. Starting with
1815	* XSAVE it was moved down till after we've got the count.
1816	*/
1817	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
1818	{
1819	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1820	{
1821	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1822	X86FXSTATE Ign;
1823	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1824	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1825	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1826	SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
1827	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1828	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1829	pVCpu->cpum.s.Hyper.rsp = uRSP;
1830	}
1831	}
1832
1833	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1834	{
1835	uint32_t cCpus;
1836	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1837	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1838	VERR_SSM_UNEXPECTED_DATA);
1839	}
1840	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
1841	\|\| pVM->cCpus == 1,
1842	("cCpus=%u\n", pVM->cCpus),
1843	VERR_SSM_UNEXPECTED_DATA);
1844
1845	uint32_t cbMsrs = 0;
1846	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1847	{
1848	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
1849	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
1850	VERR_SSM_UNEXPECTED_DATA);
1851	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
1852	VERR_SSM_UNEXPECTED_DATA);
1853	}
1854
1855	/*
1856	* Do the per-CPU restoring.
1857	*/
1858	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1859	{
1860	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1861	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1862
1863	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
1864	{
1865	/*
1866	* The XSAVE saved state layout moved the hyper state down here.
1867	*/
1868	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1869	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1870	rc = SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1871	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1872	pVCpu->cpum.s.Hyper.rsp = uRSP;
1873	AssertRCReturn(rc, rc);
1874
1875	/*
1876	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
1877	*/
1878	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1879	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1880	AssertRCReturn(rc, rc);
1881
1882	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
1883	if (pGstCtx->fXStateMask != 0)
1884	{
1885	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
1886	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
1887	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
1888	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
1889	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
1890	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1891	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
1892	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1893	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
1894	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
1895	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
1896	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1897	}
1898
1899	/* Check that the XCR0 mask is valid (invalid results in #GP). */
1900	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
1901	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
1902	{
1903	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
1904	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
1905	VERR_CPUM_INVALID_XCR0);
1906	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
1907	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1908	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
1909	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1910	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
1911	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
1912	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
1913	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1914	}
1915
1916	/* Check that the XCR1 is zero, as we don't implement it yet. */
1917	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
1918
1919	/*
1920	* Restore the individual extended state components we support.
1921	*/
1922	if (pGstCtx->fXStateMask != 0)
1923	{
1924	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
1925	0, g_aCpumXSaveHdrFields, NULL);
1926	AssertRCReturn(rc, rc);
1927	AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
1928	("bmXState=%#RX64 fXStateMask=%#RX64\n",
1929	pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
1930	VERR_CPUM_INVALID_XSAVE_HDR);
1931	}
1932	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1933	{
1934	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
1935	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1936	}
1937	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1938	{
1939	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
1940	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1941	}
1942	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1943	{
1944	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
1945	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1946	}
1947	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1948	{
1949	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
1950	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1951	}
1952	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1953	{
1954	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
1955	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1956	}
1957	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
1958	{
1959	if (pVM->cpum.ro.GuestFeatures.fSvm)
1960	{
1961	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
1962	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
1963	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
1964	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
1965	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
1966	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
1967	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
1968	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
1969	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
1970	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
1971	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1972	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
1973	SSMR3GetU32(pSSM, &pGstCtx->hwvirt.fLocalForcedActions);
1974	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
1975	}
1976	}
1977	}
1978	else
1979	{
1980	/*
1981	* Pre XSAVE saved state.
1982	*/
1983	SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
1984	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1985	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1986	}
1987
1988	/*
1989	* Restore a couple of flags and the MSRs.
1990	*/
1991	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
1992	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
1993
1994	rc = VINF_SUCCESS;
1995	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1996	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
1997	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1998	{
1999	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2000	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2001	}
2002	AssertRCReturn(rc, rc);
2003
2004	/* REM and other may have cleared must-be-one fields in DR6 and
2005	DR7, fix these. */
2006	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
2007	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
2008	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
2009	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
2010	}
2011
2012	/* Older states does not have the internal selector register flags
2013	and valid selector value. Supply those. */
2014	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2015	{
2016	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2017	{
2018	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2019	bool const fValid = !VM_IS_RAW_MODE_ENABLED(pVM)
2020	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2021	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2022	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2023	if (fValid)
2024	{
2025	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2026	{
2027	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2028	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2029	}
2030
2031	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2032	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2033	}
2034	else
2035	{
2036	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2037	{
2038	paSelReg[iSelReg].fFlags = 0;
2039	paSelReg[iSelReg].ValidSel = 0;
2040	}
2041
2042	/* This might not be 104% correct, but I think it's close
2043	enough for all practical purposes... (REM always loaded
2044	LDTR registers.) */
2045	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2046	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2047	}
2048	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2049	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2050	}
2051	}
2052
2053	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2054	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2055	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2056	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2057	pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2058
2059	/*
2060	* A quick sanity check.
2061	*/
2062	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2063	{
2064	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2065	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2066	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2067	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2068	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2069	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2070	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2071	}
2072	}
2073
2074	pVM->cpum.s.fPendingRestore = false;
2075
2076	/*
2077	* Guest CPUIDs.
2078	*/
2079	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
2080	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2081	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
2082	}
2083
2084
2085	/**
2086	* @callback_method_impl{FNSSMINTLOADDONE}
2087	*/
2088	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2089	{
2090	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2091	return VINF_SUCCESS;
2092
2093	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2094	if (pVM->cpum.s.fPendingRestore)
2095	{
2096	LogRel(("CPUM: Missing state!\n"));
2097	return VERR_INTERNAL_ERROR_2;
2098	}
2099
2100	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2101	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2102	{
2103	PVMCPU pVCpu = &pVM->aCpus[idCpu];
2104
2105	/* Notify PGM of the NXE states in case they've changed. */
2106	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2107
2108	/* During init. this is done in CPUMR3InitCompleted(). */
2109	if (fSupportsLongMode)
2110	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
2111	}
2112	return VINF_SUCCESS;
2113	}
2114
2115
2116	/**
2117	* Checks if the CPUM state restore is still pending.
2118	*
2119	* @returns true / false.
2120	* @param pVM The cross context VM structure.
2121	*/
2122	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2123	{
2124	return pVM->cpum.s.fPendingRestore;
2125	}
2126
2127
2128	/**
2129	* Formats the EFLAGS value into mnemonics.
2130	*
2131	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2132	* @param efl The EFLAGS value.
2133	*/
2134	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2135	{
2136	/*
2137	* Format the flags.
2138	*/
2139	static const struct
2140	{
2141	const char pszSet; const char pszClear; uint32_t fFlag;
2142	} s_aFlags[] =
2143	{
2144	{ "vip",NULL, X86_EFL_VIP },
2145	{ "vif",NULL, X86_EFL_VIF },
2146	{ "ac", NULL, X86_EFL_AC },
2147	{ "vm", NULL, X86_EFL_VM },
2148	{ "rf", NULL, X86_EFL_RF },
2149	{ "nt", NULL, X86_EFL_NT },
2150	{ "ov", "nv", X86_EFL_OF },
2151	{ "dn", "up", X86_EFL_DF },
2152	{ "ei", "di", X86_EFL_IF },
2153	{ "tf", NULL, X86_EFL_TF },
2154	{ "nt", "pl", X86_EFL_SF },
2155	{ "nz", "zr", X86_EFL_ZF },
2156	{ "ac", "na", X86_EFL_AF },
2157	{ "po", "pe", X86_EFL_PF },
2158	{ "cy", "nc", X86_EFL_CF },
2159	};
2160	char *psz = pszEFlags;
2161	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2162	{
2163	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2164	if (pszAdd)
2165	{
2166	strcpy(psz, pszAdd);
2167	psz += strlen(pszAdd);
2168	*psz++ = ' ';
2169	}
2170	}
2171	psz[-1] = '\0';
2172	}
2173
2174
2175	/**
2176	* Formats a full register dump.
2177	*
2178	* @param pVM The cross context VM structure.
2179	* @param pCtx The context to format.
2180	* @param pCtxCore The context core to format.
2181	* @param pHlp Output functions.
2182	* @param enmType The dump type.
2183	* @param pszPrefix Register name prefix.
2184	*/
2185	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
2186	const char *pszPrefix)
2187	{
2188	NOREF(pVM);
2189
2190	/*
2191	* Format the EFLAGS.
2192	*/
2193	uint32_t efl = pCtxCore->eflags.u32;
2194	char szEFlags[80];
2195	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2196
2197	/*
2198	* Format the registers.
2199	*/
2200	switch (enmType)
2201	{
2202	case CPUMDUMPTYPE_TERSE:
2203	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2204	pHlp->pfnPrintf(pHlp,
2205	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2206	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2207	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2208	"%sr14=%016RX64 %sr15=%016RX64\n"
2209	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2210	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2211	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2212	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2213	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2214	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2215	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2216	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2217	else
2218	pHlp->pfnPrintf(pHlp,
2219	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2220	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2221	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2222	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2223	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2224	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2225	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2226	break;
2227
2228	case CPUMDUMPTYPE_DEFAULT:
2229	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2230	pHlp->pfnPrintf(pHlp,
2231	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2232	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2233	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2234	"%sr14=%016RX64 %sr15=%016RX64\n"
2235	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2236	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2237	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2238	,
2239	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2240	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2241	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2242	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2243	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2244	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2245	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2246	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2247	else
2248	pHlp->pfnPrintf(pHlp,
2249	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2250	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2251	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2252	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2253	,
2254	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2255	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2256	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2257	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2258	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2259	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2260	break;
2261
2262	case CPUMDUMPTYPE_VERBOSE:
2263	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2264	pHlp->pfnPrintf(pHlp,
2265	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2266	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2267	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2268	"%sr14=%016RX64 %sr15=%016RX64\n"
2269	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2270	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2271	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2272	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2273	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2274	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2275	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2276	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2277	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2278	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2279	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2280	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2281	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2282	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2283	,
2284	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2285	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2286	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2287	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2288	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2289	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2290	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2291	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2292	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2293	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2294	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2295	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2296	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2297	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2298	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2299	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2300	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2301	else
2302	pHlp->pfnPrintf(pHlp,
2303	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2304	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2305	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2306	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2307	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2308	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2309	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2310	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2311	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2312	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2313	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2314	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2315	,
2316	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2317	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2318	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2319	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2320	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2321	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2322	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2323	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2324	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2325	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2326	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2327	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2328
2329	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
2330	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
2331	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
2332	if (pCtx->CTX_SUFF(pXState))
2333	{
2334	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
2335	pHlp->pfnPrintf(pHlp,
2336	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2337	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2338	,
2339	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
2340	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
2341	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
2342	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
2343	);
2344	/*
2345	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
2346	* not (FP)R0-7 as Intel SDM suggests.
2347	*/
2348	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
2349	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
2350	{
2351	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
2352	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
2353	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
2354	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
2355	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
2356	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
2357	iExponent -= 16383; /* subtract bias */
2358	/** @todo This isn't entirenly correct and needs more work! */
2359	pHlp->pfnPrintf(pHlp,
2360	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
2361	pszPrefix, iST, pszPrefix, iFPR,
2362	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
2363	uTag, chSign, iInteger, u64Fraction, iExponent);
2364	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
2365	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2366	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
2367	else
2368	pHlp->pfnPrintf(pHlp, "\n");
2369	}
2370
2371	/* XMM/YMM/ZMM registers. */
2372	if (pCtx->fXStateMask & XSAVE_C_YMM)
2373	{
2374	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2375	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
2376	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2377	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2378	pszPrefix, i, i < 10 ? " " : "",
2379	pYmmHiCtx->aYmmHi[i].au32[3],
2380	pYmmHiCtx->aYmmHi[i].au32[2],
2381	pYmmHiCtx->aYmmHi[i].au32[1],
2382	pYmmHiCtx->aYmmHi[i].au32[0],
2383	pFpuCtx->aXMM[i].au32[3],
2384	pFpuCtx->aXMM[i].au32[2],
2385	pFpuCtx->aXMM[i].au32[1],
2386	pFpuCtx->aXMM[i].au32[0]);
2387	else
2388	{
2389	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2390	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2391	pHlp->pfnPrintf(pHlp,
2392	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2393	pszPrefix, i, i < 10 ? " " : "",
2394	pZmmHi256->aHi256Regs[i].au32[7],
2395	pZmmHi256->aHi256Regs[i].au32[6],
2396	pZmmHi256->aHi256Regs[i].au32[5],
2397	pZmmHi256->aHi256Regs[i].au32[4],
2398	pZmmHi256->aHi256Regs[i].au32[3],
2399	pZmmHi256->aHi256Regs[i].au32[2],
2400	pZmmHi256->aHi256Regs[i].au32[1],
2401	pZmmHi256->aHi256Regs[i].au32[0],
2402	pYmmHiCtx->aYmmHi[i].au32[3],
2403	pYmmHiCtx->aYmmHi[i].au32[2],
2404	pYmmHiCtx->aYmmHi[i].au32[1],
2405	pYmmHiCtx->aYmmHi[i].au32[0],
2406	pFpuCtx->aXMM[i].au32[3],
2407	pFpuCtx->aXMM[i].au32[2],
2408	pFpuCtx->aXMM[i].au32[1],
2409	pFpuCtx->aXMM[i].au32[0]);
2410
2411	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2412	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
2413	pHlp->pfnPrintf(pHlp,
2414	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2415	pszPrefix, i + 16,
2416	pZmm16Hi->aRegs[i].au32[15],
2417	pZmm16Hi->aRegs[i].au32[14],
2418	pZmm16Hi->aRegs[i].au32[13],
2419	pZmm16Hi->aRegs[i].au32[12],
2420	pZmm16Hi->aRegs[i].au32[11],
2421	pZmm16Hi->aRegs[i].au32[10],
2422	pZmm16Hi->aRegs[i].au32[9],
2423	pZmm16Hi->aRegs[i].au32[8],
2424	pZmm16Hi->aRegs[i].au32[7],
2425	pZmm16Hi->aRegs[i].au32[6],
2426	pZmm16Hi->aRegs[i].au32[5],
2427	pZmm16Hi->aRegs[i].au32[4],
2428	pZmm16Hi->aRegs[i].au32[3],
2429	pZmm16Hi->aRegs[i].au32[2],
2430	pZmm16Hi->aRegs[i].au32[1],
2431	pZmm16Hi->aRegs[i].au32[0]);
2432	}
2433	}
2434	else
2435	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2436	pHlp->pfnPrintf(pHlp,
2437	i & 1
2438	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2439	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2440	pszPrefix, i, i < 10 ? " " : "",
2441	pFpuCtx->aXMM[i].au32[3],
2442	pFpuCtx->aXMM[i].au32[2],
2443	pFpuCtx->aXMM[i].au32[1],
2444	pFpuCtx->aXMM[i].au32[0]);
2445
2446	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
2447	{
2448	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
2449	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
2450	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
2451	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
2452	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
2453	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
2454	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
2455	}
2456
2457	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
2458	{
2459	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2460	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
2461	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
2462	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
2463	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
2464	}
2465
2466	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
2467	{
2468	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2469	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
2470	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
2471	}
2472
2473	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
2474	if (pFpuCtx->au32RsrvdRest[i])
2475	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
2476	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
2477	}
2478
2479	pHlp->pfnPrintf(pHlp,
2480	"%sEFER =%016RX64\n"
2481	"%sPAT =%016RX64\n"
2482	"%sSTAR =%016RX64\n"
2483	"%sCSTAR =%016RX64\n"
2484	"%sLSTAR =%016RX64\n"
2485	"%sSFMASK =%016RX64\n"
2486	"%sKERNELGSBASE =%016RX64\n",
2487	pszPrefix, pCtx->msrEFER,
2488	pszPrefix, pCtx->msrPAT,
2489	pszPrefix, pCtx->msrSTAR,
2490	pszPrefix, pCtx->msrCSTAR,
2491	pszPrefix, pCtx->msrLSTAR,
2492	pszPrefix, pCtx->msrSFMASK,
2493	pszPrefix, pCtx->msrKERNELGSBASE);
2494	break;
2495	}
2496	}
2497
2498
2499	/**
2500	* Display all cpu states and any other cpum info.
2501	*
2502	* @param pVM The cross context VM structure.
2503	* @param pHlp The info helper functions.
2504	* @param pszArgs Arguments, ignored.
2505	*/
2506	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2507	{
2508	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2509	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2510	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
2511	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2512	cpumR3InfoHost(pVM, pHlp, pszArgs);
2513	}
2514
2515
2516	/**
2517	* Parses the info argument.
2518	*
2519	* The argument starts with 'verbose', 'terse' or 'default' and then
2520	* continues with the comment string.
2521	*
2522	* @param pszArgs The pointer to the argument string.
2523	* @param penmType Where to store the dump type request.
2524	* @param ppszComment Where to store the pointer to the comment string.
2525	*/
2526	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2527	{
2528	if (!pszArgs)
2529	{
2530	*penmType = CPUMDUMPTYPE_DEFAULT;
2531	*ppszComment = "";
2532	}
2533	else
2534	{
2535	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
2536	{
2537	pszArgs += 7;
2538	*penmType = CPUMDUMPTYPE_VERBOSE;
2539	}
2540	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
2541	{
2542	pszArgs += 5;
2543	*penmType = CPUMDUMPTYPE_TERSE;
2544	}
2545	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
2546	{
2547	pszArgs += 7;
2548	*penmType = CPUMDUMPTYPE_DEFAULT;
2549	}
2550	else
2551	*penmType = CPUMDUMPTYPE_DEFAULT;
2552	*ppszComment = RTStrStripL(pszArgs);
2553	}
2554	}
2555
2556
2557	/**
2558	* Display the guest cpu state.
2559	*
2560	* @param pVM The cross context VM structure.
2561	* @param pHlp The info helper functions.
2562	* @param pszArgs Arguments.
2563	*/
2564	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2565	{
2566	CPUMDUMPTYPE enmType;
2567	const char *pszComment;
2568	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2569
2570	PVMCPU pVCpu = VMMGetCpu(pVM);
2571	if (!pVCpu)
2572	pVCpu = &pVM->aCpus[0];
2573
2574	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2575
2576	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2577	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2578	}
2579
2580
2581	/**
2582	* Displays an SVM VMCB control area.
2583	*
2584	* @param pHlp The info helper functions.
2585	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
2586	* @param pszPrefix Caller specified string prefix.
2587	*/
2588	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
2589	{
2590	AssertReturnVoid(pHlp);
2591	AssertReturnVoid(pVmcbCtrl);
2592
2593	pHlp->pfnPrintf(pHlp, "%su16InterceptRdCRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
2594	pHlp->pfnPrintf(pHlp, "%su16InterceptWrCRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
2595	pHlp->pfnPrintf(pHlp, "%su16InterceptRdDRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
2596	pHlp->pfnPrintf(pHlp, "%su16InterceptWrDRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
2597	pHlp->pfnPrintf(pHlp, "%su32InterceptXcpt = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
2598	pHlp->pfnPrintf(pHlp, "%su64InterceptCtrl = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
2599	pHlp->pfnPrintf(pHlp, "%su16PauseFilterThreshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
2600	pHlp->pfnPrintf(pHlp, "%su16PauseFilterCount = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
2601	pHlp->pfnPrintf(pHlp, "%su64IOPMPhysAddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
2602	pHlp->pfnPrintf(pHlp, "%su64MSRPMPhysAddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
2603	pHlp->pfnPrintf(pHlp, "%su64TSCOffset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
2604	pHlp->pfnPrintf(pHlp, "%sTLBCtrl\n", pszPrefix);
2605	pHlp->pfnPrintf(pHlp, "%s u32ASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
2606	pHlp->pfnPrintf(pHlp, "%s u8TLBFlush = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
2607	pHlp->pfnPrintf(pHlp, "%sIntCtrl\n", pszPrefix);
2608	pHlp->pfnPrintf(pHlp, "%s u8VTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
2609	pHlp->pfnPrintf(pHlp, "%s u1VIrqPending = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
2610	pHlp->pfnPrintf(pHlp, "%s u1VGif = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
2611	pHlp->pfnPrintf(pHlp, "%s u4VIntrPrio = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
2612	pHlp->pfnPrintf(pHlp, "%s u1IgnoreTPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
2613	pHlp->pfnPrintf(pHlp, "%s u1VIntrMasking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
2614	pHlp->pfnPrintf(pHlp, "%s u1VGifEnable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
2615	pHlp->pfnPrintf(pHlp, "%s u1AvicEnable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
2616	pHlp->pfnPrintf(pHlp, "%s u8VIntrVector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
2617	pHlp->pfnPrintf(pHlp, "%sIntShadow\n", pszPrefix);
2618	pHlp->pfnPrintf(pHlp, "%s u1IntShadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
2619	pHlp->pfnPrintf(pHlp, "%s u1GuestIntMask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
2620	pHlp->pfnPrintf(pHlp, "%su64ExitCode = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
2621	pHlp->pfnPrintf(pHlp, "%su64ExitInfo1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
2622	pHlp->pfnPrintf(pHlp, "%su64ExitInfo2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
2623	pHlp->pfnPrintf(pHlp, "%sExitIntInfo\n", pszPrefix);
2624	pHlp->pfnPrintf(pHlp, "%s u8Vector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
2625	pHlp->pfnPrintf(pHlp, "%s u3Type = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
2626	pHlp->pfnPrintf(pHlp, "%s u1ErrorCodeValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
2627	pHlp->pfnPrintf(pHlp, "%s u1Valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
2628	pHlp->pfnPrintf(pHlp, "%s u32ErrorCode = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
2629	pHlp->pfnPrintf(pHlp, "%sNestedPaging and SEV\n", pszPrefix);
2630	pHlp->pfnPrintf(pHlp, "%s u1NestedPaging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
2631	pHlp->pfnPrintf(pHlp, "%s u1Sev = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
2632	pHlp->pfnPrintf(pHlp, "%s u1SevEs = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
2633	pHlp->pfnPrintf(pHlp, "%sAvicBar\n", pszPrefix);
2634	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
2635	pHlp->pfnPrintf(pHlp, "%sEventInject\n", pszPrefix);
2636	pHlp->pfnPrintf(pHlp, "%s EventInject\n", pszPrefix);
2637	pHlp->pfnPrintf(pHlp, "%s u8Vector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
2638	pHlp->pfnPrintf(pHlp, "%s u3Type = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
2639	pHlp->pfnPrintf(pHlp, "%s u1ErrorCodeValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
2640	pHlp->pfnPrintf(pHlp, "%s u1Valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
2641	pHlp->pfnPrintf(pHlp, "%s u32ErrorCode = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
2642	pHlp->pfnPrintf(pHlp, "%su64NestedPagingCR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
2643	pHlp->pfnPrintf(pHlp, "%sLBR virtualization\n", pszPrefix);
2644	pHlp->pfnPrintf(pHlp, "%s u1LbrVirt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
2645	pHlp->pfnPrintf(pHlp, "%s u1VirtVmsaveVmload = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
2646	pHlp->pfnPrintf(pHlp, "%su32VmcbCleanBits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
2647	pHlp->pfnPrintf(pHlp, "%su64NextRIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
2648	pHlp->pfnPrintf(pHlp, "%scbInstrFetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
2649	pHlp->pfnPrintf(pHlp, "%sabInstr = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
2650	pHlp->pfnPrintf(pHlp, "%sAvicBackingPagePtr\n", pszPrefix);
2651	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
2652	pHlp->pfnPrintf(pHlp, "%sAvicLogicalTablePtr\n", pszPrefix);
2653	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
2654	pHlp->pfnPrintf(pHlp, "%sAvicPhysicalTablePtr\n", pszPrefix);
2655	pHlp->pfnPrintf(pHlp, "%s u8LastGuestCoreId = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
2656	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
2657	}
2658
2659
2660	/**
2661	* Helper for dumping the SVM VMCB selector registers.
2662	*
2663	* @param pHlp The info helper functions.
2664	* @param pSel Pointer to the SVM selector register.
2665	* @param pszName Name of the selector.
2666	* @param pszPrefix Caller specified string prefix.
2667	*/
2668	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
2669	{
2670	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
2671	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
2672	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
2673	}
2674
2675
2676	/**
2677	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
2678	*
2679	* @param pHlp The info helper functions.
2680	* @param pXdtr Pointer to the descriptor table register.
2681	* @param pszName Name of the descriptor table register.
2682	* @param pszPrefix Caller specified string prefix.
2683	*/
2684	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
2685	{
2686	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
2687	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
2688	}
2689
2690
2691	/**
2692	* Displays an SVM VMCB state-save area.
2693	*
2694	* @param pHlp The info helper functions.
2695	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
2696	* @param pszPrefix Caller specified string prefix.
2697	*/
2698	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
2699	{
2700	AssertReturnVoid(pHlp);
2701	AssertReturnVoid(pVmcbStateSave);
2702
2703	char szEFlags[80];
2704	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
2705
2706	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
2707	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
2708	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
2709	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
2710	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
2711	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
2712	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
2713	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
2714	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
2715	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
2716	pHlp->pfnPrintf(pHlp, "%su8CPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
2717	pHlp->pfnPrintf(pHlp, "%su64EFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
2718	pHlp->pfnPrintf(pHlp, "%su64CR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
2719	pHlp->pfnPrintf(pHlp, "%su64CR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
2720	pHlp->pfnPrintf(pHlp, "%su64CR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
2721	pHlp->pfnPrintf(pHlp, "%su64DR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
2722	pHlp->pfnPrintf(pHlp, "%su64DR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
2723	pHlp->pfnPrintf(pHlp, "%su64RFlags = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
2724	pHlp->pfnPrintf(pHlp, "%su64RIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
2725	pHlp->pfnPrintf(pHlp, "%su64RSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
2726	pHlp->pfnPrintf(pHlp, "%su64RAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
2727	pHlp->pfnPrintf(pHlp, "%su64STAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
2728	pHlp->pfnPrintf(pHlp, "%su64LSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
2729	pHlp->pfnPrintf(pHlp, "%su64CSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
2730	pHlp->pfnPrintf(pHlp, "%su64SFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
2731	pHlp->pfnPrintf(pHlp, "%su64KernelGSBase = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
2732	pHlp->pfnPrintf(pHlp, "%su64SysEnterCS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
2733	pHlp->pfnPrintf(pHlp, "%su64SysEnterEIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
2734	pHlp->pfnPrintf(pHlp, "%su64SysEnterESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
2735	pHlp->pfnPrintf(pHlp, "%su64CR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
2736	pHlp->pfnPrintf(pHlp, "%su64PAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
2737	pHlp->pfnPrintf(pHlp, "%su64DBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
2738	pHlp->pfnPrintf(pHlp, "%su64BR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
2739	pHlp->pfnPrintf(pHlp, "%su64BR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
2740	pHlp->pfnPrintf(pHlp, "%su64LASTEXCPFROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
2741	pHlp->pfnPrintf(pHlp, "%su64LASTEXCPTO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
2742	}
2743
2744
2745	/**
2746	* Display the guest's hardware-virtualization cpu state.
2747	*
2748	* @param pVM The cross context VM structure.
2749	* @param pHlp The info helper functions.
2750	* @param pszArgs Arguments, ignored.
2751	*/
2752	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2753	{
2754	RT_NOREF(pszArgs);
2755
2756	PVMCPU pVCpu = VMMGetCpu(pVM);
2757	if (!pVCpu)
2758	pVCpu = &pVM->aCpus[0];
2759
2760	/*
2761	* Figure out what to dump.
2762	*
2763	* In the future we may need to dump everything whether or not we're actively in nested-guest mode
2764	* or not, hence the reason why we use a mask to determine what needs dumping. Currently, we only
2765	* dump hwvirt. state when the guest CPU is executing a nested-guest.
2766	*/
2767	/** @todo perhaps make this configurable through pszArgs, depending on how much
2768	* noise we wish to accept when nested hwvirt. isn't used. */
2769	#define CPUMHWVIRTDUMP_NONE (0)
2770	#define CPUMHWVIRTDUMP_SVM RT_BIT(0)
2771	#define CPUMHWVIRTDUMP_VMX RT_BIT(1)
2772	#define CPUMHWVIRTDUMP_COMMON RT_BIT(2)
2773	#define CPUMHWVIRTDUMP_LAST CPUMHWVIRTDUMP_VMX
2774
2775	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2776	static const char *const s_aHwvirtModes[] = { "No/inactive", "SVM", "VMX", "Common" };
2777	uint8_t const idxHwvirtState = CPUMIsGuestInSvmNestedHwVirtMode(pCtx) ? CPUMHWVIRTDUMP_SVM
2778	: CPUMIsGuestInVmxNestedHwVirtMode(pCtx) ? CPUMHWVIRTDUMP_VMX : CPUMHWVIRTDUMP_NONE;
2779	AssertCompile(CPUMHWVIRTDUMP_LAST <= RT_ELEMENTS(s_aHwvirtModes));
2780	Assert(idxHwvirtState < RT_ELEMENTS(s_aHwvirtModes));
2781	const char *pcszHwvirtMode = s_aHwvirtModes[idxHwvirtState];
2782	uint32_t fDumpState = idxHwvirtState \| CPUMHWVIRTDUMP_COMMON;
2783
2784	/*
2785	* Dump it.
2786	*/
2787	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
2788
2789	if (fDumpState & CPUMHWVIRTDUMP_COMMON)
2790	{
2791	pHlp->pfnPrintf(pHlp, "fGif = %RTbool\n", pCtx->hwvirt.fGif);
2792	pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
2793	}
2794	pHlp->pfnPrintf(pHlp, "%s hwvirt state%s\n", pcszHwvirtMode, (fDumpState & (CPUMHWVIRTDUMP_SVM \| CPUMHWVIRTDUMP_VMX)) ?
2795	":" : "");
2796	if (fDumpState & CPUMHWVIRTDUMP_SVM)
2797	{
2798	char szEFlags[80];
2799	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
2800
2801	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
2802	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
2803	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
2804	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.pVmcbR3->ctrl, " " /* pszPrefix */);
2805	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
2806	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.pVmcbR3->guest, " " /* pszPrefix */);
2807	pHlp->pfnPrintf(pHlp, " HostState:\n");
2808	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
2809	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
2810	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
2811	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
2812	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
2813	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
2814	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
2815	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
2816	PCPUMSELREG pSel = &pCtx->hwvirt.svm.HostState.es;
2817	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2818	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
2819	pSel = &pCtx->hwvirt.svm.HostState.cs;
2820	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2821	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
2822	pSel = &pCtx->hwvirt.svm.HostState.ss;
2823	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2824	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
2825	pSel = &pCtx->hwvirt.svm.HostState.ds;
2826	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2827	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
2828	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
2829	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
2830	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
2831	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
2832	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
2833	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
2834	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
2835	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR3 = %p\n", pCtx->hwvirt.svm.pvMsrBitmapR3);
2836	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvMsrBitmapR0);
2837	pHlp->pfnPrintf(pHlp, " pvIoBitmapR3 = %p\n", pCtx->hwvirt.svm.pvIoBitmapR3);
2838	pHlp->pfnPrintf(pHlp, " pvIoBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvIoBitmapR0);
2839	}
2840
2841	/** @todo Intel. */
2842	#if 0
2843	if (fDumpState & CPUMHWVIRTDUMP_VMX)
2844	{
2845	}
2846	#endif
2847
2848	#undef CPUMHWVIRTDUMP_NONE
2849	#undef CPUMHWVIRTDUMP_COMMON
2850	#undef CPUMHWVIRTDUMP_SVM
2851	#undef CPUMHWVIRTDUMP_VMX
2852	#undef CPUMHWVIRTDUMP_LAST
2853	#undef CPUMHWVIRTDUMP_ALL
2854	}
2855
2856	/**
2857	* Display the current guest instruction
2858	*
2859	* @param pVM The cross context VM structure.
2860	* @param pHlp The info helper functions.
2861	* @param pszArgs Arguments, ignored.
2862	*/
2863	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2864	{
2865	NOREF(pszArgs);
2866
2867	PVMCPU pVCpu = VMMGetCpu(pVM);
2868	if (!pVCpu)
2869	pVCpu = &pVM->aCpus[0];
2870
2871	char szInstruction[256];
2872	szInstruction[0] = '\0';
2873	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2874	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
2875	}
2876
2877
2878	/**
2879	* Display the hypervisor cpu state.
2880	*
2881	* @param pVM The cross context VM structure.
2882	* @param pHlp The info helper functions.
2883	* @param pszArgs Arguments, ignored.
2884	*/
2885	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2886	{
2887	PVMCPU pVCpu = VMMGetCpu(pVM);
2888	if (!pVCpu)
2889	pVCpu = &pVM->aCpus[0];
2890
2891	CPUMDUMPTYPE enmType;
2892	const char *pszComment;
2893	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2894	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2895	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
2896	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2897	}
2898
2899
2900	/**
2901	* Display the host cpu state.
2902	*
2903	* @param pVM The cross context VM structure.
2904	* @param pHlp The info helper functions.
2905	* @param pszArgs Arguments, ignored.
2906	*/
2907	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2908	{
2909	CPUMDUMPTYPE enmType;
2910	const char *pszComment;
2911	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2912	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2913
2914	PVMCPU pVCpu = VMMGetCpu(pVM);
2915	if (!pVCpu)
2916	pVCpu = &pVM->aCpus[0];
2917	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
2918
2919	/*
2920	* Format the EFLAGS.
2921	*/
2922	#if HC_ARCH_BITS == 32
2923	uint32_t efl = pCtx->eflags.u32;
2924	#else
2925	uint64_t efl = pCtx->rflags;
2926	#endif
2927	char szEFlags[80];
2928	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2929
2930	/*
2931	* Format the registers.
2932	*/
2933	#if HC_ARCH_BITS == 32
2934	pHlp->pfnPrintf(pHlp,
2935	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2936	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2937	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2938	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2939	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2940	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2941	,
2942	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
2943	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2944	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2945	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
2946	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2947	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
2948	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2949	#else
2950	pHlp->pfnPrintf(pHlp,
2951	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2952	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2953	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2954	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2955	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2956	"r14=%016RX64 r15=%016RX64\n"
2957	"iopl=%d %31s\n"
2958	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2959	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2960	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
2961	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2962	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2963	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2964	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2965	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2966	,
2967	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
2968	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2969	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
2970	/pCtx->r8, pCtx->r9,/ pCtx->r10,
2971	pCtx->r11, pCtx->r12, pCtx->r13,
2972	pCtx->r14, pCtx->r15,
2973	X86_EFL_GET_IOPL(efl), szEFlags,
2974	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2975	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
2976	pCtx->cr4, pCtx->ldtr, pCtx->tr,
2977	pCtx->dr0, pCtx->dr1, pCtx->dr2,
2978	pCtx->dr3, pCtx->dr6, pCtx->dr7,
2979	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2980	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2981	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2982	#endif
2983	}
2984
2985	/**
2986	* Structure used when disassembling and instructions in DBGF.
2987	* This is used so the reader function can get the stuff it needs.
2988	*/
2989	typedef struct CPUMDISASSTATE
2990	{
2991	/** Pointer to the CPU structure. */
2992	PDISCPUSTATE pCpu;
2993	/** Pointer to the VM. */
2994	PVM pVM;
2995	/** Pointer to the VMCPU. */
2996	PVMCPU pVCpu;
2997	/** Pointer to the first byte in the segment. */
2998	RTGCUINTPTR GCPtrSegBase;
2999	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3000	RTGCUINTPTR GCPtrSegEnd;
3001	/** The size of the segment minus 1. */
3002	RTGCUINTPTR cbSegLimit;
3003	/** Pointer to the current page - R3 Ptr. */
3004	void const *pvPageR3;
3005	/** Pointer to the current page - GC Ptr. */
3006	RTGCPTR pvPageGC;
3007	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3008	PGMPAGEMAPLOCK PageMapLock;
3009	/** Whether the PageMapLock is valid or not. */
3010	bool fLocked;
3011	/** 64 bits mode or not. */
3012	bool f64Bits;
3013	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3014
3015
3016	/**
3017	* @callback_method_impl{FNDISREADBYTES}
3018	*/
3019	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
3020	{
3021	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
3022	for (;;)
3023	{
3024	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
3025
3026	/*
3027	* Need to update the page translation?
3028	*/
3029	if ( !pState->pvPageR3
3030	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3031	{
3032	int rc = VINF_SUCCESS;
3033
3034	/* translate the address */
3035	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3036	if ( VM_IS_RAW_MODE_ENABLED(pState->pVM)
3037	&& MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
3038	{
3039	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3040	if (!pState->pvPageR3)
3041	rc = VERR_INVALID_POINTER;
3042	}
3043	else
3044	{
3045	/* Release mapping lock previously acquired. */
3046	if (pState->fLocked)
3047	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3048	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3049	pState->fLocked = RT_SUCCESS_NP(rc);
3050	}
3051	if (RT_FAILURE(rc))
3052	{
3053	pState->pvPageR3 = NULL;
3054	return rc;
3055	}
3056	}
3057
3058	/*
3059	* Check the segment limit.
3060	*/
3061	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
3062	return VERR_OUT_OF_SELECTOR_BOUNDS;
3063
3064	/*
3065	* Calc how much we can read.
3066	*/
3067	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3068	if (!pState->f64Bits)
3069	{
3070	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3071	if (cb > cbSeg && cbSeg)
3072	cb = cbSeg;
3073	}
3074	if (cb > cbMaxRead)
3075	cb = cbMaxRead;
3076
3077	/*
3078	* Read and advance or exit.
3079	*/
3080	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3081	offInstr += (uint8_t)cb;
3082	if (cb >= cbMinRead)
3083	{
3084	pDis->cbCachedInstr = offInstr;
3085	return VINF_SUCCESS;
3086	}
3087	cbMinRead -= (uint8_t)cb;
3088	cbMaxRead -= (uint8_t)cb;
3089	}
3090	}
3091
3092
3093	/**
3094	* Disassemble an instruction and return the information in the provided structure.
3095	*
3096	* @returns VBox status code.
3097	* @param pVM The cross context VM structure.
3098	* @param pVCpu The cross context virtual CPU structure.
3099	* @param pCtx Pointer to the guest CPU context.
3100	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3101	* @param pCpu Disassembly state.
3102	* @param pszPrefix String prefix for logging (debug only).
3103	*
3104	*/
3105	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
3106	const char *pszPrefix)
3107	{
3108	CPUMDISASSTATE State;
3109	int rc;
3110
3111	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3112	State.pCpu = pCpu;
3113	State.pvPageGC = 0;
3114	State.pvPageR3 = NULL;
3115	State.pVM = pVM;
3116	State.pVCpu = pVCpu;
3117	State.fLocked = false;
3118	State.f64Bits = false;
3119
3120	/*
3121	* Get selector information.
3122	*/
3123	DISCPUMODE enmDisCpuMode;
3124	if ( (pCtx->cr0 & X86_CR0_PE)
3125	&& pCtx->eflags.Bits.u1VM == 0)
3126	{
3127	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
3128	{
3129	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3130	CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
3131	# endif
3132	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
3133	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
3134	}
3135	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
3136	State.GCPtrSegBase = pCtx->cs.u64Base;
3137	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
3138	State.cbSegLimit = pCtx->cs.u32Limit;
3139	enmDisCpuMode = (State.f64Bits)
3140	? DISCPUMODE_64BIT
3141	: pCtx->cs.Attr.n.u1DefBig
3142	? DISCPUMODE_32BIT
3143	: DISCPUMODE_16BIT;
3144	}
3145	else
3146	{
3147	/* real or V86 mode */
3148	enmDisCpuMode = DISCPUMODE_16BIT;
3149	State.GCPtrSegBase = pCtx->cs.Sel * 16;
3150	State.GCPtrSegEnd = 0xFFFFFFFF;
3151	State.cbSegLimit = 0xFFFFFFFF;
3152	}
3153
3154	/*
3155	* Disassemble the instruction.
3156	*/
3157	uint32_t cbInstr;
3158	#ifndef LOG_ENABLED
3159	RT_NOREF_PV(pszPrefix);
3160	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
3161	if (RT_SUCCESS(rc))
3162	{
3163	#else
3164	char szOutput[160];
3165	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
3166	pCpu, &cbInstr, szOutput, sizeof(szOutput));
3167	if (RT_SUCCESS(rc))
3168	{
3169	/* log it */
3170	if (pszPrefix)
3171	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3172	else
3173	Log(("%s", szOutput));
3174	#endif
3175	rc = VINF_SUCCESS;
3176	}
3177	else
3178	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
3179
3180	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
3181	if (State.fLocked)
3182	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3183
3184	return rc;
3185	}
3186
3187
3188
3189	/**
3190	* API for controlling a few of the CPU features found in CR4.
3191	*
3192	* Currently only X86_CR4_TSD is accepted as input.
3193	*
3194	* @returns VBox status code.
3195	*
3196	* @param pVM The cross context VM structure.
3197	* @param fOr The CR4 OR mask.
3198	* @param fAnd The CR4 AND mask.
3199	*/
3200	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3201	{
3202	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3203	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3204
3205	pVM->cpum.s.CR4.OrMask &= fAnd;
3206	pVM->cpum.s.CR4.OrMask \|= fOr;
3207
3208	return VINF_SUCCESS;
3209	}
3210
3211
3212	/**
3213	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
3214	*
3215	* Only REM should ever call this function!
3216	*
3217	* @returns The changed flags.
3218	* @param pVCpu The cross context virtual CPU structure.
3219	* @param puCpl Where to return the current privilege level (CPL).
3220	*/
3221	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
3222	{
3223	Assert(!pVCpu->cpum.s.fRawEntered);
3224	Assert(!pVCpu->cpum.s.fRemEntered);
3225
3226	/*
3227	* Get the CPL first.
3228	*/
3229	*puCpl = CPUMGetGuestCPL(pVCpu);
3230
3231	/*
3232	* Get and reset the flags.
3233	*/
3234	uint32_t fFlags = pVCpu->cpum.s.fChanged;
3235	pVCpu->cpum.s.fChanged = 0;
3236
3237	/** @todo change the switcher to use the fChanged flags. */
3238	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
3239	{
3240	fFlags \|= CPUM_CHANGED_FPU_REM;
3241	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
3242	}
3243
3244	pVCpu->cpum.s.fRemEntered = true;
3245	return fFlags;
3246	}
3247
3248
3249	/**
3250	* Leaves REM.
3251	*
3252	* @param pVCpu The cross context virtual CPU structure.
3253	* @param fNoOutOfSyncSels This is @c false if there are out of sync
3254	* registers.
3255	*/
3256	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
3257	{
3258	Assert(!pVCpu->cpum.s.fRawEntered);
3259	Assert(pVCpu->cpum.s.fRemEntered);
3260
3261	RT_NOREF_PV(fNoOutOfSyncSels);
3262
3263	pVCpu->cpum.s.fRemEntered = false;
3264	}
3265
3266
3267	/**
3268	* Called when the ring-3 init phase completes.
3269	*
3270	* @returns VBox status code.
3271	* @param pVM The cross context VM structure.
3272	* @param enmWhat Which init phase.
3273	*/
3274	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
3275	{
3276	switch (enmWhat)
3277	{
3278	case VMINITCOMPLETED_RING3:
3279	{
3280	/*
3281	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
3282	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
3283	*/
3284	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
3285	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3286	{
3287	PVMCPU pVCpu = &pVM->aCpus[i];
3288	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
3289	if (fSupportsLongMode)
3290	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
3291	}
3292
3293	cpumR3MsrRegStats(pVM);
3294	break;
3295	}
3296
3297	case VMINITCOMPLETED_HM:
3298	{
3299	/*
3300	* Currently, nested VMX/SVM both derives their guest VMX/SVM CPUID bit from the host
3301	* CPUID bit. This could be later changed if we need to support nested-VMX on CPUs
3302	* that are not capable of VMX.
3303	*/
3304	if (pVM->cpum.s.GuestFeatures.fVmx)
3305	{
3306	Assert( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
3307	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA);
3308	cpumR3InitVmxCpuFeatures(pVM);
3309	DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
3310	}
3311
3312	if (pVM->cpum.s.GuestFeatures.fVmx)
3313	LogRel(("CPUM: Enabled guest VMX support\n"));
3314	else if (pVM->cpum.s.GuestFeatures.fSvm)
3315	LogRel(("CPUM: Enabled guest SVM support\n"));
3316	break;
3317	}
3318
3319	default:
3320	break;
3321	}
3322	return VINF_SUCCESS;
3323	}
3324
3325
3326	/**
3327	* Called when the ring-0 init phases completed.
3328	*
3329	* @param pVM The cross context VM structure.
3330	*/
3331	VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
3332	{
3333	/*
3334	* Log the cpuid.
3335	*/
3336	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
3337	RTCPUSET OnlineSet;
3338	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
3339	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
3340	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
3341	RTCPUID cCores = RTMpGetCoreCount();
3342	if (cCores)
3343	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
3344	LogRel(("*********************** CPUID dump **********************\n"));
3345	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
3346	LogRel(("\n"));
3347	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
3348	RTLogRelSetBuffering(fOldBuffered);
3349	LogRel(("****************** End of CPUID dump ********************\n"));
3350	}
3351

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 73494

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