CPUM.cpp@ 69111

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1	/* $Id: CPUM.cpp 69111 2017-10-17 14:26:02Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*
33	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34	*
35	* TODO: proper write up, currently just some notes.
36	*
37	* The ring-0 FPU handling per OS:
38	*
39	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
40	* convention (Visual C++ doesn't seem to have a way to disable
41	* generating such code either), so CR0.TS/EM are always zero from what I
42	* can tell. We are also forced to always load/save the guest XMM0-XMM15
43	* registers when entering/leaving guest context. Interrupt handlers
44	* using FPU/SSE will offically have call save and restore functions
45	* exported by the kernel, if the really really have to use the state.
46	*
47	* - 32-bit windows does lazy FPU handling, I think, probably including
48	* lazying saving. The Windows Internals book states that it's a bad
49	* idea to use the FPU in kernel space. However, it looks like it will
50	* restore the FPU state of the current thread in case of a kernel \#NM.
51	* Interrupt handlers should be same as for 64-bit.
52	*
53	* - Darwin allows taking \#NM in kernel space, restoring current thread's
54	* state if I read the code correctly. It saves the FPU state of the
55	* outgoing thread, and uses CR0.TS to lazily load the state of the
56	* incoming one. No idea yet how the FPU is treated by interrupt
57	* handlers, i.e. whether they are allowed to disable the state or
58	* something.
59	*
60	* - Linux also allows \#NM in kernel space (don't know since when), and
61	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62	* loads the incoming unless configured to agressivly load it. Interrupt
63	* handlers can ask whether they're allowed to use the FPU, and may
64	* freely trash the state if Linux thinks it has saved the thread's state
65	* already. This is a problem.
66	*
67	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68	* context. When switching threads, the kernel will save the state of
69	* the outgoing thread and lazy load the incoming one using CR0.TS.
70	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
71	* to do stuff, HAT are among the users. The routines there will
72	* manually clear CR0.TS and save the XMM registers they use only if
73	* CR0.TS was zero upon entry. They will skip it when not, because as
74	* mentioned above, the FPU state is saved when switching away from a
75	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76	* preserve. This is a problem if we restore CR0.TS to 1 after loading
77	* the guest state.
78	*
79	* - FreeBSD - no idea yet.
80	*
81	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83	* FPU states.
84	*
85	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86	* saving and restoring the host and guest states. The motivation for this
87	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88	*
89	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90	* state and only restore it once we've restore the host FPU state. This has the
91	* accidental side effect of triggering Solaris to preserve XMM registers in
92	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94	*
95	*
96	* @section sec_cpum_logging Logging Level Assignments.
97	*
98	* Following log level assignments:
99	* - Log6 is used for FPU state management.
100	* - Log7 is used for FPU state actualization.
101	*
102	*/
103
104
105	/*********************************************************************************************************************************
106	* Header Files *
107	*********************************************************************************************************************************/
108	#define LOG_GROUP LOG_GROUP_CPUM
109	#include <VBox/vmm/cpum.h>
110	#include <VBox/vmm/cpumdis.h>
111	#include <VBox/vmm/cpumctx-v1_6.h>
112	#include <VBox/vmm/pgm.h>
113	#include <VBox/vmm/apic.h>
114	#include <VBox/vmm/mm.h>
115	#include <VBox/vmm/em.h>
116	#include <VBox/vmm/iem.h>
117	#include <VBox/vmm/selm.h>
118	#include <VBox/vmm/dbgf.h>
119	#include <VBox/vmm/patm.h>
120	#include <VBox/vmm/hm.h>
121	#include <VBox/vmm/ssm.h>
122	#include "CPUMInternal.h"
123	#include <VBox/vmm/vm.h>
124
125	#include <VBox/param.h>
126	#include <VBox/dis.h>
127	#include <VBox/err.h>
128	#include <VBox/log.h>
129	#include <iprt/asm-amd64-x86.h>
130	#include <iprt/assert.h>
131	#include <iprt/cpuset.h>
132	#include <iprt/mem.h>
133	#include <iprt/mp.h>
134	#include <iprt/string.h>
135
136
137	/*********************************************************************************************************************************
138	* Defined Constants And Macros *
139	*********************************************************************************************************************************/
140	/**
141	* This was used in the saved state up to the early life of version 14.
142	*
143	* It indicates that we may have some out-of-sync hidden segement registers.
144	* It is only relevant for raw-mode.
145	*/
146	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
147
148
149	/*********************************************************************************************************************************
150	* Structures and Typedefs *
151	*********************************************************************************************************************************/
152
153	/**
154	* What kind of cpu info dump to perform.
155	*/
156	typedef enum CPUMDUMPTYPE
157	{
158	CPUMDUMPTYPE_TERSE,
159	CPUMDUMPTYPE_DEFAULT,
160	CPUMDUMPTYPE_VERBOSE
161	} CPUMDUMPTYPE;
162	/** Pointer to a cpu info dump type. */
163	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
164
165
166	/*********************************************************************************************************************************
167	* Internal Functions *
168	*********************************************************************************************************************************/
169	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
170	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
171	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
172	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
173	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
174	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
179	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
180
181
182	/*********************************************************************************************************************************
183	* Global Variables *
184	*********************************************************************************************************************************/
185	/** Saved state field descriptors for CPUMCTX. */
186	static const SSMFIELD g_aCpumCtxFields[] =
187	{
188	SSMFIELD_ENTRY( CPUMCTX, rdi),
189	SSMFIELD_ENTRY( CPUMCTX, rsi),
190	SSMFIELD_ENTRY( CPUMCTX, rbp),
191	SSMFIELD_ENTRY( CPUMCTX, rax),
192	SSMFIELD_ENTRY( CPUMCTX, rbx),
193	SSMFIELD_ENTRY( CPUMCTX, rdx),
194	SSMFIELD_ENTRY( CPUMCTX, rcx),
195	SSMFIELD_ENTRY( CPUMCTX, rsp),
196	SSMFIELD_ENTRY( CPUMCTX, rflags),
197	SSMFIELD_ENTRY( CPUMCTX, rip),
198	SSMFIELD_ENTRY( CPUMCTX, r8),
199	SSMFIELD_ENTRY( CPUMCTX, r9),
200	SSMFIELD_ENTRY( CPUMCTX, r10),
201	SSMFIELD_ENTRY( CPUMCTX, r11),
202	SSMFIELD_ENTRY( CPUMCTX, r12),
203	SSMFIELD_ENTRY( CPUMCTX, r13),
204	SSMFIELD_ENTRY( CPUMCTX, r14),
205	SSMFIELD_ENTRY( CPUMCTX, r15),
206	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
207	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
208	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
209	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
210	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
211	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
212	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
213	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
214	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
215	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
216	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
217	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
218	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
219	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
220	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
221	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
222	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
223	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
224	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
225	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
226	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
227	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
228	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
229	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
230	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, cr0),
243	SSMFIELD_ENTRY( CPUMCTX, cr2),
244	SSMFIELD_ENTRY( CPUMCTX, cr3),
245	SSMFIELD_ENTRY( CPUMCTX, cr4),
246	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
247	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
248	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
249	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
250	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
251	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
252	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
253	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
254	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
255	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
256	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
257	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
258	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
259	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
260	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
261	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
262	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
263	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
264	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
265	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
266	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
267	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
268	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
269	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
270	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
271	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
272	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
273	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
274	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
275	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
276	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
277	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
278	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
279	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
280	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
281	SSMFIELD_ENTRY_TERM()
282	};
283
284	/** Saved state field descriptors for CPUMCTX. */
285	static const SSMFIELD g_aCpumX87Fields[] =
286	{
287	SSMFIELD_ENTRY( X86FXSTATE, FCW),
288	SSMFIELD_ENTRY( X86FXSTATE, FSW),
289	SSMFIELD_ENTRY( X86FXSTATE, FTW),
290	SSMFIELD_ENTRY( X86FXSTATE, FOP),
291	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
292	SSMFIELD_ENTRY( X86FXSTATE, CS),
293	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
294	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
295	SSMFIELD_ENTRY( X86FXSTATE, DS),
296	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
297	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
298	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
299	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
300	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
301	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
302	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
303	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
304	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
305	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
306	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
307	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
308	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
309	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
310	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
311	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
312	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
313	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
314	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
315	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
316	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
317	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
318	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
319	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
320	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
321	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
322	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
323	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
324	SSMFIELD_ENTRY_TERM()
325	};
326
327	/** Saved state field descriptors for X86XSAVEHDR. */
328	static const SSMFIELD g_aCpumXSaveHdrFields[] =
329	{
330	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
331	SSMFIELD_ENTRY_TERM()
332	};
333
334	/** Saved state field descriptors for X86XSAVEYMMHI. */
335	static const SSMFIELD g_aCpumYmmHiFields[] =
336	{
337	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
338	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
339	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
340	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
341	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
342	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
343	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
344	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
345	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
346	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
347	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
348	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
349	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
350	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
351	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
352	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
353	SSMFIELD_ENTRY_TERM()
354	};
355
356	/** Saved state field descriptors for X86XSAVEBNDREGS. */
357	static const SSMFIELD g_aCpumBndRegsFields[] =
358	{
359	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
360	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
361	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
362	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
363	SSMFIELD_ENTRY_TERM()
364	};
365
366	/** Saved state field descriptors for X86XSAVEBNDCFG. */
367	static const SSMFIELD g_aCpumBndCfgFields[] =
368	{
369	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
370	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
371	SSMFIELD_ENTRY_TERM()
372	};
373
374	#if 0 /** @todo */
375	/** Saved state field descriptors for X86XSAVEOPMASK. */
376	static const SSMFIELD g_aCpumOpmaskFields[] =
377	{
378	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
379	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
380	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
381	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
382	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
383	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
384	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
385	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
386	SSMFIELD_ENTRY_TERM()
387	};
388	#endif
389
390	/** Saved state field descriptors for X86XSAVEZMMHI256. */
391	static const SSMFIELD g_aCpumZmmHi256Fields[] =
392	{
393	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
394	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
395	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
396	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
397	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
398	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
399	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
400	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
401	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
402	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
403	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
404	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
405	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
406	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
407	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
408	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
409	SSMFIELD_ENTRY_TERM()
410	};
411
412	/** Saved state field descriptors for X86XSAVEZMM16HI. */
413	static const SSMFIELD g_aCpumZmm16HiFields[] =
414	{
415	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
416	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
417	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
418	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
419	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
420	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
421	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
422	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
423	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
424	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
425	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
426	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
427	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
428	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
429	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
430	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
431	SSMFIELD_ENTRY_TERM()
432	};
433
434
435
436	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
437	* registeres changed. */
438	static const SSMFIELD g_aCpumX87FieldsMem[] =
439	{
440	SSMFIELD_ENTRY( X86FXSTATE, FCW),
441	SSMFIELD_ENTRY( X86FXSTATE, FSW),
442	SSMFIELD_ENTRY( X86FXSTATE, FTW),
443	SSMFIELD_ENTRY( X86FXSTATE, FOP),
444	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
445	SSMFIELD_ENTRY( X86FXSTATE, CS),
446	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
447	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
448	SSMFIELD_ENTRY( X86FXSTATE, DS),
449	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
450	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
451	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
452	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
453	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
454	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
455	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
456	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
457	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
458	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
459	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
460	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
461	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
462	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
463	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
464	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
465	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
466	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
467	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
468	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
469	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
470	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
471	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
472	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
473	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
474	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
475	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
476	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
477	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
478	};
479
480	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
481	* registeres changed. */
482	static const SSMFIELD g_aCpumCtxFieldsMem[] =
483	{
484	SSMFIELD_ENTRY( CPUMCTX, rdi),
485	SSMFIELD_ENTRY( CPUMCTX, rsi),
486	SSMFIELD_ENTRY( CPUMCTX, rbp),
487	SSMFIELD_ENTRY( CPUMCTX, rax),
488	SSMFIELD_ENTRY( CPUMCTX, rbx),
489	SSMFIELD_ENTRY( CPUMCTX, rdx),
490	SSMFIELD_ENTRY( CPUMCTX, rcx),
491	SSMFIELD_ENTRY( CPUMCTX, rsp),
492	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
493	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
494	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
495	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
496	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
497	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
498	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
499	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
500	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
501	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
502	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
503	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
504	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
505	SSMFIELD_ENTRY( CPUMCTX, rflags),
506	SSMFIELD_ENTRY( CPUMCTX, rip),
507	SSMFIELD_ENTRY( CPUMCTX, r8),
508	SSMFIELD_ENTRY( CPUMCTX, r9),
509	SSMFIELD_ENTRY( CPUMCTX, r10),
510	SSMFIELD_ENTRY( CPUMCTX, r11),
511	SSMFIELD_ENTRY( CPUMCTX, r12),
512	SSMFIELD_ENTRY( CPUMCTX, r13),
513	SSMFIELD_ENTRY( CPUMCTX, r14),
514	SSMFIELD_ENTRY( CPUMCTX, r15),
515	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
516	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
517	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
518	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
519	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
520	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
521	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
522	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
523	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
524	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
525	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
526	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
527	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
528	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
529	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
530	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
531	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
532	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
533	SSMFIELD_ENTRY( CPUMCTX, cr0),
534	SSMFIELD_ENTRY( CPUMCTX, cr2),
535	SSMFIELD_ENTRY( CPUMCTX, cr3),
536	SSMFIELD_ENTRY( CPUMCTX, cr4),
537	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
538	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
539	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
540	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
541	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
542	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
543	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
544	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
545	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
546	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
547	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
548	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
549	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
550	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
551	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
552	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
553	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
554	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
555	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
556	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
557	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
558	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
559	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
560	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
561	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
562	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
563	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
564	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
565	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
566	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
567	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
568	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
569	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
570	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
571	SSMFIELD_ENTRY_TERM()
572	};
573
574	/** Saved state field descriptors for CPUMCTX_VER1_6. */
575	static const SSMFIELD g_aCpumX87FieldsV16[] =
576	{
577	SSMFIELD_ENTRY( X86FXSTATE, FCW),
578	SSMFIELD_ENTRY( X86FXSTATE, FSW),
579	SSMFIELD_ENTRY( X86FXSTATE, FTW),
580	SSMFIELD_ENTRY( X86FXSTATE, FOP),
581	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
582	SSMFIELD_ENTRY( X86FXSTATE, CS),
583	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
584	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
585	SSMFIELD_ENTRY( X86FXSTATE, DS),
586	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
587	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
588	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
589	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
590	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
591	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
592	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
593	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
594	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
595	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
596	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
597	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
598	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
599	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
600	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
601	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
602	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
603	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
604	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
605	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
606	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
607	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
608	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
609	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
610	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
611	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
612	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
613	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
614	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
615	SSMFIELD_ENTRY_TERM()
616	};
617
618	/** Saved state field descriptors for CPUMCTX_VER1_6. */
619	static const SSMFIELD g_aCpumCtxFieldsV16[] =
620	{
621	SSMFIELD_ENTRY( CPUMCTX, rdi),
622	SSMFIELD_ENTRY( CPUMCTX, rsi),
623	SSMFIELD_ENTRY( CPUMCTX, rbp),
624	SSMFIELD_ENTRY( CPUMCTX, rax),
625	SSMFIELD_ENTRY( CPUMCTX, rbx),
626	SSMFIELD_ENTRY( CPUMCTX, rdx),
627	SSMFIELD_ENTRY( CPUMCTX, rcx),
628	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
629	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
630	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
631	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
632	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
633	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
634	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
635	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
636	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
637	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
638	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
639	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
640	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
641	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
642	SSMFIELD_ENTRY( CPUMCTX, rflags),
643	SSMFIELD_ENTRY( CPUMCTX, rip),
644	SSMFIELD_ENTRY( CPUMCTX, r8),
645	SSMFIELD_ENTRY( CPUMCTX, r9),
646	SSMFIELD_ENTRY( CPUMCTX, r10),
647	SSMFIELD_ENTRY( CPUMCTX, r11),
648	SSMFIELD_ENTRY( CPUMCTX, r12),
649	SSMFIELD_ENTRY( CPUMCTX, r13),
650	SSMFIELD_ENTRY( CPUMCTX, r14),
651	SSMFIELD_ENTRY( CPUMCTX, r15),
652	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
653	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
654	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
655	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
656	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
657	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
658	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
659	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
660	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
661	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
662	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
663	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
664	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
665	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
666	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
667	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
668	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
669	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
670	SSMFIELD_ENTRY( CPUMCTX, cr0),
671	SSMFIELD_ENTRY( CPUMCTX, cr2),
672	SSMFIELD_ENTRY( CPUMCTX, cr3),
673	SSMFIELD_ENTRY( CPUMCTX, cr4),
674	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
675	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
676	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
677	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
678	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
679	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
680	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
681	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
682	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
683	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
684	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
685	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
686	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
687	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
688	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
689	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
690	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
691	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
692	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
693	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
694	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
695	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
696	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
697	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
698	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
699	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
700	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
701	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
702	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
703	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
704	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
705	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
706	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
707	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
708	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
709	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
710	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
711	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
712	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
713	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
714	SSMFIELD_ENTRY_TERM()
715	};
716
717
718	/**
719	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
720	*
721	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
722	* (last instruction pointer, last data pointer, last opcode) except when the ES
723	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
724	* clear these registers there is potential, local FPU leakage from a process
725	* using the FPU to another.
726	*
727	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
728	*
729	* @param pVM The cross context VM structure.
730	*/
731	static void cpumR3CheckLeakyFpu(PVM pVM)
732	{
733	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
734	uint32_t const u32Family = u32CpuVersion >> 8;
735	if ( u32Family >= 6 /* K7 and higher */
736	&& ASMIsAmdCpu())
737	{
738	uint32_t cExt = ASMCpuId_EAX(0x80000000);
739	if (ASMIsValidExtRange(cExt))
740	{
741	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
742	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
743	{
744	for (VMCPUID i = 0; i < pVM->cCpus; i++)
745	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
746	Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
747	}
748	}
749	}
750	}
751
752
753	/**
754	* Frees memory allocated by cpumR3AllocHwVirtState().
755	*
756	* @param pVM The cross context VM structure.
757	*/
758	static void cpumR3FreeHwVirtState(PVM pVM)
759	{
760	Assert(pVM->cpum.ro.GuestFeatures.fSvm);
761	for (VMCPUID i = 0; i < pVM->cCpus; i++)
762	{
763	PVMCPU pVCpu = &pVM->aCpus[i];
764	if (pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3)
765	{
766	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES);
767	pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3 = NULL;
768	}
769	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = NIL_RTHCPHYS;
770
771	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3)
772	{
773	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES);
774	pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3 = NULL;
775	}
776
777	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3)
778	{
779	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES);
780	pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3 = NULL;
781	}
782	}
783	}
784
785
786	/**
787	* Allocates memory required by the hardware virtualization state.
788	*
789	* @returns VBox status code.
790	* @param pVM The cross context VM structure.
791	*/
792	static int cpumR3AllocHwVirtState(PVM pVM)
793	{
794	Assert(pVM->cpum.ro.GuestFeatures.fSvm);
795
796	int rc = VINF_SUCCESS;
797	LogRel(("CPUM: Allocating a total of %u pages for the nested-guest SVM MSR and IO permission bitmaps\n",
798	pVM->cCpus * (SVM_MSRPM_PAGES + SVM_IOPM_PAGES)));
799	for (VMCPUID i = 0; i < pVM->cCpus; i++)
800	{
801	PVMCPU pVCpu = &pVM->aCpus[i];
802
803	/*
804	* Allocate the nested-guest VMCB.
805	*/
806	SUPPAGE SupNstGstVmcbPage;
807	RT_ZERO(SupNstGstVmcbPage);
808	SupNstGstVmcbPage.Phys = NIL_RTHCPHYS;
809	Assert(SVM_VMCB_PAGES == 1);
810	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
811	rc = SUPR3PageAllocEx(SVM_VMCB_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3,
812	&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR0, &SupNstGstVmcbPage);
813	if (RT_FAILURE(rc))
814	{
815	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
816	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCB\n", pVCpu->idCpu, SVM_VMCB_PAGES));
817	break;
818	}
819	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = SupNstGstVmcbPage.Phys;
820
821	/*
822	* Allocate the MSRPM (MSR Permission bitmap).
823	*/
824	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
825	rc = SUPR3PageAllocEx(SVM_MSRPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3,
826	&pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR0, NULL /* paPages */);
827	if (RT_FAILURE(rc))
828	{
829	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
830	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR permission bitmap\n", pVCpu->idCpu,
831	SVM_MSRPM_PAGES));
832	break;
833	}
834
835	/*
836	* Allocate the IOPM (IO Permission bitmap).
837	*/
838	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
839	rc = SUPR3PageAllocEx(SVM_IOPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3,
840	&pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR0, NULL /* paPages */);
841	if (RT_FAILURE(rc))
842	{
843	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
844	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's IO permission bitmap\n", pVCpu->idCpu,
845	SVM_IOPM_PAGES));
846	break;
847	}
848	}
849
850	/* On any failure, cleanup. */
851	if (RT_FAILURE(rc))
852	cpumR3FreeHwVirtState(pVM);
853
854	return rc;
855	}
856
857
858	/**
859	* Initializes the CPUM.
860	*
861	* @returns VBox status code.
862	* @param pVM The cross context VM structure.
863	*/
864	VMMR3DECL(int) CPUMR3Init(PVM pVM)
865	{
866	LogFlow(("CPUMR3Init\n"));
867
868	/*
869	* Assert alignment, sizes and tables.
870	*/
871	AssertCompileMemberAlignment(VM, cpum.s, 32);
872	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
873	AssertCompileSizeAlignment(CPUMCTX, 64);
874	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
875	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
876	AssertCompileMemberAlignment(VM, cpum, 64);
877	AssertCompileMemberAlignment(VM, aCpus, 64);
878	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
879	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
880	#ifdef VBOX_STRICT
881	int rc2 = cpumR3MsrStrictInitChecks();
882	AssertRCReturn(rc2, rc2);
883	#endif
884
885	/*
886	* Initialize offsets.
887	*/
888
889	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
890	pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
891	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
892
893
894	/* Calculate the offset from CPUMCPU to CPUM. */
895	for (VMCPUID i = 0; i < pVM->cCpus; i++)
896	{
897	PVMCPU pVCpu = &pVM->aCpus[i];
898
899	pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
900	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
901	}
902
903	/*
904	* Gather info about the host CPU.
905	*/
906	if (!ASMHasCpuId())
907	{
908	Log(("The CPU doesn't support CPUID!\n"));
909	return VERR_UNSUPPORTED_CPU;
910	}
911
912	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
913
914	PCPUMCPUIDLEAF paLeaves;
915	uint32_t cLeaves;
916	int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
917	AssertLogRelRCReturn(rc, rc);
918
919	rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
920	RTMemFree(paLeaves);
921	AssertLogRelRCReturn(rc, rc);
922	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
923
924	/*
925	* Check that the CPU supports the minimum features we require.
926	*/
927	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
928	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
929	if (!pVM->cpum.s.HostFeatures.fMmx)
930	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
931	if (!pVM->cpum.s.HostFeatures.fTsc)
932	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
933
934	/*
935	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
936	*/
937	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
938	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
939
940	/*
941	* Figure out which XSAVE/XRSTOR features are available on the host.
942	*/
943	uint64_t fXcr0Host = 0;
944	uint64_t fXStateHostMask = 0;
945	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
946	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
947	{
948	fXStateHostMask = fXcr0Host = ASMGetXcr0();
949	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
950	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
951	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
952	}
953	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
954	if (!HMIsEnabled(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
955	fXStateHostMask = 0;
956	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
957	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
958
959	/*
960	* Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
961	*/
962	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
963	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
964	AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
965
966	uint8_t *pbXStates;
967	rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
968	MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
969	AssertLogRelRCReturn(rc, rc);
970
971	for (VMCPUID i = 0; i < pVM->cCpus; i++)
972	{
973	PVMCPU pVCpu = &pVM->aCpus[i];
974
975	pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
976	pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
977	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
978	pbXStates += cbMaxXState;
979
980	pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
981	pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
982	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
983	pbXStates += cbMaxXState;
984
985	pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
986	pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
987	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
988	pbXStates += cbMaxXState;
989
990	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
991	}
992
993	/*
994	* Register saved state data item.
995	*/
996	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
997	NULL, cpumR3LiveExec, NULL,
998	NULL, cpumR3SaveExec, NULL,
999	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
1000	if (RT_FAILURE(rc))
1001	return rc;
1002
1003	/*
1004	* Register info handlers and registers with the debugger facility.
1005	*/
1006	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
1007	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
1008	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
1009	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
1010	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
1011	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
1012	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
1013	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
1014	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
1015	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
1016	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
1017	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
1018	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
1019
1020	rc = cpumR3DbgInit(pVM);
1021	if (RT_FAILURE(rc))
1022	return rc;
1023
1024	/*
1025	* Check if we need to workaround partial/leaky FPU handling.
1026	*/
1027	cpumR3CheckLeakyFpu(pVM);
1028
1029	/*
1030	* Initialize the Guest CPUID and MSR states.
1031	*/
1032	rc = cpumR3InitCpuIdAndMsrs(pVM);
1033	if (RT_FAILURE(rc))
1034	return rc;
1035
1036	/*
1037	* Allocate memory required by the guest hardware virtualization state.
1038	*/
1039	if (pVM->cpum.ro.GuestFeatures.fSvm)
1040	{
1041	rc = cpumR3AllocHwVirtState(pVM);
1042	if (RT_FAILURE(rc))
1043	return rc;
1044	}
1045
1046	CPUMR3Reset(pVM);
1047	return VINF_SUCCESS;
1048	}
1049
1050
1051	/**
1052	* Applies relocations to data and code managed by this
1053	* component. This function will be called at init and
1054	* whenever the VMM need to relocate it self inside the GC.
1055	*
1056	* The CPUM will update the addresses used by the switcher.
1057	*
1058	* @param pVM The cross context VM structure.
1059	*/
1060	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
1061	{
1062	LogFlow(("CPUMR3Relocate\n"));
1063
1064	pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
1065	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
1066
1067	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1068	{
1069	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1070	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
1071	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
1072	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
1073
1074	/* Recheck the guest DRx values in raw-mode. */
1075	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
1076	}
1077	}
1078
1079
1080	/**
1081	* Apply late CPUM property changes based on the fHWVirtEx setting
1082	*
1083	* @param pVM The cross context VM structure.
1084	* @param fHWVirtExEnabled HWVirtEx enabled/disabled
1085	*/
1086	VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
1087	{
1088	/*
1089	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
1090	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1091	* of processors from (cpuid(4).eax >> 26) + 1.
1092	*
1093	* Note: this code is obsolete, but let's keep it here for reference.
1094	* Purpose is valid when we artificially cap the max std id to less than 4.
1095	*/
1096	if (!fHWVirtExEnabled)
1097	{
1098	Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
1099	\|\| pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
1100	pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
1101	}
1102	}
1103
1104	/**
1105	* Terminates the CPUM.
1106	*
1107	* Termination means cleaning up and freeing all resources,
1108	* the VM it self is at this point powered off or suspended.
1109	*
1110	* @returns VBox status code.
1111	* @param pVM The cross context VM structure.
1112	*/
1113	VMMR3DECL(int) CPUMR3Term(PVM pVM)
1114	{
1115	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1116	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1117	{
1118	PVMCPU pVCpu = &pVM->aCpus[i];
1119	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1120
1121	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1122	pVCpu->cpum.s.uMagic = 0;
1123	pCtx->dr[5] = 0;
1124	}
1125	#endif
1126
1127	if (pVM->cpum.ro.GuestFeatures.fSvm)
1128	cpumR3FreeHwVirtState(pVM);
1129	return VINF_SUCCESS;
1130	}
1131
1132
1133	/**
1134	* Resets a virtual CPU.
1135	*
1136	* Used by CPUMR3Reset and CPU hot plugging.
1137	*
1138	* @param pVM The cross context VM structure.
1139	* @param pVCpu The cross context virtual CPU structure of the CPU that is
1140	* being reset. This may differ from the current EMT.
1141	*/
1142	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
1143	{
1144	/** @todo anything different for VCPU > 0? */
1145	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1146
1147	/*
1148	* Initialize everything to ZERO first.
1149	*/
1150	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1151
1152	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
1153	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
1154	memset(pCtx, 0, RT_OFFSETOF(CPUMCTX, pXStateR0));
1155
1156	pVCpu->cpum.s.fUseFlags = fUseFlags;
1157
1158	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
1159	pCtx->eip = 0x0000fff0;
1160	pCtx->edx = 0x00000600; /* P6 processor */
1161	pCtx->eflags.Bits.u1Reserved0 = 1;
1162
1163	pCtx->cs.Sel = 0xf000;
1164	pCtx->cs.ValidSel = 0xf000;
1165	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1166	pCtx->cs.u64Base = UINT64_C(0xffff0000);
1167	pCtx->cs.u32Limit = 0x0000ffff;
1168	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1169	pCtx->cs.Attr.n.u1Present = 1;
1170	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1171
1172	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1173	pCtx->ds.u32Limit = 0x0000ffff;
1174	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1175	pCtx->ds.Attr.n.u1Present = 1;
1176	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1177
1178	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1179	pCtx->es.u32Limit = 0x0000ffff;
1180	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1181	pCtx->es.Attr.n.u1Present = 1;
1182	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1183
1184	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1185	pCtx->fs.u32Limit = 0x0000ffff;
1186	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1187	pCtx->fs.Attr.n.u1Present = 1;
1188	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1189
1190	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1191	pCtx->gs.u32Limit = 0x0000ffff;
1192	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1193	pCtx->gs.Attr.n.u1Present = 1;
1194	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1195
1196	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1197	pCtx->ss.u32Limit = 0x0000ffff;
1198	pCtx->ss.Attr.n.u1Present = 1;
1199	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1200	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1201
1202	pCtx->idtr.cbIdt = 0xffff;
1203	pCtx->gdtr.cbGdt = 0xffff;
1204
1205	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1206	pCtx->ldtr.u32Limit = 0xffff;
1207	pCtx->ldtr.Attr.n.u1Present = 1;
1208	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1209
1210	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1211	pCtx->tr.u32Limit = 0xffff;
1212	pCtx->tr.Attr.n.u1Present = 1;
1213	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1214
1215	pCtx->dr[6] = X86_DR6_INIT_VAL;
1216	pCtx->dr[7] = X86_DR7_INIT_VAL;
1217
1218	PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
1219	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
1220	pFpuCtx->FCW = 0x37f;
1221
1222	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1223	IA-32 Processor States Following Power-up, Reset, or INIT */
1224	pFpuCtx->MXCSR = 0x1F80;
1225	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
1226
1227	pCtx->aXcr[0] = XSAVE_C_X87;
1228	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_OFFSETOF(X86XSAVEAREA, Hdr))
1229	{
1230	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
1231	as we don't know what happened before. (Bother optimize later?) */
1232	pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
1233	}
1234
1235	/*
1236	* MSRs.
1237	*/
1238	/* Init PAT MSR */
1239	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1240
1241	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1242	* The Intel docs don't mention it. */
1243	Assert(!pCtx->msrEFER);
1244
1245	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
1246	is supposed to be here, just trying provide useful/sensible values. */
1247	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
1248	if (pRange)
1249	{
1250	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1251	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1252	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
1253	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
1254	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1255	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
1256	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1257	}
1258
1259	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1260
1261	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1262	* called from each EMT while we're getting called by CPUMR3Reset()
1263	* iteratively on the same thread. Fix later. */
1264	#if 0 /** @todo r=bird: This we will do in TM, not here. */
1265	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1266	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1267	#endif
1268
1269
1270	/* C-state control. Guesses. */
1271	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
1272	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
1273	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
1274	* functionality. The default value must be different due to incompatible write mask.
1275	*/
1276	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
1277	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
1278
1279	/*
1280	* Hardware virtualization state.
1281	*/
1282	/* SVM. */
1283	if (pCtx->hwvirt.svm.CTX_SUFF(pVmcb))
1284	memset(pCtx->hwvirt.svm.CTX_SUFF(pVmcb), 0, SVM_VMCB_PAGES << PAGE_SHIFT);
1285	pCtx->hwvirt.svm.uMsrHSavePa = 0;
1286	pCtx->hwvirt.svm.GCPhysVmcb = 0;
1287	pCtx->hwvirt.svm.fGif = 1;
1288	}
1289
1290
1291	/**
1292	* Resets the CPU.
1293	*
1294	* @returns VINF_SUCCESS.
1295	* @param pVM The cross context VM structure.
1296	*/
1297	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1298	{
1299	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1300	{
1301	CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
1302
1303	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1304	PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1305
1306	/* Magic marker for searching in crash dumps. */
1307	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1308	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1309	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1310	#endif
1311	}
1312	}
1313
1314
1315
1316
1317	/**
1318	* Pass 0 live exec callback.
1319	*
1320	* @returns VINF_SSM_DONT_CALL_AGAIN.
1321	* @param pVM The cross context VM structure.
1322	* @param pSSM The saved state handle.
1323	* @param uPass The pass (0).
1324	*/
1325	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1326	{
1327	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
1328	cpumR3SaveCpuId(pVM, pSSM);
1329	return VINF_SSM_DONT_CALL_AGAIN;
1330	}
1331
1332
1333	/**
1334	* Execute state save operation.
1335	*
1336	* @returns VBox status code.
1337	* @param pVM The cross context VM structure.
1338	* @param pSSM SSM operation handle.
1339	*/
1340	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1341	{
1342	/*
1343	* Save.
1344	*/
1345	SSMR3PutU32(pSSM, pVM->cCpus);
1346	SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
1347	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1348	{
1349	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1350
1351	SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1352
1353	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1354	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1355	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1356	if (pGstCtx->fXStateMask != 0)
1357	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
1358	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1359	{
1360	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1361	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1362	}
1363	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1364	{
1365	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1366	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1367	}
1368	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1369	{
1370	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1371	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1372	}
1373	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1374	{
1375	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1376	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1377	}
1378	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1379	{
1380	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1381	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1382	}
1383
1384	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1385	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1386	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
1387	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
1388	}
1389
1390	cpumR3SaveCpuId(pVM, pSSM);
1391	return VINF_SUCCESS;
1392	}
1393
1394
1395	/**
1396	* @callback_method_impl{FNSSMINTLOADPREP}
1397	*/
1398	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1399	{
1400	NOREF(pSSM);
1401	pVM->cpum.s.fPendingRestore = true;
1402	return VINF_SUCCESS;
1403	}
1404
1405
1406	/**
1407	* @callback_method_impl{FNSSMINTLOADEXEC}
1408	*/
1409	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1410	{
1411	int rc; /* Only for AssertRCReturn use. */
1412
1413	/*
1414	* Validate version.
1415	*/
1416	if ( uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
1417	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
1418	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
1419	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
1420	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
1421	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
1422	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
1423	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1424	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1425	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1426	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1427	{
1428	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1429	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1430	}
1431
1432	if (uPass == SSM_PASS_FINAL)
1433	{
1434	/*
1435	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1436	* really old SSM file versions.)
1437	*/
1438	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1439	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1440	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1441	SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1442
1443	/*
1444	* Figure x86 and ctx field definitions to use for older states.
1445	*/
1446	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
1447	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
1448	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
1449	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1450	{
1451	paCpumCtx1Fields = g_aCpumX87FieldsV16;
1452	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
1453	}
1454	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1455	{
1456	paCpumCtx1Fields = g_aCpumX87FieldsMem;
1457	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
1458	}
1459
1460	/*
1461	* The hyper state used to preceed the CPU count. Starting with
1462	* XSAVE it was moved down till after we've got the count.
1463	*/
1464	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
1465	{
1466	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1467	{
1468	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1469	X86FXSTATE Ign;
1470	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1471	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1472	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1473	SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
1474	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1475	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1476	pVCpu->cpum.s.Hyper.rsp = uRSP;
1477	}
1478	}
1479
1480	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1481	{
1482	uint32_t cCpus;
1483	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1484	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1485	VERR_SSM_UNEXPECTED_DATA);
1486	}
1487	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
1488	\|\| pVM->cCpus == 1,
1489	("cCpus=%u\n", pVM->cCpus),
1490	VERR_SSM_UNEXPECTED_DATA);
1491
1492	uint32_t cbMsrs = 0;
1493	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1494	{
1495	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
1496	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
1497	VERR_SSM_UNEXPECTED_DATA);
1498	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
1499	VERR_SSM_UNEXPECTED_DATA);
1500	}
1501
1502	/*
1503	* Do the per-CPU restoring.
1504	*/
1505	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1506	{
1507	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1508	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1509
1510	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
1511	{
1512	/*
1513	* The XSAVE saved state layout moved the hyper state down here.
1514	*/
1515	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1516	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1517	rc = SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1518	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1519	pVCpu->cpum.s.Hyper.rsp = uRSP;
1520	AssertRCReturn(rc, rc);
1521
1522	/*
1523	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
1524	*/
1525	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1526	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1527	AssertRCReturn(rc, rc);
1528
1529	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
1530	if (pGstCtx->fXStateMask != 0)
1531	{
1532	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
1533	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
1534	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
1535	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
1536	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
1537	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1538	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
1539	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1540	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
1541	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
1542	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
1543	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1544	}
1545
1546	/* Check that the XCR0 mask is valid (invalid results in #GP). */
1547	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
1548	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
1549	{
1550	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
1551	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
1552	VERR_CPUM_INVALID_XCR0);
1553	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
1554	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1555	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
1556	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1557	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
1558	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
1559	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
1560	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1561	}
1562
1563	/* Check that the XCR1 is zero, as we don't implement it yet. */
1564	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
1565
1566	/*
1567	* Restore the individual extended state components we support.
1568	*/
1569	if (pGstCtx->fXStateMask != 0)
1570	{
1571	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
1572	0, g_aCpumXSaveHdrFields, NULL);
1573	AssertRCReturn(rc, rc);
1574	AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
1575	("bmXState=%#RX64 fXStateMask=%#RX64\n",
1576	pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
1577	VERR_CPUM_INVALID_XSAVE_HDR);
1578	}
1579	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1580	{
1581	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
1582	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1583	}
1584	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1585	{
1586	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
1587	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1588	}
1589	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1590	{
1591	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
1592	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1593	}
1594	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1595	{
1596	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
1597	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1598	}
1599	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1600	{
1601	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
1602	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1603	}
1604	}
1605	else
1606	{
1607	/*
1608	* Pre XSAVE saved state.
1609	*/
1610	SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
1611	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1612	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1613	}
1614
1615	/*
1616	* Restore a couple of flags and the MSRs.
1617	*/
1618	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
1619	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
1620
1621	rc = VINF_SUCCESS;
1622	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1623	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
1624	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1625	{
1626	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
1627	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
1628	}
1629	AssertRCReturn(rc, rc);
1630
1631	/* REM and other may have cleared must-be-one fields in DR6 and
1632	DR7, fix these. */
1633	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
1634	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
1635	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
1636	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
1637	}
1638
1639	/* Older states does not have the internal selector register flags
1640	and valid selector value. Supply those. */
1641	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1642	{
1643	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1644	{
1645	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1646	bool const fValid = HMIsEnabled(pVM)
1647	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1648	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
1649	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
1650	if (fValid)
1651	{
1652	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1653	{
1654	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
1655	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
1656	}
1657
1658	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1659	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1660	}
1661	else
1662	{
1663	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1664	{
1665	paSelReg[iSelReg].fFlags = 0;
1666	paSelReg[iSelReg].ValidSel = 0;
1667	}
1668
1669	/* This might not be 104% correct, but I think it's close
1670	enough for all practical purposes... (REM always loaded
1671	LDTR registers.) */
1672	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1673	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1674	}
1675	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1676	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
1677	}
1678	}
1679
1680	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
1681	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1682	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1683	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1684	pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
1685
1686	/*
1687	* A quick sanity check.
1688	*/
1689	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1690	{
1691	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1692	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1693	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1694	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1695	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1696	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1697	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1698	}
1699	}
1700
1701	pVM->cpum.s.fPendingRestore = false;
1702
1703	/*
1704	* Guest CPUIDs.
1705	*/
1706	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
1707	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1708	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
1709	}
1710
1711
1712	/**
1713	* @callback_method_impl{FNSSMINTLOADDONE}
1714	*/
1715	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
1716	{
1717	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
1718	return VINF_SUCCESS;
1719
1720	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
1721	if (pVM->cpum.s.fPendingRestore)
1722	{
1723	LogRel(("CPUM: Missing state!\n"));
1724	return VERR_INTERNAL_ERROR_2;
1725	}
1726
1727	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
1728	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1729	{
1730	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1731
1732	/* Notify PGM of the NXE states in case they've changed. */
1733	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
1734
1735	/* During init. this is done in CPUMR3InitCompleted(). */
1736	if (fSupportsLongMode)
1737	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
1738	}
1739	return VINF_SUCCESS;
1740	}
1741
1742
1743	/**
1744	* Checks if the CPUM state restore is still pending.
1745	*
1746	* @returns true / false.
1747	* @param pVM The cross context VM structure.
1748	*/
1749	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
1750	{
1751	return pVM->cpum.s.fPendingRestore;
1752	}
1753
1754
1755	/**
1756	* Formats the EFLAGS value into mnemonics.
1757	*
1758	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1759	* @param efl The EFLAGS value.
1760	*/
1761	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1762	{
1763	/*
1764	* Format the flags.
1765	*/
1766	static const struct
1767	{
1768	const char pszSet; const char pszClear; uint32_t fFlag;
1769	} s_aFlags[] =
1770	{
1771	{ "vip",NULL, X86_EFL_VIP },
1772	{ "vif",NULL, X86_EFL_VIF },
1773	{ "ac", NULL, X86_EFL_AC },
1774	{ "vm", NULL, X86_EFL_VM },
1775	{ "rf", NULL, X86_EFL_RF },
1776	{ "nt", NULL, X86_EFL_NT },
1777	{ "ov", "nv", X86_EFL_OF },
1778	{ "dn", "up", X86_EFL_DF },
1779	{ "ei", "di", X86_EFL_IF },
1780	{ "tf", NULL, X86_EFL_TF },
1781	{ "nt", "pl", X86_EFL_SF },
1782	{ "nz", "zr", X86_EFL_ZF },
1783	{ "ac", "na", X86_EFL_AF },
1784	{ "po", "pe", X86_EFL_PF },
1785	{ "cy", "nc", X86_EFL_CF },
1786	};
1787	char *psz = pszEFlags;
1788	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1789	{
1790	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1791	if (pszAdd)
1792	{
1793	strcpy(psz, pszAdd);
1794	psz += strlen(pszAdd);
1795	*psz++ = ' ';
1796	}
1797	}
1798	psz[-1] = '\0';
1799	}
1800
1801
1802	/**
1803	* Formats a full register dump.
1804	*
1805	* @param pVM The cross context VM structure.
1806	* @param pCtx The context to format.
1807	* @param pCtxCore The context core to format.
1808	* @param pHlp Output functions.
1809	* @param enmType The dump type.
1810	* @param pszPrefix Register name prefix.
1811	*/
1812	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
1813	const char *pszPrefix)
1814	{
1815	NOREF(pVM);
1816
1817	/*
1818	* Format the EFLAGS.
1819	*/
1820	uint32_t efl = pCtxCore->eflags.u32;
1821	char szEFlags[80];
1822	cpumR3InfoFormatFlags(&szEFlags[0], efl);
1823
1824	/*
1825	* Format the registers.
1826	*/
1827	switch (enmType)
1828	{
1829	case CPUMDUMPTYPE_TERSE:
1830	if (CPUMIsGuestIn64BitCodeEx(pCtx))
1831	pHlp->pfnPrintf(pHlp,
1832	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1833	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1834	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1835	"%sr14=%016RX64 %sr15=%016RX64\n"
1836	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1837	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1838	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1839	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1840	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1841	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1842	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1843	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1844	else
1845	pHlp->pfnPrintf(pHlp,
1846	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1847	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1848	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1849	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1850	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1851	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1852	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1853	break;
1854
1855	case CPUMDUMPTYPE_DEFAULT:
1856	if (CPUMIsGuestIn64BitCodeEx(pCtx))
1857	pHlp->pfnPrintf(pHlp,
1858	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1859	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1860	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1861	"%sr14=%016RX64 %sr15=%016RX64\n"
1862	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1863	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1864	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1865	,
1866	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1867	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1868	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1869	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1870	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1871	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1872	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1873	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1874	else
1875	pHlp->pfnPrintf(pHlp,
1876	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1877	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1878	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1879	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1880	,
1881	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1882	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1883	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1884	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1885	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1886	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1887	break;
1888
1889	case CPUMDUMPTYPE_VERBOSE:
1890	if (CPUMIsGuestIn64BitCodeEx(pCtx))
1891	pHlp->pfnPrintf(pHlp,
1892	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1893	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1894	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1895	"%sr14=%016RX64 %sr15=%016RX64\n"
1896	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1897	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1898	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1899	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1900	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1901	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1902	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1903	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1904	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1905	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1906	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1907	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1908	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1909	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1910	,
1911	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1912	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1913	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1914	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1915	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1916	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1917	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1918	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1919	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1920	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1921	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1922	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1923	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1924	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1925	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1926	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1927	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1928	else
1929	pHlp->pfnPrintf(pHlp,
1930	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1931	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1932	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1933	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1934	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1935	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1936	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1937	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1938	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1939	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1940	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1941	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1942	,
1943	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1944	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1945	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1946	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1947	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1948	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1949	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1950	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1951	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1952	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1953	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1954	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1955
1956	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
1957	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
1958	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
1959	if (pCtx->CTX_SUFF(pXState))
1960	{
1961	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1962	pHlp->pfnPrintf(pHlp,
1963	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1964	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
1965	,
1966	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
1967	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
1968	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
1969	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
1970	);
1971	/*
1972	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
1973	* not (FP)R0-7 as Intel SDM suggests.
1974	*/
1975	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
1976	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
1977	{
1978	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
1979	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
1980	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
1981	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
1982	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
1983	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
1984	iExponent -= 16383; /* subtract bias */
1985	/** @todo This isn't entirenly correct and needs more work! */
1986	pHlp->pfnPrintf(pHlp,
1987	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
1988	pszPrefix, iST, pszPrefix, iFPR,
1989	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
1990	uTag, chSign, iInteger, u64Fraction, iExponent);
1991	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
1992	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
1993	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
1994	else
1995	pHlp->pfnPrintf(pHlp, "\n");
1996	}
1997
1998	/* XMM/YMM/ZMM registers. */
1999	if (pCtx->fXStateMask & XSAVE_C_YMM)
2000	{
2001	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2002	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
2003	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2004	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2005	pszPrefix, i, i < 10 ? " " : "",
2006	pYmmHiCtx->aYmmHi[i].au32[3],
2007	pYmmHiCtx->aYmmHi[i].au32[2],
2008	pYmmHiCtx->aYmmHi[i].au32[1],
2009	pYmmHiCtx->aYmmHi[i].au32[0],
2010	pFpuCtx->aXMM[i].au32[3],
2011	pFpuCtx->aXMM[i].au32[2],
2012	pFpuCtx->aXMM[i].au32[1],
2013	pFpuCtx->aXMM[i].au32[0]);
2014	else
2015	{
2016	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2017	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2018	pHlp->pfnPrintf(pHlp,
2019	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2020	pszPrefix, i, i < 10 ? " " : "",
2021	pZmmHi256->aHi256Regs[i].au32[7],
2022	pZmmHi256->aHi256Regs[i].au32[6],
2023	pZmmHi256->aHi256Regs[i].au32[5],
2024	pZmmHi256->aHi256Regs[i].au32[4],
2025	pZmmHi256->aHi256Regs[i].au32[3],
2026	pZmmHi256->aHi256Regs[i].au32[2],
2027	pZmmHi256->aHi256Regs[i].au32[1],
2028	pZmmHi256->aHi256Regs[i].au32[0],
2029	pYmmHiCtx->aYmmHi[i].au32[3],
2030	pYmmHiCtx->aYmmHi[i].au32[2],
2031	pYmmHiCtx->aYmmHi[i].au32[1],
2032	pYmmHiCtx->aYmmHi[i].au32[0],
2033	pFpuCtx->aXMM[i].au32[3],
2034	pFpuCtx->aXMM[i].au32[2],
2035	pFpuCtx->aXMM[i].au32[1],
2036	pFpuCtx->aXMM[i].au32[0]);
2037
2038	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2039	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
2040	pHlp->pfnPrintf(pHlp,
2041	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2042	pszPrefix, i + 16,
2043	pZmm16Hi->aRegs[i].au32[15],
2044	pZmm16Hi->aRegs[i].au32[14],
2045	pZmm16Hi->aRegs[i].au32[13],
2046	pZmm16Hi->aRegs[i].au32[12],
2047	pZmm16Hi->aRegs[i].au32[11],
2048	pZmm16Hi->aRegs[i].au32[10],
2049	pZmm16Hi->aRegs[i].au32[9],
2050	pZmm16Hi->aRegs[i].au32[8],
2051	pZmm16Hi->aRegs[i].au32[7],
2052	pZmm16Hi->aRegs[i].au32[6],
2053	pZmm16Hi->aRegs[i].au32[5],
2054	pZmm16Hi->aRegs[i].au32[4],
2055	pZmm16Hi->aRegs[i].au32[3],
2056	pZmm16Hi->aRegs[i].au32[2],
2057	pZmm16Hi->aRegs[i].au32[1],
2058	pZmm16Hi->aRegs[i].au32[0]);
2059	}
2060	}
2061	else
2062	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2063	pHlp->pfnPrintf(pHlp,
2064	i & 1
2065	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2066	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2067	pszPrefix, i, i < 10 ? " " : "",
2068	pFpuCtx->aXMM[i].au32[3],
2069	pFpuCtx->aXMM[i].au32[2],
2070	pFpuCtx->aXMM[i].au32[1],
2071	pFpuCtx->aXMM[i].au32[0]);
2072
2073	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
2074	{
2075	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
2076	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
2077	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
2078	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
2079	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
2080	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
2081	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
2082	}
2083
2084	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
2085	{
2086	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2087	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
2088	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
2089	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
2090	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
2091	}
2092
2093	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
2094	{
2095	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2096	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
2097	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
2098	}
2099
2100	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
2101	if (pFpuCtx->au32RsrvdRest[i])
2102	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
2103	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2104	}
2105
2106	pHlp->pfnPrintf(pHlp,
2107	"%sEFER =%016RX64\n"
2108	"%sPAT =%016RX64\n"
2109	"%sSTAR =%016RX64\n"
2110	"%sCSTAR =%016RX64\n"
2111	"%sLSTAR =%016RX64\n"
2112	"%sSFMASK =%016RX64\n"
2113	"%sKERNELGSBASE =%016RX64\n",
2114	pszPrefix, pCtx->msrEFER,
2115	pszPrefix, pCtx->msrPAT,
2116	pszPrefix, pCtx->msrSTAR,
2117	pszPrefix, pCtx->msrCSTAR,
2118	pszPrefix, pCtx->msrLSTAR,
2119	pszPrefix, pCtx->msrSFMASK,
2120	pszPrefix, pCtx->msrKERNELGSBASE);
2121	break;
2122	}
2123	}
2124
2125
2126	/**
2127	* Display all cpu states and any other cpum info.
2128	*
2129	* @param pVM The cross context VM structure.
2130	* @param pHlp The info helper functions.
2131	* @param pszArgs Arguments, ignored.
2132	*/
2133	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2134	{
2135	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2136	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2137	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
2138	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2139	cpumR3InfoHost(pVM, pHlp, pszArgs);
2140	}
2141
2142
2143	/**
2144	* Parses the info argument.
2145	*
2146	* The argument starts with 'verbose', 'terse' or 'default' and then
2147	* continues with the comment string.
2148	*
2149	* @param pszArgs The pointer to the argument string.
2150	* @param penmType Where to store the dump type request.
2151	* @param ppszComment Where to store the pointer to the comment string.
2152	*/
2153	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2154	{
2155	if (!pszArgs)
2156	{
2157	*penmType = CPUMDUMPTYPE_DEFAULT;
2158	*ppszComment = "";
2159	}
2160	else
2161	{
2162	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
2163	{
2164	pszArgs += 7;
2165	*penmType = CPUMDUMPTYPE_VERBOSE;
2166	}
2167	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
2168	{
2169	pszArgs += 5;
2170	*penmType = CPUMDUMPTYPE_TERSE;
2171	}
2172	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
2173	{
2174	pszArgs += 7;
2175	*penmType = CPUMDUMPTYPE_DEFAULT;
2176	}
2177	else
2178	*penmType = CPUMDUMPTYPE_DEFAULT;
2179	*ppszComment = RTStrStripL(pszArgs);
2180	}
2181	}
2182
2183
2184	/**
2185	* Display the guest cpu state.
2186	*
2187	* @param pVM The cross context VM structure.
2188	* @param pHlp The info helper functions.
2189	* @param pszArgs Arguments.
2190	*/
2191	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2192	{
2193	CPUMDUMPTYPE enmType;
2194	const char *pszComment;
2195	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2196
2197	PVMCPU pVCpu = VMMGetCpu(pVM);
2198	if (!pVCpu)
2199	pVCpu = &pVM->aCpus[0];
2200
2201	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2202
2203	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2204	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2205	}
2206
2207
2208	/**
2209	* Display the guest's hardware-virtualization cpu state.
2210	*
2211	* @param pVM The cross context VM structure.
2212	* @param pHlp The info helper functions.
2213	* @param pszArgs Arguments, ignored.
2214	*/
2215	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2216	{
2217	RT_NOREF(pszArgs);
2218
2219	PVMCPU pVCpu = VMMGetCpu(pVM);
2220	if (!pVCpu)
2221	pVCpu = &pVM->aCpus[0];
2222
2223	/*
2224	* Figure out what to dump.
2225	*
2226	* In the future we may need to dump everything whether or not we're actively in nested-guest mode
2227	* or not, hence the reason why we use a mask to determine what needs dumping. Currently, we only
2228	* dump hwvirt. state when the guest CPU is executing a nested-guest.
2229	*/
2230	/** @todo perhaps make this configurable through pszArgs, depending on how much
2231	* noise we wish to accept when nested hwvirt. isn't used. */
2232	#define CPUMHWVIRTDUMP_NONE (0)
2233	#define CPUMHWVIRTDUMP_SVM RT_BIT(0)
2234	#define CPUMHWVIRTDUMP_VMX RT_BIT(1)
2235	#define CPUMHWVIRTDUMP_COMMON RT_BIT(2)
2236	#define CPUMHWVIRTDUMP_LAST CPUMHWVIRTDUMP_VMX
2237	#define CPUMHWVIRTDUMP_ALL (CPUMHWVIRTDUMP_COMMON \| CPUMHWVIRTDUMP_VMX \| CPUMHWVIRTDUMP_SVM)
2238
2239	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2240	static const char *const s_aHwvirtModes[] = { "No/inactive", "SVM", "VMX", "Common" };
2241	uint8_t const idxHwvirtState = CPUMIsGuestInSvmNestedHwVirtMode(pCtx) ? CPUMHWVIRTDUMP_SVM
2242	: CPUMIsGuestInVmxNestedHwVirtMode(pCtx) ? CPUMHWVIRTDUMP_VMX : CPUMHWVIRTDUMP_NONE;
2243	AssertCompile(CPUMHWVIRTDUMP_LAST <= RT_ELEMENTS(s_aHwvirtModes));
2244	Assert(idxHwvirtState < RT_ELEMENTS(s_aHwvirtModes));
2245	const char *pcszHwvirtMode = s_aHwvirtModes[idxHwvirtState];
2246	uint32_t const fDumpState = idxHwvirtState; /* \| CPUMHWVIRTDUMP_ALL */
2247
2248	/*
2249	* Dump it.
2250	*/
2251	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
2252
2253	if (fDumpState & CPUMHWVIRTDUMP_COMMON)
2254	pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
2255	pHlp->pfnPrintf(pHlp, "%s hwvirt state%s\n", pcszHwvirtMode, fDumpState ? ":" : "");
2256	if (fDumpState & CPUMHWVIRTDUMP_SVM)
2257	{
2258	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
2259	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
2260	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
2261	HMR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.pVmcbR3->ctrl, " " /* pszPrefix */);
2262	/** @todo HMR3InfoSvmVmcbStateSave. */
2263	pHlp->pfnPrintf(pHlp, " HostState:\n");
2264	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
2265	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
2266	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
2267	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
2268	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
2269	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
2270	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
2271	pHlp->pfnPrintf(pHlp, " rflags = %#RX64\n", pCtx->hwvirt.svm.HostState.rflags.u64);
2272	PCPUMSELREG pSel = &pCtx->hwvirt.svm.HostState.es;
2273	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2274	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->fFlags);
2275	pSel = &pCtx->hwvirt.svm.HostState.cs;
2276	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2277	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->fFlags);
2278	pSel = &pCtx->hwvirt.svm.HostState.ss;
2279	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2280	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->fFlags);
2281	pSel = &pCtx->hwvirt.svm.HostState.ds;
2282	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2283	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->fFlags);
2284	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
2285	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
2286	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
2287	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
2288	pHlp->pfnPrintf(pHlp, " fGif = %u\n", pCtx->hwvirt.svm.fGif);
2289	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
2290	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
2291	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
2292	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR3 = %p\n", pCtx->hwvirt.svm.pvMsrBitmapR3);
2293	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvMsrBitmapR0);
2294	pHlp->pfnPrintf(pHlp, " pvIoBitmapR3 = %p\n", pCtx->hwvirt.svm.pvIoBitmapR3);
2295	pHlp->pfnPrintf(pHlp, " pvIoBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvIoBitmapR0);
2296	}
2297
2298	/** @todo Intel. */
2299	#if 0
2300	if (fDumpState & CPUMHWVIRTDUMP_VMX)
2301	{
2302	}
2303	#endif
2304
2305	#undef CPUMHWVIRTDUMP_NONE
2306	#undef CPUMHWVIRTDUMP_COMMON
2307	#undef CPUMHWVIRTDUMP_SVM
2308	#undef CPUMHWVIRTDUMP_VMX
2309	#undef CPUMHWVIRTDUMP_LAST
2310	#undef CPUMHWVIRTDUMP_ALL
2311	}
2312
2313	/**
2314	* Display the current guest instruction
2315	*
2316	* @param pVM The cross context VM structure.
2317	* @param pHlp The info helper functions.
2318	* @param pszArgs Arguments, ignored.
2319	*/
2320	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2321	{
2322	NOREF(pszArgs);
2323
2324	PVMCPU pVCpu = VMMGetCpu(pVM);
2325	if (!pVCpu)
2326	pVCpu = &pVM->aCpus[0];
2327
2328	char szInstruction[256];
2329	szInstruction[0] = '\0';
2330	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2331	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
2332	}
2333
2334
2335	/**
2336	* Display the hypervisor cpu state.
2337	*
2338	* @param pVM The cross context VM structure.
2339	* @param pHlp The info helper functions.
2340	* @param pszArgs Arguments, ignored.
2341	*/
2342	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2343	{
2344	PVMCPU pVCpu = VMMGetCpu(pVM);
2345	if (!pVCpu)
2346	pVCpu = &pVM->aCpus[0];
2347
2348	CPUMDUMPTYPE enmType;
2349	const char *pszComment;
2350	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2351	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2352	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
2353	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2354	}
2355
2356
2357	/**
2358	* Display the host cpu state.
2359	*
2360	* @param pVM The cross context VM structure.
2361	* @param pHlp The info helper functions.
2362	* @param pszArgs Arguments, ignored.
2363	*/
2364	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2365	{
2366	CPUMDUMPTYPE enmType;
2367	const char *pszComment;
2368	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2369	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2370
2371	PVMCPU pVCpu = VMMGetCpu(pVM);
2372	if (!pVCpu)
2373	pVCpu = &pVM->aCpus[0];
2374	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
2375
2376	/*
2377	* Format the EFLAGS.
2378	*/
2379	#if HC_ARCH_BITS == 32
2380	uint32_t efl = pCtx->eflags.u32;
2381	#else
2382	uint64_t efl = pCtx->rflags;
2383	#endif
2384	char szEFlags[80];
2385	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2386
2387	/*
2388	* Format the registers.
2389	*/
2390	#if HC_ARCH_BITS == 32
2391	pHlp->pfnPrintf(pHlp,
2392	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2393	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2394	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2395	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2396	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2397	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2398	,
2399	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
2400	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2401	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2402	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
2403	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2404	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
2405	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2406	#else
2407	pHlp->pfnPrintf(pHlp,
2408	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2409	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2410	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2411	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2412	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2413	"r14=%016RX64 r15=%016RX64\n"
2414	"iopl=%d %31s\n"
2415	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2416	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2417	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
2418	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2419	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2420	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2421	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2422	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2423	,
2424	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
2425	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2426	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
2427	/pCtx->r8, pCtx->r9,/ pCtx->r10,
2428	pCtx->r11, pCtx->r12, pCtx->r13,
2429	pCtx->r14, pCtx->r15,
2430	X86_EFL_GET_IOPL(efl), szEFlags,
2431	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2432	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
2433	pCtx->cr4, pCtx->ldtr, pCtx->tr,
2434	pCtx->dr0, pCtx->dr1, pCtx->dr2,
2435	pCtx->dr3, pCtx->dr6, pCtx->dr7,
2436	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2437	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2438	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2439	#endif
2440	}
2441
2442	/**
2443	* Structure used when disassembling and instructions in DBGF.
2444	* This is used so the reader function can get the stuff it needs.
2445	*/
2446	typedef struct CPUMDISASSTATE
2447	{
2448	/** Pointer to the CPU structure. */
2449	PDISCPUSTATE pCpu;
2450	/** Pointer to the VM. */
2451	PVM pVM;
2452	/** Pointer to the VMCPU. */
2453	PVMCPU pVCpu;
2454	/** Pointer to the first byte in the segment. */
2455	RTGCUINTPTR GCPtrSegBase;
2456	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
2457	RTGCUINTPTR GCPtrSegEnd;
2458	/** The size of the segment minus 1. */
2459	RTGCUINTPTR cbSegLimit;
2460	/** Pointer to the current page - R3 Ptr. */
2461	void const *pvPageR3;
2462	/** Pointer to the current page - GC Ptr. */
2463	RTGCPTR pvPageGC;
2464	/** The lock information that PGMPhysReleasePageMappingLock needs. */
2465	PGMPAGEMAPLOCK PageMapLock;
2466	/** Whether the PageMapLock is valid or not. */
2467	bool fLocked;
2468	/** 64 bits mode or not. */
2469	bool f64Bits;
2470	} CPUMDISASSTATE, *PCPUMDISASSTATE;
2471
2472
2473	/**
2474	* @callback_method_impl{FNDISREADBYTES}
2475	*/
2476	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
2477	{
2478	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
2479	for (;;)
2480	{
2481	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
2482
2483	/*
2484	* Need to update the page translation?
2485	*/
2486	if ( !pState->pvPageR3
2487	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2488	{
2489	int rc = VINF_SUCCESS;
2490
2491	/* translate the address */
2492	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2493	if ( !HMIsEnabled(pState->pVM)
2494	&& MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
2495	{
2496	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2497	if (!pState->pvPageR3)
2498	rc = VERR_INVALID_POINTER;
2499	}
2500	else
2501	{
2502	/* Release mapping lock previously acquired. */
2503	if (pState->fLocked)
2504	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2505	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2506	pState->fLocked = RT_SUCCESS_NP(rc);
2507	}
2508	if (RT_FAILURE(rc))
2509	{
2510	pState->pvPageR3 = NULL;
2511	return rc;
2512	}
2513	}
2514
2515	/*
2516	* Check the segment limit.
2517	*/
2518	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
2519	return VERR_OUT_OF_SELECTOR_BOUNDS;
2520
2521	/*
2522	* Calc how much we can read.
2523	*/
2524	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2525	if (!pState->f64Bits)
2526	{
2527	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2528	if (cb > cbSeg && cbSeg)
2529	cb = cbSeg;
2530	}
2531	if (cb > cbMaxRead)
2532	cb = cbMaxRead;
2533
2534	/*
2535	* Read and advance or exit.
2536	*/
2537	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2538	offInstr += (uint8_t)cb;
2539	if (cb >= cbMinRead)
2540	{
2541	pDis->cbCachedInstr = offInstr;
2542	return VINF_SUCCESS;
2543	}
2544	cbMinRead -= (uint8_t)cb;
2545	cbMaxRead -= (uint8_t)cb;
2546	}
2547	}
2548
2549
2550	/**
2551	* Disassemble an instruction and return the information in the provided structure.
2552	*
2553	* @returns VBox status code.
2554	* @param pVM The cross context VM structure.
2555	* @param pVCpu The cross context virtual CPU structure.
2556	* @param pCtx Pointer to the guest CPU context.
2557	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
2558	* @param pCpu Disassembly state.
2559	* @param pszPrefix String prefix for logging (debug only).
2560	*
2561	*/
2562	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
2563	const char *pszPrefix)
2564	{
2565	CPUMDISASSTATE State;
2566	int rc;
2567
2568	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2569	State.pCpu = pCpu;
2570	State.pvPageGC = 0;
2571	State.pvPageR3 = NULL;
2572	State.pVM = pVM;
2573	State.pVCpu = pVCpu;
2574	State.fLocked = false;
2575	State.f64Bits = false;
2576
2577	/*
2578	* Get selector information.
2579	*/
2580	DISCPUMODE enmDisCpuMode;
2581	if ( (pCtx->cr0 & X86_CR0_PE)
2582	&& pCtx->eflags.Bits.u1VM == 0)
2583	{
2584	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2585	{
2586	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2587	CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
2588	# endif
2589	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2590	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
2591	}
2592	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
2593	State.GCPtrSegBase = pCtx->cs.u64Base;
2594	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
2595	State.cbSegLimit = pCtx->cs.u32Limit;
2596	enmDisCpuMode = (State.f64Bits)
2597	? DISCPUMODE_64BIT
2598	: pCtx->cs.Attr.n.u1DefBig
2599	? DISCPUMODE_32BIT
2600	: DISCPUMODE_16BIT;
2601	}
2602	else
2603	{
2604	/* real or V86 mode */
2605	enmDisCpuMode = DISCPUMODE_16BIT;
2606	State.GCPtrSegBase = pCtx->cs.Sel * 16;
2607	State.GCPtrSegEnd = 0xFFFFFFFF;
2608	State.cbSegLimit = 0xFFFFFFFF;
2609	}
2610
2611	/*
2612	* Disassemble the instruction.
2613	*/
2614	uint32_t cbInstr;
2615	#ifndef LOG_ENABLED
2616	RT_NOREF_PV(pszPrefix);
2617	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
2618	if (RT_SUCCESS(rc))
2619	{
2620	#else
2621	char szOutput[160];
2622	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
2623	pCpu, &cbInstr, szOutput, sizeof(szOutput));
2624	if (RT_SUCCESS(rc))
2625	{
2626	/* log it */
2627	if (pszPrefix)
2628	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2629	else
2630	Log(("%s", szOutput));
2631	#endif
2632	rc = VINF_SUCCESS;
2633	}
2634	else
2635	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
2636
2637	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
2638	if (State.fLocked)
2639	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2640
2641	return rc;
2642	}
2643
2644
2645
2646	/**
2647	* API for controlling a few of the CPU features found in CR4.
2648	*
2649	* Currently only X86_CR4_TSD is accepted as input.
2650	*
2651	* @returns VBox status code.
2652	*
2653	* @param pVM The cross context VM structure.
2654	* @param fOr The CR4 OR mask.
2655	* @param fAnd The CR4 AND mask.
2656	*/
2657	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2658	{
2659	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2660	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2661
2662	pVM->cpum.s.CR4.OrMask &= fAnd;
2663	pVM->cpum.s.CR4.OrMask \|= fOr;
2664
2665	return VINF_SUCCESS;
2666	}
2667
2668
2669	/**
2670	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
2671	*
2672	* Only REM should ever call this function!
2673	*
2674	* @returns The changed flags.
2675	* @param pVCpu The cross context virtual CPU structure.
2676	* @param puCpl Where to return the current privilege level (CPL).
2677	*/
2678	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
2679	{
2680	Assert(!pVCpu->cpum.s.fRawEntered);
2681	Assert(!pVCpu->cpum.s.fRemEntered);
2682
2683	/*
2684	* Get the CPL first.
2685	*/
2686	*puCpl = CPUMGetGuestCPL(pVCpu);
2687
2688	/*
2689	* Get and reset the flags.
2690	*/
2691	uint32_t fFlags = pVCpu->cpum.s.fChanged;
2692	pVCpu->cpum.s.fChanged = 0;
2693
2694	/** @todo change the switcher to use the fChanged flags. */
2695	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
2696	{
2697	fFlags \|= CPUM_CHANGED_FPU_REM;
2698	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
2699	}
2700
2701	pVCpu->cpum.s.fRemEntered = true;
2702	return fFlags;
2703	}
2704
2705
2706	/**
2707	* Leaves REM.
2708	*
2709	* @param pVCpu The cross context virtual CPU structure.
2710	* @param fNoOutOfSyncSels This is @c false if there are out of sync
2711	* registers.
2712	*/
2713	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
2714	{
2715	Assert(!pVCpu->cpum.s.fRawEntered);
2716	Assert(pVCpu->cpum.s.fRemEntered);
2717
2718	RT_NOREF_PV(fNoOutOfSyncSels);
2719
2720	pVCpu->cpum.s.fRemEntered = false;
2721	}
2722
2723
2724	/**
2725	* Called when the ring-3 init phase completes.
2726	*
2727	* @returns VBox status code.
2728	* @param pVM The cross context VM structure.
2729	* @param enmWhat Which init phase.
2730	*/
2731	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
2732	{
2733	switch (enmWhat)
2734	{
2735	case VMINITCOMPLETED_RING3:
2736	{
2737	/*
2738	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
2739	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
2740	*/
2741	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2742	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2743	{
2744	PVMCPU pVCpu = &pVM->aCpus[i];
2745	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
2746	if (fSupportsLongMode)
2747	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
2748	}
2749
2750	cpumR3MsrRegStats(pVM);
2751	break;
2752	}
2753
2754	default:
2755	break;
2756	}
2757	return VINF_SUCCESS;
2758	}
2759
2760
2761	/**
2762	* Called when the ring-0 init phases completed.
2763	*
2764	* @param pVM The cross context VM structure.
2765	*/
2766	VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
2767	{
2768	/*
2769	* Log the cpuid.
2770	*/
2771	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
2772	RTCPUSET OnlineSet;
2773	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
2774	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
2775	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
2776	RTCPUID cCores = RTMpGetCoreCount();
2777	if (cCores)
2778	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
2779	LogRel(("*********************** CPUID dump **********************\n"));
2780	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
2781	LogRel(("\n"));
2782	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
2783	RTLogRelSetBuffering(fOldBuffered);
2784	LogRel(("****************** End of CPUID dump ********************\n"));
2785	}
2786

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 69111

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