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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 68403

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1/* $Id: CPUM.cpp 68403 2017-08-14 09:40:36Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 *
33 * @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34 *
35 * TODO: proper write up, currently just some notes.
36 *
37 * The ring-0 FPU handling per OS:
38 *
39 * - 64-bit Windows uses XMM registers in the kernel as part of the calling
40 * convention (Visual C++ doesn't seem to have a way to disable
41 * generating such code either), so CR0.TS/EM are always zero from what I
42 * can tell. We are also forced to always load/save the guest XMM0-XMM15
43 * registers when entering/leaving guest context. Interrupt handlers
44 * using FPU/SSE will offically have call save and restore functions
45 * exported by the kernel, if the really really have to use the state.
46 *
47 * - 32-bit windows does lazy FPU handling, I think, probably including
48 * lazying saving. The Windows Internals book states that it's a bad
49 * idea to use the FPU in kernel space. However, it looks like it will
50 * restore the FPU state of the current thread in case of a kernel \#NM.
51 * Interrupt handlers should be same as for 64-bit.
52 *
53 * - Darwin allows taking \#NM in kernel space, restoring current thread's
54 * state if I read the code correctly. It saves the FPU state of the
55 * outgoing thread, and uses CR0.TS to lazily load the state of the
56 * incoming one. No idea yet how the FPU is treated by interrupt
57 * handlers, i.e. whether they are allowed to disable the state or
58 * something.
59 *
60 * - Linux also allows \#NM in kernel space (don't know since when), and
61 * uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62 * loads the incoming unless configured to agressivly load it. Interrupt
63 * handlers can ask whether they're allowed to use the FPU, and may
64 * freely trash the state if Linux thinks it has saved the thread's state
65 * already. This is a problem.
66 *
67 * - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68 * context. When switching threads, the kernel will save the state of
69 * the outgoing thread and lazy load the incoming one using CR0.TS.
70 * There are a few routines in seeblk.s which uses the SSE unit in ring-0
71 * to do stuff, HAT are among the users. The routines there will
72 * manually clear CR0.TS and save the XMM registers they use only if
73 * CR0.TS was zero upon entry. They will skip it when not, because as
74 * mentioned above, the FPU state is saved when switching away from a
75 * thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76 * preserve. This is a problem if we restore CR0.TS to 1 after loading
77 * the guest state.
78 *
79 * - FreeBSD - no idea yet.
80 *
81 * - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82 * possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83 * FPU states.
84 *
85 * Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86 * saving and restoring the host and guest states. The motivation for this
87 * change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88 *
89 * Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90 * state and only restore it once we've restore the host FPU state. This has the
91 * accidental side effect of triggering Solaris to preserve XMM registers in
92 * sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93 * the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94 *
95 *
96 * @section sec_cpum_logging Logging Level Assignments.
97 *
98 * Following log level assignments:
99 * - Log6 is used for FPU state management.
100 * - Log7 is used for FPU state actualization.
101 *
102 */
103
104
105/*********************************************************************************************************************************
106* Header Files *
107*********************************************************************************************************************************/
108#define LOG_GROUP LOG_GROUP_CPUM
109#include <VBox/vmm/cpum.h>
110#include <VBox/vmm/cpumdis.h>
111#include <VBox/vmm/cpumctx-v1_6.h>
112#include <VBox/vmm/pgm.h>
113#include <VBox/vmm/apic.h>
114#include <VBox/vmm/mm.h>
115#include <VBox/vmm/em.h>
116#include <VBox/vmm/iem.h>
117#include <VBox/vmm/selm.h>
118#include <VBox/vmm/dbgf.h>
119#include <VBox/vmm/patm.h>
120#include <VBox/vmm/hm.h>
121#include <VBox/vmm/ssm.h>
122#include "CPUMInternal.h"
123#include <VBox/vmm/vm.h>
124
125#include <VBox/param.h>
126#include <VBox/dis.h>
127#include <VBox/err.h>
128#include <VBox/log.h>
129#include <iprt/asm-amd64-x86.h>
130#include <iprt/assert.h>
131#include <iprt/cpuset.h>
132#include <iprt/mem.h>
133#include <iprt/mp.h>
134#include <iprt/string.h>
135
136
137/*********************************************************************************************************************************
138* Defined Constants And Macros *
139*********************************************************************************************************************************/
140/**
141 * This was used in the saved state up to the early life of version 14.
142 *
143 * It indicates that we may have some out-of-sync hidden segement registers.
144 * It is only relevant for raw-mode.
145 */
146#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
147
148
149/*********************************************************************************************************************************
150* Structures and Typedefs *
151*********************************************************************************************************************************/
152
153/**
154 * What kind of cpu info dump to perform.
155 */
156typedef enum CPUMDUMPTYPE
157{
158 CPUMDUMPTYPE_TERSE,
159 CPUMDUMPTYPE_DEFAULT,
160 CPUMDUMPTYPE_VERBOSE
161} CPUMDUMPTYPE;
162/** Pointer to a cpu info dump type. */
163typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
164
165
166/*********************************************************************************************************************************
167* Internal Functions *
168*********************************************************************************************************************************/
169static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
170static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
171static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
172static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
173static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
174static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
179static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
180
181
182/*********************************************************************************************************************************
183* Global Variables *
184*********************************************************************************************************************************/
185/** Saved state field descriptors for CPUMCTX. */
186static const SSMFIELD g_aCpumCtxFields[] =
187{
188 SSMFIELD_ENTRY( CPUMCTX, rdi),
189 SSMFIELD_ENTRY( CPUMCTX, rsi),
190 SSMFIELD_ENTRY( CPUMCTX, rbp),
191 SSMFIELD_ENTRY( CPUMCTX, rax),
192 SSMFIELD_ENTRY( CPUMCTX, rbx),
193 SSMFIELD_ENTRY( CPUMCTX, rdx),
194 SSMFIELD_ENTRY( CPUMCTX, rcx),
195 SSMFIELD_ENTRY( CPUMCTX, rsp),
196 SSMFIELD_ENTRY( CPUMCTX, rflags),
197 SSMFIELD_ENTRY( CPUMCTX, rip),
198 SSMFIELD_ENTRY( CPUMCTX, r8),
199 SSMFIELD_ENTRY( CPUMCTX, r9),
200 SSMFIELD_ENTRY( CPUMCTX, r10),
201 SSMFIELD_ENTRY( CPUMCTX, r11),
202 SSMFIELD_ENTRY( CPUMCTX, r12),
203 SSMFIELD_ENTRY( CPUMCTX, r13),
204 SSMFIELD_ENTRY( CPUMCTX, r14),
205 SSMFIELD_ENTRY( CPUMCTX, r15),
206 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
207 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
208 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
209 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
210 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
211 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
212 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
213 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
214 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
215 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
216 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
217 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
218 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
219 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
220 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
221 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
222 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
223 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
224 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
225 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
226 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
227 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
228 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
229 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
230 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
231 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
232 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
233 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
234 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
235 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
236 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
237 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
238 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
239 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
240 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
241 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
242 SSMFIELD_ENTRY( CPUMCTX, cr0),
243 SSMFIELD_ENTRY( CPUMCTX, cr2),
244 SSMFIELD_ENTRY( CPUMCTX, cr3),
245 SSMFIELD_ENTRY( CPUMCTX, cr4),
246 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
247 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
248 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
249 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
250 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
251 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
252 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
253 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
254 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
255 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
256 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
257 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
258 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
259 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
260 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
261 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
262 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
263 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
264 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
265 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
266 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
267 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
268 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
269 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
270 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
271 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
272 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
273 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
274 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
275 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
276 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
277 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
278 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
279 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
280 SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
281 SSMFIELD_ENTRY_TERM()
282};
283
284/** Saved state field descriptors for CPUMCTX. */
285static const SSMFIELD g_aCpumX87Fields[] =
286{
287 SSMFIELD_ENTRY( X86FXSTATE, FCW),
288 SSMFIELD_ENTRY( X86FXSTATE, FSW),
289 SSMFIELD_ENTRY( X86FXSTATE, FTW),
290 SSMFIELD_ENTRY( X86FXSTATE, FOP),
291 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
292 SSMFIELD_ENTRY( X86FXSTATE, CS),
293 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
294 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
295 SSMFIELD_ENTRY( X86FXSTATE, DS),
296 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
297 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
298 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
299 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
300 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
301 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
302 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
303 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
304 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
305 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
306 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
307 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
308 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
309 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
310 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
311 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
312 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
313 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
314 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
315 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
316 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
317 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
318 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
319 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
320 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
321 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
322 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
323 SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
324 SSMFIELD_ENTRY_TERM()
325};
326
327/** Saved state field descriptors for X86XSAVEHDR. */
328static const SSMFIELD g_aCpumXSaveHdrFields[] =
329{
330 SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
331 SSMFIELD_ENTRY_TERM()
332};
333
334/** Saved state field descriptors for X86XSAVEYMMHI. */
335static const SSMFIELD g_aCpumYmmHiFields[] =
336{
337 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
338 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
339 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
340 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
341 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
342 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
343 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
344 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
345 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
346 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
347 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
348 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
349 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
350 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
351 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
352 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
353 SSMFIELD_ENTRY_TERM()
354};
355
356/** Saved state field descriptors for X86XSAVEBNDREGS. */
357static const SSMFIELD g_aCpumBndRegsFields[] =
358{
359 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
360 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
361 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
362 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
363 SSMFIELD_ENTRY_TERM()
364};
365
366/** Saved state field descriptors for X86XSAVEBNDCFG. */
367static const SSMFIELD g_aCpumBndCfgFields[] =
368{
369 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
370 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
371 SSMFIELD_ENTRY_TERM()
372};
373
374#if 0 /** @todo */
375/** Saved state field descriptors for X86XSAVEOPMASK. */
376static const SSMFIELD g_aCpumOpmaskFields[] =
377{
378 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
379 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
380 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
381 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
382 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
383 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
384 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
385 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
386 SSMFIELD_ENTRY_TERM()
387};
388#endif
389
390/** Saved state field descriptors for X86XSAVEZMMHI256. */
391static const SSMFIELD g_aCpumZmmHi256Fields[] =
392{
393 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
394 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
395 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
396 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
397 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
398 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
399 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
400 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
401 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
402 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
403 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
404 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
405 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
406 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
407 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
408 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
409 SSMFIELD_ENTRY_TERM()
410};
411
412/** Saved state field descriptors for X86XSAVEZMM16HI. */
413static const SSMFIELD g_aCpumZmm16HiFields[] =
414{
415 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
416 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
417 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
418 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
419 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
420 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
421 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
422 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
423 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
424 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
425 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
426 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
427 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
428 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
429 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
430 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
431 SSMFIELD_ENTRY_TERM()
432};
433
434
435
436/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
437 * registeres changed. */
438static const SSMFIELD g_aCpumX87FieldsMem[] =
439{
440 SSMFIELD_ENTRY( X86FXSTATE, FCW),
441 SSMFIELD_ENTRY( X86FXSTATE, FSW),
442 SSMFIELD_ENTRY( X86FXSTATE, FTW),
443 SSMFIELD_ENTRY( X86FXSTATE, FOP),
444 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
445 SSMFIELD_ENTRY( X86FXSTATE, CS),
446 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
447 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
448 SSMFIELD_ENTRY( X86FXSTATE, DS),
449 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
450 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
451 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
452 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
453 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
454 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
455 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
456 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
457 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
458 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
459 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
460 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
461 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
462 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
463 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
464 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
465 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
466 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
467 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
468 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
469 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
470 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
471 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
472 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
473 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
474 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
475 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
476 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
477 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
478};
479
480/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
481 * registeres changed. */
482static const SSMFIELD g_aCpumCtxFieldsMem[] =
483{
484 SSMFIELD_ENTRY( CPUMCTX, rdi),
485 SSMFIELD_ENTRY( CPUMCTX, rsi),
486 SSMFIELD_ENTRY( CPUMCTX, rbp),
487 SSMFIELD_ENTRY( CPUMCTX, rax),
488 SSMFIELD_ENTRY( CPUMCTX, rbx),
489 SSMFIELD_ENTRY( CPUMCTX, rdx),
490 SSMFIELD_ENTRY( CPUMCTX, rcx),
491 SSMFIELD_ENTRY( CPUMCTX, rsp),
492 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
493 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
494 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
495 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
496 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
497 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
498 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
499 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
500 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
501 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
502 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
503 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
504 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
505 SSMFIELD_ENTRY( CPUMCTX, rflags),
506 SSMFIELD_ENTRY( CPUMCTX, rip),
507 SSMFIELD_ENTRY( CPUMCTX, r8),
508 SSMFIELD_ENTRY( CPUMCTX, r9),
509 SSMFIELD_ENTRY( CPUMCTX, r10),
510 SSMFIELD_ENTRY( CPUMCTX, r11),
511 SSMFIELD_ENTRY( CPUMCTX, r12),
512 SSMFIELD_ENTRY( CPUMCTX, r13),
513 SSMFIELD_ENTRY( CPUMCTX, r14),
514 SSMFIELD_ENTRY( CPUMCTX, r15),
515 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
516 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
517 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
518 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
519 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
520 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
521 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
522 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
523 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
524 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
525 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
526 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
527 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
528 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
529 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
530 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
531 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
532 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
533 SSMFIELD_ENTRY( CPUMCTX, cr0),
534 SSMFIELD_ENTRY( CPUMCTX, cr2),
535 SSMFIELD_ENTRY( CPUMCTX, cr3),
536 SSMFIELD_ENTRY( CPUMCTX, cr4),
537 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
538 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
539 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
540 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
541 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
542 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
543 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
544 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
545 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
546 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
547 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
548 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
549 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
550 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
551 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
552 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
553 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
554 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
555 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
556 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
557 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
558 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
559 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
560 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
561 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
562 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
563 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
564 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
565 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
566 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
567 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
568 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
569 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
570 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
571 SSMFIELD_ENTRY_TERM()
572};
573
574/** Saved state field descriptors for CPUMCTX_VER1_6. */
575static const SSMFIELD g_aCpumX87FieldsV16[] =
576{
577 SSMFIELD_ENTRY( X86FXSTATE, FCW),
578 SSMFIELD_ENTRY( X86FXSTATE, FSW),
579 SSMFIELD_ENTRY( X86FXSTATE, FTW),
580 SSMFIELD_ENTRY( X86FXSTATE, FOP),
581 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
582 SSMFIELD_ENTRY( X86FXSTATE, CS),
583 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
584 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
585 SSMFIELD_ENTRY( X86FXSTATE, DS),
586 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
587 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
588 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
589 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
590 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
591 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
592 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
593 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
594 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
595 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
596 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
597 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
598 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
599 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
600 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
601 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
602 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
603 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
604 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
605 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
606 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
607 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
608 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
609 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
610 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
611 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
612 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
613 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
614 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
615 SSMFIELD_ENTRY_TERM()
616};
617
618/** Saved state field descriptors for CPUMCTX_VER1_6. */
619static const SSMFIELD g_aCpumCtxFieldsV16[] =
620{
621 SSMFIELD_ENTRY( CPUMCTX, rdi),
622 SSMFIELD_ENTRY( CPUMCTX, rsi),
623 SSMFIELD_ENTRY( CPUMCTX, rbp),
624 SSMFIELD_ENTRY( CPUMCTX, rax),
625 SSMFIELD_ENTRY( CPUMCTX, rbx),
626 SSMFIELD_ENTRY( CPUMCTX, rdx),
627 SSMFIELD_ENTRY( CPUMCTX, rcx),
628 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
629 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
630 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
631 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
632 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
633 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
634 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
635 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
636 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
637 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
638 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
639 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
640 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
641 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
642 SSMFIELD_ENTRY( CPUMCTX, rflags),
643 SSMFIELD_ENTRY( CPUMCTX, rip),
644 SSMFIELD_ENTRY( CPUMCTX, r8),
645 SSMFIELD_ENTRY( CPUMCTX, r9),
646 SSMFIELD_ENTRY( CPUMCTX, r10),
647 SSMFIELD_ENTRY( CPUMCTX, r11),
648 SSMFIELD_ENTRY( CPUMCTX, r12),
649 SSMFIELD_ENTRY( CPUMCTX, r13),
650 SSMFIELD_ENTRY( CPUMCTX, r14),
651 SSMFIELD_ENTRY( CPUMCTX, r15),
652 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
653 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
654 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
655 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
656 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
657 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
658 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
659 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
660 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
661 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
662 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
663 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
664 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
665 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
666 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
667 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
668 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
669 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
670 SSMFIELD_ENTRY( CPUMCTX, cr0),
671 SSMFIELD_ENTRY( CPUMCTX, cr2),
672 SSMFIELD_ENTRY( CPUMCTX, cr3),
673 SSMFIELD_ENTRY( CPUMCTX, cr4),
674 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
675 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
676 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
677 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
678 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
679 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
680 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
681 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
682 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
683 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
684 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
685 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
686 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
687 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
688 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
689 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
690 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
691 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
692 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
693 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
694 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
695 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
696 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
697 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
698 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
699 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
700 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
701 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
702 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
703 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
704 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
705 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
706 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
707 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
708 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
709 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
710 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
711 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
712 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
713 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
714 SSMFIELD_ENTRY_TERM()
715};
716
717
718/**
719 * Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
720 *
721 * AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
722 * (last instruction pointer, last data pointer, last opcode) except when the ES
723 * bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
724 * clear these registers there is potential, local FPU leakage from a process
725 * using the FPU to another.
726 *
727 * See AMD Instruction Reference for FXSAVE, FXRSTOR.
728 *
729 * @param pVM The cross context VM structure.
730 */
731static void cpumR3CheckLeakyFpu(PVM pVM)
732{
733 uint32_t u32CpuVersion = ASMCpuId_EAX(1);
734 uint32_t const u32Family = u32CpuVersion >> 8;
735 if ( u32Family >= 6 /* K7 and higher */
736 && ASMIsAmdCpu())
737 {
738 uint32_t cExt = ASMCpuId_EAX(0x80000000);
739 if (ASMIsValidExtRange(cExt))
740 {
741 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
742 if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
743 {
744 for (VMCPUID i = 0; i < pVM->cCpus; i++)
745 pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_FFXSR_LEAKY;
746 Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
747 }
748 }
749 }
750}
751
752
753/**
754 * Frees memory allocated by cpumR3AllocHwVirtState().
755 *
756 * @param pVM The cross context VM structure.
757 */
758static void cpumR3FreeHwVirtState(PVM pVM)
759{
760 Assert(pVM->cpum.ro.GuestFeatures.fSvm);
761 for (VMCPUID i = 0; i < pVM->cCpus; i++)
762 {
763 PVMCPU pVCpu = &pVM->aCpus[i];
764 if (pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3)
765 {
766 SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES);
767 pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3 = NULL;
768 }
769 pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = NIL_RTHCPHYS;
770
771 if (pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3)
772 {
773 SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES);
774 pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3 = NULL;
775 }
776
777 if (pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3)
778 {
779 SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES);
780 pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3 = NULL;
781 }
782 }
783}
784
785
786/**
787 * Allocates memory required by the hardware virtualization state.
788 *
789 * @returns VBox status code.
790 * @param pVM The cross context VM structure.
791 */
792static int cpumR3AllocHwVirtState(PVM pVM)
793{
794 Assert(pVM->cpum.ro.GuestFeatures.fSvm);
795
796 int rc = VINF_SUCCESS;
797 LogRel(("CPUM: Allocating a total of %u pages for the nested-guest SVM MSR and IO permission bitmaps\n",
798 pVM->cCpus * (SVM_MSRPM_PAGES + SVM_IOPM_PAGES)));
799 for (VMCPUID i = 0; i < pVM->cCpus; i++)
800 {
801 PVMCPU pVCpu = &pVM->aCpus[i];
802
803 /*
804 * Allocate the nested-guest VMCB.
805 */
806 SUPPAGE SupNstGstVmcbPage;
807 RT_ZERO(SupNstGstVmcbPage);
808 SupNstGstVmcbPage.Phys = NIL_RTHCPHYS;
809 Assert(SVM_VMCB_PAGES == 1);
810 Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
811 rc = SUPR3PageAllocEx(SVM_VMCB_PAGES, 0 /* fFlags */, (void **)&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3,
812 &pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR0, &SupNstGstVmcbPage);
813 if (RT_FAILURE(rc))
814 {
815 Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
816 LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCB\n", pVCpu->idCpu, SVM_VMCB_PAGES));
817 break;
818 }
819 pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = SupNstGstVmcbPage.Phys;
820
821 /*
822 * Allocate the MSRPM (MSR Permission bitmap).
823 */
824 Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
825 rc = SUPR3PageAllocEx(SVM_MSRPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3,
826 &pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR0, NULL /* paPages */);
827 if (RT_FAILURE(rc))
828 {
829 Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
830 LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR permission bitmap\n", pVCpu->idCpu,
831 SVM_MSRPM_PAGES));
832 break;
833 }
834
835 /*
836 * Allocate the IOPM (IO Permission bitmap).
837 */
838 Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
839 rc = SUPR3PageAllocEx(SVM_IOPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3,
840 &pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR0, NULL /* paPages */);
841 if (RT_FAILURE(rc))
842 {
843 Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
844 LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's IO permission bitmap\n", pVCpu->idCpu,
845 SVM_IOPM_PAGES));
846 break;
847 }
848 }
849
850 /* On any failure, cleanup. */
851 if (RT_FAILURE(rc))
852 cpumR3FreeHwVirtState(pVM);
853
854 return rc;
855}
856
857
858/**
859 * Initializes the CPUM.
860 *
861 * @returns VBox status code.
862 * @param pVM The cross context VM structure.
863 */
864VMMR3DECL(int) CPUMR3Init(PVM pVM)
865{
866 LogFlow(("CPUMR3Init\n"));
867
868 /*
869 * Assert alignment, sizes and tables.
870 */
871 AssertCompileMemberAlignment(VM, cpum.s, 32);
872 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
873 AssertCompileSizeAlignment(CPUMCTX, 64);
874 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
875 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
876 AssertCompileMemberAlignment(VM, cpum, 64);
877 AssertCompileMemberAlignment(VM, aCpus, 64);
878 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
879 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
880#ifdef VBOX_STRICT
881 int rc2 = cpumR3MsrStrictInitChecks();
882 AssertRCReturn(rc2, rc2);
883#endif
884
885 /*
886 * Initialize offsets.
887 */
888
889 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
890 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
891 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
892
893
894 /* Calculate the offset from CPUMCPU to CPUM. */
895 for (VMCPUID i = 0; i < pVM->cCpus; i++)
896 {
897 PVMCPU pVCpu = &pVM->aCpus[i];
898
899 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
900 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
901 }
902
903 /*
904 * Gather info about the host CPU.
905 */
906 if (!ASMHasCpuId())
907 {
908 Log(("The CPU doesn't support CPUID!\n"));
909 return VERR_UNSUPPORTED_CPU;
910 }
911
912 pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
913
914 PCPUMCPUIDLEAF paLeaves;
915 uint32_t cLeaves;
916 int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
917 AssertLogRelRCReturn(rc, rc);
918
919 rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
920 RTMemFree(paLeaves);
921 AssertLogRelRCReturn(rc, rc);
922 pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
923
924 /*
925 * Check that the CPU supports the minimum features we require.
926 */
927 if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
928 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
929 if (!pVM->cpum.s.HostFeatures.fMmx)
930 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
931 if (!pVM->cpum.s.HostFeatures.fTsc)
932 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
933
934 /*
935 * Setup the CR4 AND and OR masks used in the raw-mode switcher.
936 */
937 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
938 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
939
940 /*
941 * Figure out which XSAVE/XRSTOR features are available on the host.
942 */
943 uint64_t fXcr0Host = 0;
944 uint64_t fXStateHostMask = 0;
945 if ( pVM->cpum.s.HostFeatures.fXSaveRstor
946 && pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
947 {
948 fXStateHostMask = fXcr0Host = ASMGetXcr0();
949 fXStateHostMask &= XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI;
950 AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 | XSAVE_C_SSE)) == (XSAVE_C_X87 | XSAVE_C_SSE),
951 ("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
952 }
953 pVM->cpum.s.fXStateHostMask = fXStateHostMask;
954 if (!HMIsEnabled(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
955 fXStateHostMask = 0;
956 LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
957 pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
958
959 /*
960 * Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
961 */
962 uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
963 cbMaxXState = RT_ALIGN(cbMaxXState, 128);
964 AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
965
966 uint8_t *pbXStates;
967 rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
968 MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
969 AssertLogRelRCReturn(rc, rc);
970
971 for (VMCPUID i = 0; i < pVM->cCpus; i++)
972 {
973 PVMCPU pVCpu = &pVM->aCpus[i];
974
975 pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
976 pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
977 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
978 pbXStates += cbMaxXState;
979
980 pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
981 pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
982 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
983 pbXStates += cbMaxXState;
984
985 pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
986 pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
987 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
988 pbXStates += cbMaxXState;
989
990 pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
991 }
992
993 /*
994 * Register saved state data item.
995 */
996 rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
997 NULL, cpumR3LiveExec, NULL,
998 NULL, cpumR3SaveExec, NULL,
999 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
1000 if (RT_FAILURE(rc))
1001 return rc;
1002
1003 /*
1004 * Register info handlers and registers with the debugger facility.
1005 */
1006 DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
1007 &cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
1008 DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
1009 &cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
1010 DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
1011 &cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
1012 DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
1013 &cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
1014 DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
1015 &cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
1016 DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
1017 &cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
1018 DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
1019
1020 rc = cpumR3DbgInit(pVM);
1021 if (RT_FAILURE(rc))
1022 return rc;
1023
1024 /*
1025 * Check if we need to workaround partial/leaky FPU handling.
1026 */
1027 cpumR3CheckLeakyFpu(pVM);
1028
1029 /*
1030 * Initialize the Guest CPUID and MSR states.
1031 */
1032 rc = cpumR3InitCpuIdAndMsrs(pVM);
1033 if (RT_FAILURE(rc))
1034 return rc;
1035
1036 /*
1037 * Allocate memory required by the guest hardware virtualization state.
1038 */
1039 if (pVM->cpum.ro.GuestFeatures.fSvm)
1040 {
1041 rc = cpumR3AllocHwVirtState(pVM);
1042 if (RT_FAILURE(rc))
1043 return rc;
1044 }
1045
1046 CPUMR3Reset(pVM);
1047 return VINF_SUCCESS;
1048}
1049
1050
1051/**
1052 * Applies relocations to data and code managed by this
1053 * component. This function will be called at init and
1054 * whenever the VMM need to relocate it self inside the GC.
1055 *
1056 * The CPUM will update the addresses used by the switcher.
1057 *
1058 * @param pVM The cross context VM structure.
1059 */
1060VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
1061{
1062 LogFlow(("CPUMR3Relocate\n"));
1063
1064 pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
1065 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
1066
1067 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1068 {
1069 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1070 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
1071 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
1072 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
1073
1074 /* Recheck the guest DRx values in raw-mode. */
1075 CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
1076 }
1077}
1078
1079
1080/**
1081 * Apply late CPUM property changes based on the fHWVirtEx setting
1082 *
1083 * @param pVM The cross context VM structure.
1084 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
1085 */
1086VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
1087{
1088 /*
1089 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
1090 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1091 * of processors from (cpuid(4).eax >> 26) + 1.
1092 *
1093 * Note: this code is obsolete, but let's keep it here for reference.
1094 * Purpose is valid when we artificially cap the max std id to less than 4.
1095 */
1096 if (!fHWVirtExEnabled)
1097 {
1098 Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
1099 || pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
1100 pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
1101 }
1102}
1103
1104/**
1105 * Terminates the CPUM.
1106 *
1107 * Termination means cleaning up and freeing all resources,
1108 * the VM it self is at this point powered off or suspended.
1109 *
1110 * @returns VBox status code.
1111 * @param pVM The cross context VM structure.
1112 */
1113VMMR3DECL(int) CPUMR3Term(PVM pVM)
1114{
1115#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1116 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1117 {
1118 PVMCPU pVCpu = &pVM->aCpus[i];
1119 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1120
1121 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1122 pVCpu->cpum.s.uMagic = 0;
1123 pCtx->dr[5] = 0;
1124 }
1125#endif
1126
1127 if (pVM->cpum.ro.GuestFeatures.fSvm)
1128 cpumR3FreeHwVirtState(pVM);
1129 return VINF_SUCCESS;
1130}
1131
1132
1133/**
1134 * Resets a virtual CPU.
1135 *
1136 * Used by CPUMR3Reset and CPU hot plugging.
1137 *
1138 * @param pVM The cross context VM structure.
1139 * @param pVCpu The cross context virtual CPU structure of the CPU that is
1140 * being reset. This may differ from the current EMT.
1141 */
1142VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
1143{
1144 /** @todo anything different for VCPU > 0? */
1145 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1146
1147 /*
1148 * Initialize everything to ZERO first.
1149 */
1150 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1151
1152 AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
1153 AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
1154 memset(pCtx, 0, RT_OFFSETOF(CPUMCTX, pXStateR0));
1155
1156 pVCpu->cpum.s.fUseFlags = fUseFlags;
1157
1158 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
1159 pCtx->eip = 0x0000fff0;
1160 pCtx->edx = 0x00000600; /* P6 processor */
1161 pCtx->eflags.Bits.u1Reserved0 = 1;
1162
1163 pCtx->cs.Sel = 0xf000;
1164 pCtx->cs.ValidSel = 0xf000;
1165 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1166 pCtx->cs.u64Base = UINT64_C(0xffff0000);
1167 pCtx->cs.u32Limit = 0x0000ffff;
1168 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1169 pCtx->cs.Attr.n.u1Present = 1;
1170 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1171
1172 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1173 pCtx->ds.u32Limit = 0x0000ffff;
1174 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1175 pCtx->ds.Attr.n.u1Present = 1;
1176 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1177
1178 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1179 pCtx->es.u32Limit = 0x0000ffff;
1180 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1181 pCtx->es.Attr.n.u1Present = 1;
1182 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1183
1184 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1185 pCtx->fs.u32Limit = 0x0000ffff;
1186 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1187 pCtx->fs.Attr.n.u1Present = 1;
1188 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1189
1190 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1191 pCtx->gs.u32Limit = 0x0000ffff;
1192 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1193 pCtx->gs.Attr.n.u1Present = 1;
1194 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1195
1196 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1197 pCtx->ss.u32Limit = 0x0000ffff;
1198 pCtx->ss.Attr.n.u1Present = 1;
1199 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1200 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1201
1202 pCtx->idtr.cbIdt = 0xffff;
1203 pCtx->gdtr.cbGdt = 0xffff;
1204
1205 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1206 pCtx->ldtr.u32Limit = 0xffff;
1207 pCtx->ldtr.Attr.n.u1Present = 1;
1208 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1209
1210 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1211 pCtx->tr.u32Limit = 0xffff;
1212 pCtx->tr.Attr.n.u1Present = 1;
1213 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1214
1215 pCtx->dr[6] = X86_DR6_INIT_VAL;
1216 pCtx->dr[7] = X86_DR7_INIT_VAL;
1217
1218 PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
1219 pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
1220 pFpuCtx->FCW = 0x37f;
1221
1222 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1223 IA-32 Processor States Following Power-up, Reset, or INIT */
1224 pFpuCtx->MXCSR = 0x1F80;
1225 pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
1226
1227 pCtx->aXcr[0] = XSAVE_C_X87;
1228 if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_OFFSETOF(X86XSAVEAREA, Hdr))
1229 {
1230 /* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
1231 as we don't know what happened before. (Bother optimize later?) */
1232 pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 | XSAVE_C_SSE;
1233 }
1234
1235 /*
1236 * MSRs.
1237 */
1238 /* Init PAT MSR */
1239 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1240
1241 /* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1242 * The Intel docs don't mention it. */
1243 Assert(!pCtx->msrEFER);
1244
1245 /* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
1246 is supposed to be here, just trying provide useful/sensible values. */
1247 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
1248 if (pRange)
1249 {
1250 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1251 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1252 | (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
1253 | MSR_IA32_MISC_ENABLE_FAST_STRINGS;
1254 pRange->fWrIgnMask |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1255 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
1256 pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1257 }
1258
1259 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1260
1261 /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1262 * called from each EMT while we're getting called by CPUMR3Reset()
1263 * iteratively on the same thread. Fix later. */
1264#if 0 /** @todo r=bird: This we will do in TM, not here. */
1265 /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1266 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1267#endif
1268
1269
1270 /* C-state control. Guesses. */
1271 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
1272
1273 /*
1274 * Hardware virtualization state.
1275 */
1276 /* SVM. */
1277 if (pCtx->hwvirt.svm.CTX_SUFF(pVmcb))
1278 memset(pCtx->hwvirt.svm.CTX_SUFF(pVmcb), 0, SVM_VMCB_PAGES << PAGE_SHIFT);
1279 pCtx->hwvirt.svm.uMsrHSavePa = 0;
1280 pCtx->hwvirt.svm.GCPhysVmcb = 0;
1281 pCtx->hwvirt.svm.fGif = 1;
1282}
1283
1284
1285/**
1286 * Resets the CPU.
1287 *
1288 * @returns VINF_SUCCESS.
1289 * @param pVM The cross context VM structure.
1290 */
1291VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1292{
1293 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1294 {
1295 CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
1296
1297#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1298 PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1299
1300 /* Magic marker for searching in crash dumps. */
1301 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1302 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1303 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1304#endif
1305 }
1306}
1307
1308
1309
1310
1311/**
1312 * Pass 0 live exec callback.
1313 *
1314 * @returns VINF_SSM_DONT_CALL_AGAIN.
1315 * @param pVM The cross context VM structure.
1316 * @param pSSM The saved state handle.
1317 * @param uPass The pass (0).
1318 */
1319static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1320{
1321 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
1322 cpumR3SaveCpuId(pVM, pSSM);
1323 return VINF_SSM_DONT_CALL_AGAIN;
1324}
1325
1326
1327/**
1328 * Execute state save operation.
1329 *
1330 * @returns VBox status code.
1331 * @param pVM The cross context VM structure.
1332 * @param pSSM SSM operation handle.
1333 */
1334static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1335{
1336 /*
1337 * Save.
1338 */
1339 SSMR3PutU32(pSSM, pVM->cCpus);
1340 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
1341 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1342 {
1343 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1344
1345 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1346
1347 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1348 SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1349 SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1350 if (pGstCtx->fXStateMask != 0)
1351 SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
1352 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1353 {
1354 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1355 SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1356 }
1357 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1358 {
1359 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1360 SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1361 }
1362 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1363 {
1364 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1365 SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1366 }
1367 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1368 {
1369 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1370 SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1371 }
1372 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1373 {
1374 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1375 SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1376 }
1377
1378 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1379 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1380 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
1381 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
1382 }
1383
1384 cpumR3SaveCpuId(pVM, pSSM);
1385 return VINF_SUCCESS;
1386}
1387
1388
1389/**
1390 * @callback_method_impl{FNSSMINTLOADPREP}
1391 */
1392static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1393{
1394 NOREF(pSSM);
1395 pVM->cpum.s.fPendingRestore = true;
1396 return VINF_SUCCESS;
1397}
1398
1399
1400/**
1401 * @callback_method_impl{FNSSMINTLOADEXEC}
1402 */
1403static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1404{
1405 int rc; /* Only for AssertRCReturn use. */
1406
1407 /*
1408 * Validate version.
1409 */
1410 if ( uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
1411 && uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
1412 && uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
1413 && uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
1414 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
1415 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
1416 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
1417 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1418 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1419 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1420 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1421 {
1422 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1423 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1424 }
1425
1426 if (uPass == SSM_PASS_FINAL)
1427 {
1428 /*
1429 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1430 * really old SSM file versions.)
1431 */
1432 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1433 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1434 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1435 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1436
1437 /*
1438 * Figure x86 and ctx field definitions to use for older states.
1439 */
1440 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
1441 PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
1442 PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
1443 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1444 {
1445 paCpumCtx1Fields = g_aCpumX87FieldsV16;
1446 paCpumCtx2Fields = g_aCpumCtxFieldsV16;
1447 }
1448 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1449 {
1450 paCpumCtx1Fields = g_aCpumX87FieldsMem;
1451 paCpumCtx2Fields = g_aCpumCtxFieldsMem;
1452 }
1453
1454 /*
1455 * The hyper state used to preceed the CPU count. Starting with
1456 * XSAVE it was moved down till after we've got the count.
1457 */
1458 if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
1459 {
1460 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1461 {
1462 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1463 X86FXSTATE Ign;
1464 SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1465 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1466 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1467 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
1468 fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1469 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1470 pVCpu->cpum.s.Hyper.rsp = uRSP;
1471 }
1472 }
1473
1474 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1475 {
1476 uint32_t cCpus;
1477 rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1478 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1479 VERR_SSM_UNEXPECTED_DATA);
1480 }
1481 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
1482 || pVM->cCpus == 1,
1483 ("cCpus=%u\n", pVM->cCpus),
1484 VERR_SSM_UNEXPECTED_DATA);
1485
1486 uint32_t cbMsrs = 0;
1487 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1488 {
1489 rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
1490 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
1491 VERR_SSM_UNEXPECTED_DATA);
1492 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
1493 VERR_SSM_UNEXPECTED_DATA);
1494 }
1495
1496 /*
1497 * Do the per-CPU restoring.
1498 */
1499 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1500 {
1501 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1502 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1503
1504 if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
1505 {
1506 /*
1507 * The XSAVE saved state layout moved the hyper state down here.
1508 */
1509 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1510 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1511 rc = SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1512 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1513 pVCpu->cpum.s.Hyper.rsp = uRSP;
1514 AssertRCReturn(rc, rc);
1515
1516 /*
1517 * Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
1518 */
1519 rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1520 rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1521 AssertRCReturn(rc, rc);
1522
1523 /* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
1524 if (pGstCtx->fXStateMask != 0)
1525 {
1526 AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
1527 ("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
1528 pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
1529 VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
1530 AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
1531 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1532 AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
1533 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1534 AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1535 || (pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1536 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
1537 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1538 }
1539
1540 /* Check that the XCR0 mask is valid (invalid results in #GP). */
1541 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
1542 if (pGstCtx->aXcr[0] != XSAVE_C_X87)
1543 {
1544 AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask | XSAVE_C_X87)),
1545 ("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
1546 VERR_CPUM_INVALID_XCR0);
1547 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
1548 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1549 AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
1550 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1551 AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1552 || (pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1553 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
1554 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1555 }
1556
1557 /* Check that the XCR1 is zero, as we don't implement it yet. */
1558 AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
1559
1560 /*
1561 * Restore the individual extended state components we support.
1562 */
1563 if (pGstCtx->fXStateMask != 0)
1564 {
1565 rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
1566 0, g_aCpumXSaveHdrFields, NULL);
1567 AssertRCReturn(rc, rc);
1568 AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
1569 ("bmXState=%#RX64 fXStateMask=%#RX64\n",
1570 pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
1571 VERR_CPUM_INVALID_XSAVE_HDR);
1572 }
1573 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1574 {
1575 PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
1576 SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1577 }
1578 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1579 {
1580 PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
1581 SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1582 }
1583 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1584 {
1585 PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
1586 SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1587 }
1588 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1589 {
1590 PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
1591 SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1592 }
1593 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1594 {
1595 PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
1596 SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1597 }
1598 }
1599 else
1600 {
1601 /*
1602 * Pre XSAVE saved state.
1603 */
1604 SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
1605 fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1606 SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1607 }
1608
1609 /*
1610 * Restore a couple of flags and the MSRs.
1611 */
1612 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
1613 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
1614
1615 rc = VINF_SUCCESS;
1616 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1617 rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
1618 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1619 {
1620 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
1621 rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
1622 }
1623 AssertRCReturn(rc, rc);
1624
1625 /* REM and other may have cleared must-be-one fields in DR6 and
1626 DR7, fix these. */
1627 pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
1628 pGstCtx->dr[6] |= X86_DR6_RA1_MASK;
1629 pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
1630 pGstCtx->dr[7] |= X86_DR7_RA1_MASK;
1631 }
1632
1633 /* Older states does not have the internal selector register flags
1634 and valid selector value. Supply those. */
1635 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1636 {
1637 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1638 {
1639 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1640 bool const fValid = HMIsEnabled(pVM)
1641 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1642 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
1643 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
1644 if (fValid)
1645 {
1646 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1647 {
1648 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
1649 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
1650 }
1651
1652 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1653 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1654 }
1655 else
1656 {
1657 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1658 {
1659 paSelReg[iSelReg].fFlags = 0;
1660 paSelReg[iSelReg].ValidSel = 0;
1661 }
1662
1663 /* This might not be 104% correct, but I think it's close
1664 enough for all practical purposes... (REM always loaded
1665 LDTR registers.) */
1666 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1667 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1668 }
1669 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1670 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
1671 }
1672 }
1673
1674 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
1675 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1676 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1677 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1678 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
1679
1680 /*
1681 * A quick sanity check.
1682 */
1683 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1684 {
1685 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1686 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1687 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1688 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1689 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1690 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1691 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1692 }
1693 }
1694
1695 pVM->cpum.s.fPendingRestore = false;
1696
1697 /*
1698 * Guest CPUIDs.
1699 */
1700 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
1701 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1702 return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
1703}
1704
1705
1706/**
1707 * @callback_method_impl{FNSSMINTLOADDONE}
1708 */
1709static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
1710{
1711 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
1712 return VINF_SUCCESS;
1713
1714 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
1715 if (pVM->cpum.s.fPendingRestore)
1716 {
1717 LogRel(("CPUM: Missing state!\n"));
1718 return VERR_INTERNAL_ERROR_2;
1719 }
1720
1721 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
1722 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1723 {
1724 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1725
1726 /* Notify PGM of the NXE states in case they've changed. */
1727 PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
1728
1729 /* During init. this is done in CPUMR3InitCompleted(). */
1730 if (fSupportsLongMode)
1731 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
1732 }
1733 return VINF_SUCCESS;
1734}
1735
1736
1737/**
1738 * Checks if the CPUM state restore is still pending.
1739 *
1740 * @returns true / false.
1741 * @param pVM The cross context VM structure.
1742 */
1743VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
1744{
1745 return pVM->cpum.s.fPendingRestore;
1746}
1747
1748
1749/**
1750 * Formats the EFLAGS value into mnemonics.
1751 *
1752 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1753 * @param efl The EFLAGS value.
1754 */
1755static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1756{
1757 /*
1758 * Format the flags.
1759 */
1760 static const struct
1761 {
1762 const char *pszSet; const char *pszClear; uint32_t fFlag;
1763 } s_aFlags[] =
1764 {
1765 { "vip",NULL, X86_EFL_VIP },
1766 { "vif",NULL, X86_EFL_VIF },
1767 { "ac", NULL, X86_EFL_AC },
1768 { "vm", NULL, X86_EFL_VM },
1769 { "rf", NULL, X86_EFL_RF },
1770 { "nt", NULL, X86_EFL_NT },
1771 { "ov", "nv", X86_EFL_OF },
1772 { "dn", "up", X86_EFL_DF },
1773 { "ei", "di", X86_EFL_IF },
1774 { "tf", NULL, X86_EFL_TF },
1775 { "nt", "pl", X86_EFL_SF },
1776 { "nz", "zr", X86_EFL_ZF },
1777 { "ac", "na", X86_EFL_AF },
1778 { "po", "pe", X86_EFL_PF },
1779 { "cy", "nc", X86_EFL_CF },
1780 };
1781 char *psz = pszEFlags;
1782 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1783 {
1784 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1785 if (pszAdd)
1786 {
1787 strcpy(psz, pszAdd);
1788 psz += strlen(pszAdd);
1789 *psz++ = ' ';
1790 }
1791 }
1792 psz[-1] = '\0';
1793}
1794
1795
1796/**
1797 * Formats a full register dump.
1798 *
1799 * @param pVM The cross context VM structure.
1800 * @param pCtx The context to format.
1801 * @param pCtxCore The context core to format.
1802 * @param pHlp Output functions.
1803 * @param enmType The dump type.
1804 * @param pszPrefix Register name prefix.
1805 */
1806static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
1807 const char *pszPrefix)
1808{
1809 NOREF(pVM);
1810
1811 /*
1812 * Format the EFLAGS.
1813 */
1814 uint32_t efl = pCtxCore->eflags.u32;
1815 char szEFlags[80];
1816 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1817
1818 /*
1819 * Format the registers.
1820 */
1821 switch (enmType)
1822 {
1823 case CPUMDUMPTYPE_TERSE:
1824 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1825 pHlp->pfnPrintf(pHlp,
1826 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1827 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1828 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1829 "%sr14=%016RX64 %sr15=%016RX64\n"
1830 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1831 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1832 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1833 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1834 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1835 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1836 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1837 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1838 else
1839 pHlp->pfnPrintf(pHlp,
1840 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1841 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1842 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1843 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1844 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1845 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1846 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1847 break;
1848
1849 case CPUMDUMPTYPE_DEFAULT:
1850 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1851 pHlp->pfnPrintf(pHlp,
1852 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1853 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1854 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1855 "%sr14=%016RX64 %sr15=%016RX64\n"
1856 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1857 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1858 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1859 ,
1860 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1861 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1862 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1863 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1864 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1865 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1866 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1867 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1868 else
1869 pHlp->pfnPrintf(pHlp,
1870 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1871 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1872 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1873 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1874 ,
1875 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1876 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1877 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1878 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1879 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1880 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1881 break;
1882
1883 case CPUMDUMPTYPE_VERBOSE:
1884 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1885 pHlp->pfnPrintf(pHlp,
1886 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1887 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1888 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1889 "%sr14=%016RX64 %sr15=%016RX64\n"
1890 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1891 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1892 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1893 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1894 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1895 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1896 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1897 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1898 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1899 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1900 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1901 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1902 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1903 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1904 ,
1905 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1906 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1907 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1908 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1909 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1910 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1911 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1912 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1913 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1914 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1915 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1916 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1917 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1918 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1919 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1920 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1921 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1922 else
1923 pHlp->pfnPrintf(pHlp,
1924 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1925 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1926 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1927 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1928 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1929 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1930 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1931 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1932 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1933 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1934 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1935 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1936 ,
1937 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1938 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1939 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1940 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1941 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1942 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1943 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1944 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1945 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1946 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1947 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1948 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1949
1950 pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
1951 pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
1952 pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
1953 if (pCtx->CTX_SUFF(pXState))
1954 {
1955 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1956 pHlp->pfnPrintf(pHlp,
1957 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1958 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
1959 ,
1960 pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
1961 pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
1962 pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
1963 pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
1964 );
1965 /*
1966 * The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
1967 * not (FP)R0-7 as Intel SDM suggests.
1968 */
1969 unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
1970 for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
1971 {
1972 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
1973 unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
1974 char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
1975 unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
1976 uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
1977 int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
1978 iExponent -= 16383; /* subtract bias */
1979 /** @todo This isn't entirenly correct and needs more work! */
1980 pHlp->pfnPrintf(pHlp,
1981 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
1982 pszPrefix, iST, pszPrefix, iFPR,
1983 pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
1984 uTag, chSign, iInteger, u64Fraction, iExponent);
1985 if (pFpuCtx->aRegs[iST].au16[5] || pFpuCtx->aRegs[iST].au16[6] || pFpuCtx->aRegs[iST].au16[7])
1986 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
1987 pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
1988 else
1989 pHlp->pfnPrintf(pHlp, "\n");
1990 }
1991
1992 /* XMM/YMM/ZMM registers. */
1993 if (pCtx->fXStateMask & XSAVE_C_YMM)
1994 {
1995 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1996 if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
1997 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1998 pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1999 pszPrefix, i, i < 10 ? " " : "",
2000 pYmmHiCtx->aYmmHi[i].au32[3],
2001 pYmmHiCtx->aYmmHi[i].au32[2],
2002 pYmmHiCtx->aYmmHi[i].au32[1],
2003 pYmmHiCtx->aYmmHi[i].au32[0],
2004 pFpuCtx->aXMM[i].au32[3],
2005 pFpuCtx->aXMM[i].au32[2],
2006 pFpuCtx->aXMM[i].au32[1],
2007 pFpuCtx->aXMM[i].au32[0]);
2008 else
2009 {
2010 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2011 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2012 pHlp->pfnPrintf(pHlp,
2013 "%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2014 pszPrefix, i, i < 10 ? " " : "",
2015 pZmmHi256->aHi256Regs[i].au32[7],
2016 pZmmHi256->aHi256Regs[i].au32[6],
2017 pZmmHi256->aHi256Regs[i].au32[5],
2018 pZmmHi256->aHi256Regs[i].au32[4],
2019 pZmmHi256->aHi256Regs[i].au32[3],
2020 pZmmHi256->aHi256Regs[i].au32[2],
2021 pZmmHi256->aHi256Regs[i].au32[1],
2022 pZmmHi256->aHi256Regs[i].au32[0],
2023 pYmmHiCtx->aYmmHi[i].au32[3],
2024 pYmmHiCtx->aYmmHi[i].au32[2],
2025 pYmmHiCtx->aYmmHi[i].au32[1],
2026 pYmmHiCtx->aYmmHi[i].au32[0],
2027 pFpuCtx->aXMM[i].au32[3],
2028 pFpuCtx->aXMM[i].au32[2],
2029 pFpuCtx->aXMM[i].au32[1],
2030 pFpuCtx->aXMM[i].au32[0]);
2031
2032 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2033 for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
2034 pHlp->pfnPrintf(pHlp,
2035 "%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2036 pszPrefix, i + 16,
2037 pZmm16Hi->aRegs[i].au32[15],
2038 pZmm16Hi->aRegs[i].au32[14],
2039 pZmm16Hi->aRegs[i].au32[13],
2040 pZmm16Hi->aRegs[i].au32[12],
2041 pZmm16Hi->aRegs[i].au32[11],
2042 pZmm16Hi->aRegs[i].au32[10],
2043 pZmm16Hi->aRegs[i].au32[9],
2044 pZmm16Hi->aRegs[i].au32[8],
2045 pZmm16Hi->aRegs[i].au32[7],
2046 pZmm16Hi->aRegs[i].au32[6],
2047 pZmm16Hi->aRegs[i].au32[5],
2048 pZmm16Hi->aRegs[i].au32[4],
2049 pZmm16Hi->aRegs[i].au32[3],
2050 pZmm16Hi->aRegs[i].au32[2],
2051 pZmm16Hi->aRegs[i].au32[1],
2052 pZmm16Hi->aRegs[i].au32[0]);
2053 }
2054 }
2055 else
2056 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2057 pHlp->pfnPrintf(pHlp,
2058 i & 1
2059 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2060 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2061 pszPrefix, i, i < 10 ? " " : "",
2062 pFpuCtx->aXMM[i].au32[3],
2063 pFpuCtx->aXMM[i].au32[2],
2064 pFpuCtx->aXMM[i].au32[1],
2065 pFpuCtx->aXMM[i].au32[0]);
2066
2067 if (pCtx->fXStateMask & XSAVE_C_OPMASK)
2068 {
2069 PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
2070 for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
2071 pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
2072 pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
2073 pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
2074 pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
2075 pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
2076 }
2077
2078 if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
2079 {
2080 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2081 for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
2082 pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
2083 pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
2084 pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
2085 }
2086
2087 if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
2088 {
2089 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2090 pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
2091 pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
2092 }
2093
2094 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
2095 if (pFpuCtx->au32RsrvdRest[i])
2096 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
2097 pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2098 }
2099
2100 pHlp->pfnPrintf(pHlp,
2101 "%sEFER =%016RX64\n"
2102 "%sPAT =%016RX64\n"
2103 "%sSTAR =%016RX64\n"
2104 "%sCSTAR =%016RX64\n"
2105 "%sLSTAR =%016RX64\n"
2106 "%sSFMASK =%016RX64\n"
2107 "%sKERNELGSBASE =%016RX64\n",
2108 pszPrefix, pCtx->msrEFER,
2109 pszPrefix, pCtx->msrPAT,
2110 pszPrefix, pCtx->msrSTAR,
2111 pszPrefix, pCtx->msrCSTAR,
2112 pszPrefix, pCtx->msrLSTAR,
2113 pszPrefix, pCtx->msrSFMASK,
2114 pszPrefix, pCtx->msrKERNELGSBASE);
2115 break;
2116 }
2117}
2118
2119
2120/**
2121 * Display all cpu states and any other cpum info.
2122 *
2123 * @param pVM The cross context VM structure.
2124 * @param pHlp The info helper functions.
2125 * @param pszArgs Arguments, ignored.
2126 */
2127static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2128{
2129 cpumR3InfoGuest(pVM, pHlp, pszArgs);
2130 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2131 cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
2132 cpumR3InfoHyper(pVM, pHlp, pszArgs);
2133 cpumR3InfoHost(pVM, pHlp, pszArgs);
2134}
2135
2136
2137/**
2138 * Parses the info argument.
2139 *
2140 * The argument starts with 'verbose', 'terse' or 'default' and then
2141 * continues with the comment string.
2142 *
2143 * @param pszArgs The pointer to the argument string.
2144 * @param penmType Where to store the dump type request.
2145 * @param ppszComment Where to store the pointer to the comment string.
2146 */
2147static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
2148{
2149 if (!pszArgs)
2150 {
2151 *penmType = CPUMDUMPTYPE_DEFAULT;
2152 *ppszComment = "";
2153 }
2154 else
2155 {
2156 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
2157 {
2158 pszArgs += 7;
2159 *penmType = CPUMDUMPTYPE_VERBOSE;
2160 }
2161 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
2162 {
2163 pszArgs += 5;
2164 *penmType = CPUMDUMPTYPE_TERSE;
2165 }
2166 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
2167 {
2168 pszArgs += 7;
2169 *penmType = CPUMDUMPTYPE_DEFAULT;
2170 }
2171 else
2172 *penmType = CPUMDUMPTYPE_DEFAULT;
2173 *ppszComment = RTStrStripL(pszArgs);
2174 }
2175}
2176
2177
2178/**
2179 * Display the guest cpu state.
2180 *
2181 * @param pVM The cross context VM structure.
2182 * @param pHlp The info helper functions.
2183 * @param pszArgs Arguments.
2184 */
2185static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2186{
2187 CPUMDUMPTYPE enmType;
2188 const char *pszComment;
2189 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2190
2191 PVMCPU pVCpu = VMMGetCpu(pVM);
2192 if (!pVCpu)
2193 pVCpu = &pVM->aCpus[0];
2194
2195 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2196
2197 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2198 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2199}
2200
2201
2202/**
2203 * Display the guest's hardware-virtualization cpu state.
2204 *
2205 * @param pVM The cross context VM structure.
2206 * @param pHlp The info helper functions.
2207 * @param pszArgs Arguments, ignored.
2208 */
2209static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2210{
2211 RT_NOREF(pszArgs);
2212
2213 PVMCPU pVCpu = VMMGetCpu(pVM);
2214 if (!pVCpu)
2215 pVCpu = &pVM->aCpus[0];
2216
2217 /*
2218 * Figure out what to dump.
2219 *
2220 * In the future we may need to dump everything whether or not we're actively in nested-guest mode
2221 * or not, hence the reason why we use a mask to determine what needs dumping. Currently, we only
2222 * dump hwvirt. state when the guest CPU is executing a nested-guest.
2223 */
2224 /** @todo perhaps make this configurable through pszArgs, depending on how much
2225 * noise we wish to accept when nested hwvirt. isn't used. */
2226#define CPUMHWVIRTDUMP_NONE (0)
2227#define CPUMHWVIRTDUMP_SVM RT_BIT(0)
2228#define CPUMHWVIRTDUMP_VMX RT_BIT(1)
2229#define CPUMHWVIRTDUMP_COMMON RT_BIT(2)
2230#define CPUMHWVIRTDUMP_LAST CPUMHWVIRTDUMP_VMX
2231#define CPUMHWVIRTDUMP_ALL (CPUMHWVIRTDUMP_COMMON | CPUMHWVIRTDUMP_VMX | CPUMHWVIRTDUMP_SVM)
2232
2233 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2234 static const char *const s_aHwvirtModes[] = { "No/inactive", "SVM", "VMX", "Common" };
2235 uint8_t const idxHwvirtState = CPUMIsGuestInSvmNestedHwVirtMode(pCtx) ? CPUMHWVIRTDUMP_SVM
2236 : CPUMIsGuestInVmxNestedHwVirtMode(pCtx) ? CPUMHWVIRTDUMP_VMX : CPUMHWVIRTDUMP_NONE;
2237 AssertCompile(CPUMHWVIRTDUMP_LAST <= RT_ELEMENTS(s_aHwvirtModes));
2238 Assert(idxHwvirtState < RT_ELEMENTS(s_aHwvirtModes));
2239 const char *pcszHwvirtMode = s_aHwvirtModes[idxHwvirtState];
2240 uint32_t const fDumpState = idxHwvirtState; /* | CPUMHWVIRTDUMP_ALL */
2241
2242 /*
2243 * Dump it.
2244 */
2245 pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
2246
2247 if (fDumpState & CPUMHWVIRTDUMP_COMMON)
2248 pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
2249 pHlp->pfnPrintf(pHlp, "%s hwvirt state%s\n", pcszHwvirtMode, fDumpState ? ":" : "");
2250 if (fDumpState & CPUMHWVIRTDUMP_SVM)
2251 {
2252 pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
2253 pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
2254 pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
2255 HMR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.pVmcbR3->ctrl, " " /* pszPrefix */);
2256 /** @todo HMR3InfoSvmVmcbStateSave. */
2257 pHlp->pfnPrintf(pHlp, " HostState:\n");
2258 pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
2259 pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
2260 pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
2261 pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
2262 pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
2263 pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
2264 pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
2265 pHlp->pfnPrintf(pHlp, " rflags = %#RX64\n", pCtx->hwvirt.svm.HostState.rflags.u64);
2266 PCPUMSELREG pSel = &pCtx->hwvirt.svm.HostState.es;
2267 pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2268 pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->fFlags);
2269 pSel = &pCtx->hwvirt.svm.HostState.cs;
2270 pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2271 pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->fFlags);
2272 pSel = &pCtx->hwvirt.svm.HostState.ss;
2273 pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2274 pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->fFlags);
2275 pSel = &pCtx->hwvirt.svm.HostState.ds;
2276 pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2277 pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->fFlags);
2278 pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
2279 pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
2280 pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
2281 pCtx->hwvirt.svm.HostState.idtr.cbIdt);
2282 pHlp->pfnPrintf(pHlp, " fGif = %u\n", pCtx->hwvirt.svm.fGif);
2283 pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
2284 pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
2285 pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
2286 pHlp->pfnPrintf(pHlp, " pvMsrBitmapR3 = %p\n", pCtx->hwvirt.svm.pvMsrBitmapR3);
2287 pHlp->pfnPrintf(pHlp, " pvMsrBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvMsrBitmapR0);
2288 pHlp->pfnPrintf(pHlp, " pvIoBitmapR3 = %p\n", pCtx->hwvirt.svm.pvIoBitmapR3);
2289 pHlp->pfnPrintf(pHlp, " pvIoBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvIoBitmapR0);
2290 }
2291
2292 /** @todo Intel. */
2293#if 0
2294 if (fDumpState & CPUMHWVIRTDUMP_VMX)
2295 {
2296 }
2297#endif
2298
2299#undef CPUMHWVIRTDUMP_NONE
2300#undef CPUMHWVIRTDUMP_COMMON
2301#undef CPUMHWVIRTDUMP_SVM
2302#undef CPUMHWVIRTDUMP_VMX
2303#undef CPUMHWVIRTDUMP_LAST
2304#undef CPUMHWVIRTDUMP_ALL
2305}
2306
2307/**
2308 * Display the current guest instruction
2309 *
2310 * @param pVM The cross context VM structure.
2311 * @param pHlp The info helper functions.
2312 * @param pszArgs Arguments, ignored.
2313 */
2314static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2315{
2316 NOREF(pszArgs);
2317
2318 PVMCPU pVCpu = VMMGetCpu(pVM);
2319 if (!pVCpu)
2320 pVCpu = &pVM->aCpus[0];
2321
2322 char szInstruction[256];
2323 szInstruction[0] = '\0';
2324 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2325 pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
2326}
2327
2328
2329/**
2330 * Display the hypervisor cpu state.
2331 *
2332 * @param pVM The cross context VM structure.
2333 * @param pHlp The info helper functions.
2334 * @param pszArgs Arguments, ignored.
2335 */
2336static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2337{
2338 PVMCPU pVCpu = VMMGetCpu(pVM);
2339 if (!pVCpu)
2340 pVCpu = &pVM->aCpus[0];
2341
2342 CPUMDUMPTYPE enmType;
2343 const char *pszComment;
2344 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2345 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2346 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
2347 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2348}
2349
2350
2351/**
2352 * Display the host cpu state.
2353 *
2354 * @param pVM The cross context VM structure.
2355 * @param pHlp The info helper functions.
2356 * @param pszArgs Arguments, ignored.
2357 */
2358static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2359{
2360 CPUMDUMPTYPE enmType;
2361 const char *pszComment;
2362 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2363 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2364
2365 PVMCPU pVCpu = VMMGetCpu(pVM);
2366 if (!pVCpu)
2367 pVCpu = &pVM->aCpus[0];
2368 PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
2369
2370 /*
2371 * Format the EFLAGS.
2372 */
2373#if HC_ARCH_BITS == 32
2374 uint32_t efl = pCtx->eflags.u32;
2375#else
2376 uint64_t efl = pCtx->rflags;
2377#endif
2378 char szEFlags[80];
2379 cpumR3InfoFormatFlags(&szEFlags[0], efl);
2380
2381 /*
2382 * Format the registers.
2383 */
2384#if HC_ARCH_BITS == 32
2385 pHlp->pfnPrintf(pHlp,
2386 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2387 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2388 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2389 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2390 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2391 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2392 ,
2393 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
2394 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2395 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2396 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
2397 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2398 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
2399 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2400#else
2401 pHlp->pfnPrintf(pHlp,
2402 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2403 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2404 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2405 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2406 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2407 "r14=%016RX64 r15=%016RX64\n"
2408 "iopl=%d %31s\n"
2409 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2410 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2411 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
2412 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2413 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2414 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2415 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2416 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2417 ,
2418 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
2419 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2420 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
2421 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
2422 pCtx->r11, pCtx->r12, pCtx->r13,
2423 pCtx->r14, pCtx->r15,
2424 X86_EFL_GET_IOPL(efl), szEFlags,
2425 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2426 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
2427 pCtx->cr4, pCtx->ldtr, pCtx->tr,
2428 pCtx->dr0, pCtx->dr1, pCtx->dr2,
2429 pCtx->dr3, pCtx->dr6, pCtx->dr7,
2430 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2431 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2432 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2433#endif
2434}
2435
2436/**
2437 * Structure used when disassembling and instructions in DBGF.
2438 * This is used so the reader function can get the stuff it needs.
2439 */
2440typedef struct CPUMDISASSTATE
2441{
2442 /** Pointer to the CPU structure. */
2443 PDISCPUSTATE pCpu;
2444 /** Pointer to the VM. */
2445 PVM pVM;
2446 /** Pointer to the VMCPU. */
2447 PVMCPU pVCpu;
2448 /** Pointer to the first byte in the segment. */
2449 RTGCUINTPTR GCPtrSegBase;
2450 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2451 RTGCUINTPTR GCPtrSegEnd;
2452 /** The size of the segment minus 1. */
2453 RTGCUINTPTR cbSegLimit;
2454 /** Pointer to the current page - R3 Ptr. */
2455 void const *pvPageR3;
2456 /** Pointer to the current page - GC Ptr. */
2457 RTGCPTR pvPageGC;
2458 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2459 PGMPAGEMAPLOCK PageMapLock;
2460 /** Whether the PageMapLock is valid or not. */
2461 bool fLocked;
2462 /** 64 bits mode or not. */
2463 bool f64Bits;
2464} CPUMDISASSTATE, *PCPUMDISASSTATE;
2465
2466
2467/**
2468 * @callback_method_impl{FNDISREADBYTES}
2469 */
2470static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
2471{
2472 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
2473 for (;;)
2474 {
2475 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
2476
2477 /*
2478 * Need to update the page translation?
2479 */
2480 if ( !pState->pvPageR3
2481 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2482 {
2483 int rc = VINF_SUCCESS;
2484
2485 /* translate the address */
2486 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2487 if ( !HMIsEnabled(pState->pVM)
2488 && MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
2489 {
2490 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2491 if (!pState->pvPageR3)
2492 rc = VERR_INVALID_POINTER;
2493 }
2494 else
2495 {
2496 /* Release mapping lock previously acquired. */
2497 if (pState->fLocked)
2498 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2499 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2500 pState->fLocked = RT_SUCCESS_NP(rc);
2501 }
2502 if (RT_FAILURE(rc))
2503 {
2504 pState->pvPageR3 = NULL;
2505 return rc;
2506 }
2507 }
2508
2509 /*
2510 * Check the segment limit.
2511 */
2512 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
2513 return VERR_OUT_OF_SELECTOR_BOUNDS;
2514
2515 /*
2516 * Calc how much we can read.
2517 */
2518 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2519 if (!pState->f64Bits)
2520 {
2521 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2522 if (cb > cbSeg && cbSeg)
2523 cb = cbSeg;
2524 }
2525 if (cb > cbMaxRead)
2526 cb = cbMaxRead;
2527
2528 /*
2529 * Read and advance or exit.
2530 */
2531 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2532 offInstr += (uint8_t)cb;
2533 if (cb >= cbMinRead)
2534 {
2535 pDis->cbCachedInstr = offInstr;
2536 return VINF_SUCCESS;
2537 }
2538 cbMinRead -= (uint8_t)cb;
2539 cbMaxRead -= (uint8_t)cb;
2540 }
2541}
2542
2543
2544/**
2545 * Disassemble an instruction and return the information in the provided structure.
2546 *
2547 * @returns VBox status code.
2548 * @param pVM The cross context VM structure.
2549 * @param pVCpu The cross context virtual CPU structure.
2550 * @param pCtx Pointer to the guest CPU context.
2551 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2552 * @param pCpu Disassembly state.
2553 * @param pszPrefix String prefix for logging (debug only).
2554 *
2555 */
2556VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
2557 const char *pszPrefix)
2558{
2559 CPUMDISASSTATE State;
2560 int rc;
2561
2562 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2563 State.pCpu = pCpu;
2564 State.pvPageGC = 0;
2565 State.pvPageR3 = NULL;
2566 State.pVM = pVM;
2567 State.pVCpu = pVCpu;
2568 State.fLocked = false;
2569 State.f64Bits = false;
2570
2571 /*
2572 * Get selector information.
2573 */
2574 DISCPUMODE enmDisCpuMode;
2575 if ( (pCtx->cr0 & X86_CR0_PE)
2576 && pCtx->eflags.Bits.u1VM == 0)
2577 {
2578 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2579 {
2580# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2581 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
2582# endif
2583 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2584 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
2585 }
2586 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
2587 State.GCPtrSegBase = pCtx->cs.u64Base;
2588 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
2589 State.cbSegLimit = pCtx->cs.u32Limit;
2590 enmDisCpuMode = (State.f64Bits)
2591 ? DISCPUMODE_64BIT
2592 : pCtx->cs.Attr.n.u1DefBig
2593 ? DISCPUMODE_32BIT
2594 : DISCPUMODE_16BIT;
2595 }
2596 else
2597 {
2598 /* real or V86 mode */
2599 enmDisCpuMode = DISCPUMODE_16BIT;
2600 State.GCPtrSegBase = pCtx->cs.Sel * 16;
2601 State.GCPtrSegEnd = 0xFFFFFFFF;
2602 State.cbSegLimit = 0xFFFFFFFF;
2603 }
2604
2605 /*
2606 * Disassemble the instruction.
2607 */
2608 uint32_t cbInstr;
2609#ifndef LOG_ENABLED
2610 RT_NOREF_PV(pszPrefix);
2611 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
2612 if (RT_SUCCESS(rc))
2613 {
2614#else
2615 char szOutput[160];
2616 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
2617 pCpu, &cbInstr, szOutput, sizeof(szOutput));
2618 if (RT_SUCCESS(rc))
2619 {
2620 /* log it */
2621 if (pszPrefix)
2622 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2623 else
2624 Log(("%s", szOutput));
2625#endif
2626 rc = VINF_SUCCESS;
2627 }
2628 else
2629 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
2630
2631 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2632 if (State.fLocked)
2633 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2634
2635 return rc;
2636}
2637
2638
2639
2640/**
2641 * API for controlling a few of the CPU features found in CR4.
2642 *
2643 * Currently only X86_CR4_TSD is accepted as input.
2644 *
2645 * @returns VBox status code.
2646 *
2647 * @param pVM The cross context VM structure.
2648 * @param fOr The CR4 OR mask.
2649 * @param fAnd The CR4 AND mask.
2650 */
2651VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2652{
2653 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2654 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2655
2656 pVM->cpum.s.CR4.OrMask &= fAnd;
2657 pVM->cpum.s.CR4.OrMask |= fOr;
2658
2659 return VINF_SUCCESS;
2660}
2661
2662
2663/**
2664 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
2665 *
2666 * Only REM should ever call this function!
2667 *
2668 * @returns The changed flags.
2669 * @param pVCpu The cross context virtual CPU structure.
2670 * @param puCpl Where to return the current privilege level (CPL).
2671 */
2672VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
2673{
2674 Assert(!pVCpu->cpum.s.fRawEntered);
2675 Assert(!pVCpu->cpum.s.fRemEntered);
2676
2677 /*
2678 * Get the CPL first.
2679 */
2680 *puCpl = CPUMGetGuestCPL(pVCpu);
2681
2682 /*
2683 * Get and reset the flags.
2684 */
2685 uint32_t fFlags = pVCpu->cpum.s.fChanged;
2686 pVCpu->cpum.s.fChanged = 0;
2687
2688 /** @todo change the switcher to use the fChanged flags. */
2689 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
2690 {
2691 fFlags |= CPUM_CHANGED_FPU_REM;
2692 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
2693 }
2694
2695 pVCpu->cpum.s.fRemEntered = true;
2696 return fFlags;
2697}
2698
2699
2700/**
2701 * Leaves REM.
2702 *
2703 * @param pVCpu The cross context virtual CPU structure.
2704 * @param fNoOutOfSyncSels This is @c false if there are out of sync
2705 * registers.
2706 */
2707VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
2708{
2709 Assert(!pVCpu->cpum.s.fRawEntered);
2710 Assert(pVCpu->cpum.s.fRemEntered);
2711
2712 RT_NOREF_PV(fNoOutOfSyncSels);
2713
2714 pVCpu->cpum.s.fRemEntered = false;
2715}
2716
2717
2718/**
2719 * Called when the ring-3 init phase completes.
2720 *
2721 * @returns VBox status code.
2722 * @param pVM The cross context VM structure.
2723 * @param enmWhat Which init phase.
2724 */
2725VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
2726{
2727 switch (enmWhat)
2728 {
2729 case VMINITCOMPLETED_RING3:
2730 {
2731 /*
2732 * Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
2733 * Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
2734 */
2735 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2736 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2737 {
2738 PVMCPU pVCpu = &pVM->aCpus[i];
2739 /* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
2740 if (fSupportsLongMode)
2741 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
2742 }
2743
2744 cpumR3MsrRegStats(pVM);
2745 break;
2746 }
2747
2748 default:
2749 break;
2750 }
2751 return VINF_SUCCESS;
2752}
2753
2754
2755/**
2756 * Called when the ring-0 init phases completed.
2757 *
2758 * @param pVM The cross context VM structure.
2759 */
2760VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
2761{
2762 /*
2763 * Log the cpuid.
2764 */
2765 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
2766 RTCPUSET OnlineSet;
2767 LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
2768 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
2769 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
2770 RTCPUID cCores = RTMpGetCoreCount();
2771 if (cCores)
2772 LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
2773 LogRel(("************************* CPUID dump ************************\n"));
2774 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
2775 LogRel(("\n"));
2776 DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
2777 RTLogRelSetBuffering(fOldBuffered);
2778 LogRel(("******************** End of CPUID dump **********************\n"));
2779}
2780
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