VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 62639

Last change on this file since 62639 was 62637, checked in by vboxsync, 8 years ago

VMMR3: warnings
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 115.4 KB
Line 
1/* $Id: CPUM.cpp 62637 2016-07-28 17:12:17Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 *
33 * @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34 *
35 * TODO: proper write up, currently just some notes.
36 *
37 * The ring-0 FPU handling per OS:
38 *
39 * - 64-bit Windows uses XMM registers in the kernel as part of the calling
40 * convention (Visual C++ doesn't seem to have a way to disable
41 * generating such code either), so CR0.TS/EM are always zero from what I
42 * can tell. We are also forced to always load/save the guest XMM0-XMM15
43 * registers when entering/leaving guest context. Interrupt handlers
44 * using FPU/SSE will offically have call save and restore functions
45 * exported by the kernel, if the really really have to use the state.
46 *
47 * - 32-bit windows does lazy FPU handling, I think, probably including
48 * lazying saving. The Windows Internals book states that it's a bad
49 * idea to use the FPU in kernel space. However, it looks like it will
50 * restore the FPU state of the current thread in case of a kernel \#NM.
51 * Interrupt handlers should be same as for 64-bit.
52 *
53 * - Darwin allows taking \#NM in kernel space, restoring current thread's
54 * state if I read the code correctly. It saves the FPU state of the
55 * outgoing thread, and uses CR0.TS to lazily load the state of the
56 * incoming one. No idea yet how the FPU is treated by interrupt
57 * handlers, i.e. whether they are allowed to disable the state or
58 * something.
59 *
60 * - Linux also allows \#NM in kernel space (don't know since when), and
61 * uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62 * loads the incoming unless configured to agressivly load it. Interrupt
63 * handlers can ask whether they're allowed to use the FPU, and may
64 * freely trash the state if Linux thinks it has saved the thread's state
65 * already. This is a problem.
66 *
67 * - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68 * context. When switching threads, the kernel will save the state of
69 * the outgoing thread and lazy load the incoming one using CR0.TS.
70 * There are a few routines in seeblk.s which uses the SSE unit in ring-0
71 * to do stuff, HAT are among the users. The routines there will
72 * manually clear CR0.TS and save the XMM registers they use only if
73 * CR0.TS was zero upon entry. They will skip it when not, because as
74 * mentioned above, the FPU state is saved when switching away from a
75 * thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76 * preserve. This is a problem if we restore CR0.TS to 1 after loading
77 * the guest state.
78 *
79 * - FreeBSD - no idea yet.
80 *
81 * - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82 * possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83 * FPU states.
84 *
85 * Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86 * saving and restoring the host and guest states. The motivation for this
87 * change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88 *
89 * Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90 * state and only restore it once we've restore the host FPU state. This has the
91 * accidental side effect of triggering Solaris to preserve XMM registers in
92 * sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93 * the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94 *
95 *
96 * @section sec_cpum_logging Logging Level Assignments.
97 *
98 * Following log level assignments:
99 * - Log6 is used for FPU state management.
100 * - Log7 is used for FPU state actualization.
101 *
102 */
103
104
105/*********************************************************************************************************************************
106* Header Files *
107*********************************************************************************************************************************/
108#define LOG_GROUP LOG_GROUP_CPUM
109#include <VBox/vmm/cpum.h>
110#include <VBox/vmm/cpumdis.h>
111#include <VBox/vmm/cpumctx-v1_6.h>
112#include <VBox/vmm/pgm.h>
113#include <VBox/vmm/pdmapi.h>
114#include <VBox/vmm/mm.h>
115#include <VBox/vmm/em.h>
116#include <VBox/vmm/selm.h>
117#include <VBox/vmm/dbgf.h>
118#include <VBox/vmm/patm.h>
119#include <VBox/vmm/hm.h>
120#include <VBox/vmm/ssm.h>
121#include "CPUMInternal.h"
122#include <VBox/vmm/vm.h>
123
124#include <VBox/param.h>
125#include <VBox/dis.h>
126#include <VBox/err.h>
127#include <VBox/log.h>
128#include <iprt/asm-amd64-x86.h>
129#include <iprt/assert.h>
130#include <iprt/cpuset.h>
131#include <iprt/mem.h>
132#include <iprt/mp.h>
133#include <iprt/string.h>
134
135
136/*********************************************************************************************************************************
137* Defined Constants And Macros *
138*********************************************************************************************************************************/
139/**
140 * This was used in the saved state up to the early life of version 14.
141 *
142 * It indicates that we may have some out-of-sync hidden segement registers.
143 * It is only relevant for raw-mode.
144 */
145#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
146
147
148/*********************************************************************************************************************************
149* Structures and Typedefs *
150*********************************************************************************************************************************/
151
152/**
153 * What kind of cpu info dump to perform.
154 */
155typedef enum CPUMDUMPTYPE
156{
157 CPUMDUMPTYPE_TERSE,
158 CPUMDUMPTYPE_DEFAULT,
159 CPUMDUMPTYPE_VERBOSE
160} CPUMDUMPTYPE;
161/** Pointer to a cpu info dump type. */
162typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
163
164
165/*********************************************************************************************************************************
166* Internal Functions *
167*********************************************************************************************************************************/
168static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
169static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
170static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
171static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
172static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
173static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
174static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178
179
180/*********************************************************************************************************************************
181* Global Variables *
182*********************************************************************************************************************************/
183/** Saved state field descriptors for CPUMCTX. */
184static const SSMFIELD g_aCpumCtxFields[] =
185{
186 SSMFIELD_ENTRY( CPUMCTX, rdi),
187 SSMFIELD_ENTRY( CPUMCTX, rsi),
188 SSMFIELD_ENTRY( CPUMCTX, rbp),
189 SSMFIELD_ENTRY( CPUMCTX, rax),
190 SSMFIELD_ENTRY( CPUMCTX, rbx),
191 SSMFIELD_ENTRY( CPUMCTX, rdx),
192 SSMFIELD_ENTRY( CPUMCTX, rcx),
193 SSMFIELD_ENTRY( CPUMCTX, rsp),
194 SSMFIELD_ENTRY( CPUMCTX, rflags),
195 SSMFIELD_ENTRY( CPUMCTX, rip),
196 SSMFIELD_ENTRY( CPUMCTX, r8),
197 SSMFIELD_ENTRY( CPUMCTX, r9),
198 SSMFIELD_ENTRY( CPUMCTX, r10),
199 SSMFIELD_ENTRY( CPUMCTX, r11),
200 SSMFIELD_ENTRY( CPUMCTX, r12),
201 SSMFIELD_ENTRY( CPUMCTX, r13),
202 SSMFIELD_ENTRY( CPUMCTX, r14),
203 SSMFIELD_ENTRY( CPUMCTX, r15),
204 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
205 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
206 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
207 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
208 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
209 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
210 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
211 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
212 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
213 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
214 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
215 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
216 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
217 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
218 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
219 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
220 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
221 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
222 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
223 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
224 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
225 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
226 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
227 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
228 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
229 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
230 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
231 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
232 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
233 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
234 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
235 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
236 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
237 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
238 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
239 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
240 SSMFIELD_ENTRY( CPUMCTX, cr0),
241 SSMFIELD_ENTRY( CPUMCTX, cr2),
242 SSMFIELD_ENTRY( CPUMCTX, cr3),
243 SSMFIELD_ENTRY( CPUMCTX, cr4),
244 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
245 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
246 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
247 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
248 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
249 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
250 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
251 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
252 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
253 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
254 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
255 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
256 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
257 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
258 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
259 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
260 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
261 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
262 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
263 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
264 /* msrApicBase is not included here, it resides in the APIC device state. */
265 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
266 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
267 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
268 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
269 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
270 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
271 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
272 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
273 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
274 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
275 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
276 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
277 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
278 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
279 SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
280 SSMFIELD_ENTRY_TERM()
281};
282
283/** Saved state field descriptors for CPUMCTX. */
284static const SSMFIELD g_aCpumX87Fields[] =
285{
286 SSMFIELD_ENTRY( X86FXSTATE, FCW),
287 SSMFIELD_ENTRY( X86FXSTATE, FSW),
288 SSMFIELD_ENTRY( X86FXSTATE, FTW),
289 SSMFIELD_ENTRY( X86FXSTATE, FOP),
290 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
291 SSMFIELD_ENTRY( X86FXSTATE, CS),
292 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
293 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
294 SSMFIELD_ENTRY( X86FXSTATE, DS),
295 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
296 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
297 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
298 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
299 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
300 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
301 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
302 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
303 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
304 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
305 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
306 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
307 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
308 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
309 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
310 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
311 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
312 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
313 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
314 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
315 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
316 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
317 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
318 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
319 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
320 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
321 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
322 SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
323 SSMFIELD_ENTRY_TERM()
324};
325
326/** Saved state field descriptors for X86XSAVEHDR. */
327static const SSMFIELD g_aCpumXSaveHdrFields[] =
328{
329 SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
330 SSMFIELD_ENTRY_TERM()
331};
332
333/** Saved state field descriptors for X86XSAVEYMMHI. */
334static const SSMFIELD g_aCpumYmmHiFields[] =
335{
336 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
337 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
338 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
339 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
340 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
341 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
342 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
343 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
344 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
345 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
346 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
347 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
348 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
349 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
350 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
351 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
352 SSMFIELD_ENTRY_TERM()
353};
354
355/** Saved state field descriptors for X86XSAVEBNDREGS. */
356static const SSMFIELD g_aCpumBndRegsFields[] =
357{
358 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
359 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
360 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
361 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
362 SSMFIELD_ENTRY_TERM()
363};
364
365/** Saved state field descriptors for X86XSAVEBNDCFG. */
366static const SSMFIELD g_aCpumBndCfgFields[] =
367{
368 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
369 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
370 SSMFIELD_ENTRY_TERM()
371};
372
373/** Saved state field descriptors for X86XSAVEOPMASK. */
374static const SSMFIELD g_aCpumOpmaskFields[] =
375{
376 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
377 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
378 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
379 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
380 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
381 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
382 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
383 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
384 SSMFIELD_ENTRY_TERM()
385};
386
387/** Saved state field descriptors for X86XSAVEZMMHI256. */
388static const SSMFIELD g_aCpumZmmHi256Fields[] =
389{
390 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
391 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
392 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
393 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
394 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
395 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
396 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
397 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
398 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
399 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
400 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
401 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
402 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
403 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
404 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
405 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
406 SSMFIELD_ENTRY_TERM()
407};
408
409/** Saved state field descriptors for X86XSAVEZMM16HI. */
410static const SSMFIELD g_aCpumZmm16HiFields[] =
411{
412 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
413 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
414 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
415 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
416 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
417 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
418 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
419 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
420 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
421 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
422 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
423 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
424 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
425 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
426 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
427 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
428 SSMFIELD_ENTRY_TERM()
429};
430
431
432
433/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
434 * registeres changed. */
435static const SSMFIELD g_aCpumX87FieldsMem[] =
436{
437 SSMFIELD_ENTRY( X86FXSTATE, FCW),
438 SSMFIELD_ENTRY( X86FXSTATE, FSW),
439 SSMFIELD_ENTRY( X86FXSTATE, FTW),
440 SSMFIELD_ENTRY( X86FXSTATE, FOP),
441 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
442 SSMFIELD_ENTRY( X86FXSTATE, CS),
443 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
444 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
445 SSMFIELD_ENTRY( X86FXSTATE, DS),
446 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
447 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
448 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
449 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
450 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
451 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
452 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
453 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
454 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
455 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
456 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
457 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
458 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
459 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
460 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
461 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
462 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
463 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
464 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
465 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
466 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
467 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
468 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
469 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
470 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
471 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
472 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
473 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
474 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
475};
476
477/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
478 * registeres changed. */
479static const SSMFIELD g_aCpumCtxFieldsMem[] =
480{
481 SSMFIELD_ENTRY( CPUMCTX, rdi),
482 SSMFIELD_ENTRY( CPUMCTX, rsi),
483 SSMFIELD_ENTRY( CPUMCTX, rbp),
484 SSMFIELD_ENTRY( CPUMCTX, rax),
485 SSMFIELD_ENTRY( CPUMCTX, rbx),
486 SSMFIELD_ENTRY( CPUMCTX, rdx),
487 SSMFIELD_ENTRY( CPUMCTX, rcx),
488 SSMFIELD_ENTRY( CPUMCTX, rsp),
489 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
490 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
491 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
492 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
493 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
494 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
495 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
496 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
497 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
498 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
499 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
500 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
501 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
502 SSMFIELD_ENTRY( CPUMCTX, rflags),
503 SSMFIELD_ENTRY( CPUMCTX, rip),
504 SSMFIELD_ENTRY( CPUMCTX, r8),
505 SSMFIELD_ENTRY( CPUMCTX, r9),
506 SSMFIELD_ENTRY( CPUMCTX, r10),
507 SSMFIELD_ENTRY( CPUMCTX, r11),
508 SSMFIELD_ENTRY( CPUMCTX, r12),
509 SSMFIELD_ENTRY( CPUMCTX, r13),
510 SSMFIELD_ENTRY( CPUMCTX, r14),
511 SSMFIELD_ENTRY( CPUMCTX, r15),
512 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
513 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
514 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
515 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
516 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
517 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
518 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
519 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
520 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
521 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
522 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
523 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
524 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
525 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
526 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
527 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
528 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
529 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
530 SSMFIELD_ENTRY( CPUMCTX, cr0),
531 SSMFIELD_ENTRY( CPUMCTX, cr2),
532 SSMFIELD_ENTRY( CPUMCTX, cr3),
533 SSMFIELD_ENTRY( CPUMCTX, cr4),
534 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
535 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
536 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
537 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
538 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
539 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
540 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
541 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
542 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
543 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
544 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
545 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
546 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
547 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
548 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
549 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
550 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
551 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
552 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
553 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
554 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
555 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
556 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
557 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
558 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
559 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
560 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
561 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
562 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
563 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
564 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
565 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
566 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
567 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
568 SSMFIELD_ENTRY_TERM()
569};
570
571/** Saved state field descriptors for CPUMCTX_VER1_6. */
572static const SSMFIELD g_aCpumX87FieldsV16[] =
573{
574 SSMFIELD_ENTRY( X86FXSTATE, FCW),
575 SSMFIELD_ENTRY( X86FXSTATE, FSW),
576 SSMFIELD_ENTRY( X86FXSTATE, FTW),
577 SSMFIELD_ENTRY( X86FXSTATE, FOP),
578 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
579 SSMFIELD_ENTRY( X86FXSTATE, CS),
580 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
581 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
582 SSMFIELD_ENTRY( X86FXSTATE, DS),
583 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
584 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
585 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
586 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
587 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
588 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
589 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
590 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
591 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
592 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
593 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
594 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
595 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
596 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
597 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
598 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
599 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
600 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
601 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
602 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
603 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
604 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
605 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
606 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
607 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
608 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
609 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
610 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
611 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
612 SSMFIELD_ENTRY_TERM()
613};
614
615/** Saved state field descriptors for CPUMCTX_VER1_6. */
616static const SSMFIELD g_aCpumCtxFieldsV16[] =
617{
618 SSMFIELD_ENTRY( CPUMCTX, rdi),
619 SSMFIELD_ENTRY( CPUMCTX, rsi),
620 SSMFIELD_ENTRY( CPUMCTX, rbp),
621 SSMFIELD_ENTRY( CPUMCTX, rax),
622 SSMFIELD_ENTRY( CPUMCTX, rbx),
623 SSMFIELD_ENTRY( CPUMCTX, rdx),
624 SSMFIELD_ENTRY( CPUMCTX, rcx),
625 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
626 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
627 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
628 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
629 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
630 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
631 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
632 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
633 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
634 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
635 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
636 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
637 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
638 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
639 SSMFIELD_ENTRY( CPUMCTX, rflags),
640 SSMFIELD_ENTRY( CPUMCTX, rip),
641 SSMFIELD_ENTRY( CPUMCTX, r8),
642 SSMFIELD_ENTRY( CPUMCTX, r9),
643 SSMFIELD_ENTRY( CPUMCTX, r10),
644 SSMFIELD_ENTRY( CPUMCTX, r11),
645 SSMFIELD_ENTRY( CPUMCTX, r12),
646 SSMFIELD_ENTRY( CPUMCTX, r13),
647 SSMFIELD_ENTRY( CPUMCTX, r14),
648 SSMFIELD_ENTRY( CPUMCTX, r15),
649 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
650 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
651 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
652 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
653 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
654 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
655 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
656 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
657 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
658 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
659 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
660 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
661 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
662 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
663 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
664 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
665 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
666 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
667 SSMFIELD_ENTRY( CPUMCTX, cr0),
668 SSMFIELD_ENTRY( CPUMCTX, cr2),
669 SSMFIELD_ENTRY( CPUMCTX, cr3),
670 SSMFIELD_ENTRY( CPUMCTX, cr4),
671 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
672 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
673 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
674 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
675 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
676 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
677 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
678 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
679 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
680 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
681 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
682 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
683 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
684 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
685 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
686 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
687 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
688 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
689 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
690 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
691 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
692 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
693 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
694 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
695 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
696 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
697 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
698 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
699 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
700 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
701 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
702 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
703 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
704 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
705 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
706 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
707 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
708 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
709 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
710 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
711 SSMFIELD_ENTRY_TERM()
712};
713
714
715/**
716 * Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
717 *
718 * AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
719 * (last instruction pointer, last data pointer, last opcode) except when the ES
720 * bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
721 * clear these registers there is potential, local FPU leakage from a process
722 * using the FPU to another.
723 *
724 * See AMD Instruction Reference for FXSAVE, FXRSTOR.
725 *
726 * @param pVM The cross context VM structure.
727 */
728static void cpumR3CheckLeakyFpu(PVM pVM)
729{
730 uint32_t u32CpuVersion = ASMCpuId_EAX(1);
731 uint32_t const u32Family = u32CpuVersion >> 8;
732 if ( u32Family >= 6 /* K7 and higher */
733 && ASMIsAmdCpu())
734 {
735 uint32_t cExt = ASMCpuId_EAX(0x80000000);
736 if (ASMIsValidExtRange(cExt))
737 {
738 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
739 if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
740 {
741 for (VMCPUID i = 0; i < pVM->cCpus; i++)
742 pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_FFXSR_LEAKY;
743 Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
744 }
745 }
746 }
747}
748
749
750/**
751 * Initializes the CPUM.
752 *
753 * @returns VBox status code.
754 * @param pVM The cross context VM structure.
755 */
756VMMR3DECL(int) CPUMR3Init(PVM pVM)
757{
758 LogFlow(("CPUMR3Init\n"));
759
760 /*
761 * Assert alignment, sizes and tables.
762 */
763 AssertCompileMemberAlignment(VM, cpum.s, 32);
764 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
765 AssertCompileSizeAlignment(CPUMCTX, 64);
766 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
767 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
768 AssertCompileMemberAlignment(VM, cpum, 64);
769 AssertCompileMemberAlignment(VM, aCpus, 64);
770 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
771 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
772#ifdef VBOX_STRICT
773 int rc2 = cpumR3MsrStrictInitChecks();
774 AssertRCReturn(rc2, rc2);
775#endif
776
777 /*
778 * Initialize offsets.
779 */
780
781 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
782 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
783 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
784
785
786 /* Calculate the offset from CPUMCPU to CPUM. */
787 for (VMCPUID i = 0; i < pVM->cCpus; i++)
788 {
789 PVMCPU pVCpu = &pVM->aCpus[i];
790
791 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
792 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
793 }
794
795 /*
796 * Gather info about the host CPU.
797 */
798 if (!ASMHasCpuId())
799 {
800 Log(("The CPU doesn't support CPUID!\n"));
801 return VERR_UNSUPPORTED_CPU;
802 }
803
804 PCPUMCPUIDLEAF paLeaves;
805 uint32_t cLeaves;
806 int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
807 AssertLogRelRCReturn(rc, rc);
808
809 rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
810 RTMemFree(paLeaves);
811 AssertLogRelRCReturn(rc, rc);
812 pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
813
814 /*
815 * Check that the CPU supports the minimum features we require.
816 */
817 if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
818 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
819 if (!pVM->cpum.s.HostFeatures.fMmx)
820 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
821 if (!pVM->cpum.s.HostFeatures.fTsc)
822 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
823
824 /*
825 * Setup the CR4 AND and OR masks used in the raw-mode switcher.
826 */
827 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
828 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
829
830 /*
831 * Figure out which XSAVE/XRSTOR features are available on the host.
832 */
833 uint64_t fXcr0Host = 0;
834 uint64_t fXStateHostMask = 0;
835 if ( pVM->cpum.s.HostFeatures.fXSaveRstor
836 && pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
837 {
838 fXStateHostMask = fXcr0Host = ASMGetXcr0();
839 fXStateHostMask &= XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI;
840 AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 | XSAVE_C_SSE)) == (XSAVE_C_X87 | XSAVE_C_SSE),
841 ("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
842 }
843 pVM->cpum.s.fXStateHostMask = fXStateHostMask;
844 if (!HMIsEnabled(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
845 fXStateHostMask = 0;
846 LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
847 pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
848
849 /*
850 * Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
851 */
852 uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
853 cbMaxXState = RT_ALIGN(cbMaxXState, 128);
854 AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
855
856 uint8_t *pbXStates;
857 rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
858 MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
859 AssertLogRelRCReturn(rc, rc);
860
861 for (VMCPUID i = 0; i < pVM->cCpus; i++)
862 {
863 PVMCPU pVCpu = &pVM->aCpus[i];
864
865 pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
866 pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
867 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
868 pbXStates += cbMaxXState;
869
870 pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
871 pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
872 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
873 pbXStates += cbMaxXState;
874
875 pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
876 pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
877 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
878 pbXStates += cbMaxXState;
879
880 pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
881 }
882
883 /*
884 * Setup hypervisor startup values.
885 */
886
887 /*
888 * Register saved state data item.
889 */
890 rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
891 NULL, cpumR3LiveExec, NULL,
892 NULL, cpumR3SaveExec, NULL,
893 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
894 if (RT_FAILURE(rc))
895 return rc;
896
897 /*
898 * Register info handlers and registers with the debugger facility.
899 */
900 DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
901 &cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
902 DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
903 &cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
904 DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
905 &cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
906 DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
907 &cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
908 DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
909 &cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
910 DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
911
912 rc = cpumR3DbgInit(pVM);
913 if (RT_FAILURE(rc))
914 return rc;
915
916 /*
917 * Check if we need to workaround partial/leaky FPU handling.
918 */
919 cpumR3CheckLeakyFpu(pVM);
920
921 /*
922 * Initialize the Guest CPUID and MSR states.
923 */
924 rc = cpumR3InitCpuIdAndMsrs(pVM);
925 if (RT_FAILURE(rc))
926 return rc;
927 CPUMR3Reset(pVM);
928 return VINF_SUCCESS;
929}
930
931
932/**
933 * Applies relocations to data and code managed by this
934 * component. This function will be called at init and
935 * whenever the VMM need to relocate it self inside the GC.
936 *
937 * The CPUM will update the addresses used by the switcher.
938 *
939 * @param pVM The cross context VM structure.
940 */
941VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
942{
943 LogFlow(("CPUMR3Relocate\n"));
944
945 pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
946 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
947
948 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
949 {
950 PVMCPU pVCpu = &pVM->aCpus[iCpu];
951 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
952 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
953 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
954
955 /* Recheck the guest DRx values in raw-mode. */
956 CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
957 }
958}
959
960
961/**
962 * Apply late CPUM property changes based on the fHWVirtEx setting
963 *
964 * @param pVM The cross context VM structure.
965 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
966 */
967VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
968{
969 /*
970 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
971 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
972 * of processors from (cpuid(4).eax >> 26) + 1.
973 *
974 * Note: this code is obsolete, but let's keep it here for reference.
975 * Purpose is valid when we artificially cap the max std id to less than 4.
976 */
977 if (!fHWVirtExEnabled)
978 {
979 Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
980 || pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
981 pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
982 }
983}
984
985/**
986 * Terminates the CPUM.
987 *
988 * Termination means cleaning up and freeing all resources,
989 * the VM it self is at this point powered off or suspended.
990 *
991 * @returns VBox status code.
992 * @param pVM The cross context VM structure.
993 */
994VMMR3DECL(int) CPUMR3Term(PVM pVM)
995{
996#ifdef VBOX_WITH_CRASHDUMP_MAGIC
997 for (VMCPUID i = 0; i < pVM->cCpus; i++)
998 {
999 PVMCPU pVCpu = &pVM->aCpus[i];
1000 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1001
1002 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1003 pVCpu->cpum.s.uMagic = 0;
1004 pCtx->dr[5] = 0;
1005 }
1006#else
1007 NOREF(pVM);
1008#endif
1009 return VINF_SUCCESS;
1010}
1011
1012
1013/**
1014 * Resets a virtual CPU.
1015 *
1016 * Used by CPUMR3Reset and CPU hot plugging.
1017 *
1018 * @param pVM The cross context VM structure.
1019 * @param pVCpu The cross context virtual CPU structure of the CPU that is
1020 * being reset. This may differ from the current EMT.
1021 */
1022VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
1023{
1024 /** @todo anything different for VCPU > 0? */
1025 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1026
1027 /*
1028 * Initialize everything to ZERO first.
1029 */
1030 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1031
1032 AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
1033 AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
1034 memset(pCtx, 0, RT_OFFSETOF(CPUMCTX, pXStateR0));
1035
1036 pVCpu->cpum.s.fUseFlags = fUseFlags;
1037
1038 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
1039 pCtx->eip = 0x0000fff0;
1040 pCtx->edx = 0x00000600; /* P6 processor */
1041 pCtx->eflags.Bits.u1Reserved0 = 1;
1042
1043 pCtx->cs.Sel = 0xf000;
1044 pCtx->cs.ValidSel = 0xf000;
1045 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1046 pCtx->cs.u64Base = UINT64_C(0xffff0000);
1047 pCtx->cs.u32Limit = 0x0000ffff;
1048 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1049 pCtx->cs.Attr.n.u1Present = 1;
1050 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1051
1052 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1053 pCtx->ds.u32Limit = 0x0000ffff;
1054 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1055 pCtx->ds.Attr.n.u1Present = 1;
1056 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1057
1058 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1059 pCtx->es.u32Limit = 0x0000ffff;
1060 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1061 pCtx->es.Attr.n.u1Present = 1;
1062 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1063
1064 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1065 pCtx->fs.u32Limit = 0x0000ffff;
1066 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1067 pCtx->fs.Attr.n.u1Present = 1;
1068 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1069
1070 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1071 pCtx->gs.u32Limit = 0x0000ffff;
1072 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1073 pCtx->gs.Attr.n.u1Present = 1;
1074 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1075
1076 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1077 pCtx->ss.u32Limit = 0x0000ffff;
1078 pCtx->ss.Attr.n.u1Present = 1;
1079 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1080 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1081
1082 pCtx->idtr.cbIdt = 0xffff;
1083 pCtx->gdtr.cbGdt = 0xffff;
1084
1085 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1086 pCtx->ldtr.u32Limit = 0xffff;
1087 pCtx->ldtr.Attr.n.u1Present = 1;
1088 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1089
1090 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1091 pCtx->tr.u32Limit = 0xffff;
1092 pCtx->tr.Attr.n.u1Present = 1;
1093 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1094
1095 pCtx->dr[6] = X86_DR6_INIT_VAL;
1096 pCtx->dr[7] = X86_DR7_INIT_VAL;
1097
1098 PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
1099 pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
1100 pFpuCtx->FCW = 0x37f;
1101
1102 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1103 IA-32 Processor States Following Power-up, Reset, or INIT */
1104 pFpuCtx->MXCSR = 0x1F80;
1105 pFpuCtx->MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
1106 supports all bits, since a zero value here should be read as 0xffbf. */
1107 pCtx->aXcr[0] = XSAVE_C_X87;
1108 if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_OFFSETOF(X86XSAVEAREA, Hdr))
1109 {
1110 /* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
1111 as we don't know what happened before. (Bother optimize later?) */
1112 pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 | XSAVE_C_SSE;
1113 }
1114
1115 /*
1116 * MSRs.
1117 */
1118 /* Init PAT MSR */
1119 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1120
1121 /* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1122 * The Intel docs don't mention it. */
1123 Assert(!pCtx->msrEFER);
1124
1125 /* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
1126 is supposed to be here, just trying provide useful/sensible values. */
1127 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
1128 if (pRange)
1129 {
1130 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1131 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1132 | (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
1133 | MSR_IA32_MISC_ENABLE_FAST_STRINGS;
1134 pRange->fWrIgnMask |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1135 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
1136 pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1137 }
1138
1139 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1140
1141 /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1142 * called from each EMT while we're getting called by CPUMR3Reset()
1143 * iteratively on the same thread. Fix later. */
1144#if 0 /** @todo r=bird: This we will do in TM, not here. */
1145 /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1146 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1147#endif
1148
1149
1150 /* C-state control. Guesses. */
1151 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
1152
1153
1154 /*
1155 * Get the APIC base MSR from the APIC device. For historical reasons (saved state), the APIC base
1156 * continues to reside in the APIC device and we cache it here in the VCPU for all further accesses.
1157 */
1158 PDMApicGetBaseMsr(pVCpu, &pCtx->msrApicBase, true /* fIgnoreErrors */);
1159#ifdef VBOX_WITH_NEW_APIC
1160 LogRel(("CPUM: VCPU%3d: Cached APIC base MSR = %#RX64\n", pVCpu->idCpu, pVCpu->cpum.s.Guest.msrApicBase));
1161#endif
1162}
1163
1164
1165/**
1166 * Resets the CPU.
1167 *
1168 * @returns VINF_SUCCESS.
1169 * @param pVM The cross context VM structure.
1170 */
1171VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1172{
1173 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1174 {
1175 CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
1176
1177#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1178 PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1179
1180 /* Magic marker for searching in crash dumps. */
1181 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1182 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1183 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1184#endif
1185 }
1186}
1187
1188
1189
1190
1191/**
1192 * Pass 0 live exec callback.
1193 *
1194 * @returns VINF_SSM_DONT_CALL_AGAIN.
1195 * @param pVM The cross context VM structure.
1196 * @param pSSM The saved state handle.
1197 * @param uPass The pass (0).
1198 */
1199static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1200{
1201 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
1202 cpumR3SaveCpuId(pVM, pSSM);
1203 return VINF_SSM_DONT_CALL_AGAIN;
1204}
1205
1206
1207/**
1208 * Execute state save operation.
1209 *
1210 * @returns VBox status code.
1211 * @param pVM The cross context VM structure.
1212 * @param pSSM SSM operation handle.
1213 */
1214static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1215{
1216 /*
1217 * Save.
1218 */
1219 SSMR3PutU32(pSSM, pVM->cCpus);
1220 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
1221 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1222 {
1223 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1224
1225 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1226
1227 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1228 SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1229 SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1230 if (pGstCtx->fXStateMask != 0)
1231 SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
1232 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1233 {
1234 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1235 SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1236 }
1237 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1238 {
1239 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1240 SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1241 }
1242 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1243 {
1244 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1245 SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1246 }
1247 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1248 {
1249 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1250 SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1251 }
1252 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1253 {
1254 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1255 SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1256 }
1257
1258 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1259 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1260 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
1261 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
1262 }
1263
1264 cpumR3SaveCpuId(pVM, pSSM);
1265 return VINF_SUCCESS;
1266}
1267
1268
1269/**
1270 * @callback_method_impl{FNSSMINTLOADPREP}
1271 */
1272static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1273{
1274 NOREF(pSSM);
1275 pVM->cpum.s.fPendingRestore = true;
1276 return VINF_SUCCESS;
1277}
1278
1279
1280/**
1281 * @callback_method_impl{FNSSMINTLOADEXEC}
1282 */
1283static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1284{
1285 int rc; /* Only for AssertRCReturn use. */
1286
1287 /*
1288 * Validate version.
1289 */
1290 if ( uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
1291 && uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
1292 && uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
1293 && uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
1294 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
1295 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
1296 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
1297 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1298 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1299 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1300 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1301 {
1302 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1303 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1304 }
1305
1306 if (uPass == SSM_PASS_FINAL)
1307 {
1308 /*
1309 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1310 * really old SSM file versions.)
1311 */
1312 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1313 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1314 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1315 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1316
1317 /*
1318 * Figure x86 and ctx field definitions to use for older states.
1319 */
1320 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
1321 PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
1322 PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
1323 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1324 {
1325 paCpumCtx1Fields = g_aCpumX87FieldsV16;
1326 paCpumCtx2Fields = g_aCpumCtxFieldsV16;
1327 }
1328 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1329 {
1330 paCpumCtx1Fields = g_aCpumX87FieldsMem;
1331 paCpumCtx2Fields = g_aCpumCtxFieldsMem;
1332 }
1333
1334 /*
1335 * The hyper state used to preceed the CPU count. Starting with
1336 * XSAVE it was moved down till after we've got the count.
1337 */
1338 if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
1339 {
1340 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1341 {
1342 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1343 X86FXSTATE Ign;
1344 SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1345 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1346 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1347 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
1348 fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1349 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1350 pVCpu->cpum.s.Hyper.rsp = uRSP;
1351 }
1352 }
1353
1354 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1355 {
1356 uint32_t cCpus;
1357 rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1358 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1359 VERR_SSM_UNEXPECTED_DATA);
1360 }
1361 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
1362 || pVM->cCpus == 1,
1363 ("cCpus=%u\n", pVM->cCpus),
1364 VERR_SSM_UNEXPECTED_DATA);
1365
1366 uint32_t cbMsrs = 0;
1367 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1368 {
1369 rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
1370 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
1371 VERR_SSM_UNEXPECTED_DATA);
1372 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
1373 VERR_SSM_UNEXPECTED_DATA);
1374 }
1375
1376 /*
1377 * Do the per-CPU restoring.
1378 */
1379 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1380 {
1381 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1382 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1383
1384 if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
1385 {
1386 /*
1387 * The XSAVE saved state layout moved the hyper state down here.
1388 */
1389 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1390 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1391 rc = SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1392 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1393 pVCpu->cpum.s.Hyper.rsp = uRSP;
1394 AssertRCReturn(rc, rc);
1395
1396 /*
1397 * Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
1398 */
1399 rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1400 rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1401 AssertRCReturn(rc, rc);
1402
1403 /* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
1404 if (pGstCtx->fXStateMask != 0)
1405 {
1406 AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
1407 ("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
1408 pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
1409 VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
1410 AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
1411 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1412 AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
1413 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1414 AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1415 || (pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1416 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
1417 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1418 }
1419
1420 /* Check that the XCR0 mask is valid (invalid results in #GP). */
1421 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
1422 if (pGstCtx->aXcr[0] != XSAVE_C_X87)
1423 {
1424 AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask | XSAVE_C_X87)),
1425 ("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
1426 VERR_CPUM_INVALID_XCR0);
1427 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
1428 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1429 AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
1430 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1431 AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1432 || (pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1433 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
1434 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1435 }
1436
1437 /* Check that the XCR1 is zero, as we don't implement it yet. */
1438 AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
1439
1440 /*
1441 * Restore the individual extended state components we support.
1442 */
1443 if (pGstCtx->fXStateMask != 0)
1444 {
1445 rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
1446 0, g_aCpumXSaveHdrFields, NULL);
1447 AssertRCReturn(rc, rc);
1448 AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
1449 ("bmXState=%#RX64 fXStateMask=%#RX64\n",
1450 pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
1451 VERR_CPUM_INVALID_XSAVE_HDR);
1452 }
1453 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1454 {
1455 PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
1456 SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1457 }
1458 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1459 {
1460 PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
1461 SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1462 }
1463 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1464 {
1465 PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
1466 SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1467 }
1468 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1469 {
1470 PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
1471 SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1472 }
1473 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1474 {
1475 PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
1476 SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1477 }
1478 }
1479 else
1480 {
1481 /*
1482 * Pre XSAVE saved state.
1483 */
1484 SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
1485 fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1486 SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1487 }
1488
1489 /*
1490 * Restore a couple of flags and the MSRs.
1491 */
1492 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
1493 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
1494
1495 rc = VINF_SUCCESS;
1496 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1497 rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
1498 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1499 {
1500 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
1501 rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
1502 }
1503 AssertRCReturn(rc, rc);
1504
1505 /* REM and other may have cleared must-be-one fields in DR6 and
1506 DR7, fix these. */
1507 pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
1508 pGstCtx->dr[6] |= X86_DR6_RA1_MASK;
1509 pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
1510 pGstCtx->dr[7] |= X86_DR7_RA1_MASK;
1511 }
1512
1513 /* Older states does not have the internal selector register flags
1514 and valid selector value. Supply those. */
1515 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1516 {
1517 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1518 {
1519 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1520 bool const fValid = HMIsEnabled(pVM)
1521 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1522 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
1523 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
1524 if (fValid)
1525 {
1526 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1527 {
1528 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
1529 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
1530 }
1531
1532 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1533 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1534 }
1535 else
1536 {
1537 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1538 {
1539 paSelReg[iSelReg].fFlags = 0;
1540 paSelReg[iSelReg].ValidSel = 0;
1541 }
1542
1543 /* This might not be 104% correct, but I think it's close
1544 enough for all practical purposes... (REM always loaded
1545 LDTR registers.) */
1546 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1547 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1548 }
1549 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1550 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
1551 }
1552 }
1553
1554 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
1555 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1556 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1557 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1558 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
1559
1560 /*
1561 * A quick sanity check.
1562 */
1563 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1564 {
1565 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1566 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1567 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1568 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1569 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1570 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1571 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1572 }
1573 }
1574
1575 pVM->cpum.s.fPendingRestore = false;
1576
1577 /*
1578 * Guest CPUIDs.
1579 */
1580 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
1581 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1582 return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
1583}
1584
1585
1586/**
1587 * @callback_method_impl{FNSSMINTLOADDONE}
1588 */
1589static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
1590{
1591 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
1592 return VINF_SUCCESS;
1593
1594 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
1595 if (pVM->cpum.s.fPendingRestore)
1596 {
1597 LogRel(("CPUM: Missing state!\n"));
1598 return VERR_INTERNAL_ERROR_2;
1599 }
1600
1601 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
1602 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1603 {
1604 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1605
1606 /* Notify PGM of the NXE states in case they've changed. */
1607 PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
1608
1609 /* Cache the local APIC base from the APIC device. During init. this is done in CPUMR3ResetCpu(). */
1610 PDMApicGetBaseMsr(pVCpu, &pVCpu->cpum.s.Guest.msrApicBase, true /* fIgnoreErrors */);
1611#ifdef VBOX_WITH_NEW_APIC
1612 LogRel(("CPUM: VCPU%3d: Cached APIC base MSR = %#RX64\n", idCpu, pVCpu->cpum.s.Guest.msrApicBase));
1613#endif
1614
1615 /* During init. this is done in CPUMR3InitCompleted(). */
1616 if (fSupportsLongMode)
1617 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
1618 }
1619 return VINF_SUCCESS;
1620}
1621
1622
1623/**
1624 * Checks if the CPUM state restore is still pending.
1625 *
1626 * @returns true / false.
1627 * @param pVM The cross context VM structure.
1628 */
1629VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
1630{
1631 return pVM->cpum.s.fPendingRestore;
1632}
1633
1634
1635/**
1636 * Formats the EFLAGS value into mnemonics.
1637 *
1638 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1639 * @param efl The EFLAGS value.
1640 */
1641static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1642{
1643 /*
1644 * Format the flags.
1645 */
1646 static const struct
1647 {
1648 const char *pszSet; const char *pszClear; uint32_t fFlag;
1649 } s_aFlags[] =
1650 {
1651 { "vip",NULL, X86_EFL_VIP },
1652 { "vif",NULL, X86_EFL_VIF },
1653 { "ac", NULL, X86_EFL_AC },
1654 { "vm", NULL, X86_EFL_VM },
1655 { "rf", NULL, X86_EFL_RF },
1656 { "nt", NULL, X86_EFL_NT },
1657 { "ov", "nv", X86_EFL_OF },
1658 { "dn", "up", X86_EFL_DF },
1659 { "ei", "di", X86_EFL_IF },
1660 { "tf", NULL, X86_EFL_TF },
1661 { "nt", "pl", X86_EFL_SF },
1662 { "nz", "zr", X86_EFL_ZF },
1663 { "ac", "na", X86_EFL_AF },
1664 { "po", "pe", X86_EFL_PF },
1665 { "cy", "nc", X86_EFL_CF },
1666 };
1667 char *psz = pszEFlags;
1668 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1669 {
1670 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1671 if (pszAdd)
1672 {
1673 strcpy(psz, pszAdd);
1674 psz += strlen(pszAdd);
1675 *psz++ = ' ';
1676 }
1677 }
1678 psz[-1] = '\0';
1679}
1680
1681
1682/**
1683 * Formats a full register dump.
1684 *
1685 * @param pVM The cross context VM structure.
1686 * @param pCtx The context to format.
1687 * @param pCtxCore The context core to format.
1688 * @param pHlp Output functions.
1689 * @param enmType The dump type.
1690 * @param pszPrefix Register name prefix.
1691 */
1692static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
1693 const char *pszPrefix)
1694{
1695 NOREF(pVM);
1696
1697 /*
1698 * Format the EFLAGS.
1699 */
1700 uint32_t efl = pCtxCore->eflags.u32;
1701 char szEFlags[80];
1702 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1703
1704 /*
1705 * Format the registers.
1706 */
1707 switch (enmType)
1708 {
1709 case CPUMDUMPTYPE_TERSE:
1710 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1711 pHlp->pfnPrintf(pHlp,
1712 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1713 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1714 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1715 "%sr14=%016RX64 %sr15=%016RX64\n"
1716 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1717 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1718 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1719 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1720 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1721 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1722 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1723 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1724 else
1725 pHlp->pfnPrintf(pHlp,
1726 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1727 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1728 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1729 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1730 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1731 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1732 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1733 break;
1734
1735 case CPUMDUMPTYPE_DEFAULT:
1736 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1737 pHlp->pfnPrintf(pHlp,
1738 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1739 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1740 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1741 "%sr14=%016RX64 %sr15=%016RX64\n"
1742 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1743 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1744 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1745 ,
1746 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1747 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1748 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1749 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1750 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1751 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1752 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1753 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1754 else
1755 pHlp->pfnPrintf(pHlp,
1756 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1757 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1758 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1759 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1760 ,
1761 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1762 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1763 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1764 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1765 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1766 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1767 break;
1768
1769 case CPUMDUMPTYPE_VERBOSE:
1770 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1771 pHlp->pfnPrintf(pHlp,
1772 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1773 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1774 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1775 "%sr14=%016RX64 %sr15=%016RX64\n"
1776 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1777 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1778 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1779 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1780 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1781 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1782 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1783 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1784 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1785 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1786 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1787 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1788 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1789 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1790 ,
1791 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1792 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1793 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1794 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1795 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1796 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1797 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1798 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1799 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1800 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1801 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1802 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1803 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1804 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1805 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1806 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1807 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1808 else
1809 pHlp->pfnPrintf(pHlp,
1810 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1811 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1812 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1813 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1814 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1815 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1816 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1817 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1818 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1819 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1820 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1821 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1822 ,
1823 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1824 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1825 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1826 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1827 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1828 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1829 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1830 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1831 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1832 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1833 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1834 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1835
1836 pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
1837 pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
1838 pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
1839 if (pCtx->CTX_SUFF(pXState))
1840 {
1841 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1842 pHlp->pfnPrintf(pHlp,
1843 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1844 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
1845 ,
1846 pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
1847 pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
1848 pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
1849 pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
1850 );
1851 /*
1852 * The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
1853 * not (FP)R0-7 as Intel SDM suggests.
1854 */
1855 unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
1856 for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
1857 {
1858 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
1859 unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
1860 char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
1861 unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
1862 uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
1863 int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
1864 iExponent -= 16383; /* subtract bias */
1865 /** @todo This isn't entirenly correct and needs more work! */
1866 pHlp->pfnPrintf(pHlp,
1867 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
1868 pszPrefix, iST, pszPrefix, iFPR,
1869 pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
1870 uTag, chSign, iInteger, u64Fraction, iExponent);
1871 if (pFpuCtx->aRegs[iST].au16[5] || pFpuCtx->aRegs[iST].au16[6] || pFpuCtx->aRegs[iST].au16[7])
1872 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
1873 pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
1874 else
1875 pHlp->pfnPrintf(pHlp, "\n");
1876 }
1877
1878 /* XMM/YMM/ZMM registers. */
1879 if (pCtx->fXStateMask & XSAVE_C_YMM)
1880 {
1881 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1882 if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
1883 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1884 pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1885 pszPrefix, i, i < 10 ? " " : "",
1886 pYmmHiCtx->aYmmHi[i].au32[3],
1887 pYmmHiCtx->aYmmHi[i].au32[2],
1888 pYmmHiCtx->aYmmHi[i].au32[1],
1889 pYmmHiCtx->aYmmHi[i].au32[0],
1890 pFpuCtx->aXMM[i].au32[3],
1891 pFpuCtx->aXMM[i].au32[2],
1892 pFpuCtx->aXMM[i].au32[1],
1893 pFpuCtx->aXMM[i].au32[0]);
1894 else
1895 {
1896 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1897 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1898 pHlp->pfnPrintf(pHlp,
1899 "%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1900 pszPrefix, i, i < 10 ? " " : "",
1901 pZmmHi256->aHi256Regs[i].au32[7],
1902 pZmmHi256->aHi256Regs[i].au32[6],
1903 pZmmHi256->aHi256Regs[i].au32[5],
1904 pZmmHi256->aHi256Regs[i].au32[4],
1905 pZmmHi256->aHi256Regs[i].au32[3],
1906 pZmmHi256->aHi256Regs[i].au32[2],
1907 pZmmHi256->aHi256Regs[i].au32[1],
1908 pZmmHi256->aHi256Regs[i].au32[0],
1909 pYmmHiCtx->aYmmHi[i].au32[3],
1910 pYmmHiCtx->aYmmHi[i].au32[2],
1911 pYmmHiCtx->aYmmHi[i].au32[1],
1912 pYmmHiCtx->aYmmHi[i].au32[0],
1913 pFpuCtx->aXMM[i].au32[3],
1914 pFpuCtx->aXMM[i].au32[2],
1915 pFpuCtx->aXMM[i].au32[1],
1916 pFpuCtx->aXMM[i].au32[0]);
1917
1918 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1919 for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
1920 pHlp->pfnPrintf(pHlp,
1921 "%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1922 pszPrefix, i + 16,
1923 pZmm16Hi->aRegs[i].au32[15],
1924 pZmm16Hi->aRegs[i].au32[14],
1925 pZmm16Hi->aRegs[i].au32[13],
1926 pZmm16Hi->aRegs[i].au32[12],
1927 pZmm16Hi->aRegs[i].au32[11],
1928 pZmm16Hi->aRegs[i].au32[10],
1929 pZmm16Hi->aRegs[i].au32[9],
1930 pZmm16Hi->aRegs[i].au32[8],
1931 pZmm16Hi->aRegs[i].au32[7],
1932 pZmm16Hi->aRegs[i].au32[6],
1933 pZmm16Hi->aRegs[i].au32[5],
1934 pZmm16Hi->aRegs[i].au32[4],
1935 pZmm16Hi->aRegs[i].au32[3],
1936 pZmm16Hi->aRegs[i].au32[2],
1937 pZmm16Hi->aRegs[i].au32[1],
1938 pZmm16Hi->aRegs[i].au32[0]);
1939 }
1940 }
1941 else
1942 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1943 pHlp->pfnPrintf(pHlp,
1944 i & 1
1945 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
1946 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
1947 pszPrefix, i, i < 10 ? " " : "",
1948 pFpuCtx->aXMM[i].au32[3],
1949 pFpuCtx->aXMM[i].au32[2],
1950 pFpuCtx->aXMM[i].au32[1],
1951 pFpuCtx->aXMM[i].au32[0]);
1952
1953 if (pCtx->fXStateMask & XSAVE_C_OPMASK)
1954 {
1955 PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
1956 for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
1957 pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
1958 pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
1959 pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
1960 pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
1961 pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
1962 }
1963
1964 if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
1965 {
1966 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1967 for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
1968 pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
1969 pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
1970 pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
1971 }
1972
1973 if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
1974 {
1975 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1976 pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
1977 pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
1978 }
1979
1980 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
1981 if (pFpuCtx->au32RsrvdRest[i])
1982 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
1983 pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
1984 }
1985
1986 pHlp->pfnPrintf(pHlp,
1987 "%sEFER =%016RX64\n"
1988 "%sPAT =%016RX64\n"
1989 "%sSTAR =%016RX64\n"
1990 "%sCSTAR =%016RX64\n"
1991 "%sLSTAR =%016RX64\n"
1992 "%sSFMASK =%016RX64\n"
1993 "%sKERNELGSBASE =%016RX64\n",
1994 pszPrefix, pCtx->msrEFER,
1995 pszPrefix, pCtx->msrPAT,
1996 pszPrefix, pCtx->msrSTAR,
1997 pszPrefix, pCtx->msrCSTAR,
1998 pszPrefix, pCtx->msrLSTAR,
1999 pszPrefix, pCtx->msrSFMASK,
2000 pszPrefix, pCtx->msrKERNELGSBASE);
2001 break;
2002 }
2003}
2004
2005
2006/**
2007 * Display all cpu states and any other cpum info.
2008 *
2009 * @param pVM The cross context VM structure.
2010 * @param pHlp The info helper functions.
2011 * @param pszArgs Arguments, ignored.
2012 */
2013static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2014{
2015 cpumR3InfoGuest(pVM, pHlp, pszArgs);
2016 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2017 cpumR3InfoHyper(pVM, pHlp, pszArgs);
2018 cpumR3InfoHost(pVM, pHlp, pszArgs);
2019}
2020
2021
2022/**
2023 * Parses the info argument.
2024 *
2025 * The argument starts with 'verbose', 'terse' or 'default' and then
2026 * continues with the comment string.
2027 *
2028 * @param pszArgs The pointer to the argument string.
2029 * @param penmType Where to store the dump type request.
2030 * @param ppszComment Where to store the pointer to the comment string.
2031 */
2032static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
2033{
2034 if (!pszArgs)
2035 {
2036 *penmType = CPUMDUMPTYPE_DEFAULT;
2037 *ppszComment = "";
2038 }
2039 else
2040 {
2041 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
2042 {
2043 pszArgs += 7;
2044 *penmType = CPUMDUMPTYPE_VERBOSE;
2045 }
2046 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
2047 {
2048 pszArgs += 5;
2049 *penmType = CPUMDUMPTYPE_TERSE;
2050 }
2051 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
2052 {
2053 pszArgs += 7;
2054 *penmType = CPUMDUMPTYPE_DEFAULT;
2055 }
2056 else
2057 *penmType = CPUMDUMPTYPE_DEFAULT;
2058 *ppszComment = RTStrStripL(pszArgs);
2059 }
2060}
2061
2062
2063/**
2064 * Display the guest cpu state.
2065 *
2066 * @param pVM The cross context VM structure.
2067 * @param pHlp The info helper functions.
2068 * @param pszArgs Arguments, ignored.
2069 */
2070static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2071{
2072 CPUMDUMPTYPE enmType;
2073 const char *pszComment;
2074 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2075
2076 PVMCPU pVCpu = VMMGetCpu(pVM);
2077 if (!pVCpu)
2078 pVCpu = &pVM->aCpus[0];
2079
2080 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2081
2082 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2083 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2084}
2085
2086
2087/**
2088 * Display the current guest instruction
2089 *
2090 * @param pVM The cross context VM structure.
2091 * @param pHlp The info helper functions.
2092 * @param pszArgs Arguments, ignored.
2093 */
2094static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2095{
2096 NOREF(pszArgs);
2097
2098 PVMCPU pVCpu = VMMGetCpu(pVM);
2099 if (!pVCpu)
2100 pVCpu = &pVM->aCpus[0];
2101
2102 char szInstruction[256];
2103 szInstruction[0] = '\0';
2104 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2105 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2106}
2107
2108
2109/**
2110 * Display the hypervisor cpu state.
2111 *
2112 * @param pVM The cross context VM structure.
2113 * @param pHlp The info helper functions.
2114 * @param pszArgs Arguments, ignored.
2115 */
2116static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2117{
2118 PVMCPU pVCpu = VMMGetCpu(pVM);
2119 if (!pVCpu)
2120 pVCpu = &pVM->aCpus[0];
2121
2122 CPUMDUMPTYPE enmType;
2123 const char *pszComment;
2124 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2125 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2126 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
2127 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2128}
2129
2130
2131/**
2132 * Display the host cpu state.
2133 *
2134 * @param pVM The cross context VM structure.
2135 * @param pHlp The info helper functions.
2136 * @param pszArgs Arguments, ignored.
2137 */
2138static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2139{
2140 CPUMDUMPTYPE enmType;
2141 const char *pszComment;
2142 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2143 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2144
2145 PVMCPU pVCpu = VMMGetCpu(pVM);
2146 if (!pVCpu)
2147 pVCpu = &pVM->aCpus[0];
2148 PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
2149
2150 /*
2151 * Format the EFLAGS.
2152 */
2153#if HC_ARCH_BITS == 32
2154 uint32_t efl = pCtx->eflags.u32;
2155#else
2156 uint64_t efl = pCtx->rflags;
2157#endif
2158 char szEFlags[80];
2159 cpumR3InfoFormatFlags(&szEFlags[0], efl);
2160
2161 /*
2162 * Format the registers.
2163 */
2164#if HC_ARCH_BITS == 32
2165 pHlp->pfnPrintf(pHlp,
2166 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2167 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2168 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2169 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2170 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2171 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2172 ,
2173 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
2174 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2175 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2176 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
2177 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2178 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
2179 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2180#else
2181 pHlp->pfnPrintf(pHlp,
2182 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2183 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2184 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2185 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2186 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2187 "r14=%016RX64 r15=%016RX64\n"
2188 "iopl=%d %31s\n"
2189 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2190 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2191 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
2192 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2193 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2194 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2195 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2196 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2197 ,
2198 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
2199 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2200 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
2201 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
2202 pCtx->r11, pCtx->r12, pCtx->r13,
2203 pCtx->r14, pCtx->r15,
2204 X86_EFL_GET_IOPL(efl), szEFlags,
2205 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2206 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
2207 pCtx->cr4, pCtx->ldtr, pCtx->tr,
2208 pCtx->dr0, pCtx->dr1, pCtx->dr2,
2209 pCtx->dr3, pCtx->dr6, pCtx->dr7,
2210 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2211 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2212 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2213#endif
2214}
2215
2216/**
2217 * Structure used when disassembling and instructions in DBGF.
2218 * This is used so the reader function can get the stuff it needs.
2219 */
2220typedef struct CPUMDISASSTATE
2221{
2222 /** Pointer to the CPU structure. */
2223 PDISCPUSTATE pCpu;
2224 /** Pointer to the VM. */
2225 PVM pVM;
2226 /** Pointer to the VMCPU. */
2227 PVMCPU pVCpu;
2228 /** Pointer to the first byte in the segment. */
2229 RTGCUINTPTR GCPtrSegBase;
2230 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2231 RTGCUINTPTR GCPtrSegEnd;
2232 /** The size of the segment minus 1. */
2233 RTGCUINTPTR cbSegLimit;
2234 /** Pointer to the current page - R3 Ptr. */
2235 void const *pvPageR3;
2236 /** Pointer to the current page - GC Ptr. */
2237 RTGCPTR pvPageGC;
2238 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2239 PGMPAGEMAPLOCK PageMapLock;
2240 /** Whether the PageMapLock is valid or not. */
2241 bool fLocked;
2242 /** 64 bits mode or not. */
2243 bool f64Bits;
2244} CPUMDISASSTATE, *PCPUMDISASSTATE;
2245
2246
2247/**
2248 * @callback_method_impl{FNDISREADBYTES}
2249 */
2250static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
2251{
2252 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
2253 for (;;)
2254 {
2255 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
2256
2257 /*
2258 * Need to update the page translation?
2259 */
2260 if ( !pState->pvPageR3
2261 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2262 {
2263 int rc = VINF_SUCCESS;
2264
2265 /* translate the address */
2266 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2267 if ( !HMIsEnabled(pState->pVM)
2268 && MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
2269 {
2270 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2271 if (!pState->pvPageR3)
2272 rc = VERR_INVALID_POINTER;
2273 }
2274 else
2275 {
2276 /* Release mapping lock previously acquired. */
2277 if (pState->fLocked)
2278 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2279 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2280 pState->fLocked = RT_SUCCESS_NP(rc);
2281 }
2282 if (RT_FAILURE(rc))
2283 {
2284 pState->pvPageR3 = NULL;
2285 return rc;
2286 }
2287 }
2288
2289 /*
2290 * Check the segment limit.
2291 */
2292 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
2293 return VERR_OUT_OF_SELECTOR_BOUNDS;
2294
2295 /*
2296 * Calc how much we can read.
2297 */
2298 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2299 if (!pState->f64Bits)
2300 {
2301 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2302 if (cb > cbSeg && cbSeg)
2303 cb = cbSeg;
2304 }
2305 if (cb > cbMaxRead)
2306 cb = cbMaxRead;
2307
2308 /*
2309 * Read and advance or exit.
2310 */
2311 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2312 offInstr += (uint8_t)cb;
2313 if (cb >= cbMinRead)
2314 {
2315 pDis->cbCachedInstr = offInstr;
2316 return VINF_SUCCESS;
2317 }
2318 cbMinRead -= (uint8_t)cb;
2319 cbMaxRead -= (uint8_t)cb;
2320 }
2321}
2322
2323
2324/**
2325 * Disassemble an instruction and return the information in the provided structure.
2326 *
2327 * @returns VBox status code.
2328 * @param pVM The cross context VM structure.
2329 * @param pVCpu The cross context virtual CPU structure.
2330 * @param pCtx Pointer to the guest CPU context.
2331 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2332 * @param pCpu Disassembly state.
2333 * @param pszPrefix String prefix for logging (debug only).
2334 *
2335 */
2336VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
2337 const char *pszPrefix)
2338{
2339 CPUMDISASSTATE State;
2340 int rc;
2341
2342 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2343 State.pCpu = pCpu;
2344 State.pvPageGC = 0;
2345 State.pvPageR3 = NULL;
2346 State.pVM = pVM;
2347 State.pVCpu = pVCpu;
2348 State.fLocked = false;
2349 State.f64Bits = false;
2350
2351 /*
2352 * Get selector information.
2353 */
2354 DISCPUMODE enmDisCpuMode;
2355 if ( (pCtx->cr0 & X86_CR0_PE)
2356 && pCtx->eflags.Bits.u1VM == 0)
2357 {
2358 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2359 {
2360# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2361 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
2362# endif
2363 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2364 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
2365 }
2366 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
2367 State.GCPtrSegBase = pCtx->cs.u64Base;
2368 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
2369 State.cbSegLimit = pCtx->cs.u32Limit;
2370 enmDisCpuMode = (State.f64Bits)
2371 ? DISCPUMODE_64BIT
2372 : pCtx->cs.Attr.n.u1DefBig
2373 ? DISCPUMODE_32BIT
2374 : DISCPUMODE_16BIT;
2375 }
2376 else
2377 {
2378 /* real or V86 mode */
2379 enmDisCpuMode = DISCPUMODE_16BIT;
2380 State.GCPtrSegBase = pCtx->cs.Sel * 16;
2381 State.GCPtrSegEnd = 0xFFFFFFFF;
2382 State.cbSegLimit = 0xFFFFFFFF;
2383 }
2384
2385 /*
2386 * Disassemble the instruction.
2387 */
2388 uint32_t cbInstr;
2389#ifndef LOG_ENABLED
2390 RT_NOREF_PV(pszPrefix);
2391 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
2392 if (RT_SUCCESS(rc))
2393 {
2394#else
2395 char szOutput[160];
2396 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
2397 pCpu, &cbInstr, szOutput, sizeof(szOutput));
2398 if (RT_SUCCESS(rc))
2399 {
2400 /* log it */
2401 if (pszPrefix)
2402 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2403 else
2404 Log(("%s", szOutput));
2405#endif
2406 rc = VINF_SUCCESS;
2407 }
2408 else
2409 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
2410
2411 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2412 if (State.fLocked)
2413 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2414
2415 return rc;
2416}
2417
2418
2419
2420/**
2421 * API for controlling a few of the CPU features found in CR4.
2422 *
2423 * Currently only X86_CR4_TSD is accepted as input.
2424 *
2425 * @returns VBox status code.
2426 *
2427 * @param pVM The cross context VM structure.
2428 * @param fOr The CR4 OR mask.
2429 * @param fAnd The CR4 AND mask.
2430 */
2431VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2432{
2433 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2434 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2435
2436 pVM->cpum.s.CR4.OrMask &= fAnd;
2437 pVM->cpum.s.CR4.OrMask |= fOr;
2438
2439 return VINF_SUCCESS;
2440}
2441
2442
2443/**
2444 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
2445 *
2446 * Only REM should ever call this function!
2447 *
2448 * @returns The changed flags.
2449 * @param pVCpu The cross context virtual CPU structure.
2450 * @param puCpl Where to return the current privilege level (CPL).
2451 */
2452VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
2453{
2454 Assert(!pVCpu->cpum.s.fRawEntered);
2455 Assert(!pVCpu->cpum.s.fRemEntered);
2456
2457 /*
2458 * Get the CPL first.
2459 */
2460 *puCpl = CPUMGetGuestCPL(pVCpu);
2461
2462 /*
2463 * Get and reset the flags.
2464 */
2465 uint32_t fFlags = pVCpu->cpum.s.fChanged;
2466 pVCpu->cpum.s.fChanged = 0;
2467
2468 /** @todo change the switcher to use the fChanged flags. */
2469 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
2470 {
2471 fFlags |= CPUM_CHANGED_FPU_REM;
2472 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
2473 }
2474
2475 pVCpu->cpum.s.fRemEntered = true;
2476 return fFlags;
2477}
2478
2479
2480/**
2481 * Leaves REM.
2482 *
2483 * @param pVCpu The cross context virtual CPU structure.
2484 * @param fNoOutOfSyncSels This is @c false if there are out of sync
2485 * registers.
2486 */
2487VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
2488{
2489 Assert(!pVCpu->cpum.s.fRawEntered);
2490 Assert(pVCpu->cpum.s.fRemEntered);
2491
2492 RT_NOREF_PV(fNoOutOfSyncSels);
2493
2494 pVCpu->cpum.s.fRemEntered = false;
2495}
2496
2497
2498/**
2499 * Called when the ring-3 init phase completes.
2500 *
2501 * @returns VBox status code.
2502 * @param pVM The cross context VM structure.
2503 * @param enmWhat Which init phase.
2504 */
2505VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
2506{
2507 switch (enmWhat)
2508 {
2509 case VMINITCOMPLETED_RING3:
2510 {
2511 /*
2512 * Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
2513 * Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
2514 */
2515 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2516 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2517 {
2518 PVMCPU pVCpu = &pVM->aCpus[i];
2519 /* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
2520 if (fSupportsLongMode)
2521 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
2522 }
2523
2524 cpumR3MsrRegStats(pVM);
2525 break;
2526 }
2527
2528 case VMINITCOMPLETED_RING0:
2529 {
2530 /* Cache the APIC base (from the APIC device) once it has been initialized. */
2531 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2532 {
2533 PVMCPU pVCpu = &pVM->aCpus[i];
2534 PDMApicGetBaseMsr(pVCpu, &pVCpu->cpum.s.Guest.msrApicBase, true /* fIgnoreErrors */);
2535#ifdef VBOX_WITH_NEW_APIC
2536 LogRel(("CPUM: VCPU%3d: Cached APIC base MSR = %#RX64\n", i, pVCpu->cpum.s.Guest.msrApicBase));
2537#endif
2538 }
2539 break;
2540 }
2541
2542 default:
2543 break;
2544 }
2545 return VINF_SUCCESS;
2546}
2547
2548
2549/**
2550 * Called when the ring-0 init phases completed.
2551 *
2552 * @param pVM The cross context VM structure.
2553 */
2554VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
2555{
2556 /*
2557 * Log the cpuid.
2558 */
2559 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
2560 RTCPUSET OnlineSet;
2561 LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
2562 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
2563 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
2564 RTCPUID cCores = RTMpGetCoreCount();
2565 if (cCores)
2566 LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
2567 LogRel(("************************* CPUID dump ************************\n"));
2568 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
2569 LogRel(("\n"));
2570 DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
2571 RTLogRelSetBuffering(fOldBuffered);
2572 LogRel(("******************** End of CPUID dump **********************\n"));
2573}
2574
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette