VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 61128

Last change on this file since 61128 was 61128, checked in by vboxsync, 8 years ago

CPUM: Slightly improved FPU state printing.
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1/* $Id: CPUM.cpp 61128 2016-05-23 11:39:38Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 */
33
34
35/*********************************************************************************************************************************
36* Header Files *
37*********************************************************************************************************************************/
38#define LOG_GROUP LOG_GROUP_CPUM
39#include <VBox/vmm/cpum.h>
40#include <VBox/vmm/cpumdis.h>
41#include <VBox/vmm/cpumctx-v1_6.h>
42#include <VBox/vmm/pgm.h>
43#include <VBox/vmm/pdmapi.h>
44#include <VBox/vmm/mm.h>
45#include <VBox/vmm/em.h>
46#include <VBox/vmm/selm.h>
47#include <VBox/vmm/dbgf.h>
48#include <VBox/vmm/patm.h>
49#include <VBox/vmm/hm.h>
50#include <VBox/vmm/ssm.h>
51#include "CPUMInternal.h"
52#include <VBox/vmm/vm.h>
53
54#include <VBox/param.h>
55#include <VBox/dis.h>
56#include <VBox/err.h>
57#include <VBox/log.h>
58#include <iprt/asm-amd64-x86.h>
59#include <iprt/assert.h>
60#include <iprt/cpuset.h>
61#include <iprt/mem.h>
62#include <iprt/mp.h>
63#include <iprt/string.h>
64#include "internal/pgm.h"
65
66
67/*********************************************************************************************************************************
68* Defined Constants And Macros *
69*********************************************************************************************************************************/
70/**
71 * This was used in the saved state up to the early life of version 14.
72 *
73 * It indicates that we may have some out-of-sync hidden segement registers.
74 * It is only relevant for raw-mode.
75 */
76#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
77
78
79/*********************************************************************************************************************************
80* Structures and Typedefs *
81*********************************************************************************************************************************/
82
83/**
84 * What kind of cpu info dump to perform.
85 */
86typedef enum CPUMDUMPTYPE
87{
88 CPUMDUMPTYPE_TERSE,
89 CPUMDUMPTYPE_DEFAULT,
90 CPUMDUMPTYPE_VERBOSE
91} CPUMDUMPTYPE;
92/** Pointer to a cpu info dump type. */
93typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
94
95
96/*********************************************************************************************************************************
97* Internal Functions *
98*********************************************************************************************************************************/
99static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
100static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
101static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
102static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
103static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
104static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109
110
111/*********************************************************************************************************************************
112* Global Variables *
113*********************************************************************************************************************************/
114/** Saved state field descriptors for CPUMCTX. */
115static const SSMFIELD g_aCpumCtxFields[] =
116{
117 SSMFIELD_ENTRY( CPUMCTX, rdi),
118 SSMFIELD_ENTRY( CPUMCTX, rsi),
119 SSMFIELD_ENTRY( CPUMCTX, rbp),
120 SSMFIELD_ENTRY( CPUMCTX, rax),
121 SSMFIELD_ENTRY( CPUMCTX, rbx),
122 SSMFIELD_ENTRY( CPUMCTX, rdx),
123 SSMFIELD_ENTRY( CPUMCTX, rcx),
124 SSMFIELD_ENTRY( CPUMCTX, rsp),
125 SSMFIELD_ENTRY( CPUMCTX, rflags),
126 SSMFIELD_ENTRY( CPUMCTX, rip),
127 SSMFIELD_ENTRY( CPUMCTX, r8),
128 SSMFIELD_ENTRY( CPUMCTX, r9),
129 SSMFIELD_ENTRY( CPUMCTX, r10),
130 SSMFIELD_ENTRY( CPUMCTX, r11),
131 SSMFIELD_ENTRY( CPUMCTX, r12),
132 SSMFIELD_ENTRY( CPUMCTX, r13),
133 SSMFIELD_ENTRY( CPUMCTX, r14),
134 SSMFIELD_ENTRY( CPUMCTX, r15),
135 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
136 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
137 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
138 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
139 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
140 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
141 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
142 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
143 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
144 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
145 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
146 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
147 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
148 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
149 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
150 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
151 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
152 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
153 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
154 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
155 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
156 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
157 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
158 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
159 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
160 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
161 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
162 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
163 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
164 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
165 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
166 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
167 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
168 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
169 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
170 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
171 SSMFIELD_ENTRY( CPUMCTX, cr0),
172 SSMFIELD_ENTRY( CPUMCTX, cr2),
173 SSMFIELD_ENTRY( CPUMCTX, cr3),
174 SSMFIELD_ENTRY( CPUMCTX, cr4),
175 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
176 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
177 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
178 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
179 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
180 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
181 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
182 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
183 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
184 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
185 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
186 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
187 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
188 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
189 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
190 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
191 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
192 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
193 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
194 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
195 /* msrApicBase is not included here, it resides in the APIC device state. */
196 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
197 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
198 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
199 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
200 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
201 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
202 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
203 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
204 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
205 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
206 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
207 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
208 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
209 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
210 SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
211 SSMFIELD_ENTRY_TERM()
212};
213
214/** Saved state field descriptors for CPUMCTX. */
215static const SSMFIELD g_aCpumX87Fields[] =
216{
217 SSMFIELD_ENTRY( X86FXSTATE, FCW),
218 SSMFIELD_ENTRY( X86FXSTATE, FSW),
219 SSMFIELD_ENTRY( X86FXSTATE, FTW),
220 SSMFIELD_ENTRY( X86FXSTATE, FOP),
221 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
222 SSMFIELD_ENTRY( X86FXSTATE, CS),
223 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
224 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
225 SSMFIELD_ENTRY( X86FXSTATE, DS),
226 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
227 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
228 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
229 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
230 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
231 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
232 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
233 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
234 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
235 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
236 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
237 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
238 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
239 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
240 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
241 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
242 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
243 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
244 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
245 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
246 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
247 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
248 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
249 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
250 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
251 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
252 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
253 SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
254 SSMFIELD_ENTRY_TERM()
255};
256
257/** Saved state field descriptors for X86XSAVEHDR. */
258static const SSMFIELD g_aCpumXSaveHdrFields[] =
259{
260 SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
261 SSMFIELD_ENTRY_TERM()
262};
263
264/** Saved state field descriptors for X86XSAVEYMMHI. */
265static const SSMFIELD g_aCpumYmmHiFields[] =
266{
267 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
268 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
269 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
270 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
271 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
272 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
273 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
274 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
275 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
276 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
277 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
278 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
279 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
280 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
281 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
282 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
283 SSMFIELD_ENTRY_TERM()
284};
285
286/** Saved state field descriptors for X86XSAVEBNDREGS. */
287static const SSMFIELD g_aCpumBndRegsFields[] =
288{
289 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
290 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
291 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
292 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
293 SSMFIELD_ENTRY_TERM()
294};
295
296/** Saved state field descriptors for X86XSAVEBNDCFG. */
297static const SSMFIELD g_aCpumBndCfgFields[] =
298{
299 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
300 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
301 SSMFIELD_ENTRY_TERM()
302};
303
304/** Saved state field descriptors for X86XSAVEOPMASK. */
305static const SSMFIELD g_aCpumOpmaskFields[] =
306{
307 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
308 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
309 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
310 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
311 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
312 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
313 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
314 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
315 SSMFIELD_ENTRY_TERM()
316};
317
318/** Saved state field descriptors for X86XSAVEZMMHI256. */
319static const SSMFIELD g_aCpumZmmHi256Fields[] =
320{
321 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
322 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
323 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
324 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
325 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
326 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
327 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
328 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
329 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
330 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
331 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
332 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
333 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
334 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
335 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
336 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
337 SSMFIELD_ENTRY_TERM()
338};
339
340/** Saved state field descriptors for X86XSAVEZMM16HI. */
341static const SSMFIELD g_aCpumZmm16HiFields[] =
342{
343 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
344 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
345 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
346 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
347 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
348 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
349 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
350 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
351 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
352 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
353 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
354 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
355 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
356 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
357 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
358 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
359 SSMFIELD_ENTRY_TERM()
360};
361
362
363
364/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
365 * registeres changed. */
366static const SSMFIELD g_aCpumX87FieldsMem[] =
367{
368 SSMFIELD_ENTRY( X86FXSTATE, FCW),
369 SSMFIELD_ENTRY( X86FXSTATE, FSW),
370 SSMFIELD_ENTRY( X86FXSTATE, FTW),
371 SSMFIELD_ENTRY( X86FXSTATE, FOP),
372 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
373 SSMFIELD_ENTRY( X86FXSTATE, CS),
374 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
375 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
376 SSMFIELD_ENTRY( X86FXSTATE, DS),
377 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
378 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
379 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
380 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
381 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
382 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
383 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
384 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
385 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
386 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
387 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
388 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
389 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
390 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
391 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
392 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
393 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
394 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
395 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
396 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
397 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
398 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
399 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
400 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
401 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
402 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
403 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
404 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
405 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
406};
407
408/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
409 * registeres changed. */
410static const SSMFIELD g_aCpumCtxFieldsMem[] =
411{
412 SSMFIELD_ENTRY( CPUMCTX, rdi),
413 SSMFIELD_ENTRY( CPUMCTX, rsi),
414 SSMFIELD_ENTRY( CPUMCTX, rbp),
415 SSMFIELD_ENTRY( CPUMCTX, rax),
416 SSMFIELD_ENTRY( CPUMCTX, rbx),
417 SSMFIELD_ENTRY( CPUMCTX, rdx),
418 SSMFIELD_ENTRY( CPUMCTX, rcx),
419 SSMFIELD_ENTRY( CPUMCTX, rsp),
420 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
421 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
422 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
423 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
424 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
425 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
426 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
427 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
428 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
429 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
430 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
431 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
432 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
433 SSMFIELD_ENTRY( CPUMCTX, rflags),
434 SSMFIELD_ENTRY( CPUMCTX, rip),
435 SSMFIELD_ENTRY( CPUMCTX, r8),
436 SSMFIELD_ENTRY( CPUMCTX, r9),
437 SSMFIELD_ENTRY( CPUMCTX, r10),
438 SSMFIELD_ENTRY( CPUMCTX, r11),
439 SSMFIELD_ENTRY( CPUMCTX, r12),
440 SSMFIELD_ENTRY( CPUMCTX, r13),
441 SSMFIELD_ENTRY( CPUMCTX, r14),
442 SSMFIELD_ENTRY( CPUMCTX, r15),
443 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
444 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
445 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
446 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
447 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
448 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
449 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
450 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
451 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
452 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
453 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
454 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
455 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
456 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
457 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
458 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
459 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
460 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
461 SSMFIELD_ENTRY( CPUMCTX, cr0),
462 SSMFIELD_ENTRY( CPUMCTX, cr2),
463 SSMFIELD_ENTRY( CPUMCTX, cr3),
464 SSMFIELD_ENTRY( CPUMCTX, cr4),
465 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
466 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
467 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
468 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
469 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
470 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
471 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
472 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
473 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
474 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
475 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
476 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
477 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
478 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
479 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
480 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
481 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
482 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
483 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
484 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
485 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
486 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
487 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
488 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
489 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
490 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
491 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
492 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
493 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
494 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
495 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
496 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
497 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
498 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
499 SSMFIELD_ENTRY_TERM()
500};
501
502/** Saved state field descriptors for CPUMCTX_VER1_6. */
503static const SSMFIELD g_aCpumX87FieldsV16[] =
504{
505 SSMFIELD_ENTRY( X86FXSTATE, FCW),
506 SSMFIELD_ENTRY( X86FXSTATE, FSW),
507 SSMFIELD_ENTRY( X86FXSTATE, FTW),
508 SSMFIELD_ENTRY( X86FXSTATE, FOP),
509 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
510 SSMFIELD_ENTRY( X86FXSTATE, CS),
511 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
512 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
513 SSMFIELD_ENTRY( X86FXSTATE, DS),
514 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
515 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
516 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
517 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
518 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
519 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
520 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
521 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
522 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
523 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
524 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
525 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
526 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
527 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
528 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
529 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
530 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
531 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
532 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
533 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
534 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
535 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
536 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
537 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
538 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
539 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
540 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
541 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
542 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
543 SSMFIELD_ENTRY_TERM()
544};
545
546/** Saved state field descriptors for CPUMCTX_VER1_6. */
547static const SSMFIELD g_aCpumCtxFieldsV16[] =
548{
549 SSMFIELD_ENTRY( CPUMCTX, rdi),
550 SSMFIELD_ENTRY( CPUMCTX, rsi),
551 SSMFIELD_ENTRY( CPUMCTX, rbp),
552 SSMFIELD_ENTRY( CPUMCTX, rax),
553 SSMFIELD_ENTRY( CPUMCTX, rbx),
554 SSMFIELD_ENTRY( CPUMCTX, rdx),
555 SSMFIELD_ENTRY( CPUMCTX, rcx),
556 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
557 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
558 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
559 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
560 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
561 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
562 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
563 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
564 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
565 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
566 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
567 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
568 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
569 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
570 SSMFIELD_ENTRY( CPUMCTX, rflags),
571 SSMFIELD_ENTRY( CPUMCTX, rip),
572 SSMFIELD_ENTRY( CPUMCTX, r8),
573 SSMFIELD_ENTRY( CPUMCTX, r9),
574 SSMFIELD_ENTRY( CPUMCTX, r10),
575 SSMFIELD_ENTRY( CPUMCTX, r11),
576 SSMFIELD_ENTRY( CPUMCTX, r12),
577 SSMFIELD_ENTRY( CPUMCTX, r13),
578 SSMFIELD_ENTRY( CPUMCTX, r14),
579 SSMFIELD_ENTRY( CPUMCTX, r15),
580 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
581 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
582 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
583 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
584 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
585 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
586 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
587 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
588 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
589 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
590 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
591 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
592 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
593 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
594 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
595 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
596 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
597 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
598 SSMFIELD_ENTRY( CPUMCTX, cr0),
599 SSMFIELD_ENTRY( CPUMCTX, cr2),
600 SSMFIELD_ENTRY( CPUMCTX, cr3),
601 SSMFIELD_ENTRY( CPUMCTX, cr4),
602 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
603 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
604 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
605 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
606 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
607 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
608 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
609 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
610 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
611 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
612 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
613 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
614 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
615 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
616 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
617 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
618 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
619 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
620 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
621 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
622 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
623 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
624 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
625 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
626 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
627 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
628 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
629 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
630 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
631 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
632 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
633 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
634 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
635 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
636 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
637 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
638 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
639 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
640 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
641 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
642 SSMFIELD_ENTRY_TERM()
643};
644
645
646/**
647 * Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
648 *
649 * AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
650 * (last instruction pointer, last data pointer, last opcode) except when the ES
651 * bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
652 * clear these registers there is potential, local FPU leakage from a process
653 * using the FPU to another.
654 *
655 * See AMD Instruction Reference for FXSAVE, FXRSTOR.
656 *
657 * @param pVM The cross context VM structure.
658 */
659static void cpumR3CheckLeakyFpu(PVM pVM)
660{
661 uint32_t u32CpuVersion = ASMCpuId_EAX(1);
662 uint32_t const u32Family = u32CpuVersion >> 8;
663 if ( u32Family >= 6 /* K7 and higher */
664 && ASMIsAmdCpu())
665 {
666 uint32_t cExt = ASMCpuId_EAX(0x80000000);
667 if (ASMIsValidExtRange(cExt))
668 {
669 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
670 if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
671 {
672 for (VMCPUID i = 0; i < pVM->cCpus; i++)
673 pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_FFXSR_LEAKY;
674 Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
675 }
676 }
677 }
678}
679
680
681/**
682 * Initializes the CPUM.
683 *
684 * @returns VBox status code.
685 * @param pVM The cross context VM structure.
686 */
687VMMR3DECL(int) CPUMR3Init(PVM pVM)
688{
689 LogFlow(("CPUMR3Init\n"));
690
691 /*
692 * Assert alignment, sizes and tables.
693 */
694 AssertCompileMemberAlignment(VM, cpum.s, 32);
695 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
696 AssertCompileSizeAlignment(CPUMCTX, 64);
697 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
698 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
699 AssertCompileMemberAlignment(VM, cpum, 64);
700 AssertCompileMemberAlignment(VM, aCpus, 64);
701 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
702 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
703#ifdef VBOX_STRICT
704 int rc2 = cpumR3MsrStrictInitChecks();
705 AssertRCReturn(rc2, rc2);
706#endif
707
708 /*
709 * Initialize offsets.
710 */
711
712 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
713 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
714 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
715
716
717 /* Calculate the offset from CPUMCPU to CPUM. */
718 for (VMCPUID i = 0; i < pVM->cCpus; i++)
719 {
720 PVMCPU pVCpu = &pVM->aCpus[i];
721
722 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
723 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
724 }
725
726 /*
727 * Gather info about the host CPU.
728 */
729 if (!ASMHasCpuId())
730 {
731 Log(("The CPU doesn't support CPUID!\n"));
732 return VERR_UNSUPPORTED_CPU;
733 }
734
735 PCPUMCPUIDLEAF paLeaves;
736 uint32_t cLeaves;
737 int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
738 AssertLogRelRCReturn(rc, rc);
739
740 rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
741 RTMemFree(paLeaves);
742 AssertLogRelRCReturn(rc, rc);
743 pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
744
745 /*
746 * Check that the CPU supports the minimum features we require.
747 */
748 if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
749 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
750 if (!pVM->cpum.s.HostFeatures.fMmx)
751 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
752 if (!pVM->cpum.s.HostFeatures.fTsc)
753 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
754
755 /*
756 * Setup the CR4 AND and OR masks used in the raw-mode switcher.
757 */
758 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
759 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
760
761 /*
762 * Figure out which XSAVE/XRSTOR features are available on the host.
763 */
764 uint64_t fXcr0Host = 0;
765 uint64_t fXStateHostMask = 0;
766 if ( pVM->cpum.s.HostFeatures.fXSaveRstor
767 && pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
768 {
769 fXStateHostMask = fXcr0Host = ASMGetXcr0();
770 fXStateHostMask &= XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI;
771 AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 | XSAVE_C_SSE)) == (XSAVE_C_X87 | XSAVE_C_SSE),
772 ("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
773 }
774 pVM->cpum.s.fXStateHostMask = fXStateHostMask;
775 if (!HMIsEnabled(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
776 fXStateHostMask = 0;
777 LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
778 pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
779
780 /*
781 * Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
782 */
783 uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
784 cbMaxXState = RT_ALIGN(cbMaxXState, 128);
785 AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
786
787 uint8_t *pbXStates;
788 rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
789 MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
790 AssertLogRelRCReturn(rc, rc);
791
792 for (VMCPUID i = 0; i < pVM->cCpus; i++)
793 {
794 PVMCPU pVCpu = &pVM->aCpus[i];
795
796 pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
797 pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
798 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
799 pbXStates += cbMaxXState;
800
801 pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
802 pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
803 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
804 pbXStates += cbMaxXState;
805
806 pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
807 pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
808 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
809 pbXStates += cbMaxXState;
810
811 pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
812 }
813
814 /*
815 * Setup hypervisor startup values.
816 */
817
818 /*
819 * Register saved state data item.
820 */
821 rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
822 NULL, cpumR3LiveExec, NULL,
823 NULL, cpumR3SaveExec, NULL,
824 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
825 if (RT_FAILURE(rc))
826 return rc;
827
828 /*
829 * Register info handlers and registers with the debugger facility.
830 */
831 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
832 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
833 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
834 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
835 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
836 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
837
838 rc = cpumR3DbgInit(pVM);
839 if (RT_FAILURE(rc))
840 return rc;
841
842 /*
843 * Check if we need to workaround partial/leaky FPU handling.
844 */
845 cpumR3CheckLeakyFpu(pVM);
846
847 /*
848 * Initialize the Guest CPUID and MSR states.
849 */
850 rc = cpumR3InitCpuIdAndMsrs(pVM);
851 if (RT_FAILURE(rc))
852 return rc;
853 CPUMR3Reset(pVM);
854 return VINF_SUCCESS;
855}
856
857
858/**
859 * Applies relocations to data and code managed by this
860 * component. This function will be called at init and
861 * whenever the VMM need to relocate it self inside the GC.
862 *
863 * The CPUM will update the addresses used by the switcher.
864 *
865 * @param pVM The cross context VM structure.
866 */
867VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
868{
869 LogFlow(("CPUMR3Relocate\n"));
870
871 pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
872 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
873
874 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
875 {
876 PVMCPU pVCpu = &pVM->aCpus[iCpu];
877 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
878 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
879 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
880
881 /* Recheck the guest DRx values in raw-mode. */
882 CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
883 }
884}
885
886
887/**
888 * Apply late CPUM property changes based on the fHWVirtEx setting
889 *
890 * @param pVM The cross context VM structure.
891 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
892 */
893VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
894{
895 /*
896 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
897 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
898 * of processors from (cpuid(4).eax >> 26) + 1.
899 *
900 * Note: this code is obsolete, but let's keep it here for reference.
901 * Purpose is valid when we artificially cap the max std id to less than 4.
902 */
903 if (!fHWVirtExEnabled)
904 {
905 Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
906 || pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
907 pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
908 }
909}
910
911/**
912 * Terminates the CPUM.
913 *
914 * Termination means cleaning up and freeing all resources,
915 * the VM it self is at this point powered off or suspended.
916 *
917 * @returns VBox status code.
918 * @param pVM The cross context VM structure.
919 */
920VMMR3DECL(int) CPUMR3Term(PVM pVM)
921{
922#ifdef VBOX_WITH_CRASHDUMP_MAGIC
923 for (VMCPUID i = 0; i < pVM->cCpus; i++)
924 {
925 PVMCPU pVCpu = &pVM->aCpus[i];
926 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
927
928 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
929 pVCpu->cpum.s.uMagic = 0;
930 pCtx->dr[5] = 0;
931 }
932#else
933 NOREF(pVM);
934#endif
935 return VINF_SUCCESS;
936}
937
938
939/**
940 * Resets a virtual CPU.
941 *
942 * Used by CPUMR3Reset and CPU hot plugging.
943 *
944 * @param pVM The cross context VM structure.
945 * @param pVCpu The cross context virtual CPU structure of the CPU that is
946 * being reset. This may differ from the current EMT.
947 */
948VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
949{
950 /** @todo anything different for VCPU > 0? */
951 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
952
953 /*
954 * Initialize everything to ZERO first.
955 */
956 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
957
958 AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
959 AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
960 memset(pCtx, 0, RT_OFFSETOF(CPUMCTX, pXStateR0));
961
962 pVCpu->cpum.s.fUseFlags = fUseFlags;
963
964 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
965 pCtx->eip = 0x0000fff0;
966 pCtx->edx = 0x00000600; /* P6 processor */
967 pCtx->eflags.Bits.u1Reserved0 = 1;
968
969 pCtx->cs.Sel = 0xf000;
970 pCtx->cs.ValidSel = 0xf000;
971 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
972 pCtx->cs.u64Base = UINT64_C(0xffff0000);
973 pCtx->cs.u32Limit = 0x0000ffff;
974 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
975 pCtx->cs.Attr.n.u1Present = 1;
976 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
977
978 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
979 pCtx->ds.u32Limit = 0x0000ffff;
980 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
981 pCtx->ds.Attr.n.u1Present = 1;
982 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
983
984 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
985 pCtx->es.u32Limit = 0x0000ffff;
986 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
987 pCtx->es.Attr.n.u1Present = 1;
988 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
989
990 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
991 pCtx->fs.u32Limit = 0x0000ffff;
992 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
993 pCtx->fs.Attr.n.u1Present = 1;
994 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
995
996 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
997 pCtx->gs.u32Limit = 0x0000ffff;
998 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
999 pCtx->gs.Attr.n.u1Present = 1;
1000 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1001
1002 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1003 pCtx->ss.u32Limit = 0x0000ffff;
1004 pCtx->ss.Attr.n.u1Present = 1;
1005 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1006 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1007
1008 pCtx->idtr.cbIdt = 0xffff;
1009 pCtx->gdtr.cbGdt = 0xffff;
1010
1011 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1012 pCtx->ldtr.u32Limit = 0xffff;
1013 pCtx->ldtr.Attr.n.u1Present = 1;
1014 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1015
1016 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1017 pCtx->tr.u32Limit = 0xffff;
1018 pCtx->tr.Attr.n.u1Present = 1;
1019 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1020
1021 pCtx->dr[6] = X86_DR6_INIT_VAL;
1022 pCtx->dr[7] = X86_DR7_INIT_VAL;
1023
1024 PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
1025 pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
1026 pFpuCtx->FCW = 0x37f;
1027
1028 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1029 IA-32 Processor States Following Power-up, Reset, or INIT */
1030 pFpuCtx->MXCSR = 0x1F80;
1031 pFpuCtx->MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
1032 supports all bits, since a zero value here should be read as 0xffbf. */
1033 pCtx->aXcr[0] = XSAVE_C_X87;
1034 if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_OFFSETOF(X86XSAVEAREA, Hdr))
1035 {
1036 /* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
1037 as we don't know what happened before. (Bother optimize later?) */
1038 pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 | XSAVE_C_SSE;
1039 }
1040
1041 /*
1042 * MSRs.
1043 */
1044 /* Init PAT MSR */
1045 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1046
1047 /* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1048 * The Intel docs don't mention it. */
1049 Assert(!pCtx->msrEFER);
1050
1051 /* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
1052 is supposed to be here, just trying provide useful/sensible values. */
1053 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
1054 if (pRange)
1055 {
1056 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1057 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1058 | (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
1059 | MSR_IA32_MISC_ENABLE_FAST_STRINGS;
1060 pRange->fWrIgnMask |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1061 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
1062 pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1063 }
1064
1065 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1066
1067 /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1068 * called from each EMT while we're getting called by CPUMR3Reset()
1069 * iteratively on the same thread. Fix later. */
1070#if 0 /** @todo r=bird: This we will do in TM, not here. */
1071 /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1072 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1073#endif
1074
1075
1076 /* C-state control. Guesses. */
1077 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
1078
1079
1080 /*
1081 * Get the APIC base MSR from the APIC device. For historical reasons (saved state), the APIC base
1082 * continues to reside in the APIC device and we cache it here in the VCPU for all further accesses.
1083 */
1084 PDMApicGetBaseMsr(pVCpu, &pCtx->msrApicBase, true /* fIgnoreErrors */);
1085#ifdef VBOX_WITH_NEW_APIC
1086 LogRel(("CPUM: VCPU%3d: Cached APIC base MSR = %#RX64\n", pVCpu->idCpu, pVCpu->cpum.s.Guest.msrApicBase));
1087#endif
1088}
1089
1090
1091/**
1092 * Resets the CPU.
1093 *
1094 * @returns VINF_SUCCESS.
1095 * @param pVM The cross context VM structure.
1096 */
1097VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1098{
1099 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1100 {
1101 CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
1102
1103#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1104 PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1105
1106 /* Magic marker for searching in crash dumps. */
1107 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1108 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1109 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1110#endif
1111 }
1112}
1113
1114
1115
1116
1117/**
1118 * Pass 0 live exec callback.
1119 *
1120 * @returns VINF_SSM_DONT_CALL_AGAIN.
1121 * @param pVM The cross context VM structure.
1122 * @param pSSM The saved state handle.
1123 * @param uPass The pass (0).
1124 */
1125static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1126{
1127 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
1128 cpumR3SaveCpuId(pVM, pSSM);
1129 return VINF_SSM_DONT_CALL_AGAIN;
1130}
1131
1132
1133/**
1134 * Execute state save operation.
1135 *
1136 * @returns VBox status code.
1137 * @param pVM The cross context VM structure.
1138 * @param pSSM SSM operation handle.
1139 */
1140static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1141{
1142 /*
1143 * Save.
1144 */
1145 SSMR3PutU32(pSSM, pVM->cCpus);
1146 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
1147 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1148 {
1149 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1150
1151 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1152
1153 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1154 SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1155 SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1156 if (pGstCtx->fXStateMask != 0)
1157 SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
1158 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1159 {
1160 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1161 SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1162 }
1163 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1164 {
1165 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1166 SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1167 }
1168 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1169 {
1170 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1171 SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1172 }
1173 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1174 {
1175 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1176 SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1177 }
1178 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1179 {
1180 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1181 SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1182 }
1183
1184 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1185 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1186 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
1187 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
1188 }
1189
1190 cpumR3SaveCpuId(pVM, pSSM);
1191 return VINF_SUCCESS;
1192}
1193
1194
1195/**
1196 * @callback_method_impl{FNSSMINTLOADPREP}
1197 */
1198static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1199{
1200 NOREF(pSSM);
1201 pVM->cpum.s.fPendingRestore = true;
1202 return VINF_SUCCESS;
1203}
1204
1205
1206/**
1207 * @callback_method_impl{FNSSMINTLOADEXEC}
1208 */
1209static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1210{
1211 int rc; /* Only for AssertRCReturn use. */
1212
1213 /*
1214 * Validate version.
1215 */
1216 if ( uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
1217 && uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
1218 && uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
1219 && uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
1220 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
1221 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
1222 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
1223 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1224 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1225 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1226 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1227 {
1228 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1229 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1230 }
1231
1232 if (uPass == SSM_PASS_FINAL)
1233 {
1234 /*
1235 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1236 * really old SSM file versions.)
1237 */
1238 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1239 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1240 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1241 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1242
1243 /*
1244 * Figure x86 and ctx field definitions to use for older states.
1245 */
1246 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
1247 PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
1248 PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
1249 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1250 {
1251 paCpumCtx1Fields = g_aCpumX87FieldsV16;
1252 paCpumCtx2Fields = g_aCpumCtxFieldsV16;
1253 }
1254 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1255 {
1256 paCpumCtx1Fields = g_aCpumX87FieldsMem;
1257 paCpumCtx2Fields = g_aCpumCtxFieldsMem;
1258 }
1259
1260 /*
1261 * The hyper state used to preceed the CPU count. Starting with
1262 * XSAVE it was moved down till after we've got the count.
1263 */
1264 if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
1265 {
1266 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1267 {
1268 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1269 X86FXSTATE Ign;
1270 SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1271 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1272 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1273 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
1274 fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1275 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1276 pVCpu->cpum.s.Hyper.rsp = uRSP;
1277 }
1278 }
1279
1280 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1281 {
1282 uint32_t cCpus;
1283 rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1284 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1285 VERR_SSM_UNEXPECTED_DATA);
1286 }
1287 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
1288 || pVM->cCpus == 1,
1289 ("cCpus=%u\n", pVM->cCpus),
1290 VERR_SSM_UNEXPECTED_DATA);
1291
1292 uint32_t cbMsrs = 0;
1293 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1294 {
1295 rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
1296 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
1297 VERR_SSM_UNEXPECTED_DATA);
1298 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
1299 VERR_SSM_UNEXPECTED_DATA);
1300 }
1301
1302 /*
1303 * Do the per-CPU restoring.
1304 */
1305 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1306 {
1307 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1308 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1309
1310 if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
1311 {
1312 /*
1313 * The XSAVE saved state layout moved the hyper state down here.
1314 */
1315 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1316 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1317 rc = SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1318 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1319 pVCpu->cpum.s.Hyper.rsp = uRSP;
1320 AssertRCReturn(rc, rc);
1321
1322 /*
1323 * Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
1324 */
1325 rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1326 rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1327 AssertRCReturn(rc, rc);
1328
1329 /* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
1330 if (pGstCtx->fXStateMask != 0)
1331 {
1332 AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
1333 ("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
1334 pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
1335 VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
1336 AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
1337 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1338 AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
1339 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1340 AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1341 || (pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1342 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
1343 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1344 }
1345
1346 /* Check that the XCR0 mask is valid (invalid results in #GP). */
1347 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
1348 if (pGstCtx->aXcr[0] != XSAVE_C_X87)
1349 {
1350 AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask | XSAVE_C_X87)),
1351 ("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
1352 VERR_CPUM_INVALID_XCR0);
1353 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
1354 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1355 AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
1356 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1357 AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1358 || (pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1359 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
1360 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1361 }
1362
1363 /* Check that the XCR1 is zero, as we don't implement it yet. */
1364 AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
1365
1366 /*
1367 * Restore the individual extended state components we support.
1368 */
1369 if (pGstCtx->fXStateMask != 0)
1370 {
1371 rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
1372 0, g_aCpumXSaveHdrFields, NULL);
1373 AssertRCReturn(rc, rc);
1374 AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
1375 ("bmXState=%#RX64 fXStateMask=%#RX64\n",
1376 pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
1377 VERR_CPUM_INVALID_XSAVE_HDR);
1378 }
1379 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1380 {
1381 PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
1382 SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1383 }
1384 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1385 {
1386 PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
1387 SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1388 }
1389 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1390 {
1391 PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
1392 SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1393 }
1394 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1395 {
1396 PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
1397 SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1398 }
1399 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1400 {
1401 PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
1402 SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1403 }
1404 }
1405 else
1406 {
1407 /*
1408 * Pre XSAVE saved state.
1409 */
1410 SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
1411 fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1412 SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1413 }
1414
1415 /*
1416 * Restore a couple of flags and the MSRs.
1417 */
1418 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
1419 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
1420
1421 rc = VINF_SUCCESS;
1422 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1423 rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
1424 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1425 {
1426 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
1427 rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
1428 }
1429 AssertRCReturn(rc, rc);
1430
1431 /* REM and other may have cleared must-be-one fields in DR6 and
1432 DR7, fix these. */
1433 pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
1434 pGstCtx->dr[6] |= X86_DR6_RA1_MASK;
1435 pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
1436 pGstCtx->dr[7] |= X86_DR7_RA1_MASK;
1437 }
1438
1439 /* Older states does not have the internal selector register flags
1440 and valid selector value. Supply those. */
1441 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1442 {
1443 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1444 {
1445 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1446 bool const fValid = HMIsEnabled(pVM)
1447 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1448 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
1449 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
1450 if (fValid)
1451 {
1452 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1453 {
1454 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
1455 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
1456 }
1457
1458 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1459 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1460 }
1461 else
1462 {
1463 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1464 {
1465 paSelReg[iSelReg].fFlags = 0;
1466 paSelReg[iSelReg].ValidSel = 0;
1467 }
1468
1469 /* This might not be 104% correct, but I think it's close
1470 enough for all practical purposes... (REM always loaded
1471 LDTR registers.) */
1472 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1473 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1474 }
1475 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1476 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
1477 }
1478 }
1479
1480 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
1481 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1482 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1483 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1484 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
1485
1486 /*
1487 * A quick sanity check.
1488 */
1489 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1490 {
1491 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1492 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1493 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1494 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1495 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1496 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1497 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1498 }
1499 }
1500
1501 pVM->cpum.s.fPendingRestore = false;
1502
1503 /*
1504 * Guest CPUIDs.
1505 */
1506 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
1507 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1508 return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
1509}
1510
1511
1512/**
1513 * @callback_method_impl{FNSSMINTLOADDONE}
1514 */
1515static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
1516{
1517 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
1518 return VINF_SUCCESS;
1519
1520 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
1521 if (pVM->cpum.s.fPendingRestore)
1522 {
1523 LogRel(("CPUM: Missing state!\n"));
1524 return VERR_INTERNAL_ERROR_2;
1525 }
1526
1527 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
1528 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1529 {
1530 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1531
1532 /* Notify PGM of the NXE states in case they've changed. */
1533 PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
1534
1535 /* Cache the local APIC base from the APIC device. During init. this is done in CPUMR3ResetCpu(). */
1536 PDMApicGetBaseMsr(pVCpu, &pVCpu->cpum.s.Guest.msrApicBase, true /* fIgnoreErrors */);
1537#ifdef VBOX_WITH_NEW_APIC
1538 LogRel(("CPUM: VCPU%3d: Cached APIC base MSR = %#RX64\n", idCpu, pVCpu->cpum.s.Guest.msrApicBase));
1539#endif
1540
1541 /* During init. this is done in CPUMR3InitCompleted(). */
1542 if (fSupportsLongMode)
1543 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
1544 }
1545 return VINF_SUCCESS;
1546}
1547
1548
1549/**
1550 * Checks if the CPUM state restore is still pending.
1551 *
1552 * @returns true / false.
1553 * @param pVM The cross context VM structure.
1554 */
1555VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
1556{
1557 return pVM->cpum.s.fPendingRestore;
1558}
1559
1560
1561/**
1562 * Formats the EFLAGS value into mnemonics.
1563 *
1564 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1565 * @param efl The EFLAGS value.
1566 */
1567static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1568{
1569 /*
1570 * Format the flags.
1571 */
1572 static const struct
1573 {
1574 const char *pszSet; const char *pszClear; uint32_t fFlag;
1575 } s_aFlags[] =
1576 {
1577 { "vip",NULL, X86_EFL_VIP },
1578 { "vif",NULL, X86_EFL_VIF },
1579 { "ac", NULL, X86_EFL_AC },
1580 { "vm", NULL, X86_EFL_VM },
1581 { "rf", NULL, X86_EFL_RF },
1582 { "nt", NULL, X86_EFL_NT },
1583 { "ov", "nv", X86_EFL_OF },
1584 { "dn", "up", X86_EFL_DF },
1585 { "ei", "di", X86_EFL_IF },
1586 { "tf", NULL, X86_EFL_TF },
1587 { "nt", "pl", X86_EFL_SF },
1588 { "nz", "zr", X86_EFL_ZF },
1589 { "ac", "na", X86_EFL_AF },
1590 { "po", "pe", X86_EFL_PF },
1591 { "cy", "nc", X86_EFL_CF },
1592 };
1593 char *psz = pszEFlags;
1594 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1595 {
1596 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1597 if (pszAdd)
1598 {
1599 strcpy(psz, pszAdd);
1600 psz += strlen(pszAdd);
1601 *psz++ = ' ';
1602 }
1603 }
1604 psz[-1] = '\0';
1605}
1606
1607
1608/**
1609 * Formats a full register dump.
1610 *
1611 * @param pVM The cross context VM structure.
1612 * @param pCtx The context to format.
1613 * @param pCtxCore The context core to format.
1614 * @param pHlp Output functions.
1615 * @param enmType The dump type.
1616 * @param pszPrefix Register name prefix.
1617 */
1618static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
1619 const char *pszPrefix)
1620{
1621 NOREF(pVM);
1622
1623 /*
1624 * Format the EFLAGS.
1625 */
1626 uint32_t efl = pCtxCore->eflags.u32;
1627 char szEFlags[80];
1628 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1629
1630 /*
1631 * Format the registers.
1632 */
1633 switch (enmType)
1634 {
1635 case CPUMDUMPTYPE_TERSE:
1636 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1637 pHlp->pfnPrintf(pHlp,
1638 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1639 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1640 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1641 "%sr14=%016RX64 %sr15=%016RX64\n"
1642 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1643 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1644 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1645 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1646 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1647 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1648 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1649 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1650 else
1651 pHlp->pfnPrintf(pHlp,
1652 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1653 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1654 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1655 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1656 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1657 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1658 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1659 break;
1660
1661 case CPUMDUMPTYPE_DEFAULT:
1662 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1663 pHlp->pfnPrintf(pHlp,
1664 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1665 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1666 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1667 "%sr14=%016RX64 %sr15=%016RX64\n"
1668 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1669 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1670 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1671 ,
1672 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1673 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1674 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1675 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1676 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1677 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1678 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1679 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1680 else
1681 pHlp->pfnPrintf(pHlp,
1682 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1683 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1684 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1685 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1686 ,
1687 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1688 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1689 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1690 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1691 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1692 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1693 break;
1694
1695 case CPUMDUMPTYPE_VERBOSE:
1696 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1697 pHlp->pfnPrintf(pHlp,
1698 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1699 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1700 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1701 "%sr14=%016RX64 %sr15=%016RX64\n"
1702 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1703 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1704 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1705 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1706 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1707 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1708 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1709 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1710 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1711 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1712 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1713 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1714 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1715 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1716 ,
1717 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1718 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1719 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1720 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1721 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1722 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1723 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1724 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1725 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1726 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1727 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1728 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1729 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1730 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1731 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1732 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1733 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1734 else
1735 pHlp->pfnPrintf(pHlp,
1736 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1737 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1738 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1739 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1740 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1741 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1742 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1743 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1744 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1745 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1746 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1747 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1748 ,
1749 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1750 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1751 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1752 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1753 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1754 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1755 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1756 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1757 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1758 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1759 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1760 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1761
1762 pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
1763 pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
1764 pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
1765 if (pCtx->CTX_SUFF(pXState))
1766 {
1767 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1768 pHlp->pfnPrintf(pHlp,
1769 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1770 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
1771 ,
1772 pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
1773 pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
1774 pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
1775 pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
1776 );
1777 /*
1778 * The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
1779 * not (FP)R0-7 as Intel SDM suggests.
1780 */
1781 unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
1782 for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
1783 {
1784 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
1785 unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
1786 char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
1787 unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
1788 uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
1789 int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
1790 iExponent -= 16383; /* subtract bias */
1791 /** @todo This isn't entirenly correct and needs more work! */
1792 pHlp->pfnPrintf(pHlp,
1793 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
1794 pszPrefix, iST, pszPrefix, iFPR,
1795 pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
1796 uTag, chSign, iInteger, u64Fraction, iExponent);
1797 if (pFpuCtx->aRegs[iST].au16[5] || pFpuCtx->aRegs[iST].au16[6] || pFpuCtx->aRegs[iST].au16[7])
1798 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
1799 pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
1800 else
1801 pHlp->pfnPrintf(pHlp, "\n");
1802 }
1803
1804 /* XMM/YMM/ZMM registers. */
1805 if (pCtx->fXStateMask & XSAVE_C_YMM)
1806 {
1807 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1808 if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
1809 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1810 pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1811 pszPrefix, i, i < 10 ? " " : "",
1812 pYmmHiCtx->aYmmHi[i].au32[3],
1813 pYmmHiCtx->aYmmHi[i].au32[2],
1814 pYmmHiCtx->aYmmHi[i].au32[1],
1815 pYmmHiCtx->aYmmHi[i].au32[0],
1816 pFpuCtx->aXMM[i].au32[3],
1817 pFpuCtx->aXMM[i].au32[2],
1818 pFpuCtx->aXMM[i].au32[1],
1819 pFpuCtx->aXMM[i].au32[0]);
1820 else
1821 {
1822 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1823 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1824 pHlp->pfnPrintf(pHlp,
1825 "%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1826 pszPrefix, i, i < 10 ? " " : "",
1827 pZmmHi256->aHi256Regs[i].au32[7],
1828 pZmmHi256->aHi256Regs[i].au32[6],
1829 pZmmHi256->aHi256Regs[i].au32[5],
1830 pZmmHi256->aHi256Regs[i].au32[4],
1831 pZmmHi256->aHi256Regs[i].au32[3],
1832 pZmmHi256->aHi256Regs[i].au32[2],
1833 pZmmHi256->aHi256Regs[i].au32[1],
1834 pZmmHi256->aHi256Regs[i].au32[0],
1835 pYmmHiCtx->aYmmHi[i].au32[3],
1836 pYmmHiCtx->aYmmHi[i].au32[2],
1837 pYmmHiCtx->aYmmHi[i].au32[1],
1838 pYmmHiCtx->aYmmHi[i].au32[0],
1839 pFpuCtx->aXMM[i].au32[3],
1840 pFpuCtx->aXMM[i].au32[2],
1841 pFpuCtx->aXMM[i].au32[1],
1842 pFpuCtx->aXMM[i].au32[0]);
1843
1844 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1845 for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
1846 pHlp->pfnPrintf(pHlp,
1847 "%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1848 pszPrefix, i + 16,
1849 pZmm16Hi->aRegs[i].au32[15],
1850 pZmm16Hi->aRegs[i].au32[14],
1851 pZmm16Hi->aRegs[i].au32[13],
1852 pZmm16Hi->aRegs[i].au32[12],
1853 pZmm16Hi->aRegs[i].au32[11],
1854 pZmm16Hi->aRegs[i].au32[10],
1855 pZmm16Hi->aRegs[i].au32[9],
1856 pZmm16Hi->aRegs[i].au32[8],
1857 pZmm16Hi->aRegs[i].au32[7],
1858 pZmm16Hi->aRegs[i].au32[6],
1859 pZmm16Hi->aRegs[i].au32[5],
1860 pZmm16Hi->aRegs[i].au32[4],
1861 pZmm16Hi->aRegs[i].au32[3],
1862 pZmm16Hi->aRegs[i].au32[2],
1863 pZmm16Hi->aRegs[i].au32[1],
1864 pZmm16Hi->aRegs[i].au32[0]);
1865 }
1866 }
1867 else
1868 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1869 pHlp->pfnPrintf(pHlp,
1870 i & 1
1871 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
1872 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
1873 pszPrefix, i, i < 10 ? " " : "",
1874 pFpuCtx->aXMM[i].au32[3],
1875 pFpuCtx->aXMM[i].au32[2],
1876 pFpuCtx->aXMM[i].au32[1],
1877 pFpuCtx->aXMM[i].au32[0]);
1878
1879 if (pCtx->fXStateMask & XSAVE_C_OPMASK)
1880 {
1881 PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
1882 for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
1883 pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
1884 pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
1885 pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
1886 pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
1887 pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
1888 }
1889
1890 if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
1891 {
1892 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1893 for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
1894 pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
1895 pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
1896 pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
1897 }
1898
1899 if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
1900 {
1901 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1902 pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
1903 pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
1904 }
1905
1906 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
1907 if (pFpuCtx->au32RsrvdRest[i])
1908 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
1909 pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
1910 }
1911
1912 pHlp->pfnPrintf(pHlp,
1913 "%sEFER =%016RX64\n"
1914 "%sPAT =%016RX64\n"
1915 "%sSTAR =%016RX64\n"
1916 "%sCSTAR =%016RX64\n"
1917 "%sLSTAR =%016RX64\n"
1918 "%sSFMASK =%016RX64\n"
1919 "%sKERNELGSBASE =%016RX64\n",
1920 pszPrefix, pCtx->msrEFER,
1921 pszPrefix, pCtx->msrPAT,
1922 pszPrefix, pCtx->msrSTAR,
1923 pszPrefix, pCtx->msrCSTAR,
1924 pszPrefix, pCtx->msrLSTAR,
1925 pszPrefix, pCtx->msrSFMASK,
1926 pszPrefix, pCtx->msrKERNELGSBASE);
1927 break;
1928 }
1929}
1930
1931
1932/**
1933 * Display all cpu states and any other cpum info.
1934 *
1935 * @param pVM The cross context VM structure.
1936 * @param pHlp The info helper functions.
1937 * @param pszArgs Arguments, ignored.
1938 */
1939static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1940{
1941 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1942 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1943 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1944 cpumR3InfoHost(pVM, pHlp, pszArgs);
1945}
1946
1947
1948/**
1949 * Parses the info argument.
1950 *
1951 * The argument starts with 'verbose', 'terse' or 'default' and then
1952 * continues with the comment string.
1953 *
1954 * @param pszArgs The pointer to the argument string.
1955 * @param penmType Where to store the dump type request.
1956 * @param ppszComment Where to store the pointer to the comment string.
1957 */
1958static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1959{
1960 if (!pszArgs)
1961 {
1962 *penmType = CPUMDUMPTYPE_DEFAULT;
1963 *ppszComment = "";
1964 }
1965 else
1966 {
1967 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
1968 {
1969 pszArgs += 7;
1970 *penmType = CPUMDUMPTYPE_VERBOSE;
1971 }
1972 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
1973 {
1974 pszArgs += 5;
1975 *penmType = CPUMDUMPTYPE_TERSE;
1976 }
1977 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
1978 {
1979 pszArgs += 7;
1980 *penmType = CPUMDUMPTYPE_DEFAULT;
1981 }
1982 else
1983 *penmType = CPUMDUMPTYPE_DEFAULT;
1984 *ppszComment = RTStrStripL(pszArgs);
1985 }
1986}
1987
1988
1989/**
1990 * Display the guest cpu state.
1991 *
1992 * @param pVM The cross context VM structure.
1993 * @param pHlp The info helper functions.
1994 * @param pszArgs Arguments, ignored.
1995 */
1996static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1997{
1998 CPUMDUMPTYPE enmType;
1999 const char *pszComment;
2000 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2001
2002 /* @todo SMP support! */
2003 PVMCPU pVCpu = VMMGetCpu(pVM);
2004 if (!pVCpu)
2005 pVCpu = &pVM->aCpus[0];
2006
2007 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2008
2009 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2010 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2011}
2012
2013
2014/**
2015 * Display the current guest instruction
2016 *
2017 * @param pVM The cross context VM structure.
2018 * @param pHlp The info helper functions.
2019 * @param pszArgs Arguments, ignored.
2020 */
2021static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2022{
2023 NOREF(pszArgs);
2024
2025 /** @todo SMP support! */
2026 PVMCPU pVCpu = VMMGetCpu(pVM);
2027 if (!pVCpu)
2028 pVCpu = &pVM->aCpus[0];
2029
2030 char szInstruction[256];
2031 szInstruction[0] = '\0';
2032 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2033 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2034}
2035
2036
2037/**
2038 * Display the hypervisor cpu state.
2039 *
2040 * @param pVM The cross context VM structure.
2041 * @param pHlp The info helper functions.
2042 * @param pszArgs Arguments, ignored.
2043 */
2044static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2045{
2046 CPUMDUMPTYPE enmType;
2047 const char *pszComment;
2048 /* @todo SMP */
2049 PVMCPU pVCpu = &pVM->aCpus[0];
2050
2051 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2052 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2053 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
2054 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2055}
2056
2057
2058/**
2059 * Display the host cpu state.
2060 *
2061 * @param pVM The cross context VM structure.
2062 * @param pHlp The info helper functions.
2063 * @param pszArgs Arguments, ignored.
2064 */
2065static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2066{
2067 CPUMDUMPTYPE enmType;
2068 const char *pszComment;
2069 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2070 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2071
2072 /*
2073 * Format the EFLAGS.
2074 */
2075 /* @todo SMP */
2076 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
2077#if HC_ARCH_BITS == 32
2078 uint32_t efl = pCtx->eflags.u32;
2079#else
2080 uint64_t efl = pCtx->rflags;
2081#endif
2082 char szEFlags[80];
2083 cpumR3InfoFormatFlags(&szEFlags[0], efl);
2084
2085 /*
2086 * Format the registers.
2087 */
2088#if HC_ARCH_BITS == 32
2089 pHlp->pfnPrintf(pHlp,
2090 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2091 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2092 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2093 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2094 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2095 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2096 ,
2097 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
2098 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2099 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2100 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
2101 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2102 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
2103 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2104#else
2105 pHlp->pfnPrintf(pHlp,
2106 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2107 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2108 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2109 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2110 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2111 "r14=%016RX64 r15=%016RX64\n"
2112 "iopl=%d %31s\n"
2113 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2114 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2115 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
2116 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2117 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2118 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2119 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2120 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2121 ,
2122 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
2123 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2124 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
2125 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
2126 pCtx->r11, pCtx->r12, pCtx->r13,
2127 pCtx->r14, pCtx->r15,
2128 X86_EFL_GET_IOPL(efl), szEFlags,
2129 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2130 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
2131 pCtx->cr4, pCtx->ldtr, pCtx->tr,
2132 pCtx->dr0, pCtx->dr1, pCtx->dr2,
2133 pCtx->dr3, pCtx->dr6, pCtx->dr7,
2134 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2135 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2136 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2137#endif
2138}
2139
2140/**
2141 * Structure used when disassembling and instructions in DBGF.
2142 * This is used so the reader function can get the stuff it needs.
2143 */
2144typedef struct CPUMDISASSTATE
2145{
2146 /** Pointer to the CPU structure. */
2147 PDISCPUSTATE pCpu;
2148 /** Pointer to the VM. */
2149 PVM pVM;
2150 /** Pointer to the VMCPU. */
2151 PVMCPU pVCpu;
2152 /** Pointer to the first byte in the segment. */
2153 RTGCUINTPTR GCPtrSegBase;
2154 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2155 RTGCUINTPTR GCPtrSegEnd;
2156 /** The size of the segment minus 1. */
2157 RTGCUINTPTR cbSegLimit;
2158 /** Pointer to the current page - R3 Ptr. */
2159 void const *pvPageR3;
2160 /** Pointer to the current page - GC Ptr. */
2161 RTGCPTR pvPageGC;
2162 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2163 PGMPAGEMAPLOCK PageMapLock;
2164 /** Whether the PageMapLock is valid or not. */
2165 bool fLocked;
2166 /** 64 bits mode or not. */
2167 bool f64Bits;
2168} CPUMDISASSTATE, *PCPUMDISASSTATE;
2169
2170
2171/**
2172 * @callback_method_impl{FNDISREADBYTES}
2173 */
2174static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
2175{
2176 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
2177 for (;;)
2178 {
2179 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
2180
2181 /*
2182 * Need to update the page translation?
2183 */
2184 if ( !pState->pvPageR3
2185 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2186 {
2187 int rc = VINF_SUCCESS;
2188
2189 /* translate the address */
2190 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2191 if ( !HMIsEnabled(pState->pVM)
2192 && MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
2193 {
2194 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2195 if (!pState->pvPageR3)
2196 rc = VERR_INVALID_POINTER;
2197 }
2198 else
2199 {
2200 /* Release mapping lock previously acquired. */
2201 if (pState->fLocked)
2202 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2203 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2204 pState->fLocked = RT_SUCCESS_NP(rc);
2205 }
2206 if (RT_FAILURE(rc))
2207 {
2208 pState->pvPageR3 = NULL;
2209 return rc;
2210 }
2211 }
2212
2213 /*
2214 * Check the segment limit.
2215 */
2216 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
2217 return VERR_OUT_OF_SELECTOR_BOUNDS;
2218
2219 /*
2220 * Calc how much we can read.
2221 */
2222 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2223 if (!pState->f64Bits)
2224 {
2225 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2226 if (cb > cbSeg && cbSeg)
2227 cb = cbSeg;
2228 }
2229 if (cb > cbMaxRead)
2230 cb = cbMaxRead;
2231
2232 /*
2233 * Read and advance or exit.
2234 */
2235 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2236 offInstr += (uint8_t)cb;
2237 if (cb >= cbMinRead)
2238 {
2239 pDis->cbCachedInstr = offInstr;
2240 return VINF_SUCCESS;
2241 }
2242 cbMinRead -= (uint8_t)cb;
2243 cbMaxRead -= (uint8_t)cb;
2244 }
2245}
2246
2247
2248/**
2249 * Disassemble an instruction and return the information in the provided structure.
2250 *
2251 * @returns VBox status code.
2252 * @param pVM The cross context VM structure.
2253 * @param pVCpu The cross context virtual CPU structure.
2254 * @param pCtx Pointer to the guest CPU context.
2255 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2256 * @param pCpu Disassembly state.
2257 * @param pszPrefix String prefix for logging (debug only).
2258 *
2259 */
2260VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2261{
2262 CPUMDISASSTATE State;
2263 int rc;
2264
2265 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2266 State.pCpu = pCpu;
2267 State.pvPageGC = 0;
2268 State.pvPageR3 = NULL;
2269 State.pVM = pVM;
2270 State.pVCpu = pVCpu;
2271 State.fLocked = false;
2272 State.f64Bits = false;
2273
2274 /*
2275 * Get selector information.
2276 */
2277 DISCPUMODE enmDisCpuMode;
2278 if ( (pCtx->cr0 & X86_CR0_PE)
2279 && pCtx->eflags.Bits.u1VM == 0)
2280 {
2281 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2282 {
2283# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2284 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
2285# endif
2286 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2287 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
2288 }
2289 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
2290 State.GCPtrSegBase = pCtx->cs.u64Base;
2291 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
2292 State.cbSegLimit = pCtx->cs.u32Limit;
2293 enmDisCpuMode = (State.f64Bits)
2294 ? DISCPUMODE_64BIT
2295 : pCtx->cs.Attr.n.u1DefBig
2296 ? DISCPUMODE_32BIT
2297 : DISCPUMODE_16BIT;
2298 }
2299 else
2300 {
2301 /* real or V86 mode */
2302 enmDisCpuMode = DISCPUMODE_16BIT;
2303 State.GCPtrSegBase = pCtx->cs.Sel * 16;
2304 State.GCPtrSegEnd = 0xFFFFFFFF;
2305 State.cbSegLimit = 0xFFFFFFFF;
2306 }
2307
2308 /*
2309 * Disassemble the instruction.
2310 */
2311 uint32_t cbInstr;
2312#ifndef LOG_ENABLED
2313 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
2314 if (RT_SUCCESS(rc))
2315 {
2316#else
2317 char szOutput[160];
2318 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
2319 pCpu, &cbInstr, szOutput, sizeof(szOutput));
2320 if (RT_SUCCESS(rc))
2321 {
2322 /* log it */
2323 if (pszPrefix)
2324 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2325 else
2326 Log(("%s", szOutput));
2327#endif
2328 rc = VINF_SUCCESS;
2329 }
2330 else
2331 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
2332
2333 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2334 if (State.fLocked)
2335 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2336
2337 return rc;
2338}
2339
2340
2341
2342/**
2343 * API for controlling a few of the CPU features found in CR4.
2344 *
2345 * Currently only X86_CR4_TSD is accepted as input.
2346 *
2347 * @returns VBox status code.
2348 *
2349 * @param pVM The cross context VM structure.
2350 * @param fOr The CR4 OR mask.
2351 * @param fAnd The CR4 AND mask.
2352 */
2353VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2354{
2355 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2356 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2357
2358 pVM->cpum.s.CR4.OrMask &= fAnd;
2359 pVM->cpum.s.CR4.OrMask |= fOr;
2360
2361 return VINF_SUCCESS;
2362}
2363
2364
2365/**
2366 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
2367 *
2368 * Only REM should ever call this function!
2369 *
2370 * @returns The changed flags.
2371 * @param pVCpu The cross context virtual CPU structure.
2372 * @param puCpl Where to return the current privilege level (CPL).
2373 */
2374VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
2375{
2376 Assert(!pVCpu->cpum.s.fRawEntered);
2377 Assert(!pVCpu->cpum.s.fRemEntered);
2378
2379 /*
2380 * Get the CPL first.
2381 */
2382 *puCpl = CPUMGetGuestCPL(pVCpu);
2383
2384 /*
2385 * Get and reset the flags.
2386 */
2387 uint32_t fFlags = pVCpu->cpum.s.fChanged;
2388 pVCpu->cpum.s.fChanged = 0;
2389
2390 /** @todo change the switcher to use the fChanged flags. */
2391 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
2392 {
2393 fFlags |= CPUM_CHANGED_FPU_REM;
2394 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
2395 }
2396
2397 pVCpu->cpum.s.fRemEntered = true;
2398 return fFlags;
2399}
2400
2401
2402/**
2403 * Leaves REM.
2404 *
2405 * @param pVCpu The cross context virtual CPU structure.
2406 * @param fNoOutOfSyncSels This is @c false if there are out of sync
2407 * registers.
2408 */
2409VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
2410{
2411 Assert(!pVCpu->cpum.s.fRawEntered);
2412 Assert(pVCpu->cpum.s.fRemEntered);
2413
2414 pVCpu->cpum.s.fRemEntered = false;
2415}
2416
2417
2418/**
2419 * Called when the ring-3 init phase completes.
2420 *
2421 * @returns VBox status code.
2422 * @param pVM The cross context VM structure.
2423 * @param enmWhat Which init phase.
2424 */
2425VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
2426{
2427 switch (enmWhat)
2428 {
2429 case VMINITCOMPLETED_RING3:
2430 {
2431 /*
2432 * Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
2433 * Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
2434 */
2435 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2436 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2437 {
2438 PVMCPU pVCpu = &pVM->aCpus[i];
2439 /* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
2440 if (fSupportsLongMode)
2441 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
2442 }
2443
2444 cpumR3MsrRegStats(pVM);
2445 break;
2446 }
2447
2448 case VMINITCOMPLETED_RING0:
2449 {
2450 /* Cache the APIC base (from the APIC device) once it has been initialized. */
2451 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2452 {
2453 PVMCPU pVCpu = &pVM->aCpus[i];
2454 PDMApicGetBaseMsr(pVCpu, &pVCpu->cpum.s.Guest.msrApicBase, true /* fIgnoreErrors */);
2455#ifdef VBOX_WITH_NEW_APIC
2456 LogRel(("CPUM: VCPU%3d: Cached APIC base MSR = %#RX64\n", i, pVCpu->cpum.s.Guest.msrApicBase));
2457#endif
2458 }
2459 break;
2460 }
2461
2462 default:
2463 break;
2464 }
2465 return VINF_SUCCESS;
2466}
2467
2468
2469/**
2470 * Called when the ring-0 init phases completed.
2471 *
2472 * @param pVM The cross context VM structure.
2473 */
2474VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
2475{
2476 /*
2477 * Log the cpuid.
2478 */
2479 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
2480 RTCPUSET OnlineSet;
2481 LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
2482 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
2483 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
2484 RTCPUID cCores = RTMpGetCoreCount();
2485 if (cCores)
2486 LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
2487 LogRel(("************************* CPUID dump ************************\n"));
2488 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
2489 LogRel(("\n"));
2490 DBGFR3_INFO_LOG(pVM, "cpuid", "verbose"); /* macro */
2491 RTLogRelSetBuffering(fOldBuffered);
2492 LogRel(("******************** End of CPUID dump **********************\n"));
2493}
2494
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