VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 55078

Last change on this file since 55078 was 55063, checked in by vboxsync, 10 years ago

CPUM: State saving fixes.
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1/* $Id: CPUM.cpp 55063 2015-04-01 00:51:59Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_CPUM
38#include <VBox/vmm/cpum.h>
39#include <VBox/vmm/cpumdis.h>
40#include <VBox/vmm/cpumctx-v1_6.h>
41#include <VBox/vmm/pgm.h>
42#include <VBox/vmm/pdmapi.h>
43#include <VBox/vmm/mm.h>
44#include <VBox/vmm/em.h>
45#include <VBox/vmm/selm.h>
46#include <VBox/vmm/dbgf.h>
47#include <VBox/vmm/patm.h>
48#include <VBox/vmm/hm.h>
49#include <VBox/vmm/ssm.h>
50#include "CPUMInternal.h"
51#include <VBox/vmm/vm.h>
52
53#include <VBox/param.h>
54#include <VBox/dis.h>
55#include <VBox/err.h>
56#include <VBox/log.h>
57#include <iprt/asm-amd64-x86.h>
58#include <iprt/assert.h>
59#include <iprt/cpuset.h>
60#include <iprt/mem.h>
61#include <iprt/mp.h>
62#include <iprt/string.h>
63#include "internal/pgm.h"
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/**
70 * This was used in the saved state up to the early life of version 14.
71 *
72 * It indicates that we may have some out-of-sync hidden segement registers.
73 * It is only relevant for raw-mode.
74 */
75#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
76
77
78/*******************************************************************************
79* Structures and Typedefs *
80*******************************************************************************/
81
82/**
83 * What kind of cpu info dump to perform.
84 */
85typedef enum CPUMDUMPTYPE
86{
87 CPUMDUMPTYPE_TERSE,
88 CPUMDUMPTYPE_DEFAULT,
89 CPUMDUMPTYPE_VERBOSE
90} CPUMDUMPTYPE;
91/** Pointer to a cpu info dump type. */
92typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
93
94
95/*******************************************************************************
96* Internal Functions *
97*******************************************************************************/
98static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
99static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
100static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
101static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
102static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
103static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108
109
110/*******************************************************************************
111* Global Variables *
112*******************************************************************************/
113/** Saved state field descriptors for CPUMCTX. */
114static const SSMFIELD g_aCpumX87Fields[] =
115{
116 SSMFIELD_ENTRY( X86FXSTATE, FCW),
117 SSMFIELD_ENTRY( X86FXSTATE, FSW),
118 SSMFIELD_ENTRY( X86FXSTATE, FTW),
119 SSMFIELD_ENTRY( X86FXSTATE, FOP),
120 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
121 SSMFIELD_ENTRY( X86FXSTATE, CS),
122 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
123 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
124 SSMFIELD_ENTRY( X86FXSTATE, DS),
125 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
126 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
127 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
128 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
129 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
130 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
131 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
132 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
133 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
134 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
135 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
136 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
137 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
138 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
139 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
140 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
141 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
142 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
143 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
144 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
145 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
146 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
147 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
148 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
149 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
150 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
151 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
152 SSMFIELD_ENTRY_TERM()
153};
154
155/** Saved state field descriptors for CPUMCTX. */
156static const SSMFIELD g_aCpumCtxFields[] =
157{
158 SSMFIELD_ENTRY( CPUMCTX, rdi),
159 SSMFIELD_ENTRY( CPUMCTX, rsi),
160 SSMFIELD_ENTRY( CPUMCTX, rbp),
161 SSMFIELD_ENTRY( CPUMCTX, rax),
162 SSMFIELD_ENTRY( CPUMCTX, rbx),
163 SSMFIELD_ENTRY( CPUMCTX, rdx),
164 SSMFIELD_ENTRY( CPUMCTX, rcx),
165 SSMFIELD_ENTRY( CPUMCTX, rsp),
166 SSMFIELD_ENTRY( CPUMCTX, rflags),
167 SSMFIELD_ENTRY( CPUMCTX, rip),
168 SSMFIELD_ENTRY( CPUMCTX, r8),
169 SSMFIELD_ENTRY( CPUMCTX, r9),
170 SSMFIELD_ENTRY( CPUMCTX, r10),
171 SSMFIELD_ENTRY( CPUMCTX, r11),
172 SSMFIELD_ENTRY( CPUMCTX, r12),
173 SSMFIELD_ENTRY( CPUMCTX, r13),
174 SSMFIELD_ENTRY( CPUMCTX, r14),
175 SSMFIELD_ENTRY( CPUMCTX, r15),
176 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
177 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
178 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
179 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
180 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
181 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
182 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
183 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
184 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
185 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
186 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
187 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
188 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
189 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
190 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
191 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
192 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
193 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
194 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
195 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
196 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
197 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
198 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
199 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
200 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
201 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
202 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
203 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
204 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
205 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
206 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
207 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
208 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
209 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
210 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
211 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
212 SSMFIELD_ENTRY( CPUMCTX, cr0),
213 SSMFIELD_ENTRY( CPUMCTX, cr2),
214 SSMFIELD_ENTRY( CPUMCTX, cr3),
215 SSMFIELD_ENTRY( CPUMCTX, cr4),
216 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
217 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
218 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
219 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
220 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
221 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
222 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
223 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
224 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
225 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
226 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
227 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
228 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
229 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
230 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
231 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
232 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
233 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
234 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
235 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
236 /* msrApicBase is not included here, it resides in the APIC device state. */
237 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
238 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
239 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
240 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
241 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
242 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
243 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
244 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
245 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
246 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
247 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
248 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
249 SSMFIELD_ENTRY_TERM()
250};
251
252/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
253 * registeres changed. */
254static const SSMFIELD g_aCpumX87FieldsMem[] =
255{
256 SSMFIELD_ENTRY( X86FXSTATE, FCW),
257 SSMFIELD_ENTRY( X86FXSTATE, FSW),
258 SSMFIELD_ENTRY( X86FXSTATE, FTW),
259 SSMFIELD_ENTRY( X86FXSTATE, FOP),
260 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
261 SSMFIELD_ENTRY( X86FXSTATE, CS),
262 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
263 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
264 SSMFIELD_ENTRY( X86FXSTATE, DS),
265 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
266 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
267 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
268 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
269 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
270 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
271 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
272 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
273 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
274 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
275 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
276 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
277 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
278 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
279 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
280 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
281 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
282 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
283 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
284 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
285 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
286 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
287 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
288 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
289 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
290 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
291 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
292 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
293 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
294};
295
296/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
297 * registeres changed. */
298static const SSMFIELD g_aCpumCtxFieldsMem[] =
299{
300 SSMFIELD_ENTRY( CPUMCTX, rdi),
301 SSMFIELD_ENTRY( CPUMCTX, rsi),
302 SSMFIELD_ENTRY( CPUMCTX, rbp),
303 SSMFIELD_ENTRY( CPUMCTX, rax),
304 SSMFIELD_ENTRY( CPUMCTX, rbx),
305 SSMFIELD_ENTRY( CPUMCTX, rdx),
306 SSMFIELD_ENTRY( CPUMCTX, rcx),
307 SSMFIELD_ENTRY( CPUMCTX, rsp),
308 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
309 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
310 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
311 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
312 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
313 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
314 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
315 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
316 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
317 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
318 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
319 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
320 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
321 SSMFIELD_ENTRY( CPUMCTX, rflags),
322 SSMFIELD_ENTRY( CPUMCTX, rip),
323 SSMFIELD_ENTRY( CPUMCTX, r8),
324 SSMFIELD_ENTRY( CPUMCTX, r9),
325 SSMFIELD_ENTRY( CPUMCTX, r10),
326 SSMFIELD_ENTRY( CPUMCTX, r11),
327 SSMFIELD_ENTRY( CPUMCTX, r12),
328 SSMFIELD_ENTRY( CPUMCTX, r13),
329 SSMFIELD_ENTRY( CPUMCTX, r14),
330 SSMFIELD_ENTRY( CPUMCTX, r15),
331 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
332 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
333 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
334 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
335 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
336 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
337 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
338 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
339 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
340 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
341 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
342 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
343 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
344 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
345 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
346 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
347 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
348 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
349 SSMFIELD_ENTRY( CPUMCTX, cr0),
350 SSMFIELD_ENTRY( CPUMCTX, cr2),
351 SSMFIELD_ENTRY( CPUMCTX, cr3),
352 SSMFIELD_ENTRY( CPUMCTX, cr4),
353 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
354 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
355 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
356 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
357 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
358 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
359 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
360 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
361 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
362 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
363 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
364 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
365 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
366 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
367 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
368 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
369 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
370 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
371 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
372 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
373 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
374 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
375 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
376 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
377 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
378 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
379 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
380 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
381 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
382 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
383 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
384 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
385 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
386 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
387 SSMFIELD_ENTRY_TERM()
388};
389
390/** Saved state field descriptors for CPUMCTX_VER1_6. */
391static const SSMFIELD g_aCpumX87FieldsV16[] =
392{
393 SSMFIELD_ENTRY( X86FXSTATE, FCW),
394 SSMFIELD_ENTRY( X86FXSTATE, FSW),
395 SSMFIELD_ENTRY( X86FXSTATE, FTW),
396 SSMFIELD_ENTRY( X86FXSTATE, FOP),
397 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
398 SSMFIELD_ENTRY( X86FXSTATE, CS),
399 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
400 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
401 SSMFIELD_ENTRY( X86FXSTATE, DS),
402 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
403 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
404 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
405 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
406 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
407 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
408 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
409 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
410 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
411 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
412 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
413 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
414 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
415 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
416 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
417 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
418 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
419 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
420 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
421 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
422 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
423 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
424 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
425 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
426 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
427 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
428 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
429 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
430 SSMFIELD_ENTRY_TERM()
431};
432
433/** Saved state field descriptors for CPUMCTX_VER1_6. */
434static const SSMFIELD g_aCpumCtxFieldsV16[] =
435{
436 SSMFIELD_ENTRY( CPUMCTX, rdi),
437 SSMFIELD_ENTRY( CPUMCTX, rsi),
438 SSMFIELD_ENTRY( CPUMCTX, rbp),
439 SSMFIELD_ENTRY( CPUMCTX, rax),
440 SSMFIELD_ENTRY( CPUMCTX, rbx),
441 SSMFIELD_ENTRY( CPUMCTX, rdx),
442 SSMFIELD_ENTRY( CPUMCTX, rcx),
443 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
444 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
445 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
446 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
447 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
448 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
449 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
450 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
451 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
452 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
453 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
454 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
455 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
456 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
457 SSMFIELD_ENTRY( CPUMCTX, rflags),
458 SSMFIELD_ENTRY( CPUMCTX, rip),
459 SSMFIELD_ENTRY( CPUMCTX, r8),
460 SSMFIELD_ENTRY( CPUMCTX, r9),
461 SSMFIELD_ENTRY( CPUMCTX, r10),
462 SSMFIELD_ENTRY( CPUMCTX, r11),
463 SSMFIELD_ENTRY( CPUMCTX, r12),
464 SSMFIELD_ENTRY( CPUMCTX, r13),
465 SSMFIELD_ENTRY( CPUMCTX, r14),
466 SSMFIELD_ENTRY( CPUMCTX, r15),
467 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
468 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
469 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
470 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
471 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
472 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
473 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
474 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
475 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
476 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
477 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
478 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
479 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
480 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
481 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
482 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
483 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
484 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
485 SSMFIELD_ENTRY( CPUMCTX, cr0),
486 SSMFIELD_ENTRY( CPUMCTX, cr2),
487 SSMFIELD_ENTRY( CPUMCTX, cr3),
488 SSMFIELD_ENTRY( CPUMCTX, cr4),
489 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
490 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
491 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
492 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
493 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
494 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
495 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
496 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
497 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
498 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
499 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
500 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
501 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
502 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
503 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
504 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
505 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
506 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
507 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
508 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
509 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
510 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
511 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
512 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
513 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
514 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
515 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
516 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
517 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
518 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
519 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
520 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
521 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
522 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
523 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
524 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
525 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
526 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
527 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
528 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
529 SSMFIELD_ENTRY_TERM()
530};
531
532
533/**
534 * Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
535 *
536 * AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
537 * (last instruction pointer, last data pointer, last opcode) except when the ES
538 * bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
539 * clear these registers there is potential, local FPU leakage from a process
540 * using the FPU to another.
541 *
542 * See AMD Instruction Reference for FXSAVE, FXRSTOR.
543 *
544 * @param pVM Pointer to the VM.
545 */
546static void cpumR3CheckLeakyFpu(PVM pVM)
547{
548 uint32_t u32CpuVersion = ASMCpuId_EAX(1);
549 uint32_t const u32Family = u32CpuVersion >> 8;
550 if ( u32Family >= 6 /* K7 and higher */
551 && ASMIsAmdCpu())
552 {
553 uint32_t cExt = ASMCpuId_EAX(0x80000000);
554 if (ASMIsValidExtRange(cExt))
555 {
556 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
557 if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
558 {
559 for (VMCPUID i = 0; i < pVM->cCpus; i++)
560 pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_FFXSR_LEAKY;
561 Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
562 }
563 }
564 }
565}
566
567
568/**
569 * Initializes the CPUM.
570 *
571 * @returns VBox status code.
572 * @param pVM Pointer to the VM.
573 */
574VMMR3DECL(int) CPUMR3Init(PVM pVM)
575{
576 LogFlow(("CPUMR3Init\n"));
577
578 /*
579 * Assert alignment, sizes and tables.
580 */
581 AssertCompileMemberAlignment(VM, cpum.s, 32);
582 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
583 AssertCompileSizeAlignment(CPUMCTX, 64);
584 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
585 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
586 AssertCompileMemberAlignment(VM, cpum, 64);
587 AssertCompileMemberAlignment(VM, aCpus, 64);
588 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
589 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
590#ifdef VBOX_STRICT
591 int rc2 = cpumR3MsrStrictInitChecks();
592 AssertRCReturn(rc2, rc2);
593#endif
594
595 /*
596 * Initialize offsets.
597 */
598
599 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
600 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
601 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
602
603
604 /* Calculate the offset from CPUMCPU to CPUM. */
605 for (VMCPUID i = 0; i < pVM->cCpus; i++)
606 {
607 PVMCPU pVCpu = &pVM->aCpus[i];
608
609 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
610 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
611 }
612
613 /*
614 * Gather info about the host CPU.
615 */
616 if (!ASMHasCpuId())
617 {
618 Log(("The CPU doesn't support CPUID!\n"));
619 return VERR_UNSUPPORTED_CPU;
620 }
621
622 PCPUMCPUIDLEAF paLeaves;
623 uint32_t cLeaves;
624 int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
625 AssertLogRelRCReturn(rc, rc);
626
627 rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
628 RTMemFree(paLeaves);
629 AssertLogRelRCReturn(rc, rc);
630 pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
631
632 /*
633 * Check that the CPU supports the minimum features we require.
634 */
635 if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
636 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
637 if (!pVM->cpum.s.HostFeatures.fMmx)
638 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
639 if (!pVM->cpum.s.HostFeatures.fTsc)
640 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
641
642 /*
643 * Setup the CR4 AND and OR masks used in the raw-mode switcher.
644 */
645 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
646 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
647
648 /*
649 * Allocate memory for the extended CPU state.
650 */
651 uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
652 cbMaxXState = RT_ALIGN(cbMaxXState, 128);
653 AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
654
655 uint8_t *pbXStates;
656 rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
657 MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
658 AssertLogRelRCReturn(rc, rc);
659
660 for (VMCPUID i = 0; i < pVM->cCpus; i++)
661 {
662 PVMCPU pVCpu = &pVM->aCpus[i];
663
664 pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
665 pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
666 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
667 pbXStates += cbMaxXState;
668
669 pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
670 pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
671 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
672 pbXStates += cbMaxXState;
673
674 pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
675 pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
676 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
677 pbXStates += cbMaxXState;
678 }
679
680 /*
681 * Setup hypervisor startup values.
682 */
683
684 /*
685 * Register saved state data item.
686 */
687 rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
688 NULL, cpumR3LiveExec, NULL,
689 NULL, cpumR3SaveExec, NULL,
690 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
691 if (RT_FAILURE(rc))
692 return rc;
693
694 /*
695 * Register info handlers and registers with the debugger facility.
696 */
697 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
698 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
699 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
700 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
701 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
702 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
703
704 rc = cpumR3DbgInit(pVM);
705 if (RT_FAILURE(rc))
706 return rc;
707
708 /*
709 * Check if we need to workaround partial/leaky FPU handling.
710 */
711 cpumR3CheckLeakyFpu(pVM);
712
713 /*
714 * Initialize the Guest CPUID and MSR states.
715 */
716 rc = cpumR3InitCpuIdAndMsrs(pVM);
717 if (RT_FAILURE(rc))
718 return rc;
719 CPUMR3Reset(pVM);
720 return VINF_SUCCESS;
721}
722
723
724/**
725 * Applies relocations to data and code managed by this
726 * component. This function will be called at init and
727 * whenever the VMM need to relocate it self inside the GC.
728 *
729 * The CPUM will update the addresses used by the switcher.
730 *
731 * @param pVM The VM.
732 */
733VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
734{
735 LogFlow(("CPUMR3Relocate\n"));
736
737 pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
738 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
739
740 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
741 {
742 PVMCPU pVCpu = &pVM->aCpus[iCpu];
743 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
744 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
745 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
746
747 /* Recheck the guest DRx values in raw-mode. */
748 CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
749 }
750}
751
752
753/**
754 * Apply late CPUM property changes based on the fHWVirtEx setting
755 *
756 * @param pVM Pointer to the VM.
757 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
758 */
759VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
760{
761 /*
762 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
763 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
764 * of processors from (cpuid(4).eax >> 26) + 1.
765 *
766 * Note: this code is obsolete, but let's keep it here for reference.
767 * Purpose is valid when we artificially cap the max std id to less than 4.
768 */
769 if (!fHWVirtExEnabled)
770 {
771 Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
772 || pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
773 pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
774 }
775}
776
777/**
778 * Terminates the CPUM.
779 *
780 * Termination means cleaning up and freeing all resources,
781 * the VM it self is at this point powered off or suspended.
782 *
783 * @returns VBox status code.
784 * @param pVM Pointer to the VM.
785 */
786VMMR3DECL(int) CPUMR3Term(PVM pVM)
787{
788#ifdef VBOX_WITH_CRASHDUMP_MAGIC
789 for (VMCPUID i = 0; i < pVM->cCpus; i++)
790 {
791 PVMCPU pVCpu = &pVM->aCpus[i];
792 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
793
794 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
795 pVCpu->cpum.s.uMagic = 0;
796 pCtx->dr[5] = 0;
797 }
798#else
799 NOREF(pVM);
800#endif
801 return VINF_SUCCESS;
802}
803
804
805/**
806 * Resets a virtual CPU.
807 *
808 * Used by CPUMR3Reset and CPU hot plugging.
809 *
810 * @param pVM Pointer to the cross context VM structure.
811 * @param pVCpu Pointer to the cross context virtual CPU structure of
812 * the CPU that is being reset. This may differ from the
813 * current EMT.
814 */
815VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
816{
817 /** @todo anything different for VCPU > 0? */
818 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
819
820 /*
821 * Initialize everything to ZERO first.
822 */
823 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
824
825 AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
826 AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
827 memset(pCtx, 0, RT_OFFSETOF(CPUMCTX, pXStateR0));
828
829 pVCpu->cpum.s.fUseFlags = fUseFlags;
830
831 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
832 pCtx->eip = 0x0000fff0;
833 pCtx->edx = 0x00000600; /* P6 processor */
834 pCtx->eflags.Bits.u1Reserved0 = 1;
835
836 pCtx->cs.Sel = 0xf000;
837 pCtx->cs.ValidSel = 0xf000;
838 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
839 pCtx->cs.u64Base = UINT64_C(0xffff0000);
840 pCtx->cs.u32Limit = 0x0000ffff;
841 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
842 pCtx->cs.Attr.n.u1Present = 1;
843 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
844
845 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
846 pCtx->ds.u32Limit = 0x0000ffff;
847 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
848 pCtx->ds.Attr.n.u1Present = 1;
849 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
850
851 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
852 pCtx->es.u32Limit = 0x0000ffff;
853 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
854 pCtx->es.Attr.n.u1Present = 1;
855 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
856
857 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
858 pCtx->fs.u32Limit = 0x0000ffff;
859 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
860 pCtx->fs.Attr.n.u1Present = 1;
861 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
862
863 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
864 pCtx->gs.u32Limit = 0x0000ffff;
865 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
866 pCtx->gs.Attr.n.u1Present = 1;
867 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
868
869 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
870 pCtx->ss.u32Limit = 0x0000ffff;
871 pCtx->ss.Attr.n.u1Present = 1;
872 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
873 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
874
875 pCtx->idtr.cbIdt = 0xffff;
876 pCtx->gdtr.cbGdt = 0xffff;
877
878 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
879 pCtx->ldtr.u32Limit = 0xffff;
880 pCtx->ldtr.Attr.n.u1Present = 1;
881 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
882
883 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
884 pCtx->tr.u32Limit = 0xffff;
885 pCtx->tr.Attr.n.u1Present = 1;
886 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
887
888 pCtx->dr[6] = X86_DR6_INIT_VAL;
889 pCtx->dr[7] = X86_DR7_INIT_VAL;
890
891 PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
892 pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
893 pFpuCtx->FCW = 0x37f;
894
895 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
896 IA-32 Processor States Following Power-up, Reset, or INIT */
897 pFpuCtx->MXCSR = 0x1F80;
898 pFpuCtx->MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
899 supports all bits, since a zero value here should be read as 0xffbf. */
900
901 /*
902 * MSRs.
903 */
904 /* Init PAT MSR */
905 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
906
907 /* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
908 * The Intel docs don't mention it. */
909 Assert(!pCtx->msrEFER);
910
911 /* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
912 is supposed to be here, just trying provide useful/sensible values. */
913 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
914 if (pRange)
915 {
916 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
917 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
918 | (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
919 | MSR_IA32_MISC_ENABLE_FAST_STRINGS;
920 pRange->fWrIgnMask |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
921 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
922 pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
923 }
924
925 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
926
927 /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
928 * called from each EMT while we're getting called by CPUMR3Reset()
929 * iteratively on the same thread. Fix later. */
930#if 0 /** @todo r=bird: This we will do in TM, not here. */
931 /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
932 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
933#endif
934
935
936 /* C-state control. Guesses. */
937 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
938
939
940 /*
941 * Get the APIC base MSR from the APIC device. For historical reasons (saved state), the APIC base
942 * continues to reside in the APIC device and we cache it here in the VCPU for all further accesses.
943 */
944 PDMApicGetBase(pVCpu, &pCtx->msrApicBase);
945}
946
947
948/**
949 * Resets the CPU.
950 *
951 * @returns VINF_SUCCESS.
952 * @param pVM Pointer to the VM.
953 */
954VMMR3DECL(void) CPUMR3Reset(PVM pVM)
955{
956 for (VMCPUID i = 0; i < pVM->cCpus; i++)
957 {
958 CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
959
960#ifdef VBOX_WITH_CRASHDUMP_MAGIC
961 PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
962
963 /* Magic marker for searching in crash dumps. */
964 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
965 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
966 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
967#endif
968 }
969}
970
971
972
973
974/**
975 * Pass 0 live exec callback.
976 *
977 * @returns VINF_SSM_DONT_CALL_AGAIN.
978 * @param pVM Pointer to the VM.
979 * @param pSSM The saved state handle.
980 * @param uPass The pass (0).
981 */
982static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
983{
984 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
985 cpumR3SaveCpuId(pVM, pSSM);
986 return VINF_SSM_DONT_CALL_AGAIN;
987}
988
989
990/**
991 * Execute state save operation.
992 *
993 * @returns VBox status code.
994 * @param pVM Pointer to the VM.
995 * @param pSSM SSM operation handle.
996 */
997static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
998{
999 /*
1000 * Save.
1001 */
1002 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1003 {
1004 PVMCPU pVCpu = &pVM->aCpus[i];
1005 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper.pXStateR3->x87, sizeof(*pVCpu->cpum.s.Hyper.pXStateR3),
1006 SSMSTRUCT_FLAGS_NO_TAIL_MARKER, g_aCpumX87Fields, NULL);
1007 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
1008 SSMSTRUCT_FLAGS_NO_LEAD_MARKER, g_aCpumCtxFields, NULL);
1009 }
1010
1011 SSMR3PutU32(pSSM, pVM->cCpus);
1012 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
1013 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1014 {
1015 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1016
1017 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Guest.pXStateR3->x87, sizeof(*pVCpu->cpum.s.Guest.pXStateR3),
1018 SSMSTRUCT_FLAGS_NO_TAIL_MARKER, g_aCpumX87Fields, NULL);
1019 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest),
1020 SSMSTRUCT_FLAGS_NO_LEAD_MARKER, g_aCpumCtxFields, NULL);
1021 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1022 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1023 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
1024 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
1025 }
1026
1027 cpumR3SaveCpuId(pVM, pSSM);
1028 return VINF_SUCCESS;
1029}
1030
1031
1032/**
1033 * @copydoc FNSSMINTLOADPREP
1034 */
1035static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1036{
1037 NOREF(pSSM);
1038 pVM->cpum.s.fPendingRestore = true;
1039 return VINF_SUCCESS;
1040}
1041
1042
1043/**
1044 * @copydoc FNSSMINTLOADEXEC
1045 */
1046static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1047{
1048 /*
1049 * Validate version.
1050 */
1051 if ( uVersion != CPUM_SAVED_STATE_VERSION
1052 && uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
1053 && uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
1054 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
1055 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
1056 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
1057 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1058 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1059 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1060 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1061 {
1062 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1063 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1064 }
1065
1066 if (uPass == SSM_PASS_FINAL)
1067 {
1068 /*
1069 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1070 * really old SSM file versions.)
1071 */
1072 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1073 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1074 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1075 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1076
1077 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
1078 PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
1079 PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
1080 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1081 {
1082 paCpumCtx1Fields = g_aCpumX87FieldsV16;
1083 paCpumCtx2Fields = g_aCpumCtxFieldsV16;
1084 }
1085 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1086 {
1087 paCpumCtx1Fields = g_aCpumX87FieldsMem;
1088 paCpumCtx2Fields = g_aCpumCtxFieldsMem;
1089 }
1090
1091 /*
1092 * Restore.
1093 */
1094 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1095 {
1096 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1097 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1098 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1099 /** @todo drop the FPU bits here! */
1100 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper.pXStateR3->x87, sizeof(pVCpu->cpum.s.Hyper.pXStateR3->x87),
1101 fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1102 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
1103 fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1104 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1105 pVCpu->cpum.s.Hyper.rsp = uRSP;
1106 }
1107
1108 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1109 {
1110 uint32_t cCpus;
1111 int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1112 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1113 VERR_SSM_UNEXPECTED_DATA);
1114 }
1115 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
1116 || pVM->cCpus == 1,
1117 ("cCpus=%u\n", pVM->cCpus),
1118 VERR_SSM_UNEXPECTED_DATA);
1119
1120 uint32_t cbMsrs = 0;
1121 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1122 {
1123 int rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
1124 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
1125 VERR_SSM_UNEXPECTED_DATA);
1126 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
1127 VERR_SSM_UNEXPECTED_DATA);
1128 }
1129
1130 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1131 {
1132 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1133 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Guest.pXStateR3->x87, sizeof(pVCpu->cpum.s.Guest.pXStateR3->x87),
1134 fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1135 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest),
1136 fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1137 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
1138 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
1139 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1140 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
1141 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1142 {
1143 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
1144 SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
1145 }
1146
1147 /* REM and other may have cleared must-be-one fields in DR6 and
1148 DR7, fix these. */
1149 pVCpu->cpum.s.Guest.dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
1150 pVCpu->cpum.s.Guest.dr[6] |= X86_DR6_RA1_MASK;
1151 pVCpu->cpum.s.Guest.dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
1152 pVCpu->cpum.s.Guest.dr[7] |= X86_DR7_RA1_MASK;
1153 }
1154
1155 /* Older states does not have the internal selector register flags
1156 and valid selector value. Supply those. */
1157 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1158 {
1159 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1160 {
1161 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1162 bool const fValid = HMIsEnabled(pVM)
1163 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1164 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
1165 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
1166 if (fValid)
1167 {
1168 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1169 {
1170 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
1171 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
1172 }
1173
1174 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1175 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1176 }
1177 else
1178 {
1179 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1180 {
1181 paSelReg[iSelReg].fFlags = 0;
1182 paSelReg[iSelReg].ValidSel = 0;
1183 }
1184
1185 /* This might not be 104% correct, but I think it's close
1186 enough for all practical purposes... (REM always loaded
1187 LDTR registers.) */
1188 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1189 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1190 }
1191 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1192 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
1193 }
1194 }
1195
1196 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
1197 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1198 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1199 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1200 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
1201
1202 /*
1203 * A quick sanity check.
1204 */
1205 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1206 {
1207 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1208 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1209 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1210 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1211 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1212 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1213 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1214 }
1215 }
1216
1217 pVM->cpum.s.fPendingRestore = false;
1218
1219 /*
1220 * Guest CPUIDs.
1221 */
1222 if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
1223 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1224
1225 /** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
1226 * actually required. */
1227
1228 /*
1229 * Restore the CPUID leaves.
1230 *
1231 * Note that we support restoring less than the current amount of standard
1232 * leaves because we've been allowed more is newer version of VBox.
1233 */
1234 uint32_t cElements;
1235 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1236 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
1237 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1238 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
1239
1240 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1241 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
1242 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1243 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
1244
1245 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1246 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
1247 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1248 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
1249
1250 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
1251
1252 /*
1253 * Check that the basic cpuid id information is unchanged.
1254 */
1255 /** @todo we should check the 64 bits capabilities too! */
1256 uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
1257 ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1258 ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1259 uint32_t au32CpuIdSaved[8];
1260 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1261 if (RT_SUCCESS(rc))
1262 {
1263 /* Ignore CPU stepping. */
1264 au32CpuId[4] &= 0xfffffff0;
1265 au32CpuIdSaved[4] &= 0xfffffff0;
1266
1267 /* Ignore APIC ID (AMD specs). */
1268 au32CpuId[5] &= ~0xff000000;
1269 au32CpuIdSaved[5] &= ~0xff000000;
1270
1271 /* Ignore the number of Logical CPUs (AMD specs). */
1272 au32CpuId[5] &= ~0x00ff0000;
1273 au32CpuIdSaved[5] &= ~0x00ff0000;
1274
1275 /* Ignore some advanced capability bits, that we don't expose to the guest. */
1276 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
1277 | X86_CPUID_FEATURE_ECX_VMX
1278 | X86_CPUID_FEATURE_ECX_SMX
1279 | X86_CPUID_FEATURE_ECX_EST
1280 | X86_CPUID_FEATURE_ECX_TM2
1281 | X86_CPUID_FEATURE_ECX_CNTXID
1282 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1283 | X86_CPUID_FEATURE_ECX_PDCM
1284 | X86_CPUID_FEATURE_ECX_DCA
1285 | X86_CPUID_FEATURE_ECX_X2APIC
1286 );
1287 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
1288 | X86_CPUID_FEATURE_ECX_VMX
1289 | X86_CPUID_FEATURE_ECX_SMX
1290 | X86_CPUID_FEATURE_ECX_EST
1291 | X86_CPUID_FEATURE_ECX_TM2
1292 | X86_CPUID_FEATURE_ECX_CNTXID
1293 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1294 | X86_CPUID_FEATURE_ECX_PDCM
1295 | X86_CPUID_FEATURE_ECX_DCA
1296 | X86_CPUID_FEATURE_ECX_X2APIC
1297 );
1298
1299 /* Make sure we don't forget to update the masks when enabling
1300 * features in the future.
1301 */
1302 AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
1303 ( X86_CPUID_FEATURE_ECX_DTES64
1304 | X86_CPUID_FEATURE_ECX_VMX
1305 | X86_CPUID_FEATURE_ECX_SMX
1306 | X86_CPUID_FEATURE_ECX_EST
1307 | X86_CPUID_FEATURE_ECX_TM2
1308 | X86_CPUID_FEATURE_ECX_CNTXID
1309 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1310 | X86_CPUID_FEATURE_ECX_PDCM
1311 | X86_CPUID_FEATURE_ECX_DCA
1312 | X86_CPUID_FEATURE_ECX_X2APIC
1313 )));
1314 /* do the compare */
1315 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
1316 {
1317 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1318 LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
1319 "Saved=%.*Rhxs\n"
1320 "Real =%.*Rhxs\n",
1321 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1322 sizeof(au32CpuId), au32CpuId));
1323 else
1324 {
1325 LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
1326 "Saved=%.*Rhxs\n"
1327 "Real =%.*Rhxs\n",
1328 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1329 sizeof(au32CpuId), au32CpuId));
1330 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1331 }
1332 }
1333 }
1334
1335 return rc;
1336}
1337
1338
1339/**
1340 * @copydoc FNSSMINTLOADPREP
1341 */
1342static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
1343{
1344 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
1345 return VINF_SUCCESS;
1346
1347 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
1348 if (pVM->cpum.s.fPendingRestore)
1349 {
1350 LogRel(("CPUM: Missing state!\n"));
1351 return VERR_INTERNAL_ERROR_2;
1352 }
1353
1354 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
1355 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1356 {
1357 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1358
1359 /* Notify PGM of the NXE states in case they've changed. */
1360 PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
1361
1362 /* Cache the local APIC base from the APIC device. During init. this is done in CPUMR3ResetCpu(). */
1363 PDMApicGetBase(pVCpu, &pVCpu->cpum.s.Guest.msrApicBase);
1364
1365 /* During init. this is done in CPUMR3InitCompleted(). */
1366 if (fSupportsLongMode)
1367 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
1368 }
1369 return VINF_SUCCESS;
1370}
1371
1372
1373/**
1374 * Checks if the CPUM state restore is still pending.
1375 *
1376 * @returns true / false.
1377 * @param pVM Pointer to the VM.
1378 */
1379VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
1380{
1381 return pVM->cpum.s.fPendingRestore;
1382}
1383
1384
1385/**
1386 * Formats the EFLAGS value into mnemonics.
1387 *
1388 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1389 * @param efl The EFLAGS value.
1390 */
1391static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1392{
1393 /*
1394 * Format the flags.
1395 */
1396 static const struct
1397 {
1398 const char *pszSet; const char *pszClear; uint32_t fFlag;
1399 } s_aFlags[] =
1400 {
1401 { "vip",NULL, X86_EFL_VIP },
1402 { "vif",NULL, X86_EFL_VIF },
1403 { "ac", NULL, X86_EFL_AC },
1404 { "vm", NULL, X86_EFL_VM },
1405 { "rf", NULL, X86_EFL_RF },
1406 { "nt", NULL, X86_EFL_NT },
1407 { "ov", "nv", X86_EFL_OF },
1408 { "dn", "up", X86_EFL_DF },
1409 { "ei", "di", X86_EFL_IF },
1410 { "tf", NULL, X86_EFL_TF },
1411 { "nt", "pl", X86_EFL_SF },
1412 { "nz", "zr", X86_EFL_ZF },
1413 { "ac", "na", X86_EFL_AF },
1414 { "po", "pe", X86_EFL_PF },
1415 { "cy", "nc", X86_EFL_CF },
1416 };
1417 char *psz = pszEFlags;
1418 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1419 {
1420 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1421 if (pszAdd)
1422 {
1423 strcpy(psz, pszAdd);
1424 psz += strlen(pszAdd);
1425 *psz++ = ' ';
1426 }
1427 }
1428 psz[-1] = '\0';
1429}
1430
1431
1432/**
1433 * Formats a full register dump.
1434 *
1435 * @param pVM Pointer to the VM.
1436 * @param pCtx The context to format.
1437 * @param pCtxCore The context core to format.
1438 * @param pHlp Output functions.
1439 * @param enmType The dump type.
1440 * @param pszPrefix Register name prefix.
1441 */
1442static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
1443 const char *pszPrefix)
1444{
1445 NOREF(pVM);
1446
1447 /*
1448 * Format the EFLAGS.
1449 */
1450 uint32_t efl = pCtxCore->eflags.u32;
1451 char szEFlags[80];
1452 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1453
1454 /*
1455 * Format the registers.
1456 */
1457 switch (enmType)
1458 {
1459 case CPUMDUMPTYPE_TERSE:
1460 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1461 pHlp->pfnPrintf(pHlp,
1462 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1463 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1464 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1465 "%sr14=%016RX64 %sr15=%016RX64\n"
1466 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1467 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1468 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1469 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1470 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1471 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1472 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1473 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1474 else
1475 pHlp->pfnPrintf(pHlp,
1476 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1477 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1478 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1479 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1480 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1481 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1482 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1483 break;
1484
1485 case CPUMDUMPTYPE_DEFAULT:
1486 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1487 pHlp->pfnPrintf(pHlp,
1488 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1489 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1490 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1491 "%sr14=%016RX64 %sr15=%016RX64\n"
1492 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1493 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1494 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1495 ,
1496 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1497 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1498 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1499 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1500 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1501 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1502 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1503 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1504 else
1505 pHlp->pfnPrintf(pHlp,
1506 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1507 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1508 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1509 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1510 ,
1511 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1512 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1513 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1514 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1515 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1516 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1517 break;
1518
1519 case CPUMDUMPTYPE_VERBOSE:
1520 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1521 pHlp->pfnPrintf(pHlp,
1522 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1523 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1524 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1525 "%sr14=%016RX64 %sr15=%016RX64\n"
1526 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1527 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1528 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1529 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1530 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1531 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1532 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1533 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1534 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1535 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1536 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1537 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1538 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1539 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1540 ,
1541 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1542 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1543 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1544 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1545 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1546 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1547 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1548 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1549 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1550 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1551 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1552 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1553 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1554 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1555 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1556 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1557 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1558 else
1559 pHlp->pfnPrintf(pHlp,
1560 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1561 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1562 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1563 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1564 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1565 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1566 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1567 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1568 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1569 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1570 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1571 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1572 ,
1573 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1574 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1575 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1576 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1577 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1578 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1579 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1580 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1581 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1582 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1583 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1584 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1585
1586 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1587 pHlp->pfnPrintf(pHlp,
1588 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1589 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
1590 ,
1591 pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
1592 pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
1593 pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
1594 pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
1595 );
1596 unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
1597 for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
1598 {
1599 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
1600 unsigned uTag = pFpuCtx->FTW & (1 << iFPR) ? 1 : 0;
1601 char chSign = pFpuCtx->aRegs[0].au16[4] & 0x8000 ? '-' : '+';
1602 unsigned iInteger = (unsigned)(pFpuCtx->aRegs[0].au64[0] >> 63);
1603 uint64_t u64Fraction = pFpuCtx->aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
1604 unsigned uExponent = pFpuCtx->aRegs[0].au16[4] & 0x7fff;
1605 /** @todo This isn't entirenly correct and needs more work! */
1606 pHlp->pfnPrintf(pHlp,
1607 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
1608 pszPrefix, iST, pszPrefix, iFPR,
1609 pFpuCtx->aRegs[0].au16[4], pFpuCtx->aRegs[0].au32[1], pFpuCtx->aRegs[0].au32[0],
1610 uTag, chSign, iInteger, u64Fraction, uExponent);
1611 if (pFpuCtx->aRegs[0].au16[5] || pFpuCtx->aRegs[0].au16[6] || pFpuCtx->aRegs[0].au16[7])
1612 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
1613 pFpuCtx->aRegs[0].au16[5], pFpuCtx->aRegs[0].au16[6], pFpuCtx->aRegs[0].au16[7]);
1614 else
1615 pHlp->pfnPrintf(pHlp, "\n");
1616 }
1617 for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pFpuCtx->aXMM); iXMM++)
1618 pHlp->pfnPrintf(pHlp,
1619 iXMM & 1
1620 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
1621 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
1622 pszPrefix, iXMM, iXMM < 10 ? " " : "",
1623 pFpuCtx->aXMM[iXMM].au32[3],
1624 pFpuCtx->aXMM[iXMM].au32[2],
1625 pFpuCtx->aXMM[iXMM].au32[1],
1626 pFpuCtx->aXMM[iXMM].au32[0]);
1627 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
1628 if (pFpuCtx->au32RsrvdRest[i])
1629 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
1630 pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
1631
1632 pHlp->pfnPrintf(pHlp,
1633 "%sEFER =%016RX64\n"
1634 "%sPAT =%016RX64\n"
1635 "%sSTAR =%016RX64\n"
1636 "%sCSTAR =%016RX64\n"
1637 "%sLSTAR =%016RX64\n"
1638 "%sSFMASK =%016RX64\n"
1639 "%sKERNELGSBASE =%016RX64\n",
1640 pszPrefix, pCtx->msrEFER,
1641 pszPrefix, pCtx->msrPAT,
1642 pszPrefix, pCtx->msrSTAR,
1643 pszPrefix, pCtx->msrCSTAR,
1644 pszPrefix, pCtx->msrLSTAR,
1645 pszPrefix, pCtx->msrSFMASK,
1646 pszPrefix, pCtx->msrKERNELGSBASE);
1647 break;
1648 }
1649}
1650
1651
1652/**
1653 * Display all cpu states and any other cpum info.
1654 *
1655 * @param pVM Pointer to the VM.
1656 * @param pHlp The info helper functions.
1657 * @param pszArgs Arguments, ignored.
1658 */
1659static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1660{
1661 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1662 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1663 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1664 cpumR3InfoHost(pVM, pHlp, pszArgs);
1665}
1666
1667
1668/**
1669 * Parses the info argument.
1670 *
1671 * The argument starts with 'verbose', 'terse' or 'default' and then
1672 * continues with the comment string.
1673 *
1674 * @param pszArgs The pointer to the argument string.
1675 * @param penmType Where to store the dump type request.
1676 * @param ppszComment Where to store the pointer to the comment string.
1677 */
1678static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1679{
1680 if (!pszArgs)
1681 {
1682 *penmType = CPUMDUMPTYPE_DEFAULT;
1683 *ppszComment = "";
1684 }
1685 else
1686 {
1687 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
1688 {
1689 pszArgs += 7;
1690 *penmType = CPUMDUMPTYPE_VERBOSE;
1691 }
1692 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
1693 {
1694 pszArgs += 5;
1695 *penmType = CPUMDUMPTYPE_TERSE;
1696 }
1697 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
1698 {
1699 pszArgs += 7;
1700 *penmType = CPUMDUMPTYPE_DEFAULT;
1701 }
1702 else
1703 *penmType = CPUMDUMPTYPE_DEFAULT;
1704 *ppszComment = RTStrStripL(pszArgs);
1705 }
1706}
1707
1708
1709/**
1710 * Display the guest cpu state.
1711 *
1712 * @param pVM Pointer to the VM.
1713 * @param pHlp The info helper functions.
1714 * @param pszArgs Arguments, ignored.
1715 */
1716static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1717{
1718 CPUMDUMPTYPE enmType;
1719 const char *pszComment;
1720 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1721
1722 /* @todo SMP support! */
1723 PVMCPU pVCpu = VMMGetCpu(pVM);
1724 if (!pVCpu)
1725 pVCpu = &pVM->aCpus[0];
1726
1727 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
1728
1729 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1730 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1731}
1732
1733
1734/**
1735 * Display the current guest instruction
1736 *
1737 * @param pVM Pointer to the VM.
1738 * @param pHlp The info helper functions.
1739 * @param pszArgs Arguments, ignored.
1740 */
1741static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1742{
1743 NOREF(pszArgs);
1744
1745 /** @todo SMP support! */
1746 PVMCPU pVCpu = VMMGetCpu(pVM);
1747 if (!pVCpu)
1748 pVCpu = &pVM->aCpus[0];
1749
1750 char szInstruction[256];
1751 szInstruction[0] = '\0';
1752 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
1753 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1754}
1755
1756
1757/**
1758 * Display the hypervisor cpu state.
1759 *
1760 * @param pVM Pointer to the VM.
1761 * @param pHlp The info helper functions.
1762 * @param pszArgs Arguments, ignored.
1763 */
1764static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1765{
1766 CPUMDUMPTYPE enmType;
1767 const char *pszComment;
1768 /* @todo SMP */
1769 PVMCPU pVCpu = &pVM->aCpus[0];
1770
1771 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1772 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1773 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
1774 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1775}
1776
1777
1778/**
1779 * Display the host cpu state.
1780 *
1781 * @param pVM Pointer to the VM.
1782 * @param pHlp The info helper functions.
1783 * @param pszArgs Arguments, ignored.
1784 */
1785static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1786{
1787 CPUMDUMPTYPE enmType;
1788 const char *pszComment;
1789 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1790 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1791
1792 /*
1793 * Format the EFLAGS.
1794 */
1795 /* @todo SMP */
1796 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1797#if HC_ARCH_BITS == 32
1798 uint32_t efl = pCtx->eflags.u32;
1799#else
1800 uint64_t efl = pCtx->rflags;
1801#endif
1802 char szEFlags[80];
1803 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1804
1805 /*
1806 * Format the registers.
1807 */
1808#if HC_ARCH_BITS == 32
1809# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1810 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1811# endif
1812 {
1813 pHlp->pfnPrintf(pHlp,
1814 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1815 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1816 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1817 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1818 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1819 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1820 ,
1821 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1822 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1823 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
1824 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1825 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1826 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
1827 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1828 }
1829# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1830 else
1831# endif
1832#endif
1833#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1834 {
1835 pHlp->pfnPrintf(pHlp,
1836 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1837 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1838 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1839 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1840 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1841 "r14=%016RX64 r15=%016RX64\n"
1842 "iopl=%d %31s\n"
1843 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1844 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1845 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1846 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1847 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1848 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1849 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1850 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1851 ,
1852 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1853 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1854 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1855 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1856 pCtx->r11, pCtx->r12, pCtx->r13,
1857 pCtx->r14, pCtx->r15,
1858 X86_EFL_GET_IOPL(efl), szEFlags,
1859 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
1860 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1861 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1862 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1863 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1864 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1865 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1866 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1867 }
1868#endif
1869}
1870
1871/**
1872 * Structure used when disassembling and instructions in DBGF.
1873 * This is used so the reader function can get the stuff it needs.
1874 */
1875typedef struct CPUMDISASSTATE
1876{
1877 /** Pointer to the CPU structure. */
1878 PDISCPUSTATE pCpu;
1879 /** Pointer to the VM. */
1880 PVM pVM;
1881 /** Pointer to the VMCPU. */
1882 PVMCPU pVCpu;
1883 /** Pointer to the first byte in the segment. */
1884 RTGCUINTPTR GCPtrSegBase;
1885 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
1886 RTGCUINTPTR GCPtrSegEnd;
1887 /** The size of the segment minus 1. */
1888 RTGCUINTPTR cbSegLimit;
1889 /** Pointer to the current page - R3 Ptr. */
1890 void const *pvPageR3;
1891 /** Pointer to the current page - GC Ptr. */
1892 RTGCPTR pvPageGC;
1893 /** The lock information that PGMPhysReleasePageMappingLock needs. */
1894 PGMPAGEMAPLOCK PageMapLock;
1895 /** Whether the PageMapLock is valid or not. */
1896 bool fLocked;
1897 /** 64 bits mode or not. */
1898 bool f64Bits;
1899} CPUMDISASSTATE, *PCPUMDISASSTATE;
1900
1901
1902/**
1903 * @callback_method_impl{FNDISREADBYTES}
1904 */
1905static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
1906{
1907 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
1908 for (;;)
1909 {
1910 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
1911
1912 /*
1913 * Need to update the page translation?
1914 */
1915 if ( !pState->pvPageR3
1916 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
1917 {
1918 int rc = VINF_SUCCESS;
1919
1920 /* translate the address */
1921 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
1922 if ( !HMIsEnabled(pState->pVM)
1923 && MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
1924 {
1925 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
1926 if (!pState->pvPageR3)
1927 rc = VERR_INVALID_POINTER;
1928 }
1929 else
1930 {
1931 /* Release mapping lock previously acquired. */
1932 if (pState->fLocked)
1933 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
1934 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
1935 pState->fLocked = RT_SUCCESS_NP(rc);
1936 }
1937 if (RT_FAILURE(rc))
1938 {
1939 pState->pvPageR3 = NULL;
1940 return rc;
1941 }
1942 }
1943
1944 /*
1945 * Check the segment limit.
1946 */
1947 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
1948 return VERR_OUT_OF_SELECTOR_BOUNDS;
1949
1950 /*
1951 * Calc how much we can read.
1952 */
1953 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
1954 if (!pState->f64Bits)
1955 {
1956 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
1957 if (cb > cbSeg && cbSeg)
1958 cb = cbSeg;
1959 }
1960 if (cb > cbMaxRead)
1961 cb = cbMaxRead;
1962
1963 /*
1964 * Read and advance or exit.
1965 */
1966 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
1967 offInstr += (uint8_t)cb;
1968 if (cb >= cbMinRead)
1969 {
1970 pDis->cbCachedInstr = offInstr;
1971 return VINF_SUCCESS;
1972 }
1973 cbMinRead -= (uint8_t)cb;
1974 cbMaxRead -= (uint8_t)cb;
1975 }
1976}
1977
1978
1979/**
1980 * Disassemble an instruction and return the information in the provided structure.
1981 *
1982 * @returns VBox status code.
1983 * @param pVM Pointer to the VM.
1984 * @param pVCpu Pointer to the VMCPU.
1985 * @param pCtx Pointer to the guest CPU context.
1986 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
1987 * @param pCpu Disassembly state.
1988 * @param pszPrefix String prefix for logging (debug only).
1989 *
1990 */
1991VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
1992{
1993 CPUMDISASSTATE State;
1994 int rc;
1995
1996 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
1997 State.pCpu = pCpu;
1998 State.pvPageGC = 0;
1999 State.pvPageR3 = NULL;
2000 State.pVM = pVM;
2001 State.pVCpu = pVCpu;
2002 State.fLocked = false;
2003 State.f64Bits = false;
2004
2005 /*
2006 * Get selector information.
2007 */
2008 DISCPUMODE enmDisCpuMode;
2009 if ( (pCtx->cr0 & X86_CR0_PE)
2010 && pCtx->eflags.Bits.u1VM == 0)
2011 {
2012 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2013 {
2014# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2015 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
2016# endif
2017 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2018 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
2019 }
2020 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
2021 State.GCPtrSegBase = pCtx->cs.u64Base;
2022 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
2023 State.cbSegLimit = pCtx->cs.u32Limit;
2024 enmDisCpuMode = (State.f64Bits)
2025 ? DISCPUMODE_64BIT
2026 : pCtx->cs.Attr.n.u1DefBig
2027 ? DISCPUMODE_32BIT
2028 : DISCPUMODE_16BIT;
2029 }
2030 else
2031 {
2032 /* real or V86 mode */
2033 enmDisCpuMode = DISCPUMODE_16BIT;
2034 State.GCPtrSegBase = pCtx->cs.Sel * 16;
2035 State.GCPtrSegEnd = 0xFFFFFFFF;
2036 State.cbSegLimit = 0xFFFFFFFF;
2037 }
2038
2039 /*
2040 * Disassemble the instruction.
2041 */
2042 uint32_t cbInstr;
2043#ifndef LOG_ENABLED
2044 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
2045 if (RT_SUCCESS(rc))
2046 {
2047#else
2048 char szOutput[160];
2049 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
2050 pCpu, &cbInstr, szOutput, sizeof(szOutput));
2051 if (RT_SUCCESS(rc))
2052 {
2053 /* log it */
2054 if (pszPrefix)
2055 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2056 else
2057 Log(("%s", szOutput));
2058#endif
2059 rc = VINF_SUCCESS;
2060 }
2061 else
2062 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
2063
2064 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2065 if (State.fLocked)
2066 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2067
2068 return rc;
2069}
2070
2071
2072
2073/**
2074 * API for controlling a few of the CPU features found in CR4.
2075 *
2076 * Currently only X86_CR4_TSD is accepted as input.
2077 *
2078 * @returns VBox status code.
2079 *
2080 * @param pVM Pointer to the VM.
2081 * @param fOr The CR4 OR mask.
2082 * @param fAnd The CR4 AND mask.
2083 */
2084VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2085{
2086 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2087 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2088
2089 pVM->cpum.s.CR4.OrMask &= fAnd;
2090 pVM->cpum.s.CR4.OrMask |= fOr;
2091
2092 return VINF_SUCCESS;
2093}
2094
2095
2096/**
2097 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
2098 *
2099 * Only REM should ever call this function!
2100 *
2101 * @returns The changed flags.
2102 * @param pVCpu Pointer to the VMCPU.
2103 * @param puCpl Where to return the current privilege level (CPL).
2104 */
2105VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
2106{
2107 Assert(!pVCpu->cpum.s.fRawEntered);
2108 Assert(!pVCpu->cpum.s.fRemEntered);
2109
2110 /*
2111 * Get the CPL first.
2112 */
2113 *puCpl = CPUMGetGuestCPL(pVCpu);
2114
2115 /*
2116 * Get and reset the flags.
2117 */
2118 uint32_t fFlags = pVCpu->cpum.s.fChanged;
2119 pVCpu->cpum.s.fChanged = 0;
2120
2121 /** @todo change the switcher to use the fChanged flags. */
2122 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
2123 {
2124 fFlags |= CPUM_CHANGED_FPU_REM;
2125 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
2126 }
2127
2128 pVCpu->cpum.s.fRemEntered = true;
2129 return fFlags;
2130}
2131
2132
2133/**
2134 * Leaves REM.
2135 *
2136 * @param pVCpu Pointer to the VMCPU.
2137 * @param fNoOutOfSyncSels This is @c false if there are out of sync
2138 * registers.
2139 */
2140VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
2141{
2142 Assert(!pVCpu->cpum.s.fRawEntered);
2143 Assert(pVCpu->cpum.s.fRemEntered);
2144
2145 pVCpu->cpum.s.fRemEntered = false;
2146}
2147
2148
2149/**
2150 * Called when the ring-3 init phase completes.
2151 *
2152 * @returns VBox status code.
2153 * @param pVM Pointer to the VM.
2154 */
2155VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM)
2156{
2157 /*
2158 * Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
2159 * Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
2160 */
2161 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2162 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2163 {
2164 PVMCPU pVCpu = &pVM->aCpus[i];
2165
2166 /* Cache the APIC base (from the APIC device) once it has been initialized. */
2167 PDMApicGetBase(pVCpu, &pVCpu->cpum.s.Guest.msrApicBase);
2168 Log(("CPUMR3InitCompleted pVM=%p APIC base[%u]=%RX64\n", pVM, (unsigned)i, pVCpu->cpum.s.Guest.msrApicBase));
2169
2170 /* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
2171 if (fSupportsLongMode)
2172 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
2173 }
2174 return VINF_SUCCESS;
2175}
2176
2177
2178/**
2179 * Called when the ring-0 init phases comleted.
2180 *
2181 * @param pVM Pointer to the VM.
2182 */
2183VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
2184{
2185 /*
2186 * Log the cpuid.
2187 */
2188 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
2189 RTCPUSET OnlineSet;
2190 LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
2191 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
2192 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
2193 RTCPUID cCores = RTMpGetCoreCount();
2194 if (cCores)
2195 LogRel(("Physical host cores: %u\n", (unsigned)cCores));
2196 LogRel(("************************* CPUID dump ************************\n"));
2197 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
2198 LogRel(("\n"));
2199 DBGFR3_INFO_LOG(pVM, "cpuid", "verbose"); /* macro */
2200 RTLogRelSetBuffering(fOldBuffered);
2201 LogRel(("******************** End of CPUID dump **********************\n"));
2202}
2203
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