VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 44847

Last change on this file since 44847 was 44399, checked in by vboxsync, 12 years ago

DBGF,DBGC,++: PVM -> PUVM. Some refactoring and cleanup as well.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 212.5 KB
Line 
1/* $Id: CPUM.cpp 44399 2013-01-27 21:12:53Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_CPUM
38#include <VBox/vmm/cpum.h>
39#include <VBox/vmm/cpumdis.h>
40#include <VBox/vmm/cpumctx-v1_6.h>
41#include <VBox/vmm/pgm.h>
42#include <VBox/vmm/pdmapi.h>
43#include <VBox/vmm/mm.h>
44#include <VBox/vmm/selm.h>
45#include <VBox/vmm/dbgf.h>
46#include <VBox/vmm/patm.h>
47#include <VBox/vmm/hm.h>
48#include <VBox/vmm/ssm.h>
49#include "CPUMInternal.h"
50#include <VBox/vmm/vm.h>
51
52#include <VBox/param.h>
53#include <VBox/dis.h>
54#include <VBox/err.h>
55#include <VBox/log.h>
56#include <iprt/assert.h>
57#include <iprt/asm-amd64-x86.h>
58#include <iprt/string.h>
59#include <iprt/mp.h>
60#include <iprt/cpuset.h>
61#include "internal/pgm.h"
62
63
64/*******************************************************************************
65* Defined Constants And Macros *
66*******************************************************************************/
67/** The current saved state version. */
68#define CPUM_SAVED_STATE_VERSION 14
69/** The current saved state version before using SSMR3PutStruct. */
70#define CPUM_SAVED_STATE_VERSION_MEM 13
71/** The saved state version before introducing the MSR size field. */
72#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
73/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
74 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
75#define CPUM_SAVED_STATE_VERSION_VER3_2 11
76/** The saved state version of 3.0 and 3.1 trunk before the teleportation
77 * changes. */
78#define CPUM_SAVED_STATE_VERSION_VER3_0 10
79/** The saved state version for the 2.1 trunk before the MSR changes. */
80#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
81/** The saved state version of 2.0, used for backwards compatibility. */
82#define CPUM_SAVED_STATE_VERSION_VER2_0 8
83/** The saved state version of 1.6, used for backwards compatibility. */
84#define CPUM_SAVED_STATE_VERSION_VER1_6 6
85
86
87/**
88 * This was used in the saved state up to the early life of version 14.
89 *
90 * It indicates that we may have some out-of-sync hidden segement registers.
91 * It is only relevant for raw-mode.
92 */
93#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
94
95
96/*******************************************************************************
97* Structures and Typedefs *
98*******************************************************************************/
99
100/**
101 * What kind of cpu info dump to perform.
102 */
103typedef enum CPUMDUMPTYPE
104{
105 CPUMDUMPTYPE_TERSE,
106 CPUMDUMPTYPE_DEFAULT,
107 CPUMDUMPTYPE_VERBOSE
108} CPUMDUMPTYPE;
109/** Pointer to a cpu info dump type. */
110typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
111
112
113/*******************************************************************************
114* Internal Functions *
115*******************************************************************************/
116static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
117static int cpumR3CpuIdInit(PVM pVM);
118static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
119static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
120static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
121static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
122static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
123static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
124static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
125static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
126static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
127static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
128static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
129
130
131/*******************************************************************************
132* Global Variables *
133*******************************************************************************/
134/** Saved state field descriptors for CPUMCTX. */
135static const SSMFIELD g_aCpumCtxFields[] =
136{
137 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
138 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
139 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
140 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
141 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
142 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
143 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
144 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
145 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
146 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
147 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
148 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
149 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
150 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
151 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
152 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
153 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
154 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
155 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
156 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
157 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
158 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
159 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
160 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
161 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
162 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
163 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
164 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
165 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
166 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
167 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
168 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
169 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
170 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
171 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
172 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
173 SSMFIELD_ENTRY( CPUMCTX, rdi),
174 SSMFIELD_ENTRY( CPUMCTX, rsi),
175 SSMFIELD_ENTRY( CPUMCTX, rbp),
176 SSMFIELD_ENTRY( CPUMCTX, rax),
177 SSMFIELD_ENTRY( CPUMCTX, rbx),
178 SSMFIELD_ENTRY( CPUMCTX, rdx),
179 SSMFIELD_ENTRY( CPUMCTX, rcx),
180 SSMFIELD_ENTRY( CPUMCTX, rsp),
181 SSMFIELD_ENTRY( CPUMCTX, rflags),
182 SSMFIELD_ENTRY( CPUMCTX, rip),
183 SSMFIELD_ENTRY( CPUMCTX, r8),
184 SSMFIELD_ENTRY( CPUMCTX, r9),
185 SSMFIELD_ENTRY( CPUMCTX, r10),
186 SSMFIELD_ENTRY( CPUMCTX, r11),
187 SSMFIELD_ENTRY( CPUMCTX, r12),
188 SSMFIELD_ENTRY( CPUMCTX, r13),
189 SSMFIELD_ENTRY( CPUMCTX, r14),
190 SSMFIELD_ENTRY( CPUMCTX, r15),
191 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
192 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
193 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
194 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
195 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
196 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
197 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
198 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
199 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
200 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
201 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
202 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
203 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
204 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
205 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
206 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
207 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
208 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
209 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
210 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
211 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
212 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
213 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
214 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
215 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
216 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
217 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
218 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
219 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
220 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
221 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
222 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
223 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
224 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
225 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
226 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
227 SSMFIELD_ENTRY( CPUMCTX, cr0),
228 SSMFIELD_ENTRY( CPUMCTX, cr2),
229 SSMFIELD_ENTRY( CPUMCTX, cr3),
230 SSMFIELD_ENTRY( CPUMCTX, cr4),
231 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
232 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
233 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
234 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
235 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
236 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
237 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
238 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
239 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
240 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
241 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
242 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
243 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
244 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
245 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
246 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
247 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
248 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
249 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
250 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
251 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
252 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
253 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
254 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
255 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
256 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
257 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
258 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
259 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
260 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
261 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
262 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
263 SSMFIELD_ENTRY_TERM()
264};
265
266/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
267 * registeres changed. */
268static const SSMFIELD g_aCpumCtxFieldsMem[] =
269{
270 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
271 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
272 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
273 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
274 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
275 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
276 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
277 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
278 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
279 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
280 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
281 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
282 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
283 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
284 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
285 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
286 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
287 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
288 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
289 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
290 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
291 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
292 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
293 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
294 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
295 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
296 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
297 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
298 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
299 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
300 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
301 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
302 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
303 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
304 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
305 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
306 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
307 SSMFIELD_ENTRY( CPUMCTX, rdi),
308 SSMFIELD_ENTRY( CPUMCTX, rsi),
309 SSMFIELD_ENTRY( CPUMCTX, rbp),
310 SSMFIELD_ENTRY( CPUMCTX, rax),
311 SSMFIELD_ENTRY( CPUMCTX, rbx),
312 SSMFIELD_ENTRY( CPUMCTX, rdx),
313 SSMFIELD_ENTRY( CPUMCTX, rcx),
314 SSMFIELD_ENTRY( CPUMCTX, rsp),
315 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
316 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
317 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
318 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
319 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
320 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
321 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
322 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
323 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
324 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
325 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
326 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
327 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
328 SSMFIELD_ENTRY( CPUMCTX, rflags),
329 SSMFIELD_ENTRY( CPUMCTX, rip),
330 SSMFIELD_ENTRY( CPUMCTX, r8),
331 SSMFIELD_ENTRY( CPUMCTX, r9),
332 SSMFIELD_ENTRY( CPUMCTX, r10),
333 SSMFIELD_ENTRY( CPUMCTX, r11),
334 SSMFIELD_ENTRY( CPUMCTX, r12),
335 SSMFIELD_ENTRY( CPUMCTX, r13),
336 SSMFIELD_ENTRY( CPUMCTX, r14),
337 SSMFIELD_ENTRY( CPUMCTX, r15),
338 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
339 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
340 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
341 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
342 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
343 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
344 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
345 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
346 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
347 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
348 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
349 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
350 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
351 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
352 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
353 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
354 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
355 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
356 SSMFIELD_ENTRY( CPUMCTX, cr0),
357 SSMFIELD_ENTRY( CPUMCTX, cr2),
358 SSMFIELD_ENTRY( CPUMCTX, cr3),
359 SSMFIELD_ENTRY( CPUMCTX, cr4),
360 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
361 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
362 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
363 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
364 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
365 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
366 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
367 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
368 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
369 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
370 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
371 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
372 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
373 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
374 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
375 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
376 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
377 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
378 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
379 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
380 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
381 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
382 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
383 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
384 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
385 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
386 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
387 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
388 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
389 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
390 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
391 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
392 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
393 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
394 SSMFIELD_ENTRY_TERM()
395};
396
397/** Saved state field descriptors for CPUMCTX_VER1_6. */
398static const SSMFIELD g_aCpumCtxFieldsV16[] =
399{
400 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
401 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
402 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
403 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
404 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
405 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
406 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
407 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
408 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
409 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
410 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
411 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
412 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
413 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
414 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
415 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
416 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
417 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
418 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
419 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
420 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
421 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
422 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
423 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
424 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
425 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
426 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
427 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
428 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
429 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
430 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
431 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
432 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
433 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
434 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
435 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
436 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
437 SSMFIELD_ENTRY( CPUMCTX, rdi),
438 SSMFIELD_ENTRY( CPUMCTX, rsi),
439 SSMFIELD_ENTRY( CPUMCTX, rbp),
440 SSMFIELD_ENTRY( CPUMCTX, rax),
441 SSMFIELD_ENTRY( CPUMCTX, rbx),
442 SSMFIELD_ENTRY( CPUMCTX, rdx),
443 SSMFIELD_ENTRY( CPUMCTX, rcx),
444 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
445 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
446 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
447 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
448 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
449 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
450 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
451 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
452 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
453 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
454 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
455 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
456 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
457 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
458 SSMFIELD_ENTRY( CPUMCTX, rflags),
459 SSMFIELD_ENTRY( CPUMCTX, rip),
460 SSMFIELD_ENTRY( CPUMCTX, r8),
461 SSMFIELD_ENTRY( CPUMCTX, r9),
462 SSMFIELD_ENTRY( CPUMCTX, r10),
463 SSMFIELD_ENTRY( CPUMCTX, r11),
464 SSMFIELD_ENTRY( CPUMCTX, r12),
465 SSMFIELD_ENTRY( CPUMCTX, r13),
466 SSMFIELD_ENTRY( CPUMCTX, r14),
467 SSMFIELD_ENTRY( CPUMCTX, r15),
468 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
469 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
470 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
471 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
472 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
473 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
474 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
475 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
476 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
477 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
478 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
479 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
480 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
481 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
482 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
483 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
484 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
485 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
486 SSMFIELD_ENTRY( CPUMCTX, cr0),
487 SSMFIELD_ENTRY( CPUMCTX, cr2),
488 SSMFIELD_ENTRY( CPUMCTX, cr3),
489 SSMFIELD_ENTRY( CPUMCTX, cr4),
490 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
491 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
492 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
493 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
494 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
495 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
496 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
497 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
498 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
499 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
500 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
501 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
502 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
503 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
504 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
505 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
506 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
507 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
508 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
509 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
510 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
511 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
512 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
513 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
514 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
515 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
516 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
517 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
518 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
519 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
520 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
521 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
522 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
523 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
524 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
525 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
526 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
527 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
528 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
529 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
530 SSMFIELD_ENTRY_TERM()
531};
532
533
534/**
535 * Initializes the CPUM.
536 *
537 * @returns VBox status code.
538 * @param pVM Pointer to the VM.
539 */
540VMMR3DECL(int) CPUMR3Init(PVM pVM)
541{
542 LogFlow(("CPUMR3Init\n"));
543
544 /*
545 * Assert alignment and sizes.
546 */
547 AssertCompileMemberAlignment(VM, cpum.s, 32);
548 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
549 AssertCompileSizeAlignment(CPUMCTX, 64);
550 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
551 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
552 AssertCompileMemberAlignment(VM, cpum, 64);
553 AssertCompileMemberAlignment(VM, aCpus, 64);
554 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
555 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
556
557 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
558 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
559 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
560
561 /* Calculate the offset from CPUMCPU to CPUM. */
562 for (VMCPUID i = 0; i < pVM->cCpus; i++)
563 {
564 PVMCPU pVCpu = &pVM->aCpus[i];
565
566 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
567 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
568 }
569
570 /*
571 * Check that the CPU supports the minimum features we require.
572 */
573 if (!ASMHasCpuId())
574 {
575 Log(("The CPU doesn't support CPUID!\n"));
576 return VERR_UNSUPPORTED_CPU;
577 }
578 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
579 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
580
581 /* Setup the CR4 AND and OR masks used in the switcher */
582 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
583 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
584 {
585 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
586 /* No FXSAVE implies no SSE */
587 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
588 pVM->cpum.s.CR4.OrMask = 0;
589 }
590 else
591 {
592 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
593 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
594 }
595
596 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
597 {
598 Log(("The CPU doesn't support MMX!\n"));
599 return VERR_UNSUPPORTED_CPU;
600 }
601 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
602 {
603 Log(("The CPU doesn't support TSC!\n"));
604 return VERR_UNSUPPORTED_CPU;
605 }
606 /* Bogus on AMD? */
607 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
608 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
609
610 /*
611 * Detect the host CPU vendor.
612 * (The guest CPU vendor is re-detected later on.)
613 */
614 uint32_t uEAX, uEBX, uECX, uEDX;
615 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
616 pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
617 pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
618
619 /*
620 * Setup hypervisor startup values.
621 */
622
623 /*
624 * Register saved state data item.
625 */
626 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
627 NULL, cpumR3LiveExec, NULL,
628 NULL, cpumR3SaveExec, NULL,
629 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
630 if (RT_FAILURE(rc))
631 return rc;
632
633 /*
634 * Register info handlers and registers with the debugger facility.
635 */
636 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
637 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
638 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
639 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
640 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
641 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
642
643 rc = cpumR3DbgInit(pVM);
644 if (RT_FAILURE(rc))
645 return rc;
646
647 /*
648 * Initialize the Guest CPUID state.
649 */
650 rc = cpumR3CpuIdInit(pVM);
651 if (RT_FAILURE(rc))
652 return rc;
653 CPUMR3Reset(pVM);
654 return VINF_SUCCESS;
655}
656
657
658/**
659 * Detect the CPU vendor give n the
660 *
661 * @returns The vendor.
662 * @param uEAX EAX from CPUID(0).
663 * @param uEBX EBX from CPUID(0).
664 * @param uECX ECX from CPUID(0).
665 * @param uEDX EDX from CPUID(0).
666 */
667static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
668{
669 if (ASMIsValidStdRange(uEAX))
670 {
671 if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
672 return CPUMCPUVENDOR_AMD;
673
674 if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
675 return CPUMCPUVENDOR_INTEL;
676
677 if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
678 return CPUMCPUVENDOR_VIA;
679
680 /** @todo detect the other buggers... */
681 }
682
683 return CPUMCPUVENDOR_UNKNOWN;
684}
685
686
687/**
688 * Fetches overrides for a CPUID leaf.
689 *
690 * @returns VBox status code.
691 * @param pLeaf The leaf to load the overrides into.
692 * @param pCfgNode The CFGM node containing the overrides
693 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
694 * @param iLeaf The CPUID leaf number.
695 */
696static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
697{
698 PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
699 if (pLeafNode)
700 {
701 uint32_t u32;
702 int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
703 if (RT_SUCCESS(rc))
704 pLeaf->eax = u32;
705 else
706 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
707
708 rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
709 if (RT_SUCCESS(rc))
710 pLeaf->ebx = u32;
711 else
712 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
713
714 rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
715 if (RT_SUCCESS(rc))
716 pLeaf->ecx = u32;
717 else
718 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
719
720 rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
721 if (RT_SUCCESS(rc))
722 pLeaf->edx = u32;
723 else
724 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
725
726 }
727 return VINF_SUCCESS;
728}
729
730
731/**
732 * Load the overrides for a set of CPUID leaves.
733 *
734 * @returns VBox status code.
735 * @param paLeaves The leaf array.
736 * @param cLeaves The number of leaves.
737 * @param uStart The start leaf number.
738 * @param pCfgNode The CFGM node containing the overrides
739 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
740 */
741static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
742{
743 for (uint32_t i = 0; i < cLeaves; i++)
744 {
745 int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
746 if (RT_FAILURE(rc))
747 return rc;
748 }
749
750 return VINF_SUCCESS;
751}
752
753/**
754 * Init a set of host CPUID leaves.
755 *
756 * @returns VBox status code.
757 * @param paLeaves The leaf array.
758 * @param cLeaves The number of leaves.
759 * @param uStart The start leaf number.
760 * @param pCfgNode The /CPUM/HostCPUID/ node.
761 */
762static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
763{
764 /* Using the ECX variant for all of them can't hurt... */
765 for (uint32_t i = 0; i < cLeaves; i++)
766 ASMCpuId_Idx_ECX(uStart + i, 0, &paLeaves[i].eax, &paLeaves[i].ebx, &paLeaves[i].ecx, &paLeaves[i].edx);
767
768 /* Load CPUID leaf override; we currently don't care if the user
769 specifies features the host CPU doesn't support. */
770 return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
771}
772
773
774/**
775 * Initializes the emulated CPU's cpuid information.
776 *
777 * @returns VBox status code.
778 * @param pVM Pointer to the VM.
779 */
780static int cpumR3CpuIdInit(PVM pVM)
781{
782 PCPUM pCPUM = &pVM->cpum.s;
783 PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
784 uint32_t i;
785 int rc;
786
787#define PORTABLE_CLEAR_BITS_WHEN(Lvl, LeafSuffReg, FeatNm, fMask, uValue) \
788 if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fMask)) == (uValue) ) \
789 { \
790 LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: %#x -> 0\n", pCPUM->aGuestCpuId##LeafSuffReg & (fMask))); \
791 pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fMask); \
792 }
793#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, LeafSuffReg, FeatNm, fBitMask) \
794 if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fBitMask)) ) \
795 { \
796 LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: 1 -> 0\n")); \
797 pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fBitMask); \
798 }
799
800 /*
801 * Read the configuration.
802 */
803 /** @cfgm{CPUM/SyntheticCpu, boolean, false}
804 * Enables the Synthetic CPU. The Vendor ID and Processor Name are
805 * completely overridden by VirtualBox custom strings. Some
806 * CPUID information is withheld, like the cache info. */
807 rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false);
808 AssertRCReturn(rc, rc);
809
810 /** @cfgm{CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
811 * When non-zero CPUID features that could cause portability issues will be
812 * stripped. The higher the value the more features gets stripped. Higher
813 * values should only be used when older CPUs are involved since it may
814 * harm performance and maybe also cause problems with specific guests. */
815 rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, 0);
816 AssertRCReturn(rc, rc);
817
818 AssertLogRelReturn(!pCPUM->fSyntheticCpu || !pCPUM->u8PortableCpuIdLevel, VERR_CPUM_INCOMPATIBLE_CONFIG);
819
820 /*
821 * Get the host CPUID leaves and redetect the guest CPU vendor (could've
822 * been overridden).
823 */
824 /** @cfgm{CPUM/HostCPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
825 * Overrides the host CPUID leaf values used for calculating the guest CPUID
826 * leaves. This can be used to preserve the CPUID values when moving a VM to a
827 * different machine. Another use is restricting (or extending) the feature set
828 * exposed to the guest. */
829 PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
830 rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
831 AssertRCReturn(rc, rc);
832 rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
833 AssertRCReturn(rc, rc);
834 rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
835 AssertRCReturn(rc, rc);
836
837 pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
838 pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
839
840 /*
841 * Determine the default leaf.
842 *
843 * Intel returns values of the highest standard function, while AMD
844 * returns zeros. VIA on the other hand seems to returning nothing or
845 * perhaps some random garbage, we don't try to duplicate this behavior.
846 */
847 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10, /** @todo r=bird: Use the host value here in case of overrides and more than 10 leaves being stripped already. */
848 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
849 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
850
851 /** @cfgm{/CPUM/CMPXCHG16B, boolean, false}
852 * Expose CMPXCHG16B to the guest if supported by the host.
853 */
854 bool fCmpXchg16b;
855 rc = CFGMR3QueryBoolDef(pCpumCfg, "CMPXCHG16B", &fCmpXchg16b, false); AssertRCReturn(rc, rc);
856
857 bool fMonitor;
858 rc = CFGMR3QueryBoolDef(pCpumCfg, "MONITOR", &fMonitor, true); AssertRCReturn(rc, rc);
859
860 /* Cpuid 1 & 0x80000001:
861 * Only report features we can support.
862 *
863 * Note! When enabling new features the Synthetic CPU and Portable CPUID
864 * options may require adjusting (i.e. stripping what was enabled).
865 */
866 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
867 | X86_CPUID_FEATURE_EDX_VME
868 | X86_CPUID_FEATURE_EDX_DE
869 | X86_CPUID_FEATURE_EDX_PSE
870 | X86_CPUID_FEATURE_EDX_TSC
871 | X86_CPUID_FEATURE_EDX_MSR
872 //| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
873 | X86_CPUID_FEATURE_EDX_MCE
874 | X86_CPUID_FEATURE_EDX_CX8
875 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
876 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
877 //| X86_CPUID_FEATURE_EDX_SEP
878 | X86_CPUID_FEATURE_EDX_MTRR
879 | X86_CPUID_FEATURE_EDX_PGE
880 | X86_CPUID_FEATURE_EDX_MCA
881 | X86_CPUID_FEATURE_EDX_CMOV
882 | X86_CPUID_FEATURE_EDX_PAT
883 | X86_CPUID_FEATURE_EDX_PSE36
884 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
885 | X86_CPUID_FEATURE_EDX_CLFSH
886 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
887 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
888 | X86_CPUID_FEATURE_EDX_MMX
889 | X86_CPUID_FEATURE_EDX_FXSR
890 | X86_CPUID_FEATURE_EDX_SSE
891 | X86_CPUID_FEATURE_EDX_SSE2
892 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
893 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
894 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
895 //| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
896 | 0;
897 pCPUM->aGuestCpuIdStd[1].ecx &= 0
898 | X86_CPUID_FEATURE_ECX_SSE3
899 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
900 | ((fMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
901 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
902 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
903 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
904 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
905 | X86_CPUID_FEATURE_ECX_SSSE3
906 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
907 | (fCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
908 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
909 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
910 /* ECX Bit 21 - x2APIC support - not yet. */
911 // | X86_CPUID_FEATURE_ECX_X2APIC
912 /* ECX Bit 23 - POPCNT instruction. */
913 //| X86_CPUID_FEATURE_ECX_POPCNT
914 | 0;
915 if (pCPUM->u8PortableCpuIdLevel > 0)
916 {
917 PORTABLE_CLEAR_BITS_WHEN(1, Std[1].eax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
918 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
919 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
920 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, CX16, X86_CPUID_FEATURE_ECX_CX16);
921 PORTABLE_DISABLE_FEATURE_BIT(2, Std[1].edx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
922 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, SSE, X86_CPUID_FEATURE_EDX_SSE);
923 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
924 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
925
926 Assert(!(pCPUM->aGuestCpuIdStd[1].edx & ( X86_CPUID_FEATURE_EDX_SEP
927 | X86_CPUID_FEATURE_EDX_PSN
928 | X86_CPUID_FEATURE_EDX_DS
929 | X86_CPUID_FEATURE_EDX_ACPI
930 | X86_CPUID_FEATURE_EDX_SS
931 | X86_CPUID_FEATURE_EDX_TM
932 | X86_CPUID_FEATURE_EDX_PBE
933 )));
934 Assert(!(pCPUM->aGuestCpuIdStd[1].ecx & ( X86_CPUID_FEATURE_ECX_PCLMUL
935 | X86_CPUID_FEATURE_ECX_DTES64
936 | X86_CPUID_FEATURE_ECX_CPLDS
937 | X86_CPUID_FEATURE_ECX_VMX
938 | X86_CPUID_FEATURE_ECX_SMX
939 | X86_CPUID_FEATURE_ECX_EST
940 | X86_CPUID_FEATURE_ECX_TM2
941 | X86_CPUID_FEATURE_ECX_CNTXID
942 | X86_CPUID_FEATURE_ECX_FMA
943 | X86_CPUID_FEATURE_ECX_CX16
944 | X86_CPUID_FEATURE_ECX_TPRUPDATE
945 | X86_CPUID_FEATURE_ECX_PDCM
946 | X86_CPUID_FEATURE_ECX_DCA
947 | X86_CPUID_FEATURE_ECX_MOVBE
948 | X86_CPUID_FEATURE_ECX_AES
949 | X86_CPUID_FEATURE_ECX_POPCNT
950 | X86_CPUID_FEATURE_ECX_XSAVE
951 | X86_CPUID_FEATURE_ECX_OSXSAVE
952 | X86_CPUID_FEATURE_ECX_AVX
953 )));
954 }
955
956 /* Cpuid 0x80000001:
957 * Only report features we can support.
958 *
959 * Note! When enabling new features the Synthetic CPU and Portable CPUID
960 * options may require adjusting (i.e. stripping what was enabled).
961 *
962 * ASSUMES that this is ALWAYS the AMD defined feature set if present.
963 */
964 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
965 | X86_CPUID_AMD_FEATURE_EDX_VME
966 | X86_CPUID_AMD_FEATURE_EDX_DE
967 | X86_CPUID_AMD_FEATURE_EDX_PSE
968 | X86_CPUID_AMD_FEATURE_EDX_TSC
969 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
970 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
971 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
972 | X86_CPUID_AMD_FEATURE_EDX_CX8
973 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
974 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
975 //| X86_CPUID_EXT_FEATURE_EDX_SEP
976 | X86_CPUID_AMD_FEATURE_EDX_MTRR
977 | X86_CPUID_AMD_FEATURE_EDX_PGE
978 | X86_CPUID_AMD_FEATURE_EDX_MCA
979 | X86_CPUID_AMD_FEATURE_EDX_CMOV
980 | X86_CPUID_AMD_FEATURE_EDX_PAT
981 | X86_CPUID_AMD_FEATURE_EDX_PSE36
982 //| X86_CPUID_EXT_FEATURE_EDX_NX - not virtualized, requires PAE.
983 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
984 | X86_CPUID_AMD_FEATURE_EDX_MMX
985 | X86_CPUID_AMD_FEATURE_EDX_FXSR
986 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
987 //| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
988 | X86_CPUID_EXT_FEATURE_EDX_RDTSCP
989 //| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
990 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
991 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
992 | 0;
993 pCPUM->aGuestCpuIdExt[1].ecx &= 0
994 //| X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
995 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
996 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
997 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
998 /* Note: This could prevent teleporting from AMD to Intel CPUs! */
999 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
1000 //| X86_CPUID_AMD_FEATURE_ECX_ABM
1001 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
1002 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1003 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1004 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
1005 //| X86_CPUID_AMD_FEATURE_ECX_IBS
1006 //| X86_CPUID_AMD_FEATURE_ECX_SSE5
1007 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1008 //| X86_CPUID_AMD_FEATURE_ECX_WDT
1009 | 0;
1010 if (pCPUM->u8PortableCpuIdLevel > 0)
1011 {
1012 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].ecx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1013 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1014 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1015 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1016 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1017 PORTABLE_DISABLE_FEATURE_BIT(2, Ext[1].ecx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1018 PORTABLE_DISABLE_FEATURE_BIT(3, Ext[1].ecx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1019
1020 Assert(!(pCPUM->aGuestCpuIdExt[1].ecx & ( X86_CPUID_AMD_FEATURE_ECX_CMPL
1021 | X86_CPUID_AMD_FEATURE_ECX_SVM
1022 | X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1023 | X86_CPUID_AMD_FEATURE_ECX_CR8L
1024 | X86_CPUID_AMD_FEATURE_ECX_ABM
1025 | X86_CPUID_AMD_FEATURE_ECX_SSE4A
1026 | X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1027 | X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1028 | X86_CPUID_AMD_FEATURE_ECX_OSVW
1029 | X86_CPUID_AMD_FEATURE_ECX_IBS
1030 | X86_CPUID_AMD_FEATURE_ECX_SSE5
1031 | X86_CPUID_AMD_FEATURE_ECX_SKINIT
1032 | X86_CPUID_AMD_FEATURE_ECX_WDT
1033 | UINT32_C(0xffffc000)
1034 )));
1035 Assert(!(pCPUM->aGuestCpuIdExt[1].edx & ( RT_BIT(10)
1036 | X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1037 | RT_BIT(18)
1038 | RT_BIT(19)
1039 | RT_BIT(21)
1040 | X86_CPUID_AMD_FEATURE_EDX_AXMMX
1041 | X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1042 | RT_BIT(28)
1043 )));
1044 }
1045
1046 /*
1047 * Apply the Synthetic CPU modifications. (TODO: move this up)
1048 */
1049 if (pCPUM->fSyntheticCpu)
1050 {
1051 static const char s_szVendor[13] = "VirtualBox ";
1052 static const char s_szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
1053
1054 pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
1055
1056 /* Limit the nr of standard leaves; 5 for monitor/mwait */
1057 pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
1058
1059 /* 0: Vendor */
1060 pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)s_szVendor)[0];
1061 pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)s_szVendor)[2];
1062 pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)s_szVendor)[1];
1063
1064 /* 1.eax: Version information. family : model : stepping */
1065 pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
1066
1067 /* Leaves 2 - 4 are Intel only - zero them out */
1068 memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
1069 memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
1070 memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
1071
1072 /* Leaf 5 = monitor/mwait */
1073
1074 /* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
1075 pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
1076 /* AMD only - set to zero. */
1077 pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
1078
1079 /* 0x800000001: shared feature bits are set dynamically. */
1080 memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
1081
1082 /* 0x800000002-4: Processor Name String Identifier. */
1083 pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)s_szProcessor)[0];
1084 pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)s_szProcessor)[1];
1085 pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)s_szProcessor)[2];
1086 pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)s_szProcessor)[3];
1087 pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)s_szProcessor)[4];
1088 pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)s_szProcessor)[5];
1089 pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)s_szProcessor)[6];
1090 pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)s_szProcessor)[7];
1091 pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)s_szProcessor)[8];
1092 pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)s_szProcessor)[9];
1093 pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)s_szProcessor)[10];
1094 pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)s_szProcessor)[11];
1095
1096 /* 0x800000005-7 - reserved -> zero */
1097 memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
1098 memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
1099 memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
1100
1101 /* 0x800000008: only the max virtual and physical address size. */
1102 pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
1103 }
1104
1105 /*
1106 * Hide HTT, multicode, SMP, whatever.
1107 * (APIC-ID := 0 and #LogCpus := 0)
1108 */
1109 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
1110#ifdef VBOX_WITH_MULTI_CORE
1111 if ( pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
1112 && pVM->cCpus > 1)
1113 {
1114 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
1115 pCPUM->aGuestCpuIdStd[1].ebx |= (pVM->cCpus << 16);
1116 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
1117 }
1118#endif
1119
1120 /* Cpuid 2:
1121 * Intel: Cache and TLB information
1122 * AMD: Reserved
1123 * VIA: Reserved
1124 * Safe to expose; restrict the number of calls to 1 for the portable case.
1125 */
1126 if ( pCPUM->u8PortableCpuIdLevel > 0
1127 && pCPUM->aGuestCpuIdStd[0].eax >= 2
1128 && (pCPUM->aGuestCpuIdStd[2].eax & 0xff) > 1)
1129 {
1130 LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCPUM->aGuestCpuIdStd[2].eax & 0xff));
1131 pCPUM->aGuestCpuIdStd[2].eax &= UINT32_C(0xfffffffe);
1132 }
1133
1134 /* Cpuid 3:
1135 * Intel: EAX, EBX - reserved (transmeta uses these)
1136 * ECX, EDX - Processor Serial Number if available, otherwise reserved
1137 * AMD: Reserved
1138 * VIA: Reserved
1139 * Safe to expose
1140 */
1141 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
1142 {
1143 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
1144 if (pCPUM->u8PortableCpuIdLevel > 0)
1145 pCPUM->aGuestCpuIdStd[3].eax = pCPUM->aGuestCpuIdStd[3].ebx = 0;
1146 }
1147
1148 /* Cpuid 4:
1149 * Intel: Deterministic Cache Parameters Leaf
1150 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
1151 * AMD: Reserved
1152 * VIA: Reserved
1153 * Safe to expose, except for EAX:
1154 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
1155 * Bits 31-26: Maximum number of processor cores in this physical package**
1156 * Note: These SMP values are constant regardless of ECX
1157 */
1158 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
1159 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
1160#ifdef VBOX_WITH_MULTI_CORE
1161 if ( pVM->cCpus > 1
1162 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1163 {
1164 AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
1165 /* One logical processor with possibly multiple cores. */
1166 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
1167 pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
1168 }
1169#endif
1170
1171 /* Cpuid 5: Monitor/mwait Leaf
1172 * Intel: ECX, EDX - reserved
1173 * EAX, EBX - Smallest and largest monitor line size
1174 * AMD: EDX - reserved
1175 * EAX, EBX - Smallest and largest monitor line size
1176 * ECX - extensions (ignored for now)
1177 * VIA: Reserved
1178 * Safe to expose
1179 */
1180 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
1181 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
1182
1183 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
1184 /** @cfgm{/CPUM/MWaitExtensions, boolean, false}
1185 * Expose MWAIT extended features to the guest. For now we expose
1186 * just MWAIT break on interrupt feature (bit 1).
1187 */
1188 bool fMWaitExtensions;
1189 rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
1190 if (fMWaitExtensions)
1191 {
1192 pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
1193 /* @todo: for now we just expose host's MWAIT C-states, although conceptually
1194 it shall be part of our power management virtualization model */
1195#if 0
1196 /* MWAIT sub C-states */
1197 pCPUM->aGuestCpuIdStd[5].edx =
1198 (0 << 0) /* 0 in C0 */ |
1199 (2 << 4) /* 2 in C1 */ |
1200 (2 << 8) /* 2 in C2 */ |
1201 (2 << 12) /* 2 in C3 */ |
1202 (0 << 16) /* 0 in C4 */
1203 ;
1204#endif
1205 }
1206 else
1207 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
1208
1209 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
1210 * Safe to pass on to the guest.
1211 *
1212 * Intel: 0x800000005 reserved
1213 * 0x800000006 L2 cache information
1214 * AMD: 0x800000005 L1 cache information
1215 * 0x800000006 L2/L3 cache information
1216 * VIA: 0x800000005 TLB and L1 cache information
1217 * 0x800000006 L2 cache information
1218 */
1219
1220 /* Cpuid 0x800000007:
1221 * Intel: Reserved
1222 * AMD: EAX, EBX, ECX - reserved
1223 * EDX: Advanced Power Management Information
1224 * VIA: Reserved
1225 */
1226 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
1227 {
1228 Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
1229
1230 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
1231
1232 if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1233 {
1234 /* Only expose the TSC invariant capability bit to the guest. */
1235 pCPUM->aGuestCpuIdExt[7].edx &= 0
1236 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
1237 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
1238 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
1239 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
1240 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
1241 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
1242 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
1243 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
1244#if 0
1245 /*
1246 * We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
1247 * Linux kernels blindly assume that the AMD performance counters work
1248 * if this is set for 64 bits guests. (Can't really find a CPUID feature
1249 * bit for them though.)
1250 */
1251 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
1252#endif
1253 | 0;
1254 }
1255 else
1256 pCPUM->aGuestCpuIdExt[7].edx = 0;
1257 }
1258
1259 /* Cpuid 0x800000008:
1260 * Intel: EAX: Virtual/Physical address Size
1261 * EBX, ECX, EDX - reserved
1262 * AMD: EBX, EDX - reserved
1263 * EAX: Virtual/Physical/Guest address Size
1264 * ECX: Number of cores + APICIdCoreIdSize
1265 * VIA: EAX: Virtual/Physical address Size
1266 * EBX, ECX, EDX - reserved
1267 */
1268 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
1269 {
1270 /* Only expose the virtual and physical address sizes to the guest. */
1271 pCPUM->aGuestCpuIdExt[8].eax &= UINT32_C(0x0000ffff);
1272 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
1273 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
1274 * NC (0-7) Number of cores; 0 equals 1 core */
1275 pCPUM->aGuestCpuIdExt[8].ecx = 0;
1276#ifdef VBOX_WITH_MULTI_CORE
1277 if ( pVM->cCpus > 1
1278 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1279 {
1280 /* Legacy method to determine the number of cores. */
1281 pCPUM->aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
1282 pCPUM->aGuestCpuIdExt[8].ecx |= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
1283 }
1284#endif
1285 }
1286
1287 /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
1288 * Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
1289 * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
1290 * This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
1291 */
1292 bool fNt4LeafLimit;
1293 rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
1294 if (fNt4LeafLimit)
1295 pCPUM->aGuestCpuIdStd[0].eax = 3; /** @todo r=bird: shouldn't we check if pCPUM->aGuestCpuIdStd[0].eax > 3 before setting it 3 here? */
1296
1297 /*
1298 * Limit it the number of entries and fill the remaining with the defaults.
1299 *
1300 * The limits are masking off stuff about power saving and similar, this
1301 * is perhaps a bit crudely done as there is probably some relatively harmless
1302 * info too in these leaves (like words about having a constant TSC).
1303 */
1304 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
1305 pCPUM->aGuestCpuIdStd[0].eax = 5;
1306 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
1307 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
1308
1309 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
1310 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
1311 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
1312 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
1313 : 0;
1314 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
1315 i++)
1316 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
1317
1318 /*
1319 * Centaur stuff (VIA).
1320 *
1321 * The important part here (we think) is to make sure the 0xc0000000
1322 * function returns 0xc0000001. As for the features, we don't currently
1323 * let on about any of those... 0xc0000002 seems to be some
1324 * temperature/hz/++ stuff, include it as well (static).
1325 */
1326 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
1327 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
1328 {
1329 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
1330 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
1331 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
1332 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
1333 i++)
1334 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
1335 }
1336 else
1337 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
1338 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
1339
1340 /*
1341 * Hypervisor identification.
1342 *
1343 * We only return minimal information, primarily ensuring that the
1344 * 0x40000000 function returns 0x40000001 and identifying ourselves.
1345 * Currently we do not support any hypervisor-specific interface.
1346 */
1347 pCPUM->aGuestCpuIdHyper[0].eax = UINT32_C(0x40000001);
1348 pCPUM->aGuestCpuIdHyper[0].ebx = pCPUM->aGuestCpuIdHyper[0].ecx
1349 = pCPUM->aGuestCpuIdHyper[0].edx = 0x786f4256; /* 'VBox' */
1350 pCPUM->aGuestCpuIdHyper[1].eax = 0x656e6f6e; /* 'none' */
1351 pCPUM->aGuestCpuIdHyper[1].ebx = pCPUM->aGuestCpuIdHyper[1].ecx
1352 = pCPUM->aGuestCpuIdHyper[1].edx = 0; /* Reserved */
1353
1354 /*
1355 * Load CPUID overrides from configuration.
1356 * Note: Kind of redundant now, but allows unchanged overrides
1357 */
1358 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
1359 * Overrides the CPUID leaf values. */
1360 PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
1361 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
1362 AssertRCReturn(rc, rc);
1363 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
1364 AssertRCReturn(rc, rc);
1365 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
1366 AssertRCReturn(rc, rc);
1367
1368 /*
1369 * Check if PAE was explicitely enabled by the user.
1370 */
1371 bool fEnable;
1372 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
1373 if (fEnable)
1374 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1375
1376 /*
1377 * We don't normally enable NX for raw-mode, so give the user a chance to
1378 * force it on.
1379 */
1380 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false); AssertRCReturn(rc, rc);
1381 if (fEnable)
1382 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1383
1384 /*
1385 * We don't enable the Hypervisor Present bit by default, but it may
1386 * be needed by some guests.
1387 */
1388 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false); AssertRCReturn(rc, rc);
1389 if (fEnable)
1390 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
1391
1392#undef PORTABLE_DISABLE_FEATURE_BIT
1393#undef PORTABLE_CLEAR_BITS_WHEN
1394
1395 return VINF_SUCCESS;
1396}
1397
1398
1399/**
1400 * Applies relocations to data and code managed by this
1401 * component. This function will be called at init and
1402 * whenever the VMM need to relocate it self inside the GC.
1403 *
1404 * The CPUM will update the addresses used by the switcher.
1405 *
1406 * @param pVM The VM.
1407 */
1408VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
1409{
1410 LogFlow(("CPUMR3Relocate\n"));
1411 /* nothing to do any more. */
1412}
1413
1414
1415/**
1416 * Apply late CPUM property changes based on the fHWVirtEx setting
1417 *
1418 * @param pVM Pointer to the VM.
1419 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
1420 */
1421VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
1422{
1423 /*
1424 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
1425 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1426 * of processors from (cpuid(4).eax >> 26) + 1.
1427 *
1428 * Note: this code is obsolete, but let's keep it here for reference.
1429 * Purpose is valid when we artificially cap the max std id to less than 4.
1430 */
1431 if (!fHWVirtExEnabled)
1432 {
1433 Assert( pVM->cpum.s.aGuestCpuIdStd[4].eax == 0
1434 || pVM->cpum.s.aGuestCpuIdStd[0].eax < 0x4);
1435 pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
1436 }
1437}
1438
1439/**
1440 * Terminates the CPUM.
1441 *
1442 * Termination means cleaning up and freeing all resources,
1443 * the VM it self is at this point powered off or suspended.
1444 *
1445 * @returns VBox status code.
1446 * @param pVM Pointer to the VM.
1447 */
1448VMMR3DECL(int) CPUMR3Term(PVM pVM)
1449{
1450#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1451 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1452 {
1453 PVMCPU pVCpu = &pVM->aCpus[i];
1454 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1455
1456 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1457 pVCpu->cpum.s.uMagic = 0;
1458 pCtx->dr[5] = 0;
1459 }
1460#else
1461 NOREF(pVM);
1462#endif
1463 return VINF_SUCCESS;
1464}
1465
1466
1467/**
1468 * Resets a virtual CPU.
1469 *
1470 * Used by CPUMR3Reset and CPU hot plugging.
1471 *
1472 * @param pVCpu Pointer to the VMCPU.
1473 */
1474VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
1475{
1476 /** @todo anything different for VCPU > 0? */
1477 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1478
1479 /*
1480 * Initialize everything to ZERO first.
1481 */
1482 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1483 memset(pCtx, 0, sizeof(*pCtx));
1484 pVCpu->cpum.s.fUseFlags = fUseFlags;
1485
1486 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
1487 pCtx->eip = 0x0000fff0;
1488 pCtx->edx = 0x00000600; /* P6 processor */
1489 pCtx->eflags.Bits.u1Reserved0 = 1;
1490
1491 pCtx->cs.Sel = 0xf000;
1492 pCtx->cs.ValidSel = 0xf000;
1493 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1494 pCtx->cs.u64Base = UINT64_C(0xffff0000);
1495 pCtx->cs.u32Limit = 0x0000ffff;
1496 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1497 pCtx->cs.Attr.n.u1Present = 1;
1498 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1499
1500 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1501 pCtx->ds.u32Limit = 0x0000ffff;
1502 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1503 pCtx->ds.Attr.n.u1Present = 1;
1504 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1505
1506 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1507 pCtx->es.u32Limit = 0x0000ffff;
1508 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1509 pCtx->es.Attr.n.u1Present = 1;
1510 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1511
1512 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1513 pCtx->fs.u32Limit = 0x0000ffff;
1514 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1515 pCtx->fs.Attr.n.u1Present = 1;
1516 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1517
1518 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1519 pCtx->gs.u32Limit = 0x0000ffff;
1520 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1521 pCtx->gs.Attr.n.u1Present = 1;
1522 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1523
1524 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1525 pCtx->ss.u32Limit = 0x0000ffff;
1526 pCtx->ss.Attr.n.u1Present = 1;
1527 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1528 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1529
1530 pCtx->idtr.cbIdt = 0xffff;
1531 pCtx->gdtr.cbGdt = 0xffff;
1532
1533 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1534 pCtx->ldtr.u32Limit = 0xffff;
1535 pCtx->ldtr.Attr.n.u1Present = 1;
1536 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1537
1538 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1539 pCtx->tr.u32Limit = 0xffff;
1540 pCtx->tr.Attr.n.u1Present = 1;
1541 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1542
1543 pCtx->dr[6] = X86_DR6_INIT_VAL;
1544 pCtx->dr[7] = X86_DR7_INIT_VAL;
1545
1546 pCtx->fpu.FTW = 0x00; /* All empty (abbridged tag reg edition). */
1547 pCtx->fpu.FCW = 0x37f;
1548
1549 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1550 IA-32 Processor States Following Power-up, Reset, or INIT */
1551 pCtx->fpu.MXCSR = 0x1F80;
1552 pCtx->fpu.MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
1553 supports all bits, since a zero value here should be read as 0xffbf. */
1554
1555 /* Init PAT MSR */
1556 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1557
1558 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
1559 * The Intel docs don't mention it.
1560 */
1561 pCtx->msrEFER = 0;
1562
1563 /*
1564 * Get the APIC base MSR from the APIC device. For historical reasons (saved state), the APIC base
1565 * continues to reside in the APIC device and we cache it here in the VCPU for all further accesses.
1566 */
1567 PDMApicGetBase(pVCpu, &pCtx->msrApicBase);
1568}
1569
1570
1571/**
1572 * Resets the CPU.
1573 *
1574 * @returns VINF_SUCCESS.
1575 * @param pVM Pointer to the VM.
1576 */
1577VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1578{
1579 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1580 {
1581 CPUMR3ResetCpu(&pVM->aCpus[i]);
1582
1583#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1584 PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1585
1586 /* Magic marker for searching in crash dumps. */
1587 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1588 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1589 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1590#endif
1591 }
1592}
1593
1594
1595/**
1596 * Called both in pass 0 and the final pass.
1597 *
1598 * @param pVM Pointer to the VM.
1599 * @param pSSM The saved state handle.
1600 */
1601static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1602{
1603 /*
1604 * Save all the CPU ID leaves here so we can check them for compatibility
1605 * upon loading.
1606 */
1607 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1608 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1609
1610 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1611 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1612
1613 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1614 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1615
1616 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1617
1618 /*
1619 * Save a good portion of the raw CPU IDs as well as they may come in
1620 * handy when validating features for raw mode.
1621 */
1622 CPUMCPUID aRawStd[16];
1623 for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1624 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1625 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1626 SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1627
1628 CPUMCPUID aRawExt[32];
1629 for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1630 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1631 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1632 SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1633}
1634
1635
1636/**
1637 * Loads the CPU ID leaves saved by pass 0.
1638 *
1639 * @returns VBox status code.
1640 * @param pVM Pointer to the VM.
1641 * @param pSSM The saved state handle.
1642 * @param uVersion The format version.
1643 */
1644static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1645{
1646 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1647
1648 /*
1649 * Define a bunch of macros for simplifying the code.
1650 */
1651 /* Generic expression + failure message. */
1652#define CPUID_CHECK_RET(expr, fmt) \
1653 do { \
1654 if (!(expr)) \
1655 { \
1656 char *pszMsg = RTStrAPrintf2 fmt; /* lack of variadic macros sucks */ \
1657 if (fStrictCpuIdChecks) \
1658 { \
1659 int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1660 RTStrFree(pszMsg); \
1661 return rcCpuid; \
1662 } \
1663 LogRel(("CPUM: %s\n", pszMsg)); \
1664 RTStrFree(pszMsg); \
1665 } \
1666 } while (0)
1667#define CPUID_CHECK_WRN(expr, fmt) \
1668 do { \
1669 if (!(expr)) \
1670 LogRel(fmt); \
1671 } while (0)
1672
1673 /* For comparing two values and bitch if they differs. */
1674#define CPUID_CHECK2_RET(what, host, saved) \
1675 do { \
1676 if ((host) != (saved)) \
1677 { \
1678 if (fStrictCpuIdChecks) \
1679 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1680 N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1681 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1682 } \
1683 } while (0)
1684#define CPUID_CHECK2_WRN(what, host, saved) \
1685 do { \
1686 if ((host) != (saved)) \
1687 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1688 } while (0)
1689
1690 /* For checking raw cpu features (raw mode). */
1691#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1692 do { \
1693 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1694 { \
1695 if (fStrictCpuIdChecks) \
1696 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1697 N_(#bit " mismatch: host=%d saved=%d"), \
1698 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1699 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1700 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1701 } \
1702 } while (0)
1703#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1704 do { \
1705 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1706 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1707 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1708 } while (0)
1709#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1710
1711 /* For checking guest features. */
1712#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1713 do { \
1714 if ( (aGuestCpuId##set [1].reg & bit) \
1715 && !(aHostRaw##set [1].reg & bit) \
1716 && !(aHostOverride##set [1].reg & bit) \
1717 && !(aGuestOverride##set [1].reg & bit) \
1718 ) \
1719 { \
1720 if (fStrictCpuIdChecks) \
1721 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1722 N_(#bit " is not supported by the host but has already exposed to the guest")); \
1723 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1724 } \
1725 } while (0)
1726#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1727 do { \
1728 if ( (aGuestCpuId##set [1].reg & bit) \
1729 && !(aHostRaw##set [1].reg & bit) \
1730 && !(aHostOverride##set [1].reg & bit) \
1731 && !(aGuestOverride##set [1].reg & bit) \
1732 ) \
1733 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1734 } while (0)
1735#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1736 do { \
1737 if ( (aGuestCpuId##set [1].reg & bit) \
1738 && !(aHostRaw##set [1].reg & bit) \
1739 && !(aHostOverride##set [1].reg & bit) \
1740 && !(aGuestOverride##set [1].reg & bit) \
1741 ) \
1742 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1743 } while (0)
1744#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1745
1746 /* For checking guest features if AMD guest CPU. */
1747#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1748 do { \
1749 if ( (aGuestCpuId##set [1].reg & bit) \
1750 && fGuestAmd \
1751 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1752 && !(aHostOverride##set [1].reg & bit) \
1753 && !(aGuestOverride##set [1].reg & bit) \
1754 ) \
1755 { \
1756 if (fStrictCpuIdChecks) \
1757 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1758 N_(#bit " is not supported by the host but has already exposed to the guest")); \
1759 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1760 } \
1761 } while (0)
1762#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1763 do { \
1764 if ( (aGuestCpuId##set [1].reg & bit) \
1765 && fGuestAmd \
1766 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1767 && !(aHostOverride##set [1].reg & bit) \
1768 && !(aGuestOverride##set [1].reg & bit) \
1769 ) \
1770 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1771 } while (0)
1772#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1773 do { \
1774 if ( (aGuestCpuId##set [1].reg & bit) \
1775 && fGuestAmd \
1776 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1777 && !(aHostOverride##set [1].reg & bit) \
1778 && !(aGuestOverride##set [1].reg & bit) \
1779 ) \
1780 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1781 } while (0)
1782#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1783
1784 /* For checking AMD features which have a corresponding bit in the standard
1785 range. (Intel defines very few bits in the extended feature sets.) */
1786#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1787 do { \
1788 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1789 && !(fHostAmd \
1790 ? aHostRawExt[1].reg & (ExtBit) \
1791 : aHostRawStd[1].reg & (StdBit)) \
1792 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1793 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1794 ) \
1795 { \
1796 if (fStrictCpuIdChecks) \
1797 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1798 N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1799 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1800 } \
1801 } while (0)
1802#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1803 do { \
1804 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1805 && !(fHostAmd \
1806 ? aHostRawExt[1].reg & (ExtBit) \
1807 : aHostRawStd[1].reg & (StdBit)) \
1808 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1809 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1810 ) \
1811 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1812 } while (0)
1813#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1814 do { \
1815 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1816 && !(fHostAmd \
1817 ? aHostRawExt[1].reg & (ExtBit) \
1818 : aHostRawStd[1].reg & (StdBit)) \
1819 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1820 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1821 ) \
1822 LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1823 } while (0)
1824#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1825
1826 /*
1827 * Load them into stack buffers first.
1828 */
1829 CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1830 uint32_t cGuestCpuIdStd;
1831 int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1832 if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1833 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1834 SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1835
1836 CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1837 uint32_t cGuestCpuIdExt;
1838 rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1839 if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1840 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1841 SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1842
1843 CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1844 uint32_t cGuestCpuIdCentaur;
1845 rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1846 if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1847 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1848 SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1849
1850 CPUMCPUID GuestCpuIdDef;
1851 rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1852 AssertRCReturn(rc, rc);
1853
1854 CPUMCPUID aRawStd[16];
1855 uint32_t cRawStd;
1856 rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1857 if (cRawStd > RT_ELEMENTS(aRawStd))
1858 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1859 SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1860
1861 CPUMCPUID aRawExt[32];
1862 uint32_t cRawExt;
1863 rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1864 if (cRawExt > RT_ELEMENTS(aRawExt))
1865 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1866 rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1867 AssertRCReturn(rc, rc);
1868
1869 /*
1870 * Note that we support restoring less than the current amount of standard
1871 * leaves because we've been allowed more is newer version of VBox.
1872 *
1873 * So, pad new entries with the default.
1874 */
1875 for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1876 aGuestCpuIdStd[i] = GuestCpuIdDef;
1877
1878 for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1879 aGuestCpuIdExt[i] = GuestCpuIdDef;
1880
1881 for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1882 aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1883
1884 for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1885 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1886
1887 for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1888 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1889
1890 /*
1891 * Get the raw CPU IDs for the current host.
1892 */
1893 CPUMCPUID aHostRawStd[16];
1894 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1895 ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1896
1897 CPUMCPUID aHostRawExt[32];
1898 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1899 ASMCpuId(i | UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1900
1901 /*
1902 * Get the host and guest overrides so we don't reject the state because
1903 * some feature was enabled thru these interfaces.
1904 * Note! We currently only need the feature leaves, so skip rest.
1905 */
1906 PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1907 CPUMCPUID aGuestOverrideStd[2];
1908 memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1909 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1910
1911 CPUMCPUID aGuestOverrideExt[2];
1912 memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1913 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1914
1915 pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1916 CPUMCPUID aHostOverrideStd[2];
1917 memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1918 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1919
1920 CPUMCPUID aHostOverrideExt[2];
1921 memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1922 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1923
1924 /*
1925 * This can be skipped.
1926 */
1927 bool fStrictCpuIdChecks;
1928 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1929
1930
1931
1932 /*
1933 * For raw-mode we'll require that the CPUs are very similar since we don't
1934 * intercept CPUID instructions for user mode applications.
1935 */
1936 if (!HMIsEnabled(pVM))
1937 {
1938 /* CPUID(0) */
1939 CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1940 && aHostRawStd[0].ecx == aRawStd[0].ecx
1941 && aHostRawStd[0].edx == aRawStd[0].edx,
1942 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1943 &aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1944 &aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1945 CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1946 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1947 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1948
1949 bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1950
1951 /* CPUID(1).eax */
1952 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1953 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1954 CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1955
1956 /* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1957 CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1958 CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1959
1960 /* CPUID(1).ecx */
1961 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1962 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1963 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1964 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1965 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1966 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1967 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1968 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1969 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1970 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1971 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1972 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
1973 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1974 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1975 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1976 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1977 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
1978 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
1979 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1980 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1981 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1982 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1983 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
1984 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
1985 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
1986 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
1987 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
1988 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
1989 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
1990 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
1991 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
1992 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_HVP);
1993
1994 /* CPUID(1).edx */
1995 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1996 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1997 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
1998 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1999 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
2000 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
2001 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2002 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2003 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
2004 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2005 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2006 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2007 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2008 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2009 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2010 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
2011 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2012 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2013 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2014 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
2015 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2016 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
2017 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
2018 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
2019 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
2020 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
2021 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
2022 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
2023 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
2024 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
2025 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/);
2026 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
2027
2028 /* CPUID(2) - config, mostly about caches. ignore. */
2029 /* CPUID(3) - processor serial number. ignore. */
2030 /* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
2031 /* CPUID(5) - mwait/monitor config. ignore. */
2032 /* CPUID(6) - power management. ignore. */
2033 /* CPUID(7) - ???. ignore. */
2034 /* CPUID(8) - ???. ignore. */
2035 /* CPUID(9) - DCA. ignore for now. */
2036 /* CPUID(a) - PeMo info. ignore for now. */
2037 /* CPUID(b) - topology info - takes ECX as input. ignore. */
2038
2039 /* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
2040 CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
2041 || aHostRawStd[0].eax >= UINT32_C(0x0000000d),
2042 ("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
2043 if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
2044 && aHostRawStd[0].eax >= UINT32_C(0x0000000d))
2045 {
2046 CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
2047 CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
2048 CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
2049 CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
2050 }
2051
2052 /* CPUID(0x80000000) - same as CPUID(0) except for eax.
2053 Note! Intel have/is marking many of the fields here as reserved. We
2054 will verify them as if it's an AMD CPU. */
2055 CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
2056 || !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
2057 (N_("Extended leaves was present on saved state host, but is missing on the current\n")));
2058 if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
2059 {
2060 CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
2061 && aHostRawExt[0].ecx == aRawExt[0].ecx
2062 && aHostRawExt[0].edx == aRawExt[0].edx,
2063 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
2064 &aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
2065 &aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
2066 CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
2067
2068 /* CPUID(0x80000001).eax - same as CPUID(0).eax. */
2069 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
2070 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
2071 CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
2072 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
2073 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
2074
2075 /* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
2076 CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
2077 CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
2078 CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
2079
2080 /* CPUID(0x80000001).ecx */
2081 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2082 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
2083 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
2084 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
2085 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2086 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
2087 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
2088 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
2089 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
2090 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
2091 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
2092 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
2093 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
2094 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
2095 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2096 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2097 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2098 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2099 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2100 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2101 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2102 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2103 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2104 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2105 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2106 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2107 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2108 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2109 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2110 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2111 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2112 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2113
2114 /* CPUID(0x80000001).edx */
2115 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
2116 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
2117 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
2118 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
2119 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
2120 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
2121 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
2122 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
2123 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
2124 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
2125 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2126 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SEP);
2127 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
2128 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
2129 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
2130 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2131 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
2132 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
2133 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2134 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2135 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2136 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /*reserved*/);
2137 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2138 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
2139 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
2140 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2141 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2142 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2143 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /*reserved*/);
2144 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2145 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2146 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2147
2148 /** @todo verify the rest as well. */
2149 }
2150 }
2151
2152
2153
2154 /*
2155 * Verify that we can support the features already exposed to the guest on
2156 * this host.
2157 *
2158 * Most of the features we're emulating requires intercepting instruction
2159 * and doing it the slow way, so there is no need to warn when they aren't
2160 * present in the host CPU. Thus we use IGN instead of EMU on these.
2161 *
2162 * Trailing comments:
2163 * "EMU" - Possible to emulate, could be lots of work and very slow.
2164 * "EMU?" - Can this be emulated?
2165 */
2166 /* CPUID(1).ecx */
2167 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
2168 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
2169 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
2170 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
2171 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
2172 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
2173 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
2174 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
2175 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
2176 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
2177 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
2178 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
2179 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
2180 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
2181 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
2182 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
2183 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
2184 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
2185 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
2186 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
2187 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
2188 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
2189 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
2190 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
2191 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
2192 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
2193 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
2194 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
2195 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
2196 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
2197 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
2198 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
2199
2200 /* CPUID(1).edx */
2201 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2202 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2203 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
2204 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2205 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2206 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2207 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2208 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2209 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2210 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2211 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2212 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2213 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2214 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2215 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2216 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2217 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2218 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2219 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2220 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
2221 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2222 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
2223 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
2224 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2225 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2226 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
2227 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
2228 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
2229 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
2230 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
2231 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/); // -> EMU
2232 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
2233
2234 /* CPUID(0x80000000). */
2235 if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
2236 && aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
2237 {
2238 /** @todo deal with no 0x80000001 on the host. */
2239 bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
2240 bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
2241
2242 /* CPUID(0x80000001).ecx */
2243 CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
2244 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
2245 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
2246 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
2247 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
2248 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
2249 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
2250 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
2251 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
2252 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
2253 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
2254 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
2255 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
2256 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
2257 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2258 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2259 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2260 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2261 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2262 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2263 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2264 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2265 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2266 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2267 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2268 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2269 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2270 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2271 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2272 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2273 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2274 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2275
2276 /* CPUID(0x80000001).edx */
2277 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
2278 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
2279 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
2280 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
2281 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2282 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2283 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
2284 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
2285 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2286 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
2287 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2288 CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
2289 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
2290 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
2291 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
2292 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2293 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
2294 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
2295 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2296 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2297 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2298 CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /*reserved*/);
2299 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2300 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2301 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2302 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2303 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2304 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2305 CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /*reserved*/);
2306 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2307 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2308 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2309 }
2310
2311 /*
2312 * We're good, commit the CPU ID leaves.
2313 */
2314 memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
2315 memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
2316 memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
2317 pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
2318
2319#undef CPUID_CHECK_RET
2320#undef CPUID_CHECK_WRN
2321#undef CPUID_CHECK2_RET
2322#undef CPUID_CHECK2_WRN
2323#undef CPUID_RAW_FEATURE_RET
2324#undef CPUID_RAW_FEATURE_WRN
2325#undef CPUID_RAW_FEATURE_IGN
2326#undef CPUID_GST_FEATURE_RET
2327#undef CPUID_GST_FEATURE_WRN
2328#undef CPUID_GST_FEATURE_EMU
2329#undef CPUID_GST_FEATURE_IGN
2330#undef CPUID_GST_FEATURE2_RET
2331#undef CPUID_GST_FEATURE2_WRN
2332#undef CPUID_GST_FEATURE2_EMU
2333#undef CPUID_GST_FEATURE2_IGN
2334#undef CPUID_GST_AMD_FEATURE_RET
2335#undef CPUID_GST_AMD_FEATURE_WRN
2336#undef CPUID_GST_AMD_FEATURE_EMU
2337#undef CPUID_GST_AMD_FEATURE_IGN
2338
2339 return VINF_SUCCESS;
2340}
2341
2342
2343/**
2344 * Pass 0 live exec callback.
2345 *
2346 * @returns VINF_SSM_DONT_CALL_AGAIN.
2347 * @param pVM Pointer to the VM.
2348 * @param pSSM The saved state handle.
2349 * @param uPass The pass (0).
2350 */
2351static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2352{
2353 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2354 cpumR3SaveCpuId(pVM, pSSM);
2355 return VINF_SSM_DONT_CALL_AGAIN;
2356}
2357
2358
2359/**
2360 * Execute state save operation.
2361 *
2362 * @returns VBox status code.
2363 * @param pVM Pointer to the VM.
2364 * @param pSSM SSM operation handle.
2365 */
2366static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2367{
2368 /*
2369 * Save.
2370 */
2371 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2372 {
2373 PVMCPU pVCpu = &pVM->aCpus[i];
2374 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
2375 }
2376
2377 SSMR3PutU32(pSSM, pVM->cCpus);
2378 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
2379 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2380 {
2381 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2382
2383 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), 0, g_aCpumCtxFields, NULL);
2384 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2385 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2386 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2387 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2388 }
2389
2390 cpumR3SaveCpuId(pVM, pSSM);
2391 return VINF_SUCCESS;
2392}
2393
2394
2395/**
2396 * @copydoc FNSSMINTLOADPREP
2397 */
2398static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2399{
2400 NOREF(pSSM);
2401 pVM->cpum.s.fPendingRestore = true;
2402 return VINF_SUCCESS;
2403}
2404
2405
2406/**
2407 * @copydoc FNSSMINTLOADEXEC
2408 */
2409static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2410{
2411 /*
2412 * Validate version.
2413 */
2414 if ( uVersion != CPUM_SAVED_STATE_VERSION
2415 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
2416 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2417 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2418 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2419 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2420 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2421 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2422 {
2423 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2424 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2425 }
2426
2427 if (uPass == SSM_PASS_FINAL)
2428 {
2429 /*
2430 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2431 * really old SSM file versions.)
2432 */
2433 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2434 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2435 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2436 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2437
2438 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2439 PCSSMFIELD paCpumCtxFields = g_aCpumCtxFields;
2440 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2441 paCpumCtxFields = g_aCpumCtxFieldsV16;
2442 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2443 paCpumCtxFields = g_aCpumCtxFieldsMem;
2444
2445 /*
2446 * Restore.
2447 */
2448 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2449 {
2450 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2451 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2452 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2453 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), fLoad, paCpumCtxFields, NULL);
2454 pVCpu->cpum.s.Hyper.cr3 = uCR3;
2455 pVCpu->cpum.s.Hyper.rsp = uRSP;
2456 }
2457
2458 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2459 {
2460 uint32_t cCpus;
2461 int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2462 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2463 VERR_SSM_UNEXPECTED_DATA);
2464 }
2465 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2466 || pVM->cCpus == 1,
2467 ("cCpus=%u\n", pVM->cCpus),
2468 VERR_SSM_UNEXPECTED_DATA);
2469
2470 uint32_t cbMsrs = 0;
2471 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2472 {
2473 int rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2474 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2475 VERR_SSM_UNEXPECTED_DATA);
2476 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2477 VERR_SSM_UNEXPECTED_DATA);
2478 }
2479
2480 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2481 {
2482 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2483 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), fLoad,
2484 paCpumCtxFields, NULL);
2485 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
2486 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2487 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2488 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2489 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2490 {
2491 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2492 SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2493 }
2494 }
2495
2496 /* Older states does not have the internal selector register flags
2497 and valid selector value. Supply those. */
2498 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2499 {
2500 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2501 {
2502 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2503 bool const fValid = HMIsEnabled(pVM)
2504 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2505 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2506 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2507 if (fValid)
2508 {
2509 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2510 {
2511 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2512 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2513 }
2514
2515 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2516 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2517 }
2518 else
2519 {
2520 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2521 {
2522 paSelReg[iSelReg].fFlags = 0;
2523 paSelReg[iSelReg].ValidSel = 0;
2524 }
2525
2526 /* This might not be 104% correct, but I think it's close
2527 enough for all practical purposes... (REM always loaded
2528 LDTR registers.) */
2529 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2530 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2531 }
2532 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2533 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2534 }
2535 }
2536
2537 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2538 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2539 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2540 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2541 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2542
2543 /*
2544 * A quick sanity check.
2545 */
2546 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2547 {
2548 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2549 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2550 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2551 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2552 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2553 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2554 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2555 }
2556 }
2557
2558 pVM->cpum.s.fPendingRestore = false;
2559
2560 /*
2561 * Guest CPUIDs.
2562 */
2563 if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2564 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2565
2566 /** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2567 * actually required. */
2568
2569 /*
2570 * Restore the CPUID leaves.
2571 *
2572 * Note that we support restoring less than the current amount of standard
2573 * leaves because we've been allowed more is newer version of VBox.
2574 */
2575 uint32_t cElements;
2576 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2577 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2578 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2579 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2580
2581 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2582 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2583 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2584 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2585
2586 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2587 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2588 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2589 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2590
2591 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2592
2593 /*
2594 * Check that the basic cpuid id information is unchanged.
2595 */
2596 /** @todo we should check the 64 bits capabilities too! */
2597 uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2598 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2599 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2600 uint32_t au32CpuIdSaved[8];
2601 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2602 if (RT_SUCCESS(rc))
2603 {
2604 /* Ignore CPU stepping. */
2605 au32CpuId[4] &= 0xfffffff0;
2606 au32CpuIdSaved[4] &= 0xfffffff0;
2607
2608 /* Ignore APIC ID (AMD specs). */
2609 au32CpuId[5] &= ~0xff000000;
2610 au32CpuIdSaved[5] &= ~0xff000000;
2611
2612 /* Ignore the number of Logical CPUs (AMD specs). */
2613 au32CpuId[5] &= ~0x00ff0000;
2614 au32CpuIdSaved[5] &= ~0x00ff0000;
2615
2616 /* Ignore some advanced capability bits, that we don't expose to the guest. */
2617 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2618 | X86_CPUID_FEATURE_ECX_VMX
2619 | X86_CPUID_FEATURE_ECX_SMX
2620 | X86_CPUID_FEATURE_ECX_EST
2621 | X86_CPUID_FEATURE_ECX_TM2
2622 | X86_CPUID_FEATURE_ECX_CNTXID
2623 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2624 | X86_CPUID_FEATURE_ECX_PDCM
2625 | X86_CPUID_FEATURE_ECX_DCA
2626 | X86_CPUID_FEATURE_ECX_X2APIC
2627 );
2628 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2629 | X86_CPUID_FEATURE_ECX_VMX
2630 | X86_CPUID_FEATURE_ECX_SMX
2631 | X86_CPUID_FEATURE_ECX_EST
2632 | X86_CPUID_FEATURE_ECX_TM2
2633 | X86_CPUID_FEATURE_ECX_CNTXID
2634 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2635 | X86_CPUID_FEATURE_ECX_PDCM
2636 | X86_CPUID_FEATURE_ECX_DCA
2637 | X86_CPUID_FEATURE_ECX_X2APIC
2638 );
2639
2640 /* Make sure we don't forget to update the masks when enabling
2641 * features in the future.
2642 */
2643 AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2644 ( X86_CPUID_FEATURE_ECX_DTES64
2645 | X86_CPUID_FEATURE_ECX_VMX
2646 | X86_CPUID_FEATURE_ECX_SMX
2647 | X86_CPUID_FEATURE_ECX_EST
2648 | X86_CPUID_FEATURE_ECX_TM2
2649 | X86_CPUID_FEATURE_ECX_CNTXID
2650 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2651 | X86_CPUID_FEATURE_ECX_PDCM
2652 | X86_CPUID_FEATURE_ECX_DCA
2653 | X86_CPUID_FEATURE_ECX_X2APIC
2654 )));
2655 /* do the compare */
2656 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2657 {
2658 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2659 LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2660 "Saved=%.*Rhxs\n"
2661 "Real =%.*Rhxs\n",
2662 sizeof(au32CpuIdSaved), au32CpuIdSaved,
2663 sizeof(au32CpuId), au32CpuId));
2664 else
2665 {
2666 LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2667 "Saved=%.*Rhxs\n"
2668 "Real =%.*Rhxs\n",
2669 sizeof(au32CpuIdSaved), au32CpuIdSaved,
2670 sizeof(au32CpuId), au32CpuId));
2671 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2672 }
2673 }
2674 }
2675
2676 return rc;
2677}
2678
2679
2680/**
2681 * @copydoc FNSSMINTLOADPREP
2682 */
2683static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2684{
2685 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2686 return VINF_SUCCESS;
2687
2688 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2689 if (pVM->cpum.s.fPendingRestore)
2690 {
2691 LogRel(("CPUM: Missing state!\n"));
2692 return VERR_INTERNAL_ERROR_2;
2693 }
2694
2695 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2696 {
2697 /* Notify PGM of the NXE states in case they've changed. */
2698 PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2699
2700 /* Cache the local APIC base from the APIC device. During init. this is done in CPUMR3ResetCpu(). */
2701 PDMApicGetBase(&pVM->aCpus[iCpu], &pVM->aCpus[iCpu].cpum.s.Guest.msrApicBase);
2702 }
2703 return VINF_SUCCESS;
2704}
2705
2706
2707/**
2708 * Checks if the CPUM state restore is still pending.
2709 *
2710 * @returns true / false.
2711 * @param pVM Pointer to the VM.
2712 */
2713VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2714{
2715 return pVM->cpum.s.fPendingRestore;
2716}
2717
2718
2719/**
2720 * Formats the EFLAGS value into mnemonics.
2721 *
2722 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2723 * @param efl The EFLAGS value.
2724 */
2725static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2726{
2727 /*
2728 * Format the flags.
2729 */
2730 static const struct
2731 {
2732 const char *pszSet; const char *pszClear; uint32_t fFlag;
2733 } s_aFlags[] =
2734 {
2735 { "vip",NULL, X86_EFL_VIP },
2736 { "vif",NULL, X86_EFL_VIF },
2737 { "ac", NULL, X86_EFL_AC },
2738 { "vm", NULL, X86_EFL_VM },
2739 { "rf", NULL, X86_EFL_RF },
2740 { "nt", NULL, X86_EFL_NT },
2741 { "ov", "nv", X86_EFL_OF },
2742 { "dn", "up", X86_EFL_DF },
2743 { "ei", "di", X86_EFL_IF },
2744 { "tf", NULL, X86_EFL_TF },
2745 { "nt", "pl", X86_EFL_SF },
2746 { "nz", "zr", X86_EFL_ZF },
2747 { "ac", "na", X86_EFL_AF },
2748 { "po", "pe", X86_EFL_PF },
2749 { "cy", "nc", X86_EFL_CF },
2750 };
2751 char *psz = pszEFlags;
2752 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2753 {
2754 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2755 if (pszAdd)
2756 {
2757 strcpy(psz, pszAdd);
2758 psz += strlen(pszAdd);
2759 *psz++ = ' ';
2760 }
2761 }
2762 psz[-1] = '\0';
2763}
2764
2765
2766/**
2767 * Formats a full register dump.
2768 *
2769 * @param pVM Pointer to the VM.
2770 * @param pCtx The context to format.
2771 * @param pCtxCore The context core to format.
2772 * @param pHlp Output functions.
2773 * @param enmType The dump type.
2774 * @param pszPrefix Register name prefix.
2775 */
2776static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
2777 const char *pszPrefix)
2778{
2779 NOREF(pVM);
2780
2781 /*
2782 * Format the EFLAGS.
2783 */
2784 uint32_t efl = pCtxCore->eflags.u32;
2785 char szEFlags[80];
2786 cpumR3InfoFormatFlags(&szEFlags[0], efl);
2787
2788 /*
2789 * Format the registers.
2790 */
2791 switch (enmType)
2792 {
2793 case CPUMDUMPTYPE_TERSE:
2794 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2795 pHlp->pfnPrintf(pHlp,
2796 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2797 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2798 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2799 "%sr14=%016RX64 %sr15=%016RX64\n"
2800 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2801 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2802 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2803 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2804 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2805 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2806 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2807 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2808 else
2809 pHlp->pfnPrintf(pHlp,
2810 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2811 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2812 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2813 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2814 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2815 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2816 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2817 break;
2818
2819 case CPUMDUMPTYPE_DEFAULT:
2820 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2821 pHlp->pfnPrintf(pHlp,
2822 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2823 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2824 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2825 "%sr14=%016RX64 %sr15=%016RX64\n"
2826 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2827 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2828 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2829 ,
2830 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2831 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2832 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2833 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2834 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2835 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2836 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2837 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2838 else
2839 pHlp->pfnPrintf(pHlp,
2840 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2841 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2842 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2843 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2844 ,
2845 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2846 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2847 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2848 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2849 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2850 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2851 break;
2852
2853 case CPUMDUMPTYPE_VERBOSE:
2854 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2855 pHlp->pfnPrintf(pHlp,
2856 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2857 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2858 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2859 "%sr14=%016RX64 %sr15=%016RX64\n"
2860 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2861 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2862 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2863 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2864 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2865 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2866 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2867 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2868 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2869 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2870 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2871 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2872 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2873 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2874 ,
2875 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2876 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2877 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2878 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2879 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2880 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2881 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2882 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2883 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2884 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2885 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2886 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2887 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2888 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2889 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2890 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2891 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2892 else
2893 pHlp->pfnPrintf(pHlp,
2894 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2895 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2896 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2897 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2898 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2899 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2900 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2901 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2902 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2903 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2904 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2905 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2906 ,
2907 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2908 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2909 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2910 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2911 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2912 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2913 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2914 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2915 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2916 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2917 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2918 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2919
2920 pHlp->pfnPrintf(pHlp,
2921 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2922 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2923 ,
2924 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2925 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2926 pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsrvd1,
2927 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2928 );
2929 unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2930 for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2931 {
2932 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2933 unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2934 char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2935 unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2936 uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2937 unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2938 /** @todo This isn't entirenly correct and needs more work! */
2939 pHlp->pfnPrintf(pHlp,
2940 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2941 pszPrefix, iST, pszPrefix, iFPR,
2942 pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2943 uTag, chSign, iInteger, u64Fraction, uExponent);
2944 if (pCtx->fpu.aRegs[0].au16[5] || pCtx->fpu.aRegs[0].au16[6] || pCtx->fpu.aRegs[0].au16[7])
2945 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2946 pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2947 else
2948 pHlp->pfnPrintf(pHlp, "\n");
2949 }
2950 for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2951 pHlp->pfnPrintf(pHlp,
2952 iXMM & 1
2953 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2954 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2955 pszPrefix, iXMM, iXMM < 10 ? " " : "",
2956 pCtx->fpu.aXMM[iXMM].au32[3],
2957 pCtx->fpu.aXMM[iXMM].au32[2],
2958 pCtx->fpu.aXMM[iXMM].au32[1],
2959 pCtx->fpu.aXMM[iXMM].au32[0]);
2960 for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2961 if (pCtx->fpu.au32RsrvdRest[i])
2962 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2963 pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2964
2965 pHlp->pfnPrintf(pHlp,
2966 "%sEFER =%016RX64\n"
2967 "%sPAT =%016RX64\n"
2968 "%sSTAR =%016RX64\n"
2969 "%sCSTAR =%016RX64\n"
2970 "%sLSTAR =%016RX64\n"
2971 "%sSFMASK =%016RX64\n"
2972 "%sKERNELGSBASE =%016RX64\n",
2973 pszPrefix, pCtx->msrEFER,
2974 pszPrefix, pCtx->msrPAT,
2975 pszPrefix, pCtx->msrSTAR,
2976 pszPrefix, pCtx->msrCSTAR,
2977 pszPrefix, pCtx->msrLSTAR,
2978 pszPrefix, pCtx->msrSFMASK,
2979 pszPrefix, pCtx->msrKERNELGSBASE);
2980 break;
2981 }
2982}
2983
2984
2985/**
2986 * Display all cpu states and any other cpum info.
2987 *
2988 * @param pVM Pointer to the VM.
2989 * @param pHlp The info helper functions.
2990 * @param pszArgs Arguments, ignored.
2991 */
2992static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2993{
2994 cpumR3InfoGuest(pVM, pHlp, pszArgs);
2995 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2996 cpumR3InfoHyper(pVM, pHlp, pszArgs);
2997 cpumR3InfoHost(pVM, pHlp, pszArgs);
2998}
2999
3000
3001/**
3002 * Parses the info argument.
3003 *
3004 * The argument starts with 'verbose', 'terse' or 'default' and then
3005 * continues with the comment string.
3006 *
3007 * @param pszArgs The pointer to the argument string.
3008 * @param penmType Where to store the dump type request.
3009 * @param ppszComment Where to store the pointer to the comment string.
3010 */
3011static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
3012{
3013 if (!pszArgs)
3014 {
3015 *penmType = CPUMDUMPTYPE_DEFAULT;
3016 *ppszComment = "";
3017 }
3018 else
3019 {
3020 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
3021 {
3022 pszArgs += 7;
3023 *penmType = CPUMDUMPTYPE_VERBOSE;
3024 }
3025 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
3026 {
3027 pszArgs += 5;
3028 *penmType = CPUMDUMPTYPE_TERSE;
3029 }
3030 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
3031 {
3032 pszArgs += 7;
3033 *penmType = CPUMDUMPTYPE_DEFAULT;
3034 }
3035 else
3036 *penmType = CPUMDUMPTYPE_DEFAULT;
3037 *ppszComment = RTStrStripL(pszArgs);
3038 }
3039}
3040
3041
3042/**
3043 * Display the guest cpu state.
3044 *
3045 * @param pVM Pointer to the VM.
3046 * @param pHlp The info helper functions.
3047 * @param pszArgs Arguments, ignored.
3048 */
3049static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3050{
3051 CPUMDUMPTYPE enmType;
3052 const char *pszComment;
3053 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3054
3055 /* @todo SMP support! */
3056 PVMCPU pVCpu = VMMGetCpu(pVM);
3057 if (!pVCpu)
3058 pVCpu = &pVM->aCpus[0];
3059
3060 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3061
3062 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3063 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3064}
3065
3066
3067/**
3068 * Display the current guest instruction
3069 *
3070 * @param pVM Pointer to the VM.
3071 * @param pHlp The info helper functions.
3072 * @param pszArgs Arguments, ignored.
3073 */
3074static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3075{
3076 NOREF(pszArgs);
3077
3078 /** @todo SMP support! */
3079 PVMCPU pVCpu = VMMGetCpu(pVM);
3080 if (!pVCpu)
3081 pVCpu = &pVM->aCpus[0];
3082
3083 char szInstruction[256];
3084 int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
3085 if (RT_SUCCESS(rc))
3086 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
3087}
3088
3089
3090/**
3091 * Display the hypervisor cpu state.
3092 *
3093 * @param pVM Pointer to the VM.
3094 * @param pHlp The info helper functions.
3095 * @param pszArgs Arguments, ignored.
3096 */
3097static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3098{
3099 CPUMDUMPTYPE enmType;
3100 const char *pszComment;
3101 /* @todo SMP */
3102 PVMCPU pVCpu = &pVM->aCpus[0];
3103
3104 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3105 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
3106 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
3107 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
3108}
3109
3110
3111/**
3112 * Display the host cpu state.
3113 *
3114 * @param pVM Pointer to the VM.
3115 * @param pHlp The info helper functions.
3116 * @param pszArgs Arguments, ignored.
3117 */
3118static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3119{
3120 CPUMDUMPTYPE enmType;
3121 const char *pszComment;
3122 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3123 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
3124
3125 /*
3126 * Format the EFLAGS.
3127 */
3128 /* @todo SMP */
3129 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
3130#if HC_ARCH_BITS == 32
3131 uint32_t efl = pCtx->eflags.u32;
3132#else
3133 uint64_t efl = pCtx->rflags;
3134#endif
3135 char szEFlags[80];
3136 cpumR3InfoFormatFlags(&szEFlags[0], efl);
3137
3138 /*
3139 * Format the registers.
3140 */
3141#if HC_ARCH_BITS == 32
3142# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3143 if (!(pCtx->efer & MSR_K6_EFER_LMA))
3144# endif
3145 {
3146 pHlp->pfnPrintf(pHlp,
3147 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
3148 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
3149 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
3150 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
3151 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
3152 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3153 ,
3154 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
3155 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
3156 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3157 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
3158 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
3159 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
3160 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3161 }
3162# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3163 else
3164# endif
3165#endif
3166#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3167 {
3168 pHlp->pfnPrintf(pHlp,
3169 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
3170 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
3171 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
3172 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
3173 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
3174 "r14=%016RX64 r15=%016RX64\n"
3175 "iopl=%d %31s\n"
3176 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
3177 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
3178 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
3179 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
3180 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
3181 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
3182 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3183 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
3184 ,
3185 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
3186 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
3187 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
3188 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
3189 pCtx->r11, pCtx->r12, pCtx->r13,
3190 pCtx->r14, pCtx->r15,
3191 X86_EFL_GET_IOPL(efl), szEFlags,
3192 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3193 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
3194 pCtx->cr4, pCtx->ldtr, pCtx->tr,
3195 pCtx->dr0, pCtx->dr1, pCtx->dr2,
3196 pCtx->dr3, pCtx->dr6, pCtx->dr7,
3197 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
3198 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
3199 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
3200 }
3201#endif
3202}
3203
3204
3205/**
3206 * Get L1 cache / TLS associativity.
3207 */
3208static const char *getCacheAss(unsigned u, char *pszBuf)
3209{
3210 if (u == 0)
3211 return "res0 ";
3212 if (u == 1)
3213 return "direct";
3214 if (u == 255)
3215 return "fully";
3216 if (u >= 256)
3217 return "???";
3218
3219 RTStrPrintf(pszBuf, 16, "%d way", u);
3220 return pszBuf;
3221}
3222
3223
3224/**
3225 * Get L2 cache associativity.
3226 */
3227const char *getL2CacheAss(unsigned u)
3228{
3229 switch (u)
3230 {
3231 case 0: return "off ";
3232 case 1: return "direct";
3233 case 2: return "2 way ";
3234 case 3: return "res3 ";
3235 case 4: return "4 way ";
3236 case 5: return "res5 ";
3237 case 6: return "8 way ";
3238 case 7: return "res7 ";
3239 case 8: return "16 way";
3240 case 9: return "res9 ";
3241 case 10: return "res10 ";
3242 case 11: return "res11 ";
3243 case 12: return "res12 ";
3244 case 13: return "res13 ";
3245 case 14: return "res14 ";
3246 case 15: return "fully ";
3247 default: return "????";
3248 }
3249}
3250
3251
3252/**
3253 * Display the guest CpuId leaves.
3254 *
3255 * @param pVM Pointer to the VM.
3256 * @param pHlp The info helper functions.
3257 * @param pszArgs "terse", "default" or "verbose".
3258 */
3259static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3260{
3261 /*
3262 * Parse the argument.
3263 */
3264 unsigned iVerbosity = 1;
3265 if (pszArgs)
3266 {
3267 pszArgs = RTStrStripL(pszArgs);
3268 if (!strcmp(pszArgs, "terse"))
3269 iVerbosity--;
3270 else if (!strcmp(pszArgs, "verbose"))
3271 iVerbosity++;
3272 }
3273
3274 /*
3275 * Start cracking.
3276 */
3277 CPUMCPUID Host;
3278 CPUMCPUID Guest;
3279 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
3280
3281 pHlp->pfnPrintf(pHlp,
3282 " RAW Standard CPUIDs\n"
3283 " Function eax ebx ecx edx\n");
3284 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
3285 {
3286 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
3287 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3288
3289 pHlp->pfnPrintf(pHlp,
3290 "Gst: %08x %08x %08x %08x %08x%s\n"
3291 "Hst: %08x %08x %08x %08x\n",
3292 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3293 i <= cStdMax ? "" : "*",
3294 Host.eax, Host.ebx, Host.ecx, Host.edx);
3295 }
3296
3297 /*
3298 * If verbose, decode it.
3299 */
3300 if (iVerbosity)
3301 {
3302 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
3303 pHlp->pfnPrintf(pHlp,
3304 "Name: %.04s%.04s%.04s\n"
3305 "Supports: 0-%x\n",
3306 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3307 }
3308
3309 /*
3310 * Get Features.
3311 */
3312 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
3313 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
3314 pVM->cpum.s.aGuestCpuIdStd[0].edx);
3315 if (cStdMax >= 1 && iVerbosity)
3316 {
3317 static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
3318
3319 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
3320 uint32_t uEAX = Guest.eax;
3321
3322 pHlp->pfnPrintf(pHlp,
3323 "Family: %d \tExtended: %d \tEffective: %d\n"
3324 "Model: %d \tExtended: %d \tEffective: %d\n"
3325 "Stepping: %d\n"
3326 "Type: %d (%s)\n"
3327 "APIC ID: %#04x\n"
3328 "Logical CPUs: %d\n"
3329 "CLFLUSH Size: %d\n"
3330 "Brand ID: %#04x\n",
3331 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3332 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3333 ASMGetCpuStepping(uEAX),
3334 (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
3335 (Guest.ebx >> 24) & 0xff,
3336 (Guest.ebx >> 16) & 0xff,
3337 (Guest.ebx >> 8) & 0xff,
3338 (Guest.ebx >> 0) & 0xff);
3339 if (iVerbosity == 1)
3340 {
3341 uint32_t uEDX = Guest.edx;
3342 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3343 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3344 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3345 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3346 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3347 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3348 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3349 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3350 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3351 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3352 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3353 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3354 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
3355 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3356 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3357 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3358 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3359 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3360 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3361 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
3362 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
3363 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
3364 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
3365 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
3366 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3367 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3368 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
3369 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
3370 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
3371 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
3372 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
3373 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3374 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
3375 pHlp->pfnPrintf(pHlp, "\n");
3376
3377 uint32_t uECX = Guest.ecx;
3378 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3379 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
3380 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
3381 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
3382 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
3383 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
3384 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
3385 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
3386 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
3387 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
3388 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
3389 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
3390 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
3391 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
3392 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
3393 if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
3394 if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
3395 if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
3396 if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID");
3397 if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
3398 if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1");
3399 if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2");
3400 if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
3401 if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
3402 if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
3403 if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL");
3404 if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
3405 if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
3406 if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
3407 if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
3408 if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
3409 if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3410 if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
3411 pHlp->pfnPrintf(pHlp, "\n");
3412 }
3413 else
3414 {
3415 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3416
3417 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
3418 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
3419 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
3420 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
3421
3422 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3423 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
3424 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
3425 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
3426 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
3427 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
3428 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
3429 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
3430 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
3431 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
3432 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
3433 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
3434 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
3435 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
3436 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
3437 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
3438 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
3439 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
3440 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
3441 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
3442 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
3443 pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
3444 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
3445 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
3446 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
3447 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
3448 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
3449 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
3450 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
3451 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technology = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
3452 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
3453 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
3454 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
3455
3456 pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
3457 pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ);
3458 pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
3459 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
3460 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
3461 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
3462 pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
3463 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
3464 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
3465 pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
3466 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
3467 pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
3468 pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
3469 pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
3470 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
3471 pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
3472 pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
3473 pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID);
3474 pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
3475 pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
3476 pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
3477 pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
3478 pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
3479 pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
3480 pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE);
3481 pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES);
3482 pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
3483 pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
3484 pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX);
3485 pHlp->pfnPrintf(pHlp, "29/30 - Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
3486 pHlp->pfnPrintf(pHlp, "Hypervisor Present (we're a guest) = %d (%d)\n", EcxGuest.u1HVP, EcxHost.u1HVP);
3487 }
3488 }
3489 if (cStdMax >= 2 && iVerbosity)
3490 {
3491 /** @todo */
3492 }
3493
3494 /*
3495 * Extended.
3496 * Implemented after AMD specs.
3497 */
3498 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
3499
3500 pHlp->pfnPrintf(pHlp,
3501 "\n"
3502 " RAW Extended CPUIDs\n"
3503 " Function eax ebx ecx edx\n");
3504 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
3505 {
3506 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
3507 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3508
3509 pHlp->pfnPrintf(pHlp,
3510 "Gst: %08x %08x %08x %08x %08x%s\n"
3511 "Hst: %08x %08x %08x %08x\n",
3512 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3513 i <= cExtMax ? "" : "*",
3514 Host.eax, Host.ebx, Host.ecx, Host.edx);
3515 }
3516
3517 /*
3518 * Understandable output
3519 */
3520 if (iVerbosity)
3521 {
3522 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
3523 pHlp->pfnPrintf(pHlp,
3524 "Ext Name: %.4s%.4s%.4s\n"
3525 "Ext Supports: 0x80000000-%#010x\n",
3526 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3527 }
3528
3529 if (iVerbosity && cExtMax >= 1)
3530 {
3531 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
3532 uint32_t uEAX = Guest.eax;
3533 pHlp->pfnPrintf(pHlp,
3534 "Family: %d \tExtended: %d \tEffective: %d\n"
3535 "Model: %d \tExtended: %d \tEffective: %d\n"
3536 "Stepping: %d\n"
3537 "Brand ID: %#05x\n",
3538 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3539 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3540 ASMGetCpuStepping(uEAX),
3541 Guest.ebx & 0xfff);
3542
3543 if (iVerbosity == 1)
3544 {
3545 uint32_t uEDX = Guest.edx;
3546 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3547 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3548 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3549 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3550 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3551 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3552 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3553 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3554 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3555 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3556 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3557 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3558 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
3559 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3560 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3561 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3562 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3563 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3564 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3565 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
3566 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
3567 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
3568 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
3569 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
3570 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3571 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3572 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
3573 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
3574 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
3575 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
3576 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
3577 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
3578 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
3579 pHlp->pfnPrintf(pHlp, "\n");
3580
3581 uint32_t uECX = Guest.ecx;
3582 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3583 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
3584 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
3585 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
3586 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3587 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3588 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3589 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3590 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3591 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3592 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3593 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3594 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3595 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3596 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3597 for (unsigned iBit = 5; iBit < 32; iBit++)
3598 if (uECX & RT_BIT(iBit))
3599 pHlp->pfnPrintf(pHlp, " %d", iBit);
3600 pHlp->pfnPrintf(pHlp, "\n");
3601 }
3602 else
3603 {
3604 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3605
3606 uint32_t uEdxGst = Guest.edx;
3607 uint32_t uEdxHst = Host.edx;
3608 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3609 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3610 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3611 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3612 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3613 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3614 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3615 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3616 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3617 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3618 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3619 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3620 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3621 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3622 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3623 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3624 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3625 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3626 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3627 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3628 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3629 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3630 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3631 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3632 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3633 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3634 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3635 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3636 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3637 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3638 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3639 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3640 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3641
3642 uint32_t uEcxGst = Guest.ecx;
3643 uint32_t uEcxHst = Host.ecx;
3644 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3645 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3646 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3647 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3648 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3649 pHlp->pfnPrintf(pHlp, "5 - Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3650 pHlp->pfnPrintf(pHlp, "6 - SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3651 pHlp->pfnPrintf(pHlp, "7 - Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3652 pHlp->pfnPrintf(pHlp, "8 - PREFETCH and PREFETCHW instruction= %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3653 pHlp->pfnPrintf(pHlp, "9 - OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3654 pHlp->pfnPrintf(pHlp, "10 - Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3655 pHlp->pfnPrintf(pHlp, "11 - SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3656 pHlp->pfnPrintf(pHlp, "12 - SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3657 pHlp->pfnPrintf(pHlp, "13 - Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3658 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3659 }
3660 }
3661
3662 if (iVerbosity && cExtMax >= 2)
3663 {
3664 char szString[4*4*3+1] = {0};
3665 uint32_t *pu32 = (uint32_t *)szString;
3666 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3667 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3668 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3669 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3670 if (cExtMax >= 3)
3671 {
3672 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3673 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3674 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3675 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3676 }
3677 if (cExtMax >= 4)
3678 {
3679 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3680 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3681 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3682 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3683 }
3684 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3685 }
3686
3687 if (iVerbosity && cExtMax >= 5)
3688 {
3689 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3690 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3691 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3692 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3693 char sz1[32];
3694 char sz2[32];
3695
3696 pHlp->pfnPrintf(pHlp,
3697 "TLB 2/4M Instr/Uni: %s %3d entries\n"
3698 "TLB 2/4M Data: %s %3d entries\n",
3699 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3700 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3701 pHlp->pfnPrintf(pHlp,
3702 "TLB 4K Instr/Uni: %s %3d entries\n"
3703 "TLB 4K Data: %s %3d entries\n",
3704 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3705 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3706 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3707 "L1 Instr Cache Lines Per Tag: %d\n"
3708 "L1 Instr Cache Associativity: %s\n"
3709 "L1 Instr Cache Size: %d KB\n",
3710 (uEDX >> 0) & 0xff,
3711 (uEDX >> 8) & 0xff,
3712 getCacheAss((uEDX >> 16) & 0xff, sz1),
3713 (uEDX >> 24) & 0xff);
3714 pHlp->pfnPrintf(pHlp,
3715 "L1 Data Cache Line Size: %d bytes\n"
3716 "L1 Data Cache Lines Per Tag: %d\n"
3717 "L1 Data Cache Associativity: %s\n"
3718 "L1 Data Cache Size: %d KB\n",
3719 (uECX >> 0) & 0xff,
3720 (uECX >> 8) & 0xff,
3721 getCacheAss((uECX >> 16) & 0xff, sz1),
3722 (uECX >> 24) & 0xff);
3723 }
3724
3725 if (iVerbosity && cExtMax >= 6)
3726 {
3727 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3728 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3729 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3730
3731 pHlp->pfnPrintf(pHlp,
3732 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3733 "L2 TLB 2/4M Data: %s %4d entries\n",
3734 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3735 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3736 pHlp->pfnPrintf(pHlp,
3737 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
3738 "L2 TLB 4K Data: %s %4d entries\n",
3739 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3740 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3741 pHlp->pfnPrintf(pHlp,
3742 "L2 Cache Line Size: %d bytes\n"
3743 "L2 Cache Lines Per Tag: %d\n"
3744 "L2 Cache Associativity: %s\n"
3745 "L2 Cache Size: %d KB\n",
3746 (uEDX >> 0) & 0xff,
3747 (uEDX >> 8) & 0xf,
3748 getL2CacheAss((uEDX >> 12) & 0xf),
3749 (uEDX >> 16) & 0xffff);
3750 }
3751
3752 if (iVerbosity && cExtMax >= 7)
3753 {
3754 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3755
3756 pHlp->pfnPrintf(pHlp, "APM Features: ");
3757 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3758 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3759 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3760 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3761 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3762 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3763 for (unsigned iBit = 6; iBit < 32; iBit++)
3764 if (uEDX & RT_BIT(iBit))
3765 pHlp->pfnPrintf(pHlp, " %d", iBit);
3766 pHlp->pfnPrintf(pHlp, "\n");
3767 }
3768
3769 if (iVerbosity && cExtMax >= 8)
3770 {
3771 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3772 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3773
3774 pHlp->pfnPrintf(pHlp,
3775 "Physical Address Width: %d bits\n"
3776 "Virtual Address Width: %d bits\n"
3777 "Guest Physical Address Width: %d bits\n",
3778 (uEAX >> 0) & 0xff,
3779 (uEAX >> 8) & 0xff,
3780 (uEAX >> 16) & 0xff);
3781 pHlp->pfnPrintf(pHlp,
3782 "Physical Core Count: %d\n",
3783 (uECX >> 0) & 0xff);
3784 }
3785
3786
3787 /*
3788 * Centaur.
3789 */
3790 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3791
3792 pHlp->pfnPrintf(pHlp,
3793 "\n"
3794 " RAW Centaur CPUIDs\n"
3795 " Function eax ebx ecx edx\n");
3796 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3797 {
3798 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3799 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3800
3801 pHlp->pfnPrintf(pHlp,
3802 "Gst: %08x %08x %08x %08x %08x%s\n"
3803 "Hst: %08x %08x %08x %08x\n",
3804 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3805 i <= cCentaurMax ? "" : "*",
3806 Host.eax, Host.ebx, Host.ecx, Host.edx);
3807 }
3808
3809 /*
3810 * Understandable output
3811 */
3812 if (iVerbosity)
3813 {
3814 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3815 pHlp->pfnPrintf(pHlp,
3816 "Centaur Supports: 0xc0000000-%#010x\n",
3817 Guest.eax);
3818 }
3819
3820 if (iVerbosity && cCentaurMax >= 1)
3821 {
3822 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3823 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3824 uint32_t uEdxHst = Host.edx;
3825
3826 if (iVerbosity == 1)
3827 {
3828 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3829 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3830 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3831 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3832 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3833 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3834 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3835 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3836 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3837 /* possibly indicating MM/HE and MM/HE-E on older chips... */
3838 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3839 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3840 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3841 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3842 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3843 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3844 for (unsigned iBit = 14; iBit < 32; iBit++)
3845 if (uEdxGst & RT_BIT(iBit))
3846 pHlp->pfnPrintf(pHlp, " %d", iBit);
3847 pHlp->pfnPrintf(pHlp, "\n");
3848 }
3849 else
3850 {
3851 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3852 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3853 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3854 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3855 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3856 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3857 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3858 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3859 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3860 /* possibly indicating MM/HE and MM/HE-E on older chips... */
3861 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3862 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3863 pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3864 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3865 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3866 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3867 pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3868 pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3869 pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3870 pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3871 pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3872 pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3873 pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3874 pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3875 pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3876 pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3877 pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3878 pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3879 pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3880 for (unsigned iBit = 27; iBit < 32; iBit++)
3881 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
3882 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3883 pHlp->pfnPrintf(pHlp, "\n");
3884 }
3885 }
3886}
3887
3888
3889/**
3890 * Structure used when disassembling and instructions in DBGF.
3891 * This is used so the reader function can get the stuff it needs.
3892 */
3893typedef struct CPUMDISASSTATE
3894{
3895 /** Pointer to the CPU structure. */
3896 PDISCPUSTATE pCpu;
3897 /** Pointer to the VM. */
3898 PVM pVM;
3899 /** Pointer to the VMCPU. */
3900 PVMCPU pVCpu;
3901 /** Pointer to the first byte in the segment. */
3902 RTGCUINTPTR GCPtrSegBase;
3903 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
3904 RTGCUINTPTR GCPtrSegEnd;
3905 /** The size of the segment minus 1. */
3906 RTGCUINTPTR cbSegLimit;
3907 /** Pointer to the current page - R3 Ptr. */
3908 void const *pvPageR3;
3909 /** Pointer to the current page - GC Ptr. */
3910 RTGCPTR pvPageGC;
3911 /** The lock information that PGMPhysReleasePageMappingLock needs. */
3912 PGMPAGEMAPLOCK PageMapLock;
3913 /** Whether the PageMapLock is valid or not. */
3914 bool fLocked;
3915 /** 64 bits mode or not. */
3916 bool f64Bits;
3917} CPUMDISASSTATE, *PCPUMDISASSTATE;
3918
3919
3920/**
3921 * @callback_method_impl{FNDISREADBYTES}
3922 */
3923static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
3924{
3925 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
3926 for (;;)
3927 {
3928 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
3929
3930 /*
3931 * Need to update the page translation?
3932 */
3933 if ( !pState->pvPageR3
3934 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3935 {
3936 int rc = VINF_SUCCESS;
3937
3938 /* translate the address */
3939 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3940 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3941 && !HMIsEnabled(pState->pVM))
3942 {
3943 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3944 if (!pState->pvPageR3)
3945 rc = VERR_INVALID_POINTER;
3946 }
3947 else
3948 {
3949 /* Release mapping lock previously acquired. */
3950 if (pState->fLocked)
3951 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3952 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3953 pState->fLocked = RT_SUCCESS_NP(rc);
3954 }
3955 if (RT_FAILURE(rc))
3956 {
3957 pState->pvPageR3 = NULL;
3958 return rc;
3959 }
3960 }
3961
3962 /*
3963 * Check the segment limit.
3964 */
3965 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
3966 return VERR_OUT_OF_SELECTOR_BOUNDS;
3967
3968 /*
3969 * Calc how much we can read.
3970 */
3971 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3972 if (!pState->f64Bits)
3973 {
3974 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3975 if (cb > cbSeg && cbSeg)
3976 cb = cbSeg;
3977 }
3978 if (cb > cbMaxRead)
3979 cb = cbMaxRead;
3980
3981 /*
3982 * Read and advance or exit.
3983 */
3984 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3985 offInstr += (uint8_t)cb;
3986 if (cb >= cbMinRead)
3987 {
3988 pDis->cbCachedInstr = offInstr;
3989 return VINF_SUCCESS;
3990 }
3991 cbMinRead -= (uint8_t)cb;
3992 cbMaxRead -= (uint8_t)cb;
3993 }
3994}
3995
3996
3997/**
3998 * Disassemble an instruction and return the information in the provided structure.
3999 *
4000 * @returns VBox status code.
4001 * @param pVM Pointer to the VM.
4002 * @param pVCpu Pointer to the VMCPU.
4003 * @param pCtx Pointer to the guest CPU context.
4004 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
4005 * @param pCpu Disassembly state.
4006 * @param pszPrefix String prefix for logging (debug only).
4007 *
4008 */
4009VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
4010{
4011 CPUMDISASSTATE State;
4012 int rc;
4013
4014 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4015 State.pCpu = pCpu;
4016 State.pvPageGC = 0;
4017 State.pvPageR3 = NULL;
4018 State.pVM = pVM;
4019 State.pVCpu = pVCpu;
4020 State.fLocked = false;
4021 State.f64Bits = false;
4022
4023 /*
4024 * Get selector information.
4025 */
4026 DISCPUMODE enmDisCpuMode;
4027 if ( (pCtx->cr0 & X86_CR0_PE)
4028 && pCtx->eflags.Bits.u1VM == 0)
4029 {
4030 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4031 {
4032# ifdef VBOX_WITH_RAW_MODE_NOT_R0
4033 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
4034# endif
4035 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4036 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4037 }
4038 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4039 State.GCPtrSegBase = pCtx->cs.u64Base;
4040 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4041 State.cbSegLimit = pCtx->cs.u32Limit;
4042 enmDisCpuMode = (State.f64Bits)
4043 ? DISCPUMODE_64BIT
4044 : pCtx->cs.Attr.n.u1DefBig
4045 ? DISCPUMODE_32BIT
4046 : DISCPUMODE_16BIT;
4047 }
4048 else
4049 {
4050 /* real or V86 mode */
4051 enmDisCpuMode = DISCPUMODE_16BIT;
4052 State.GCPtrSegBase = pCtx->cs.Sel * 16;
4053 State.GCPtrSegEnd = 0xFFFFFFFF;
4054 State.cbSegLimit = 0xFFFFFFFF;
4055 }
4056
4057 /*
4058 * Disassemble the instruction.
4059 */
4060 uint32_t cbInstr;
4061#ifndef LOG_ENABLED
4062 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4063 if (RT_SUCCESS(rc))
4064 {
4065#else
4066 char szOutput[160];
4067 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4068 pCpu, &cbInstr, szOutput, sizeof(szOutput));
4069 if (RT_SUCCESS(rc))
4070 {
4071 /* log it */
4072 if (pszPrefix)
4073 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4074 else
4075 Log(("%s", szOutput));
4076#endif
4077 rc = VINF_SUCCESS;
4078 }
4079 else
4080 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4081
4082 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
4083 if (State.fLocked)
4084 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4085
4086 return rc;
4087}
4088
4089
4090
4091/**
4092 * API for controlling a few of the CPU features found in CR4.
4093 *
4094 * Currently only X86_CR4_TSD is accepted as input.
4095 *
4096 * @returns VBox status code.
4097 *
4098 * @param pVM Pointer to the VM.
4099 * @param fOr The CR4 OR mask.
4100 * @param fAnd The CR4 AND mask.
4101 */
4102VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4103{
4104 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4105 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4106
4107 pVM->cpum.s.CR4.OrMask &= fAnd;
4108 pVM->cpum.s.CR4.OrMask |= fOr;
4109
4110 return VINF_SUCCESS;
4111}
4112
4113
4114/**
4115 * Gets a pointer to the array of standard CPUID leaves.
4116 *
4117 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
4118 *
4119 * @returns Pointer to the standard CPUID leaves (read-only).
4120 * @param pVM Pointer to the VM.
4121 * @remark Intended for PATM.
4122 */
4123VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
4124{
4125 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
4126}
4127
4128
4129/**
4130 * Gets a pointer to the array of extended CPUID leaves.
4131 *
4132 * CPUMGetGuestCpuIdExtMax() give the size of the array.
4133 *
4134 * @returns Pointer to the extended CPUID leaves (read-only).
4135 * @param pVM Pointer to the VM.
4136 * @remark Intended for PATM.
4137 */
4138VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
4139{
4140 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
4141}
4142
4143
4144/**
4145 * Gets a pointer to the array of centaur CPUID leaves.
4146 *
4147 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
4148 *
4149 * @returns Pointer to the centaur CPUID leaves (read-only).
4150 * @param pVM Pointer to the VM.
4151 * @remark Intended for PATM.
4152 */
4153VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
4154{
4155 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
4156}
4157
4158
4159/**
4160 * Gets a pointer to the default CPUID leaf.
4161 *
4162 * @returns Pointer to the default CPUID leaf (read-only).
4163 * @param pVM Pointer to the VM.
4164 * @remark Intended for PATM.
4165 */
4166VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
4167{
4168 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
4169}
4170
4171
4172/**
4173 * Transforms the guest CPU state to raw-ring mode.
4174 *
4175 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
4176 *
4177 * @returns VBox status. (recompiler failure)
4178 * @param pVCpu Pointer to the VMCPU.
4179 * @param pCtxCore The context core (for trap usage).
4180 * @see @ref pg_raw
4181 */
4182VMMR3DECL(int) CPUMR3RawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
4183{
4184 PVM pVM = pVCpu->CTX_SUFF(pVM);
4185
4186 Assert(!pVCpu->cpum.s.fRawEntered);
4187 Assert(!pVCpu->cpum.s.fRemEntered);
4188 if (!pCtxCore)
4189 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
4190
4191 /*
4192 * Are we in Ring-0?
4193 */
4194 if ( pCtxCore->ss.Sel && (pCtxCore->ss.Sel & X86_SEL_RPL) == 0
4195 && !pCtxCore->eflags.Bits.u1VM)
4196 {
4197 /*
4198 * Enter execution mode.
4199 */
4200 PATMRawEnter(pVM, pCtxCore);
4201
4202 /*
4203 * Set CPL to Ring-1.
4204 */
4205 pCtxCore->ss.Sel |= 1;
4206 if (pCtxCore->cs.Sel && (pCtxCore->cs.Sel & X86_SEL_RPL) == 0)
4207 pCtxCore->cs.Sel |= 1;
4208 }
4209 else
4210 {
4211 AssertMsg((pCtxCore->ss.Sel & X86_SEL_RPL) >= 2 || pCtxCore->eflags.Bits.u1VM,
4212 ("ring-1 code not supported\n"));
4213 /*
4214 * PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
4215 */
4216 PATMRawEnter(pVM, pCtxCore);
4217 }
4218
4219 /*
4220 * Assert sanity.
4221 */
4222 AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
4223 AssertReleaseMsg( pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss.Sel & X86_SEL_RPL)
4224 || pCtxCore->eflags.Bits.u1VM,
4225 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
4226 Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP));
4227
4228 pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */
4229
4230 pVCpu->cpum.s.fRawEntered = true;
4231 return VINF_SUCCESS;
4232}
4233
4234
4235/**
4236 * Transforms the guest CPU state from raw-ring mode to correct values.
4237 *
4238 * This function will change any selector registers with DPL=1 to DPL=0.
4239 *
4240 * @returns Adjusted rc.
4241 * @param pVCpu Pointer to the VMCPU.
4242 * @param rc Raw mode return code
4243 * @param pCtxCore The context core (for trap usage).
4244 * @see @ref pg_raw
4245 */
4246VMMR3DECL(int) CPUMR3RawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
4247{
4248 PVM pVM = pVCpu->CTX_SUFF(pVM);
4249
4250 /*
4251 * Don't leave if we've already left (in GC).
4252 */
4253 Assert(pVCpu->cpum.s.fRawEntered);
4254 Assert(!pVCpu->cpum.s.fRemEntered);
4255 if (!pVCpu->cpum.s.fRawEntered)
4256 return rc;
4257 pVCpu->cpum.s.fRawEntered = false;
4258
4259 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4260 if (!pCtxCore)
4261 pCtxCore = CPUMCTX2CORE(pCtx);
4262 Assert(pCtxCore->eflags.Bits.u1VM || (pCtxCore->ss.Sel & X86_SEL_RPL));
4263 AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss.Sel & X86_SEL_RPL),
4264 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
4265
4266 /*
4267 * Are we executing in raw ring-1?
4268 */
4269 if ( (pCtxCore->ss.Sel & X86_SEL_RPL) == 1
4270 && !pCtxCore->eflags.Bits.u1VM)
4271 {
4272 /*
4273 * Leave execution mode.
4274 */
4275 PATMRawLeave(pVM, pCtxCore, rc);
4276 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
4277 /** @todo See what happens if we remove this. */
4278 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
4279 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
4280 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
4281 pCtxCore->es.Sel &= ~X86_SEL_RPL;
4282 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
4283 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
4284 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
4285 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
4286
4287 /*
4288 * Ring-1 selector => Ring-0.
4289 */
4290 pCtxCore->ss.Sel &= ~X86_SEL_RPL;
4291 if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
4292 pCtxCore->cs.Sel &= ~X86_SEL_RPL;
4293 }
4294 else
4295 {
4296 /*
4297 * PATM is taking care of the IOPL and IF flags for us.
4298 */
4299 PATMRawLeave(pVM, pCtxCore, rc);
4300 if (!pCtxCore->eflags.Bits.u1VM)
4301 {
4302 /** @todo See what happens if we remove this. */
4303 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
4304 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
4305 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
4306 pCtxCore->es.Sel &= ~X86_SEL_RPL;
4307 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
4308 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
4309 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
4310 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
4311 }
4312 }
4313
4314 return rc;
4315}
4316
4317
4318/**
4319 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
4320 *
4321 * Only REM should ever call this function!
4322 *
4323 * @returns The changed flags.
4324 * @param pVCpu Pointer to the VMCPU.
4325 * @param puCpl Where to return the current privilege level (CPL).
4326 */
4327VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
4328{
4329 Assert(!pVCpu->cpum.s.fRawEntered);
4330 Assert(!pVCpu->cpum.s.fRemEntered);
4331
4332 /*
4333 * Get the CPL first.
4334 */
4335 *puCpl = CPUMGetGuestCPL(pVCpu);
4336
4337 /*
4338 * Get and reset the flags.
4339 */
4340 uint32_t fFlags = pVCpu->cpum.s.fChanged;
4341 pVCpu->cpum.s.fChanged = 0;
4342
4343 /** @todo change the switcher to use the fChanged flags. */
4344 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
4345 {
4346 fFlags |= CPUM_CHANGED_FPU_REM;
4347 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
4348 }
4349
4350 pVCpu->cpum.s.fRemEntered = true;
4351 return fFlags;
4352}
4353
4354
4355/**
4356 * Leaves REM.
4357 *
4358 * @param pVCpu Pointer to the VMCPU.
4359 * @param fNoOutOfSyncSels This is @c false if there are out of sync
4360 * registers.
4361 */
4362VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
4363{
4364 Assert(!pVCpu->cpum.s.fRawEntered);
4365 Assert(pVCpu->cpum.s.fRemEntered);
4366
4367 pVCpu->cpum.s.fRemEntered = false;
4368}
4369
4370
4371/**
4372 * Called when the ring-3 init phase completes.
4373 *
4374 * @returns VBox status code.
4375 * @param pVM Pointer to the VM.
4376 */
4377VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM)
4378{
4379 for (VMCPUID i = 0; i < pVM->cCpus; i++)
4380 {
4381 /* Cache the APIC base (from the APIC device) once it has been initialized. */
4382 PDMApicGetBase(&pVM->aCpus[i], &pVM->aCpus[i].cpum.s.Guest.msrApicBase);
4383 Log(("CPUMR3InitCompleted pVM=%p APIC base[%u]=%RX64\n", pVM, (unsigned)i, pVM->aCpus[i].cpum.s.Guest.msrApicBase));
4384 }
4385 return VINF_SUCCESS;
4386}
4387
4388/**
4389 * Called when the ring-0 init phases comleted.
4390 *
4391 * @param pVM Pointer to the VM.
4392 */
4393VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
4394{
4395 /*
4396 * Log the cpuid.
4397 */
4398 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
4399 RTCPUSET OnlineSet;
4400 LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4401 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4402 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4403 LogRel(("************************* CPUID dump ************************\n"));
4404 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4405 LogRel(("\n"));
4406 DBGFR3_INFO_LOG(pVM, "cpuid", "verbose"); /* macro */
4407 RTLogRelSetBuffering(fOldBuffered);
4408 LogRel(("******************** End of CPUID dump **********************\n"));
4409}
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette