VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 43858

Last change on this file since 43858 was 43667, checked in by vboxsync, 12 years ago

VMM: APIC refactor, cache APIC base MSR during init phase.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 212.4 KB
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1/* $Id: CPUM.cpp 43667 2012-10-17 11:54:39Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_CPUM
38#include <VBox/vmm/cpum.h>
39#include <VBox/vmm/cpumdis.h>
40#include <VBox/vmm/cpumctx-v1_6.h>
41#include <VBox/vmm/pgm.h>
42#include <VBox/vmm/pdmapi.h>
43#include <VBox/vmm/mm.h>
44#include <VBox/vmm/selm.h>
45#include <VBox/vmm/dbgf.h>
46#include <VBox/vmm/patm.h>
47#include <VBox/vmm/hm.h>
48#include <VBox/vmm/ssm.h>
49#include "CPUMInternal.h"
50#include <VBox/vmm/vm.h>
51
52#include <VBox/param.h>
53#include <VBox/dis.h>
54#include <VBox/err.h>
55#include <VBox/log.h>
56#include <iprt/assert.h>
57#include <iprt/asm-amd64-x86.h>
58#include <iprt/string.h>
59#include <iprt/mp.h>
60#include <iprt/cpuset.h>
61#include "internal/pgm.h"
62
63
64/*******************************************************************************
65* Defined Constants And Macros *
66*******************************************************************************/
67/** The current saved state version. */
68#define CPUM_SAVED_STATE_VERSION 14
69/** The current saved state version before using SSMR3PutStruct. */
70#define CPUM_SAVED_STATE_VERSION_MEM 13
71/** The saved state version before introducing the MSR size field. */
72#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
73/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
74 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
75#define CPUM_SAVED_STATE_VERSION_VER3_2 11
76/** The saved state version of 3.0 and 3.1 trunk before the teleportation
77 * changes. */
78#define CPUM_SAVED_STATE_VERSION_VER3_0 10
79/** The saved state version for the 2.1 trunk before the MSR changes. */
80#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
81/** The saved state version of 2.0, used for backwards compatibility. */
82#define CPUM_SAVED_STATE_VERSION_VER2_0 8
83/** The saved state version of 1.6, used for backwards compatibility. */
84#define CPUM_SAVED_STATE_VERSION_VER1_6 6
85
86
87/**
88 * This was used in the saved state up to the early life of version 14.
89 *
90 * It indicates that we may have some out-of-sync hidden segement registers.
91 * It is only relevant for raw-mode.
92 */
93#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
94
95
96/*******************************************************************************
97* Structures and Typedefs *
98*******************************************************************************/
99
100/**
101 * What kind of cpu info dump to perform.
102 */
103typedef enum CPUMDUMPTYPE
104{
105 CPUMDUMPTYPE_TERSE,
106 CPUMDUMPTYPE_DEFAULT,
107 CPUMDUMPTYPE_VERBOSE
108} CPUMDUMPTYPE;
109/** Pointer to a cpu info dump type. */
110typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
111
112
113/*******************************************************************************
114* Internal Functions *
115*******************************************************************************/
116static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
117static int cpumR3CpuIdInit(PVM pVM);
118static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
119static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
120static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
121static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
122static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
123static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
124static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
125static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
126static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
127static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
128static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
129
130
131/*******************************************************************************
132* Global Variables *
133*******************************************************************************/
134/** Saved state field descriptors for CPUMCTX. */
135static const SSMFIELD g_aCpumCtxFields[] =
136{
137 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
138 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
139 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
140 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
141 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
142 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
143 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
144 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
145 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
146 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
147 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
148 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
149 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
150 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
151 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
152 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
153 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
154 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
155 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
156 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
157 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
158 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
159 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
160 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
161 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
162 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
163 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
164 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
165 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
166 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
167 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
168 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
169 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
170 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
171 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
172 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
173 SSMFIELD_ENTRY( CPUMCTX, rdi),
174 SSMFIELD_ENTRY( CPUMCTX, rsi),
175 SSMFIELD_ENTRY( CPUMCTX, rbp),
176 SSMFIELD_ENTRY( CPUMCTX, rax),
177 SSMFIELD_ENTRY( CPUMCTX, rbx),
178 SSMFIELD_ENTRY( CPUMCTX, rdx),
179 SSMFIELD_ENTRY( CPUMCTX, rcx),
180 SSMFIELD_ENTRY( CPUMCTX, rsp),
181 SSMFIELD_ENTRY( CPUMCTX, rflags),
182 SSMFIELD_ENTRY( CPUMCTX, rip),
183 SSMFIELD_ENTRY( CPUMCTX, r8),
184 SSMFIELD_ENTRY( CPUMCTX, r9),
185 SSMFIELD_ENTRY( CPUMCTX, r10),
186 SSMFIELD_ENTRY( CPUMCTX, r11),
187 SSMFIELD_ENTRY( CPUMCTX, r12),
188 SSMFIELD_ENTRY( CPUMCTX, r13),
189 SSMFIELD_ENTRY( CPUMCTX, r14),
190 SSMFIELD_ENTRY( CPUMCTX, r15),
191 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
192 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
193 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
194 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
195 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
196 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
197 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
198 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
199 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
200 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
201 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
202 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
203 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
204 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
205 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
206 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
207 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
208 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
209 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
210 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
211 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
212 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
213 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
214 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
215 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
216 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
217 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
218 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
219 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
220 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
221 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
222 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
223 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
224 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
225 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
226 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
227 SSMFIELD_ENTRY( CPUMCTX, cr0),
228 SSMFIELD_ENTRY( CPUMCTX, cr2),
229 SSMFIELD_ENTRY( CPUMCTX, cr3),
230 SSMFIELD_ENTRY( CPUMCTX, cr4),
231 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
232 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
233 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
234 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
235 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
236 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
237 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
238 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
239 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
240 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
241 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
242 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
243 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
244 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
245 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
246 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
247 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
248 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
249 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
250 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
251 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
252 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
253 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
254 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
255 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
256 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
257 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
258 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
259 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
260 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
261 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
262 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
263 SSMFIELD_ENTRY_TERM()
264};
265
266/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
267 * registeres changed. */
268static const SSMFIELD g_aCpumCtxFieldsMem[] =
269{
270 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
271 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
272 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
273 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
274 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
275 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
276 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
277 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
278 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
279 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
280 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
281 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
282 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
283 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
284 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
285 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
286 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
287 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
288 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
289 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
290 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
291 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
292 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
293 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
294 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
295 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
296 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
297 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
298 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
299 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
300 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
301 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
302 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
303 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
304 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
305 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
306 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
307 SSMFIELD_ENTRY( CPUMCTX, rdi),
308 SSMFIELD_ENTRY( CPUMCTX, rsi),
309 SSMFIELD_ENTRY( CPUMCTX, rbp),
310 SSMFIELD_ENTRY( CPUMCTX, rax),
311 SSMFIELD_ENTRY( CPUMCTX, rbx),
312 SSMFIELD_ENTRY( CPUMCTX, rdx),
313 SSMFIELD_ENTRY( CPUMCTX, rcx),
314 SSMFIELD_ENTRY( CPUMCTX, rsp),
315 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
316 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
317 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
318 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
319 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
320 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
321 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
322 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
323 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
324 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
325 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
326 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
327 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
328 SSMFIELD_ENTRY( CPUMCTX, rflags),
329 SSMFIELD_ENTRY( CPUMCTX, rip),
330 SSMFIELD_ENTRY( CPUMCTX, r8),
331 SSMFIELD_ENTRY( CPUMCTX, r9),
332 SSMFIELD_ENTRY( CPUMCTX, r10),
333 SSMFIELD_ENTRY( CPUMCTX, r11),
334 SSMFIELD_ENTRY( CPUMCTX, r12),
335 SSMFIELD_ENTRY( CPUMCTX, r13),
336 SSMFIELD_ENTRY( CPUMCTX, r14),
337 SSMFIELD_ENTRY( CPUMCTX, r15),
338 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
339 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
340 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
341 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
342 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
343 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
344 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
345 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
346 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
347 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
348 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
349 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
350 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
351 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
352 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
353 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
354 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
355 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
356 SSMFIELD_ENTRY( CPUMCTX, cr0),
357 SSMFIELD_ENTRY( CPUMCTX, cr2),
358 SSMFIELD_ENTRY( CPUMCTX, cr3),
359 SSMFIELD_ENTRY( CPUMCTX, cr4),
360 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
361 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
362 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
363 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
364 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
365 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
366 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
367 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
368 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
369 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
370 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
371 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
372 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
373 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
374 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
375 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
376 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
377 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
378 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
379 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
380 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
381 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
382 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
383 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
384 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
385 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
386 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
387 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
388 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
389 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
390 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
391 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
392 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
393 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
394 SSMFIELD_ENTRY_TERM()
395};
396
397/** Saved state field descriptors for CPUMCTX_VER1_6. */
398static const SSMFIELD g_aCpumCtxFieldsV16[] =
399{
400 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
401 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
402 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
403 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
404 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
405 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
406 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
407 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
408 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
409 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
410 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
411 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
412 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
413 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
414 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
415 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
416 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
417 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
418 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
419 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
420 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
421 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
422 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
423 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
424 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
425 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
426 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
427 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
428 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
429 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
430 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
431 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
432 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
433 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
434 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
435 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
436 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
437 SSMFIELD_ENTRY( CPUMCTX, rdi),
438 SSMFIELD_ENTRY( CPUMCTX, rsi),
439 SSMFIELD_ENTRY( CPUMCTX, rbp),
440 SSMFIELD_ENTRY( CPUMCTX, rax),
441 SSMFIELD_ENTRY( CPUMCTX, rbx),
442 SSMFIELD_ENTRY( CPUMCTX, rdx),
443 SSMFIELD_ENTRY( CPUMCTX, rcx),
444 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
445 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
446 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
447 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
448 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
449 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
450 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
451 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
452 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
453 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
454 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
455 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
456 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
457 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
458 SSMFIELD_ENTRY( CPUMCTX, rflags),
459 SSMFIELD_ENTRY( CPUMCTX, rip),
460 SSMFIELD_ENTRY( CPUMCTX, r8),
461 SSMFIELD_ENTRY( CPUMCTX, r9),
462 SSMFIELD_ENTRY( CPUMCTX, r10),
463 SSMFIELD_ENTRY( CPUMCTX, r11),
464 SSMFIELD_ENTRY( CPUMCTX, r12),
465 SSMFIELD_ENTRY( CPUMCTX, r13),
466 SSMFIELD_ENTRY( CPUMCTX, r14),
467 SSMFIELD_ENTRY( CPUMCTX, r15),
468 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
469 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
470 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
471 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
472 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
473 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
474 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
475 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
476 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
477 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
478 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
479 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
480 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
481 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
482 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
483 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
484 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
485 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
486 SSMFIELD_ENTRY( CPUMCTX, cr0),
487 SSMFIELD_ENTRY( CPUMCTX, cr2),
488 SSMFIELD_ENTRY( CPUMCTX, cr3),
489 SSMFIELD_ENTRY( CPUMCTX, cr4),
490 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
491 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
492 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
493 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
494 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
495 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
496 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
497 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
498 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
499 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
500 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
501 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
502 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
503 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
504 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
505 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
506 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
507 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
508 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
509 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
510 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
511 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
512 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
513 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
514 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
515 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
516 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
517 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
518 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
519 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
520 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
521 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
522 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
523 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
524 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
525 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
526 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
527 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
528 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
529 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
530 SSMFIELD_ENTRY_TERM()
531};
532
533
534/**
535 * Initializes the CPUM.
536 *
537 * @returns VBox status code.
538 * @param pVM Pointer to the VM.
539 */
540VMMR3DECL(int) CPUMR3Init(PVM pVM)
541{
542 LogFlow(("CPUMR3Init\n"));
543
544 /*
545 * Assert alignment and sizes.
546 */
547 AssertCompileMemberAlignment(VM, cpum.s, 32);
548 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
549 AssertCompileSizeAlignment(CPUMCTX, 64);
550 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
551 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
552 AssertCompileMemberAlignment(VM, cpum, 64);
553 AssertCompileMemberAlignment(VM, aCpus, 64);
554 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
555 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
556
557 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
558 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
559 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
560
561 /* Calculate the offset from CPUMCPU to CPUM. */
562 for (VMCPUID i = 0; i < pVM->cCpus; i++)
563 {
564 PVMCPU pVCpu = &pVM->aCpus[i];
565
566 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
567 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
568 }
569
570 /*
571 * Check that the CPU supports the minimum features we require.
572 */
573 if (!ASMHasCpuId())
574 {
575 Log(("The CPU doesn't support CPUID!\n"));
576 return VERR_UNSUPPORTED_CPU;
577 }
578 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
579 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
580
581 /* Setup the CR4 AND and OR masks used in the switcher */
582 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
583 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
584 {
585 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
586 /* No FXSAVE implies no SSE */
587 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
588 pVM->cpum.s.CR4.OrMask = 0;
589 }
590 else
591 {
592 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
593 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
594 }
595
596 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
597 {
598 Log(("The CPU doesn't support MMX!\n"));
599 return VERR_UNSUPPORTED_CPU;
600 }
601 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
602 {
603 Log(("The CPU doesn't support TSC!\n"));
604 return VERR_UNSUPPORTED_CPU;
605 }
606 /* Bogus on AMD? */
607 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
608 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
609
610 /*
611 * Detect the host CPU vendor.
612 * (The guest CPU vendor is re-detected later on.)
613 */
614 uint32_t uEAX, uEBX, uECX, uEDX;
615 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
616 pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
617 pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
618
619 /*
620 * Setup hypervisor startup values.
621 */
622
623 /*
624 * Register saved state data item.
625 */
626 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
627 NULL, cpumR3LiveExec, NULL,
628 NULL, cpumR3SaveExec, NULL,
629 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
630 if (RT_FAILURE(rc))
631 return rc;
632
633 /*
634 * Register info handlers and registers with the debugger facility.
635 */
636 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
637 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
638 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
639 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
640 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
641 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
642
643 rc = cpumR3DbgInit(pVM);
644 if (RT_FAILURE(rc))
645 return rc;
646
647 /*
648 * Initialize the Guest CPUID state.
649 */
650 rc = cpumR3CpuIdInit(pVM);
651 if (RT_FAILURE(rc))
652 return rc;
653 CPUMR3Reset(pVM);
654 return VINF_SUCCESS;
655}
656
657
658/**
659 * Detect the CPU vendor give n the
660 *
661 * @returns The vendor.
662 * @param uEAX EAX from CPUID(0).
663 * @param uEBX EBX from CPUID(0).
664 * @param uECX ECX from CPUID(0).
665 * @param uEDX EDX from CPUID(0).
666 */
667static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
668{
669 if ( uEAX >= 1
670 && uEBX == X86_CPUID_VENDOR_AMD_EBX
671 && uECX == X86_CPUID_VENDOR_AMD_ECX
672 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
673 return CPUMCPUVENDOR_AMD;
674
675 if ( uEAX >= 1
676 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
677 && uECX == X86_CPUID_VENDOR_INTEL_ECX
678 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
679 return CPUMCPUVENDOR_INTEL;
680
681 if ( uEAX >= 1
682 && uEBX == X86_CPUID_VENDOR_VIA_EBX
683 && uECX == X86_CPUID_VENDOR_VIA_ECX
684 && uEDX == X86_CPUID_VENDOR_VIA_EDX)
685 return CPUMCPUVENDOR_VIA;
686
687 /** @todo detect the other buggers... */
688 return CPUMCPUVENDOR_UNKNOWN;
689}
690
691
692/**
693 * Fetches overrides for a CPUID leaf.
694 *
695 * @returns VBox status code.
696 * @param pLeaf The leaf to load the overrides into.
697 * @param pCfgNode The CFGM node containing the overrides
698 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
699 * @param iLeaf The CPUID leaf number.
700 */
701static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
702{
703 PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
704 if (pLeafNode)
705 {
706 uint32_t u32;
707 int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
708 if (RT_SUCCESS(rc))
709 pLeaf->eax = u32;
710 else
711 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
712
713 rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
714 if (RT_SUCCESS(rc))
715 pLeaf->ebx = u32;
716 else
717 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
718
719 rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
720 if (RT_SUCCESS(rc))
721 pLeaf->ecx = u32;
722 else
723 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
724
725 rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
726 if (RT_SUCCESS(rc))
727 pLeaf->edx = u32;
728 else
729 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
730
731 }
732 return VINF_SUCCESS;
733}
734
735
736/**
737 * Load the overrides for a set of CPUID leaves.
738 *
739 * @returns VBox status code.
740 * @param paLeaves The leaf array.
741 * @param cLeaves The number of leaves.
742 * @param uStart The start leaf number.
743 * @param pCfgNode The CFGM node containing the overrides
744 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
745 */
746static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
747{
748 for (uint32_t i = 0; i < cLeaves; i++)
749 {
750 int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
751 if (RT_FAILURE(rc))
752 return rc;
753 }
754
755 return VINF_SUCCESS;
756}
757
758/**
759 * Init a set of host CPUID leaves.
760 *
761 * @returns VBox status code.
762 * @param paLeaves The leaf array.
763 * @param cLeaves The number of leaves.
764 * @param uStart The start leaf number.
765 * @param pCfgNode The /CPUM/HostCPUID/ node.
766 */
767static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
768{
769 /* Using the ECX variant for all of them can't hurt... */
770 for (uint32_t i = 0; i < cLeaves; i++)
771 ASMCpuId_Idx_ECX(uStart + i, 0, &paLeaves[i].eax, &paLeaves[i].ebx, &paLeaves[i].ecx, &paLeaves[i].edx);
772
773 /* Load CPUID leaf override; we currently don't care if the user
774 specifies features the host CPU doesn't support. */
775 return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
776}
777
778
779/**
780 * Initializes the emulated CPU's cpuid information.
781 *
782 * @returns VBox status code.
783 * @param pVM Pointer to the VM.
784 */
785static int cpumR3CpuIdInit(PVM pVM)
786{
787 PCPUM pCPUM = &pVM->cpum.s;
788 PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
789 uint32_t i;
790 int rc;
791
792#define PORTABLE_CLEAR_BITS_WHEN(Lvl, LeafSuffReg, FeatNm, fMask, uValue) \
793 if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fMask)) == (uValue) ) \
794 { \
795 LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: %#x -> 0\n", pCPUM->aGuestCpuId##LeafSuffReg & (fMask))); \
796 pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fMask); \
797 }
798#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, LeafSuffReg, FeatNm, fBitMask) \
799 if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fBitMask)) ) \
800 { \
801 LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: 1 -> 0\n")); \
802 pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fBitMask); \
803 }
804
805 /*
806 * Read the configuration.
807 */
808 /** @cfgm{CPUM/SyntheticCpu, boolean, false}
809 * Enables the Synthetic CPU. The Vendor ID and Processor Name are
810 * completely overridden by VirtualBox custom strings. Some
811 * CPUID information is withheld, like the cache info. */
812 rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false);
813 AssertRCReturn(rc, rc);
814
815 /** @cfgm{CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
816 * When non-zero CPUID features that could cause portability issues will be
817 * stripped. The higher the value the more features gets stripped. Higher
818 * values should only be used when older CPUs are involved since it may
819 * harm performance and maybe also cause problems with specific guests. */
820 rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, 0);
821 AssertRCReturn(rc, rc);
822
823 AssertLogRelReturn(!pCPUM->fSyntheticCpu || !pCPUM->u8PortableCpuIdLevel, VERR_CPUM_INCOMPATIBLE_CONFIG);
824
825 /*
826 * Get the host CPUID leaves and redetect the guest CPU vendor (could've
827 * been overridden).
828 */
829 /** @cfgm{CPUM/HostCPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
830 * Overrides the host CPUID leaf values used for calculating the guest CPUID
831 * leaves. This can be used to preserve the CPUID values when moving a VM to a
832 * different machine. Another use is restricting (or extending) the feature set
833 * exposed to the guest. */
834 PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
835 rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
836 AssertRCReturn(rc, rc);
837 rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
838 AssertRCReturn(rc, rc);
839 rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
840 AssertRCReturn(rc, rc);
841
842 pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
843 pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
844
845 /*
846 * Determine the default leaf.
847 *
848 * Intel returns values of the highest standard function, while AMD
849 * returns zeros. VIA on the other hand seems to returning nothing or
850 * perhaps some random garbage, we don't try to duplicate this behavior.
851 */
852 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10, /** @todo r=bird: Use the host value here in case of overrides and more than 10 leaves being stripped already. */
853 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
854 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
855
856 /** @cfgm{/CPUM/CMPXCHG16B, boolean, false}
857 * Expose CMPXCHG16B to the guest if supported by the host.
858 */
859 bool fCmpXchg16b;
860 rc = CFGMR3QueryBoolDef(pCpumCfg, "CMPXCHG16B", &fCmpXchg16b, false); AssertRCReturn(rc, rc);
861
862 /* Cpuid 1 & 0x80000001:
863 * Only report features we can support.
864 *
865 * Note! When enabling new features the Synthetic CPU and Portable CPUID
866 * options may require adjusting (i.e. stripping what was enabled).
867 */
868 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
869 | X86_CPUID_FEATURE_EDX_VME
870 | X86_CPUID_FEATURE_EDX_DE
871 | X86_CPUID_FEATURE_EDX_PSE
872 | X86_CPUID_FEATURE_EDX_TSC
873 | X86_CPUID_FEATURE_EDX_MSR
874 //| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
875 | X86_CPUID_FEATURE_EDX_MCE
876 | X86_CPUID_FEATURE_EDX_CX8
877 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
878 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
879 //| X86_CPUID_FEATURE_EDX_SEP
880 | X86_CPUID_FEATURE_EDX_MTRR
881 | X86_CPUID_FEATURE_EDX_PGE
882 | X86_CPUID_FEATURE_EDX_MCA
883 | X86_CPUID_FEATURE_EDX_CMOV
884 | X86_CPUID_FEATURE_EDX_PAT
885 | X86_CPUID_FEATURE_EDX_PSE36
886 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
887 | X86_CPUID_FEATURE_EDX_CLFSH
888 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
889 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
890 | X86_CPUID_FEATURE_EDX_MMX
891 | X86_CPUID_FEATURE_EDX_FXSR
892 | X86_CPUID_FEATURE_EDX_SSE
893 | X86_CPUID_FEATURE_EDX_SSE2
894 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
895 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
896 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
897 //| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
898 | 0;
899 pCPUM->aGuestCpuIdStd[1].ecx &= 0
900 | X86_CPUID_FEATURE_ECX_SSE3
901 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
902 | ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
903 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
904 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
905 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
906 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
907 | X86_CPUID_FEATURE_ECX_SSSE3
908 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
909 | (fCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
910 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
911 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
912 /* ECX Bit 21 - x2APIC support - not yet. */
913 // | X86_CPUID_FEATURE_ECX_X2APIC
914 /* ECX Bit 23 - POPCNT instruction. */
915 //| X86_CPUID_FEATURE_ECX_POPCNT
916 | 0;
917 if (pCPUM->u8PortableCpuIdLevel > 0)
918 {
919 PORTABLE_CLEAR_BITS_WHEN(1, Std[1].eax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
920 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
921 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
922 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, CX16, X86_CPUID_FEATURE_ECX_CX16);
923 PORTABLE_DISABLE_FEATURE_BIT(2, Std[1].edx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
924 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, SSE, X86_CPUID_FEATURE_EDX_SSE);
925 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
926 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
927
928 Assert(!(pCPUM->aGuestCpuIdStd[1].edx & ( X86_CPUID_FEATURE_EDX_SEP
929 | X86_CPUID_FEATURE_EDX_PSN
930 | X86_CPUID_FEATURE_EDX_DS
931 | X86_CPUID_FEATURE_EDX_ACPI
932 | X86_CPUID_FEATURE_EDX_SS
933 | X86_CPUID_FEATURE_EDX_TM
934 | X86_CPUID_FEATURE_EDX_PBE
935 )));
936 Assert(!(pCPUM->aGuestCpuIdStd[1].ecx & ( X86_CPUID_FEATURE_ECX_PCLMUL
937 | X86_CPUID_FEATURE_ECX_DTES64
938 | X86_CPUID_FEATURE_ECX_CPLDS
939 | X86_CPUID_FEATURE_ECX_VMX
940 | X86_CPUID_FEATURE_ECX_SMX
941 | X86_CPUID_FEATURE_ECX_EST
942 | X86_CPUID_FEATURE_ECX_TM2
943 | X86_CPUID_FEATURE_ECX_CNTXID
944 | X86_CPUID_FEATURE_ECX_FMA
945 | X86_CPUID_FEATURE_ECX_CX16
946 | X86_CPUID_FEATURE_ECX_TPRUPDATE
947 | X86_CPUID_FEATURE_ECX_PDCM
948 | X86_CPUID_FEATURE_ECX_DCA
949 | X86_CPUID_FEATURE_ECX_MOVBE
950 | X86_CPUID_FEATURE_ECX_AES
951 | X86_CPUID_FEATURE_ECX_POPCNT
952 | X86_CPUID_FEATURE_ECX_XSAVE
953 | X86_CPUID_FEATURE_ECX_OSXSAVE
954 | X86_CPUID_FEATURE_ECX_AVX
955 )));
956 }
957
958 /* Cpuid 0x80000001:
959 * Only report features we can support.
960 *
961 * Note! When enabling new features the Synthetic CPU and Portable CPUID
962 * options may require adjusting (i.e. stripping what was enabled).
963 *
964 * ASSUMES that this is ALWAYS the AMD defined feature set if present.
965 */
966 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
967 | X86_CPUID_AMD_FEATURE_EDX_VME
968 | X86_CPUID_AMD_FEATURE_EDX_DE
969 | X86_CPUID_AMD_FEATURE_EDX_PSE
970 | X86_CPUID_AMD_FEATURE_EDX_TSC
971 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
972 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
973 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
974 | X86_CPUID_AMD_FEATURE_EDX_CX8
975 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
976 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
977 //| X86_CPUID_EXT_FEATURE_EDX_SEP
978 | X86_CPUID_AMD_FEATURE_EDX_MTRR
979 | X86_CPUID_AMD_FEATURE_EDX_PGE
980 | X86_CPUID_AMD_FEATURE_EDX_MCA
981 | X86_CPUID_AMD_FEATURE_EDX_CMOV
982 | X86_CPUID_AMD_FEATURE_EDX_PAT
983 | X86_CPUID_AMD_FEATURE_EDX_PSE36
984 //| X86_CPUID_EXT_FEATURE_EDX_NX - not virtualized, requires PAE.
985 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
986 | X86_CPUID_AMD_FEATURE_EDX_MMX
987 | X86_CPUID_AMD_FEATURE_EDX_FXSR
988 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
989 //| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
990 | X86_CPUID_EXT_FEATURE_EDX_RDTSCP
991 //| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
992 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
993 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
994 | 0;
995 pCPUM->aGuestCpuIdExt[1].ecx &= 0
996 //| X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
997 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
998 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
999 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1000 /* Note: This could prevent teleporting from AMD to Intel CPUs! */
1001 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
1002 //| X86_CPUID_AMD_FEATURE_ECX_ABM
1003 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
1004 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1005 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1006 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
1007 //| X86_CPUID_AMD_FEATURE_ECX_IBS
1008 //| X86_CPUID_AMD_FEATURE_ECX_SSE5
1009 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1010 //| X86_CPUID_AMD_FEATURE_ECX_WDT
1011 | 0;
1012 if (pCPUM->u8PortableCpuIdLevel > 0)
1013 {
1014 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].ecx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1015 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1016 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1017 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1018 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1019 PORTABLE_DISABLE_FEATURE_BIT(2, Ext[1].ecx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1020 PORTABLE_DISABLE_FEATURE_BIT(3, Ext[1].ecx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1021
1022 Assert(!(pCPUM->aGuestCpuIdExt[1].ecx & ( X86_CPUID_AMD_FEATURE_ECX_CMPL
1023 | X86_CPUID_AMD_FEATURE_ECX_SVM
1024 | X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1025 | X86_CPUID_AMD_FEATURE_ECX_CR8L
1026 | X86_CPUID_AMD_FEATURE_ECX_ABM
1027 | X86_CPUID_AMD_FEATURE_ECX_SSE4A
1028 | X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1029 | X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1030 | X86_CPUID_AMD_FEATURE_ECX_OSVW
1031 | X86_CPUID_AMD_FEATURE_ECX_IBS
1032 | X86_CPUID_AMD_FEATURE_ECX_SSE5
1033 | X86_CPUID_AMD_FEATURE_ECX_SKINIT
1034 | X86_CPUID_AMD_FEATURE_ECX_WDT
1035 | UINT32_C(0xffffc000)
1036 )));
1037 Assert(!(pCPUM->aGuestCpuIdExt[1].edx & ( RT_BIT(10)
1038 | X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1039 | RT_BIT(18)
1040 | RT_BIT(19)
1041 | RT_BIT(21)
1042 | X86_CPUID_AMD_FEATURE_EDX_AXMMX
1043 | X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1044 | RT_BIT(28)
1045 )));
1046 }
1047
1048 /*
1049 * Apply the Synthetic CPU modifications. (TODO: move this up)
1050 */
1051 if (pCPUM->fSyntheticCpu)
1052 {
1053 static const char s_szVendor[13] = "VirtualBox ";
1054 static const char s_szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
1055
1056 pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
1057
1058 /* Limit the nr of standard leaves; 5 for monitor/mwait */
1059 pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
1060
1061 /* 0: Vendor */
1062 pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)s_szVendor)[0];
1063 pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)s_szVendor)[2];
1064 pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)s_szVendor)[1];
1065
1066 /* 1.eax: Version information. family : model : stepping */
1067 pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
1068
1069 /* Leaves 2 - 4 are Intel only - zero them out */
1070 memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
1071 memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
1072 memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
1073
1074 /* Leaf 5 = monitor/mwait */
1075
1076 /* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
1077 pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
1078 /* AMD only - set to zero. */
1079 pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
1080
1081 /* 0x800000001: shared feature bits are set dynamically. */
1082 memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
1083
1084 /* 0x800000002-4: Processor Name String Identifier. */
1085 pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)s_szProcessor)[0];
1086 pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)s_szProcessor)[1];
1087 pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)s_szProcessor)[2];
1088 pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)s_szProcessor)[3];
1089 pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)s_szProcessor)[4];
1090 pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)s_szProcessor)[5];
1091 pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)s_szProcessor)[6];
1092 pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)s_szProcessor)[7];
1093 pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)s_szProcessor)[8];
1094 pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)s_szProcessor)[9];
1095 pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)s_szProcessor)[10];
1096 pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)s_szProcessor)[11];
1097
1098 /* 0x800000005-7 - reserved -> zero */
1099 memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
1100 memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
1101 memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
1102
1103 /* 0x800000008: only the max virtual and physical address size. */
1104 pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
1105 }
1106
1107 /*
1108 * Hide HTT, multicode, SMP, whatever.
1109 * (APIC-ID := 0 and #LogCpus := 0)
1110 */
1111 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
1112#ifdef VBOX_WITH_MULTI_CORE
1113 if ( pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
1114 && pVM->cCpus > 1)
1115 {
1116 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
1117 pCPUM->aGuestCpuIdStd[1].ebx |= (pVM->cCpus << 16);
1118 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
1119 }
1120#endif
1121
1122 /* Cpuid 2:
1123 * Intel: Cache and TLB information
1124 * AMD: Reserved
1125 * VIA: Reserved
1126 * Safe to expose; restrict the number of calls to 1 for the portable case.
1127 */
1128 if ( pCPUM->u8PortableCpuIdLevel > 0
1129 && pCPUM->aGuestCpuIdStd[0].eax >= 2
1130 && (pCPUM->aGuestCpuIdStd[2].eax & 0xff) > 1)
1131 {
1132 LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCPUM->aGuestCpuIdStd[2].eax & 0xff));
1133 pCPUM->aGuestCpuIdStd[2].eax &= UINT32_C(0xfffffffe);
1134 }
1135
1136 /* Cpuid 3:
1137 * Intel: EAX, EBX - reserved (transmeta uses these)
1138 * ECX, EDX - Processor Serial Number if available, otherwise reserved
1139 * AMD: Reserved
1140 * VIA: Reserved
1141 * Safe to expose
1142 */
1143 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
1144 {
1145 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
1146 if (pCPUM->u8PortableCpuIdLevel > 0)
1147 pCPUM->aGuestCpuIdStd[3].eax = pCPUM->aGuestCpuIdStd[3].ebx = 0;
1148 }
1149
1150 /* Cpuid 4:
1151 * Intel: Deterministic Cache Parameters Leaf
1152 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
1153 * AMD: Reserved
1154 * VIA: Reserved
1155 * Safe to expose, except for EAX:
1156 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
1157 * Bits 31-26: Maximum number of processor cores in this physical package**
1158 * Note: These SMP values are constant regardless of ECX
1159 */
1160 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
1161 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
1162#ifdef VBOX_WITH_MULTI_CORE
1163 if ( pVM->cCpus > 1
1164 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1165 {
1166 AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
1167 /* One logical processor with possibly multiple cores. */
1168 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
1169 pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
1170 }
1171#endif
1172
1173 /* Cpuid 5: Monitor/mwait Leaf
1174 * Intel: ECX, EDX - reserved
1175 * EAX, EBX - Smallest and largest monitor line size
1176 * AMD: EDX - reserved
1177 * EAX, EBX - Smallest and largest monitor line size
1178 * ECX - extensions (ignored for now)
1179 * VIA: Reserved
1180 * Safe to expose
1181 */
1182 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
1183 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
1184
1185 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
1186 /** @cfgm{/CPUM/MWaitExtensions, boolean, false}
1187 * Expose MWAIT extended features to the guest. For now we expose
1188 * just MWAIT break on interrupt feature (bit 1).
1189 */
1190 bool fMWaitExtensions;
1191 rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
1192 if (fMWaitExtensions)
1193 {
1194 pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
1195 /* @todo: for now we just expose host's MWAIT C-states, although conceptually
1196 it shall be part of our power management virtualization model */
1197#if 0
1198 /* MWAIT sub C-states */
1199 pCPUM->aGuestCpuIdStd[5].edx =
1200 (0 << 0) /* 0 in C0 */ |
1201 (2 << 4) /* 2 in C1 */ |
1202 (2 << 8) /* 2 in C2 */ |
1203 (2 << 12) /* 2 in C3 */ |
1204 (0 << 16) /* 0 in C4 */
1205 ;
1206#endif
1207 }
1208 else
1209 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
1210
1211 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
1212 * Safe to pass on to the guest.
1213 *
1214 * Intel: 0x800000005 reserved
1215 * 0x800000006 L2 cache information
1216 * AMD: 0x800000005 L1 cache information
1217 * 0x800000006 L2/L3 cache information
1218 * VIA: 0x800000005 TLB and L1 cache information
1219 * 0x800000006 L2 cache information
1220 */
1221
1222 /* Cpuid 0x800000007:
1223 * Intel: Reserved
1224 * AMD: EAX, EBX, ECX - reserved
1225 * EDX: Advanced Power Management Information
1226 * VIA: Reserved
1227 */
1228 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
1229 {
1230 Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
1231
1232 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
1233
1234 if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1235 {
1236 /* Only expose the TSC invariant capability bit to the guest. */
1237 pCPUM->aGuestCpuIdExt[7].edx &= 0
1238 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
1239 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
1240 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
1241 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
1242 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
1243 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
1244 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
1245 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
1246#if 0
1247 /*
1248 * We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
1249 * Linux kernels blindly assume that the AMD performance counters work
1250 * if this is set for 64 bits guests. (Can't really find a CPUID feature
1251 * bit for them though.)
1252 */
1253 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
1254#endif
1255 | 0;
1256 }
1257 else
1258 pCPUM->aGuestCpuIdExt[7].edx = 0;
1259 }
1260
1261 /* Cpuid 0x800000008:
1262 * Intel: EAX: Virtual/Physical address Size
1263 * EBX, ECX, EDX - reserved
1264 * AMD: EBX, EDX - reserved
1265 * EAX: Virtual/Physical/Guest address Size
1266 * ECX: Number of cores + APICIdCoreIdSize
1267 * VIA: EAX: Virtual/Physical address Size
1268 * EBX, ECX, EDX - reserved
1269 */
1270 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
1271 {
1272 /* Only expose the virtual and physical address sizes to the guest. */
1273 pCPUM->aGuestCpuIdExt[8].eax &= UINT32_C(0x0000ffff);
1274 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
1275 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
1276 * NC (0-7) Number of cores; 0 equals 1 core */
1277 pCPUM->aGuestCpuIdExt[8].ecx = 0;
1278#ifdef VBOX_WITH_MULTI_CORE
1279 if ( pVM->cCpus > 1
1280 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1281 {
1282 /* Legacy method to determine the number of cores. */
1283 pCPUM->aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
1284 pCPUM->aGuestCpuIdExt[8].ecx |= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
1285 }
1286#endif
1287 }
1288
1289 /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
1290 * Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
1291 * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
1292 * This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
1293 */
1294 bool fNt4LeafLimit;
1295 rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
1296 if (fNt4LeafLimit)
1297 pCPUM->aGuestCpuIdStd[0].eax = 3; /** @todo r=bird: shouldn't we check if pCPUM->aGuestCpuIdStd[0].eax > 3 before setting it 3 here? */
1298
1299 /*
1300 * Limit it the number of entries and fill the remaining with the defaults.
1301 *
1302 * The limits are masking off stuff about power saving and similar, this
1303 * is perhaps a bit crudely done as there is probably some relatively harmless
1304 * info too in these leaves (like words about having a constant TSC).
1305 */
1306 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
1307 pCPUM->aGuestCpuIdStd[0].eax = 5;
1308 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
1309 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
1310
1311 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
1312 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
1313 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
1314 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
1315 : 0;
1316 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
1317 i++)
1318 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
1319
1320 /*
1321 * Centaur stuff (VIA).
1322 *
1323 * The important part here (we think) is to make sure the 0xc0000000
1324 * function returns 0xc0000001. As for the features, we don't currently
1325 * let on about any of those... 0xc0000002 seems to be some
1326 * temperature/hz/++ stuff, include it as well (static).
1327 */
1328 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
1329 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
1330 {
1331 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
1332 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
1333 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
1334 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
1335 i++)
1336 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
1337 }
1338 else
1339 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
1340 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
1341
1342 /*
1343 * Hypervisor identification.
1344 *
1345 * We only return minimal information, primarily ensuring that the
1346 * 0x40000000 function returns 0x40000001 and identifying ourselves.
1347 * Currently we do not support any hypervisor-specific interface.
1348 */
1349 pCPUM->aGuestCpuIdHyper[0].eax = UINT32_C(0x40000001);
1350 pCPUM->aGuestCpuIdHyper[0].ebx = pCPUM->aGuestCpuIdHyper[0].ecx
1351 = pCPUM->aGuestCpuIdHyper[0].edx = 0x786f4256; /* 'VBox' */
1352 pCPUM->aGuestCpuIdHyper[1].eax = 0x656e6f6e; /* 'none' */
1353 pCPUM->aGuestCpuIdHyper[1].ebx = pCPUM->aGuestCpuIdHyper[1].ecx
1354 = pCPUM->aGuestCpuIdHyper[1].edx = 0; /* Reserved */
1355
1356 /*
1357 * Load CPUID overrides from configuration.
1358 * Note: Kind of redundant now, but allows unchanged overrides
1359 */
1360 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
1361 * Overrides the CPUID leaf values. */
1362 PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
1363 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
1364 AssertRCReturn(rc, rc);
1365 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
1366 AssertRCReturn(rc, rc);
1367 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
1368 AssertRCReturn(rc, rc);
1369
1370 /*
1371 * Check if PAE was explicitely enabled by the user.
1372 */
1373 bool fEnable;
1374 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
1375 if (fEnable)
1376 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1377
1378 /*
1379 * We don't normally enable NX for raw-mode, so give the user a chance to
1380 * force it on.
1381 */
1382 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false); AssertRCReturn(rc, rc);
1383 if (fEnable)
1384 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1385
1386 /*
1387 * We don't enable the Hypervisor Present bit by default, but it may
1388 * be needed by some guests.
1389 */
1390 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false); AssertRCReturn(rc, rc);
1391 if (fEnable)
1392 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
1393 /*
1394 * Log the cpuid and we're good.
1395 */
1396 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
1397 RTCPUSET OnlineSet;
1398 LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
1399 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
1400 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
1401 LogRel(("************************* CPUID dump ************************\n"));
1402 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
1403 LogRel(("\n"));
1404 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
1405 RTLogRelSetBuffering(fOldBuffered);
1406 LogRel(("******************** End of CPUID dump **********************\n"));
1407
1408#undef PORTABLE_DISABLE_FEATURE_BIT
1409#undef PORTABLE_CLEAR_BITS_WHEN
1410
1411 return VINF_SUCCESS;
1412}
1413
1414
1415/**
1416 * Applies relocations to data and code managed by this
1417 * component. This function will be called at init and
1418 * whenever the VMM need to relocate it self inside the GC.
1419 *
1420 * The CPUM will update the addresses used by the switcher.
1421 *
1422 * @param pVM The VM.
1423 */
1424VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
1425{
1426 LogFlow(("CPUMR3Relocate\n"));
1427 /* nothing to do any more. */
1428}
1429
1430
1431/**
1432 * Apply late CPUM property changes based on the fHWVirtEx setting
1433 *
1434 * @param pVM Pointer to the VM.
1435 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
1436 */
1437VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
1438{
1439 /*
1440 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
1441 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1442 * of processors from (cpuid(4).eax >> 26) + 1.
1443 *
1444 * Note: this code is obsolete, but let's keep it here for reference.
1445 * Purpose is valid when we artificially cap the max std id to less than 4.
1446 */
1447 if (!fHWVirtExEnabled)
1448 {
1449 Assert( pVM->cpum.s.aGuestCpuIdStd[4].eax == 0
1450 || pVM->cpum.s.aGuestCpuIdStd[0].eax < 0x4);
1451 pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
1452 }
1453}
1454
1455/**
1456 * Terminates the CPUM.
1457 *
1458 * Termination means cleaning up and freeing all resources,
1459 * the VM it self is at this point powered off or suspended.
1460 *
1461 * @returns VBox status code.
1462 * @param pVM Pointer to the VM.
1463 */
1464VMMR3DECL(int) CPUMR3Term(PVM pVM)
1465{
1466#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1467 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1468 {
1469 PVMCPU pVCpu = &pVM->aCpus[i];
1470 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1471
1472 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1473 pVCpu->cpum.s.uMagic = 0;
1474 pCtx->dr[5] = 0;
1475 }
1476#else
1477 NOREF(pVM);
1478#endif
1479 return VINF_SUCCESS;
1480}
1481
1482
1483/**
1484 * Resets a virtual CPU.
1485 *
1486 * Used by CPUMR3Reset and CPU hot plugging.
1487 *
1488 * @param pVCpu Pointer to the VMCPU.
1489 */
1490VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
1491{
1492 /** @todo anything different for VCPU > 0? */
1493 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1494
1495 /*
1496 * Initialize everything to ZERO first.
1497 */
1498 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1499 memset(pCtx, 0, sizeof(*pCtx));
1500 pVCpu->cpum.s.fUseFlags = fUseFlags;
1501
1502 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
1503 pCtx->eip = 0x0000fff0;
1504 pCtx->edx = 0x00000600; /* P6 processor */
1505 pCtx->eflags.Bits.u1Reserved0 = 1;
1506
1507 pCtx->cs.Sel = 0xf000;
1508 pCtx->cs.ValidSel = 0xf000;
1509 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1510 pCtx->cs.u64Base = UINT64_C(0xffff0000);
1511 pCtx->cs.u32Limit = 0x0000ffff;
1512 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1513 pCtx->cs.Attr.n.u1Present = 1;
1514 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1515
1516 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1517 pCtx->ds.u32Limit = 0x0000ffff;
1518 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1519 pCtx->ds.Attr.n.u1Present = 1;
1520 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1521
1522 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1523 pCtx->es.u32Limit = 0x0000ffff;
1524 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1525 pCtx->es.Attr.n.u1Present = 1;
1526 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1527
1528 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1529 pCtx->fs.u32Limit = 0x0000ffff;
1530 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1531 pCtx->fs.Attr.n.u1Present = 1;
1532 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1533
1534 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1535 pCtx->gs.u32Limit = 0x0000ffff;
1536 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1537 pCtx->gs.Attr.n.u1Present = 1;
1538 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1539
1540 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1541 pCtx->ss.u32Limit = 0x0000ffff;
1542 pCtx->ss.Attr.n.u1Present = 1;
1543 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1544 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1545
1546 pCtx->idtr.cbIdt = 0xffff;
1547 pCtx->gdtr.cbGdt = 0xffff;
1548
1549 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1550 pCtx->ldtr.u32Limit = 0xffff;
1551 pCtx->ldtr.Attr.n.u1Present = 1;
1552 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1553
1554 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1555 pCtx->tr.u32Limit = 0xffff;
1556 pCtx->tr.Attr.n.u1Present = 1;
1557 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1558
1559 pCtx->dr[6] = X86_DR6_INIT_VAL;
1560 pCtx->dr[7] = X86_DR7_INIT_VAL;
1561
1562 pCtx->fpu.FTW = 0x00; /* All empty (abbridged tag reg edition). */
1563 pCtx->fpu.FCW = 0x37f;
1564
1565 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1566 IA-32 Processor States Following Power-up, Reset, or INIT */
1567 pCtx->fpu.MXCSR = 0x1F80;
1568 pCtx->fpu.MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
1569 supports all bits, since a zero value here should be read as 0xffbf. */
1570
1571 /* Init PAT MSR */
1572 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1573
1574 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
1575 * The Intel docs don't mention it.
1576 */
1577 pCtx->msrEFER = 0;
1578
1579 /*
1580 * Get the APIC base MSR from the APIC device. For historical reasons (saved state), the APIC base
1581 * continues to reside in the APIC device and we cache it here in the VCPU for all further accesses.
1582 */
1583 PDMApicGetBase(pVCpu, &pCtx->msrApicBase);
1584}
1585
1586
1587/**
1588 * Resets the CPU.
1589 *
1590 * @returns VINF_SUCCESS.
1591 * @param pVM Pointer to the VM.
1592 */
1593VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1594{
1595 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1596 {
1597 CPUMR3ResetCpu(&pVM->aCpus[i]);
1598
1599#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1600 PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1601
1602 /* Magic marker for searching in crash dumps. */
1603 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1604 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1605 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1606#endif
1607 }
1608}
1609
1610
1611/**
1612 * Called both in pass 0 and the final pass.
1613 *
1614 * @param pVM Pointer to the VM.
1615 * @param pSSM The saved state handle.
1616 */
1617static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1618{
1619 /*
1620 * Save all the CPU ID leaves here so we can check them for compatibility
1621 * upon loading.
1622 */
1623 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1624 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1625
1626 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1627 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1628
1629 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1630 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1631
1632 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1633
1634 /*
1635 * Save a good portion of the raw CPU IDs as well as they may come in
1636 * handy when validating features for raw mode.
1637 */
1638 CPUMCPUID aRawStd[16];
1639 for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1640 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1641 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1642 SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1643
1644 CPUMCPUID aRawExt[32];
1645 for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1646 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1647 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1648 SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1649}
1650
1651
1652/**
1653 * Loads the CPU ID leaves saved by pass 0.
1654 *
1655 * @returns VBox status code.
1656 * @param pVM Pointer to the VM.
1657 * @param pSSM The saved state handle.
1658 * @param uVersion The format version.
1659 */
1660static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1661{
1662 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1663
1664 /*
1665 * Define a bunch of macros for simplifying the code.
1666 */
1667 /* Generic expression + failure message. */
1668#define CPUID_CHECK_RET(expr, fmt) \
1669 do { \
1670 if (!(expr)) \
1671 { \
1672 char *pszMsg = RTStrAPrintf2 fmt; /* lack of variadic macros sucks */ \
1673 if (fStrictCpuIdChecks) \
1674 { \
1675 int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1676 RTStrFree(pszMsg); \
1677 return rcCpuid; \
1678 } \
1679 LogRel(("CPUM: %s\n", pszMsg)); \
1680 RTStrFree(pszMsg); \
1681 } \
1682 } while (0)
1683#define CPUID_CHECK_WRN(expr, fmt) \
1684 do { \
1685 if (!(expr)) \
1686 LogRel(fmt); \
1687 } while (0)
1688
1689 /* For comparing two values and bitch if they differs. */
1690#define CPUID_CHECK2_RET(what, host, saved) \
1691 do { \
1692 if ((host) != (saved)) \
1693 { \
1694 if (fStrictCpuIdChecks) \
1695 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1696 N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1697 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1698 } \
1699 } while (0)
1700#define CPUID_CHECK2_WRN(what, host, saved) \
1701 do { \
1702 if ((host) != (saved)) \
1703 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1704 } while (0)
1705
1706 /* For checking raw cpu features (raw mode). */
1707#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1708 do { \
1709 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1710 { \
1711 if (fStrictCpuIdChecks) \
1712 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1713 N_(#bit " mismatch: host=%d saved=%d"), \
1714 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1715 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1716 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1717 } \
1718 } while (0)
1719#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1720 do { \
1721 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1722 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1723 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1724 } while (0)
1725#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1726
1727 /* For checking guest features. */
1728#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1729 do { \
1730 if ( (aGuestCpuId##set [1].reg & bit) \
1731 && !(aHostRaw##set [1].reg & bit) \
1732 && !(aHostOverride##set [1].reg & bit) \
1733 && !(aGuestOverride##set [1].reg & bit) \
1734 ) \
1735 { \
1736 if (fStrictCpuIdChecks) \
1737 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1738 N_(#bit " is not supported by the host but has already exposed to the guest")); \
1739 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1740 } \
1741 } while (0)
1742#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1743 do { \
1744 if ( (aGuestCpuId##set [1].reg & bit) \
1745 && !(aHostRaw##set [1].reg & bit) \
1746 && !(aHostOverride##set [1].reg & bit) \
1747 && !(aGuestOverride##set [1].reg & bit) \
1748 ) \
1749 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1750 } while (0)
1751#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1752 do { \
1753 if ( (aGuestCpuId##set [1].reg & bit) \
1754 && !(aHostRaw##set [1].reg & bit) \
1755 && !(aHostOverride##set [1].reg & bit) \
1756 && !(aGuestOverride##set [1].reg & bit) \
1757 ) \
1758 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1759 } while (0)
1760#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1761
1762 /* For checking guest features if AMD guest CPU. */
1763#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1764 do { \
1765 if ( (aGuestCpuId##set [1].reg & bit) \
1766 && fGuestAmd \
1767 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1768 && !(aHostOverride##set [1].reg & bit) \
1769 && !(aGuestOverride##set [1].reg & bit) \
1770 ) \
1771 { \
1772 if (fStrictCpuIdChecks) \
1773 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1774 N_(#bit " is not supported by the host but has already exposed to the guest")); \
1775 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1776 } \
1777 } while (0)
1778#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1779 do { \
1780 if ( (aGuestCpuId##set [1].reg & bit) \
1781 && fGuestAmd \
1782 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1783 && !(aHostOverride##set [1].reg & bit) \
1784 && !(aGuestOverride##set [1].reg & bit) \
1785 ) \
1786 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1787 } while (0)
1788#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1789 do { \
1790 if ( (aGuestCpuId##set [1].reg & bit) \
1791 && fGuestAmd \
1792 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1793 && !(aHostOverride##set [1].reg & bit) \
1794 && !(aGuestOverride##set [1].reg & bit) \
1795 ) \
1796 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1797 } while (0)
1798#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1799
1800 /* For checking AMD features which have a corresponding bit in the standard
1801 range. (Intel defines very few bits in the extended feature sets.) */
1802#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1803 do { \
1804 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1805 && !(fHostAmd \
1806 ? aHostRawExt[1].reg & (ExtBit) \
1807 : aHostRawStd[1].reg & (StdBit)) \
1808 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1809 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1810 ) \
1811 { \
1812 if (fStrictCpuIdChecks) \
1813 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1814 N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1815 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1816 } \
1817 } while (0)
1818#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1819 do { \
1820 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1821 && !(fHostAmd \
1822 ? aHostRawExt[1].reg & (ExtBit) \
1823 : aHostRawStd[1].reg & (StdBit)) \
1824 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1825 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1826 ) \
1827 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1828 } while (0)
1829#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1830 do { \
1831 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1832 && !(fHostAmd \
1833 ? aHostRawExt[1].reg & (ExtBit) \
1834 : aHostRawStd[1].reg & (StdBit)) \
1835 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1836 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1837 ) \
1838 LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1839 } while (0)
1840#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1841
1842 /*
1843 * Load them into stack buffers first.
1844 */
1845 CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1846 uint32_t cGuestCpuIdStd;
1847 int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1848 if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1849 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1850 SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1851
1852 CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1853 uint32_t cGuestCpuIdExt;
1854 rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1855 if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1856 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1857 SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1858
1859 CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1860 uint32_t cGuestCpuIdCentaur;
1861 rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1862 if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1863 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1864 SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1865
1866 CPUMCPUID GuestCpuIdDef;
1867 rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1868 AssertRCReturn(rc, rc);
1869
1870 CPUMCPUID aRawStd[16];
1871 uint32_t cRawStd;
1872 rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1873 if (cRawStd > RT_ELEMENTS(aRawStd))
1874 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1875 SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1876
1877 CPUMCPUID aRawExt[32];
1878 uint32_t cRawExt;
1879 rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1880 if (cRawExt > RT_ELEMENTS(aRawExt))
1881 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1882 rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1883 AssertRCReturn(rc, rc);
1884
1885 /*
1886 * Note that we support restoring less than the current amount of standard
1887 * leaves because we've been allowed more is newer version of VBox.
1888 *
1889 * So, pad new entries with the default.
1890 */
1891 for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1892 aGuestCpuIdStd[i] = GuestCpuIdDef;
1893
1894 for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1895 aGuestCpuIdExt[i] = GuestCpuIdDef;
1896
1897 for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1898 aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1899
1900 for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1901 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1902
1903 for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1904 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1905
1906 /*
1907 * Get the raw CPU IDs for the current host.
1908 */
1909 CPUMCPUID aHostRawStd[16];
1910 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1911 ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1912
1913 CPUMCPUID aHostRawExt[32];
1914 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1915 ASMCpuId(i | UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1916
1917 /*
1918 * Get the host and guest overrides so we don't reject the state because
1919 * some feature was enabled thru these interfaces.
1920 * Note! We currently only need the feature leaves, so skip rest.
1921 */
1922 PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1923 CPUMCPUID aGuestOverrideStd[2];
1924 memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1925 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1926
1927 CPUMCPUID aGuestOverrideExt[2];
1928 memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1929 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1930
1931 pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1932 CPUMCPUID aHostOverrideStd[2];
1933 memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1934 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1935
1936 CPUMCPUID aHostOverrideExt[2];
1937 memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1938 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1939
1940 /*
1941 * This can be skipped.
1942 */
1943 bool fStrictCpuIdChecks;
1944 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1945
1946
1947
1948 /*
1949 * For raw-mode we'll require that the CPUs are very similar since we don't
1950 * intercept CPUID instructions for user mode applications.
1951 */
1952 if (!HMIsEnabled(pVM))
1953 {
1954 /* CPUID(0) */
1955 CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1956 && aHostRawStd[0].ecx == aRawStd[0].ecx
1957 && aHostRawStd[0].edx == aRawStd[0].edx,
1958 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1959 &aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1960 &aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1961 CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1962 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1963 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1964
1965 bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1966
1967 /* CPUID(1).eax */
1968 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1969 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1970 CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1971
1972 /* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1973 CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1974 CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1975
1976 /* CPUID(1).ecx */
1977 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1978 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1979 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1980 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1981 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1982 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1983 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1984 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1985 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1986 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1987 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1988 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
1989 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1990 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1991 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1992 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1993 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
1994 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
1995 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1996 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1997 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1998 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1999 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
2000 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
2001 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
2002 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
2003 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
2004 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
2005 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
2006 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
2007 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
2008 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_HVP);
2009
2010 /* CPUID(1).edx */
2011 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2012 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2013 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
2014 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2015 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
2016 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
2017 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2018 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2019 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
2020 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2021 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2022 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2023 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2024 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2025 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2026 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
2027 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2028 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2029 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2030 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
2031 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2032 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
2033 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
2034 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
2035 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
2036 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
2037 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
2038 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
2039 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
2040 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
2041 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/);
2042 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
2043
2044 /* CPUID(2) - config, mostly about caches. ignore. */
2045 /* CPUID(3) - processor serial number. ignore. */
2046 /* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
2047 /* CPUID(5) - mwait/monitor config. ignore. */
2048 /* CPUID(6) - power management. ignore. */
2049 /* CPUID(7) - ???. ignore. */
2050 /* CPUID(8) - ???. ignore. */
2051 /* CPUID(9) - DCA. ignore for now. */
2052 /* CPUID(a) - PeMo info. ignore for now. */
2053 /* CPUID(b) - topology info - takes ECX as input. ignore. */
2054
2055 /* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
2056 CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
2057 || aHostRawStd[0].eax >= UINT32_C(0x0000000d),
2058 ("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
2059 if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
2060 && aHostRawStd[0].eax >= UINT32_C(0x0000000d))
2061 {
2062 CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
2063 CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
2064 CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
2065 CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
2066 }
2067
2068 /* CPUID(0x80000000) - same as CPUID(0) except for eax.
2069 Note! Intel have/is marking many of the fields here as reserved. We
2070 will verify them as if it's an AMD CPU. */
2071 CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
2072 || !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
2073 (N_("Extended leaves was present on saved state host, but is missing on the current\n")));
2074 if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
2075 {
2076 CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
2077 && aHostRawExt[0].ecx == aRawExt[0].ecx
2078 && aHostRawExt[0].edx == aRawExt[0].edx,
2079 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
2080 &aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
2081 &aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
2082 CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
2083
2084 /* CPUID(0x80000001).eax - same as CPUID(0).eax. */
2085 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
2086 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
2087 CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
2088 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
2089 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
2090
2091 /* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
2092 CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
2093 CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
2094 CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
2095
2096 /* CPUID(0x80000001).ecx */
2097 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2098 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
2099 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
2100 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
2101 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2102 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
2103 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
2104 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
2105 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
2106 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
2107 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
2108 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
2109 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
2110 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
2111 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2112 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2113 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2114 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2115 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2116 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2117 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2118 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2119 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2120 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2121 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2122 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2123 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2124 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2125 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2126 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2127 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2128 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2129
2130 /* CPUID(0x80000001).edx */
2131 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
2132 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
2133 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
2134 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
2135 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
2136 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
2137 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
2138 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
2139 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
2140 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
2141 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2142 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SEP);
2143 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
2144 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
2145 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
2146 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2147 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
2148 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
2149 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2150 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2151 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2152 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /*reserved*/);
2153 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2154 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
2155 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
2156 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2157 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2158 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2159 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /*reserved*/);
2160 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2161 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2162 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2163
2164 /** @todo verify the rest as well. */
2165 }
2166 }
2167
2168
2169
2170 /*
2171 * Verify that we can support the features already exposed to the guest on
2172 * this host.
2173 *
2174 * Most of the features we're emulating requires intercepting instruction
2175 * and doing it the slow way, so there is no need to warn when they aren't
2176 * present in the host CPU. Thus we use IGN instead of EMU on these.
2177 *
2178 * Trailing comments:
2179 * "EMU" - Possible to emulate, could be lots of work and very slow.
2180 * "EMU?" - Can this be emulated?
2181 */
2182 /* CPUID(1).ecx */
2183 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
2184 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
2185 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
2186 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
2187 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
2188 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
2189 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
2190 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
2191 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
2192 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
2193 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
2194 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
2195 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
2196 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
2197 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
2198 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
2199 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
2200 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
2201 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
2202 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
2203 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
2204 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
2205 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
2206 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
2207 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
2208 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
2209 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
2210 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
2211 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
2212 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
2213 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
2214 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
2215
2216 /* CPUID(1).edx */
2217 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2218 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2219 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
2220 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2221 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2222 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2223 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2224 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2225 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2226 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2227 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2228 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2229 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2230 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2231 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2232 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2233 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2234 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2235 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2236 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
2237 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2238 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
2239 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
2240 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2241 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2242 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
2243 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
2244 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
2245 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
2246 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
2247 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/); // -> EMU
2248 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
2249
2250 /* CPUID(0x80000000). */
2251 if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
2252 && aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
2253 {
2254 /** @todo deal with no 0x80000001 on the host. */
2255 bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
2256 bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
2257
2258 /* CPUID(0x80000001).ecx */
2259 CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
2260 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
2261 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
2262 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
2263 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
2264 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
2265 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
2266 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
2267 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
2268 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
2269 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
2270 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
2271 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
2272 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
2273 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2274 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2275 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2276 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2277 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2278 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2279 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2280 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2281 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2282 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2283 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2284 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2285 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2286 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2287 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2288 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2289 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2290 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2291
2292 /* CPUID(0x80000001).edx */
2293 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
2294 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
2295 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
2296 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
2297 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2298 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2299 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
2300 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
2301 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2302 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
2303 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2304 CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
2305 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
2306 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
2307 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
2308 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2309 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
2310 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
2311 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2312 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2313 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2314 CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /*reserved*/);
2315 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2316 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2317 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2318 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2319 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2320 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2321 CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /*reserved*/);
2322 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2323 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2324 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2325 }
2326
2327 /*
2328 * We're good, commit the CPU ID leaves.
2329 */
2330 memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
2331 memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
2332 memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
2333 pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
2334
2335#undef CPUID_CHECK_RET
2336#undef CPUID_CHECK_WRN
2337#undef CPUID_CHECK2_RET
2338#undef CPUID_CHECK2_WRN
2339#undef CPUID_RAW_FEATURE_RET
2340#undef CPUID_RAW_FEATURE_WRN
2341#undef CPUID_RAW_FEATURE_IGN
2342#undef CPUID_GST_FEATURE_RET
2343#undef CPUID_GST_FEATURE_WRN
2344#undef CPUID_GST_FEATURE_EMU
2345#undef CPUID_GST_FEATURE_IGN
2346#undef CPUID_GST_FEATURE2_RET
2347#undef CPUID_GST_FEATURE2_WRN
2348#undef CPUID_GST_FEATURE2_EMU
2349#undef CPUID_GST_FEATURE2_IGN
2350#undef CPUID_GST_AMD_FEATURE_RET
2351#undef CPUID_GST_AMD_FEATURE_WRN
2352#undef CPUID_GST_AMD_FEATURE_EMU
2353#undef CPUID_GST_AMD_FEATURE_IGN
2354
2355 return VINF_SUCCESS;
2356}
2357
2358
2359/**
2360 * Pass 0 live exec callback.
2361 *
2362 * @returns VINF_SSM_DONT_CALL_AGAIN.
2363 * @param pVM Pointer to the VM.
2364 * @param pSSM The saved state handle.
2365 * @param uPass The pass (0).
2366 */
2367static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2368{
2369 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2370 cpumR3SaveCpuId(pVM, pSSM);
2371 return VINF_SSM_DONT_CALL_AGAIN;
2372}
2373
2374
2375/**
2376 * Execute state save operation.
2377 *
2378 * @returns VBox status code.
2379 * @param pVM Pointer to the VM.
2380 * @param pSSM SSM operation handle.
2381 */
2382static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2383{
2384 /*
2385 * Save.
2386 */
2387 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2388 {
2389 PVMCPU pVCpu = &pVM->aCpus[i];
2390 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
2391 }
2392
2393 SSMR3PutU32(pSSM, pVM->cCpus);
2394 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
2395 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2396 {
2397 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2398
2399 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), 0, g_aCpumCtxFields, NULL);
2400 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2401 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2402 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2403 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2404 }
2405
2406 cpumR3SaveCpuId(pVM, pSSM);
2407 return VINF_SUCCESS;
2408}
2409
2410
2411/**
2412 * @copydoc FNSSMINTLOADPREP
2413 */
2414static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2415{
2416 NOREF(pSSM);
2417 pVM->cpum.s.fPendingRestore = true;
2418 return VINF_SUCCESS;
2419}
2420
2421
2422/**
2423 * @copydoc FNSSMINTLOADEXEC
2424 */
2425static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2426{
2427 /*
2428 * Validate version.
2429 */
2430 if ( uVersion != CPUM_SAVED_STATE_VERSION
2431 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
2432 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2433 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2434 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2435 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2436 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2437 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2438 {
2439 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2440 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2441 }
2442
2443 if (uPass == SSM_PASS_FINAL)
2444 {
2445 /*
2446 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2447 * really old SSM file versions.)
2448 */
2449 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2450 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2451 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2452 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2453
2454 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2455 PCSSMFIELD paCpumCtxFields = g_aCpumCtxFields;
2456 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2457 paCpumCtxFields = g_aCpumCtxFieldsV16;
2458 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2459 paCpumCtxFields = g_aCpumCtxFieldsMem;
2460
2461 /*
2462 * Restore.
2463 */
2464 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2465 {
2466 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2467 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2468 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2469 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), fLoad, paCpumCtxFields, NULL);
2470 pVCpu->cpum.s.Hyper.cr3 = uCR3;
2471 pVCpu->cpum.s.Hyper.rsp = uRSP;
2472 }
2473
2474 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2475 {
2476 uint32_t cCpus;
2477 int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2478 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2479 VERR_SSM_UNEXPECTED_DATA);
2480 }
2481 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2482 || pVM->cCpus == 1,
2483 ("cCpus=%u\n", pVM->cCpus),
2484 VERR_SSM_UNEXPECTED_DATA);
2485
2486 uint32_t cbMsrs = 0;
2487 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2488 {
2489 int rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2490 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2491 VERR_SSM_UNEXPECTED_DATA);
2492 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2493 VERR_SSM_UNEXPECTED_DATA);
2494 }
2495
2496 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2497 {
2498 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2499 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), fLoad,
2500 paCpumCtxFields, NULL);
2501 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
2502 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2503 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2504 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2505 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2506 {
2507 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2508 SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2509 }
2510 }
2511
2512 /* Older states does not have the internal selector register flags
2513 and valid selector value. Supply those. */
2514 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2515 {
2516 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2517 {
2518 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2519 bool const fValid = HMIsEnabled(pVM)
2520 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2521 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2522 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2523 if (fValid)
2524 {
2525 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2526 {
2527 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2528 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2529 }
2530
2531 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2532 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2533 }
2534 else
2535 {
2536 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2537 {
2538 paSelReg[iSelReg].fFlags = 0;
2539 paSelReg[iSelReg].ValidSel = 0;
2540 }
2541
2542 /* This might not be 104% correct, but I think it's close
2543 enough for all practical purposes... (REM always loaded
2544 LDTR registers.) */
2545 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2546 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2547 }
2548 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2549 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2550 }
2551 }
2552
2553 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2554 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2555 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2556 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2557 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2558
2559 /*
2560 * A quick sanity check.
2561 */
2562 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2563 {
2564 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2565 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2566 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2567 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2568 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2569 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2570 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2571 }
2572 }
2573
2574 pVM->cpum.s.fPendingRestore = false;
2575
2576 /*
2577 * Guest CPUIDs.
2578 */
2579 if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2580 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2581
2582 /** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2583 * actually required. */
2584
2585 /*
2586 * Restore the CPUID leaves.
2587 *
2588 * Note that we support restoring less than the current amount of standard
2589 * leaves because we've been allowed more is newer version of VBox.
2590 */
2591 uint32_t cElements;
2592 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2593 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2594 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2595 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2596
2597 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2598 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2599 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2600 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2601
2602 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2603 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2604 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2605 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2606
2607 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2608
2609 /*
2610 * Check that the basic cpuid id information is unchanged.
2611 */
2612 /** @todo we should check the 64 bits capabilities too! */
2613 uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2614 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2615 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2616 uint32_t au32CpuIdSaved[8];
2617 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2618 if (RT_SUCCESS(rc))
2619 {
2620 /* Ignore CPU stepping. */
2621 au32CpuId[4] &= 0xfffffff0;
2622 au32CpuIdSaved[4] &= 0xfffffff0;
2623
2624 /* Ignore APIC ID (AMD specs). */
2625 au32CpuId[5] &= ~0xff000000;
2626 au32CpuIdSaved[5] &= ~0xff000000;
2627
2628 /* Ignore the number of Logical CPUs (AMD specs). */
2629 au32CpuId[5] &= ~0x00ff0000;
2630 au32CpuIdSaved[5] &= ~0x00ff0000;
2631
2632 /* Ignore some advanced capability bits, that we don't expose to the guest. */
2633 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2634 | X86_CPUID_FEATURE_ECX_VMX
2635 | X86_CPUID_FEATURE_ECX_SMX
2636 | X86_CPUID_FEATURE_ECX_EST
2637 | X86_CPUID_FEATURE_ECX_TM2
2638 | X86_CPUID_FEATURE_ECX_CNTXID
2639 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2640 | X86_CPUID_FEATURE_ECX_PDCM
2641 | X86_CPUID_FEATURE_ECX_DCA
2642 | X86_CPUID_FEATURE_ECX_X2APIC
2643 );
2644 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2645 | X86_CPUID_FEATURE_ECX_VMX
2646 | X86_CPUID_FEATURE_ECX_SMX
2647 | X86_CPUID_FEATURE_ECX_EST
2648 | X86_CPUID_FEATURE_ECX_TM2
2649 | X86_CPUID_FEATURE_ECX_CNTXID
2650 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2651 | X86_CPUID_FEATURE_ECX_PDCM
2652 | X86_CPUID_FEATURE_ECX_DCA
2653 | X86_CPUID_FEATURE_ECX_X2APIC
2654 );
2655
2656 /* Make sure we don't forget to update the masks when enabling
2657 * features in the future.
2658 */
2659 AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2660 ( X86_CPUID_FEATURE_ECX_DTES64
2661 | X86_CPUID_FEATURE_ECX_VMX
2662 | X86_CPUID_FEATURE_ECX_SMX
2663 | X86_CPUID_FEATURE_ECX_EST
2664 | X86_CPUID_FEATURE_ECX_TM2
2665 | X86_CPUID_FEATURE_ECX_CNTXID
2666 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2667 | X86_CPUID_FEATURE_ECX_PDCM
2668 | X86_CPUID_FEATURE_ECX_DCA
2669 | X86_CPUID_FEATURE_ECX_X2APIC
2670 )));
2671 /* do the compare */
2672 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2673 {
2674 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2675 LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2676 "Saved=%.*Rhxs\n"
2677 "Real =%.*Rhxs\n",
2678 sizeof(au32CpuIdSaved), au32CpuIdSaved,
2679 sizeof(au32CpuId), au32CpuId));
2680 else
2681 {
2682 LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2683 "Saved=%.*Rhxs\n"
2684 "Real =%.*Rhxs\n",
2685 sizeof(au32CpuIdSaved), au32CpuIdSaved,
2686 sizeof(au32CpuId), au32CpuId));
2687 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2688 }
2689 }
2690 }
2691
2692 return rc;
2693}
2694
2695
2696/**
2697 * @copydoc FNSSMINTLOADPREP
2698 */
2699static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2700{
2701 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2702 return VINF_SUCCESS;
2703
2704 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2705 if (pVM->cpum.s.fPendingRestore)
2706 {
2707 LogRel(("CPUM: Missing state!\n"));
2708 return VERR_INTERNAL_ERROR_2;
2709 }
2710
2711 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2712 {
2713 /* Notify PGM of the NXE states in case they've changed. */
2714 PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2715
2716 /* Cache the local APIC base from the APIC device. During init. this is done in CPUMR3ResetCpu(). */
2717 PDMApicGetBase(&pVM->aCpus[iCpu], &pVM->aCpus[iCpu].cpum.s.Guest.msrApicBase);
2718 }
2719 return VINF_SUCCESS;
2720}
2721
2722
2723/**
2724 * Checks if the CPUM state restore is still pending.
2725 *
2726 * @returns true / false.
2727 * @param pVM Pointer to the VM.
2728 */
2729VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2730{
2731 return pVM->cpum.s.fPendingRestore;
2732}
2733
2734
2735/**
2736 * Formats the EFLAGS value into mnemonics.
2737 *
2738 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2739 * @param efl The EFLAGS value.
2740 */
2741static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2742{
2743 /*
2744 * Format the flags.
2745 */
2746 static const struct
2747 {
2748 const char *pszSet; const char *pszClear; uint32_t fFlag;
2749 } s_aFlags[] =
2750 {
2751 { "vip",NULL, X86_EFL_VIP },
2752 { "vif",NULL, X86_EFL_VIF },
2753 { "ac", NULL, X86_EFL_AC },
2754 { "vm", NULL, X86_EFL_VM },
2755 { "rf", NULL, X86_EFL_RF },
2756 { "nt", NULL, X86_EFL_NT },
2757 { "ov", "nv", X86_EFL_OF },
2758 { "dn", "up", X86_EFL_DF },
2759 { "ei", "di", X86_EFL_IF },
2760 { "tf", NULL, X86_EFL_TF },
2761 { "nt", "pl", X86_EFL_SF },
2762 { "nz", "zr", X86_EFL_ZF },
2763 { "ac", "na", X86_EFL_AF },
2764 { "po", "pe", X86_EFL_PF },
2765 { "cy", "nc", X86_EFL_CF },
2766 };
2767 char *psz = pszEFlags;
2768 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2769 {
2770 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2771 if (pszAdd)
2772 {
2773 strcpy(psz, pszAdd);
2774 psz += strlen(pszAdd);
2775 *psz++ = ' ';
2776 }
2777 }
2778 psz[-1] = '\0';
2779}
2780
2781
2782/**
2783 * Formats a full register dump.
2784 *
2785 * @param pVM Pointer to the VM.
2786 * @param pCtx The context to format.
2787 * @param pCtxCore The context core to format.
2788 * @param pHlp Output functions.
2789 * @param enmType The dump type.
2790 * @param pszPrefix Register name prefix.
2791 */
2792static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
2793 const char *pszPrefix)
2794{
2795 NOREF(pVM);
2796
2797 /*
2798 * Format the EFLAGS.
2799 */
2800 uint32_t efl = pCtxCore->eflags.u32;
2801 char szEFlags[80];
2802 cpumR3InfoFormatFlags(&szEFlags[0], efl);
2803
2804 /*
2805 * Format the registers.
2806 */
2807 switch (enmType)
2808 {
2809 case CPUMDUMPTYPE_TERSE:
2810 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2811 pHlp->pfnPrintf(pHlp,
2812 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2813 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2814 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2815 "%sr14=%016RX64 %sr15=%016RX64\n"
2816 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2817 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2818 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2819 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2820 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2821 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2822 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2823 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2824 else
2825 pHlp->pfnPrintf(pHlp,
2826 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2827 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2828 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2829 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2830 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2831 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2832 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2833 break;
2834
2835 case CPUMDUMPTYPE_DEFAULT:
2836 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2837 pHlp->pfnPrintf(pHlp,
2838 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2839 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2840 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2841 "%sr14=%016RX64 %sr15=%016RX64\n"
2842 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2843 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2844 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2845 ,
2846 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2847 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2848 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2849 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2850 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2851 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2852 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2853 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2854 else
2855 pHlp->pfnPrintf(pHlp,
2856 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2857 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2858 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2859 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2860 ,
2861 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2862 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2863 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2864 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2865 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2866 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2867 break;
2868
2869 case CPUMDUMPTYPE_VERBOSE:
2870 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2871 pHlp->pfnPrintf(pHlp,
2872 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2873 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2874 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2875 "%sr14=%016RX64 %sr15=%016RX64\n"
2876 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2877 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2878 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2879 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2880 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2881 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2882 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2883 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2884 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2885 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2886 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2887 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2888 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2889 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2890 ,
2891 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2892 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2893 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2894 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2895 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2896 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2897 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2898 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2899 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2900 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2901 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2902 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2903 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2904 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2905 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2906 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2907 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2908 else
2909 pHlp->pfnPrintf(pHlp,
2910 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2911 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2912 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2913 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2914 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2915 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2916 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2917 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2918 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2919 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2920 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2921 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2922 ,
2923 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2924 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2925 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2926 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2927 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2928 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2929 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2930 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2931 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2932 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2933 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2934 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2935
2936 pHlp->pfnPrintf(pHlp,
2937 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2938 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2939 ,
2940 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2941 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2942 pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsrvd1,
2943 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2944 );
2945 unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2946 for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2947 {
2948 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2949 unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2950 char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2951 unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2952 uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2953 unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2954 /** @todo This isn't entirenly correct and needs more work! */
2955 pHlp->pfnPrintf(pHlp,
2956 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2957 pszPrefix, iST, pszPrefix, iFPR,
2958 pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2959 uTag, chSign, iInteger, u64Fraction, uExponent);
2960 if (pCtx->fpu.aRegs[0].au16[5] || pCtx->fpu.aRegs[0].au16[6] || pCtx->fpu.aRegs[0].au16[7])
2961 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2962 pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2963 else
2964 pHlp->pfnPrintf(pHlp, "\n");
2965 }
2966 for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2967 pHlp->pfnPrintf(pHlp,
2968 iXMM & 1
2969 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2970 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2971 pszPrefix, iXMM, iXMM < 10 ? " " : "",
2972 pCtx->fpu.aXMM[iXMM].au32[3],
2973 pCtx->fpu.aXMM[iXMM].au32[2],
2974 pCtx->fpu.aXMM[iXMM].au32[1],
2975 pCtx->fpu.aXMM[iXMM].au32[0]);
2976 for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2977 if (pCtx->fpu.au32RsrvdRest[i])
2978 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2979 pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2980
2981 pHlp->pfnPrintf(pHlp,
2982 "%sEFER =%016RX64\n"
2983 "%sPAT =%016RX64\n"
2984 "%sSTAR =%016RX64\n"
2985 "%sCSTAR =%016RX64\n"
2986 "%sLSTAR =%016RX64\n"
2987 "%sSFMASK =%016RX64\n"
2988 "%sKERNELGSBASE =%016RX64\n",
2989 pszPrefix, pCtx->msrEFER,
2990 pszPrefix, pCtx->msrPAT,
2991 pszPrefix, pCtx->msrSTAR,
2992 pszPrefix, pCtx->msrCSTAR,
2993 pszPrefix, pCtx->msrLSTAR,
2994 pszPrefix, pCtx->msrSFMASK,
2995 pszPrefix, pCtx->msrKERNELGSBASE);
2996 break;
2997 }
2998}
2999
3000
3001/**
3002 * Display all cpu states and any other cpum info.
3003 *
3004 * @param pVM Pointer to the VM.
3005 * @param pHlp The info helper functions.
3006 * @param pszArgs Arguments, ignored.
3007 */
3008static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3009{
3010 cpumR3InfoGuest(pVM, pHlp, pszArgs);
3011 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3012 cpumR3InfoHyper(pVM, pHlp, pszArgs);
3013 cpumR3InfoHost(pVM, pHlp, pszArgs);
3014}
3015
3016
3017/**
3018 * Parses the info argument.
3019 *
3020 * The argument starts with 'verbose', 'terse' or 'default' and then
3021 * continues with the comment string.
3022 *
3023 * @param pszArgs The pointer to the argument string.
3024 * @param penmType Where to store the dump type request.
3025 * @param ppszComment Where to store the pointer to the comment string.
3026 */
3027static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
3028{
3029 if (!pszArgs)
3030 {
3031 *penmType = CPUMDUMPTYPE_DEFAULT;
3032 *ppszComment = "";
3033 }
3034 else
3035 {
3036 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
3037 {
3038 pszArgs += 7;
3039 *penmType = CPUMDUMPTYPE_VERBOSE;
3040 }
3041 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
3042 {
3043 pszArgs += 5;
3044 *penmType = CPUMDUMPTYPE_TERSE;
3045 }
3046 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
3047 {
3048 pszArgs += 7;
3049 *penmType = CPUMDUMPTYPE_DEFAULT;
3050 }
3051 else
3052 *penmType = CPUMDUMPTYPE_DEFAULT;
3053 *ppszComment = RTStrStripL(pszArgs);
3054 }
3055}
3056
3057
3058/**
3059 * Display the guest cpu state.
3060 *
3061 * @param pVM Pointer to the VM.
3062 * @param pHlp The info helper functions.
3063 * @param pszArgs Arguments, ignored.
3064 */
3065static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3066{
3067 CPUMDUMPTYPE enmType;
3068 const char *pszComment;
3069 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3070
3071 /* @todo SMP support! */
3072 PVMCPU pVCpu = VMMGetCpu(pVM);
3073 if (!pVCpu)
3074 pVCpu = &pVM->aCpus[0];
3075
3076 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3077
3078 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3079 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3080}
3081
3082
3083/**
3084 * Display the current guest instruction
3085 *
3086 * @param pVM Pointer to the VM.
3087 * @param pHlp The info helper functions.
3088 * @param pszArgs Arguments, ignored.
3089 */
3090static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3091{
3092 NOREF(pszArgs);
3093
3094 /** @todo SMP support! */
3095 PVMCPU pVCpu = VMMGetCpu(pVM);
3096 if (!pVCpu)
3097 pVCpu = &pVM->aCpus[0];
3098
3099 char szInstruction[256];
3100 int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
3101 if (RT_SUCCESS(rc))
3102 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
3103}
3104
3105
3106/**
3107 * Display the hypervisor cpu state.
3108 *
3109 * @param pVM Pointer to the VM.
3110 * @param pHlp The info helper functions.
3111 * @param pszArgs Arguments, ignored.
3112 */
3113static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3114{
3115 CPUMDUMPTYPE enmType;
3116 const char *pszComment;
3117 /* @todo SMP */
3118 PVMCPU pVCpu = &pVM->aCpus[0];
3119
3120 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3121 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
3122 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
3123 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
3124}
3125
3126
3127/**
3128 * Display the host cpu state.
3129 *
3130 * @param pVM Pointer to the VM.
3131 * @param pHlp The info helper functions.
3132 * @param pszArgs Arguments, ignored.
3133 */
3134static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3135{
3136 CPUMDUMPTYPE enmType;
3137 const char *pszComment;
3138 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3139 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
3140
3141 /*
3142 * Format the EFLAGS.
3143 */
3144 /* @todo SMP */
3145 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
3146#if HC_ARCH_BITS == 32
3147 uint32_t efl = pCtx->eflags.u32;
3148#else
3149 uint64_t efl = pCtx->rflags;
3150#endif
3151 char szEFlags[80];
3152 cpumR3InfoFormatFlags(&szEFlags[0], efl);
3153
3154 /*
3155 * Format the registers.
3156 */
3157#if HC_ARCH_BITS == 32
3158# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3159 if (!(pCtx->efer & MSR_K6_EFER_LMA))
3160# endif
3161 {
3162 pHlp->pfnPrintf(pHlp,
3163 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
3164 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
3165 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
3166 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
3167 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
3168 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3169 ,
3170 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
3171 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
3172 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3173 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
3174 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
3175 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
3176 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3177 }
3178# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3179 else
3180# endif
3181#endif
3182#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3183 {
3184 pHlp->pfnPrintf(pHlp,
3185 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
3186 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
3187 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
3188 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
3189 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
3190 "r14=%016RX64 r15=%016RX64\n"
3191 "iopl=%d %31s\n"
3192 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
3193 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
3194 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
3195 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
3196 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
3197 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
3198 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3199 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
3200 ,
3201 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
3202 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
3203 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
3204 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
3205 pCtx->r11, pCtx->r12, pCtx->r13,
3206 pCtx->r14, pCtx->r15,
3207 X86_EFL_GET_IOPL(efl), szEFlags,
3208 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3209 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
3210 pCtx->cr4, pCtx->ldtr, pCtx->tr,
3211 pCtx->dr0, pCtx->dr1, pCtx->dr2,
3212 pCtx->dr3, pCtx->dr6, pCtx->dr7,
3213 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
3214 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
3215 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
3216 }
3217#endif
3218}
3219
3220
3221/**
3222 * Get L1 cache / TLS associativity.
3223 */
3224static const char *getCacheAss(unsigned u, char *pszBuf)
3225{
3226 if (u == 0)
3227 return "res0 ";
3228 if (u == 1)
3229 return "direct";
3230 if (u == 255)
3231 return "fully";
3232 if (u >= 256)
3233 return "???";
3234
3235 RTStrPrintf(pszBuf, 16, "%d way", u);
3236 return pszBuf;
3237}
3238
3239
3240/**
3241 * Get L2 cache associativity.
3242 */
3243const char *getL2CacheAss(unsigned u)
3244{
3245 switch (u)
3246 {
3247 case 0: return "off ";
3248 case 1: return "direct";
3249 case 2: return "2 way ";
3250 case 3: return "res3 ";
3251 case 4: return "4 way ";
3252 case 5: return "res5 ";
3253 case 6: return "8 way ";
3254 case 7: return "res7 ";
3255 case 8: return "16 way";
3256 case 9: return "res9 ";
3257 case 10: return "res10 ";
3258 case 11: return "res11 ";
3259 case 12: return "res12 ";
3260 case 13: return "res13 ";
3261 case 14: return "res14 ";
3262 case 15: return "fully ";
3263 default: return "????";
3264 }
3265}
3266
3267
3268/**
3269 * Display the guest CpuId leaves.
3270 *
3271 * @param pVM Pointer to the VM.
3272 * @param pHlp The info helper functions.
3273 * @param pszArgs "terse", "default" or "verbose".
3274 */
3275static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3276{
3277 /*
3278 * Parse the argument.
3279 */
3280 unsigned iVerbosity = 1;
3281 if (pszArgs)
3282 {
3283 pszArgs = RTStrStripL(pszArgs);
3284 if (!strcmp(pszArgs, "terse"))
3285 iVerbosity--;
3286 else if (!strcmp(pszArgs, "verbose"))
3287 iVerbosity++;
3288 }
3289
3290 /*
3291 * Start cracking.
3292 */
3293 CPUMCPUID Host;
3294 CPUMCPUID Guest;
3295 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
3296
3297 pHlp->pfnPrintf(pHlp,
3298 " RAW Standard CPUIDs\n"
3299 " Function eax ebx ecx edx\n");
3300 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
3301 {
3302 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
3303 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3304
3305 pHlp->pfnPrintf(pHlp,
3306 "Gst: %08x %08x %08x %08x %08x%s\n"
3307 "Hst: %08x %08x %08x %08x\n",
3308 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3309 i <= cStdMax ? "" : "*",
3310 Host.eax, Host.ebx, Host.ecx, Host.edx);
3311 }
3312
3313 /*
3314 * If verbose, decode it.
3315 */
3316 if (iVerbosity)
3317 {
3318 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
3319 pHlp->pfnPrintf(pHlp,
3320 "Name: %.04s%.04s%.04s\n"
3321 "Supports: 0-%x\n",
3322 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3323 }
3324
3325 /*
3326 * Get Features.
3327 */
3328 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
3329 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
3330 pVM->cpum.s.aGuestCpuIdStd[0].edx);
3331 if (cStdMax >= 1 && iVerbosity)
3332 {
3333 static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
3334
3335 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
3336 uint32_t uEAX = Guest.eax;
3337
3338 pHlp->pfnPrintf(pHlp,
3339 "Family: %d \tExtended: %d \tEffective: %d\n"
3340 "Model: %d \tExtended: %d \tEffective: %d\n"
3341 "Stepping: %d\n"
3342 "Type: %d (%s)\n"
3343 "APIC ID: %#04x\n"
3344 "Logical CPUs: %d\n"
3345 "CLFLUSH Size: %d\n"
3346 "Brand ID: %#04x\n",
3347 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3348 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3349 ASMGetCpuStepping(uEAX),
3350 (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
3351 (Guest.ebx >> 24) & 0xff,
3352 (Guest.ebx >> 16) & 0xff,
3353 (Guest.ebx >> 8) & 0xff,
3354 (Guest.ebx >> 0) & 0xff);
3355 if (iVerbosity == 1)
3356 {
3357 uint32_t uEDX = Guest.edx;
3358 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3359 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3360 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3361 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3362 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3363 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3364 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3365 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3366 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3367 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3368 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3369 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3370 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
3371 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3372 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3373 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3374 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3375 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3376 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3377 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
3378 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
3379 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
3380 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
3381 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
3382 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3383 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3384 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
3385 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
3386 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
3387 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
3388 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
3389 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3390 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
3391 pHlp->pfnPrintf(pHlp, "\n");
3392
3393 uint32_t uECX = Guest.ecx;
3394 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3395 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
3396 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
3397 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
3398 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
3399 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
3400 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
3401 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
3402 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
3403 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
3404 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
3405 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
3406 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
3407 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
3408 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
3409 if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
3410 if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
3411 if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
3412 if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID");
3413 if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
3414 if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1");
3415 if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2");
3416 if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
3417 if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
3418 if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
3419 if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL");
3420 if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
3421 if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
3422 if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
3423 if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
3424 if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
3425 if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3426 if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
3427 pHlp->pfnPrintf(pHlp, "\n");
3428 }
3429 else
3430 {
3431 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3432
3433 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
3434 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
3435 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
3436 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
3437
3438 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3439 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
3440 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
3441 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
3442 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
3443 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
3444 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
3445 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
3446 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
3447 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
3448 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
3449 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
3450 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
3451 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
3452 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
3453 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
3454 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
3455 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
3456 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
3457 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
3458 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
3459 pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
3460 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
3461 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
3462 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
3463 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
3464 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
3465 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
3466 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
3467 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technology = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
3468 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
3469 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
3470 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
3471
3472 pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
3473 pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ);
3474 pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
3475 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
3476 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
3477 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
3478 pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
3479 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
3480 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
3481 pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
3482 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
3483 pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
3484 pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
3485 pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
3486 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
3487 pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
3488 pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
3489 pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID);
3490 pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
3491 pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
3492 pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
3493 pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
3494 pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
3495 pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
3496 pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE);
3497 pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES);
3498 pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
3499 pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
3500 pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX);
3501 pHlp->pfnPrintf(pHlp, "29/30 - Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
3502 pHlp->pfnPrintf(pHlp, "Hypervisor Present (we're a guest) = %d (%d)\n", EcxGuest.u1HVP, EcxHost.u1HVP);
3503 }
3504 }
3505 if (cStdMax >= 2 && iVerbosity)
3506 {
3507 /** @todo */
3508 }
3509
3510 /*
3511 * Extended.
3512 * Implemented after AMD specs.
3513 */
3514 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
3515
3516 pHlp->pfnPrintf(pHlp,
3517 "\n"
3518 " RAW Extended CPUIDs\n"
3519 " Function eax ebx ecx edx\n");
3520 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
3521 {
3522 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
3523 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3524
3525 pHlp->pfnPrintf(pHlp,
3526 "Gst: %08x %08x %08x %08x %08x%s\n"
3527 "Hst: %08x %08x %08x %08x\n",
3528 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3529 i <= cExtMax ? "" : "*",
3530 Host.eax, Host.ebx, Host.ecx, Host.edx);
3531 }
3532
3533 /*
3534 * Understandable output
3535 */
3536 if (iVerbosity)
3537 {
3538 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
3539 pHlp->pfnPrintf(pHlp,
3540 "Ext Name: %.4s%.4s%.4s\n"
3541 "Ext Supports: 0x80000000-%#010x\n",
3542 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3543 }
3544
3545 if (iVerbosity && cExtMax >= 1)
3546 {
3547 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
3548 uint32_t uEAX = Guest.eax;
3549 pHlp->pfnPrintf(pHlp,
3550 "Family: %d \tExtended: %d \tEffective: %d\n"
3551 "Model: %d \tExtended: %d \tEffective: %d\n"
3552 "Stepping: %d\n"
3553 "Brand ID: %#05x\n",
3554 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3555 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3556 ASMGetCpuStepping(uEAX),
3557 Guest.ebx & 0xfff);
3558
3559 if (iVerbosity == 1)
3560 {
3561 uint32_t uEDX = Guest.edx;
3562 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3563 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3564 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3565 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3566 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3567 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3568 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3569 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3570 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3571 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3572 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3573 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3574 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
3575 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3576 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3577 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3578 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3579 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3580 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3581 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
3582 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
3583 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
3584 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
3585 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
3586 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3587 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3588 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
3589 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
3590 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
3591 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
3592 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
3593 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
3594 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
3595 pHlp->pfnPrintf(pHlp, "\n");
3596
3597 uint32_t uECX = Guest.ecx;
3598 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3599 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
3600 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
3601 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
3602 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3603 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3604 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3605 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3606 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3607 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3608 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3609 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3610 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3611 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3612 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3613 for (unsigned iBit = 5; iBit < 32; iBit++)
3614 if (uECX & RT_BIT(iBit))
3615 pHlp->pfnPrintf(pHlp, " %d", iBit);
3616 pHlp->pfnPrintf(pHlp, "\n");
3617 }
3618 else
3619 {
3620 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3621
3622 uint32_t uEdxGst = Guest.edx;
3623 uint32_t uEdxHst = Host.edx;
3624 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3625 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3626 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3627 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3628 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3629 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3630 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3631 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3632 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3633 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3634 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3635 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3636 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3637 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3638 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3639 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3640 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3641 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3642 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3643 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3644 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3645 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3646 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3647 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3648 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3649 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3650 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3651 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3652 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3653 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3654 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3655 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3656 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3657
3658 uint32_t uEcxGst = Guest.ecx;
3659 uint32_t uEcxHst = Host.ecx;
3660 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3661 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3662 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3663 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3664 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3665 pHlp->pfnPrintf(pHlp, "5 - Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3666 pHlp->pfnPrintf(pHlp, "6 - SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3667 pHlp->pfnPrintf(pHlp, "7 - Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3668 pHlp->pfnPrintf(pHlp, "8 - PREFETCH and PREFETCHW instruction= %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3669 pHlp->pfnPrintf(pHlp, "9 - OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3670 pHlp->pfnPrintf(pHlp, "10 - Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3671 pHlp->pfnPrintf(pHlp, "11 - SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3672 pHlp->pfnPrintf(pHlp, "12 - SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3673 pHlp->pfnPrintf(pHlp, "13 - Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3674 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3675 }
3676 }
3677
3678 if (iVerbosity && cExtMax >= 2)
3679 {
3680 char szString[4*4*3+1] = {0};
3681 uint32_t *pu32 = (uint32_t *)szString;
3682 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3683 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3684 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3685 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3686 if (cExtMax >= 3)
3687 {
3688 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3689 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3690 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3691 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3692 }
3693 if (cExtMax >= 4)
3694 {
3695 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3696 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3697 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3698 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3699 }
3700 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3701 }
3702
3703 if (iVerbosity && cExtMax >= 5)
3704 {
3705 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3706 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3707 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3708 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3709 char sz1[32];
3710 char sz2[32];
3711
3712 pHlp->pfnPrintf(pHlp,
3713 "TLB 2/4M Instr/Uni: %s %3d entries\n"
3714 "TLB 2/4M Data: %s %3d entries\n",
3715 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3716 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3717 pHlp->pfnPrintf(pHlp,
3718 "TLB 4K Instr/Uni: %s %3d entries\n"
3719 "TLB 4K Data: %s %3d entries\n",
3720 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3721 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3722 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3723 "L1 Instr Cache Lines Per Tag: %d\n"
3724 "L1 Instr Cache Associativity: %s\n"
3725 "L1 Instr Cache Size: %d KB\n",
3726 (uEDX >> 0) & 0xff,
3727 (uEDX >> 8) & 0xff,
3728 getCacheAss((uEDX >> 16) & 0xff, sz1),
3729 (uEDX >> 24) & 0xff);
3730 pHlp->pfnPrintf(pHlp,
3731 "L1 Data Cache Line Size: %d bytes\n"
3732 "L1 Data Cache Lines Per Tag: %d\n"
3733 "L1 Data Cache Associativity: %s\n"
3734 "L1 Data Cache Size: %d KB\n",
3735 (uECX >> 0) & 0xff,
3736 (uECX >> 8) & 0xff,
3737 getCacheAss((uECX >> 16) & 0xff, sz1),
3738 (uECX >> 24) & 0xff);
3739 }
3740
3741 if (iVerbosity && cExtMax >= 6)
3742 {
3743 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3744 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3745 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3746
3747 pHlp->pfnPrintf(pHlp,
3748 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3749 "L2 TLB 2/4M Data: %s %4d entries\n",
3750 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3751 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3752 pHlp->pfnPrintf(pHlp,
3753 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
3754 "L2 TLB 4K Data: %s %4d entries\n",
3755 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3756 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3757 pHlp->pfnPrintf(pHlp,
3758 "L2 Cache Line Size: %d bytes\n"
3759 "L2 Cache Lines Per Tag: %d\n"
3760 "L2 Cache Associativity: %s\n"
3761 "L2 Cache Size: %d KB\n",
3762 (uEDX >> 0) & 0xff,
3763 (uEDX >> 8) & 0xf,
3764 getL2CacheAss((uEDX >> 12) & 0xf),
3765 (uEDX >> 16) & 0xffff);
3766 }
3767
3768 if (iVerbosity && cExtMax >= 7)
3769 {
3770 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3771
3772 pHlp->pfnPrintf(pHlp, "APM Features: ");
3773 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3774 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3775 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3776 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3777 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3778 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3779 for (unsigned iBit = 6; iBit < 32; iBit++)
3780 if (uEDX & RT_BIT(iBit))
3781 pHlp->pfnPrintf(pHlp, " %d", iBit);
3782 pHlp->pfnPrintf(pHlp, "\n");
3783 }
3784
3785 if (iVerbosity && cExtMax >= 8)
3786 {
3787 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3788 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3789
3790 pHlp->pfnPrintf(pHlp,
3791 "Physical Address Width: %d bits\n"
3792 "Virtual Address Width: %d bits\n"
3793 "Guest Physical Address Width: %d bits\n",
3794 (uEAX >> 0) & 0xff,
3795 (uEAX >> 8) & 0xff,
3796 (uEAX >> 16) & 0xff);
3797 pHlp->pfnPrintf(pHlp,
3798 "Physical Core Count: %d\n",
3799 (uECX >> 0) & 0xff);
3800 }
3801
3802
3803 /*
3804 * Centaur.
3805 */
3806 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3807
3808 pHlp->pfnPrintf(pHlp,
3809 "\n"
3810 " RAW Centaur CPUIDs\n"
3811 " Function eax ebx ecx edx\n");
3812 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3813 {
3814 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3815 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3816
3817 pHlp->pfnPrintf(pHlp,
3818 "Gst: %08x %08x %08x %08x %08x%s\n"
3819 "Hst: %08x %08x %08x %08x\n",
3820 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3821 i <= cCentaurMax ? "" : "*",
3822 Host.eax, Host.ebx, Host.ecx, Host.edx);
3823 }
3824
3825 /*
3826 * Understandable output
3827 */
3828 if (iVerbosity)
3829 {
3830 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3831 pHlp->pfnPrintf(pHlp,
3832 "Centaur Supports: 0xc0000000-%#010x\n",
3833 Guest.eax);
3834 }
3835
3836 if (iVerbosity && cCentaurMax >= 1)
3837 {
3838 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3839 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3840 uint32_t uEdxHst = Host.edx;
3841
3842 if (iVerbosity == 1)
3843 {
3844 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3845 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3846 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3847 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3848 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3849 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3850 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3851 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3852 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3853 /* possibly indicating MM/HE and MM/HE-E on older chips... */
3854 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3855 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3856 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3857 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3858 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3859 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3860 for (unsigned iBit = 14; iBit < 32; iBit++)
3861 if (uEdxGst & RT_BIT(iBit))
3862 pHlp->pfnPrintf(pHlp, " %d", iBit);
3863 pHlp->pfnPrintf(pHlp, "\n");
3864 }
3865 else
3866 {
3867 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3868 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3869 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3870 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3871 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3872 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3873 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3874 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3875 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3876 /* possibly indicating MM/HE and MM/HE-E on older chips... */
3877 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3878 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3879 pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3880 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3881 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3882 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3883 pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3884 pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3885 pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3886 pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3887 pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3888 pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3889 pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3890 pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3891 pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3892 pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3893 pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3894 pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3895 pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3896 for (unsigned iBit = 27; iBit < 32; iBit++)
3897 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
3898 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3899 pHlp->pfnPrintf(pHlp, "\n");
3900 }
3901 }
3902}
3903
3904
3905/**
3906 * Structure used when disassembling and instructions in DBGF.
3907 * This is used so the reader function can get the stuff it needs.
3908 */
3909typedef struct CPUMDISASSTATE
3910{
3911 /** Pointer to the CPU structure. */
3912 PDISCPUSTATE pCpu;
3913 /** Pointer to the VM. */
3914 PVM pVM;
3915 /** Pointer to the VMCPU. */
3916 PVMCPU pVCpu;
3917 /** Pointer to the first byte in the segment. */
3918 RTGCUINTPTR GCPtrSegBase;
3919 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
3920 RTGCUINTPTR GCPtrSegEnd;
3921 /** The size of the segment minus 1. */
3922 RTGCUINTPTR cbSegLimit;
3923 /** Pointer to the current page - R3 Ptr. */
3924 void const *pvPageR3;
3925 /** Pointer to the current page - GC Ptr. */
3926 RTGCPTR pvPageGC;
3927 /** The lock information that PGMPhysReleasePageMappingLock needs. */
3928 PGMPAGEMAPLOCK PageMapLock;
3929 /** Whether the PageMapLock is valid or not. */
3930 bool fLocked;
3931 /** 64 bits mode or not. */
3932 bool f64Bits;
3933} CPUMDISASSTATE, *PCPUMDISASSTATE;
3934
3935
3936/**
3937 * @callback_method_impl{FNDISREADBYTES}
3938 */
3939static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
3940{
3941 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
3942 for (;;)
3943 {
3944 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
3945
3946 /*
3947 * Need to update the page translation?
3948 */
3949 if ( !pState->pvPageR3
3950 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3951 {
3952 int rc = VINF_SUCCESS;
3953
3954 /* translate the address */
3955 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3956 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3957 && !HMIsEnabled(pState->pVM))
3958 {
3959 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3960 if (!pState->pvPageR3)
3961 rc = VERR_INVALID_POINTER;
3962 }
3963 else
3964 {
3965 /* Release mapping lock previously acquired. */
3966 if (pState->fLocked)
3967 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3968 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3969 pState->fLocked = RT_SUCCESS_NP(rc);
3970 }
3971 if (RT_FAILURE(rc))
3972 {
3973 pState->pvPageR3 = NULL;
3974 return rc;
3975 }
3976 }
3977
3978 /*
3979 * Check the segment limit.
3980 */
3981 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
3982 return VERR_OUT_OF_SELECTOR_BOUNDS;
3983
3984 /*
3985 * Calc how much we can read.
3986 */
3987 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3988 if (!pState->f64Bits)
3989 {
3990 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3991 if (cb > cbSeg && cbSeg)
3992 cb = cbSeg;
3993 }
3994 if (cb > cbMaxRead)
3995 cb = cbMaxRead;
3996
3997 /*
3998 * Read and advance or exit.
3999 */
4000 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
4001 offInstr += (uint8_t)cb;
4002 if (cb >= cbMinRead)
4003 {
4004 pDis->cbCachedInstr = offInstr;
4005 return VINF_SUCCESS;
4006 }
4007 cbMinRead -= (uint8_t)cb;
4008 cbMaxRead -= (uint8_t)cb;
4009 }
4010}
4011
4012
4013/**
4014 * Disassemble an instruction and return the information in the provided structure.
4015 *
4016 * @returns VBox status code.
4017 * @param pVM Pointer to the VM.
4018 * @param pVCpu Pointer to the VMCPU.
4019 * @param pCtx Pointer to the guest CPU context.
4020 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
4021 * @param pCpu Disassembly state.
4022 * @param pszPrefix String prefix for logging (debug only).
4023 *
4024 */
4025VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
4026{
4027 CPUMDISASSTATE State;
4028 int rc;
4029
4030 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4031 State.pCpu = pCpu;
4032 State.pvPageGC = 0;
4033 State.pvPageR3 = NULL;
4034 State.pVM = pVM;
4035 State.pVCpu = pVCpu;
4036 State.fLocked = false;
4037 State.f64Bits = false;
4038
4039 /*
4040 * Get selector information.
4041 */
4042 DISCPUMODE enmDisCpuMode;
4043 if ( (pCtx->cr0 & X86_CR0_PE)
4044 && pCtx->eflags.Bits.u1VM == 0)
4045 {
4046 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4047 {
4048 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
4049 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4050 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4051 }
4052 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4053 State.GCPtrSegBase = pCtx->cs.u64Base;
4054 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4055 State.cbSegLimit = pCtx->cs.u32Limit;
4056 enmDisCpuMode = (State.f64Bits)
4057 ? DISCPUMODE_64BIT
4058 : pCtx->cs.Attr.n.u1DefBig
4059 ? DISCPUMODE_32BIT
4060 : DISCPUMODE_16BIT;
4061 }
4062 else
4063 {
4064 /* real or V86 mode */
4065 enmDisCpuMode = DISCPUMODE_16BIT;
4066 State.GCPtrSegBase = pCtx->cs.Sel * 16;
4067 State.GCPtrSegEnd = 0xFFFFFFFF;
4068 State.cbSegLimit = 0xFFFFFFFF;
4069 }
4070
4071 /*
4072 * Disassemble the instruction.
4073 */
4074 uint32_t cbInstr;
4075#ifndef LOG_ENABLED
4076 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4077 if (RT_SUCCESS(rc))
4078 {
4079#else
4080 char szOutput[160];
4081 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4082 pCpu, &cbInstr, szOutput, sizeof(szOutput));
4083 if (RT_SUCCESS(rc))
4084 {
4085 /* log it */
4086 if (pszPrefix)
4087 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4088 else
4089 Log(("%s", szOutput));
4090#endif
4091 rc = VINF_SUCCESS;
4092 }
4093 else
4094 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4095
4096 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
4097 if (State.fLocked)
4098 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4099
4100 return rc;
4101}
4102
4103
4104
4105/**
4106 * API for controlling a few of the CPU features found in CR4.
4107 *
4108 * Currently only X86_CR4_TSD is accepted as input.
4109 *
4110 * @returns VBox status code.
4111 *
4112 * @param pVM Pointer to the VM.
4113 * @param fOr The CR4 OR mask.
4114 * @param fAnd The CR4 AND mask.
4115 */
4116VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4117{
4118 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4119 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4120
4121 pVM->cpum.s.CR4.OrMask &= fAnd;
4122 pVM->cpum.s.CR4.OrMask |= fOr;
4123
4124 return VINF_SUCCESS;
4125}
4126
4127
4128/**
4129 * Gets a pointer to the array of standard CPUID leaves.
4130 *
4131 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
4132 *
4133 * @returns Pointer to the standard CPUID leaves (read-only).
4134 * @param pVM Pointer to the VM.
4135 * @remark Intended for PATM.
4136 */
4137VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
4138{
4139 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
4140}
4141
4142
4143/**
4144 * Gets a pointer to the array of extended CPUID leaves.
4145 *
4146 * CPUMGetGuestCpuIdExtMax() give the size of the array.
4147 *
4148 * @returns Pointer to the extended CPUID leaves (read-only).
4149 * @param pVM Pointer to the VM.
4150 * @remark Intended for PATM.
4151 */
4152VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
4153{
4154 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
4155}
4156
4157
4158/**
4159 * Gets a pointer to the array of centaur CPUID leaves.
4160 *
4161 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
4162 *
4163 * @returns Pointer to the centaur CPUID leaves (read-only).
4164 * @param pVM Pointer to the VM.
4165 * @remark Intended for PATM.
4166 */
4167VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
4168{
4169 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
4170}
4171
4172
4173/**
4174 * Gets a pointer to the default CPUID leaf.
4175 *
4176 * @returns Pointer to the default CPUID leaf (read-only).
4177 * @param pVM Pointer to the VM.
4178 * @remark Intended for PATM.
4179 */
4180VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
4181{
4182 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
4183}
4184
4185
4186/**
4187 * Transforms the guest CPU state to raw-ring mode.
4188 *
4189 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
4190 *
4191 * @returns VBox status. (recompiler failure)
4192 * @param pVCpu Pointer to the VMCPU.
4193 * @param pCtxCore The context core (for trap usage).
4194 * @see @ref pg_raw
4195 */
4196VMMR3DECL(int) CPUMR3RawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
4197{
4198 PVM pVM = pVCpu->CTX_SUFF(pVM);
4199
4200 Assert(!pVCpu->cpum.s.fRawEntered);
4201 Assert(!pVCpu->cpum.s.fRemEntered);
4202 if (!pCtxCore)
4203 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
4204
4205 /*
4206 * Are we in Ring-0?
4207 */
4208 if ( pCtxCore->ss.Sel && (pCtxCore->ss.Sel & X86_SEL_RPL) == 0
4209 && !pCtxCore->eflags.Bits.u1VM)
4210 {
4211 /*
4212 * Enter execution mode.
4213 */
4214 PATMRawEnter(pVM, pCtxCore);
4215
4216 /*
4217 * Set CPL to Ring-1.
4218 */
4219 pCtxCore->ss.Sel |= 1;
4220 if (pCtxCore->cs.Sel && (pCtxCore->cs.Sel & X86_SEL_RPL) == 0)
4221 pCtxCore->cs.Sel |= 1;
4222 }
4223 else
4224 {
4225 AssertMsg((pCtxCore->ss.Sel & X86_SEL_RPL) >= 2 || pCtxCore->eflags.Bits.u1VM,
4226 ("ring-1 code not supported\n"));
4227 /*
4228 * PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
4229 */
4230 PATMRawEnter(pVM, pCtxCore);
4231 }
4232
4233 /*
4234 * Assert sanity.
4235 */
4236 AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
4237 AssertReleaseMsg( pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss.Sel & X86_SEL_RPL)
4238 || pCtxCore->eflags.Bits.u1VM,
4239 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
4240 Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP));
4241
4242 pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */
4243
4244 pVCpu->cpum.s.fRawEntered = true;
4245 return VINF_SUCCESS;
4246}
4247
4248
4249/**
4250 * Transforms the guest CPU state from raw-ring mode to correct values.
4251 *
4252 * This function will change any selector registers with DPL=1 to DPL=0.
4253 *
4254 * @returns Adjusted rc.
4255 * @param pVCpu Pointer to the VMCPU.
4256 * @param rc Raw mode return code
4257 * @param pCtxCore The context core (for trap usage).
4258 * @see @ref pg_raw
4259 */
4260VMMR3DECL(int) CPUMR3RawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
4261{
4262 PVM pVM = pVCpu->CTX_SUFF(pVM);
4263
4264 /*
4265 * Don't leave if we've already left (in GC).
4266 */
4267 Assert(pVCpu->cpum.s.fRawEntered);
4268 Assert(!pVCpu->cpum.s.fRemEntered);
4269 if (!pVCpu->cpum.s.fRawEntered)
4270 return rc;
4271 pVCpu->cpum.s.fRawEntered = false;
4272
4273 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4274 if (!pCtxCore)
4275 pCtxCore = CPUMCTX2CORE(pCtx);
4276 Assert(pCtxCore->eflags.Bits.u1VM || (pCtxCore->ss.Sel & X86_SEL_RPL));
4277 AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss.Sel & X86_SEL_RPL),
4278 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
4279
4280 /*
4281 * Are we executing in raw ring-1?
4282 */
4283 if ( (pCtxCore->ss.Sel & X86_SEL_RPL) == 1
4284 && !pCtxCore->eflags.Bits.u1VM)
4285 {
4286 /*
4287 * Leave execution mode.
4288 */
4289 PATMRawLeave(pVM, pCtxCore, rc);
4290 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
4291 /** @todo See what happens if we remove this. */
4292 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
4293 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
4294 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
4295 pCtxCore->es.Sel &= ~X86_SEL_RPL;
4296 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
4297 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
4298 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
4299 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
4300
4301 /*
4302 * Ring-1 selector => Ring-0.
4303 */
4304 pCtxCore->ss.Sel &= ~X86_SEL_RPL;
4305 if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
4306 pCtxCore->cs.Sel &= ~X86_SEL_RPL;
4307 }
4308 else
4309 {
4310 /*
4311 * PATM is taking care of the IOPL and IF flags for us.
4312 */
4313 PATMRawLeave(pVM, pCtxCore, rc);
4314 if (!pCtxCore->eflags.Bits.u1VM)
4315 {
4316 /** @todo See what happens if we remove this. */
4317 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
4318 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
4319 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
4320 pCtxCore->es.Sel &= ~X86_SEL_RPL;
4321 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
4322 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
4323 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
4324 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
4325 }
4326 }
4327
4328 return rc;
4329}
4330
4331
4332/**
4333 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
4334 *
4335 * Only REM should ever call this function!
4336 *
4337 * @returns The changed flags.
4338 * @param pVCpu Pointer to the VMCPU.
4339 * @param puCpl Where to return the current privilege level (CPL).
4340 */
4341VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
4342{
4343 Assert(!pVCpu->cpum.s.fRawEntered);
4344 Assert(!pVCpu->cpum.s.fRemEntered);
4345
4346 /*
4347 * Get the CPL first.
4348 */
4349 *puCpl = CPUMGetGuestCPL(pVCpu);
4350
4351 /*
4352 * Get and reset the flags.
4353 */
4354 uint32_t fFlags = pVCpu->cpum.s.fChanged;
4355 pVCpu->cpum.s.fChanged = 0;
4356
4357 /** @todo change the switcher to use the fChanged flags. */
4358 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
4359 {
4360 fFlags |= CPUM_CHANGED_FPU_REM;
4361 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
4362 }
4363
4364 pVCpu->cpum.s.fRemEntered = true;
4365 return fFlags;
4366}
4367
4368
4369/**
4370 * Leaves REM.
4371 *
4372 * @param pVCpu Pointer to the VMCPU.
4373 * @param fNoOutOfSyncSels This is @c false if there are out of sync
4374 * registers.
4375 */
4376VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
4377{
4378 Assert(!pVCpu->cpum.s.fRawEntered);
4379 Assert(pVCpu->cpum.s.fRemEntered);
4380
4381 pVCpu->cpum.s.fRemEntered = false;
4382}
4383
4384
4385/**
4386 * Called when the ring-3 init phase completes.
4387 *
4388 * @returns VBox status code.
4389 * @param pVM Pointer to the VM.
4390 */
4391VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM)
4392{
4393 for (VMCPUID i = 0; i < pVM->cCpus; i++)
4394 {
4395 /* Cache the APIC base (from the APIC device) once it has been initialized. */
4396 PDMApicGetBase(&pVM->aCpus[i], &pVM->aCpus[i].cpum.s.Guest.msrApicBase);
4397 Log(("CPUMR3InitCompleted pVM=%p APIC base[%u]=%RX64\n", pVM, (unsigned)i, pVM->aCpus[i].cpum.s.Guest.msrApicBase));
4398 }
4399 return VINF_SUCCESS;
4400}
4401
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