VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 43038

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1/* $Id: CPUM.cpp 42894 2012-08-21 08:00:10Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_CPUM
38#include <VBox/vmm/cpum.h>
39#include <VBox/vmm/cpumdis.h>
40#include <VBox/vmm/cpumctx-v1_6.h>
41#include <VBox/vmm/pgm.h>
42#include <VBox/vmm/mm.h>
43#include <VBox/vmm/selm.h>
44#include <VBox/vmm/dbgf.h>
45#include <VBox/vmm/patm.h>
46#include <VBox/vmm/hwaccm.h>
47#include <VBox/vmm/ssm.h>
48#include "CPUMInternal.h"
49#include <VBox/vmm/vm.h>
50
51#include <VBox/param.h>
52#include <VBox/dis.h>
53#include <VBox/err.h>
54#include <VBox/log.h>
55#include <iprt/assert.h>
56#include <iprt/asm-amd64-x86.h>
57#include <iprt/string.h>
58#include <iprt/mp.h>
59#include <iprt/cpuset.h>
60#include "internal/pgm.h"
61
62
63/*******************************************************************************
64* Defined Constants And Macros *
65*******************************************************************************/
66/** The current saved state version. */
67#define CPUM_SAVED_STATE_VERSION 14
68/** The current saved state version before using SSMR3PutStruct. */
69#define CPUM_SAVED_STATE_VERSION_MEM 13
70/** The saved state version before introducing the MSR size field. */
71#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
72/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
73 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
74#define CPUM_SAVED_STATE_VERSION_VER3_2 11
75/** The saved state version of 3.0 and 3.1 trunk before the teleportation
76 * changes. */
77#define CPUM_SAVED_STATE_VERSION_VER3_0 10
78/** The saved state version for the 2.1 trunk before the MSR changes. */
79#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
80/** The saved state version of 2.0, used for backwards compatibility. */
81#define CPUM_SAVED_STATE_VERSION_VER2_0 8
82/** The saved state version of 1.6, used for backwards compatibility. */
83#define CPUM_SAVED_STATE_VERSION_VER1_6 6
84
85
86/**
87 * This was used in the saved state up to the early life of version 14.
88 *
89 * It indicates that we may have some out-of-sync hidden segement registers.
90 * It is only relevant for raw-mode.
91 */
92#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
93
94
95/*******************************************************************************
96* Structures and Typedefs *
97*******************************************************************************/
98
99/**
100 * What kind of cpu info dump to perform.
101 */
102typedef enum CPUMDUMPTYPE
103{
104 CPUMDUMPTYPE_TERSE,
105 CPUMDUMPTYPE_DEFAULT,
106 CPUMDUMPTYPE_VERBOSE
107} CPUMDUMPTYPE;
108/** Pointer to a cpu info dump type. */
109typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
110
111
112/*******************************************************************************
113* Internal Functions *
114*******************************************************************************/
115static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
116static int cpumR3CpuIdInit(PVM pVM);
117static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
118static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
119static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
120static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
121static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
122static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
123static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
124static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
125static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
126static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
127static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
128
129
130/*******************************************************************************
131* Global Variables *
132*******************************************************************************/
133/** Saved state field descriptors for CPUMCTX. */
134static const SSMFIELD g_aCpumCtxFields[] =
135{
136 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
137 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
138 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
139 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
140 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
141 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
142 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
143 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
144 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
145 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
146 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
147 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
148 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
149 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
150 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
151 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
152 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
153 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
154 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
155 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
156 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
157 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
158 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
159 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
160 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
161 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
162 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
163 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
164 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
165 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
166 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
167 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
168 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
169 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
170 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
171 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
172 SSMFIELD_ENTRY( CPUMCTX, rdi),
173 SSMFIELD_ENTRY( CPUMCTX, rsi),
174 SSMFIELD_ENTRY( CPUMCTX, rbp),
175 SSMFIELD_ENTRY( CPUMCTX, rax),
176 SSMFIELD_ENTRY( CPUMCTX, rbx),
177 SSMFIELD_ENTRY( CPUMCTX, rdx),
178 SSMFIELD_ENTRY( CPUMCTX, rcx),
179 SSMFIELD_ENTRY( CPUMCTX, rsp),
180 SSMFIELD_ENTRY( CPUMCTX, rflags),
181 SSMFIELD_ENTRY( CPUMCTX, rip),
182 SSMFIELD_ENTRY( CPUMCTX, r8),
183 SSMFIELD_ENTRY( CPUMCTX, r9),
184 SSMFIELD_ENTRY( CPUMCTX, r10),
185 SSMFIELD_ENTRY( CPUMCTX, r11),
186 SSMFIELD_ENTRY( CPUMCTX, r12),
187 SSMFIELD_ENTRY( CPUMCTX, r13),
188 SSMFIELD_ENTRY( CPUMCTX, r14),
189 SSMFIELD_ENTRY( CPUMCTX, r15),
190 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
191 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
192 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
193 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
194 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
195 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
196 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
197 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
198 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
199 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
200 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
201 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
202 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
203 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
204 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
205 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
206 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
207 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
208 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
209 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
210 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
211 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
212 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
213 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
214 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
215 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
216 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
217 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
218 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
219 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
220 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
221 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
222 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
223 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
224 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
225 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
226 SSMFIELD_ENTRY( CPUMCTX, cr0),
227 SSMFIELD_ENTRY( CPUMCTX, cr2),
228 SSMFIELD_ENTRY( CPUMCTX, cr3),
229 SSMFIELD_ENTRY( CPUMCTX, cr4),
230 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
231 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
232 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
233 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
234 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
235 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
236 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
237 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
238 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
239 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
240 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
241 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
242 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
243 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
244 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
245 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
246 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
247 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
248 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
249 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
250 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
251 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
252 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
253 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
254 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
255 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
256 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
257 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
258 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
259 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
260 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
261 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
262 SSMFIELD_ENTRY_TERM()
263};
264
265/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
266 * registeres changed. */
267static const SSMFIELD g_aCpumCtxFieldsMem[] =
268{
269 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
270 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
271 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
272 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
273 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
274 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
275 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
276 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
277 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
278 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
279 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
280 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
281 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
282 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
283 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
284 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
285 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
286 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
287 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
288 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
289 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
290 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
291 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
292 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
293 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
294 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
295 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
296 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
297 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
298 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
299 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
300 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
301 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
302 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
303 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
304 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
305 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
306 SSMFIELD_ENTRY( CPUMCTX, rdi),
307 SSMFIELD_ENTRY( CPUMCTX, rsi),
308 SSMFIELD_ENTRY( CPUMCTX, rbp),
309 SSMFIELD_ENTRY( CPUMCTX, rax),
310 SSMFIELD_ENTRY( CPUMCTX, rbx),
311 SSMFIELD_ENTRY( CPUMCTX, rdx),
312 SSMFIELD_ENTRY( CPUMCTX, rcx),
313 SSMFIELD_ENTRY( CPUMCTX, rsp),
314 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
315 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
316 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
317 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
318 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
319 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
320 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
321 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
322 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
323 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
324 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
325 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
326 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
327 SSMFIELD_ENTRY( CPUMCTX, rflags),
328 SSMFIELD_ENTRY( CPUMCTX, rip),
329 SSMFIELD_ENTRY( CPUMCTX, r8),
330 SSMFIELD_ENTRY( CPUMCTX, r9),
331 SSMFIELD_ENTRY( CPUMCTX, r10),
332 SSMFIELD_ENTRY( CPUMCTX, r11),
333 SSMFIELD_ENTRY( CPUMCTX, r12),
334 SSMFIELD_ENTRY( CPUMCTX, r13),
335 SSMFIELD_ENTRY( CPUMCTX, r14),
336 SSMFIELD_ENTRY( CPUMCTX, r15),
337 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
338 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
339 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
340 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
341 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
342 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
343 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
344 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
345 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
346 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
347 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
348 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
349 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
350 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
351 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
352 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
353 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
354 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
355 SSMFIELD_ENTRY( CPUMCTX, cr0),
356 SSMFIELD_ENTRY( CPUMCTX, cr2),
357 SSMFIELD_ENTRY( CPUMCTX, cr3),
358 SSMFIELD_ENTRY( CPUMCTX, cr4),
359 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
360 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
361 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
362 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
363 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
364 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
365 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
366 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
367 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
368 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
369 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
370 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
371 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
372 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
373 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
374 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
375 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
376 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
377 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
378 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
379 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
380 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
381 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
382 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
383 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
384 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
385 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
386 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
387 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
388 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
389 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
390 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
391 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
392 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
393 SSMFIELD_ENTRY_TERM()
394};
395
396/** Saved state field descriptors for CPUMCTX_VER1_6. */
397static const SSMFIELD g_aCpumCtxFieldsV16[] =
398{
399 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
400 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
401 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
402 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
403 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
404 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
405 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
406 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
407 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
408 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
409 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
410 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
411 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
412 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
413 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
414 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
415 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
416 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
417 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
418 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
419 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
420 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
421 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
422 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
423 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
424 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
425 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
426 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
427 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
428 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
429 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
430 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
431 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
432 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
433 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
434 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
435 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
436 SSMFIELD_ENTRY( CPUMCTX, rdi),
437 SSMFIELD_ENTRY( CPUMCTX, rsi),
438 SSMFIELD_ENTRY( CPUMCTX, rbp),
439 SSMFIELD_ENTRY( CPUMCTX, rax),
440 SSMFIELD_ENTRY( CPUMCTX, rbx),
441 SSMFIELD_ENTRY( CPUMCTX, rdx),
442 SSMFIELD_ENTRY( CPUMCTX, rcx),
443 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
444 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
445 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
446 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
447 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
448 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
449 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
450 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
451 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
452 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
453 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
454 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
455 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
456 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
457 SSMFIELD_ENTRY( CPUMCTX, rflags),
458 SSMFIELD_ENTRY( CPUMCTX, rip),
459 SSMFIELD_ENTRY( CPUMCTX, r8),
460 SSMFIELD_ENTRY( CPUMCTX, r9),
461 SSMFIELD_ENTRY( CPUMCTX, r10),
462 SSMFIELD_ENTRY( CPUMCTX, r11),
463 SSMFIELD_ENTRY( CPUMCTX, r12),
464 SSMFIELD_ENTRY( CPUMCTX, r13),
465 SSMFIELD_ENTRY( CPUMCTX, r14),
466 SSMFIELD_ENTRY( CPUMCTX, r15),
467 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
468 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
469 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
470 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
471 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
472 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
473 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
474 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
475 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
476 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
477 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
478 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
479 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
480 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
481 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
482 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
483 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
484 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
485 SSMFIELD_ENTRY( CPUMCTX, cr0),
486 SSMFIELD_ENTRY( CPUMCTX, cr2),
487 SSMFIELD_ENTRY( CPUMCTX, cr3),
488 SSMFIELD_ENTRY( CPUMCTX, cr4),
489 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
490 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
491 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
492 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
493 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
494 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
495 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
496 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
497 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
498 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
499 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
500 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
501 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
502 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
503 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
504 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
505 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
506 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
507 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
508 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
509 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
510 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
511 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
512 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
513 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
514 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
515 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
516 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
517 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
518 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
519 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
520 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
521 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
522 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
523 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
524 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
525 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
526 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
527 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
528 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
529 SSMFIELD_ENTRY_TERM()
530};
531
532
533/**
534 * Initializes the CPUM.
535 *
536 * @returns VBox status code.
537 * @param pVM Pointer to the VM.
538 */
539VMMR3DECL(int) CPUMR3Init(PVM pVM)
540{
541 LogFlow(("CPUMR3Init\n"));
542
543 /*
544 * Assert alignment and sizes.
545 */
546 AssertCompileMemberAlignment(VM, cpum.s, 32);
547 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
548 AssertCompileSizeAlignment(CPUMCTX, 64);
549 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
550 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
551 AssertCompileMemberAlignment(VM, cpum, 64);
552 AssertCompileMemberAlignment(VM, aCpus, 64);
553 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
554 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
555
556 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
557 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
558 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
559
560 /* Calculate the offset from CPUMCPU to CPUM. */
561 for (VMCPUID i = 0; i < pVM->cCpus; i++)
562 {
563 PVMCPU pVCpu = &pVM->aCpus[i];
564
565 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
566 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
567 }
568
569 /*
570 * Check that the CPU supports the minimum features we require.
571 */
572 if (!ASMHasCpuId())
573 {
574 Log(("The CPU doesn't support CPUID!\n"));
575 return VERR_UNSUPPORTED_CPU;
576 }
577 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
578 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
579
580 /* Setup the CR4 AND and OR masks used in the switcher */
581 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
582 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
583 {
584 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
585 /* No FXSAVE implies no SSE */
586 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
587 pVM->cpum.s.CR4.OrMask = 0;
588 }
589 else
590 {
591 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
592 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
593 }
594
595 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
596 {
597 Log(("The CPU doesn't support MMX!\n"));
598 return VERR_UNSUPPORTED_CPU;
599 }
600 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
601 {
602 Log(("The CPU doesn't support TSC!\n"));
603 return VERR_UNSUPPORTED_CPU;
604 }
605 /* Bogus on AMD? */
606 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
607 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
608
609 /*
610 * Detect the host CPU vendor.
611 * (The guest CPU vendor is re-detected later on.)
612 */
613 uint32_t uEAX, uEBX, uECX, uEDX;
614 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
615 pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
616 pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
617
618 /*
619 * Setup hypervisor startup values.
620 */
621
622 /*
623 * Register saved state data item.
624 */
625 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
626 NULL, cpumR3LiveExec, NULL,
627 NULL, cpumR3SaveExec, NULL,
628 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
629 if (RT_FAILURE(rc))
630 return rc;
631
632 /*
633 * Register info handlers and registers with the debugger facility.
634 */
635 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
636 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
637 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
638 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
639 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
640 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
641
642 rc = cpumR3DbgInit(pVM);
643 if (RT_FAILURE(rc))
644 return rc;
645
646 /*
647 * Initialize the Guest CPUID state.
648 */
649 rc = cpumR3CpuIdInit(pVM);
650 if (RT_FAILURE(rc))
651 return rc;
652 CPUMR3Reset(pVM);
653 return VINF_SUCCESS;
654}
655
656
657/**
658 * Detect the CPU vendor give n the
659 *
660 * @returns The vendor.
661 * @param uEAX EAX from CPUID(0).
662 * @param uEBX EBX from CPUID(0).
663 * @param uECX ECX from CPUID(0).
664 * @param uEDX EDX from CPUID(0).
665 */
666static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
667{
668 if ( uEAX >= 1
669 && uEBX == X86_CPUID_VENDOR_AMD_EBX
670 && uECX == X86_CPUID_VENDOR_AMD_ECX
671 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
672 return CPUMCPUVENDOR_AMD;
673
674 if ( uEAX >= 1
675 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
676 && uECX == X86_CPUID_VENDOR_INTEL_ECX
677 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
678 return CPUMCPUVENDOR_INTEL;
679
680 if ( uEAX >= 1
681 && uEBX == X86_CPUID_VENDOR_VIA_EBX
682 && uECX == X86_CPUID_VENDOR_VIA_ECX
683 && uEDX == X86_CPUID_VENDOR_VIA_EDX)
684 return CPUMCPUVENDOR_VIA;
685
686 /** @todo detect the other buggers... */
687 return CPUMCPUVENDOR_UNKNOWN;
688}
689
690
691/**
692 * Fetches overrides for a CPUID leaf.
693 *
694 * @returns VBox status code.
695 * @param pLeaf The leaf to load the overrides into.
696 * @param pCfgNode The CFGM node containing the overrides
697 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
698 * @param iLeaf The CPUID leaf number.
699 */
700static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
701{
702 PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
703 if (pLeafNode)
704 {
705 uint32_t u32;
706 int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
707 if (RT_SUCCESS(rc))
708 pLeaf->eax = u32;
709 else
710 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
711
712 rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
713 if (RT_SUCCESS(rc))
714 pLeaf->ebx = u32;
715 else
716 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
717
718 rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
719 if (RT_SUCCESS(rc))
720 pLeaf->ecx = u32;
721 else
722 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
723
724 rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
725 if (RT_SUCCESS(rc))
726 pLeaf->edx = u32;
727 else
728 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
729
730 }
731 return VINF_SUCCESS;
732}
733
734
735/**
736 * Load the overrides for a set of CPUID leaves.
737 *
738 * @returns VBox status code.
739 * @param paLeaves The leaf array.
740 * @param cLeaves The number of leaves.
741 * @param uStart The start leaf number.
742 * @param pCfgNode The CFGM node containing the overrides
743 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
744 */
745static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
746{
747 for (uint32_t i = 0; i < cLeaves; i++)
748 {
749 int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
750 if (RT_FAILURE(rc))
751 return rc;
752 }
753
754 return VINF_SUCCESS;
755}
756
757/**
758 * Init a set of host CPUID leaves.
759 *
760 * @returns VBox status code.
761 * @param paLeaves The leaf array.
762 * @param cLeaves The number of leaves.
763 * @param uStart The start leaf number.
764 * @param pCfgNode The /CPUM/HostCPUID/ node.
765 */
766static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
767{
768 /* Using the ECX variant for all of them can't hurt... */
769 for (uint32_t i = 0; i < cLeaves; i++)
770 ASMCpuId_Idx_ECX(uStart + i, 0, &paLeaves[i].eax, &paLeaves[i].ebx, &paLeaves[i].ecx, &paLeaves[i].edx);
771
772 /* Load CPUID leaf override; we currently don't care if the user
773 specifies features the host CPU doesn't support. */
774 return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
775}
776
777
778/**
779 * Initializes the emulated CPU's cpuid information.
780 *
781 * @returns VBox status code.
782 * @param pVM Pointer to the VM.
783 */
784static int cpumR3CpuIdInit(PVM pVM)
785{
786 PCPUM pCPUM = &pVM->cpum.s;
787 PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
788 uint32_t i;
789 int rc;
790
791#define PORTABLE_CLEAR_BITS_WHEN(Lvl, LeafSuffReg, FeatNm, fMask, uValue) \
792 if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fMask)) == (uValue) ) \
793 { \
794 LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: %#x -> 0\n", pCPUM->aGuestCpuId##LeafSuffReg & (fMask))); \
795 pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fMask); \
796 }
797#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, LeafSuffReg, FeatNm, fBitMask) \
798 if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fBitMask)) ) \
799 { \
800 LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: 1 -> 0\n")); \
801 pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fBitMask); \
802 }
803
804 /*
805 * Read the configuration.
806 */
807 /** @cfgm{CPUM/SyntheticCpu, boolean, false}
808 * Enables the Synthetic CPU. The Vendor ID and Processor Name are
809 * completely overridden by VirtualBox custom strings. Some
810 * CPUID information is withheld, like the cache info. */
811 rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false);
812 AssertRCReturn(rc, rc);
813
814 /** @cfgm{CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
815 * When non-zero CPUID features that could cause portability issues will be
816 * stripped. The higher the value the more features gets stripped. Higher
817 * values should only be used when older CPUs are involved since it may
818 * harm performance and maybe also cause problems with specific guests. */
819 rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, 0);
820 AssertRCReturn(rc, rc);
821
822 AssertLogRelReturn(!pCPUM->fSyntheticCpu || !pCPUM->u8PortableCpuIdLevel, VERR_CPUM_INCOMPATIBLE_CONFIG);
823
824 /*
825 * Get the host CPUID leaves and redetect the guest CPU vendor (could've
826 * been overridden).
827 */
828 /** @cfgm{CPUM/HostCPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
829 * Overrides the host CPUID leaf values used for calculating the guest CPUID
830 * leaves. This can be used to preserve the CPUID values when moving a VM to a
831 * different machine. Another use is restricting (or extending) the feature set
832 * exposed to the guest. */
833 PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
834 rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
835 AssertRCReturn(rc, rc);
836 rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
837 AssertRCReturn(rc, rc);
838 rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
839 AssertRCReturn(rc, rc);
840
841 pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
842 pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
843
844 /*
845 * Determine the default leaf.
846 *
847 * Intel returns values of the highest standard function, while AMD
848 * returns zeros. VIA on the other hand seems to returning nothing or
849 * perhaps some random garbage, we don't try to duplicate this behavior.
850 */
851 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10, /** @todo r=bird: Use the host value here in case of overrides and more than 10 leaves being stripped already. */
852 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
853 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
854
855 /** @cfgm{/CPUM/CMPXCHG16B, boolean, false}
856 * Expose CMPXCHG16B to the guest if supported by the host.
857 */
858 bool fCmpXchg16b;
859 rc = CFGMR3QueryBoolDef(pCpumCfg, "CMPXCHG16B", &fCmpXchg16b, false); AssertRCReturn(rc, rc);
860
861 /* Cpuid 1 & 0x80000001:
862 * Only report features we can support.
863 *
864 * Note! When enabling new features the Synthetic CPU and Portable CPUID
865 * options may require adjusting (i.e. stripping what was enabled).
866 */
867 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
868 | X86_CPUID_FEATURE_EDX_VME
869 | X86_CPUID_FEATURE_EDX_DE
870 | X86_CPUID_FEATURE_EDX_PSE
871 | X86_CPUID_FEATURE_EDX_TSC
872 | X86_CPUID_FEATURE_EDX_MSR
873 //| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
874 | X86_CPUID_FEATURE_EDX_MCE
875 | X86_CPUID_FEATURE_EDX_CX8
876 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
877 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
878 //| X86_CPUID_FEATURE_EDX_SEP
879 | X86_CPUID_FEATURE_EDX_MTRR
880 | X86_CPUID_FEATURE_EDX_PGE
881 | X86_CPUID_FEATURE_EDX_MCA
882 | X86_CPUID_FEATURE_EDX_CMOV
883 | X86_CPUID_FEATURE_EDX_PAT
884 | X86_CPUID_FEATURE_EDX_PSE36
885 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
886 | X86_CPUID_FEATURE_EDX_CLFSH
887 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
888 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
889 | X86_CPUID_FEATURE_EDX_MMX
890 | X86_CPUID_FEATURE_EDX_FXSR
891 | X86_CPUID_FEATURE_EDX_SSE
892 | X86_CPUID_FEATURE_EDX_SSE2
893 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
894 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
895 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
896 //| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
897 | 0;
898 pCPUM->aGuestCpuIdStd[1].ecx &= 0
899 | X86_CPUID_FEATURE_ECX_SSE3
900 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
901 | ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
902 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
903 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
904 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
905 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
906 | X86_CPUID_FEATURE_ECX_SSSE3
907 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
908 | (fCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
909 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
910 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
911 /* ECX Bit 21 - x2APIC support - not yet. */
912 // | X86_CPUID_FEATURE_ECX_X2APIC
913 /* ECX Bit 23 - POPCNT instruction. */
914 //| X86_CPUID_FEATURE_ECX_POPCNT
915 | 0;
916 if (pCPUM->u8PortableCpuIdLevel > 0)
917 {
918 PORTABLE_CLEAR_BITS_WHEN(1, Std[1].eax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
919 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
920 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
921 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, CX16, X86_CPUID_FEATURE_ECX_CX16);
922 PORTABLE_DISABLE_FEATURE_BIT(2, Std[1].edx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
923 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, SSE, X86_CPUID_FEATURE_EDX_SSE);
924 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
925 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
926
927 Assert(!(pCPUM->aGuestCpuIdStd[1].edx & ( X86_CPUID_FEATURE_EDX_SEP
928 | X86_CPUID_FEATURE_EDX_PSN
929 | X86_CPUID_FEATURE_EDX_DS
930 | X86_CPUID_FEATURE_EDX_ACPI
931 | X86_CPUID_FEATURE_EDX_SS
932 | X86_CPUID_FEATURE_EDX_TM
933 | X86_CPUID_FEATURE_EDX_PBE
934 )));
935 Assert(!(pCPUM->aGuestCpuIdStd[1].ecx & ( X86_CPUID_FEATURE_ECX_PCLMUL
936 | X86_CPUID_FEATURE_ECX_DTES64
937 | X86_CPUID_FEATURE_ECX_CPLDS
938 | X86_CPUID_FEATURE_ECX_VMX
939 | X86_CPUID_FEATURE_ECX_SMX
940 | X86_CPUID_FEATURE_ECX_EST
941 | X86_CPUID_FEATURE_ECX_TM2
942 | X86_CPUID_FEATURE_ECX_CNTXID
943 | X86_CPUID_FEATURE_ECX_FMA
944 | X86_CPUID_FEATURE_ECX_CX16
945 | X86_CPUID_FEATURE_ECX_TPRUPDATE
946 | X86_CPUID_FEATURE_ECX_PDCM
947 | X86_CPUID_FEATURE_ECX_DCA
948 | X86_CPUID_FEATURE_ECX_MOVBE
949 | X86_CPUID_FEATURE_ECX_AES
950 | X86_CPUID_FEATURE_ECX_POPCNT
951 | X86_CPUID_FEATURE_ECX_XSAVE
952 | X86_CPUID_FEATURE_ECX_OSXSAVE
953 | X86_CPUID_FEATURE_ECX_AVX
954 )));
955 }
956
957 /* Cpuid 0x80000001:
958 * Only report features we can support.
959 *
960 * Note! When enabling new features the Synthetic CPU and Portable CPUID
961 * options may require adjusting (i.e. stripping what was enabled).
962 *
963 * ASSUMES that this is ALWAYS the AMD defined feature set if present.
964 */
965 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
966 | X86_CPUID_AMD_FEATURE_EDX_VME
967 | X86_CPUID_AMD_FEATURE_EDX_DE
968 | X86_CPUID_AMD_FEATURE_EDX_PSE
969 | X86_CPUID_AMD_FEATURE_EDX_TSC
970 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
971 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
972 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
973 | X86_CPUID_AMD_FEATURE_EDX_CX8
974 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
975 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
976 //| X86_CPUID_EXT_FEATURE_EDX_SEP
977 | X86_CPUID_AMD_FEATURE_EDX_MTRR
978 | X86_CPUID_AMD_FEATURE_EDX_PGE
979 | X86_CPUID_AMD_FEATURE_EDX_MCA
980 | X86_CPUID_AMD_FEATURE_EDX_CMOV
981 | X86_CPUID_AMD_FEATURE_EDX_PAT
982 | X86_CPUID_AMD_FEATURE_EDX_PSE36
983 //| X86_CPUID_EXT_FEATURE_EDX_NX - not virtualized, requires PAE.
984 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
985 | X86_CPUID_AMD_FEATURE_EDX_MMX
986 | X86_CPUID_AMD_FEATURE_EDX_FXSR
987 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
988 //| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
989 | X86_CPUID_EXT_FEATURE_EDX_RDTSCP
990 //| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
991 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
992 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
993 | 0;
994 pCPUM->aGuestCpuIdExt[1].ecx &= 0
995 //| X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
996 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
997 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
998 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
999 /* Note: This could prevent teleporting from AMD to Intel CPUs! */
1000 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
1001 //| X86_CPUID_AMD_FEATURE_ECX_ABM
1002 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
1003 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1004 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1005 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
1006 //| X86_CPUID_AMD_FEATURE_ECX_IBS
1007 //| X86_CPUID_AMD_FEATURE_ECX_SSE5
1008 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1009 //| X86_CPUID_AMD_FEATURE_ECX_WDT
1010 | 0;
1011 if (pCPUM->u8PortableCpuIdLevel > 0)
1012 {
1013 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].ecx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1014 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1015 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1016 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1017 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1018 PORTABLE_DISABLE_FEATURE_BIT(2, Ext[1].ecx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1019 PORTABLE_DISABLE_FEATURE_BIT(3, Ext[1].ecx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1020
1021 Assert(!(pCPUM->aGuestCpuIdExt[1].ecx & ( X86_CPUID_AMD_FEATURE_ECX_CMPL
1022 | X86_CPUID_AMD_FEATURE_ECX_SVM
1023 | X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1024 | X86_CPUID_AMD_FEATURE_ECX_CR8L
1025 | X86_CPUID_AMD_FEATURE_ECX_ABM
1026 | X86_CPUID_AMD_FEATURE_ECX_SSE4A
1027 | X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1028 | X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1029 | X86_CPUID_AMD_FEATURE_ECX_OSVW
1030 | X86_CPUID_AMD_FEATURE_ECX_IBS
1031 | X86_CPUID_AMD_FEATURE_ECX_SSE5
1032 | X86_CPUID_AMD_FEATURE_ECX_SKINIT
1033 | X86_CPUID_AMD_FEATURE_ECX_WDT
1034 | UINT32_C(0xffffc000)
1035 )));
1036 Assert(!(pCPUM->aGuestCpuIdExt[1].edx & ( RT_BIT(10)
1037 | X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1038 | RT_BIT(18)
1039 | RT_BIT(19)
1040 | RT_BIT(21)
1041 | X86_CPUID_AMD_FEATURE_EDX_AXMMX
1042 | X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1043 | RT_BIT(28)
1044 )));
1045 }
1046
1047 /*
1048 * Apply the Synthetic CPU modifications. (TODO: move this up)
1049 */
1050 if (pCPUM->fSyntheticCpu)
1051 {
1052 static const char s_szVendor[13] = "VirtualBox ";
1053 static const char s_szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
1054
1055 pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
1056
1057 /* Limit the nr of standard leaves; 5 for monitor/mwait */
1058 pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
1059
1060 /* 0: Vendor */
1061 pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)s_szVendor)[0];
1062 pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)s_szVendor)[2];
1063 pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)s_szVendor)[1];
1064
1065 /* 1.eax: Version information. family : model : stepping */
1066 pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
1067
1068 /* Leaves 2 - 4 are Intel only - zero them out */
1069 memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
1070 memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
1071 memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
1072
1073 /* Leaf 5 = monitor/mwait */
1074
1075 /* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
1076 pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
1077 /* AMD only - set to zero. */
1078 pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
1079
1080 /* 0x800000001: shared feature bits are set dynamically. */
1081 memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
1082
1083 /* 0x800000002-4: Processor Name String Identifier. */
1084 pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)s_szProcessor)[0];
1085 pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)s_szProcessor)[1];
1086 pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)s_szProcessor)[2];
1087 pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)s_szProcessor)[3];
1088 pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)s_szProcessor)[4];
1089 pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)s_szProcessor)[5];
1090 pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)s_szProcessor)[6];
1091 pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)s_szProcessor)[7];
1092 pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)s_szProcessor)[8];
1093 pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)s_szProcessor)[9];
1094 pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)s_szProcessor)[10];
1095 pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)s_szProcessor)[11];
1096
1097 /* 0x800000005-7 - reserved -> zero */
1098 memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
1099 memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
1100 memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
1101
1102 /* 0x800000008: only the max virtual and physical address size. */
1103 pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
1104 }
1105
1106 /*
1107 * Hide HTT, multicode, SMP, whatever.
1108 * (APIC-ID := 0 and #LogCpus := 0)
1109 */
1110 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
1111#ifdef VBOX_WITH_MULTI_CORE
1112 if ( pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
1113 && pVM->cCpus > 1)
1114 {
1115 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
1116 pCPUM->aGuestCpuIdStd[1].ebx |= (pVM->cCpus << 16);
1117 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
1118 }
1119#endif
1120
1121 /* Cpuid 2:
1122 * Intel: Cache and TLB information
1123 * AMD: Reserved
1124 * VIA: Reserved
1125 * Safe to expose; restrict the number of calls to 1 for the portable case.
1126 */
1127 if ( pCPUM->u8PortableCpuIdLevel > 0
1128 && pCPUM->aGuestCpuIdStd[0].eax >= 2
1129 && (pCPUM->aGuestCpuIdStd[2].eax & 0xff) > 1)
1130 {
1131 LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCPUM->aGuestCpuIdStd[2].eax & 0xff));
1132 pCPUM->aGuestCpuIdStd[2].eax &= UINT32_C(0xfffffffe);
1133 }
1134
1135 /* Cpuid 3:
1136 * Intel: EAX, EBX - reserved (transmeta uses these)
1137 * ECX, EDX - Processor Serial Number if available, otherwise reserved
1138 * AMD: Reserved
1139 * VIA: Reserved
1140 * Safe to expose
1141 */
1142 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
1143 {
1144 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
1145 if (pCPUM->u8PortableCpuIdLevel > 0)
1146 pCPUM->aGuestCpuIdStd[3].eax = pCPUM->aGuestCpuIdStd[3].ebx = 0;
1147 }
1148
1149 /* Cpuid 4:
1150 * Intel: Deterministic Cache Parameters Leaf
1151 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
1152 * AMD: Reserved
1153 * VIA: Reserved
1154 * Safe to expose, except for EAX:
1155 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
1156 * Bits 31-26: Maximum number of processor cores in this physical package**
1157 * Note: These SMP values are constant regardless of ECX
1158 */
1159 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
1160 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
1161#ifdef VBOX_WITH_MULTI_CORE
1162 if ( pVM->cCpus > 1
1163 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1164 {
1165 AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
1166 /* One logical processor with possibly multiple cores. */
1167 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
1168 pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
1169 }
1170#endif
1171
1172 /* Cpuid 5: Monitor/mwait Leaf
1173 * Intel: ECX, EDX - reserved
1174 * EAX, EBX - Smallest and largest monitor line size
1175 * AMD: EDX - reserved
1176 * EAX, EBX - Smallest and largest monitor line size
1177 * ECX - extensions (ignored for now)
1178 * VIA: Reserved
1179 * Safe to expose
1180 */
1181 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
1182 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
1183
1184 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
1185 /** @cfgm{/CPUM/MWaitExtensions, boolean, false}
1186 * Expose MWAIT extended features to the guest. For now we expose
1187 * just MWAIT break on interrupt feature (bit 1).
1188 */
1189 bool fMWaitExtensions;
1190 rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
1191 if (fMWaitExtensions)
1192 {
1193 pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
1194 /* @todo: for now we just expose host's MWAIT C-states, although conceptually
1195 it shall be part of our power management virtualization model */
1196#if 0
1197 /* MWAIT sub C-states */
1198 pCPUM->aGuestCpuIdStd[5].edx =
1199 (0 << 0) /* 0 in C0 */ |
1200 (2 << 4) /* 2 in C1 */ |
1201 (2 << 8) /* 2 in C2 */ |
1202 (2 << 12) /* 2 in C3 */ |
1203 (0 << 16) /* 0 in C4 */
1204 ;
1205#endif
1206 }
1207 else
1208 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
1209
1210 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
1211 * Safe to pass on to the guest.
1212 *
1213 * Intel: 0x800000005 reserved
1214 * 0x800000006 L2 cache information
1215 * AMD: 0x800000005 L1 cache information
1216 * 0x800000006 L2/L3 cache information
1217 * VIA: 0x800000005 TLB and L1 cache information
1218 * 0x800000006 L2 cache information
1219 */
1220
1221 /* Cpuid 0x800000007:
1222 * Intel: Reserved
1223 * AMD: EAX, EBX, ECX - reserved
1224 * EDX: Advanced Power Management Information
1225 * VIA: Reserved
1226 */
1227 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
1228 {
1229 Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
1230
1231 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
1232
1233 if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1234 {
1235 /* Only expose the TSC invariant capability bit to the guest. */
1236 pCPUM->aGuestCpuIdExt[7].edx &= 0
1237 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
1238 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
1239 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
1240 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
1241 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
1242 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
1243 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
1244 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
1245#if 0
1246 /*
1247 * We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
1248 * Linux kernels blindly assume that the AMD performance counters work
1249 * if this is set for 64 bits guests. (Can't really find a CPUID feature
1250 * bit for them though.)
1251 */
1252 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
1253#endif
1254 | 0;
1255 }
1256 else
1257 pCPUM->aGuestCpuIdExt[7].edx = 0;
1258 }
1259
1260 /* Cpuid 0x800000008:
1261 * Intel: EAX: Virtual/Physical address Size
1262 * EBX, ECX, EDX - reserved
1263 * AMD: EBX, EDX - reserved
1264 * EAX: Virtual/Physical/Guest address Size
1265 * ECX: Number of cores + APICIdCoreIdSize
1266 * VIA: EAX: Virtual/Physical address Size
1267 * EBX, ECX, EDX - reserved
1268 */
1269 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
1270 {
1271 /* Only expose the virtual and physical address sizes to the guest. */
1272 pCPUM->aGuestCpuIdExt[8].eax &= UINT32_C(0x0000ffff);
1273 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
1274 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
1275 * NC (0-7) Number of cores; 0 equals 1 core */
1276 pCPUM->aGuestCpuIdExt[8].ecx = 0;
1277#ifdef VBOX_WITH_MULTI_CORE
1278 if ( pVM->cCpus > 1
1279 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1280 {
1281 /* Legacy method to determine the number of cores. */
1282 pCPUM->aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
1283 pCPUM->aGuestCpuIdExt[8].ecx |= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
1284 }
1285#endif
1286 }
1287
1288 /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
1289 * Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
1290 * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
1291 * This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
1292 */
1293 bool fNt4LeafLimit;
1294 rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
1295 if (fNt4LeafLimit)
1296 pCPUM->aGuestCpuIdStd[0].eax = 3; /** @todo r=bird: shouldn't we check if pCPUM->aGuestCpuIdStd[0].eax > 3 before setting it 3 here? */
1297
1298 /*
1299 * Limit it the number of entries and fill the remaining with the defaults.
1300 *
1301 * The limits are masking off stuff about power saving and similar, this
1302 * is perhaps a bit crudely done as there is probably some relatively harmless
1303 * info too in these leaves (like words about having a constant TSC).
1304 */
1305 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
1306 pCPUM->aGuestCpuIdStd[0].eax = 5;
1307 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
1308 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
1309
1310 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
1311 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
1312 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
1313 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
1314 : 0;
1315 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
1316 i++)
1317 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
1318
1319 /*
1320 * Centaur stuff (VIA).
1321 *
1322 * The important part here (we think) is to make sure the 0xc0000000
1323 * function returns 0xc0000001. As for the features, we don't currently
1324 * let on about any of those... 0xc0000002 seems to be some
1325 * temperature/hz/++ stuff, include it as well (static).
1326 */
1327 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
1328 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
1329 {
1330 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
1331 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
1332 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
1333 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
1334 i++)
1335 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
1336 }
1337 else
1338 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
1339 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
1340
1341 /*
1342 * Hypervisor identification.
1343 *
1344 * We only return minimal information, primarily ensuring that the
1345 * 0x40000000 function returns 0x40000001 and identifying ourselves.
1346 * Currently we do not support any hypervisor-specific interface.
1347 */
1348 pCPUM->aGuestCpuIdHyper[0].eax = UINT32_C(0x40000001);
1349 pCPUM->aGuestCpuIdHyper[0].ebx = pCPUM->aGuestCpuIdHyper[0].ecx
1350 = pCPUM->aGuestCpuIdHyper[0].edx = 0x786f4256; /* 'VBox' */
1351 pCPUM->aGuestCpuIdHyper[1].eax = 0x656e6f6e; /* 'none' */
1352 pCPUM->aGuestCpuIdHyper[1].ebx = pCPUM->aGuestCpuIdHyper[1].ecx
1353 = pCPUM->aGuestCpuIdHyper[1].edx = 0; /* Reserved */
1354
1355 /*
1356 * Load CPUID overrides from configuration.
1357 * Note: Kind of redundant now, but allows unchanged overrides
1358 */
1359 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
1360 * Overrides the CPUID leaf values. */
1361 PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
1362 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
1363 AssertRCReturn(rc, rc);
1364 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
1365 AssertRCReturn(rc, rc);
1366 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
1367 AssertRCReturn(rc, rc);
1368
1369 /*
1370 * Check if PAE was explicitely enabled by the user.
1371 */
1372 bool fEnable;
1373 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
1374 if (fEnable)
1375 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1376
1377 /*
1378 * We don't normally enable NX for raw-mode, so give the user a chance to
1379 * force it on.
1380 */
1381 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false); AssertRCReturn(rc, rc);
1382 if (fEnable)
1383 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1384
1385 /*
1386 * We don't enable the Hypervisor Present bit by default, but it may
1387 * be needed by some guests.
1388 */
1389 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false); AssertRCReturn(rc, rc);
1390 if (fEnable)
1391 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
1392 /*
1393 * Log the cpuid and we're good.
1394 */
1395 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
1396 RTCPUSET OnlineSet;
1397 LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
1398 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
1399 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
1400 LogRel(("************************* CPUID dump ************************\n"));
1401 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
1402 LogRel(("\n"));
1403 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
1404 RTLogRelSetBuffering(fOldBuffered);
1405 LogRel(("******************** End of CPUID dump **********************\n"));
1406
1407#undef PORTABLE_DISABLE_FEATURE_BIT
1408#undef PORTABLE_CLEAR_BITS_WHEN
1409
1410 return VINF_SUCCESS;
1411}
1412
1413
1414/**
1415 * Applies relocations to data and code managed by this
1416 * component. This function will be called at init and
1417 * whenever the VMM need to relocate it self inside the GC.
1418 *
1419 * The CPUM will update the addresses used by the switcher.
1420 *
1421 * @param pVM The VM.
1422 */
1423VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
1424{
1425 LogFlow(("CPUMR3Relocate\n"));
1426 /* nothing to do any more. */
1427}
1428
1429
1430/**
1431 * Apply late CPUM property changes based on the fHWVirtEx setting
1432 *
1433 * @param pVM Pointer to the VM.
1434 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
1435 */
1436VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
1437{
1438 /*
1439 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
1440 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1441 * of processors from (cpuid(4).eax >> 26) + 1.
1442 *
1443 * Note: this code is obsolete, but let's keep it here for reference.
1444 * Purpose is valid when we artificially cap the max std id to less than 4.
1445 */
1446 if (!fHWVirtExEnabled)
1447 {
1448 Assert( pVM->cpum.s.aGuestCpuIdStd[4].eax == 0
1449 || pVM->cpum.s.aGuestCpuIdStd[0].eax < 0x4);
1450 pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
1451 }
1452}
1453
1454/**
1455 * Terminates the CPUM.
1456 *
1457 * Termination means cleaning up and freeing all resources,
1458 * the VM it self is at this point powered off or suspended.
1459 *
1460 * @returns VBox status code.
1461 * @param pVM Pointer to the VM.
1462 */
1463VMMR3DECL(int) CPUMR3Term(PVM pVM)
1464{
1465#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1466 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1467 {
1468 PVMCPU pVCpu = &pVM->aCpus[i];
1469 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1470
1471 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1472 pVCpu->cpum.s.uMagic = 0;
1473 pCtx->dr[5] = 0;
1474 }
1475#else
1476 NOREF(pVM);
1477#endif
1478 return VINF_SUCCESS;
1479}
1480
1481
1482/**
1483 * Resets a virtual CPU.
1484 *
1485 * Used by CPUMR3Reset and CPU hot plugging.
1486 *
1487 * @param pVCpu Pointer to the VMCPU.
1488 */
1489VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
1490{
1491 /** @todo anything different for VCPU > 0? */
1492 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1493
1494 /*
1495 * Initialize everything to ZERO first.
1496 */
1497 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1498 memset(pCtx, 0, sizeof(*pCtx));
1499 pVCpu->cpum.s.fUseFlags = fUseFlags;
1500
1501 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
1502 pCtx->eip = 0x0000fff0;
1503 pCtx->edx = 0x00000600; /* P6 processor */
1504 pCtx->eflags.Bits.u1Reserved0 = 1;
1505
1506 pCtx->cs.Sel = 0xf000;
1507 pCtx->cs.ValidSel = 0xf000;
1508 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1509 pCtx->cs.u64Base = UINT64_C(0xffff0000);
1510 pCtx->cs.u32Limit = 0x0000ffff;
1511 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1512 pCtx->cs.Attr.n.u1Present = 1;
1513 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1514
1515 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1516 pCtx->ds.u32Limit = 0x0000ffff;
1517 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1518 pCtx->ds.Attr.n.u1Present = 1;
1519 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1520
1521 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1522 pCtx->es.u32Limit = 0x0000ffff;
1523 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1524 pCtx->es.Attr.n.u1Present = 1;
1525 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1526
1527 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1528 pCtx->fs.u32Limit = 0x0000ffff;
1529 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1530 pCtx->fs.Attr.n.u1Present = 1;
1531 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1532
1533 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1534 pCtx->gs.u32Limit = 0x0000ffff;
1535 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1536 pCtx->gs.Attr.n.u1Present = 1;
1537 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1538
1539 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1540 pCtx->ss.u32Limit = 0x0000ffff;
1541 pCtx->ss.Attr.n.u1Present = 1;
1542 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1543 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1544
1545 pCtx->idtr.cbIdt = 0xffff;
1546 pCtx->gdtr.cbGdt = 0xffff;
1547
1548 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1549 pCtx->ldtr.u32Limit = 0xffff;
1550 pCtx->ldtr.Attr.n.u1Present = 1;
1551 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1552
1553 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1554 pCtx->tr.u32Limit = 0xffff;
1555 pCtx->tr.Attr.n.u1Present = 1;
1556 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1557
1558 pCtx->dr[6] = X86_DR6_INIT_VAL;
1559 pCtx->dr[7] = X86_DR7_INIT_VAL;
1560
1561 pCtx->fpu.FTW = 0x00; /* All empty (abbridged tag reg edition). */
1562 pCtx->fpu.FCW = 0x37f;
1563
1564 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1565 IA-32 Processor States Following Power-up, Reset, or INIT */
1566 pCtx->fpu.MXCSR = 0x1F80;
1567 pCtx->fpu.MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
1568 supports all bits, since a zero value here should be read as 0xffbf. */
1569
1570 /* Init PAT MSR */
1571 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1572
1573 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
1574 * The Intel docs don't mention it.
1575 */
1576 pCtx->msrEFER = 0;
1577}
1578
1579
1580/**
1581 * Resets the CPU.
1582 *
1583 * @returns VINF_SUCCESS.
1584 * @param pVM Pointer to the VM.
1585 */
1586VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1587{
1588 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1589 {
1590 CPUMR3ResetCpu(&pVM->aCpus[i]);
1591
1592#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1593 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
1594
1595 /* Magic marker for searching in crash dumps. */
1596 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1597 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1598 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1599#endif
1600 }
1601}
1602
1603
1604/**
1605 * Called both in pass 0 and the final pass.
1606 *
1607 * @param pVM Pointer to the VM.
1608 * @param pSSM The saved state handle.
1609 */
1610static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1611{
1612 /*
1613 * Save all the CPU ID leaves here so we can check them for compatibility
1614 * upon loading.
1615 */
1616 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1617 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1618
1619 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1620 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1621
1622 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1623 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1624
1625 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1626
1627 /*
1628 * Save a good portion of the raw CPU IDs as well as they may come in
1629 * handy when validating features for raw mode.
1630 */
1631 CPUMCPUID aRawStd[16];
1632 for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1633 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1634 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1635 SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1636
1637 CPUMCPUID aRawExt[32];
1638 for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1639 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1640 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1641 SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1642}
1643
1644
1645/**
1646 * Loads the CPU ID leaves saved by pass 0.
1647 *
1648 * @returns VBox status code.
1649 * @param pVM Pointer to the VM.
1650 * @param pSSM The saved state handle.
1651 * @param uVersion The format version.
1652 */
1653static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1654{
1655 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1656
1657 /*
1658 * Define a bunch of macros for simplifying the code.
1659 */
1660 /* Generic expression + failure message. */
1661#define CPUID_CHECK_RET(expr, fmt) \
1662 do { \
1663 if (!(expr)) \
1664 { \
1665 char *pszMsg = RTStrAPrintf2 fmt; /* lack of variadic macros sucks */ \
1666 if (fStrictCpuIdChecks) \
1667 { \
1668 int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1669 RTStrFree(pszMsg); \
1670 return rcCpuid; \
1671 } \
1672 LogRel(("CPUM: %s\n", pszMsg)); \
1673 RTStrFree(pszMsg); \
1674 } \
1675 } while (0)
1676#define CPUID_CHECK_WRN(expr, fmt) \
1677 do { \
1678 if (!(expr)) \
1679 LogRel(fmt); \
1680 } while (0)
1681
1682 /* For comparing two values and bitch if they differs. */
1683#define CPUID_CHECK2_RET(what, host, saved) \
1684 do { \
1685 if ((host) != (saved)) \
1686 { \
1687 if (fStrictCpuIdChecks) \
1688 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1689 N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1690 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1691 } \
1692 } while (0)
1693#define CPUID_CHECK2_WRN(what, host, saved) \
1694 do { \
1695 if ((host) != (saved)) \
1696 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1697 } while (0)
1698
1699 /* For checking raw cpu features (raw mode). */
1700#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1701 do { \
1702 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1703 { \
1704 if (fStrictCpuIdChecks) \
1705 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1706 N_(#bit " mismatch: host=%d saved=%d"), \
1707 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1708 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1709 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1710 } \
1711 } while (0)
1712#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1713 do { \
1714 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1715 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1716 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1717 } while (0)
1718#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1719
1720 /* For checking guest features. */
1721#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1722 do { \
1723 if ( (aGuestCpuId##set [1].reg & bit) \
1724 && !(aHostRaw##set [1].reg & bit) \
1725 && !(aHostOverride##set [1].reg & bit) \
1726 && !(aGuestOverride##set [1].reg & bit) \
1727 ) \
1728 { \
1729 if (fStrictCpuIdChecks) \
1730 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1731 N_(#bit " is not supported by the host but has already exposed to the guest")); \
1732 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1733 } \
1734 } while (0)
1735#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1736 do { \
1737 if ( (aGuestCpuId##set [1].reg & bit) \
1738 && !(aHostRaw##set [1].reg & bit) \
1739 && !(aHostOverride##set [1].reg & bit) \
1740 && !(aGuestOverride##set [1].reg & bit) \
1741 ) \
1742 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1743 } while (0)
1744#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1745 do { \
1746 if ( (aGuestCpuId##set [1].reg & bit) \
1747 && !(aHostRaw##set [1].reg & bit) \
1748 && !(aHostOverride##set [1].reg & bit) \
1749 && !(aGuestOverride##set [1].reg & bit) \
1750 ) \
1751 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1752 } while (0)
1753#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1754
1755 /* For checking guest features if AMD guest CPU. */
1756#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1757 do { \
1758 if ( (aGuestCpuId##set [1].reg & bit) \
1759 && fGuestAmd \
1760 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1761 && !(aHostOverride##set [1].reg & bit) \
1762 && !(aGuestOverride##set [1].reg & bit) \
1763 ) \
1764 { \
1765 if (fStrictCpuIdChecks) \
1766 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1767 N_(#bit " is not supported by the host but has already exposed to the guest")); \
1768 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1769 } \
1770 } while (0)
1771#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1772 do { \
1773 if ( (aGuestCpuId##set [1].reg & bit) \
1774 && fGuestAmd \
1775 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1776 && !(aHostOverride##set [1].reg & bit) \
1777 && !(aGuestOverride##set [1].reg & bit) \
1778 ) \
1779 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1780 } while (0)
1781#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1782 do { \
1783 if ( (aGuestCpuId##set [1].reg & bit) \
1784 && fGuestAmd \
1785 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1786 && !(aHostOverride##set [1].reg & bit) \
1787 && !(aGuestOverride##set [1].reg & bit) \
1788 ) \
1789 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1790 } while (0)
1791#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1792
1793 /* For checking AMD features which have a corresponding bit in the standard
1794 range. (Intel defines very few bits in the extended feature sets.) */
1795#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1796 do { \
1797 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1798 && !(fHostAmd \
1799 ? aHostRawExt[1].reg & (ExtBit) \
1800 : aHostRawStd[1].reg & (StdBit)) \
1801 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1802 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1803 ) \
1804 { \
1805 if (fStrictCpuIdChecks) \
1806 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1807 N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1808 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1809 } \
1810 } while (0)
1811#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1812 do { \
1813 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1814 && !(fHostAmd \
1815 ? aHostRawExt[1].reg & (ExtBit) \
1816 : aHostRawStd[1].reg & (StdBit)) \
1817 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1818 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1819 ) \
1820 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1821 } while (0)
1822#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1823 do { \
1824 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1825 && !(fHostAmd \
1826 ? aHostRawExt[1].reg & (ExtBit) \
1827 : aHostRawStd[1].reg & (StdBit)) \
1828 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1829 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1830 ) \
1831 LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1832 } while (0)
1833#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1834
1835 /*
1836 * Load them into stack buffers first.
1837 */
1838 CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1839 uint32_t cGuestCpuIdStd;
1840 int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1841 if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1842 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1843 SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1844
1845 CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1846 uint32_t cGuestCpuIdExt;
1847 rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1848 if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1849 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1850 SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1851
1852 CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1853 uint32_t cGuestCpuIdCentaur;
1854 rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1855 if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1856 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1857 SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1858
1859 CPUMCPUID GuestCpuIdDef;
1860 rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1861 AssertRCReturn(rc, rc);
1862
1863 CPUMCPUID aRawStd[16];
1864 uint32_t cRawStd;
1865 rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1866 if (cRawStd > RT_ELEMENTS(aRawStd))
1867 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1868 SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1869
1870 CPUMCPUID aRawExt[32];
1871 uint32_t cRawExt;
1872 rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1873 if (cRawExt > RT_ELEMENTS(aRawExt))
1874 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1875 rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1876 AssertRCReturn(rc, rc);
1877
1878 /*
1879 * Note that we support restoring less than the current amount of standard
1880 * leaves because we've been allowed more is newer version of VBox.
1881 *
1882 * So, pad new entries with the default.
1883 */
1884 for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1885 aGuestCpuIdStd[i] = GuestCpuIdDef;
1886
1887 for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1888 aGuestCpuIdExt[i] = GuestCpuIdDef;
1889
1890 for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1891 aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1892
1893 for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1894 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1895
1896 for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1897 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1898
1899 /*
1900 * Get the raw CPU IDs for the current host.
1901 */
1902 CPUMCPUID aHostRawStd[16];
1903 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1904 ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1905
1906 CPUMCPUID aHostRawExt[32];
1907 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1908 ASMCpuId(i | UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1909
1910 /*
1911 * Get the host and guest overrides so we don't reject the state because
1912 * some feature was enabled thru these interfaces.
1913 * Note! We currently only need the feature leaves, so skip rest.
1914 */
1915 PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1916 CPUMCPUID aGuestOverrideStd[2];
1917 memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1918 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1919
1920 CPUMCPUID aGuestOverrideExt[2];
1921 memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1922 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1923
1924 pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1925 CPUMCPUID aHostOverrideStd[2];
1926 memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1927 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1928
1929 CPUMCPUID aHostOverrideExt[2];
1930 memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1931 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1932
1933 /*
1934 * This can be skipped.
1935 */
1936 bool fStrictCpuIdChecks;
1937 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1938
1939
1940
1941 /*
1942 * For raw-mode we'll require that the CPUs are very similar since we don't
1943 * intercept CPUID instructions for user mode applications.
1944 */
1945 if (!HWACCMIsEnabled(pVM))
1946 {
1947 /* CPUID(0) */
1948 CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1949 && aHostRawStd[0].ecx == aRawStd[0].ecx
1950 && aHostRawStd[0].edx == aRawStd[0].edx,
1951 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1952 &aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1953 &aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1954 CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1955 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1956 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1957
1958 bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1959
1960 /* CPUID(1).eax */
1961 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1962 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1963 CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1964
1965 /* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1966 CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1967 CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1968
1969 /* CPUID(1).ecx */
1970 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1971 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1972 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1973 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1974 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1975 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1976 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1977 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1978 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1979 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1980 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1981 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
1982 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1983 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1984 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1985 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1986 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
1987 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
1988 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1989 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1990 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1991 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1992 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
1993 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
1994 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
1995 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
1996 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
1997 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
1998 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
1999 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
2000 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
2001 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_HVP);
2002
2003 /* CPUID(1).edx */
2004 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2005 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2006 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
2007 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2008 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
2009 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
2010 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2011 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2012 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
2013 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2014 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2015 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2016 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2017 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2018 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2019 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
2020 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2021 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2022 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2023 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
2024 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2025 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
2026 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
2027 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
2028 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
2029 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
2030 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
2031 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
2032 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
2033 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
2034 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/);
2035 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
2036
2037 /* CPUID(2) - config, mostly about caches. ignore. */
2038 /* CPUID(3) - processor serial number. ignore. */
2039 /* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
2040 /* CPUID(5) - mwait/monitor config. ignore. */
2041 /* CPUID(6) - power management. ignore. */
2042 /* CPUID(7) - ???. ignore. */
2043 /* CPUID(8) - ???. ignore. */
2044 /* CPUID(9) - DCA. ignore for now. */
2045 /* CPUID(a) - PeMo info. ignore for now. */
2046 /* CPUID(b) - topology info - takes ECX as input. ignore. */
2047
2048 /* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
2049 CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
2050 || aHostRawStd[0].eax >= UINT32_C(0x0000000d),
2051 ("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
2052 if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
2053 && aHostRawStd[0].eax >= UINT32_C(0x0000000d))
2054 {
2055 CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
2056 CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
2057 CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
2058 CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
2059 }
2060
2061 /* CPUID(0x80000000) - same as CPUID(0) except for eax.
2062 Note! Intel have/is marking many of the fields here as reserved. We
2063 will verify them as if it's an AMD CPU. */
2064 CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
2065 || !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
2066 (N_("Extended leaves was present on saved state host, but is missing on the current\n")));
2067 if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
2068 {
2069 CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
2070 && aHostRawExt[0].ecx == aRawExt[0].ecx
2071 && aHostRawExt[0].edx == aRawExt[0].edx,
2072 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
2073 &aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
2074 &aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
2075 CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
2076
2077 /* CPUID(0x80000001).eax - same as CPUID(0).eax. */
2078 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
2079 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
2080 CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
2081 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
2082 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
2083
2084 /* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
2085 CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
2086 CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
2087 CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
2088
2089 /* CPUID(0x80000001).ecx */
2090 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2091 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
2092 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
2093 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
2094 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2095 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
2096 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
2097 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
2098 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
2099 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
2100 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
2101 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
2102 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
2103 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
2104 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2105 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2106 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2107 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2108 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2109 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2110 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2111 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2112 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2113 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2114 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2115 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2116 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2117 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2118 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2119 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2120 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2121 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2122
2123 /* CPUID(0x80000001).edx */
2124 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
2125 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
2126 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
2127 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
2128 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
2129 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
2130 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
2131 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
2132 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
2133 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
2134 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2135 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SEP);
2136 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
2137 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
2138 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
2139 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2140 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
2141 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
2142 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2143 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2144 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2145 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /*reserved*/);
2146 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2147 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
2148 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
2149 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2150 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2151 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2152 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /*reserved*/);
2153 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2154 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2155 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2156
2157 /** @todo verify the rest as well. */
2158 }
2159 }
2160
2161
2162
2163 /*
2164 * Verify that we can support the features already exposed to the guest on
2165 * this host.
2166 *
2167 * Most of the features we're emulating requires intercepting instruction
2168 * and doing it the slow way, so there is no need to warn when they aren't
2169 * present in the host CPU. Thus we use IGN instead of EMU on these.
2170 *
2171 * Trailing comments:
2172 * "EMU" - Possible to emulate, could be lots of work and very slow.
2173 * "EMU?" - Can this be emulated?
2174 */
2175 /* CPUID(1).ecx */
2176 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
2177 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
2178 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
2179 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
2180 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
2181 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
2182 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
2183 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
2184 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
2185 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
2186 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
2187 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
2188 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
2189 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
2190 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
2191 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
2192 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
2193 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
2194 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
2195 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
2196 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
2197 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
2198 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
2199 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
2200 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
2201 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
2202 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
2203 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
2204 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
2205 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
2206 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
2207 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
2208
2209 /* CPUID(1).edx */
2210 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2211 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2212 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
2213 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2214 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2215 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2216 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2217 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2218 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2219 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2220 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2221 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2222 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2223 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2224 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2225 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2226 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2227 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2228 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2229 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
2230 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2231 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
2232 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
2233 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2234 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2235 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
2236 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
2237 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
2238 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
2239 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
2240 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/); // -> EMU
2241 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
2242
2243 /* CPUID(0x80000000). */
2244 if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
2245 && aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
2246 {
2247 /** @todo deal with no 0x80000001 on the host. */
2248 bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
2249 bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
2250
2251 /* CPUID(0x80000001).ecx */
2252 CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
2253 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
2254 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
2255 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
2256 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
2257 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
2258 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
2259 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
2260 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
2261 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
2262 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
2263 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
2264 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
2265 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
2266 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2267 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2268 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2269 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2270 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2271 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2272 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2273 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2274 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2275 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2276 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2277 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2278 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2279 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2280 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2281 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2282 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2283 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2284
2285 /* CPUID(0x80000001).edx */
2286 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
2287 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
2288 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
2289 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
2290 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2291 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2292 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
2293 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
2294 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2295 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
2296 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2297 CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
2298 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
2299 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
2300 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
2301 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2302 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
2303 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
2304 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2305 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2306 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2307 CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /*reserved*/);
2308 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2309 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2310 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2311 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2312 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2313 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2314 CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /*reserved*/);
2315 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2316 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2317 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2318 }
2319
2320 /*
2321 * We're good, commit the CPU ID leaves.
2322 */
2323 memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
2324 memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
2325 memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
2326 pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
2327
2328#undef CPUID_CHECK_RET
2329#undef CPUID_CHECK_WRN
2330#undef CPUID_CHECK2_RET
2331#undef CPUID_CHECK2_WRN
2332#undef CPUID_RAW_FEATURE_RET
2333#undef CPUID_RAW_FEATURE_WRN
2334#undef CPUID_RAW_FEATURE_IGN
2335#undef CPUID_GST_FEATURE_RET
2336#undef CPUID_GST_FEATURE_WRN
2337#undef CPUID_GST_FEATURE_EMU
2338#undef CPUID_GST_FEATURE_IGN
2339#undef CPUID_GST_FEATURE2_RET
2340#undef CPUID_GST_FEATURE2_WRN
2341#undef CPUID_GST_FEATURE2_EMU
2342#undef CPUID_GST_FEATURE2_IGN
2343#undef CPUID_GST_AMD_FEATURE_RET
2344#undef CPUID_GST_AMD_FEATURE_WRN
2345#undef CPUID_GST_AMD_FEATURE_EMU
2346#undef CPUID_GST_AMD_FEATURE_IGN
2347
2348 return VINF_SUCCESS;
2349}
2350
2351
2352/**
2353 * Pass 0 live exec callback.
2354 *
2355 * @returns VINF_SSM_DONT_CALL_AGAIN.
2356 * @param pVM Pointer to the VM.
2357 * @param pSSM The saved state handle.
2358 * @param uPass The pass (0).
2359 */
2360static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2361{
2362 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2363 cpumR3SaveCpuId(pVM, pSSM);
2364 return VINF_SSM_DONT_CALL_AGAIN;
2365}
2366
2367
2368/**
2369 * Execute state save operation.
2370 *
2371 * @returns VBox status code.
2372 * @param pVM Pointer to the VM.
2373 * @param pSSM SSM operation handle.
2374 */
2375static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2376{
2377 /*
2378 * Save.
2379 */
2380 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2381 {
2382 PVMCPU pVCpu = &pVM->aCpus[i];
2383 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
2384 }
2385
2386 SSMR3PutU32(pSSM, pVM->cCpus);
2387 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
2388 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2389 {
2390 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2391
2392 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), 0, g_aCpumCtxFields, NULL);
2393 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2394 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2395 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2396 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2397 }
2398
2399 cpumR3SaveCpuId(pVM, pSSM);
2400 return VINF_SUCCESS;
2401}
2402
2403
2404/**
2405 * @copydoc FNSSMINTLOADPREP
2406 */
2407static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2408{
2409 NOREF(pSSM);
2410 pVM->cpum.s.fPendingRestore = true;
2411 return VINF_SUCCESS;
2412}
2413
2414
2415/**
2416 * @copydoc FNSSMINTLOADEXEC
2417 */
2418static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2419{
2420 /*
2421 * Validate version.
2422 */
2423 if ( uVersion != CPUM_SAVED_STATE_VERSION
2424 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
2425 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2426 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2427 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2428 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2429 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2430 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2431 {
2432 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2433 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2434 }
2435
2436 if (uPass == SSM_PASS_FINAL)
2437 {
2438 /*
2439 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2440 * really old SSM file versions.)
2441 */
2442 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2443 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2444 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2445 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2446
2447 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2448 PCSSMFIELD paCpumCtxFields = g_aCpumCtxFields;
2449 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2450 paCpumCtxFields = g_aCpumCtxFieldsV16;
2451 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2452 paCpumCtxFields = g_aCpumCtxFieldsMem;
2453
2454 /*
2455 * Restore.
2456 */
2457 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2458 {
2459 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2460 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2461 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2462 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), fLoad, paCpumCtxFields, NULL);
2463 pVCpu->cpum.s.Hyper.cr3 = uCR3;
2464 pVCpu->cpum.s.Hyper.rsp = uRSP;
2465 }
2466
2467 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2468 {
2469 uint32_t cCpus;
2470 int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2471 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2472 VERR_SSM_UNEXPECTED_DATA);
2473 }
2474 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2475 || pVM->cCpus == 1,
2476 ("cCpus=%u\n", pVM->cCpus),
2477 VERR_SSM_UNEXPECTED_DATA);
2478
2479 uint32_t cbMsrs = 0;
2480 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2481 {
2482 int rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2483 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2484 VERR_SSM_UNEXPECTED_DATA);
2485 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2486 VERR_SSM_UNEXPECTED_DATA);
2487 }
2488
2489 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2490 {
2491 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2492 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), fLoad,
2493 paCpumCtxFields, NULL);
2494 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
2495 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2496 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2497 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2498 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2499 {
2500 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2501 SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2502 }
2503 }
2504
2505 /* Older states does not have the internal selector register flags
2506 and valid selector value. Supply those. */
2507 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2508 {
2509 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2510 {
2511 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2512 bool const fValid = HWACCMIsEnabled(pVM)
2513 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2514 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2515 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2516 if (fValid)
2517 {
2518 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2519 {
2520 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2521 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2522 }
2523
2524 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2525 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2526 }
2527 else
2528 {
2529 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2530 {
2531 paSelReg[iSelReg].fFlags = 0;
2532 paSelReg[iSelReg].ValidSel = 0;
2533 }
2534
2535 /* This might not be 104% correct, but I think it's close
2536 enough for all practical purposes... (REM always loaded
2537 LDTR registers.) */
2538 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2539 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2540 }
2541 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2542 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2543 }
2544 }
2545
2546 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2547 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2548 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2549 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2550 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2551
2552 /*
2553 * A quick sanity check.
2554 */
2555 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2556 {
2557 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2558 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2559 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2560 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2561 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2562 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2563 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2564 }
2565 }
2566
2567 pVM->cpum.s.fPendingRestore = false;
2568
2569 /*
2570 * Guest CPUIDs.
2571 */
2572 if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2573 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2574
2575 /** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2576 * actually required. */
2577
2578 /*
2579 * Restore the CPUID leaves.
2580 *
2581 * Note that we support restoring less than the current amount of standard
2582 * leaves because we've been allowed more is newer version of VBox.
2583 */
2584 uint32_t cElements;
2585 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2586 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2587 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2588 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2589
2590 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2591 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2592 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2593 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2594
2595 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2596 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2597 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2598 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2599
2600 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2601
2602 /*
2603 * Check that the basic cpuid id information is unchanged.
2604 */
2605 /** @todo we should check the 64 bits capabilities too! */
2606 uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2607 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2608 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2609 uint32_t au32CpuIdSaved[8];
2610 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2611 if (RT_SUCCESS(rc))
2612 {
2613 /* Ignore CPU stepping. */
2614 au32CpuId[4] &= 0xfffffff0;
2615 au32CpuIdSaved[4] &= 0xfffffff0;
2616
2617 /* Ignore APIC ID (AMD specs). */
2618 au32CpuId[5] &= ~0xff000000;
2619 au32CpuIdSaved[5] &= ~0xff000000;
2620
2621 /* Ignore the number of Logical CPUs (AMD specs). */
2622 au32CpuId[5] &= ~0x00ff0000;
2623 au32CpuIdSaved[5] &= ~0x00ff0000;
2624
2625 /* Ignore some advanced capability bits, that we don't expose to the guest. */
2626 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2627 | X86_CPUID_FEATURE_ECX_VMX
2628 | X86_CPUID_FEATURE_ECX_SMX
2629 | X86_CPUID_FEATURE_ECX_EST
2630 | X86_CPUID_FEATURE_ECX_TM2
2631 | X86_CPUID_FEATURE_ECX_CNTXID
2632 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2633 | X86_CPUID_FEATURE_ECX_PDCM
2634 | X86_CPUID_FEATURE_ECX_DCA
2635 | X86_CPUID_FEATURE_ECX_X2APIC
2636 );
2637 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2638 | X86_CPUID_FEATURE_ECX_VMX
2639 | X86_CPUID_FEATURE_ECX_SMX
2640 | X86_CPUID_FEATURE_ECX_EST
2641 | X86_CPUID_FEATURE_ECX_TM2
2642 | X86_CPUID_FEATURE_ECX_CNTXID
2643 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2644 | X86_CPUID_FEATURE_ECX_PDCM
2645 | X86_CPUID_FEATURE_ECX_DCA
2646 | X86_CPUID_FEATURE_ECX_X2APIC
2647 );
2648
2649 /* Make sure we don't forget to update the masks when enabling
2650 * features in the future.
2651 */
2652 AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2653 ( X86_CPUID_FEATURE_ECX_DTES64
2654 | X86_CPUID_FEATURE_ECX_VMX
2655 | X86_CPUID_FEATURE_ECX_SMX
2656 | X86_CPUID_FEATURE_ECX_EST
2657 | X86_CPUID_FEATURE_ECX_TM2
2658 | X86_CPUID_FEATURE_ECX_CNTXID
2659 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2660 | X86_CPUID_FEATURE_ECX_PDCM
2661 | X86_CPUID_FEATURE_ECX_DCA
2662 | X86_CPUID_FEATURE_ECX_X2APIC
2663 )));
2664 /* do the compare */
2665 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2666 {
2667 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2668 LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2669 "Saved=%.*Rhxs\n"
2670 "Real =%.*Rhxs\n",
2671 sizeof(au32CpuIdSaved), au32CpuIdSaved,
2672 sizeof(au32CpuId), au32CpuId));
2673 else
2674 {
2675 LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2676 "Saved=%.*Rhxs\n"
2677 "Real =%.*Rhxs\n",
2678 sizeof(au32CpuIdSaved), au32CpuIdSaved,
2679 sizeof(au32CpuId), au32CpuId));
2680 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2681 }
2682 }
2683 }
2684
2685 return rc;
2686}
2687
2688
2689/**
2690 * @copydoc FNSSMINTLOADPREP
2691 */
2692static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2693{
2694 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2695 return VINF_SUCCESS;
2696
2697 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2698 if (pVM->cpum.s.fPendingRestore)
2699 {
2700 LogRel(("CPUM: Missing state!\n"));
2701 return VERR_INTERNAL_ERROR_2;
2702 }
2703
2704 /* Notify PGM of the NXE states in case they've changed. */
2705 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2706 PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2707 return VINF_SUCCESS;
2708}
2709
2710
2711/**
2712 * Checks if the CPUM state restore is still pending.
2713 *
2714 * @returns true / false.
2715 * @param pVM Pointer to the VM.
2716 */
2717VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2718{
2719 return pVM->cpum.s.fPendingRestore;
2720}
2721
2722
2723/**
2724 * Formats the EFLAGS value into mnemonics.
2725 *
2726 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2727 * @param efl The EFLAGS value.
2728 */
2729static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2730{
2731 /*
2732 * Format the flags.
2733 */
2734 static const struct
2735 {
2736 const char *pszSet; const char *pszClear; uint32_t fFlag;
2737 } s_aFlags[] =
2738 {
2739 { "vip",NULL, X86_EFL_VIP },
2740 { "vif",NULL, X86_EFL_VIF },
2741 { "ac", NULL, X86_EFL_AC },
2742 { "vm", NULL, X86_EFL_VM },
2743 { "rf", NULL, X86_EFL_RF },
2744 { "nt", NULL, X86_EFL_NT },
2745 { "ov", "nv", X86_EFL_OF },
2746 { "dn", "up", X86_EFL_DF },
2747 { "ei", "di", X86_EFL_IF },
2748 { "tf", NULL, X86_EFL_TF },
2749 { "nt", "pl", X86_EFL_SF },
2750 { "nz", "zr", X86_EFL_ZF },
2751 { "ac", "na", X86_EFL_AF },
2752 { "po", "pe", X86_EFL_PF },
2753 { "cy", "nc", X86_EFL_CF },
2754 };
2755 char *psz = pszEFlags;
2756 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2757 {
2758 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2759 if (pszAdd)
2760 {
2761 strcpy(psz, pszAdd);
2762 psz += strlen(pszAdd);
2763 *psz++ = ' ';
2764 }
2765 }
2766 psz[-1] = '\0';
2767}
2768
2769
2770/**
2771 * Formats a full register dump.
2772 *
2773 * @param pVM Pointer to the VM.
2774 * @param pCtx The context to format.
2775 * @param pCtxCore The context core to format.
2776 * @param pHlp Output functions.
2777 * @param enmType The dump type.
2778 * @param pszPrefix Register name prefix.
2779 */
2780static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
2781 const char *pszPrefix)
2782{
2783 NOREF(pVM);
2784
2785 /*
2786 * Format the EFLAGS.
2787 */
2788 uint32_t efl = pCtxCore->eflags.u32;
2789 char szEFlags[80];
2790 cpumR3InfoFormatFlags(&szEFlags[0], efl);
2791
2792 /*
2793 * Format the registers.
2794 */
2795 switch (enmType)
2796 {
2797 case CPUMDUMPTYPE_TERSE:
2798 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2799 pHlp->pfnPrintf(pHlp,
2800 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2801 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2802 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2803 "%sr14=%016RX64 %sr15=%016RX64\n"
2804 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2805 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2806 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2807 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2808 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2809 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2810 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2811 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2812 else
2813 pHlp->pfnPrintf(pHlp,
2814 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2815 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2816 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2817 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2818 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2819 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2820 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2821 break;
2822
2823 case CPUMDUMPTYPE_DEFAULT:
2824 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2825 pHlp->pfnPrintf(pHlp,
2826 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2827 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2828 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2829 "%sr14=%016RX64 %sr15=%016RX64\n"
2830 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2831 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2832 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2833 ,
2834 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2835 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2836 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2837 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2838 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2839 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2840 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2841 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2842 else
2843 pHlp->pfnPrintf(pHlp,
2844 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2845 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2846 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2847 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2848 ,
2849 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2850 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2851 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2852 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2853 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2854 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2855 break;
2856
2857 case CPUMDUMPTYPE_VERBOSE:
2858 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2859 pHlp->pfnPrintf(pHlp,
2860 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2861 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2862 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2863 "%sr14=%016RX64 %sr15=%016RX64\n"
2864 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2865 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2866 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2867 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2868 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2869 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2870 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2871 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2872 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2873 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2874 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2875 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2876 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2877 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2878 ,
2879 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2880 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2881 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2882 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2883 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2884 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2885 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2886 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2887 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2888 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2889 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2890 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2891 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2892 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2893 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2894 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2895 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2896 else
2897 pHlp->pfnPrintf(pHlp,
2898 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2899 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2900 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2901 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2902 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2903 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2904 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2905 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2906 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2907 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2908 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2909 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2910 ,
2911 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2912 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2913 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2914 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2915 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2916 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2917 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2918 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2919 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2920 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2921 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2922 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2923
2924 pHlp->pfnPrintf(pHlp,
2925 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2926 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2927 ,
2928 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2929 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2930 pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsrvd1,
2931 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2932 );
2933 unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2934 for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2935 {
2936 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2937 unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2938 char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2939 unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2940 uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2941 unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2942 /** @todo This isn't entirenly correct and needs more work! */
2943 pHlp->pfnPrintf(pHlp,
2944 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2945 pszPrefix, iST, pszPrefix, iFPR,
2946 pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2947 uTag, chSign, iInteger, u64Fraction, uExponent);
2948 if (pCtx->fpu.aRegs[0].au16[5] || pCtx->fpu.aRegs[0].au16[6] || pCtx->fpu.aRegs[0].au16[7])
2949 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2950 pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2951 else
2952 pHlp->pfnPrintf(pHlp, "\n");
2953 }
2954 for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2955 pHlp->pfnPrintf(pHlp,
2956 iXMM & 1
2957 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2958 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2959 pszPrefix, iXMM, iXMM < 10 ? " " : "",
2960 pCtx->fpu.aXMM[iXMM].au32[3],
2961 pCtx->fpu.aXMM[iXMM].au32[2],
2962 pCtx->fpu.aXMM[iXMM].au32[1],
2963 pCtx->fpu.aXMM[iXMM].au32[0]);
2964 for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2965 if (pCtx->fpu.au32RsrvdRest[i])
2966 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2967 pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2968
2969 pHlp->pfnPrintf(pHlp,
2970 "%sEFER =%016RX64\n"
2971 "%sPAT =%016RX64\n"
2972 "%sSTAR =%016RX64\n"
2973 "%sCSTAR =%016RX64\n"
2974 "%sLSTAR =%016RX64\n"
2975 "%sSFMASK =%016RX64\n"
2976 "%sKERNELGSBASE =%016RX64\n",
2977 pszPrefix, pCtx->msrEFER,
2978 pszPrefix, pCtx->msrPAT,
2979 pszPrefix, pCtx->msrSTAR,
2980 pszPrefix, pCtx->msrCSTAR,
2981 pszPrefix, pCtx->msrLSTAR,
2982 pszPrefix, pCtx->msrSFMASK,
2983 pszPrefix, pCtx->msrKERNELGSBASE);
2984 break;
2985 }
2986}
2987
2988
2989/**
2990 * Display all cpu states and any other cpum info.
2991 *
2992 * @param pVM Pointer to the VM.
2993 * @param pHlp The info helper functions.
2994 * @param pszArgs Arguments, ignored.
2995 */
2996static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2997{
2998 cpumR3InfoGuest(pVM, pHlp, pszArgs);
2999 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3000 cpumR3InfoHyper(pVM, pHlp, pszArgs);
3001 cpumR3InfoHost(pVM, pHlp, pszArgs);
3002}
3003
3004
3005/**
3006 * Parses the info argument.
3007 *
3008 * The argument starts with 'verbose', 'terse' or 'default' and then
3009 * continues with the comment string.
3010 *
3011 * @param pszArgs The pointer to the argument string.
3012 * @param penmType Where to store the dump type request.
3013 * @param ppszComment Where to store the pointer to the comment string.
3014 */
3015static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
3016{
3017 if (!pszArgs)
3018 {
3019 *penmType = CPUMDUMPTYPE_DEFAULT;
3020 *ppszComment = "";
3021 }
3022 else
3023 {
3024 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
3025 {
3026 pszArgs += 7;
3027 *penmType = CPUMDUMPTYPE_VERBOSE;
3028 }
3029 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
3030 {
3031 pszArgs += 5;
3032 *penmType = CPUMDUMPTYPE_TERSE;
3033 }
3034 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
3035 {
3036 pszArgs += 7;
3037 *penmType = CPUMDUMPTYPE_DEFAULT;
3038 }
3039 else
3040 *penmType = CPUMDUMPTYPE_DEFAULT;
3041 *ppszComment = RTStrStripL(pszArgs);
3042 }
3043}
3044
3045
3046/**
3047 * Display the guest cpu state.
3048 *
3049 * @param pVM Pointer to the VM.
3050 * @param pHlp The info helper functions.
3051 * @param pszArgs Arguments, ignored.
3052 */
3053static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3054{
3055 CPUMDUMPTYPE enmType;
3056 const char *pszComment;
3057 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3058
3059 /* @todo SMP support! */
3060 PVMCPU pVCpu = VMMGetCpu(pVM);
3061 if (!pVCpu)
3062 pVCpu = &pVM->aCpus[0];
3063
3064 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3065
3066 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
3067 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3068}
3069
3070
3071/**
3072 * Display the current guest instruction
3073 *
3074 * @param pVM Pointer to the VM.
3075 * @param pHlp The info helper functions.
3076 * @param pszArgs Arguments, ignored.
3077 */
3078static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3079{
3080 NOREF(pszArgs);
3081
3082 /** @todo SMP support! */
3083 PVMCPU pVCpu = VMMGetCpu(pVM);
3084 if (!pVCpu)
3085 pVCpu = &pVM->aCpus[0];
3086
3087 char szInstruction[256];
3088 int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
3089 if (RT_SUCCESS(rc))
3090 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
3091}
3092
3093
3094/**
3095 * Display the hypervisor cpu state.
3096 *
3097 * @param pVM Pointer to the VM.
3098 * @param pHlp The info helper functions.
3099 * @param pszArgs Arguments, ignored.
3100 */
3101static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3102{
3103 CPUMDUMPTYPE enmType;
3104 const char *pszComment;
3105 /* @todo SMP */
3106 PVMCPU pVCpu = &pVM->aCpus[0];
3107
3108 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3109 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
3110 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
3111 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
3112}
3113
3114
3115/**
3116 * Display the host cpu state.
3117 *
3118 * @param pVM Pointer to the VM.
3119 * @param pHlp The info helper functions.
3120 * @param pszArgs Arguments, ignored.
3121 */
3122static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3123{
3124 CPUMDUMPTYPE enmType;
3125 const char *pszComment;
3126 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3127 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
3128
3129 /*
3130 * Format the EFLAGS.
3131 */
3132 /* @todo SMP */
3133 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
3134#if HC_ARCH_BITS == 32
3135 uint32_t efl = pCtx->eflags.u32;
3136#else
3137 uint64_t efl = pCtx->rflags;
3138#endif
3139 char szEFlags[80];
3140 cpumR3InfoFormatFlags(&szEFlags[0], efl);
3141
3142 /*
3143 * Format the registers.
3144 */
3145#if HC_ARCH_BITS == 32
3146# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3147 if (!(pCtx->efer & MSR_K6_EFER_LMA))
3148# endif
3149 {
3150 pHlp->pfnPrintf(pHlp,
3151 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
3152 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
3153 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
3154 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
3155 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
3156 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3157 ,
3158 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
3159 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
3160 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3161 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
3162 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
3163 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
3164 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3165 }
3166# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3167 else
3168# endif
3169#endif
3170#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3171 {
3172 pHlp->pfnPrintf(pHlp,
3173 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
3174 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
3175 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
3176 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
3177 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
3178 "r14=%016RX64 r15=%016RX64\n"
3179 "iopl=%d %31s\n"
3180 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
3181 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
3182 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
3183 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
3184 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
3185 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
3186 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3187 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
3188 ,
3189 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
3190 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
3191 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
3192 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
3193 pCtx->r11, pCtx->r12, pCtx->r13,
3194 pCtx->r14, pCtx->r15,
3195 X86_EFL_GET_IOPL(efl), szEFlags,
3196 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3197 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
3198 pCtx->cr4, pCtx->ldtr, pCtx->tr,
3199 pCtx->dr0, pCtx->dr1, pCtx->dr2,
3200 pCtx->dr3, pCtx->dr6, pCtx->dr7,
3201 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
3202 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
3203 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
3204 }
3205#endif
3206}
3207
3208
3209/**
3210 * Get L1 cache / TLS associativity.
3211 */
3212static const char *getCacheAss(unsigned u, char *pszBuf)
3213{
3214 if (u == 0)
3215 return "res0 ";
3216 if (u == 1)
3217 return "direct";
3218 if (u == 255)
3219 return "fully";
3220 if (u >= 256)
3221 return "???";
3222
3223 RTStrPrintf(pszBuf, 16, "%d way", u);
3224 return pszBuf;
3225}
3226
3227
3228/**
3229 * Get L2 cache associativity.
3230 */
3231const char *getL2CacheAss(unsigned u)
3232{
3233 switch (u)
3234 {
3235 case 0: return "off ";
3236 case 1: return "direct";
3237 case 2: return "2 way ";
3238 case 3: return "res3 ";
3239 case 4: return "4 way ";
3240 case 5: return "res5 ";
3241 case 6: return "8 way ";
3242 case 7: return "res7 ";
3243 case 8: return "16 way";
3244 case 9: return "res9 ";
3245 case 10: return "res10 ";
3246 case 11: return "res11 ";
3247 case 12: return "res12 ";
3248 case 13: return "res13 ";
3249 case 14: return "res14 ";
3250 case 15: return "fully ";
3251 default: return "????";
3252 }
3253}
3254
3255
3256/**
3257 * Display the guest CpuId leaves.
3258 *
3259 * @param pVM Pointer to the VM.
3260 * @param pHlp The info helper functions.
3261 * @param pszArgs "terse", "default" or "verbose".
3262 */
3263static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3264{
3265 /*
3266 * Parse the argument.
3267 */
3268 unsigned iVerbosity = 1;
3269 if (pszArgs)
3270 {
3271 pszArgs = RTStrStripL(pszArgs);
3272 if (!strcmp(pszArgs, "terse"))
3273 iVerbosity--;
3274 else if (!strcmp(pszArgs, "verbose"))
3275 iVerbosity++;
3276 }
3277
3278 /*
3279 * Start cracking.
3280 */
3281 CPUMCPUID Host;
3282 CPUMCPUID Guest;
3283 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
3284
3285 pHlp->pfnPrintf(pHlp,
3286 " RAW Standard CPUIDs\n"
3287 " Function eax ebx ecx edx\n");
3288 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
3289 {
3290 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
3291 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3292
3293 pHlp->pfnPrintf(pHlp,
3294 "Gst: %08x %08x %08x %08x %08x%s\n"
3295 "Hst: %08x %08x %08x %08x\n",
3296 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3297 i <= cStdMax ? "" : "*",
3298 Host.eax, Host.ebx, Host.ecx, Host.edx);
3299 }
3300
3301 /*
3302 * If verbose, decode it.
3303 */
3304 if (iVerbosity)
3305 {
3306 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
3307 pHlp->pfnPrintf(pHlp,
3308 "Name: %.04s%.04s%.04s\n"
3309 "Supports: 0-%x\n",
3310 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3311 }
3312
3313 /*
3314 * Get Features.
3315 */
3316 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
3317 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
3318 pVM->cpum.s.aGuestCpuIdStd[0].edx);
3319 if (cStdMax >= 1 && iVerbosity)
3320 {
3321 static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
3322
3323 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
3324 uint32_t uEAX = Guest.eax;
3325
3326 pHlp->pfnPrintf(pHlp,
3327 "Family: %d \tExtended: %d \tEffective: %d\n"
3328 "Model: %d \tExtended: %d \tEffective: %d\n"
3329 "Stepping: %d\n"
3330 "Type: %d (%s)\n"
3331 "APIC ID: %#04x\n"
3332 "Logical CPUs: %d\n"
3333 "CLFLUSH Size: %d\n"
3334 "Brand ID: %#04x\n",
3335 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3336 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3337 ASMGetCpuStepping(uEAX),
3338 (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
3339 (Guest.ebx >> 24) & 0xff,
3340 (Guest.ebx >> 16) & 0xff,
3341 (Guest.ebx >> 8) & 0xff,
3342 (Guest.ebx >> 0) & 0xff);
3343 if (iVerbosity == 1)
3344 {
3345 uint32_t uEDX = Guest.edx;
3346 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3347 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3348 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3349 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3350 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3351 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3352 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3353 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3354 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3355 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3356 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3357 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3358 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
3359 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3360 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3361 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3362 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3363 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3364 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3365 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
3366 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
3367 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
3368 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
3369 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
3370 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3371 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3372 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
3373 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
3374 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
3375 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
3376 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
3377 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3378 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
3379 pHlp->pfnPrintf(pHlp, "\n");
3380
3381 uint32_t uECX = Guest.ecx;
3382 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3383 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
3384 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
3385 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
3386 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
3387 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
3388 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
3389 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
3390 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
3391 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
3392 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
3393 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
3394 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
3395 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
3396 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
3397 if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
3398 if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
3399 if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
3400 if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID");
3401 if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
3402 if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1");
3403 if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2");
3404 if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
3405 if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
3406 if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
3407 if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL");
3408 if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
3409 if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
3410 if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
3411 if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
3412 if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
3413 if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3414 if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
3415 pHlp->pfnPrintf(pHlp, "\n");
3416 }
3417 else
3418 {
3419 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3420
3421 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
3422 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
3423 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
3424 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
3425
3426 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3427 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
3428 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
3429 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
3430 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
3431 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
3432 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
3433 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
3434 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
3435 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
3436 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
3437 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
3438 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
3439 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
3440 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
3441 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
3442 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
3443 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
3444 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
3445 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
3446 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
3447 pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
3448 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
3449 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
3450 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
3451 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
3452 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
3453 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
3454 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
3455 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technology = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
3456 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
3457 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
3458 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
3459
3460 pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
3461 pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ);
3462 pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
3463 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
3464 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
3465 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
3466 pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
3467 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
3468 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
3469 pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
3470 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
3471 pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
3472 pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
3473 pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
3474 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
3475 pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
3476 pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
3477 pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID);
3478 pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
3479 pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
3480 pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
3481 pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
3482 pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
3483 pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
3484 pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE);
3485 pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES);
3486 pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
3487 pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
3488 pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX);
3489 pHlp->pfnPrintf(pHlp, "29/30 - Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
3490 pHlp->pfnPrintf(pHlp, "Hypervisor Present (we're a guest) = %d (%d)\n", EcxGuest.u1HVP, EcxHost.u1HVP);
3491 }
3492 }
3493 if (cStdMax >= 2 && iVerbosity)
3494 {
3495 /** @todo */
3496 }
3497
3498 /*
3499 * Extended.
3500 * Implemented after AMD specs.
3501 */
3502 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
3503
3504 pHlp->pfnPrintf(pHlp,
3505 "\n"
3506 " RAW Extended CPUIDs\n"
3507 " Function eax ebx ecx edx\n");
3508 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
3509 {
3510 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
3511 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3512
3513 pHlp->pfnPrintf(pHlp,
3514 "Gst: %08x %08x %08x %08x %08x%s\n"
3515 "Hst: %08x %08x %08x %08x\n",
3516 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3517 i <= cExtMax ? "" : "*",
3518 Host.eax, Host.ebx, Host.ecx, Host.edx);
3519 }
3520
3521 /*
3522 * Understandable output
3523 */
3524 if (iVerbosity)
3525 {
3526 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
3527 pHlp->pfnPrintf(pHlp,
3528 "Ext Name: %.4s%.4s%.4s\n"
3529 "Ext Supports: 0x80000000-%#010x\n",
3530 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3531 }
3532
3533 if (iVerbosity && cExtMax >= 1)
3534 {
3535 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
3536 uint32_t uEAX = Guest.eax;
3537 pHlp->pfnPrintf(pHlp,
3538 "Family: %d \tExtended: %d \tEffective: %d\n"
3539 "Model: %d \tExtended: %d \tEffective: %d\n"
3540 "Stepping: %d\n"
3541 "Brand ID: %#05x\n",
3542 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3543 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3544 ASMGetCpuStepping(uEAX),
3545 Guest.ebx & 0xfff);
3546
3547 if (iVerbosity == 1)
3548 {
3549 uint32_t uEDX = Guest.edx;
3550 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3551 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3552 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3553 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3554 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3555 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3556 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3557 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3558 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3559 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3560 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3561 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3562 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
3563 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3564 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3565 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3566 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3567 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3568 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3569 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
3570 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
3571 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
3572 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
3573 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
3574 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3575 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3576 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
3577 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
3578 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
3579 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
3580 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
3581 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
3582 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
3583 pHlp->pfnPrintf(pHlp, "\n");
3584
3585 uint32_t uECX = Guest.ecx;
3586 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3587 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
3588 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
3589 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
3590 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3591 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3592 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3593 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3594 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3595 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3596 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3597 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3598 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3599 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3600 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3601 for (unsigned iBit = 5; iBit < 32; iBit++)
3602 if (uECX & RT_BIT(iBit))
3603 pHlp->pfnPrintf(pHlp, " %d", iBit);
3604 pHlp->pfnPrintf(pHlp, "\n");
3605 }
3606 else
3607 {
3608 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3609
3610 uint32_t uEdxGst = Guest.edx;
3611 uint32_t uEdxHst = Host.edx;
3612 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3613 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3614 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3615 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3616 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3617 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3618 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3619 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3620 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3621 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3622 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3623 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3624 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3625 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3626 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3627 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3628 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3629 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3630 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3631 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3632 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3633 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3634 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3635 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3636 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3637 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3638 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3639 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3640 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3641 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3642 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3643 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3644 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3645
3646 uint32_t uEcxGst = Guest.ecx;
3647 uint32_t uEcxHst = Host.ecx;
3648 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3649 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3650 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3651 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3652 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3653 pHlp->pfnPrintf(pHlp, "5 - Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3654 pHlp->pfnPrintf(pHlp, "6 - SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3655 pHlp->pfnPrintf(pHlp, "7 - Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3656 pHlp->pfnPrintf(pHlp, "8 - PREFETCH and PREFETCHW instruction= %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3657 pHlp->pfnPrintf(pHlp, "9 - OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3658 pHlp->pfnPrintf(pHlp, "10 - Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3659 pHlp->pfnPrintf(pHlp, "11 - SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3660 pHlp->pfnPrintf(pHlp, "12 - SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3661 pHlp->pfnPrintf(pHlp, "13 - Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3662 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3663 }
3664 }
3665
3666 if (iVerbosity && cExtMax >= 2)
3667 {
3668 char szString[4*4*3+1] = {0};
3669 uint32_t *pu32 = (uint32_t *)szString;
3670 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3671 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3672 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3673 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3674 if (cExtMax >= 3)
3675 {
3676 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3677 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3678 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3679 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3680 }
3681 if (cExtMax >= 4)
3682 {
3683 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3684 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3685 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3686 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3687 }
3688 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3689 }
3690
3691 if (iVerbosity && cExtMax >= 5)
3692 {
3693 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3694 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3695 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3696 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3697 char sz1[32];
3698 char sz2[32];
3699
3700 pHlp->pfnPrintf(pHlp,
3701 "TLB 2/4M Instr/Uni: %s %3d entries\n"
3702 "TLB 2/4M Data: %s %3d entries\n",
3703 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3704 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3705 pHlp->pfnPrintf(pHlp,
3706 "TLB 4K Instr/Uni: %s %3d entries\n"
3707 "TLB 4K Data: %s %3d entries\n",
3708 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3709 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3710 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3711 "L1 Instr Cache Lines Per Tag: %d\n"
3712 "L1 Instr Cache Associativity: %s\n"
3713 "L1 Instr Cache Size: %d KB\n",
3714 (uEDX >> 0) & 0xff,
3715 (uEDX >> 8) & 0xff,
3716 getCacheAss((uEDX >> 16) & 0xff, sz1),
3717 (uEDX >> 24) & 0xff);
3718 pHlp->pfnPrintf(pHlp,
3719 "L1 Data Cache Line Size: %d bytes\n"
3720 "L1 Data Cache Lines Per Tag: %d\n"
3721 "L1 Data Cache Associativity: %s\n"
3722 "L1 Data Cache Size: %d KB\n",
3723 (uECX >> 0) & 0xff,
3724 (uECX >> 8) & 0xff,
3725 getCacheAss((uECX >> 16) & 0xff, sz1),
3726 (uECX >> 24) & 0xff);
3727 }
3728
3729 if (iVerbosity && cExtMax >= 6)
3730 {
3731 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3732 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3733 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3734
3735 pHlp->pfnPrintf(pHlp,
3736 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3737 "L2 TLB 2/4M Data: %s %4d entries\n",
3738 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3739 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3740 pHlp->pfnPrintf(pHlp,
3741 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
3742 "L2 TLB 4K Data: %s %4d entries\n",
3743 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3744 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3745 pHlp->pfnPrintf(pHlp,
3746 "L2 Cache Line Size: %d bytes\n"
3747 "L2 Cache Lines Per Tag: %d\n"
3748 "L2 Cache Associativity: %s\n"
3749 "L2 Cache Size: %d KB\n",
3750 (uEDX >> 0) & 0xff,
3751 (uEDX >> 8) & 0xf,
3752 getL2CacheAss((uEDX >> 12) & 0xf),
3753 (uEDX >> 16) & 0xffff);
3754 }
3755
3756 if (iVerbosity && cExtMax >= 7)
3757 {
3758 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3759
3760 pHlp->pfnPrintf(pHlp, "APM Features: ");
3761 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3762 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3763 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3764 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3765 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3766 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3767 for (unsigned iBit = 6; iBit < 32; iBit++)
3768 if (uEDX & RT_BIT(iBit))
3769 pHlp->pfnPrintf(pHlp, " %d", iBit);
3770 pHlp->pfnPrintf(pHlp, "\n");
3771 }
3772
3773 if (iVerbosity && cExtMax >= 8)
3774 {
3775 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3776 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3777
3778 pHlp->pfnPrintf(pHlp,
3779 "Physical Address Width: %d bits\n"
3780 "Virtual Address Width: %d bits\n"
3781 "Guest Physical Address Width: %d bits\n",
3782 (uEAX >> 0) & 0xff,
3783 (uEAX >> 8) & 0xff,
3784 (uEAX >> 16) & 0xff);
3785 pHlp->pfnPrintf(pHlp,
3786 "Physical Core Count: %d\n",
3787 (uECX >> 0) & 0xff);
3788 }
3789
3790
3791 /*
3792 * Centaur.
3793 */
3794 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3795
3796 pHlp->pfnPrintf(pHlp,
3797 "\n"
3798 " RAW Centaur CPUIDs\n"
3799 " Function eax ebx ecx edx\n");
3800 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3801 {
3802 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3803 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3804
3805 pHlp->pfnPrintf(pHlp,
3806 "Gst: %08x %08x %08x %08x %08x%s\n"
3807 "Hst: %08x %08x %08x %08x\n",
3808 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3809 i <= cCentaurMax ? "" : "*",
3810 Host.eax, Host.ebx, Host.ecx, Host.edx);
3811 }
3812
3813 /*
3814 * Understandable output
3815 */
3816 if (iVerbosity)
3817 {
3818 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3819 pHlp->pfnPrintf(pHlp,
3820 "Centaur Supports: 0xc0000000-%#010x\n",
3821 Guest.eax);
3822 }
3823
3824 if (iVerbosity && cCentaurMax >= 1)
3825 {
3826 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3827 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3828 uint32_t uEdxHst = Host.edx;
3829
3830 if (iVerbosity == 1)
3831 {
3832 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3833 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3834 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3835 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3836 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3837 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3838 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3839 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3840 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3841 /* possibly indicating MM/HE and MM/HE-E on older chips... */
3842 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3843 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3844 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3845 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3846 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3847 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3848 for (unsigned iBit = 14; iBit < 32; iBit++)
3849 if (uEdxGst & RT_BIT(iBit))
3850 pHlp->pfnPrintf(pHlp, " %d", iBit);
3851 pHlp->pfnPrintf(pHlp, "\n");
3852 }
3853 else
3854 {
3855 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3856 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3857 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3858 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3859 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3860 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3861 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3862 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3863 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3864 /* possibly indicating MM/HE and MM/HE-E on older chips... */
3865 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3866 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3867 pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3868 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3869 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3870 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3871 pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3872 pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3873 pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3874 pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3875 pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3876 pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3877 pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3878 pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3879 pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3880 pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3881 pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3882 pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3883 pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3884 for (unsigned iBit = 27; iBit < 32; iBit++)
3885 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
3886 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3887 pHlp->pfnPrintf(pHlp, "\n");
3888 }
3889 }
3890}
3891
3892
3893/**
3894 * Structure used when disassembling and instructions in DBGF.
3895 * This is used so the reader function can get the stuff it needs.
3896 */
3897typedef struct CPUMDISASSTATE
3898{
3899 /** Pointer to the CPU structure. */
3900 PDISCPUSTATE pCpu;
3901 /** Pointer to the VM. */
3902 PVM pVM;
3903 /** Pointer to the VMCPU. */
3904 PVMCPU pVCpu;
3905 /** Pointer to the first byte in the segment. */
3906 RTGCUINTPTR GCPtrSegBase;
3907 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
3908 RTGCUINTPTR GCPtrSegEnd;
3909 /** The size of the segment minus 1. */
3910 RTGCUINTPTR cbSegLimit;
3911 /** Pointer to the current page - R3 Ptr. */
3912 void const *pvPageR3;
3913 /** Pointer to the current page - GC Ptr. */
3914 RTGCPTR pvPageGC;
3915 /** The lock information that PGMPhysReleasePageMappingLock needs. */
3916 PGMPAGEMAPLOCK PageMapLock;
3917 /** Whether the PageMapLock is valid or not. */
3918 bool fLocked;
3919 /** 64 bits mode or not. */
3920 bool f64Bits;
3921} CPUMDISASSTATE, *PCPUMDISASSTATE;
3922
3923
3924/**
3925 * @callback_method_impl{FNDISREADBYTES}
3926 */
3927static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
3928{
3929 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
3930 for (;;)
3931 {
3932 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
3933
3934 /*
3935 * Need to update the page translation?
3936 */
3937 if ( !pState->pvPageR3
3938 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3939 {
3940 int rc = VINF_SUCCESS;
3941
3942 /* translate the address */
3943 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3944 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3945 && !HWACCMIsEnabled(pState->pVM))
3946 {
3947 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3948 if (!pState->pvPageR3)
3949 rc = VERR_INVALID_POINTER;
3950 }
3951 else
3952 {
3953 /* Release mapping lock previously acquired. */
3954 if (pState->fLocked)
3955 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3956 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3957 pState->fLocked = RT_SUCCESS_NP(rc);
3958 }
3959 if (RT_FAILURE(rc))
3960 {
3961 pState->pvPageR3 = NULL;
3962 return rc;
3963 }
3964 }
3965
3966 /*
3967 * Check the segment limit.
3968 */
3969 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
3970 return VERR_OUT_OF_SELECTOR_BOUNDS;
3971
3972 /*
3973 * Calc how much we can read.
3974 */
3975 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3976 if (!pState->f64Bits)
3977 {
3978 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3979 if (cb > cbSeg && cbSeg)
3980 cb = cbSeg;
3981 }
3982 if (cb > cbMaxRead)
3983 cb = cbMaxRead;
3984
3985 /*
3986 * Read and advance or exit.
3987 */
3988 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3989 offInstr += (uint8_t)cb;
3990 if (cb >= cbMinRead)
3991 {
3992 pDis->cbCachedInstr = offInstr;
3993 return VINF_SUCCESS;
3994 }
3995 cbMinRead -= (uint8_t)cb;
3996 cbMaxRead -= (uint8_t)cb;
3997 }
3998}
3999
4000
4001/**
4002 * Disassemble an instruction and return the information in the provided structure.
4003 *
4004 * @returns VBox status code.
4005 * @param pVM Pointer to the VM.
4006 * @param pVCpu Pointer to the VMCPU.
4007 * @param pCtx Pointer to the guest CPU context.
4008 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
4009 * @param pCpu Disassembly state.
4010 * @param pszPrefix String prefix for logging (debug only).
4011 *
4012 */
4013VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
4014{
4015 CPUMDISASSTATE State;
4016 int rc;
4017
4018 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4019 State.pCpu = pCpu;
4020 State.pvPageGC = 0;
4021 State.pvPageR3 = NULL;
4022 State.pVM = pVM;
4023 State.pVCpu = pVCpu;
4024 State.fLocked = false;
4025 State.f64Bits = false;
4026
4027 /*
4028 * Get selector information.
4029 */
4030 DISCPUMODE enmDisCpuMode;
4031 if ( (pCtx->cr0 & X86_CR0_PE)
4032 && pCtx->eflags.Bits.u1VM == 0)
4033 {
4034 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4035 {
4036 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
4037 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4038 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4039 }
4040 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4041 State.GCPtrSegBase = pCtx->cs.u64Base;
4042 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4043 State.cbSegLimit = pCtx->cs.u32Limit;
4044 enmDisCpuMode = (State.f64Bits)
4045 ? DISCPUMODE_64BIT
4046 : pCtx->cs.Attr.n.u1DefBig
4047 ? DISCPUMODE_32BIT
4048 : DISCPUMODE_16BIT;
4049 }
4050 else
4051 {
4052 /* real or V86 mode */
4053 enmDisCpuMode = DISCPUMODE_16BIT;
4054 State.GCPtrSegBase = pCtx->cs.Sel * 16;
4055 State.GCPtrSegEnd = 0xFFFFFFFF;
4056 State.cbSegLimit = 0xFFFFFFFF;
4057 }
4058
4059 /*
4060 * Disassemble the instruction.
4061 */
4062 uint32_t cbInstr;
4063#ifndef LOG_ENABLED
4064 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4065 if (RT_SUCCESS(rc))
4066 {
4067#else
4068 char szOutput[160];
4069 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4070 pCpu, &cbInstr, szOutput, sizeof(szOutput));
4071 if (RT_SUCCESS(rc))
4072 {
4073 /* log it */
4074 if (pszPrefix)
4075 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4076 else
4077 Log(("%s", szOutput));
4078#endif
4079 rc = VINF_SUCCESS;
4080 }
4081 else
4082 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4083
4084 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
4085 if (State.fLocked)
4086 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4087
4088 return rc;
4089}
4090
4091
4092
4093/**
4094 * API for controlling a few of the CPU features found in CR4.
4095 *
4096 * Currently only X86_CR4_TSD is accepted as input.
4097 *
4098 * @returns VBox status code.
4099 *
4100 * @param pVM Pointer to the VM.
4101 * @param fOr The CR4 OR mask.
4102 * @param fAnd The CR4 AND mask.
4103 */
4104VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4105{
4106 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4107 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4108
4109 pVM->cpum.s.CR4.OrMask &= fAnd;
4110 pVM->cpum.s.CR4.OrMask |= fOr;
4111
4112 return VINF_SUCCESS;
4113}
4114
4115
4116/**
4117 * Gets a pointer to the array of standard CPUID leaves.
4118 *
4119 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
4120 *
4121 * @returns Pointer to the standard CPUID leaves (read-only).
4122 * @param pVM Pointer to the VM.
4123 * @remark Intended for PATM.
4124 */
4125VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
4126{
4127 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
4128}
4129
4130
4131/**
4132 * Gets a pointer to the array of extended CPUID leaves.
4133 *
4134 * CPUMGetGuestCpuIdExtMax() give the size of the array.
4135 *
4136 * @returns Pointer to the extended CPUID leaves (read-only).
4137 * @param pVM Pointer to the VM.
4138 * @remark Intended for PATM.
4139 */
4140VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
4141{
4142 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
4143}
4144
4145
4146/**
4147 * Gets a pointer to the array of centaur CPUID leaves.
4148 *
4149 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
4150 *
4151 * @returns Pointer to the centaur CPUID leaves (read-only).
4152 * @param pVM Pointer to the VM.
4153 * @remark Intended for PATM.
4154 */
4155VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
4156{
4157 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
4158}
4159
4160
4161/**
4162 * Gets a pointer to the default CPUID leaf.
4163 *
4164 * @returns Pointer to the default CPUID leaf (read-only).
4165 * @param pVM Pointer to the VM.
4166 * @remark Intended for PATM.
4167 */
4168VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
4169{
4170 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
4171}
4172
4173
4174/**
4175 * Transforms the guest CPU state to raw-ring mode.
4176 *
4177 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
4178 *
4179 * @returns VBox status. (recompiler failure)
4180 * @param pVCpu Pointer to the VMCPU.
4181 * @param pCtxCore The context core (for trap usage).
4182 * @see @ref pg_raw
4183 */
4184VMMR3DECL(int) CPUMR3RawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
4185{
4186 PVM pVM = pVCpu->CTX_SUFF(pVM);
4187
4188 Assert(!pVCpu->cpum.s.fRawEntered);
4189 Assert(!pVCpu->cpum.s.fRemEntered);
4190 if (!pCtxCore)
4191 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
4192
4193 /*
4194 * Are we in Ring-0?
4195 */
4196 if ( pCtxCore->ss.Sel && (pCtxCore->ss.Sel & X86_SEL_RPL) == 0
4197 && !pCtxCore->eflags.Bits.u1VM)
4198 {
4199 /*
4200 * Enter execution mode.
4201 */
4202 PATMRawEnter(pVM, pCtxCore);
4203
4204 /*
4205 * Set CPL to Ring-1.
4206 */
4207 pCtxCore->ss.Sel |= 1;
4208 if (pCtxCore->cs.Sel && (pCtxCore->cs.Sel & X86_SEL_RPL) == 0)
4209 pCtxCore->cs.Sel |= 1;
4210 }
4211 else
4212 {
4213 AssertMsg((pCtxCore->ss.Sel & X86_SEL_RPL) >= 2 || pCtxCore->eflags.Bits.u1VM,
4214 ("ring-1 code not supported\n"));
4215 /*
4216 * PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
4217 */
4218 PATMRawEnter(pVM, pCtxCore);
4219 }
4220
4221 /*
4222 * Assert sanity.
4223 */
4224 AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
4225 AssertReleaseMsg( pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss.Sel & X86_SEL_RPL)
4226 || pCtxCore->eflags.Bits.u1VM,
4227 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
4228 Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP));
4229
4230 pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */
4231
4232 pVCpu->cpum.s.fRawEntered = true;
4233 return VINF_SUCCESS;
4234}
4235
4236
4237/**
4238 * Transforms the guest CPU state from raw-ring mode to correct values.
4239 *
4240 * This function will change any selector registers with DPL=1 to DPL=0.
4241 *
4242 * @returns Adjusted rc.
4243 * @param pVCpu Pointer to the VMCPU.
4244 * @param rc Raw mode return code
4245 * @param pCtxCore The context core (for trap usage).
4246 * @see @ref pg_raw
4247 */
4248VMMR3DECL(int) CPUMR3RawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
4249{
4250 PVM pVM = pVCpu->CTX_SUFF(pVM);
4251
4252 /*
4253 * Don't leave if we've already left (in GC).
4254 */
4255 Assert(pVCpu->cpum.s.fRawEntered);
4256 Assert(!pVCpu->cpum.s.fRemEntered);
4257 if (!pVCpu->cpum.s.fRawEntered)
4258 return rc;
4259 pVCpu->cpum.s.fRawEntered = false;
4260
4261 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4262 if (!pCtxCore)
4263 pCtxCore = CPUMCTX2CORE(pCtx);
4264 Assert(pCtxCore->eflags.Bits.u1VM || (pCtxCore->ss.Sel & X86_SEL_RPL));
4265 AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss.Sel & X86_SEL_RPL),
4266 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
4267
4268 /*
4269 * Are we executing in raw ring-1?
4270 */
4271 if ( (pCtxCore->ss.Sel & X86_SEL_RPL) == 1
4272 && !pCtxCore->eflags.Bits.u1VM)
4273 {
4274 /*
4275 * Leave execution mode.
4276 */
4277 PATMRawLeave(pVM, pCtxCore, rc);
4278 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
4279 /** @todo See what happens if we remove this. */
4280 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
4281 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
4282 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
4283 pCtxCore->es.Sel &= ~X86_SEL_RPL;
4284 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
4285 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
4286 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
4287 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
4288
4289 /*
4290 * Ring-1 selector => Ring-0.
4291 */
4292 pCtxCore->ss.Sel &= ~X86_SEL_RPL;
4293 if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
4294 pCtxCore->cs.Sel &= ~X86_SEL_RPL;
4295 }
4296 else
4297 {
4298 /*
4299 * PATM is taking care of the IOPL and IF flags for us.
4300 */
4301 PATMRawLeave(pVM, pCtxCore, rc);
4302 if (!pCtxCore->eflags.Bits.u1VM)
4303 {
4304 /** @todo See what happens if we remove this. */
4305 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
4306 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
4307 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
4308 pCtxCore->es.Sel &= ~X86_SEL_RPL;
4309 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
4310 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
4311 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
4312 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
4313 }
4314 }
4315
4316 return rc;
4317}
4318
4319
4320/**
4321 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
4322 *
4323 * Only REM should ever call this function!
4324 *
4325 * @returns The changed flags.
4326 * @param pVCpu Pointer to the VMCPU.
4327 * @param puCpl Where to return the current privilege level (CPL).
4328 */
4329VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
4330{
4331 Assert(!pVCpu->cpum.s.fRawEntered);
4332 Assert(!pVCpu->cpum.s.fRemEntered);
4333
4334 /*
4335 * Get the CPL first.
4336 */
4337 *puCpl = CPUMGetGuestCPL(pVCpu);
4338
4339 /*
4340 * Get and reset the flags.
4341 */
4342 uint32_t fFlags = pVCpu->cpum.s.fChanged;
4343 pVCpu->cpum.s.fChanged = 0;
4344
4345 /** @todo change the switcher to use the fChanged flags. */
4346 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
4347 {
4348 fFlags |= CPUM_CHANGED_FPU_REM;
4349 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
4350 }
4351
4352 pVCpu->cpum.s.fRemEntered = true;
4353 return fFlags;
4354}
4355
4356
4357/**
4358 * Leaves REM.
4359 *
4360 * @param pVCpu Pointer to the VMCPU.
4361 * @param fNoOutOfSyncSels This is @c false if there are out of sync
4362 * registers.
4363 */
4364VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
4365{
4366 Assert(!pVCpu->cpum.s.fRawEntered);
4367 Assert(pVCpu->cpum.s.fRemEntered);
4368
4369 pVCpu->cpum.s.fRemEntered = false;
4370}
4371
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