CPUM.cpp@ 38838

Last change on this file since 38838 was 37136, checked in by vboxsync, 14 years ago
CPUM: Option to set Hypervisor Present bit.
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1	/* $Id: CPUM.cpp 37136 2011-05-18 14:45:47Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*/
33
34	/*******************************************************************************
35	* Header Files *
36	*******************************************************************************/
37	#define LOG_GROUP LOG_GROUP_CPUM
38	#include <VBox/vmm/cpum.h>
39	#include <VBox/vmm/cpumdis.h>
40	#include <VBox/vmm/pgm.h>
41	#include <VBox/vmm/mm.h>
42	#include <VBox/vmm/selm.h>
43	#include <VBox/vmm/dbgf.h>
44	#include <VBox/vmm/patm.h>
45	#include <VBox/vmm/hwaccm.h>
46	#include <VBox/vmm/ssm.h>
47	#include "CPUMInternal.h"
48	#include <VBox/vmm/vm.h>
49
50	#include <VBox/param.h>
51	#include <VBox/dis.h>
52	#include <VBox/err.h>
53	#include <VBox/log.h>
54	#include <iprt/assert.h>
55	#include <iprt/asm-amd64-x86.h>
56	#include <iprt/string.h>
57	#include <iprt/mp.h>
58	#include <iprt/cpuset.h>
59	#include "internal/pgm.h"
60
61
62	/*******************************************************************************
63	* Defined Constants And Macros *
64	*******************************************************************************/
65	/** The current saved state version. */
66	#define CPUM_SAVED_STATE_VERSION 12
67	/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
68	* selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
69	#define CPUM_SAVED_STATE_VERSION_VER3_2 11
70	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
71	* changes. */
72	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
73	/** The saved state version for the 2.1 trunk before the MSR changes. */
74	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
75	/** The saved state version of 2.0, used for backwards compatibility. */
76	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
77	/** The saved state version of 1.6, used for backwards compatibility. */
78	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
79
80
81	/*******************************************************************************
82	* Structures and Typedefs *
83	*******************************************************************************/
84
85	/**
86	* What kind of cpu info dump to perform.
87	*/
88	typedef enum CPUMDUMPTYPE
89	{
90	CPUMDUMPTYPE_TERSE,
91	CPUMDUMPTYPE_DEFAULT,
92	CPUMDUMPTYPE_VERBOSE
93	} CPUMDUMPTYPE;
94	/** Pointer to a cpu info dump type. */
95	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
96
97
98	/*******************************************************************************
99	* Internal Functions *
100	*******************************************************************************/
101	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
102	static int cpumR3CpuIdInit(PVM pVM);
103	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
104	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
105	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
106	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
107	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
108	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
112	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
113	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
114
115
116	/**
117	* Initializes the CPUM.
118	*
119	* @returns VBox status code.
120	* @param pVM The VM to operate on.
121	*/
122	VMMR3DECL(int) CPUMR3Init(PVM pVM)
123	{
124	LogFlow(("CPUMR3Init\n"));
125
126	/*
127	* Assert alignment and sizes.
128	*/
129	AssertCompileMemberAlignment(VM, cpum.s, 32);
130	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
131	AssertCompileSizeAlignment(CPUMCTX, 64);
132	AssertCompileSizeAlignment(CPUMCTXMSR, 64);
133	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
134	AssertCompileMemberAlignment(VM, cpum, 64);
135	AssertCompileMemberAlignment(VM, aCpus, 64);
136	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
137	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
138
139	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
140	pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
141	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
142
143	/* Calculate the offset from CPUMCPU to CPUM. */
144	for (VMCPUID i = 0; i < pVM->cCpus; i++)
145	{
146	PVMCPU pVCpu = &pVM->aCpus[i];
147
148	/*
149	* Setup any fixed pointers and offsets.
150	*/
151	pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
152	pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
153
154	pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
155	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
156	}
157
158	/*
159	* Check that the CPU supports the minimum features we require.
160	*/
161	if (!ASMHasCpuId())
162	{
163	Log(("The CPU doesn't support CPUID!\n"));
164	return VERR_UNSUPPORTED_CPU;
165	}
166	ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
167	ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
168
169	/* Setup the CR4 AND and OR masks used in the switcher */
170	/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
171	if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
172	{
173	Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
174	/* No FXSAVE implies no SSE */
175	pVM->cpum.s.CR4.AndMask = X86_CR4_PVI \| X86_CR4_VME;
176	pVM->cpum.s.CR4.OrMask = 0;
177	}
178	else
179	{
180	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
181	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
182	}
183
184	if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
185	{
186	Log(("The CPU doesn't support MMX!\n"));
187	return VERR_UNSUPPORTED_CPU;
188	}
189	if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
190	{
191	Log(("The CPU doesn't support TSC!\n"));
192	return VERR_UNSUPPORTED_CPU;
193	}
194	/* Bogus on AMD? */
195	if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
196	Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
197
198	/*
199	* Detect the host CPU vendor.
200	* (The guest CPU vendor is re-detected later on.)
201	*/
202	uint32_t uEAX, uEBX, uECX, uEDX;
203	ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
204	pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
205	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
206
207	/*
208	* Setup hypervisor startup values.
209	*/
210
211	/*
212	* Register saved state data item.
213	*/
214	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
215	NULL, cpumR3LiveExec, NULL,
216	NULL, cpumR3SaveExec, NULL,
217	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
218	if (RT_FAILURE(rc))
219	return rc;
220
221	/*
222	* Register info handlers and registers with the debugger facility.
223	*/
224	DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
225	DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
226	DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
227	DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
228	DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
229	DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
230
231	rc = cpumR3DbgInit(pVM);
232	if (RT_FAILURE(rc))
233	return rc;
234
235	/*
236	* Initialize the Guest CPUID state.
237	*/
238	rc = cpumR3CpuIdInit(pVM);
239	if (RT_FAILURE(rc))
240	return rc;
241	CPUMR3Reset(pVM);
242	return VINF_SUCCESS;
243	}
244
245
246	/**
247	* Detect the CPU vendor give n the
248	*
249	* @returns The vendor.
250	* @param uEAX EAX from CPUID(0).
251	* @param uEBX EBX from CPUID(0).
252	* @param uECX ECX from CPUID(0).
253	* @param uEDX EDX from CPUID(0).
254	*/
255	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
256	{
257	if ( uEAX >= 1
258	&& uEBX == X86_CPUID_VENDOR_AMD_EBX
259	&& uECX == X86_CPUID_VENDOR_AMD_ECX
260	&& uEDX == X86_CPUID_VENDOR_AMD_EDX)
261	return CPUMCPUVENDOR_AMD;
262
263	if ( uEAX >= 1
264	&& uEBX == X86_CPUID_VENDOR_INTEL_EBX
265	&& uECX == X86_CPUID_VENDOR_INTEL_ECX
266	&& uEDX == X86_CPUID_VENDOR_INTEL_EDX)
267	return CPUMCPUVENDOR_INTEL;
268
269	/** @todo detect the other buggers... */
270	return CPUMCPUVENDOR_UNKNOWN;
271	}
272
273
274	/**
275	* Fetches overrides for a CPUID leaf.
276	*
277	* @returns VBox status code.
278	* @param pLeaf The leaf to load the overrides into.
279	* @param pCfgNode The CFGM node containing the overrides
280	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
281	* @param iLeaf The CPUID leaf number.
282	*/
283	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
284	{
285	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
286	if (pLeafNode)
287	{
288	uint32_t u32;
289	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
290	if (RT_SUCCESS(rc))
291	pLeaf->eax = u32;
292	else
293	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
294
295	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
296	if (RT_SUCCESS(rc))
297	pLeaf->ebx = u32;
298	else
299	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
300
301	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
302	if (RT_SUCCESS(rc))
303	pLeaf->ecx = u32;
304	else
305	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
306
307	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
308	if (RT_SUCCESS(rc))
309	pLeaf->edx = u32;
310	else
311	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
312
313	}
314	return VINF_SUCCESS;
315	}
316
317
318	/**
319	* Load the overrides for a set of CPUID leaves.
320	*
321	* @returns VBox status code.
322	* @param paLeaves The leaf array.
323	* @param cLeaves The number of leaves.
324	* @param uStart The start leaf number.
325	* @param pCfgNode The CFGM node containing the overrides
326	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
327	*/
328	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
329	{
330	for (uint32_t i = 0; i < cLeaves; i++)
331	{
332	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
333	if (RT_FAILURE(rc))
334	return rc;
335	}
336
337	return VINF_SUCCESS;
338	}
339
340	/**
341	* Init a set of host CPUID leaves.
342	*
343	* @returns VBox status code.
344	* @param paLeaves The leaf array.
345	* @param cLeaves The number of leaves.
346	* @param uStart The start leaf number.
347	* @param pCfgNode The /CPUM/HostCPUID/ node.
348	*/
349	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
350	{
351	/* Using the ECX variant for all of them can't hurt... */
352	for (uint32_t i = 0; i < cLeaves; i++)
353	ASMCpuId_Idx_ECX(uStart + i, 0, &paLeaves[i].eax, &paLeaves[i].ebx, &paLeaves[i].ecx, &paLeaves[i].edx);
354
355	/* Load CPUID leaf override; we currently don't care if the user
356	specifies features the host CPU doesn't support. */
357	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
358	}
359
360
361	/**
362	* Initializes the emulated CPU's cpuid information.
363	*
364	* @returns VBox status code.
365	* @param pVM The VM to operate on.
366	*/
367	static int cpumR3CpuIdInit(PVM pVM)
368	{
369	PCPUM pCPUM = &pVM->cpum.s;
370	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
371	uint32_t i;
372	int rc;
373
374	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, LeafSuffReg, FeatNm, fMask, uValue) \
375	if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fMask)) == (uValue) ) \
376	{ \
377	LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: %#x -> 0\n", pCPUM->aGuestCpuId##LeafSuffReg & (fMask))); \
378	pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fMask); \
379	}
380	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, LeafSuffReg, FeatNm, fBitMask) \
381	if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fBitMask)) ) \
382	{ \
383	LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: 1 -> 0\n")); \
384	pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fBitMask); \
385	}
386
387	/*
388	* Read the configuration.
389	*/
390	/** @cfgm{CPUM/SyntheticCpu, boolean, false}
391	* Enables the Synthetic CPU. The Vendor ID and Processor Name are
392	* completely overridden by VirtualBox custom strings. Some
393	* CPUID information is withheld, like the cache info. */
394	rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false);
395	AssertRCReturn(rc, rc);
396
397	/** @cfgm{CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
398	* When non-zero CPUID features that could cause portability issues will be
399	* stripped. The higher the value the more features gets stripped. Higher
400	* values should only be used when older CPUs are involved since it may
401	* harm performance and maybe also cause problems with specific guests. */
402	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, 0);
403	AssertRCReturn(rc, rc);
404
405	AssertLogRelReturn(!pCPUM->fSyntheticCpu \|\| !pCPUM->u8PortableCpuIdLevel, VERR_INTERNAL_ERROR_2);
406
407	/*
408	* Get the host CPUID leaves and redetect the guest CPU vendor (could've
409	* been overridden).
410	*/
411	/** @cfgm{CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
412	* Overrides the host CPUID leaf values used for calculating the guest CPUID
413	* leaves. This can be used to preserve the CPUID values when moving a VM
414	* to a different machine. Another use is restricting (or extending) the
415	* feature set exposed to the guest. */
416	PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
417	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
418	AssertRCReturn(rc, rc);
419	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
420	AssertRCReturn(rc, rc);
421	rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
422	AssertRCReturn(rc, rc);
423
424	pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
425	pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
426
427	/*
428	* Determine the default leaf.
429	*
430	* Intel returns values of the highest standard function, while AMD
431	* returns zeros. VIA on the other hand seems to returning nothing or
432	* perhaps some random garbage, we don't try to duplicate this behavior.
433	*/
434	ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10, /** @todo r=bird: Use the host value here in case of overrides and more than 10 leaves being stripped already. */
435	&pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
436	&pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
437
438
439	/* Cpuid 1 & 0x80000001:
440	* Only report features we can support.
441	*
442	* Note! When enabling new features the Synthetic CPU and Portable CPUID
443	* options may require adjusting (i.e. stripping what was enabled).
444	*/
445	pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
446	\| X86_CPUID_FEATURE_EDX_VME
447	\| X86_CPUID_FEATURE_EDX_DE
448	\| X86_CPUID_FEATURE_EDX_PSE
449	\| X86_CPUID_FEATURE_EDX_TSC
450	\| X86_CPUID_FEATURE_EDX_MSR
451	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
452	\| X86_CPUID_FEATURE_EDX_MCE
453	\| X86_CPUID_FEATURE_EDX_CX8
454	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
455	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
456	//\| X86_CPUID_FEATURE_EDX_SEP
457	\| X86_CPUID_FEATURE_EDX_MTRR
458	\| X86_CPUID_FEATURE_EDX_PGE
459	\| X86_CPUID_FEATURE_EDX_MCA
460	\| X86_CPUID_FEATURE_EDX_CMOV
461	\| X86_CPUID_FEATURE_EDX_PAT
462	\| X86_CPUID_FEATURE_EDX_PSE36
463	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
464	\| X86_CPUID_FEATURE_EDX_CLFSH
465	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
466	//\| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
467	\| X86_CPUID_FEATURE_EDX_MMX
468	\| X86_CPUID_FEATURE_EDX_FXSR
469	\| X86_CPUID_FEATURE_EDX_SSE
470	\| X86_CPUID_FEATURE_EDX_SSE2
471	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
472	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
473	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
474	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
475	\| 0;
476	pCPUM->aGuestCpuIdStd[1].ecx &= 0
477	\| X86_CPUID_FEATURE_ECX_SSE3
478	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
479	\| ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
480	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
481	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
482	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
483	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
484	\| X86_CPUID_FEATURE_ECX_SSSE3
485	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
486	//\| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
487	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
488	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
489	/* ECX Bit 21 - x2APIC support - not yet. */
490	// \| X86_CPUID_FEATURE_ECX_X2APIC
491	/* ECX Bit 23 - POPCNT instruction. */
492	//\| X86_CPUID_FEATURE_ECX_POPCNT
493	\| 0;
494	if (pCPUM->u8PortableCpuIdLevel > 0)
495	{
496	PORTABLE_CLEAR_BITS_WHEN(1, Std[1].eax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
497	PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
498	PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
499	PORTABLE_DISABLE_FEATURE_BIT(2, Std[1].edx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
500	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, SSE, X86_CPUID_FEATURE_EDX_SSE);
501	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
502	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
503
504	Assert(!(pCPUM->aGuestCpuIdStd[1].edx & ( X86_CPUID_FEATURE_EDX_SEP
505	\| X86_CPUID_FEATURE_EDX_PSN
506	\| X86_CPUID_FEATURE_EDX_DS
507	\| X86_CPUID_FEATURE_EDX_ACPI
508	\| X86_CPUID_FEATURE_EDX_SS
509	\| X86_CPUID_FEATURE_EDX_TM
510	\| X86_CPUID_FEATURE_EDX_PBE
511	)));
512	Assert(!(pCPUM->aGuestCpuIdStd[1].ecx & ( X86_CPUID_FEATURE_ECX_PCLMUL
513	\| X86_CPUID_FEATURE_ECX_DTES64
514	\| X86_CPUID_FEATURE_ECX_CPLDS
515	\| X86_CPUID_FEATURE_ECX_VMX
516	\| X86_CPUID_FEATURE_ECX_SMX
517	\| X86_CPUID_FEATURE_ECX_EST
518	\| X86_CPUID_FEATURE_ECX_TM2
519	\| X86_CPUID_FEATURE_ECX_CNTXID
520	\| X86_CPUID_FEATURE_ECX_FMA
521	\| X86_CPUID_FEATURE_ECX_CX16
522	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
523	\| X86_CPUID_FEATURE_ECX_PDCM
524	\| X86_CPUID_FEATURE_ECX_DCA
525	\| X86_CPUID_FEATURE_ECX_MOVBE
526	\| X86_CPUID_FEATURE_ECX_AES
527	\| X86_CPUID_FEATURE_ECX_POPCNT
528	\| X86_CPUID_FEATURE_ECX_XSAVE
529	\| X86_CPUID_FEATURE_ECX_OSXSAVE
530	\| X86_CPUID_FEATURE_ECX_AVX
531	)));
532	}
533
534	/* Cpuid 0x80000001:
535	* Only report features we can support.
536	*
537	* Note! When enabling new features the Synthetic CPU and Portable CPUID
538	* options may require adjusting (i.e. stripping what was enabled).
539	*
540	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
541	*/
542	pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
543	\| X86_CPUID_AMD_FEATURE_EDX_VME
544	\| X86_CPUID_AMD_FEATURE_EDX_DE
545	\| X86_CPUID_AMD_FEATURE_EDX_PSE
546	\| X86_CPUID_AMD_FEATURE_EDX_TSC
547	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
548	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
549	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
550	\| X86_CPUID_AMD_FEATURE_EDX_CX8
551	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
552	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
553	//\| X86_CPUID_AMD_FEATURE_EDX_SEP
554	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
555	\| X86_CPUID_AMD_FEATURE_EDX_PGE
556	\| X86_CPUID_AMD_FEATURE_EDX_MCA
557	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
558	\| X86_CPUID_AMD_FEATURE_EDX_PAT
559	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
560	//\| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
561	//\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
562	\| X86_CPUID_AMD_FEATURE_EDX_MMX
563	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
564	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
565	//\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
566	//\| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
567	//\| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
568	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
569	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
570	\| 0;
571	pCPUM->aGuestCpuIdExt[1].ecx &= 0
572	//\| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
573	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL
574	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
575	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
576	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
577	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
578	//\| X86_CPUID_AMD_FEATURE_ECX_ABM
579	//\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
580	//\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
581	//\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
582	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
583	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
584	//\| X86_CPUID_AMD_FEATURE_ECX_SSE5
585	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
586	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
587	\| 0;
588	if (pCPUM->u8PortableCpuIdLevel > 0)
589	{
590	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].ecx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
591	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
592	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
593	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
594	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, RDTSCP, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
595	PORTABLE_DISABLE_FEATURE_BIT(2, Ext[1].ecx, LAHF_SAHF, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
596	PORTABLE_DISABLE_FEATURE_BIT(3, Ext[1].ecx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
597
598	Assert(!(pCPUM->aGuestCpuIdExt[1].ecx & ( X86_CPUID_AMD_FEATURE_ECX_CMPL
599	\| X86_CPUID_AMD_FEATURE_ECX_SVM
600	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
601	\| X86_CPUID_AMD_FEATURE_ECX_CR8L
602	\| X86_CPUID_AMD_FEATURE_ECX_ABM
603	\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
604	\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
605	\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
606	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
607	\| X86_CPUID_AMD_FEATURE_ECX_IBS
608	\| X86_CPUID_AMD_FEATURE_ECX_SSE5
609	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
610	\| X86_CPUID_AMD_FEATURE_ECX_WDT
611	\| UINT32_C(0xffffc000)
612	)));
613	Assert(!(pCPUM->aGuestCpuIdExt[1].edx & ( RT_BIT(10)
614	\| X86_CPUID_AMD_FEATURE_EDX_SEP
615	\| RT_BIT(18)
616	\| RT_BIT(19)
617	\| RT_BIT(21)
618	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
619	\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
620	\| RT_BIT(28)
621	)));
622	}
623
624	/*
625	* Apply the Synthetic CPU modifications. (TODO: move this up)
626	*/
627	if (pCPUM->fSyntheticCpu)
628	{
629	static const char s_szVendor[13] = "VirtualBox ";
630	static const char s_szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
631
632	pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
633
634	/* Limit the nr of standard leaves; 5 for monitor/mwait */
635	pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
636
637	/* 0: Vendor */
638	pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)s_szVendor)[0];
639	pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)s_szVendor)[2];
640	pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)s_szVendor)[1];
641
642	/* 1.eax: Version information. family : model : stepping */
643	pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
644
645	/* Leaves 2 - 4 are Intel only - zero them out */
646	memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
647	memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
648	memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
649
650	/* Leaf 5 = monitor/mwait */
651
652	/* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
653	pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
654	/* AMD only - set to zero. */
655	pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
656
657	/* 0x800000001: AMD only; shared feature bits are set dynamically. */
658	memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
659
660	/* 0x800000002-4: Processor Name String Identifier. */
661	pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)s_szProcessor)[0];
662	pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)s_szProcessor)[1];
663	pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)s_szProcessor)[2];
664	pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)s_szProcessor)[3];
665	pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)s_szProcessor)[4];
666	pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)s_szProcessor)[5];
667	pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)s_szProcessor)[6];
668	pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)s_szProcessor)[7];
669	pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)s_szProcessor)[8];
670	pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)s_szProcessor)[9];
671	pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)s_szProcessor)[10];
672	pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)s_szProcessor)[11];
673
674	/* 0x800000005-7 - reserved -> zero */
675	memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
676	memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
677	memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
678
679	/* 0x800000008: only the max virtual and physical address size. */
680	pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
681	}
682
683	/*
684	* Hide HTT, multicode, SMP, whatever.
685	* (APIC-ID := 0 and #LogCpus := 0)
686	*/
687	pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
688	#ifdef VBOX_WITH_MULTI_CORE
689	if ( pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
690	&& pVM->cCpus > 1)
691	{
692	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
693	pCPUM->aGuestCpuIdStd[1].ebx \|= (pVM->cCpus << 16);
694	pCPUM->aGuestCpuIdStd[1].edx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
695	}
696	#endif
697
698	/* Cpuid 2:
699	* Intel: Cache and TLB information
700	* AMD: Reserved
701	* Safe to expose; restrict the number of calls to 1 for the portable case.
702	*/
703	if ( pCPUM->u8PortableCpuIdLevel > 0
704	&& pCPUM->aGuestCpuIdStd[0].eax >= 2
705	&& (pCPUM->aGuestCpuIdStd[2].eax & 0xff) > 1)
706	{
707	LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCPUM->aGuestCpuIdStd[2].eax & 0xff));
708	pCPUM->aGuestCpuIdStd[2].eax &= UINT32_C(0xfffffffe);
709	}
710
711	/* Cpuid 3:
712	* Intel: EAX, EBX - reserved (transmeta uses these)
713	* ECX, EDX - Processor Serial Number if available, otherwise reserved
714	* AMD: Reserved
715	* Safe to expose
716	*/
717	if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
718	{
719	pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
720	if (pCPUM->u8PortableCpuIdLevel > 0)
721	pCPUM->aGuestCpuIdStd[3].eax = pCPUM->aGuestCpuIdStd[3].ebx = 0;
722	}
723
724	/* Cpuid 4:
725	* Intel: Deterministic Cache Parameters Leaf
726	* Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
727	* AMD: Reserved
728	* Safe to expose, except for EAX:
729	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
730	* Bits 31-26: Maximum number of processor cores in this physical package**
731	* Note: These SMP values are constant regardless of ECX
732	*/
733	pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
734	pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
735	#ifdef VBOX_WITH_MULTI_CORE
736	if ( pVM->cCpus > 1
737	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
738	{
739	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
740	/* One logical processor with possibly multiple cores. */
741	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
742	pCPUM->aGuestCpuIdStd[4].eax \|= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
743	}
744	#endif
745
746	/* Cpuid 5: Monitor/mwait Leaf
747	* Intel: ECX, EDX - reserved
748	* EAX, EBX - Smallest and largest monitor line size
749	* AMD: EDX - reserved
750	* EAX, EBX - Smallest and largest monitor line size
751	* ECX - extensions (ignored for now)
752	* Safe to expose
753	*/
754	if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
755	pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
756
757	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
758	/** @cfgm{/CPUM/MWaitExtensions, boolean, false}
759	* Expose MWAIT extended features to the guest. For now we expose
760	* just MWAIT break on interrupt feature (bit 1).
761	*/
762	bool fMWaitExtensions;
763	rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
764	if (fMWaitExtensions)
765	{
766	pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
767	/* @todo: for now we just expose host's MWAIT C-states, although conceptually
768	it shall be part of our power management virtualization model */
769	#if 0
770	/* MWAIT sub C-states */
771	pCPUM->aGuestCpuIdStd[5].edx =
772	(0 << 0) /* 0 in C0 */ \|
773	(2 << 4) /* 2 in C1 */ \|
774	(2 << 8) /* 2 in C2 */ \|
775	(2 << 12) /* 2 in C3 */ \|
776	(0 << 16) /* 0 in C4 */
777	;
778	#endif
779	}
780	else
781	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
782
783	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
784	* Safe to pass on to the guest.
785	*
786	* Intel: 0x800000005 reserved
787	* 0x800000006 L2 cache information
788	* AMD: 0x800000005 L1 cache information
789	* 0x800000006 L2/L3 cache information
790	*/
791
792	/* Cpuid 0x800000007:
793	* AMD: EAX, EBX, ECX - reserved
794	* EDX: Advanced Power Management Information
795	* Intel: Reserved
796	*/
797	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
798	{
799	Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
800
801	pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
802
803	if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
804	{
805	/* Only expose the TSC invariant capability bit to the guest. */
806	pCPUM->aGuestCpuIdExt[7].edx &= 0
807	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
808	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
809	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
810	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
811	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
812	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
813	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
814	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
815	#if 0 /* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
816	* Linux kernels blindly assume that the AMD performance counters work
817	* if this is set for 64 bits guests. (Can't really find a CPUID feature
818	* bit for them though.) */
819	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
820	#endif
821	\| 0;
822	}
823	else
824	pCPUM->aGuestCpuIdExt[7].edx = 0;
825	}
826
827	/* Cpuid 0x800000008:
828	* AMD: EBX, EDX - reserved
829	* EAX: Virtual/Physical/Guest address Size
830	* ECX: Number of cores + APICIdCoreIdSize
831	* Intel: EAX: Virtual/Physical address Size
832	* EBX, ECX, EDX - reserved
833	*/
834	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
835	{
836	/* Only expose the virtual and physical address sizes to the guest. */
837	pCPUM->aGuestCpuIdExt[8].eax &= UINT32_C(0x0000ffff);
838	pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
839	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
840	* NC (0-7) Number of cores; 0 equals 1 core */
841	pCPUM->aGuestCpuIdExt[8].ecx = 0;
842	#ifdef VBOX_WITH_MULTI_CORE
843	if ( pVM->cCpus > 1
844	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
845	{
846	/* Legacy method to determine the number of cores. */
847	pCPUM->aGuestCpuIdExt[1].ecx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL;
848	pCPUM->aGuestCpuIdExt[8].ecx \|= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
849	}
850	#endif
851	}
852
853	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
854	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
855	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
856	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
857	*/
858	bool fNt4LeafLimit;
859	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
860	if (fNt4LeafLimit)
861	pCPUM->aGuestCpuIdStd[0].eax = 3; /** @todo r=bird: shouldn't we check if pCPUM->aGuestCpuIdStd[0].eax > 3 before setting it 3 here? */
862
863	/*
864	* Limit it the number of entries and fill the remaining with the defaults.
865	*
866	* The limits are masking off stuff about power saving and similar, this
867	* is perhaps a bit crudely done as there is probably some relatively harmless
868	* info too in these leaves (like words about having a constant TSC).
869	*/
870	if (pCPUM->aGuestCpuIdStd[0].eax > 5)
871	pCPUM->aGuestCpuIdStd[0].eax = 5;
872	for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
873	pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
874
875	if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
876	pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
877	for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
878	? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
879	: 0;
880	i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
881	i++)
882	pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
883
884	/*
885	* Centaur stuff (VIA).
886	*
887	* The important part here (we think) is to make sure the 0xc0000000
888	* function returns 0xc0000001. As for the features, we don't currently
889	* let on about any of those... 0xc0000002 seems to be some
890	* temperature/hz/++ stuff, include it as well (static).
891	*/
892	if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
893	&& pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
894	{
895	pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
896	pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
897	for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
898	i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
899	i++)
900	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
901	}
902	else
903	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
904	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
905
906
907	/*
908	* Load CPUID overrides from configuration.
909	* Note: Kind of redundant now, but allows unchanged overrides
910	*/
911	/** @cfgm{CPUM/CPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
912	* Overrides the CPUID leaf values. */
913	PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
914	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
915	AssertRCReturn(rc, rc);
916	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
917	AssertRCReturn(rc, rc);
918	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
919	AssertRCReturn(rc, rc);
920
921	/*
922	* Check if PAE was explicitely enabled by the user.
923	*/
924	bool fEnable;
925	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
926	if (fEnable)
927	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
928
929	/*
930	* We don't normally enable NX for raw-mode, so give the user a chance to
931	* force it on.
932	*/
933	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false); AssertRCReturn(rc, rc);
934	if (fEnable)
935	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
936
937	/*
938	* We don't enable the Hypervisor Present bit by default, but it may
939	* be needed by some guests.
940	*/
941	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false); AssertRCReturn(rc, rc);
942	if (fEnable)
943	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
944	/*
945	* Log the cpuid and we're good.
946	*/
947	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
948	RTCPUSET OnlineSet;
949	LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
950	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
951	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
952	LogRel(("*********************** CPUID dump **********************\n"));
953	DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
954	LogRel(("\n"));
955	DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
956	RTLogRelSetBuffering(fOldBuffered);
957	LogRel(("****************** End of CPUID dump ********************\n"));
958
959	#undef PORTABLE_DISABLE_FEATURE_BIT
960	#undef PORTABLE_CLEAR_BITS_WHEN
961
962	return VINF_SUCCESS;
963	}
964
965
966	/**
967	* Applies relocations to data and code managed by this
968	* component. This function will be called at init and
969	* whenever the VMM need to relocate it self inside the GC.
970	*
971	* The CPUM will update the addresses used by the switcher.
972	*
973	* @param pVM The VM.
974	*/
975	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
976	{
977	LogFlow(("CPUMR3Relocate\n"));
978	for (VMCPUID i = 0; i < pVM->cCpus; i++)
979	{
980	/*
981	* Switcher pointers.
982	*/
983	PVMCPU pVCpu = &pVM->aCpus[i];
984	pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
985	Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
986
987	}
988	}
989
990
991	/**
992	* Apply late CPUM property changes based on the fHWVirtEx setting
993	*
994	* @param pVM The VM to operate on.
995	* @param fHWVirtExEnabled HWVirtEx enabled/disabled
996	*/
997	VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
998	{
999	/*
1000	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
1001	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1002	* of processors from (cpuid(4).eax >> 26) + 1.
1003	*
1004	* Note: this code is obsolete, but let's keep it here for reference.
1005	* Purpose is valid when we artificially cap the max std id to less than 4.
1006	*/
1007	if (!fHWVirtExEnabled)
1008	{
1009	Assert( pVM->cpum.s.aGuestCpuIdStd[4].eax == 0
1010	\|\| pVM->cpum.s.aGuestCpuIdStd[0].eax < 0x4);
1011	pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
1012	}
1013	}
1014
1015	/**
1016	* Terminates the CPUM.
1017	*
1018	* Termination means cleaning up and freeing all resources,
1019	* the VM it self is at this point powered off or suspended.
1020	*
1021	* @returns VBox status code.
1022	* @param pVM The VM to operate on.
1023	*/
1024	VMMR3DECL(int) CPUMR3Term(PVM pVM)
1025	{
1026	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1027	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1028	{
1029	PVMCPU pVCpu = &pVM->aCpus[i];
1030	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1031
1032	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1033	pVCpu->cpum.s.uMagic = 0;
1034	pCtx->dr[5] = 0;
1035	}
1036	#endif
1037	return 0;
1038	}
1039
1040
1041	/**
1042	* Resets a virtual CPU.
1043	*
1044	* Used by CPUMR3Reset and CPU hot plugging.
1045	*
1046	* @param pVCpu The virtual CPU handle.
1047	*/
1048	VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
1049	{
1050	/** @todo anything different for VCPU > 0? */
1051	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1052
1053	/*
1054	* Initialize everything to ZERO first.
1055	*/
1056	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1057	memset(pCtx, 0, sizeof(*pCtx));
1058	pVCpu->cpum.s.fUseFlags = fUseFlags;
1059
1060	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
1061	pCtx->eip = 0x0000fff0;
1062	pCtx->edx = 0x00000600; /* P6 processor */
1063	pCtx->eflags.Bits.u1Reserved0 = 1;
1064
1065	pCtx->cs = 0xf000;
1066	pCtx->csHid.u64Base = UINT64_C(0xffff0000);
1067	pCtx->csHid.u32Limit = 0x0000ffff;
1068	pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
1069	pCtx->csHid.Attr.n.u1Present = 1;
1070	pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ \| X86_SEL_TYPE_CODE;
1071
1072	pCtx->dsHid.u32Limit = 0x0000ffff;
1073	pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
1074	pCtx->dsHid.Attr.n.u1Present = 1;
1075	pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1076
1077	pCtx->esHid.u32Limit = 0x0000ffff;
1078	pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
1079	pCtx->esHid.Attr.n.u1Present = 1;
1080	pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1081
1082	pCtx->fsHid.u32Limit = 0x0000ffff;
1083	pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
1084	pCtx->fsHid.Attr.n.u1Present = 1;
1085	pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1086
1087	pCtx->gsHid.u32Limit = 0x0000ffff;
1088	pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
1089	pCtx->gsHid.Attr.n.u1Present = 1;
1090	pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1091
1092	pCtx->ssHid.u32Limit = 0x0000ffff;
1093	pCtx->ssHid.Attr.n.u1Present = 1;
1094	pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
1095	pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1096
1097	pCtx->idtr.cbIdt = 0xffff;
1098	pCtx->gdtr.cbGdt = 0xffff;
1099
1100	pCtx->ldtrHid.u32Limit = 0xffff;
1101	pCtx->ldtrHid.Attr.n.u1Present = 1;
1102	pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1103
1104	pCtx->trHid.u32Limit = 0xffff;
1105	pCtx->trHid.Attr.n.u1Present = 1;
1106	pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1107
1108	pCtx->dr[6] = X86_DR6_INIT_VAL;
1109	pCtx->dr[7] = X86_DR7_INIT_VAL;
1110
1111	pCtx->fpu.FTW = 0x00; /* All empty (abbridged tag reg edition). */
1112	pCtx->fpu.FCW = 0x37f;
1113
1114	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
1115	pCtx->fpu.MXCSR = 0x1F80;
1116
1117	/* Init PAT MSR */
1118	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1119
1120	/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
1121	* The Intel docs don't mention it.
1122	*/
1123	pCtx->msrEFER = 0;
1124	}
1125
1126
1127	/**
1128	* Resets the CPU.
1129	*
1130	* @returns VINF_SUCCESS.
1131	* @param pVM The VM handle.
1132	*/
1133	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1134	{
1135	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1136	{
1137	CPUMR3ResetCpu(&pVM->aCpus[i]);
1138
1139	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1140	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
1141
1142	/* Magic marker for searching in crash dumps. */
1143	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1144	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1145	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1146	#endif
1147	}
1148	}
1149
1150
1151	/**
1152	* Called both in pass 0 and the final pass.
1153	*
1154	* @param pVM The VM handle.
1155	* @param pSSM The saved state handle.
1156	*/
1157	static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1158	{
1159	/*
1160	* Save all the CPU ID leaves here so we can check them for compatibility
1161	* upon loading.
1162	*/
1163	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1164	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1165
1166	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1167	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1168
1169	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1170	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1171
1172	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1173
1174	/*
1175	* Save a good portion of the raw CPU IDs as well as they may come in
1176	* handy when validating features for raw mode.
1177	*/
1178	CPUMCPUID aRawStd[16];
1179	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1180	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1181	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1182	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1183
1184	CPUMCPUID aRawExt[32];
1185	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1186	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1187	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1188	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1189	}
1190
1191
1192	/**
1193	* Loads the CPU ID leaves saved by pass 0.
1194	*
1195	* @returns VBox status code.
1196	* @param pVM The VM handle.
1197	* @param pSSM The saved state handle.
1198	* @param uVersion The format version.
1199	*/
1200	static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1201	{
1202	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1203
1204	/*
1205	* Define a bunch of macros for simplifying the code.
1206	*/
1207	/* Generic expression + failure message. */
1208	#define CPUID_CHECK_RET(expr, fmt) \
1209	do { \
1210	if (!(expr)) \
1211	{ \
1212	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
1213	if (fStrictCpuIdChecks) \
1214	{ \
1215	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1216	RTStrFree(pszMsg); \
1217	return rcCpuid; \
1218	} \
1219	LogRel(("CPUM: %s\n", pszMsg)); \
1220	RTStrFree(pszMsg); \
1221	} \
1222	} while (0)
1223	#define CPUID_CHECK_WRN(expr, fmt) \
1224	do { \
1225	if (!(expr)) \
1226	LogRel(fmt); \
1227	} while (0)
1228
1229	/* For comparing two values and bitch if they differs. */
1230	#define CPUID_CHECK2_RET(what, host, saved) \
1231	do { \
1232	if ((host) != (saved)) \
1233	{ \
1234	if (fStrictCpuIdChecks) \
1235	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1236	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1237	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1238	} \
1239	} while (0)
1240	#define CPUID_CHECK2_WRN(what, host, saved) \
1241	do { \
1242	if ((host) != (saved)) \
1243	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1244	} while (0)
1245
1246	/* For checking raw cpu features (raw mode). */
1247	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1248	do { \
1249	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1250	{ \
1251	if (fStrictCpuIdChecks) \
1252	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1253	N_(#bit " mismatch: host=%d saved=%d"), \
1254	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1255	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1256	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1257	} \
1258	} while (0)
1259	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1260	do { \
1261	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1262	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1263	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1264	} while (0)
1265	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1266
1267	/* For checking guest features. */
1268	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1269	do { \
1270	if ( (aGuestCpuId##set [1].reg & bit) \
1271	&& !(aHostRaw##set [1].reg & bit) \
1272	&& !(aHostOverride##set [1].reg & bit) \
1273	&& !(aGuestOverride##set [1].reg & bit) \
1274	) \
1275	{ \
1276	if (fStrictCpuIdChecks) \
1277	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1278	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1279	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1280	} \
1281	} while (0)
1282	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1283	do { \
1284	if ( (aGuestCpuId##set [1].reg & bit) \
1285	&& !(aHostRaw##set [1].reg & bit) \
1286	&& !(aHostOverride##set [1].reg & bit) \
1287	&& !(aGuestOverride##set [1].reg & bit) \
1288	) \
1289	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1290	} while (0)
1291	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1292	do { \
1293	if ( (aGuestCpuId##set [1].reg & bit) \
1294	&& !(aHostRaw##set [1].reg & bit) \
1295	&& !(aHostOverride##set [1].reg & bit) \
1296	&& !(aGuestOverride##set [1].reg & bit) \
1297	) \
1298	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1299	} while (0)
1300	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1301
1302	/* For checking guest features if AMD guest CPU. */
1303	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1304	do { \
1305	if ( (aGuestCpuId##set [1].reg & bit) \
1306	&& fGuestAmd \
1307	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1308	&& !(aHostOverride##set [1].reg & bit) \
1309	&& !(aGuestOverride##set [1].reg & bit) \
1310	) \
1311	{ \
1312	if (fStrictCpuIdChecks) \
1313	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1314	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1315	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1316	} \
1317	} while (0)
1318	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1319	do { \
1320	if ( (aGuestCpuId##set [1].reg & bit) \
1321	&& fGuestAmd \
1322	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1323	&& !(aHostOverride##set [1].reg & bit) \
1324	&& !(aGuestOverride##set [1].reg & bit) \
1325	) \
1326	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1327	} while (0)
1328	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1329	do { \
1330	if ( (aGuestCpuId##set [1].reg & bit) \
1331	&& fGuestAmd \
1332	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1333	&& !(aHostOverride##set [1].reg & bit) \
1334	&& !(aGuestOverride##set [1].reg & bit) \
1335	) \
1336	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1337	} while (0)
1338	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1339
1340	/* For checking AMD features which have a corresponding bit in the standard
1341	range. (Intel defines very few bits in the extended feature sets.) */
1342	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1343	do { \
1344	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1345	&& !(fHostAmd \
1346	? aHostRawExt[1].reg & (ExtBit) \
1347	: aHostRawStd[1].reg & (StdBit)) \
1348	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1349	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1350	) \
1351	{ \
1352	if (fStrictCpuIdChecks) \
1353	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1354	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1355	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1356	} \
1357	} while (0)
1358	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1359	do { \
1360	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1361	&& !(fHostAmd \
1362	? aHostRawExt[1].reg & (ExtBit) \
1363	: aHostRawStd[1].reg & (StdBit)) \
1364	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1365	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1366	) \
1367	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1368	} while (0)
1369	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1370	do { \
1371	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1372	&& !(fHostAmd \
1373	? aHostRawExt[1].reg & (ExtBit) \
1374	: aHostRawStd[1].reg & (StdBit)) \
1375	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1376	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1377	) \
1378	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1379	} while (0)
1380	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1381
1382	/*
1383	* Load them into stack buffers first.
1384	*/
1385	CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1386	uint32_t cGuestCpuIdStd;
1387	int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1388	if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1389	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1390	SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1391
1392	CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1393	uint32_t cGuestCpuIdExt;
1394	rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1395	if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1396	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1397	SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1398
1399	CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1400	uint32_t cGuestCpuIdCentaur;
1401	rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1402	if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1403	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1404	SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1405
1406	CPUMCPUID GuestCpuIdDef;
1407	rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1408	AssertRCReturn(rc, rc);
1409
1410	CPUMCPUID aRawStd[16];
1411	uint32_t cRawStd;
1412	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1413	if (cRawStd > RT_ELEMENTS(aRawStd))
1414	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1415	SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1416
1417	CPUMCPUID aRawExt[32];
1418	uint32_t cRawExt;
1419	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1420	if (cRawExt > RT_ELEMENTS(aRawExt))
1421	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1422	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1423	AssertRCReturn(rc, rc);
1424
1425	/*
1426	* Note that we support restoring less than the current amount of standard
1427	* leaves because we've been allowed more is newer version of VBox.
1428	*
1429	* So, pad new entries with the default.
1430	*/
1431	for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1432	aGuestCpuIdStd[i] = GuestCpuIdDef;
1433
1434	for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1435	aGuestCpuIdExt[i] = GuestCpuIdDef;
1436
1437	for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1438	aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1439
1440	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1441	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1442
1443	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1444	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1445
1446	/*
1447	* Get the raw CPU IDs for the current host.
1448	*/
1449	CPUMCPUID aHostRawStd[16];
1450	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1451	ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1452
1453	CPUMCPUID aHostRawExt[32];
1454	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1455	ASMCpuId(i \| UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1456
1457	/*
1458	* Get the host and guest overrides so we don't reject the state because
1459	* some feature was enabled thru these interfaces.
1460	* Note! We currently only need the feature leaves, so skip rest.
1461	*/
1462	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1463	CPUMCPUID aGuestOverrideStd[2];
1464	memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1465	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1466
1467	CPUMCPUID aGuestOverrideExt[2];
1468	memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1469	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1470
1471	pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1472	CPUMCPUID aHostOverrideStd[2];
1473	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1474	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1475
1476	CPUMCPUID aHostOverrideExt[2];
1477	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1478	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1479
1480	/*
1481	* This can be skipped.
1482	*/
1483	bool fStrictCpuIdChecks;
1484	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1485
1486
1487
1488	/*
1489	* For raw-mode we'll require that the CPUs are very similar since we don't
1490	* intercept CPUID instructions for user mode applications.
1491	*/
1492	if (!HWACCMIsEnabled(pVM))
1493	{
1494	/* CPUID(0) */
1495	CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1496	&& aHostRawStd[0].ecx == aRawStd[0].ecx
1497	&& aHostRawStd[0].edx == aRawStd[0].edx,
1498	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1499	&aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1500	&aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1501	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1502	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1503	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1504
1505	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1506
1507	/* CPUID(1).eax */
1508	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1509	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1510	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1511
1512	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1513	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1514	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1515
1516	/* CPUID(1).ecx */
1517	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1518	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1519	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1520	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1521	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1522	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1523	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1524	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1525	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1526	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1527	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1528	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1529	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1530	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1531	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1532	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1533	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1534	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1535	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1536	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1537	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1538	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1539	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
1540	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
1541	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1542	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
1543	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
1544	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
1545	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
1546	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1547	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1548	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1549
1550	/* CPUID(1).edx */
1551	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1552	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1553	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
1554	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1555	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
1556	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
1557	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1558	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1559	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
1560	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1561	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1562	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1563	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1564	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1565	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1566	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
1567	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1568	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1569	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1570	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
1571	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1572	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
1573	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
1574	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
1575	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
1576	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
1577	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
1578	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
1579	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
1580	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
1581	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/);
1582	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
1583
1584	/* CPUID(2) - config, mostly about caches. ignore. */
1585	/* CPUID(3) - processor serial number. ignore. */
1586	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
1587	/* CPUID(5) - mwait/monitor config. ignore. */
1588	/* CPUID(6) - power management. ignore. */
1589	/* CPUID(7) - ???. ignore. */
1590	/* CPUID(8) - ???. ignore. */
1591	/* CPUID(9) - DCA. ignore for now. */
1592	/* CPUID(a) - PeMo info. ignore for now. */
1593	/* CPUID(b) - topology info - takes ECX as input. ignore. */
1594
1595	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
1596	CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
1597	\|\| aHostRawStd[0].eax >= UINT32_C(0x0000000d),
1598	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
1599	if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
1600	&& aHostRawStd[0].eax >= UINT32_C(0x0000000d))
1601	{
1602	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
1603	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
1604	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
1605	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
1606	}
1607
1608	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
1609	Note! Intel have/is marking many of the fields here as reserved. We
1610	will verify them as if it's an AMD CPU. */
1611	CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
1612	\|\| !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
1613	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
1614	if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
1615	{
1616	CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
1617	&& aHostRawExt[0].ecx == aRawExt[0].ecx
1618	&& aHostRawExt[0].edx == aRawExt[0].edx,
1619	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1620	&aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
1621	&aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
1622	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
1623
1624	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
1625	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
1626	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
1627	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
1628	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
1629	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1630
1631	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
1632	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
1633	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
1634	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
1635
1636	/* CPUID(0x80000001).ecx */
1637	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
1638	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
1639	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
1640	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
1641	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1642	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
1643	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
1644	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
1645	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
1646	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
1647	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
1648	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
1649	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
1650	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
1651	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1652	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1653	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1654	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1655	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1656	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1657	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1658	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1659	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1660	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1661	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1662	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1663	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1664	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1665	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1666	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1667	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1668	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1669
1670	/* CPUID(0x80000001).edx */
1671	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
1672	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
1673	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
1674	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
1675	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
1676	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
1677	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
1678	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
1679	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
1680	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
1681	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /reserved/);
1682	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP);
1683	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
1684	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
1685	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
1686	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1687	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
1688	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
1689	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /reserved/);
1690	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /reserved/);
1691	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1692	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /reserved/);
1693	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1694	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
1695	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
1696	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1697	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1698	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1699	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /reserved/);
1700	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1701	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1702	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1703
1704	/** @todo verify the rest as well. */
1705	}
1706	}
1707
1708
1709
1710	/*
1711	* Verify that we can support the features already exposed to the guest on
1712	* this host.
1713	*
1714	* Most of the features we're emulating requires intercepting instruction
1715	* and doing it the slow way, so there is no need to warn when they aren't
1716	* present in the host CPU. Thus we use IGN instead of EMU on these.
1717	*
1718	* Trailing comments:
1719	* "EMU" - Possible to emulate, could be lots of work and very slow.
1720	* "EMU?" - Can this be emulated?
1721	*/
1722	/* CPUID(1).ecx */
1723	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
1724	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
1725	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
1726	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1727	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
1728	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
1729	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
1730	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
1731	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
1732	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
1733	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
1734	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1735	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
1736	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
1737	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
1738	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
1739	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1740	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1741	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
1742	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
1743	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
1744	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1745	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
1746	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
1747	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1748	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
1749	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
1750	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
1751	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
1752	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1753	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1754	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1755
1756	/* CPUID(1).edx */
1757	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1758	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1759	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
1760	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1761	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1762	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1763	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1764	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1765	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1766	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1767	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1768	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1769	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1770	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1771	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1772	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1773	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1774	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1775	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1776	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
1777	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1778	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
1779	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
1780	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1781	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1782	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
1783	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
1784	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
1785	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
1786	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
1787	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
1788	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
1789
1790	/* CPUID(0x80000000). */
1791	if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
1792	&& aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
1793	{
1794	/** @todo deal with no 0x80000001 on the host. */
1795	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
1796	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
1797
1798	/* CPUID(0x80000001).ecx */
1799	CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF); // -> EMU
1800	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
1801	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
1802	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
1803	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
1804	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
1805	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
1806	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
1807	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
1808	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
1809	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
1810	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
1811	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
1812	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
1813	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1814	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1815	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1816	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1817	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1818	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1819	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1820	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1821	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1822	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1823	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1824	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1825	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1826	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1827	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1828	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1829	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1830	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1831
1832	/* CPUID(0x80000001).edx */
1833	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
1834	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
1835	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
1836	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
1837	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1838	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1839	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
1840	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
1841	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1842	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
1843	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /reserved/);
1844	CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP); // Intel: long mode only.
1845	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
1846	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
1847	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
1848	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1849	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
1850	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
1851	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /reserved/);
1852	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /reserved/);
1853	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1854	CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /reserved/);
1855	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1856	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1857	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1858	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1859	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1860	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1861	CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /reserved/);
1862	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1863	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1864	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1865	}
1866
1867	/*
1868	* We're good, commit the CPU ID leaves.
1869	*/
1870	memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
1871	memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
1872	memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
1873	pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
1874
1875	#undef CPUID_CHECK_RET
1876	#undef CPUID_CHECK_WRN
1877	#undef CPUID_CHECK2_RET
1878	#undef CPUID_CHECK2_WRN
1879	#undef CPUID_RAW_FEATURE_RET
1880	#undef CPUID_RAW_FEATURE_WRN
1881	#undef CPUID_RAW_FEATURE_IGN
1882	#undef CPUID_GST_FEATURE_RET
1883	#undef CPUID_GST_FEATURE_WRN
1884	#undef CPUID_GST_FEATURE_EMU
1885	#undef CPUID_GST_FEATURE_IGN
1886	#undef CPUID_GST_FEATURE2_RET
1887	#undef CPUID_GST_FEATURE2_WRN
1888	#undef CPUID_GST_FEATURE2_EMU
1889	#undef CPUID_GST_FEATURE2_IGN
1890	#undef CPUID_GST_AMD_FEATURE_RET
1891	#undef CPUID_GST_AMD_FEATURE_WRN
1892	#undef CPUID_GST_AMD_FEATURE_EMU
1893	#undef CPUID_GST_AMD_FEATURE_IGN
1894
1895	return VINF_SUCCESS;
1896	}
1897
1898
1899	/**
1900	* Pass 0 live exec callback.
1901	*
1902	* @returns VINF_SSM_DONT_CALL_AGAIN.
1903	* @param pVM The VM handle.
1904	* @param pSSM The saved state handle.
1905	* @param uPass The pass (0).
1906	*/
1907	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1908	{
1909	AssertReturn(uPass == 0, VERR_INTERNAL_ERROR_4);
1910	cpumR3SaveCpuId(pVM, pSSM);
1911	return VINF_SSM_DONT_CALL_AGAIN;
1912	}
1913
1914
1915	/**
1916	* Execute state save operation.
1917	*
1918	* @returns VBox status code.
1919	* @param pVM VM Handle.
1920	* @param pSSM SSM operation handle.
1921	*/
1922	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1923	{
1924	/*
1925	* Save.
1926	*/
1927	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1928	{
1929	PVMCPU pVCpu = &pVM->aCpus[i];
1930
1931	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1932	}
1933
1934	SSMR3PutU32(pSSM, pVM->cCpus);
1935	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1936	{
1937	PVMCPU pVCpu = &pVM->aCpus[i];
1938
1939	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
1940	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1941	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1942	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
1943	}
1944
1945	cpumR3SaveCpuId(pVM, pSSM);
1946	return VINF_SUCCESS;
1947	}
1948
1949
1950	/**
1951	* Load a version 1.6 CPUMCTX structure.
1952	*
1953	* @returns VBox status code.
1954	* @param pVM VM Handle.
1955	* @param pCpumctx16 Version 1.6 CPUMCTX
1956	*/
1957	static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
1958	{
1959	#define CPUMCTX16_LOADREG(RegName) \
1960	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
1961
1962	#define CPUMCTX16_LOADDRXREG(RegName) \
1963	pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
1964
1965	#define CPUMCTX16_LOADHIDREG(RegName) \
1966	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
1967	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
1968	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
1969
1970	#define CPUMCTX16_LOADSEGREG(RegName) \
1971	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
1972	CPUMCTX16_LOADHIDREG(RegName);
1973
1974	pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
1975
1976	CPUMCTX16_LOADREG(rax);
1977	CPUMCTX16_LOADREG(rbx);
1978	CPUMCTX16_LOADREG(rcx);
1979	CPUMCTX16_LOADREG(rdx);
1980	CPUMCTX16_LOADREG(rdi);
1981	CPUMCTX16_LOADREG(rsi);
1982	CPUMCTX16_LOADREG(rbp);
1983	CPUMCTX16_LOADREG(esp);
1984	CPUMCTX16_LOADREG(rip);
1985	CPUMCTX16_LOADREG(rflags);
1986
1987	CPUMCTX16_LOADSEGREG(cs);
1988	CPUMCTX16_LOADSEGREG(ds);
1989	CPUMCTX16_LOADSEGREG(es);
1990	CPUMCTX16_LOADSEGREG(fs);
1991	CPUMCTX16_LOADSEGREG(gs);
1992	CPUMCTX16_LOADSEGREG(ss);
1993
1994	CPUMCTX16_LOADREG(r8);
1995	CPUMCTX16_LOADREG(r9);
1996	CPUMCTX16_LOADREG(r10);
1997	CPUMCTX16_LOADREG(r11);
1998	CPUMCTX16_LOADREG(r12);
1999	CPUMCTX16_LOADREG(r13);
2000	CPUMCTX16_LOADREG(r14);
2001	CPUMCTX16_LOADREG(r15);
2002
2003	CPUMCTX16_LOADREG(cr0);
2004	CPUMCTX16_LOADREG(cr2);
2005	CPUMCTX16_LOADREG(cr3);
2006	CPUMCTX16_LOADREG(cr4);
2007
2008	CPUMCTX16_LOADDRXREG(0);
2009	CPUMCTX16_LOADDRXREG(1);
2010	CPUMCTX16_LOADDRXREG(2);
2011	CPUMCTX16_LOADDRXREG(3);
2012	CPUMCTX16_LOADDRXREG(4);
2013	CPUMCTX16_LOADDRXREG(5);
2014	CPUMCTX16_LOADDRXREG(6);
2015	CPUMCTX16_LOADDRXREG(7);
2016
2017	pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
2018	pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
2019	pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
2020	pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
2021
2022	CPUMCTX16_LOADREG(ldtr);
2023	CPUMCTX16_LOADREG(tr);
2024
2025	pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
2026
2027	CPUMCTX16_LOADREG(msrEFER);
2028	CPUMCTX16_LOADREG(msrSTAR);
2029	CPUMCTX16_LOADREG(msrPAT);
2030	CPUMCTX16_LOADREG(msrLSTAR);
2031	CPUMCTX16_LOADREG(msrCSTAR);
2032	CPUMCTX16_LOADREG(msrSFMASK);
2033	CPUMCTX16_LOADREG(msrKERNELGSBASE);
2034
2035	CPUMCTX16_LOADHIDREG(ldtr);
2036	CPUMCTX16_LOADHIDREG(tr);
2037
2038	#undef CPUMCTX16_LOADSEGREG
2039	#undef CPUMCTX16_LOADHIDREG
2040	#undef CPUMCTX16_LOADDRXREG
2041	#undef CPUMCTX16_LOADREG
2042	}
2043
2044
2045	/**
2046	* @copydoc FNSSMINTLOADPREP
2047	*/
2048	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2049	{
2050	pVM->cpum.s.fPendingRestore = true;
2051	return VINF_SUCCESS;
2052	}
2053
2054
2055	/**
2056	* @copydoc FNSSMINTLOADEXEC
2057	*/
2058	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2059	{
2060	/*
2061	* Validate version.
2062	*/
2063	if ( uVersion != CPUM_SAVED_STATE_VERSION
2064	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2065	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2066	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2067	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2068	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2069	{
2070	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2071	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2072	}
2073
2074	if (uPass == SSM_PASS_FINAL)
2075	{
2076	/*
2077	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2078	* really old SSM file versions.)
2079	*/
2080	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2081	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2082	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2083	SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2084
2085	/*
2086	* Restore.
2087	*/
2088	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2089	{
2090	PVMCPU pVCpu = &pVM->aCpus[i];
2091	uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2092	uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
2093
2094	SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
2095	pVCpu->cpum.s.Hyper.cr3 = uCR3;
2096	pVCpu->cpum.s.Hyper.esp = uESP;
2097	}
2098
2099	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2100	{
2101	CPUMCTX_VER1_6 cpumctx16;
2102	memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
2103	SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
2104
2105	/* Save the old cpumctx state into the new one. */
2106	cpumR3LoadCPUM1_6(pVM, &cpumctx16);
2107
2108	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
2109	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
2110	}
2111	else
2112	{
2113	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2114	{
2115	uint32_t cCpus;
2116	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2117	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2118	VERR_SSM_UNEXPECTED_DATA);
2119	}
2120	AssertLogRelMsgReturn( uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2121	\|\| pVM->cCpus == 1,
2122	("cCpus=%u\n", pVM->cCpus),
2123	VERR_SSM_UNEXPECTED_DATA);
2124
2125	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2126	{
2127	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
2128	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
2129	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
2130	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2131	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
2132	}
2133	}
2134
2135	/* Older states does not set CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID for
2136	raw-mode guest, so we have to do it ourselves. */
2137	if ( uVersion <= CPUM_SAVED_STATE_VERSION_VER3_2
2138	&& !HWACCMIsEnabled(pVM))
2139	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2140	pVM->aCpus[iCpu].cpum.s.fChanged \|= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2141	}
2142
2143	pVM->cpum.s.fPendingRestore = false;
2144
2145	/*
2146	* Guest CPUIDs.
2147	*/
2148	if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2149	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2150
2151	/** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2152	* actually required. */
2153
2154	/*
2155	* Restore the CPUID leaves.
2156	*
2157	* Note that we support restoring less than the current amount of standard
2158	* leaves because we've been allowed more is newer version of VBox.
2159	*/
2160	uint32_t cElements;
2161	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2162	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2163	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2164	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2165
2166	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2167	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2168	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2169	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2170
2171	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2172	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2173	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2174	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2175
2176	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2177
2178	/*
2179	* Check that the basic cpuid id information is unchanged.
2180	*/
2181	/** @todo we should check the 64 bits capabilities too! */
2182	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2183	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2184	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2185	uint32_t au32CpuIdSaved[8];
2186	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2187	if (RT_SUCCESS(rc))
2188	{
2189	/* Ignore CPU stepping. */
2190	au32CpuId[4] &= 0xfffffff0;
2191	au32CpuIdSaved[4] &= 0xfffffff0;
2192
2193	/* Ignore APIC ID (AMD specs). */
2194	au32CpuId[5] &= ~0xff000000;
2195	au32CpuIdSaved[5] &= ~0xff000000;
2196
2197	/* Ignore the number of Logical CPUs (AMD specs). */
2198	au32CpuId[5] &= ~0x00ff0000;
2199	au32CpuIdSaved[5] &= ~0x00ff0000;
2200
2201	/* Ignore some advanced capability bits, that we don't expose to the guest. */
2202	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2203	\| X86_CPUID_FEATURE_ECX_VMX
2204	\| X86_CPUID_FEATURE_ECX_SMX
2205	\| X86_CPUID_FEATURE_ECX_EST
2206	\| X86_CPUID_FEATURE_ECX_TM2
2207	\| X86_CPUID_FEATURE_ECX_CNTXID
2208	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2209	\| X86_CPUID_FEATURE_ECX_PDCM
2210	\| X86_CPUID_FEATURE_ECX_DCA
2211	\| X86_CPUID_FEATURE_ECX_X2APIC
2212	);
2213	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2214	\| X86_CPUID_FEATURE_ECX_VMX
2215	\| X86_CPUID_FEATURE_ECX_SMX
2216	\| X86_CPUID_FEATURE_ECX_EST
2217	\| X86_CPUID_FEATURE_ECX_TM2
2218	\| X86_CPUID_FEATURE_ECX_CNTXID
2219	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2220	\| X86_CPUID_FEATURE_ECX_PDCM
2221	\| X86_CPUID_FEATURE_ECX_DCA
2222	\| X86_CPUID_FEATURE_ECX_X2APIC
2223	);
2224
2225	/* Make sure we don't forget to update the masks when enabling
2226	* features in the future.
2227	*/
2228	AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2229	( X86_CPUID_FEATURE_ECX_DTES64
2230	\| X86_CPUID_FEATURE_ECX_VMX
2231	\| X86_CPUID_FEATURE_ECX_SMX
2232	\| X86_CPUID_FEATURE_ECX_EST
2233	\| X86_CPUID_FEATURE_ECX_TM2
2234	\| X86_CPUID_FEATURE_ECX_CNTXID
2235	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2236	\| X86_CPUID_FEATURE_ECX_PDCM
2237	\| X86_CPUID_FEATURE_ECX_DCA
2238	\| X86_CPUID_FEATURE_ECX_X2APIC
2239	)));
2240	/* do the compare */
2241	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2242	{
2243	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2244	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2245	"Saved=%.*Rhxs\n"
2246	"Real =%.*Rhxs\n",
2247	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2248	sizeof(au32CpuId), au32CpuId));
2249	else
2250	{
2251	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2252	"Saved=%.*Rhxs\n"
2253	"Real =%.*Rhxs\n",
2254	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2255	sizeof(au32CpuId), au32CpuId));
2256	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2257	}
2258	}
2259	}
2260
2261	return rc;
2262	}
2263
2264
2265	/**
2266	* @copydoc FNSSMINTLOADPREP
2267	*/
2268	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2269	{
2270	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2271	return VINF_SUCCESS;
2272
2273	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2274	if (pVM->cpum.s.fPendingRestore)
2275	{
2276	LogRel(("CPUM: Missing state!\n"));
2277	return VERR_INTERNAL_ERROR_2;
2278	}
2279
2280	/* Notify PGM of the NXE states in case they've changed. */
2281	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2282	PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2283	return VINF_SUCCESS;
2284	}
2285
2286
2287	/**
2288	* Checks if the CPUM state restore is still pending.
2289	*
2290	* @returns true / false.
2291	* @param pVM The VM handle.
2292	*/
2293	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2294	{
2295	return pVM->cpum.s.fPendingRestore;
2296	}
2297
2298
2299	/**
2300	* Formats the EFLAGS value into mnemonics.
2301	*
2302	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2303	* @param efl The EFLAGS value.
2304	*/
2305	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2306	{
2307	/*
2308	* Format the flags.
2309	*/
2310	static const struct
2311	{
2312	const char pszSet; const char pszClear; uint32_t fFlag;
2313	} s_aFlags[] =
2314	{
2315	{ "vip",NULL, X86_EFL_VIP },
2316	{ "vif",NULL, X86_EFL_VIF },
2317	{ "ac", NULL, X86_EFL_AC },
2318	{ "vm", NULL, X86_EFL_VM },
2319	{ "rf", NULL, X86_EFL_RF },
2320	{ "nt", NULL, X86_EFL_NT },
2321	{ "ov", "nv", X86_EFL_OF },
2322	{ "dn", "up", X86_EFL_DF },
2323	{ "ei", "di", X86_EFL_IF },
2324	{ "tf", NULL, X86_EFL_TF },
2325	{ "nt", "pl", X86_EFL_SF },
2326	{ "nz", "zr", X86_EFL_ZF },
2327	{ "ac", "na", X86_EFL_AF },
2328	{ "po", "pe", X86_EFL_PF },
2329	{ "cy", "nc", X86_EFL_CF },
2330	};
2331	char *psz = pszEFlags;
2332	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2333	{
2334	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2335	if (pszAdd)
2336	{
2337	strcpy(psz, pszAdd);
2338	psz += strlen(pszAdd);
2339	*psz++ = ' ';
2340	}
2341	}
2342	psz[-1] = '\0';
2343	}
2344
2345
2346	/**
2347	* Formats a full register dump.
2348	*
2349	* @param pVM VM Handle.
2350	* @param pCtx The context to format.
2351	* @param pCtxCore The context core to format.
2352	* @param pHlp Output functions.
2353	* @param enmType The dump type.
2354	* @param pszPrefix Register name prefix.
2355	*/
2356	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
2357	{
2358	/*
2359	* Format the EFLAGS.
2360	*/
2361	uint32_t efl = pCtxCore->eflags.u32;
2362	char szEFlags[80];
2363	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2364
2365	/*
2366	* Format the registers.
2367	*/
2368	switch (enmType)
2369	{
2370	case CPUMDUMPTYPE_TERSE:
2371	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2372	pHlp->pfnPrintf(pHlp,
2373	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2374	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2375	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2376	"%sr14=%016RX64 %sr15=%016RX64\n"
2377	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2378	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2379	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2380	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2381	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2382	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2383	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2384	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2385	else
2386	pHlp->pfnPrintf(pHlp,
2387	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2388	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2389	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2390	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2391	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2392	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2393	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2394	break;
2395
2396	case CPUMDUMPTYPE_DEFAULT:
2397	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2398	pHlp->pfnPrintf(pHlp,
2399	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2400	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2401	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2402	"%sr14=%016RX64 %sr15=%016RX64\n"
2403	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2404	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2405	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2406	,
2407	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2408	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2409	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2410	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2411	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2412	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2413	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2414	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2415	else
2416	pHlp->pfnPrintf(pHlp,
2417	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2418	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2419	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2420	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2421	,
2422	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2423	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2424	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2425	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2426	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2427	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2428	break;
2429
2430	case CPUMDUMPTYPE_VERBOSE:
2431	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2432	pHlp->pfnPrintf(pHlp,
2433	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2434	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2435	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2436	"%sr14=%016RX64 %sr15=%016RX64\n"
2437	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2438	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2439	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2440	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2441	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2442	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2443	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2444	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2445	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2446	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2447	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2448	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2449	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2450	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2451	,
2452	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2453	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2454	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2455	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2456	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
2457	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
2458	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
2459	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
2460	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
2461	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
2462	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2463	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2464	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2465	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2466	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2467	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2468	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2469	else
2470	pHlp->pfnPrintf(pHlp,
2471	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2472	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2473	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2474	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2475	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2476	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2477	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2478	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2479	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2480	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2481	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2482	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2483	,
2484	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2485	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2486	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2487	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2488	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2489	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2490	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2491	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2492	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2493	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2494	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2495	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2496
2497	pHlp->pfnPrintf(pHlp,
2498	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2499	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2500	,
2501	pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2502	pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2503	pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsrvd1,
2504	pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2505	);
2506	unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2507	for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2508	{
2509	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2510	unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2511	char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2512	unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2513	uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2514	unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2515	/** @todo This isn't entirenly correct and needs more work! */
2516	pHlp->pfnPrintf(pHlp,
2517	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2518	pszPrefix, iST, pszPrefix, iFPR,
2519	pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2520	uTag, chSign, iInteger, u64Fraction, uExponent);
2521	if (pCtx->fpu.aRegs[0].au16[5] \|\| pCtx->fpu.aRegs[0].au16[6] \|\| pCtx->fpu.aRegs[0].au16[7])
2522	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2523	pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2524	else
2525	pHlp->pfnPrintf(pHlp, "\n");
2526	}
2527	for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2528	pHlp->pfnPrintf(pHlp,
2529	iXMM & 1
2530	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2531	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2532	pszPrefix, iXMM, iXMM < 10 ? " " : "",
2533	pCtx->fpu.aXMM[iXMM].au32[3],
2534	pCtx->fpu.aXMM[iXMM].au32[2],
2535	pCtx->fpu.aXMM[iXMM].au32[1],
2536	pCtx->fpu.aXMM[iXMM].au32[0]);
2537	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2538	if (pCtx->fpu.au32RsrvdRest[i])
2539	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2540	pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2541
2542	pHlp->pfnPrintf(pHlp,
2543	"%sEFER =%016RX64\n"
2544	"%sPAT =%016RX64\n"
2545	"%sSTAR =%016RX64\n"
2546	"%sCSTAR =%016RX64\n"
2547	"%sLSTAR =%016RX64\n"
2548	"%sSFMASK =%016RX64\n"
2549	"%sKERNELGSBASE =%016RX64\n",
2550	pszPrefix, pCtx->msrEFER,
2551	pszPrefix, pCtx->msrPAT,
2552	pszPrefix, pCtx->msrSTAR,
2553	pszPrefix, pCtx->msrCSTAR,
2554	pszPrefix, pCtx->msrLSTAR,
2555	pszPrefix, pCtx->msrSFMASK,
2556	pszPrefix, pCtx->msrKERNELGSBASE);
2557	break;
2558	}
2559	}
2560
2561
2562	/**
2563	* Display all cpu states and any other cpum info.
2564	*
2565	* @param pVM VM Handle.
2566	* @param pHlp The info helper functions.
2567	* @param pszArgs Arguments, ignored.
2568	*/
2569	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2570	{
2571	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2572	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2573	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2574	cpumR3InfoHost(pVM, pHlp, pszArgs);
2575	}
2576
2577
2578	/**
2579	* Parses the info argument.
2580	*
2581	* The argument starts with 'verbose', 'terse' or 'default' and then
2582	* continues with the comment string.
2583	*
2584	* @param pszArgs The pointer to the argument string.
2585	* @param penmType Where to store the dump type request.
2586	* @param ppszComment Where to store the pointer to the comment string.
2587	*/
2588	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2589	{
2590	if (!pszArgs)
2591	{
2592	*penmType = CPUMDUMPTYPE_DEFAULT;
2593	*ppszComment = "";
2594	}
2595	else
2596	{
2597	if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
2598	{
2599	pszArgs += 5;
2600	*penmType = CPUMDUMPTYPE_VERBOSE;
2601	}
2602	else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
2603	{
2604	pszArgs += 5;
2605	*penmType = CPUMDUMPTYPE_TERSE;
2606	}
2607	else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
2608	{
2609	pszArgs += 7;
2610	*penmType = CPUMDUMPTYPE_DEFAULT;
2611	}
2612	else
2613	*penmType = CPUMDUMPTYPE_DEFAULT;
2614	*ppszComment = RTStrStripL(pszArgs);
2615	}
2616	}
2617
2618
2619	/**
2620	* Display the guest cpu state.
2621	*
2622	* @param pVM VM Handle.
2623	* @param pHlp The info helper functions.
2624	* @param pszArgs Arguments, ignored.
2625	*/
2626	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2627	{
2628	CPUMDUMPTYPE enmType;
2629	const char *pszComment;
2630	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2631
2632	/* @todo SMP support! */
2633	PVMCPU pVCpu = VMMGetCpu(pVM);
2634	if (!pVCpu)
2635	pVCpu = &pVM->aCpus[0];
2636
2637	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2638
2639	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2640	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2641	}
2642
2643
2644	/**
2645	* Display the current guest instruction
2646	*
2647	* @param pVM VM Handle.
2648	* @param pHlp The info helper functions.
2649	* @param pszArgs Arguments, ignored.
2650	*/
2651	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2652	{
2653	char szInstruction[256];
2654	/* @todo SMP support! */
2655	PVMCPU pVCpu = VMMGetCpu(pVM);
2656	if (!pVCpu)
2657	pVCpu = &pVM->aCpus[0];
2658
2659	int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2660	if (RT_SUCCESS(rc))
2661	pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2662	}
2663
2664
2665	/**
2666	* Display the hypervisor cpu state.
2667	*
2668	* @param pVM VM Handle.
2669	* @param pHlp The info helper functions.
2670	* @param pszArgs Arguments, ignored.
2671	*/
2672	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2673	{
2674	CPUMDUMPTYPE enmType;
2675	const char *pszComment;
2676	/* @todo SMP */
2677	PVMCPU pVCpu = &pVM->aCpus[0];
2678
2679	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2680	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2681	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
2682	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2683	}
2684
2685
2686	/**
2687	* Display the host cpu state.
2688	*
2689	* @param pVM VM Handle.
2690	* @param pHlp The info helper functions.
2691	* @param pszArgs Arguments, ignored.
2692	*/
2693	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2694	{
2695	CPUMDUMPTYPE enmType;
2696	const char *pszComment;
2697	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2698	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2699
2700	/*
2701	* Format the EFLAGS.
2702	*/
2703	/* @todo SMP */
2704	PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
2705	#if HC_ARCH_BITS == 32
2706	uint32_t efl = pCtx->eflags.u32;
2707	#else
2708	uint64_t efl = pCtx->rflags;
2709	#endif
2710	char szEFlags[80];
2711	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2712
2713	/*
2714	* Format the registers.
2715	*/
2716	#if HC_ARCH_BITS == 32
2717	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2718	if (!(pCtx->efer & MSR_K6_EFER_LMA))
2719	# endif
2720	{
2721	pHlp->pfnPrintf(pHlp,
2722	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2723	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2724	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2725	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2726	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2727	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2728	,
2729	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
2730	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2731	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2732	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
2733	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2734	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
2735	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2736	}
2737	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2738	else
2739	# endif
2740	#endif
2741	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2742	{
2743	pHlp->pfnPrintf(pHlp,
2744	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2745	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2746	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2747	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2748	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2749	"r14=%016RX64 r15=%016RX64\n"
2750	"iopl=%d %31s\n"
2751	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2752	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2753	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
2754	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2755	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2756	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2757	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2758	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2759	,
2760	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
2761	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2762	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
2763	/pCtx->r8, pCtx->r9,/ pCtx->r10,
2764	pCtx->r11, pCtx->r12, pCtx->r13,
2765	pCtx->r14, pCtx->r15,
2766	X86_EFL_GET_IOPL(efl), szEFlags,
2767	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2768	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
2769	pCtx->cr4, pCtx->ldtr, pCtx->tr,
2770	pCtx->dr0, pCtx->dr1, pCtx->dr2,
2771	pCtx->dr3, pCtx->dr6, pCtx->dr7,
2772	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2773	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2774	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2775	}
2776	#endif
2777	}
2778
2779
2780	/**
2781	* Get L1 cache / TLS associativity.
2782	*/
2783	static const char getCacheAss(unsigned u, char pszBuf)
2784	{
2785	if (u == 0)
2786	return "res0 ";
2787	if (u == 1)
2788	return "direct";
2789	if (u == 255)
2790	return "fully";
2791	if (u >= 256)
2792	return "???";
2793
2794	RTStrPrintf(pszBuf, 16, "%d way", u);
2795	return pszBuf;
2796	}
2797
2798
2799	/**
2800	* Get L2 cache associativity.
2801	*/
2802	const char *getL2CacheAss(unsigned u)
2803	{
2804	switch (u)
2805	{
2806	case 0: return "off ";
2807	case 1: return "direct";
2808	case 2: return "2 way ";
2809	case 3: return "res3 ";
2810	case 4: return "4 way ";
2811	case 5: return "res5 ";
2812	case 6: return "8 way ";
2813	case 7: return "res7 ";
2814	case 8: return "16 way";
2815	case 9: return "res9 ";
2816	case 10: return "res10 ";
2817	case 11: return "res11 ";
2818	case 12: return "res12 ";
2819	case 13: return "res13 ";
2820	case 14: return "res14 ";
2821	case 15: return "fully ";
2822	default: return "????";
2823	}
2824	}
2825
2826
2827	/**
2828	* Display the guest CpuId leaves.
2829	*
2830	* @param pVM VM Handle.
2831	* @param pHlp The info helper functions.
2832	* @param pszArgs "terse", "default" or "verbose".
2833	*/
2834	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2835	{
2836	/*
2837	* Parse the argument.
2838	*/
2839	unsigned iVerbosity = 1;
2840	if (pszArgs)
2841	{
2842	pszArgs = RTStrStripL(pszArgs);
2843	if (!strcmp(pszArgs, "terse"))
2844	iVerbosity--;
2845	else if (!strcmp(pszArgs, "verbose"))
2846	iVerbosity++;
2847	}
2848
2849	/*
2850	* Start cracking.
2851	*/
2852	CPUMCPUID Host;
2853	CPUMCPUID Guest;
2854	unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
2855
2856	pHlp->pfnPrintf(pHlp,
2857	" RAW Standard CPUIDs\n"
2858	" Function eax ebx ecx edx\n");
2859	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
2860	{
2861	Guest = pVM->cpum.s.aGuestCpuIdStd[i];
2862	ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2863
2864	pHlp->pfnPrintf(pHlp,
2865	"Gst: %08x %08x %08x %08x %08x%s\n"
2866	"Hst: %08x %08x %08x %08x\n",
2867	i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2868	i <= cStdMax ? "" : "*",
2869	Host.eax, Host.ebx, Host.ecx, Host.edx);
2870	}
2871
2872	/*
2873	* If verbose, decode it.
2874	*/
2875	if (iVerbosity)
2876	{
2877	Guest = pVM->cpum.s.aGuestCpuIdStd[0];
2878	pHlp->pfnPrintf(pHlp,
2879	"Name: %.04s%.04s%.04s\n"
2880	"Supports: 0-%x\n",
2881	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2882	}
2883
2884	/*
2885	* Get Features.
2886	*/
2887	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
2888	pVM->cpum.s.aGuestCpuIdStd[0].ecx,
2889	pVM->cpum.s.aGuestCpuIdStd[0].edx);
2890	if (cStdMax >= 1 && iVerbosity)
2891	{
2892	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
2893
2894	Guest = pVM->cpum.s.aGuestCpuIdStd[1];
2895	uint32_t uEAX = Guest.eax;
2896
2897	pHlp->pfnPrintf(pHlp,
2898	"Family: %d \tExtended: %d \tEffective: %d\n"
2899	"Model: %d \tExtended: %d \tEffective: %d\n"
2900	"Stepping: %d\n"
2901	"Type: %d (%s)\n"
2902	"APIC ID: %#04x\n"
2903	"Logical CPUs: %d\n"
2904	"CLFLUSH Size: %d\n"
2905	"Brand ID: %#04x\n",
2906	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2907	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2908	ASMGetCpuStepping(uEAX),
2909	(uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
2910	(Guest.ebx >> 24) & 0xff,
2911	(Guest.ebx >> 16) & 0xff,
2912	(Guest.ebx >> 8) & 0xff,
2913	(Guest.ebx >> 0) & 0xff);
2914	if (iVerbosity == 1)
2915	{
2916	uint32_t uEDX = Guest.edx;
2917	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2918	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2919	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2920	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2921	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2922	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2923	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2924	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2925	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2926	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2927	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2928	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2929	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
2930	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2931	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2932	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2933	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2934	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2935	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2936	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
2937	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
2938	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
2939	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
2940	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
2941	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2942	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2943	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
2944	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
2945	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
2946	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
2947	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
2948	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2949	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
2950	pHlp->pfnPrintf(pHlp, "\n");
2951
2952	uint32_t uECX = Guest.ecx;
2953	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2954	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
2955	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
2956	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
2957	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
2958	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
2959	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
2960	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
2961	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
2962	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
2963	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
2964	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
2965	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
2966	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
2967	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
2968	if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
2969	if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
2970	if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
2971	if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID");
2972	if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
2973	if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1");
2974	if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2");
2975	if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
2976	if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
2977	if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
2978	if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL");
2979	if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
2980	if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
2981	if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
2982	if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
2983	if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
2984	if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2985	if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
2986	pHlp->pfnPrintf(pHlp, "\n");
2987	}
2988	else
2989	{
2990	ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2991
2992	X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
2993	X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
2994	X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
2995	X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
2996
2997	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2998	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
2999	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
3000	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
3001	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
3002	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
3003	pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
3004	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
3005	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
3006	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
3007	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
3008	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
3009	pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
3010	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
3011	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
3012	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
3013	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
3014	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
3015	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
3016	pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
3017	pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
3018	pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
3019	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
3020	pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
3021	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
3022	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
3023	pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
3024	pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
3025	pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
3026	pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technology = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
3027	pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
3028	pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
3029	pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
3030
3031	pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
3032	pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ);
3033	pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
3034	pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
3035	pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
3036	pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
3037	pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
3038	pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
3039	pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
3040	pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
3041	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
3042	pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
3043	pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
3044	pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
3045	pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
3046	pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
3047	pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
3048	pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID);
3049	pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
3050	pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
3051	pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
3052	pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
3053	pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
3054	pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
3055	pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE);
3056	pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES);
3057	pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
3058	pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
3059	pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX);
3060	pHlp->pfnPrintf(pHlp, "29/30 - Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
3061	pHlp->pfnPrintf(pHlp, "Hypervisor Present (we're a guest) = %d (%d)\n", EcxGuest.u1HVP, EcxHost.u1HVP);
3062	}
3063	}
3064	if (cStdMax >= 2 && iVerbosity)
3065	{
3066	/** @todo */
3067	}
3068
3069	/*
3070	* Extended.
3071	* Implemented after AMD specs.
3072	*/
3073	unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
3074
3075	pHlp->pfnPrintf(pHlp,
3076	"\n"
3077	" RAW Extended CPUIDs\n"
3078	" Function eax ebx ecx edx\n");
3079	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
3080	{
3081	Guest = pVM->cpum.s.aGuestCpuIdExt[i];
3082	ASMCpuId(0x80000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3083
3084	pHlp->pfnPrintf(pHlp,
3085	"Gst: %08x %08x %08x %08x %08x%s\n"
3086	"Hst: %08x %08x %08x %08x\n",
3087	0x80000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3088	i <= cExtMax ? "" : "*",
3089	Host.eax, Host.ebx, Host.ecx, Host.edx);
3090	}
3091
3092	/*
3093	* Understandable output
3094	*/
3095	if (iVerbosity)
3096	{
3097	Guest = pVM->cpum.s.aGuestCpuIdExt[0];
3098	pHlp->pfnPrintf(pHlp,
3099	"Ext Name: %.4s%.4s%.4s\n"
3100	"Ext Supports: 0x80000000-%#010x\n",
3101	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3102	}
3103
3104	if (iVerbosity && cExtMax >= 1)
3105	{
3106	Guest = pVM->cpum.s.aGuestCpuIdExt[1];
3107	uint32_t uEAX = Guest.eax;
3108	pHlp->pfnPrintf(pHlp,
3109	"Family: %d \tExtended: %d \tEffective: %d\n"
3110	"Model: %d \tExtended: %d \tEffective: %d\n"
3111	"Stepping: %d\n"
3112	"Brand ID: %#05x\n",
3113	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3114	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3115	ASMGetCpuStepping(uEAX),
3116	Guest.ebx & 0xfff);
3117
3118	if (iVerbosity == 1)
3119	{
3120	uint32_t uEDX = Guest.edx;
3121	pHlp->pfnPrintf(pHlp, "Features EDX: ");
3122	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3123	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3124	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3125	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3126	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3127	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3128	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3129	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3130	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3131	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3132	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3133	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
3134	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3135	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3136	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3137	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3138	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3139	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3140	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
3141	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
3142	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
3143	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
3144	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
3145	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3146	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3147	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
3148	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
3149	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
3150	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
3151	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
3152	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
3153	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
3154	pHlp->pfnPrintf(pHlp, "\n");
3155
3156	uint32_t uECX = Guest.ecx;
3157	pHlp->pfnPrintf(pHlp, "Features ECX: ");
3158	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
3159	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
3160	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
3161	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3162	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3163	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3164	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3165	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3166	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3167	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3168	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3169	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3170	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3171	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3172	for (unsigned iBit = 5; iBit < 32; iBit++)
3173	if (uECX & RT_BIT(iBit))
3174	pHlp->pfnPrintf(pHlp, " %d", iBit);
3175	pHlp->pfnPrintf(pHlp, "\n");
3176	}
3177	else
3178	{
3179	ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3180
3181	uint32_t uEdxGst = Guest.edx;
3182	uint32_t uEdxHst = Host.edx;
3183	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3184	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3185	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3186	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3187	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3188	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3189	pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3190	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3191	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3192	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3193	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3194	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3195	pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3196	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3197	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3198	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3199	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3200	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3201	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3202	pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3203	pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3204	pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3205	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3206	pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3207	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3208	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3209	pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3210	pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3211	pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3212	pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3213	pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3214	pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3215	pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3216
3217	uint32_t uEcxGst = Guest.ecx;
3218	uint32_t uEcxHst = Host.ecx;
3219	pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3220	pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3221	pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3222	pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3223	pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3224	pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3225	pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3226	pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3227	pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3228	pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3229	pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3230	pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3231	pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3232	pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3233	pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3234	}
3235	}
3236
3237	if (iVerbosity && cExtMax >= 2)
3238	{
3239	char szString[443+1] = {0};
3240	uint32_t pu32 = (uint32_t )szString;
3241	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3242	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3243	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3244	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3245	if (cExtMax >= 3)
3246	{
3247	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3248	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3249	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3250	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3251	}
3252	if (cExtMax >= 4)
3253	{
3254	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3255	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3256	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3257	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3258	}
3259	pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3260	}
3261
3262	if (iVerbosity && cExtMax >= 5)
3263	{
3264	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3265	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3266	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3267	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3268	char sz1[32];
3269	char sz2[32];
3270
3271	pHlp->pfnPrintf(pHlp,
3272	"TLB 2/4M Instr/Uni: %s %3d entries\n"
3273	"TLB 2/4M Data: %s %3d entries\n",
3274	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3275	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3276	pHlp->pfnPrintf(pHlp,
3277	"TLB 4K Instr/Uni: %s %3d entries\n"
3278	"TLB 4K Data: %s %3d entries\n",
3279	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3280	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3281	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3282	"L1 Instr Cache Lines Per Tag: %d\n"
3283	"L1 Instr Cache Associativity: %s\n"
3284	"L1 Instr Cache Size: %d KB\n",
3285	(uEDX >> 0) & 0xff,
3286	(uEDX >> 8) & 0xff,
3287	getCacheAss((uEDX >> 16) & 0xff, sz1),
3288	(uEDX >> 24) & 0xff);
3289	pHlp->pfnPrintf(pHlp,
3290	"L1 Data Cache Line Size: %d bytes\n"
3291	"L1 Data Cache Lines Per Tag: %d\n"
3292	"L1 Data Cache Associativity: %s\n"
3293	"L1 Data Cache Size: %d KB\n",
3294	(uECX >> 0) & 0xff,
3295	(uECX >> 8) & 0xff,
3296	getCacheAss((uECX >> 16) & 0xff, sz1),
3297	(uECX >> 24) & 0xff);
3298	}
3299
3300	if (iVerbosity && cExtMax >= 6)
3301	{
3302	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3303	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3304	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3305
3306	pHlp->pfnPrintf(pHlp,
3307	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3308	"L2 TLB 2/4M Data: %s %4d entries\n",
3309	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3310	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3311	pHlp->pfnPrintf(pHlp,
3312	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
3313	"L2 TLB 4K Data: %s %4d entries\n",
3314	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3315	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3316	pHlp->pfnPrintf(pHlp,
3317	"L2 Cache Line Size: %d bytes\n"
3318	"L2 Cache Lines Per Tag: %d\n"
3319	"L2 Cache Associativity: %s\n"
3320	"L2 Cache Size: %d KB\n",
3321	(uEDX >> 0) & 0xff,
3322	(uEDX >> 8) & 0xf,
3323	getL2CacheAss((uEDX >> 12) & 0xf),
3324	(uEDX >> 16) & 0xffff);
3325	}
3326
3327	if (iVerbosity && cExtMax >= 7)
3328	{
3329	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3330
3331	pHlp->pfnPrintf(pHlp, "APM Features: ");
3332	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3333	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3334	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3335	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3336	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3337	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3338	for (unsigned iBit = 6; iBit < 32; iBit++)
3339	if (uEDX & RT_BIT(iBit))
3340	pHlp->pfnPrintf(pHlp, " %d", iBit);
3341	pHlp->pfnPrintf(pHlp, "\n");
3342	}
3343
3344	if (iVerbosity && cExtMax >= 8)
3345	{
3346	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3347	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3348
3349	pHlp->pfnPrintf(pHlp,
3350	"Physical Address Width: %d bits\n"
3351	"Virtual Address Width: %d bits\n"
3352	"Guest Physical Address Width: %d bits\n",
3353	(uEAX >> 0) & 0xff,
3354	(uEAX >> 8) & 0xff,
3355	(uEAX >> 16) & 0xff);
3356	pHlp->pfnPrintf(pHlp,
3357	"Physical Core Count: %d\n",
3358	(uECX >> 0) & 0xff);
3359	}
3360
3361
3362	/*
3363	* Centaur.
3364	*/
3365	unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3366
3367	pHlp->pfnPrintf(pHlp,
3368	"\n"
3369	" RAW Centaur CPUIDs\n"
3370	" Function eax ebx ecx edx\n");
3371	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3372	{
3373	Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3374	ASMCpuId(0xc0000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3375
3376	pHlp->pfnPrintf(pHlp,
3377	"Gst: %08x %08x %08x %08x %08x%s\n"
3378	"Hst: %08x %08x %08x %08x\n",
3379	0xc0000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3380	i <= cCentaurMax ? "" : "*",
3381	Host.eax, Host.ebx, Host.ecx, Host.edx);
3382	}
3383
3384	/*
3385	* Understandable output
3386	*/
3387	if (iVerbosity)
3388	{
3389	Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3390	pHlp->pfnPrintf(pHlp,
3391	"Centaur Supports: 0xc0000000-%#010x\n",
3392	Guest.eax);
3393	}
3394
3395	if (iVerbosity && cCentaurMax >= 1)
3396	{
3397	ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3398	uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3399	uint32_t uEdxHst = Host.edx;
3400
3401	if (iVerbosity == 1)
3402	{
3403	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3404	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3405	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3406	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3407	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3408	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3409	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3410	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3411	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3412	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3413	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3414	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3415	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3416	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3417	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3418	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3419	for (unsigned iBit = 14; iBit < 32; iBit++)
3420	if (uEdxGst & RT_BIT(iBit))
3421	pHlp->pfnPrintf(pHlp, " %d", iBit);
3422	pHlp->pfnPrintf(pHlp, "\n");
3423	}
3424	else
3425	{
3426	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3427	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3428	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3429	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3430	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3431	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3432	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3433	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3434	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3435	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3436	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3437	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3438	pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3439	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3440	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3441	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3442	for (unsigned iBit = 14; iBit < 32; iBit++)
3443	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
3444	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3445	pHlp->pfnPrintf(pHlp, "\n");
3446	}
3447	}
3448	}
3449
3450
3451	/**
3452	* Structure used when disassembling and instructions in DBGF.
3453	* This is used so the reader function can get the stuff it needs.
3454	*/
3455	typedef struct CPUMDISASSTATE
3456	{
3457	/** Pointer to the CPU structure. */
3458	PDISCPUSTATE pCpu;
3459	/** The VM handle. */
3460	PVM pVM;
3461	/** The VMCPU handle. */
3462	PVMCPU pVCpu;
3463	/** Pointer to the first byte in the segment. */
3464	RTGCUINTPTR GCPtrSegBase;
3465	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3466	RTGCUINTPTR GCPtrSegEnd;
3467	/** The size of the segment minus 1. */
3468	RTGCUINTPTR cbSegLimit;
3469	/** Pointer to the current page - R3 Ptr. */
3470	void const *pvPageR3;
3471	/** Pointer to the current page - GC Ptr. */
3472	RTGCPTR pvPageGC;
3473	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3474	PGMPAGEMAPLOCK PageMapLock;
3475	/** Whether the PageMapLock is valid or not. */
3476	bool fLocked;
3477	/** 64 bits mode or not. */
3478	bool f64Bits;
3479	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3480
3481
3482	/**
3483	* Instruction reader.
3484	*
3485	* @returns VBox status code.
3486	* @param PtrSrc Address to read from.
3487	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
3488	* @param pu8Dst Where to store the bytes.
3489	* @param cbRead Number of bytes to read.
3490	* @param uDisCpu Pointer to the disassembler cpu state.
3491	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
3492	*/
3493	static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, unsigned cbRead, void uDisCpu)
3494	{
3495	PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
3496	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
3497	Assert(cbRead > 0);
3498	for (;;)
3499	{
3500	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
3501
3502	/* Need to update the page translation? */
3503	if ( !pState->pvPageR3
3504	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3505	{
3506	int rc = VINF_SUCCESS;
3507
3508	/* translate the address */
3509	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3510	if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3511	&& !HWACCMIsEnabled(pState->pVM))
3512	{
3513	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3514	if (!pState->pvPageR3)
3515	rc = VERR_INVALID_POINTER;
3516	}
3517	else
3518	{
3519	/* Release mapping lock previously acquired. */
3520	if (pState->fLocked)
3521	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3522	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3523	pState->fLocked = RT_SUCCESS_NP(rc);
3524	}
3525	if (RT_FAILURE(rc))
3526	{
3527	pState->pvPageR3 = NULL;
3528	return rc;
3529	}
3530	}
3531
3532	/* check the segment limit */
3533	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
3534	return VERR_OUT_OF_SELECTOR_BOUNDS;
3535
3536	/* calc how much we can read */
3537	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3538	if (!pState->f64Bits)
3539	{
3540	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3541	if (cb > cbSeg && cbSeg)
3542	cb = cbSeg;
3543	}
3544	if (cb > cbRead)
3545	cb = cbRead;
3546
3547	/* read and advance */
3548	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3549	cbRead -= cb;
3550	if (!cbRead)
3551	return VINF_SUCCESS;
3552	pu8Dst += cb;
3553	PtrSrc += cb;
3554	}
3555	}
3556
3557
3558	/**
3559	* Disassemble an instruction and return the information in the provided structure.
3560	*
3561	* @returns VBox status code.
3562	* @param pVM VM Handle
3563	* @param pVCpu VMCPU Handle
3564	* @param pCtx CPU context
3565	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3566	* @param pCpu Disassembly state
3567	* @param pszPrefix String prefix for logging (debug only)
3568	*
3569	*/
3570	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
3571	{
3572	CPUMDISASSTATE State;
3573	int rc;
3574
3575	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3576	State.pCpu = pCpu;
3577	State.pvPageGC = 0;
3578	State.pvPageR3 = NULL;
3579	State.pVM = pVM;
3580	State.pVCpu = pVCpu;
3581	State.fLocked = false;
3582	State.f64Bits = false;
3583
3584	/*
3585	* Get selector information.
3586	*/
3587	if ( (pCtx->cr0 & X86_CR0_PE)
3588	&& pCtx->eflags.Bits.u1VM == 0)
3589	{
3590	if (CPUMAreHiddenSelRegsValid(pVCpu))
3591	{
3592	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
3593	State.GCPtrSegBase = pCtx->csHid.u64Base;
3594	State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
3595	State.cbSegLimit = pCtx->csHid.u32Limit;
3596	pCpu->mode = (State.f64Bits)
3597	? CPUMODE_64BIT
3598	: pCtx->csHid.Attr.n.u1DefBig
3599	? CPUMODE_32BIT
3600	: CPUMODE_16BIT;
3601	}
3602	else
3603	{
3604	DBGFSELINFO SelInfo;
3605
3606	rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
3607	if (RT_FAILURE(rc))
3608	{
3609	AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3610	return rc;
3611	}
3612
3613	/*
3614	* Validate the selector.
3615	*/
3616	rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
3617	if (RT_FAILURE(rc))
3618	{
3619	AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3620	return rc;
3621	}
3622	State.GCPtrSegBase = SelInfo.GCPtrBase;
3623	State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
3624	State.cbSegLimit = SelInfo.cbLimit;
3625	pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
3626	}
3627	}
3628	else
3629	{
3630	/* real or V86 mode */
3631	pCpu->mode = CPUMODE_16BIT;
3632	State.GCPtrSegBase = pCtx->cs * 16;
3633	State.GCPtrSegEnd = 0xFFFFFFFF;
3634	State.cbSegLimit = 0xFFFFFFFF;
3635	}
3636
3637	/*
3638	* Disassemble the instruction.
3639	*/
3640	pCpu->pfnReadBytes = cpumR3DisasInstrRead;
3641	pCpu->apvUserData[0] = &State;
3642
3643	uint32_t cbInstr;
3644	#ifndef LOG_ENABLED
3645	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
3646	if (RT_SUCCESS(rc))
3647	{
3648	#else
3649	char szOutput[160];
3650	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
3651	if (RT_SUCCESS(rc))
3652	{
3653	/* log it */
3654	if (pszPrefix)
3655	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3656	else
3657	Log(("%s", szOutput));
3658	#endif
3659	rc = VINF_SUCCESS;
3660	}
3661	else
3662	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
3663
3664	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
3665	if (State.fLocked)
3666	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3667
3668	return rc;
3669	}
3670
3671	#ifdef DEBUG
3672
3673	/**
3674	* Disassemble an instruction and dump it to the log
3675	*
3676	* @returns VBox status code.
3677	* @param pVM VM Handle
3678	* @param pVCpu VMCPU Handle
3679	* @param pCtx CPU context
3680	* @param pc GC instruction pointer
3681	* @param pszPrefix String prefix for logging
3682	*
3683	* @deprecated Use DBGFR3DisasInstrCurrentLog().
3684	*/
3685	VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
3686	{
3687	DISCPUSTATE Cpu;
3688	CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
3689	}
3690
3691
3692	/**
3693	* Debug helper - Saves guest context on raw mode entry (for fatal dump)
3694	*
3695	* @internal
3696	*/
3697	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
3698	{
3699	/** @todo SMP support!! */
3700	pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
3701	}
3702
3703	#endif /* DEBUG */
3704
3705	/**
3706	* API for controlling a few of the CPU features found in CR4.
3707	*
3708	* Currently only X86_CR4_TSD is accepted as input.
3709	*
3710	* @returns VBox status code.
3711	*
3712	* @param pVM The VM handle.
3713	* @param fOr The CR4 OR mask.
3714	* @param fAnd The CR4 AND mask.
3715	*/
3716	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3717	{
3718	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3719	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3720
3721	pVM->cpum.s.CR4.OrMask &= fAnd;
3722	pVM->cpum.s.CR4.OrMask \|= fOr;
3723
3724	return VINF_SUCCESS;
3725	}
3726
3727
3728	/**
3729	* Gets a pointer to the array of standard CPUID leaves.
3730	*
3731	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
3732	*
3733	* @returns Pointer to the standard CPUID leaves (read-only).
3734	* @param pVM The VM handle.
3735	* @remark Intended for PATM.
3736	*/
3737	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
3738	{
3739	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
3740	}
3741
3742
3743	/**
3744	* Gets a pointer to the array of extended CPUID leaves.
3745	*
3746	* CPUMGetGuestCpuIdExtMax() give the size of the array.
3747	*
3748	* @returns Pointer to the extended CPUID leaves (read-only).
3749	* @param pVM The VM handle.
3750	* @remark Intended for PATM.
3751	*/
3752	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
3753	{
3754	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
3755	}
3756
3757
3758	/**
3759	* Gets a pointer to the array of centaur CPUID leaves.
3760	*
3761	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
3762	*
3763	* @returns Pointer to the centaur CPUID leaves (read-only).
3764	* @param pVM The VM handle.
3765	* @remark Intended for PATM.
3766	*/
3767	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
3768	{
3769	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
3770	}
3771
3772
3773	/**
3774	* Gets a pointer to the default CPUID leaf.
3775	*
3776	* @returns Pointer to the default CPUID leaf (read-only).
3777	* @param pVM The VM handle.
3778	* @remark Intended for PATM.
3779	*/
3780	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
3781	{
3782	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
3783	}
3784
3785
3786	/**
3787	* Transforms the guest CPU state to raw-ring mode.
3788	*
3789	* This function will change the any of the cs and ss register with DPL=0 to DPL=1.
3790	*
3791	* @returns VBox status. (recompiler failure)
3792	* @param pVCpu The VMCPU handle.
3793	* @param pCtxCore The context core (for trap usage).
3794	* @see @ref pg_raw
3795	*/
3796	VMMR3DECL(int) CPUMR3RawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
3797	{
3798	PVM pVM = pVCpu->CTX_SUFF(pVM);
3799
3800	Assert(!pVCpu->cpum.s.fRawEntered);
3801	Assert(!pVCpu->cpum.s.fRemEntered);
3802	if (!pCtxCore)
3803	pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
3804
3805	/*
3806	* Are we in Ring-0?
3807	*/
3808	if ( pCtxCore->ss && (pCtxCore->ss & X86_SEL_RPL) == 0
3809	&& !pCtxCore->eflags.Bits.u1VM)
3810	{
3811	/*
3812	* Enter execution mode.
3813	*/
3814	PATMRawEnter(pVM, pCtxCore);
3815
3816	/*
3817	* Set CPL to Ring-1.
3818	*/
3819	pCtxCore->ss \|= 1;
3820	if (pCtxCore->cs && (pCtxCore->cs & X86_SEL_RPL) == 0)
3821	pCtxCore->cs \|= 1;
3822	}
3823	else
3824	{
3825	AssertMsg((pCtxCore->ss & X86_SEL_RPL) >= 2 \|\| pCtxCore->eflags.Bits.u1VM,
3826	("ring-1 code not supported\n"));
3827	/*
3828	* PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
3829	*/
3830	PATMRawEnter(pVM, pCtxCore);
3831	}
3832
3833	/*
3834	* Invalidate the hidden registers.
3835	*/
3836	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3837
3838	/*
3839	* Assert sanity.
3840	*/
3841	AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
3842	AssertReleaseMsg( pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL)
3843	\|\| pCtxCore->eflags.Bits.u1VM,
3844	("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
3845	Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)) == (X86_CR0_PG \| X86_CR0_PE \| X86_CR0_WP));
3846
3847	pCtxCore->eflags.u32 \|= X86_EFL_IF; /* paranoia */
3848
3849	pVCpu->cpum.s.fRawEntered = true;
3850	return VINF_SUCCESS;
3851	}
3852
3853
3854	/**
3855	* Transforms the guest CPU state from raw-ring mode to correct values.
3856	*
3857	* This function will change any selector registers with DPL=1 to DPL=0.
3858	*
3859	* @returns Adjusted rc.
3860	* @param pVCpu The VMCPU handle.
3861	* @param rc Raw mode return code
3862	* @param pCtxCore The context core (for trap usage).
3863	* @see @ref pg_raw
3864	*/
3865	VMMR3DECL(int) CPUMR3RawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
3866	{
3867	PVM pVM = pVCpu->CTX_SUFF(pVM);
3868
3869	/*
3870	* Don't leave if we've already left (in GC).
3871	*/
3872	Assert(pVCpu->cpum.s.fRawEntered);
3873	Assert(!pVCpu->cpum.s.fRemEntered);
3874	if (!pVCpu->cpum.s.fRawEntered)
3875	return rc;
3876	pVCpu->cpum.s.fRawEntered = false;
3877
3878	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3879	if (!pCtxCore)
3880	pCtxCore = CPUMCTX2CORE(pCtx);
3881	Assert(pCtxCore->eflags.Bits.u1VM \|\| (pCtxCore->ss & X86_SEL_RPL));
3882	AssertMsg(pCtxCore->eflags.Bits.u1VM \|\| pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL),
3883	("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
3884
3885	/*
3886	* Are we executing in raw ring-1?
3887	*/
3888	if ( (pCtxCore->ss & X86_SEL_RPL) == 1
3889	&& !pCtxCore->eflags.Bits.u1VM)
3890	{
3891	/*
3892	* Leave execution mode.
3893	*/
3894	PATMRawLeave(pVM, pCtxCore, rc);
3895	/* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
3896	/** @todo See what happens if we remove this. */
3897	if ((pCtxCore->ds & X86_SEL_RPL) == 1)
3898	pCtxCore->ds &= ~X86_SEL_RPL;
3899	if ((pCtxCore->es & X86_SEL_RPL) == 1)
3900	pCtxCore->es &= ~X86_SEL_RPL;
3901	if ((pCtxCore->fs & X86_SEL_RPL) == 1)
3902	pCtxCore->fs &= ~X86_SEL_RPL;
3903	if ((pCtxCore->gs & X86_SEL_RPL) == 1)
3904	pCtxCore->gs &= ~X86_SEL_RPL;
3905
3906	/*
3907	* Ring-1 selector => Ring-0.
3908	*/
3909	pCtxCore->ss &= ~X86_SEL_RPL;
3910	if ((pCtxCore->cs & X86_SEL_RPL) == 1)
3911	pCtxCore->cs &= ~X86_SEL_RPL;
3912	}
3913	else
3914	{
3915	/*
3916	* PATM is taking care of the IOPL and IF flags for us.
3917	*/
3918	PATMRawLeave(pVM, pCtxCore, rc);
3919	if (!pCtxCore->eflags.Bits.u1VM)
3920	{
3921	/** @todo See what happens if we remove this. */
3922	if ((pCtxCore->ds & X86_SEL_RPL) == 1)
3923	pCtxCore->ds &= ~X86_SEL_RPL;
3924	if ((pCtxCore->es & X86_SEL_RPL) == 1)
3925	pCtxCore->es &= ~X86_SEL_RPL;
3926	if ((pCtxCore->fs & X86_SEL_RPL) == 1)
3927	pCtxCore->fs &= ~X86_SEL_RPL;
3928	if ((pCtxCore->gs & X86_SEL_RPL) == 1)
3929	pCtxCore->gs &= ~X86_SEL_RPL;
3930	}
3931	}
3932
3933	return rc;
3934	}
3935
3936
3937	/**
3938	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
3939	*
3940	* Only REM should ever call this function!
3941	*
3942	* @returns The changed flags.
3943	* @param pVCpu The VMCPU handle.
3944	* @param puCpl Where to return the current privilege level (CPL).
3945	*/
3946	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
3947	{
3948	Assert(!pVCpu->cpum.s.fRawEntered);
3949	Assert(!pVCpu->cpum.s.fRemEntered);
3950
3951	/*
3952	* Get the CPL first.
3953	*/
3954	*puCpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.s.Guest));
3955
3956	/*
3957	* Get and reset the flags, leaving CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID set.
3958	*/
3959	uint32_t fFlags = pVCpu->cpum.s.fChanged;
3960	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID; /* leave it set */
3961
3962	/** @todo change the switcher to use the fChanged flags. */
3963	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
3964	{
3965	fFlags \|= CPUM_CHANGED_FPU_REM;
3966	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
3967	}
3968
3969	pVCpu->cpum.s.fRemEntered = true;
3970	return fFlags;
3971	}
3972
3973
3974	/**
3975	* Leaves REM and works the CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID flag.
3976	*
3977	* @param pVCpu The virtual CPU handle.
3978	* @param fNoOutOfSyncSels This is @c false if there are out of sync
3979	* registers.
3980	*/
3981	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
3982	{
3983	Assert(!pVCpu->cpum.s.fRawEntered);
3984	Assert(pVCpu->cpum.s.fRemEntered);
3985
3986	if (fNoOutOfSyncSels)
3987	pVCpu->cpum.s.fChanged &= ~CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3988	else
3989	pVCpu->cpum.s.fChanged \|= ~CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3990
3991	pVCpu->cpum.s.fRemEntered = false;
3992	}
3993

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 38838

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