CPUM.cpp@ 78126

Last change on this file since 78126 was 76993, checked in by vboxsync, 6 years ago
VMM: Nested VMX: bugref:9180 Allowing fetching VM-exit names from ring-0 as well. Various naming cleanups. Added HMDumpHwvirtVmxState() to be able to dump virtual VMCS state from ring-0 as well. Remove unusued HMIsVmxSupported() function.
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File size: 219.0 KB

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1	/* $Id: CPUM.cpp 76993 2019-01-25 14:34:46Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*
33	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34	*
35	* TODO: proper write up, currently just some notes.
36	*
37	* The ring-0 FPU handling per OS:
38	*
39	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
40	* convention (Visual C++ doesn't seem to have a way to disable
41	* generating such code either), so CR0.TS/EM are always zero from what I
42	* can tell. We are also forced to always load/save the guest XMM0-XMM15
43	* registers when entering/leaving guest context. Interrupt handlers
44	* using FPU/SSE will offically have call save and restore functions
45	* exported by the kernel, if the really really have to use the state.
46	*
47	* - 32-bit windows does lazy FPU handling, I think, probably including
48	* lazying saving. The Windows Internals book states that it's a bad
49	* idea to use the FPU in kernel space. However, it looks like it will
50	* restore the FPU state of the current thread in case of a kernel \#NM.
51	* Interrupt handlers should be same as for 64-bit.
52	*
53	* - Darwin allows taking \#NM in kernel space, restoring current thread's
54	* state if I read the code correctly. It saves the FPU state of the
55	* outgoing thread, and uses CR0.TS to lazily load the state of the
56	* incoming one. No idea yet how the FPU is treated by interrupt
57	* handlers, i.e. whether they are allowed to disable the state or
58	* something.
59	*
60	* - Linux also allows \#NM in kernel space (don't know since when), and
61	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62	* loads the incoming unless configured to agressivly load it. Interrupt
63	* handlers can ask whether they're allowed to use the FPU, and may
64	* freely trash the state if Linux thinks it has saved the thread's state
65	* already. This is a problem.
66	*
67	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68	* context. When switching threads, the kernel will save the state of
69	* the outgoing thread and lazy load the incoming one using CR0.TS.
70	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
71	* to do stuff, HAT are among the users. The routines there will
72	* manually clear CR0.TS and save the XMM registers they use only if
73	* CR0.TS was zero upon entry. They will skip it when not, because as
74	* mentioned above, the FPU state is saved when switching away from a
75	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76	* preserve. This is a problem if we restore CR0.TS to 1 after loading
77	* the guest state.
78	*
79	* - FreeBSD - no idea yet.
80	*
81	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83	* FPU states.
84	*
85	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86	* saving and restoring the host and guest states. The motivation for this
87	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88	*
89	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90	* state and only restore it once we've restore the host FPU state. This has the
91	* accidental side effect of triggering Solaris to preserve XMM registers in
92	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94	*
95	*
96	* @section sec_cpum_logging Logging Level Assignments.
97	*
98	* Following log level assignments:
99	* - Log6 is used for FPU state management.
100	* - Log7 is used for FPU state actualization.
101	*
102	*/
103
104
105	/*********************************************************************************************************************************
106	* Header Files *
107	*********************************************************************************************************************************/
108	#define LOG_GROUP LOG_GROUP_CPUM
109	#include <VBox/vmm/cpum.h>
110	#include <VBox/vmm/cpumdis.h>
111	#include <VBox/vmm/cpumctx-v1_6.h>
112	#include <VBox/vmm/pgm.h>
113	#include <VBox/vmm/apic.h>
114	#include <VBox/vmm/mm.h>
115	#include <VBox/vmm/em.h>
116	#include <VBox/vmm/iem.h>
117	#include <VBox/vmm/selm.h>
118	#include <VBox/vmm/dbgf.h>
119	#include <VBox/vmm/patm.h>
120	#include <VBox/vmm/hm.h>
121	#include <VBox/vmm/ssm.h>
122	#include "CPUMInternal.h"
123	#include <VBox/vmm/vm.h>
124
125	#include <VBox/param.h>
126	#include <VBox/dis.h>
127	#include <VBox/err.h>
128	#include <VBox/log.h>
129	#include <iprt/asm-amd64-x86.h>
130	#include <iprt/assert.h>
131	#include <iprt/cpuset.h>
132	#include <iprt/mem.h>
133	#include <iprt/mp.h>
134	#include <iprt/string.h>
135
136
137	/*********************************************************************************************************************************
138	* Defined Constants And Macros *
139	*********************************************************************************************************************************/
140	/**
141	* This was used in the saved state up to the early life of version 14.
142	*
143	* It indicates that we may have some out-of-sync hidden segement registers.
144	* It is only relevant for raw-mode.
145	*/
146	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
147
148
149	/*********************************************************************************************************************************
150	* Structures and Typedefs *
151	*********************************************************************************************************************************/
152
153	/**
154	* What kind of cpu info dump to perform.
155	*/
156	typedef enum CPUMDUMPTYPE
157	{
158	CPUMDUMPTYPE_TERSE,
159	CPUMDUMPTYPE_DEFAULT,
160	CPUMDUMPTYPE_VERBOSE
161	} CPUMDUMPTYPE;
162	/** Pointer to a cpu info dump type. */
163	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
164
165
166	/*********************************************************************************************************************************
167	* Internal Functions *
168	*********************************************************************************************************************************/
169	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
170	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
171	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
172	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
173	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
174	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
179	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
180
181
182	/*********************************************************************************************************************************
183	* Global Variables *
184	*********************************************************************************************************************************/
185	/** Saved state field descriptors for CPUMCTX. */
186	static const SSMFIELD g_aCpumCtxFields[] =
187	{
188	SSMFIELD_ENTRY( CPUMCTX, rdi),
189	SSMFIELD_ENTRY( CPUMCTX, rsi),
190	SSMFIELD_ENTRY( CPUMCTX, rbp),
191	SSMFIELD_ENTRY( CPUMCTX, rax),
192	SSMFIELD_ENTRY( CPUMCTX, rbx),
193	SSMFIELD_ENTRY( CPUMCTX, rdx),
194	SSMFIELD_ENTRY( CPUMCTX, rcx),
195	SSMFIELD_ENTRY( CPUMCTX, rsp),
196	SSMFIELD_ENTRY( CPUMCTX, rflags),
197	SSMFIELD_ENTRY( CPUMCTX, rip),
198	SSMFIELD_ENTRY( CPUMCTX, r8),
199	SSMFIELD_ENTRY( CPUMCTX, r9),
200	SSMFIELD_ENTRY( CPUMCTX, r10),
201	SSMFIELD_ENTRY( CPUMCTX, r11),
202	SSMFIELD_ENTRY( CPUMCTX, r12),
203	SSMFIELD_ENTRY( CPUMCTX, r13),
204	SSMFIELD_ENTRY( CPUMCTX, r14),
205	SSMFIELD_ENTRY( CPUMCTX, r15),
206	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
207	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
208	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
209	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
210	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
211	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
212	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
213	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
214	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
215	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
216	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
217	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
218	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
219	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
220	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
221	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
222	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
223	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
224	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
225	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
226	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
227	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
228	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
229	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
230	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, cr0),
243	SSMFIELD_ENTRY( CPUMCTX, cr2),
244	SSMFIELD_ENTRY( CPUMCTX, cr3),
245	SSMFIELD_ENTRY( CPUMCTX, cr4),
246	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
247	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
248	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
249	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
250	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
251	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
252	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
253	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
254	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
255	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
256	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
257	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
258	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
259	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
260	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
261	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
262	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
263	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
264	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
265	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
266	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
267	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
268	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
269	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
270	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
271	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
272	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
273	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
274	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
275	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
276	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
277	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
278	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
279	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
280	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
281	SSMFIELD_ENTRY_TERM()
282	};
283
284	/** Saved state field descriptors for SVM nested hardware-virtualization
285	* Host State. */
286	static const SSMFIELD g_aSvmHwvirtHostState[] =
287	{
288	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
289	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
290	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
291	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
292	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
293	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
294	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
295	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
296	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
297	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
298	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
299	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
300	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
301	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
302	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
303	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
304	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
305	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
306	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
307	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
308	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
309	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
310	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
311	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
312	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
313	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
314	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
315	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
316	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
317	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
318	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
319	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
320	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
321	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
322	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
323	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
324	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
325	SSMFIELD_ENTRY_TERM()
326	};
327
328	/** Saved state field descriptors for CPUMCTX. */
329	static const SSMFIELD g_aCpumX87Fields[] =
330	{
331	SSMFIELD_ENTRY( X86FXSTATE, FCW),
332	SSMFIELD_ENTRY( X86FXSTATE, FSW),
333	SSMFIELD_ENTRY( X86FXSTATE, FTW),
334	SSMFIELD_ENTRY( X86FXSTATE, FOP),
335	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
336	SSMFIELD_ENTRY( X86FXSTATE, CS),
337	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
338	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
339	SSMFIELD_ENTRY( X86FXSTATE, DS),
340	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
341	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
342	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
343	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
344	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
345	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
346	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
347	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
348	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
349	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
350	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
351	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
352	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
353	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
354	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
355	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
356	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
357	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
358	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
359	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
360	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
361	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
362	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
363	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
364	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
365	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
366	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
367	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
368	SSMFIELD_ENTRY_TERM()
369	};
370
371	/** Saved state field descriptors for X86XSAVEHDR. */
372	static const SSMFIELD g_aCpumXSaveHdrFields[] =
373	{
374	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
375	SSMFIELD_ENTRY_TERM()
376	};
377
378	/** Saved state field descriptors for X86XSAVEYMMHI. */
379	static const SSMFIELD g_aCpumYmmHiFields[] =
380	{
381	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
382	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
383	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
384	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
385	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
386	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
387	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
388	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
389	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
390	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
391	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
392	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
393	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
394	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
395	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
396	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
397	SSMFIELD_ENTRY_TERM()
398	};
399
400	/** Saved state field descriptors for X86XSAVEBNDREGS. */
401	static const SSMFIELD g_aCpumBndRegsFields[] =
402	{
403	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
404	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
405	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
406	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
407	SSMFIELD_ENTRY_TERM()
408	};
409
410	/** Saved state field descriptors for X86XSAVEBNDCFG. */
411	static const SSMFIELD g_aCpumBndCfgFields[] =
412	{
413	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
414	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
415	SSMFIELD_ENTRY_TERM()
416	};
417
418	#if 0 /** @todo */
419	/** Saved state field descriptors for X86XSAVEOPMASK. */
420	static const SSMFIELD g_aCpumOpmaskFields[] =
421	{
422	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
423	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
424	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
425	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
426	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
427	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
428	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
429	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
430	SSMFIELD_ENTRY_TERM()
431	};
432	#endif
433
434	/** Saved state field descriptors for X86XSAVEZMMHI256. */
435	static const SSMFIELD g_aCpumZmmHi256Fields[] =
436	{
437	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
438	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
439	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
440	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
441	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
442	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
443	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
444	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
445	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
446	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
447	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
448	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
449	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
450	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
451	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
452	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
453	SSMFIELD_ENTRY_TERM()
454	};
455
456	/** Saved state field descriptors for X86XSAVEZMM16HI. */
457	static const SSMFIELD g_aCpumZmm16HiFields[] =
458	{
459	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
460	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
461	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
462	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
463	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
464	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
465	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
466	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
467	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
468	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
469	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
470	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
471	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
472	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
473	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
474	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
475	SSMFIELD_ENTRY_TERM()
476	};
477
478
479
480	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
481	* registeres changed. */
482	static const SSMFIELD g_aCpumX87FieldsMem[] =
483	{
484	SSMFIELD_ENTRY( X86FXSTATE, FCW),
485	SSMFIELD_ENTRY( X86FXSTATE, FSW),
486	SSMFIELD_ENTRY( X86FXSTATE, FTW),
487	SSMFIELD_ENTRY( X86FXSTATE, FOP),
488	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
489	SSMFIELD_ENTRY( X86FXSTATE, CS),
490	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
491	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
492	SSMFIELD_ENTRY( X86FXSTATE, DS),
493	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
494	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
495	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
496	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
497	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
498	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
499	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
500	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
501	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
502	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
503	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
504	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
505	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
506	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
507	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
508	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
509	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
510	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
511	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
512	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
513	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
514	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
515	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
516	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
517	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
518	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
519	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
520	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
521	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
522	};
523
524	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
525	* registeres changed. */
526	static const SSMFIELD g_aCpumCtxFieldsMem[] =
527	{
528	SSMFIELD_ENTRY( CPUMCTX, rdi),
529	SSMFIELD_ENTRY( CPUMCTX, rsi),
530	SSMFIELD_ENTRY( CPUMCTX, rbp),
531	SSMFIELD_ENTRY( CPUMCTX, rax),
532	SSMFIELD_ENTRY( CPUMCTX, rbx),
533	SSMFIELD_ENTRY( CPUMCTX, rdx),
534	SSMFIELD_ENTRY( CPUMCTX, rcx),
535	SSMFIELD_ENTRY( CPUMCTX, rsp),
536	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
537	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
538	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
539	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
540	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
541	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
542	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
543	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
544	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
545	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
546	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
547	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
548	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
549	SSMFIELD_ENTRY( CPUMCTX, rflags),
550	SSMFIELD_ENTRY( CPUMCTX, rip),
551	SSMFIELD_ENTRY( CPUMCTX, r8),
552	SSMFIELD_ENTRY( CPUMCTX, r9),
553	SSMFIELD_ENTRY( CPUMCTX, r10),
554	SSMFIELD_ENTRY( CPUMCTX, r11),
555	SSMFIELD_ENTRY( CPUMCTX, r12),
556	SSMFIELD_ENTRY( CPUMCTX, r13),
557	SSMFIELD_ENTRY( CPUMCTX, r14),
558	SSMFIELD_ENTRY( CPUMCTX, r15),
559	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
560	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
561	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
562	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
563	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
564	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
565	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
566	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
567	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
568	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
569	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
570	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
571	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
572	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
573	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
574	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
575	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
576	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
577	SSMFIELD_ENTRY( CPUMCTX, cr0),
578	SSMFIELD_ENTRY( CPUMCTX, cr2),
579	SSMFIELD_ENTRY( CPUMCTX, cr3),
580	SSMFIELD_ENTRY( CPUMCTX, cr4),
581	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
582	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
583	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
584	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
585	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
586	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
587	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
588	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
589	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
590	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
591	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
592	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
593	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
594	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
595	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
596	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
597	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
598	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
599	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
600	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
601	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
602	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
603	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
604	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
605	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
606	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
607	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
608	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
609	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
610	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
611	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
612	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
613	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
614	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
615	SSMFIELD_ENTRY_TERM()
616	};
617
618	/** Saved state field descriptors for CPUMCTX_VER1_6. */
619	static const SSMFIELD g_aCpumX87FieldsV16[] =
620	{
621	SSMFIELD_ENTRY( X86FXSTATE, FCW),
622	SSMFIELD_ENTRY( X86FXSTATE, FSW),
623	SSMFIELD_ENTRY( X86FXSTATE, FTW),
624	SSMFIELD_ENTRY( X86FXSTATE, FOP),
625	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
626	SSMFIELD_ENTRY( X86FXSTATE, CS),
627	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
628	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
629	SSMFIELD_ENTRY( X86FXSTATE, DS),
630	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
631	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
632	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
633	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
634	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
635	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
636	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
637	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
638	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
639	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
640	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
641	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
642	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
643	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
644	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
645	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
646	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
647	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
648	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
649	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
650	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
651	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
652	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
653	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
654	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
655	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
656	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
657	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
658	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
659	SSMFIELD_ENTRY_TERM()
660	};
661
662	/** Saved state field descriptors for CPUMCTX_VER1_6. */
663	static const SSMFIELD g_aCpumCtxFieldsV16[] =
664	{
665	SSMFIELD_ENTRY( CPUMCTX, rdi),
666	SSMFIELD_ENTRY( CPUMCTX, rsi),
667	SSMFIELD_ENTRY( CPUMCTX, rbp),
668	SSMFIELD_ENTRY( CPUMCTX, rax),
669	SSMFIELD_ENTRY( CPUMCTX, rbx),
670	SSMFIELD_ENTRY( CPUMCTX, rdx),
671	SSMFIELD_ENTRY( CPUMCTX, rcx),
672	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
673	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
674	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
675	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
676	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
677	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
678	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
679	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
680	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
681	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
682	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
683	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
684	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
685	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
686	SSMFIELD_ENTRY( CPUMCTX, rflags),
687	SSMFIELD_ENTRY( CPUMCTX, rip),
688	SSMFIELD_ENTRY( CPUMCTX, r8),
689	SSMFIELD_ENTRY( CPUMCTX, r9),
690	SSMFIELD_ENTRY( CPUMCTX, r10),
691	SSMFIELD_ENTRY( CPUMCTX, r11),
692	SSMFIELD_ENTRY( CPUMCTX, r12),
693	SSMFIELD_ENTRY( CPUMCTX, r13),
694	SSMFIELD_ENTRY( CPUMCTX, r14),
695	SSMFIELD_ENTRY( CPUMCTX, r15),
696	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
697	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
698	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
699	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
700	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
701	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
702	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
703	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
704	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
705	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
706	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
707	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
708	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
709	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
710	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
711	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
712	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
713	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
714	SSMFIELD_ENTRY( CPUMCTX, cr0),
715	SSMFIELD_ENTRY( CPUMCTX, cr2),
716	SSMFIELD_ENTRY( CPUMCTX, cr3),
717	SSMFIELD_ENTRY( CPUMCTX, cr4),
718	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
719	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
720	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
721	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
722	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
723	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
724	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
725	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
726	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
727	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
728	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
729	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
730	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
731	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
732	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
733	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
734	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
735	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
736	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
737	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
738	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
739	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
740	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
741	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
742	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
743	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
744	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
745	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
746	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
747	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
748	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
749	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
750	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
751	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
752	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
753	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
754	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
755	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
756	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
757	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
758	SSMFIELD_ENTRY_TERM()
759	};
760
761
762	/**
763	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
764	*
765	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
766	* (last instruction pointer, last data pointer, last opcode) except when the ES
767	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
768	* clear these registers there is potential, local FPU leakage from a process
769	* using the FPU to another.
770	*
771	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
772	*
773	* @param pVM The cross context VM structure.
774	*/
775	static void cpumR3CheckLeakyFpu(PVM pVM)
776	{
777	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
778	uint32_t const u32Family = u32CpuVersion >> 8;
779	if ( u32Family >= 6 /* K7 and higher */
780	&& ASMIsAmdCpu())
781	{
782	uint32_t cExt = ASMCpuId_EAX(0x80000000);
783	if (ASMIsValidExtRange(cExt))
784	{
785	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
786	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
787	{
788	for (VMCPUID i = 0; i < pVM->cCpus; i++)
789	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
790	Log(("CPUM: Host CPU has leaky fxsave/fxrstor behaviour\n"));
791	}
792	}
793	}
794	}
795
796
797	/**
798	* Frees memory allocated for the SVM hardware virtualization state.
799	*
800	* @param pVM The cross context VM structure.
801	*/
802	static void cpumR3FreeSvmHwVirtState(PVM pVM)
803	{
804	Assert(pVM->cpum.s.GuestFeatures.fSvm);
805	for (VMCPUID i = 0; i < pVM->cCpus; i++)
806	{
807	PVMCPU pVCpu = &pVM->aCpus[i];
808	if (pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3)
809	{
810	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES);
811	pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3 = NULL;
812	}
813	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = NIL_RTHCPHYS;
814
815	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3)
816	{
817	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES);
818	pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3 = NULL;
819	}
820
821	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3)
822	{
823	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES);
824	pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3 = NULL;
825	}
826	}
827	}
828
829
830	/**
831	* Allocates memory for the SVM hardware virtualization state.
832	*
833	* @returns VBox status code.
834	* @param pVM The cross context VM structure.
835	*/
836	static int cpumR3AllocSvmHwVirtState(PVM pVM)
837	{
838	Assert(pVM->cpum.s.GuestFeatures.fSvm);
839
840	int rc = VINF_SUCCESS;
841	LogRel(("CPUM: Allocating %u pages for the nested-guest SVM MSR and IO permission bitmaps\n",
842	pVM->cCpus * (SVM_MSRPM_PAGES + SVM_IOPM_PAGES)));
843	for (VMCPUID i = 0; i < pVM->cCpus; i++)
844	{
845	PVMCPU pVCpu = &pVM->aCpus[i];
846	pVCpu->cpum.s.Guest.hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
847
848	/*
849	* Allocate the nested-guest VMCB.
850	*/
851	SUPPAGE SupNstGstVmcbPage;
852	RT_ZERO(SupNstGstVmcbPage);
853	SupNstGstVmcbPage.Phys = NIL_RTHCPHYS;
854	Assert(SVM_VMCB_PAGES == 1);
855	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
856	rc = SUPR3PageAllocEx(SVM_VMCB_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3,
857	&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR0, &SupNstGstVmcbPage);
858	if (RT_FAILURE(rc))
859	{
860	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
861	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCB\n", pVCpu->idCpu, SVM_VMCB_PAGES));
862	break;
863	}
864	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = SupNstGstVmcbPage.Phys;
865
866	/*
867	* Allocate the MSRPM (MSR Permission bitmap).
868	*/
869	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
870	rc = SUPR3PageAllocEx(SVM_MSRPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3,
871	&pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR0, NULL /* paPages */);
872	if (RT_FAILURE(rc))
873	{
874	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
875	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR permission bitmap\n", pVCpu->idCpu,
876	SVM_MSRPM_PAGES));
877	break;
878	}
879
880	/*
881	* Allocate the IOPM (IO Permission bitmap).
882	*/
883	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
884	rc = SUPR3PageAllocEx(SVM_IOPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3,
885	&pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR0, NULL /* paPages */);
886	if (RT_FAILURE(rc))
887	{
888	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
889	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's IO permission bitmap\n", pVCpu->idCpu,
890	SVM_IOPM_PAGES));
891	break;
892	}
893	}
894
895	/* On any failure, cleanup. */
896	if (RT_FAILURE(rc))
897	cpumR3FreeSvmHwVirtState(pVM);
898
899	return rc;
900	}
901
902
903	/**
904	* Resets per-VCPU SVM hardware virtualization state.
905	*
906	* @param pVCpu The cross context virtual CPU structure.
907	*/
908	DECLINLINE(void) cpumR3ResetSvmHwVirtState(PVMCPU pVCpu)
909	{
910	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
911	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
912	Assert(pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
913
914	memset(pCtx->hwvirt.svm.CTX_SUFF(pVmcb), 0, SVM_VMCB_PAGES << PAGE_SHIFT);
915	pCtx->hwvirt.svm.uMsrHSavePa = 0;
916	pCtx->hwvirt.svm.uPrevPauseTick = 0;
917	}
918
919
920	/**
921	* Frees memory allocated for the VMX hardware virtualization state.
922	*
923	* @param pVM The cross context VM structure.
924	*/
925	static void cpumR3FreeVmxHwVirtState(PVM pVM)
926	{
927	Assert(pVM->cpum.s.GuestFeatures.fVmx);
928	for (VMCPUID i = 0; i < pVM->cCpus; i++)
929	{
930	PVMCPU pVCpu = &pVM->aCpus[i];
931	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3)
932	{
933	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3, VMX_V_VMCS_PAGES);
934	pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3 = NULL;
935	}
936	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pShadowVmcsR3)
937	{
938	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pShadowVmcsR3, VMX_V_VMCS_PAGES);
939	pVCpu->cpum.s.Guest.hwvirt.vmx.pShadowVmcsR3 = NULL;
940	}
941	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pvVirtApicPageR3)
942	{
943	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pvVirtApicPageR3, VMX_V_VIRT_APIC_PAGES);
944	pVCpu->cpum.s.Guest.hwvirt.vmx.pvVirtApicPageR3 = NULL;
945	}
946	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmreadBitmapR3)
947	{
948	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmreadBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_PAGES);
949	pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmreadBitmapR3 = NULL;
950	}
951	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmwriteBitmapR3)
952	{
953	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmwriteBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_PAGES);
954	pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmwriteBitmapR3 = NULL;
955	}
956	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pAutoMsrAreaR3)
957	{
958	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pAutoMsrAreaR3, VMX_V_AUTOMSR_AREA_PAGES);
959	pVCpu->cpum.s.Guest.hwvirt.vmx.pAutoMsrAreaR3 = NULL;
960	}
961	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pvMsrBitmapR3)
962	{
963	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_PAGES);
964	pVCpu->cpum.s.Guest.hwvirt.vmx.pvMsrBitmapR3 = NULL;
965	}
966	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pvIoBitmapR3)
967	{
968	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES);
969	pVCpu->cpum.s.Guest.hwvirt.vmx.pvIoBitmapR3 = NULL;
970	}
971	}
972	}
973
974
975	/**
976	* Allocates memory for the VMX hardware virtualization state.
977	*
978	* @returns VBox status code.
979	* @param pVM The cross context VM structure.
980	*/
981	static int cpumR3AllocVmxHwVirtState(PVM pVM)
982	{
983	int rc = VINF_SUCCESS;
984	LogRel(("CPUM: Allocating %u pages for the nested-guest VMCS and related structures\n",
985	pVM->cCpus * ( VMX_V_VMCS_PAGES + VMX_V_VIRT_APIC_PAGES + VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * 2
986	+ VMX_V_AUTOMSR_AREA_PAGES)));
987	for (VMCPUID i = 0; i < pVM->cCpus; i++)
988	{
989	PVMCPU pVCpu = &pVM->aCpus[i];
990	pVCpu->cpum.s.Guest.hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
991
992	/*
993	* Allocate the nested-guest current VMCS.
994	*/
995	Assert(VMX_V_VMCS_PAGES == 1);
996	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3);
997	rc = SUPR3PageAllocEx(VMX_V_VMCS_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3,
998	&pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR0, NULL /* paPages */);
999	if (RT_FAILURE(rc))
1000	{
1001	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3);
1002	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCS\n", pVCpu->idCpu, VMX_V_VMCS_PAGES));
1003	break;
1004	}
1005
1006	/*
1007	* Allocate the nested-guest shadow VMCS.
1008	*/
1009	Assert(VMX_V_VMCS_PAGES == 1);
1010	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pShadowVmcsR3);
1011	rc = SUPR3PageAllocEx(VMX_V_VMCS_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.vmx.pShadowVmcsR3,
1012	&pVCpu->cpum.s.Guest.hwvirt.vmx.pShadowVmcsR0, NULL /* paPages */);
1013	if (RT_FAILURE(rc))
1014	{
1015	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pShadowVmcsR3);
1016	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's shadow VMCS\n", pVCpu->idCpu, VMX_V_VMCS_PAGES));
1017	break;
1018	}
1019
1020	/*
1021	* Allocate the Virtual-APIC page.
1022	*/
1023	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvVirtApicPageR3);
1024	rc = SUPR3PageAllocEx(VMX_V_VIRT_APIC_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.vmx.pvVirtApicPageR3,
1025	&pVCpu->cpum.s.Guest.hwvirt.vmx.pvVirtApicPageR0, NULL /* paPages */);
1026	if (RT_FAILURE(rc))
1027	{
1028	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvVirtApicPageR3);
1029	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's Virtual-APIC page\n", pVCpu->idCpu,
1030	VMX_V_VIRT_APIC_PAGES));
1031	break;
1032	}
1033
1034	/*
1035	* Allocate the VMREAD-bitmap.
1036	*/
1037	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmreadBitmapR3);
1038	rc = SUPR3PageAllocEx(VMX_V_VMREAD_VMWRITE_BITMAP_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmreadBitmapR3,
1039	&pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmreadBitmapR0, NULL /* paPages */);
1040	if (RT_FAILURE(rc))
1041	{
1042	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmreadBitmapR3);
1043	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMREAD-bitmap\n", pVCpu->idCpu,
1044	VMX_V_VMREAD_VMWRITE_BITMAP_PAGES));
1045	break;
1046	}
1047
1048	/*
1049	* Allocatge the VMWRITE-bitmap.
1050	*/
1051	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmwriteBitmapR3);
1052	rc = SUPR3PageAllocEx(VMX_V_VMREAD_VMWRITE_BITMAP_PAGES, 0 /* fFlags */,
1053	&pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmwriteBitmapR3,
1054	&pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmwriteBitmapR0, NULL /* paPages */);
1055	if (RT_FAILURE(rc))
1056	{
1057	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmwriteBitmapR3);
1058	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMWRITE-bitmap\n", pVCpu->idCpu,
1059	VMX_V_VMREAD_VMWRITE_BITMAP_PAGES));
1060	break;
1061	}
1062
1063	/*
1064	* Allocate the MSR auto-load/store area.
1065	*/
1066	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pAutoMsrAreaR3);
1067	rc = SUPR3PageAllocEx(VMX_V_AUTOMSR_AREA_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.vmx.pAutoMsrAreaR3,
1068	&pVCpu->cpum.s.Guest.hwvirt.vmx.pAutoMsrAreaR0, NULL /* paPages */);
1069	if (RT_FAILURE(rc))
1070	{
1071	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pAutoMsrAreaR3);
1072	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's auto-load/store MSR area\n", pVCpu->idCpu,
1073	VMX_V_AUTOMSR_AREA_PAGES));
1074	break;
1075	}
1076
1077	/*
1078	* Allocate the MSR bitmap.
1079	*/
1080	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvMsrBitmapR3);
1081	rc = SUPR3PageAllocEx(VMX_V_MSR_BITMAP_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.vmx.pvMsrBitmapR3,
1082	&pVCpu->cpum.s.Guest.hwvirt.vmx.pvMsrBitmapR0, NULL /* paPages */);
1083	if (RT_FAILURE(rc))
1084	{
1085	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvMsrBitmapR3);
1086	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR bitmap\n", pVCpu->idCpu,
1087	VMX_V_MSR_BITMAP_PAGES));
1088	break;
1089	}
1090
1091	/*
1092	* Allocate the I/O bitmaps (A and B).
1093	*/
1094	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvIoBitmapR3);
1095	rc = SUPR3PageAllocEx(VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES, 0 /* fFlags */,
1096	(void **)&pVCpu->cpum.s.Guest.hwvirt.vmx.pvIoBitmapR3,
1097	&pVCpu->cpum.s.Guest.hwvirt.vmx.pvIoBitmapR0, NULL /* paPages */);
1098	if (RT_FAILURE(rc))
1099	{
1100	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvIoBitmapR3);
1101	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's I/O bitmaps\n", pVCpu->idCpu,
1102	VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES));
1103	break;
1104	}
1105	}
1106
1107	/* On any failure, cleanup. */
1108	if (RT_FAILURE(rc))
1109	cpumR3FreeVmxHwVirtState(pVM);
1110
1111	return rc;
1112	}
1113
1114
1115	/**
1116	* Resets per-VCPU VMX hardware virtualization state.
1117	*
1118	* @param pVCpu The cross context virtual CPU structure.
1119	*/
1120	DECLINLINE(void) cpumR3ResetVmxHwVirtState(PVMCPU pVCpu)
1121	{
1122	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1123	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1124	Assert(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
1125	Assert(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs));
1126
1127	memset(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs), 0, VMX_V_VMCS_SIZE);
1128	memset(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs), 0, VMX_V_VMCS_SIZE);
1129	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1130	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1131	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1132	pCtx->hwvirt.vmx.fInVmxRootMode = false;
1133	pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1134	/* Don't reset diagnostics here. */
1135	}
1136
1137
1138	/**
1139	* Displays the host and guest VMX features.
1140	*
1141	* @param pVM The cross context VM structure.
1142	* @param pHlp The info helper functions.
1143	* @param pszArgs "terse", "default" or "verbose".
1144	*/
1145	DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1146	{
1147	RT_NOREF(pszArgs);
1148	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
1149	PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
1150	if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
1151	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA
1152	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_SHANGHAI)
1153	{
1154	#define VMXFEATDUMP(a_szDesc, a_Var) \
1155	pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
1156
1157	pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
1158	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1159	VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
1160	/* Basic. */
1161	VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
1162	/* Pin-based controls. */
1163	VMXFEATDUMP("ExtIntExit - External interrupt exiting ", fVmxExtIntExit);
1164	VMXFEATDUMP("NmiExit - NMI exiting ", fVmxNmiExit);
1165	VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
1166	VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
1167	VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
1168	/* Processor-based controls. */
1169	VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
1170	VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
1171	VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
1172	VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
1173	VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
1174	VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
1175	VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
1176	VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1177	VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1178	VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1179	VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1180	VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1181	VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1182	VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1183	VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1184	VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1185	VMXFEATDUMP("MonitorTrapFlag - Monitor trap flag ", fVmxMonitorTrapFlag);
1186	VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1187	VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1188	VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1189	VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1190	/* Secondary processor-based controls. */
1191	VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1192	VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1193	VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1194	VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1195	VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
1196	VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1197	VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1198	VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1199	VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1200	VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1201	VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1202	VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1203	VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1204	VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1205	VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1206	VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1207	VMXFEATDUMP("PML - Page-Modification Log (PML) ", fVmxPml);
1208	VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1209	VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1210	/* VM-entry controls. */
1211	VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1212	VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1213	VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER MSR on VM-entry ", fVmxEntryLoadEferMsr);
1214	VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT MSR on VM-entry ", fVmxEntryLoadPatMsr);
1215	/* VM-exit controls. */
1216	VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1217	VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1218	VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1219	VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT MSR on VM-exit ", fVmxExitSavePatMsr);
1220	VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT MSR on VM-exit ", fVmxExitLoadPatMsr);
1221	VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER MSR on VM-exit ", fVmxExitSaveEferMsr);
1222	VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER MSR on VM-exit ", fVmxExitLoadEferMsr);
1223	VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1224	/* Miscellaneous data. */
1225	VMXFEATDUMP("ExitSaveEferLma - Save IA32_EFER.LMA on VM-exit ", fVmxExitSaveEferLma);
1226	VMXFEATDUMP("IntelPt - Intel PT (Processor Trace) in VMX operation ", fVmxIntelPt);
1227	VMXFEATDUMP("VmwriteAll - Write allowed to read-only VMCS fields ", fVmxVmwriteAll);
1228	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1229	#undef VMXFEATDUMP
1230	}
1231	else
1232	pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1233	}
1234
1235
1236	/**
1237	* Checks whether nested-guest execution using hardware-assisted VMX (e.g, using HM
1238	* or NEM) is allowed.
1239	*
1240	* @returns @c true if hardware-assisted nested-guest execution is allowed, @c false
1241	* otherwise.
1242	* @param pVM The cross context VM structure.
1243	*/
1244	static bool cpumR3IsHwAssistNstGstExecAllowed(PVM pVM)
1245	{
1246	AssertMsg(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET, ("Calling this function too early!\n"));
1247	#ifndef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
1248	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT
1249	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1250	return true;
1251	#else
1252	NOREF(pVM);
1253	#endif
1254	return false;
1255	}
1256
1257
1258	/**
1259	* Initializes the VMX guest MSRs from guest CPU features based on the host MSRs.
1260	*
1261	* @param pVM The cross context VM structure.
1262	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1263	* and no hardware-assisted nested-guest execution is
1264	* possible for this VM.
1265	* @param pGuestFeatures The guest features to use (only VMX features are
1266	* accessed).
1267	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1268	*
1269	* @remarks This function ASSUMES the VMX guest-features are already exploded!
1270	*/
1271	static void cpumR3InitVmxGuestMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PCCPUMFEATURES pGuestFeatures, PVMXMSRS pGuestVmxMsrs)
1272	{
1273	bool const fIsNstGstHwExecAllowed = cpumR3IsHwAssistNstGstExecAllowed(pVM);
1274
1275	Assert(!fIsNstGstHwExecAllowed \|\| pHostVmxMsrs);
1276	Assert(pGuestFeatures->fVmx);
1277
1278	/*
1279	* We don't support the following MSRs yet:
1280	* - True Pin-based VM-execution controls.
1281	* - True Processor-based VM-execution controls.
1282	* - True VM-entry VM-execution controls.
1283	* - True VM-exit VM-execution controls.
1284	* - EPT/VPID capabilities.
1285	*/
1286
1287	/* Feature control. */
1288	pGuestVmxMsrs->u64FeatCtrl = MSR_IA32_FEATURE_CONTROL_LOCK \| MSR_IA32_FEATURE_CONTROL_VMXON;
1289
1290	/* Basic information. */
1291	{
1292	uint64_t const u64Basic = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1293	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1294	\| RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, !pGuestFeatures->fLongMode )
1295	\| RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1296	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1297	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1298	\| RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, 0 );
1299	pGuestVmxMsrs->u64Basic = u64Basic;
1300	}
1301
1302	/* Pin-based VM-execution controls. */
1303	{
1304	uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1305	\| (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1306	\| (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1307	\| (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1308	\| (pGuestFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1309	uint32_t const fAllowed0 = VMX_PIN_CTLS_DEFAULT1;
1310	uint32_t const fAllowed1 = fFeatures \| VMX_PIN_CTLS_DEFAULT1;
1311	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n",
1312	fAllowed0, fAllowed1, fFeatures));
1313	pGuestVmxMsrs->PinCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1314	}
1315
1316	/* Processor-based VM-execution controls. */
1317	{
1318	uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1319	\| (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1320	\| (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1321	\| (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1322	\| (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1323	\| (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1324	\| (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1325	\| (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1326	\| (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1327	\| (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1328	\| (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1329	\| (pGuestFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1330	\| (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1331	\| (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1332	\| (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1333	\| (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1334	\| (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1335	\| (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1336	\| (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1337	\| (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1338	\| (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1339	uint32_t const fAllowed0 = VMX_PROC_CTLS_DEFAULT1;
1340	uint32_t const fAllowed1 = fFeatures \| VMX_PROC_CTLS_DEFAULT1;
1341	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1342	fAllowed1, fFeatures));
1343	pGuestVmxMsrs->ProcCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1344	}
1345
1346	/* Secondary processor-based VM-execution controls. */
1347	if (pGuestFeatures->fVmxSecondaryExecCtls)
1348	{
1349	uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1350	\| (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1351	\| (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1352	\| (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1353	\| (pGuestFeatures->fVmxVirtX2ApicMode << VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT )
1354	\| (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1355	\| (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1356	\| (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT)
1357	\| (pGuestFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1358	\| (pGuestFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1359	\| (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1360	\| (pGuestFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1361	\| (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1362	\| (pGuestFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1363	\| (pGuestFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1364	\| (pGuestFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1365	\| (pGuestFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1366	\| (pGuestFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1367	\| (pGuestFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1368	\| (pGuestFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT );
1369	uint32_t const fAllowed0 = 0;
1370	uint32_t const fAllowed1 = fFeatures;
1371	pGuestVmxMsrs->ProcCtls2.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1372	}
1373
1374	/* VM-exit controls. */
1375	{
1376	uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1377	\| (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1378	\| (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1379	\| (pGuestFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1380	\| (pGuestFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1381	\| (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1382	\| (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1383	\| (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT );
1384	/* Set the default1 class bits. See Intel spec. A.4 "VM-exit Controls". */
1385	uint32_t const fAllowed0 = VMX_EXIT_CTLS_DEFAULT1;
1386	uint32_t const fAllowed1 = fFeatures \| VMX_EXIT_CTLS_DEFAULT1;
1387	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1388	fAllowed1, fFeatures));
1389	pGuestVmxMsrs->ExitCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1390	}
1391
1392	/* VM-entry controls. */
1393	{
1394	uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1395	\| (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1396	\| (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1397	\| (pGuestFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1398	uint32_t const fAllowed0 = VMX_ENTRY_CTLS_DEFAULT1;
1399	uint32_t const fAllowed1 = fFeatures \| VMX_ENTRY_CTLS_DEFAULT1;
1400	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed0=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1401	fAllowed1, fFeatures));
1402	pGuestVmxMsrs->EntryCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1403	}
1404
1405	/* Miscellaneous data. */
1406	{
1407	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Misc : 0;
1408
1409	uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_AUTOMSR_COUNT_MAX);
1410	uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK;
1411	pGuestVmxMsrs->u64Misc = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1412	\| RT_BF_MAKE(VMX_BF_MISC_EXIT_SAVE_EFER_LMA, pGuestFeatures->fVmxExitSaveEferLma )
1413	\| RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState )
1414	\| RT_BF_MAKE(VMX_BF_MISC_INTEL_PT, pGuestFeatures->fVmxIntelPt )
1415	\| RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1416	\| RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1417	\| RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1418	\| RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1419	\| RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pGuestFeatures->fVmxVmwriteAll )
1420	\| RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pGuestFeatures->fVmxEntryInjectSoftInt)
1421	\| RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1422	}
1423
1424	/* CR0 Fixed-0. */
1425	pGuestVmxMsrs->u64Cr0Fixed0 = pGuestFeatures->fVmxUnrestrictedGuest ? VMX_V_CR0_FIXED0_UX: VMX_V_CR0_FIXED0;
1426
1427	/* CR0 Fixed-1. */
1428	{
1429	/*
1430	* All CPUs I've looked at so far report CR0 fixed-1 bits as 0xffffffff.
1431	* This is different from CR4 fixed-1 bits which are reported as per the
1432	* CPU features and/or micro-architecture/generation. Why? Ask Intel.
1433	*/
1434	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr0Fixed1 : 0xffffffff;
1435	pGuestVmxMsrs->u64Cr0Fixed1 = uHostMsr \| VMX_V_CR0_FIXED0; /* Make sure the CR0 MB1 bits are not clear. */
1436	}
1437
1438	/* CR4 Fixed-0. */
1439	pGuestVmxMsrs->u64Cr4Fixed0 = VMX_V_CR4_FIXED0;
1440
1441	/* CR4 Fixed-1. */
1442	{
1443	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr4Fixed1 : CPUMGetGuestCR4ValidMask(pVM);
1444	pGuestVmxMsrs->u64Cr4Fixed1 = uHostMsr \| VMX_V_CR4_FIXED0; /* Make sure the CR4 MB1 bits are not clear. */
1445	}
1446
1447	/* VMCS Enumeration. */
1448	pGuestVmxMsrs->u64VmcsEnum = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1449
1450	/* VM Functions. */
1451	if (pGuestFeatures->fVmxVmFunc)
1452	pGuestVmxMsrs->u64VmFunc = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1453	}
1454
1455
1456	#if 0
1457	/**
1458	* Checks whether the given guest CPU VMX features are compatible with the provided
1459	* base features.
1460	*
1461	* @returns @c true if compatible, @c false otherwise.
1462	* @param pVM The cross context VM structure.
1463	* @param pBase The base VMX CPU features.
1464	* @param pGst The guest VMX CPU features.
1465	*
1466	* @remarks Only VMX feature bits are examined.
1467	*/
1468	static bool cpumR3AreVmxCpuFeaturesCompatible(PVM pVM, PCCPUMFEATURES pBase, PCCPUMFEATURES pGst)
1469	{
1470	if (cpumR3IsHwAssistVmxNstGstExecAllowed(pVM))
1471	{
1472	uint64_t const fBase = ((uint64_t)pBase->fVmxInsOutInfo << 0) \| ((uint64_t)pBase->fVmxExtIntExit << 1)
1473	\| ((uint64_t)pBase->fVmxNmiExit << 2) \| ((uint64_t)pBase->fVmxVirtNmi << 3)
1474	\| ((uint64_t)pBase->fVmxPreemptTimer << 4) \| ((uint64_t)pBase->fVmxPostedInt << 5)
1475	\| ((uint64_t)pBase->fVmxIntWindowExit << 6) \| ((uint64_t)pBase->fVmxTscOffsetting << 7)
1476	\| ((uint64_t)pBase->fVmxHltExit << 8) \| ((uint64_t)pBase->fVmxInvlpgExit << 9)
1477	\| ((uint64_t)pBase->fVmxMwaitExit << 10) \| ((uint64_t)pBase->fVmxRdpmcExit << 11)
1478	\| ((uint64_t)pBase->fVmxRdtscExit << 12) \| ((uint64_t)pBase->fVmxCr3LoadExit << 13)
1479	\| ((uint64_t)pBase->fVmxCr3StoreExit << 14) \| ((uint64_t)pBase->fVmxCr8LoadExit << 15)
1480	\| ((uint64_t)pBase->fVmxCr8StoreExit << 16) \| ((uint64_t)pBase->fVmxUseTprShadow << 17)
1481	\| ((uint64_t)pBase->fVmxNmiWindowExit << 18) \| ((uint64_t)pBase->fVmxMovDRxExit << 19)
1482	\| ((uint64_t)pBase->fVmxUncondIoExit << 20) \| ((uint64_t)pBase->fVmxUseIoBitmaps << 21)
1483	\| ((uint64_t)pBase->fVmxMonitorTrapFlag << 22) \| ((uint64_t)pBase->fVmxUseMsrBitmaps << 23)
1484	\| ((uint64_t)pBase->fVmxMonitorExit << 24) \| ((uint64_t)pBase->fVmxPauseExit << 25)
1485	\| ((uint64_t)pBase->fVmxSecondaryExecCtls << 26) \| ((uint64_t)pBase->fVmxVirtApicAccess << 27)
1486	\| ((uint64_t)pBase->fVmxEpt << 28) \| ((uint64_t)pBase->fVmxDescTableExit << 29)
1487	\| ((uint64_t)pBase->fVmxRdtscp << 30) \| ((uint64_t)pBase->fVmxVirtX2ApicMode << 31)
1488	\| ((uint64_t)pBase->fVmxVpid << 32) \| ((uint64_t)pBase->fVmxWbinvdExit << 33)
1489	\| ((uint64_t)pBase->fVmxUnrestrictedGuest << 34) \| ((uint64_t)pBase->fVmxApicRegVirt << 35)
1490	\| ((uint64_t)pBase->fVmxVirtIntDelivery << 36) \| ((uint64_t)pBase->fVmxPauseLoopExit << 37)
1491	\| ((uint64_t)pBase->fVmxRdrandExit << 38) \| ((uint64_t)pBase->fVmxInvpcid << 39)
1492	\| ((uint64_t)pBase->fVmxVmFunc << 40) \| ((uint64_t)pBase->fVmxVmcsShadowing << 41)
1493	\| ((uint64_t)pBase->fVmxRdseedExit << 42) \| ((uint64_t)pBase->fVmxPml << 43)
1494	\| ((uint64_t)pBase->fVmxEptXcptVe << 44) \| ((uint64_t)pBase->fVmxXsavesXrstors << 45)
1495	\| ((uint64_t)pBase->fVmxUseTscScaling << 46) \| ((uint64_t)pBase->fVmxEntryLoadDebugCtls << 47)
1496	\| ((uint64_t)pBase->fVmxIa32eModeGuest << 48) \| ((uint64_t)pBase->fVmxEntryLoadEferMsr << 49)
1497	\| ((uint64_t)pBase->fVmxEntryLoadPatMsr << 50) \| ((uint64_t)pBase->fVmxExitSaveDebugCtls << 51)
1498	\| ((uint64_t)pBase->fVmxHostAddrSpaceSize << 52) \| ((uint64_t)pBase->fVmxExitAckExtInt << 53)
1499	\| ((uint64_t)pBase->fVmxExitSavePatMsr << 54) \| ((uint64_t)pBase->fVmxExitLoadPatMsr << 55)
1500	\| ((uint64_t)pBase->fVmxExitSaveEferMsr << 56) \| ((uint64_t)pBase->fVmxExitLoadEferMsr << 57)
1501	\| ((uint64_t)pBase->fVmxSavePreemptTimer << 58) \| ((uint64_t)pBase->fVmxExitSaveEferLma << 59)
1502	\| ((uint64_t)pBase->fVmxIntelPt << 60) \| ((uint64_t)pBase->fVmxVmwriteAll << 61)
1503	\| ((uint64_t)pBase->fVmxEntryInjectSoftInt << 62);
1504
1505	uint64_t const fGst = ((uint64_t)pGst->fVmxInsOutInfo << 0) \| ((uint64_t)pGst->fVmxExtIntExit << 1)
1506	\| ((uint64_t)pGst->fVmxNmiExit << 2) \| ((uint64_t)pGst->fVmxVirtNmi << 3)
1507	\| ((uint64_t)pGst->fVmxPreemptTimer << 4) \| ((uint64_t)pGst->fVmxPostedInt << 5)
1508	\| ((uint64_t)pGst->fVmxIntWindowExit << 6) \| ((uint64_t)pGst->fVmxTscOffsetting << 7)
1509	\| ((uint64_t)pGst->fVmxHltExit << 8) \| ((uint64_t)pGst->fVmxInvlpgExit << 9)
1510	\| ((uint64_t)pGst->fVmxMwaitExit << 10) \| ((uint64_t)pGst->fVmxRdpmcExit << 11)
1511	\| ((uint64_t)pGst->fVmxRdtscExit << 12) \| ((uint64_t)pGst->fVmxCr3LoadExit << 13)
1512	\| ((uint64_t)pGst->fVmxCr3StoreExit << 14) \| ((uint64_t)pGst->fVmxCr8LoadExit << 15)
1513	\| ((uint64_t)pGst->fVmxCr8StoreExit << 16) \| ((uint64_t)pGst->fVmxUseTprShadow << 17)
1514	\| ((uint64_t)pGst->fVmxNmiWindowExit << 18) \| ((uint64_t)pGst->fVmxMovDRxExit << 19)
1515	\| ((uint64_t)pGst->fVmxUncondIoExit << 20) \| ((uint64_t)pGst->fVmxUseIoBitmaps << 21)
1516	\| ((uint64_t)pGst->fVmxMonitorTrapFlag << 22) \| ((uint64_t)pGst->fVmxUseMsrBitmaps << 23)
1517	\| ((uint64_t)pGst->fVmxMonitorExit << 24) \| ((uint64_t)pGst->fVmxPauseExit << 25)
1518	\| ((uint64_t)pGst->fVmxSecondaryExecCtls << 26) \| ((uint64_t)pGst->fVmxVirtApicAccess << 27)
1519	\| ((uint64_t)pGst->fVmxEpt << 28) \| ((uint64_t)pGst->fVmxDescTableExit << 29)
1520	\| ((uint64_t)pGst->fVmxRdtscp << 30) \| ((uint64_t)pGst->fVmxVirtX2ApicMode << 31)
1521	\| ((uint64_t)pGst->fVmxVpid << 32) \| ((uint64_t)pGst->fVmxWbinvdExit << 33)
1522	\| ((uint64_t)pGst->fVmxUnrestrictedGuest << 34) \| ((uint64_t)pGst->fVmxApicRegVirt << 35)
1523	\| ((uint64_t)pGst->fVmxVirtIntDelivery << 36) \| ((uint64_t)pGst->fVmxPauseLoopExit << 37)
1524	\| ((uint64_t)pGst->fVmxRdrandExit << 38) \| ((uint64_t)pGst->fVmxInvpcid << 39)
1525	\| ((uint64_t)pGst->fVmxVmFunc << 40) \| ((uint64_t)pGst->fVmxVmcsShadowing << 41)
1526	\| ((uint64_t)pGst->fVmxRdseedExit << 42) \| ((uint64_t)pGst->fVmxPml << 43)
1527	\| ((uint64_t)pGst->fVmxEptXcptVe << 44) \| ((uint64_t)pGst->fVmxXsavesXrstors << 45)
1528	\| ((uint64_t)pGst->fVmxUseTscScaling << 46) \| ((uint64_t)pGst->fVmxEntryLoadDebugCtls << 47)
1529	\| ((uint64_t)pGst->fVmxIa32eModeGuest << 48) \| ((uint64_t)pGst->fVmxEntryLoadEferMsr << 49)
1530	\| ((uint64_t)pGst->fVmxEntryLoadPatMsr << 50) \| ((uint64_t)pGst->fVmxExitSaveDebugCtls << 51)
1531	\| ((uint64_t)pGst->fVmxHostAddrSpaceSize << 52) \| ((uint64_t)pGst->fVmxExitAckExtInt << 53)
1532	\| ((uint64_t)pGst->fVmxExitSavePatMsr << 54) \| ((uint64_t)pGst->fVmxExitLoadPatMsr << 55)
1533	\| ((uint64_t)pGst->fVmxExitSaveEferMsr << 56) \| ((uint64_t)pGst->fVmxExitLoadEferMsr << 57)
1534	\| ((uint64_t)pGst->fVmxSavePreemptTimer << 58) \| ((uint64_t)pGst->fVmxExitSaveEferLma << 59)
1535	\| ((uint64_t)pGst->fVmxIntelPt << 60) \| ((uint64_t)pGst->fVmxVmwriteAll << 61)
1536	\| ((uint64_t)pGst->fVmxEntryInjectSoftInt << 62);
1537
1538	if ((fBase \| fGst) != fBase)
1539	return false;
1540	return true;
1541	}
1542	return true;
1543	}
1544	#endif
1545
1546
1547	/**
1548	* Initializes VMX guest features and MSRs.
1549	*
1550	* @param pVM The cross context VM structure.
1551	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1552	* and no hardware-assisted nested-guest execution is
1553	* possible for this VM.
1554	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1555	*/
1556	void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs)
1557	{
1558	Assert(pVM);
1559	Assert(pGuestVmxMsrs);
1560
1561	/*
1562	* Initialize the set of VMX features we emulate.
1563	*
1564	* Note! Some bits might be reported as 1 always if they fall under the
1565	* default1 class bits (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1566	*/
1567	CPUMFEATURES EmuFeat;
1568	RT_ZERO(EmuFeat);
1569	EmuFeat.fVmx = 1;
1570	EmuFeat.fVmxInsOutInfo = 0;
1571	EmuFeat.fVmxExtIntExit = 1;
1572	EmuFeat.fVmxNmiExit = 1;
1573	EmuFeat.fVmxVirtNmi = 0;
1574	EmuFeat.fVmxPreemptTimer = 0; /** @todo NSTVMX: enable this. */
1575	EmuFeat.fVmxPostedInt = 0;
1576	EmuFeat.fVmxIntWindowExit = 1;
1577	EmuFeat.fVmxTscOffsetting = 1;
1578	EmuFeat.fVmxHltExit = 1;
1579	EmuFeat.fVmxInvlpgExit = 1;
1580	EmuFeat.fVmxMwaitExit = 1;
1581	EmuFeat.fVmxRdpmcExit = 1;
1582	EmuFeat.fVmxRdtscExit = 1;
1583	EmuFeat.fVmxCr3LoadExit = 1;
1584	EmuFeat.fVmxCr3StoreExit = 1;
1585	EmuFeat.fVmxCr8LoadExit = 1;
1586	EmuFeat.fVmxCr8StoreExit = 1;
1587	EmuFeat.fVmxUseTprShadow = 0;
1588	EmuFeat.fVmxNmiWindowExit = 0;
1589	EmuFeat.fVmxMovDRxExit = 1;
1590	EmuFeat.fVmxUncondIoExit = 1;
1591	EmuFeat.fVmxUseIoBitmaps = 1;
1592	EmuFeat.fVmxMonitorTrapFlag = 0;
1593	EmuFeat.fVmxUseMsrBitmaps = 1;
1594	EmuFeat.fVmxMonitorExit = 1;
1595	EmuFeat.fVmxPauseExit = 1;
1596	EmuFeat.fVmxSecondaryExecCtls = 1;
1597	EmuFeat.fVmxVirtApicAccess = 0;
1598	EmuFeat.fVmxEpt = 0;
1599	EmuFeat.fVmxDescTableExit = 1;
1600	EmuFeat.fVmxRdtscp = 1;
1601	EmuFeat.fVmxVirtX2ApicMode = 0;
1602	EmuFeat.fVmxVpid = 0;
1603	EmuFeat.fVmxWbinvdExit = 1;
1604	EmuFeat.fVmxUnrestrictedGuest = 0;
1605	EmuFeat.fVmxApicRegVirt = 0;
1606	EmuFeat.fVmxVirtIntDelivery = 0;
1607	EmuFeat.fVmxPauseLoopExit = 0;
1608	EmuFeat.fVmxRdrandExit = 0;
1609	EmuFeat.fVmxInvpcid = 1;
1610	EmuFeat.fVmxVmFunc = 0;
1611	EmuFeat.fVmxVmcsShadowing = 0;
1612	EmuFeat.fVmxRdseedExit = 0;
1613	EmuFeat.fVmxPml = 0;
1614	EmuFeat.fVmxEptXcptVe = 0;
1615	EmuFeat.fVmxXsavesXrstors = 0;
1616	EmuFeat.fVmxUseTscScaling = 0;
1617	EmuFeat.fVmxEntryLoadDebugCtls = 1;
1618	EmuFeat.fVmxIa32eModeGuest = 1;
1619	EmuFeat.fVmxEntryLoadEferMsr = 1;
1620	EmuFeat.fVmxEntryLoadPatMsr = 0;
1621	EmuFeat.fVmxExitSaveDebugCtls = 1;
1622	EmuFeat.fVmxHostAddrSpaceSize = 1;
1623	EmuFeat.fVmxExitAckExtInt = 0;
1624	EmuFeat.fVmxExitSavePatMsr = 0;
1625	EmuFeat.fVmxExitLoadPatMsr = 0;
1626	EmuFeat.fVmxExitSaveEferMsr = 1;
1627	EmuFeat.fVmxExitLoadEferMsr = 1;
1628	EmuFeat.fVmxSavePreemptTimer = 0;
1629	EmuFeat.fVmxExitSaveEferLma = 1;
1630	EmuFeat.fVmxIntelPt = 0;
1631	EmuFeat.fVmxVmwriteAll = 0;
1632	EmuFeat.fVmxEntryInjectSoftInt = 0;
1633
1634	/*
1635	* Merge guest features.
1636	*
1637	* When hardware-assisted VMX may be used, any feature we emulate must also be supported
1638	* by the hardware, hence we merge our emulated features with the host features below.
1639	*/
1640	PCCPUMFEATURES pBaseFeat = cpumR3IsHwAssistNstGstExecAllowed(pVM) ? &pVM->cpum.s.HostFeatures : &EmuFeat;
1641	PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1642	Assert(pBaseFeat->fVmx);
1643	pGuestFeat->fVmxInsOutInfo = (pBaseFeat->fVmxInsOutInfo & EmuFeat.fVmxInsOutInfo );
1644	pGuestFeat->fVmxExtIntExit = (pBaseFeat->fVmxExtIntExit & EmuFeat.fVmxExtIntExit );
1645	pGuestFeat->fVmxNmiExit = (pBaseFeat->fVmxNmiExit & EmuFeat.fVmxNmiExit );
1646	pGuestFeat->fVmxVirtNmi = (pBaseFeat->fVmxVirtNmi & EmuFeat.fVmxVirtNmi );
1647	pGuestFeat->fVmxPreemptTimer = (pBaseFeat->fVmxPreemptTimer & EmuFeat.fVmxPreemptTimer );
1648	pGuestFeat->fVmxPostedInt = (pBaseFeat->fVmxPostedInt & EmuFeat.fVmxPostedInt );
1649	pGuestFeat->fVmxIntWindowExit = (pBaseFeat->fVmxIntWindowExit & EmuFeat.fVmxIntWindowExit );
1650	pGuestFeat->fVmxTscOffsetting = (pBaseFeat->fVmxTscOffsetting & EmuFeat.fVmxTscOffsetting );
1651	pGuestFeat->fVmxHltExit = (pBaseFeat->fVmxHltExit & EmuFeat.fVmxHltExit );
1652	pGuestFeat->fVmxInvlpgExit = (pBaseFeat->fVmxInvlpgExit & EmuFeat.fVmxInvlpgExit );
1653	pGuestFeat->fVmxMwaitExit = (pBaseFeat->fVmxMwaitExit & EmuFeat.fVmxMwaitExit );
1654	pGuestFeat->fVmxRdpmcExit = (pBaseFeat->fVmxRdpmcExit & EmuFeat.fVmxRdpmcExit );
1655	pGuestFeat->fVmxRdtscExit = (pBaseFeat->fVmxRdtscExit & EmuFeat.fVmxRdtscExit );
1656	pGuestFeat->fVmxCr3LoadExit = (pBaseFeat->fVmxCr3LoadExit & EmuFeat.fVmxCr3LoadExit );
1657	pGuestFeat->fVmxCr3StoreExit = (pBaseFeat->fVmxCr3StoreExit & EmuFeat.fVmxCr3StoreExit );
1658	pGuestFeat->fVmxCr8LoadExit = (pBaseFeat->fVmxCr8LoadExit & EmuFeat.fVmxCr8LoadExit );
1659	pGuestFeat->fVmxCr8StoreExit = (pBaseFeat->fVmxCr8StoreExit & EmuFeat.fVmxCr8StoreExit );
1660	pGuestFeat->fVmxUseTprShadow = (pBaseFeat->fVmxUseTprShadow & EmuFeat.fVmxUseTprShadow );
1661	pGuestFeat->fVmxNmiWindowExit = (pBaseFeat->fVmxNmiWindowExit & EmuFeat.fVmxNmiWindowExit );
1662	pGuestFeat->fVmxMovDRxExit = (pBaseFeat->fVmxMovDRxExit & EmuFeat.fVmxMovDRxExit );
1663	pGuestFeat->fVmxUncondIoExit = (pBaseFeat->fVmxUncondIoExit & EmuFeat.fVmxUncondIoExit );
1664	pGuestFeat->fVmxUseIoBitmaps = (pBaseFeat->fVmxUseIoBitmaps & EmuFeat.fVmxUseIoBitmaps );
1665	pGuestFeat->fVmxMonitorTrapFlag = (pBaseFeat->fVmxMonitorTrapFlag & EmuFeat.fVmxMonitorTrapFlag );
1666	pGuestFeat->fVmxUseMsrBitmaps = (pBaseFeat->fVmxUseMsrBitmaps & EmuFeat.fVmxUseMsrBitmaps );
1667	pGuestFeat->fVmxMonitorExit = (pBaseFeat->fVmxMonitorExit & EmuFeat.fVmxMonitorExit );
1668	pGuestFeat->fVmxPauseExit = (pBaseFeat->fVmxPauseExit & EmuFeat.fVmxPauseExit );
1669	pGuestFeat->fVmxSecondaryExecCtls = (pBaseFeat->fVmxSecondaryExecCtls & EmuFeat.fVmxSecondaryExecCtls );
1670	pGuestFeat->fVmxVirtApicAccess = (pBaseFeat->fVmxVirtApicAccess & EmuFeat.fVmxVirtApicAccess );
1671	pGuestFeat->fVmxEpt = (pBaseFeat->fVmxEpt & EmuFeat.fVmxEpt );
1672	pGuestFeat->fVmxDescTableExit = (pBaseFeat->fVmxDescTableExit & EmuFeat.fVmxDescTableExit );
1673	pGuestFeat->fVmxRdtscp = (pBaseFeat->fVmxRdtscp & EmuFeat.fVmxRdtscp );
1674	pGuestFeat->fVmxVirtX2ApicMode = (pBaseFeat->fVmxVirtX2ApicMode & EmuFeat.fVmxVirtX2ApicMode );
1675	pGuestFeat->fVmxVpid = (pBaseFeat->fVmxVpid & EmuFeat.fVmxVpid );
1676	pGuestFeat->fVmxWbinvdExit = (pBaseFeat->fVmxWbinvdExit & EmuFeat.fVmxWbinvdExit );
1677	pGuestFeat->fVmxUnrestrictedGuest = (pBaseFeat->fVmxUnrestrictedGuest & EmuFeat.fVmxUnrestrictedGuest );
1678	pGuestFeat->fVmxApicRegVirt = (pBaseFeat->fVmxApicRegVirt & EmuFeat.fVmxApicRegVirt );
1679	pGuestFeat->fVmxVirtIntDelivery = (pBaseFeat->fVmxVirtIntDelivery & EmuFeat.fVmxVirtIntDelivery );
1680	pGuestFeat->fVmxPauseLoopExit = (pBaseFeat->fVmxPauseLoopExit & EmuFeat.fVmxPauseLoopExit );
1681	pGuestFeat->fVmxRdrandExit = (pBaseFeat->fVmxRdrandExit & EmuFeat.fVmxRdrandExit );
1682	pGuestFeat->fVmxInvpcid = (pBaseFeat->fVmxInvpcid & EmuFeat.fVmxInvpcid );
1683	pGuestFeat->fVmxVmFunc = (pBaseFeat->fVmxVmFunc & EmuFeat.fVmxVmFunc );
1684	pGuestFeat->fVmxVmcsShadowing = (pBaseFeat->fVmxVmcsShadowing & EmuFeat.fVmxVmcsShadowing );
1685	pGuestFeat->fVmxRdseedExit = (pBaseFeat->fVmxRdseedExit & EmuFeat.fVmxRdseedExit );
1686	pGuestFeat->fVmxPml = (pBaseFeat->fVmxPml & EmuFeat.fVmxPml );
1687	pGuestFeat->fVmxEptXcptVe = (pBaseFeat->fVmxEptXcptVe & EmuFeat.fVmxEptXcptVe );
1688	pGuestFeat->fVmxXsavesXrstors = (pBaseFeat->fVmxXsavesXrstors & EmuFeat.fVmxXsavesXrstors );
1689	pGuestFeat->fVmxUseTscScaling = (pBaseFeat->fVmxUseTscScaling & EmuFeat.fVmxUseTscScaling );
1690	pGuestFeat->fVmxEntryLoadDebugCtls = (pBaseFeat->fVmxEntryLoadDebugCtls & EmuFeat.fVmxEntryLoadDebugCtls );
1691	pGuestFeat->fVmxIa32eModeGuest = (pBaseFeat->fVmxIa32eModeGuest & EmuFeat.fVmxIa32eModeGuest );
1692	pGuestFeat->fVmxEntryLoadEferMsr = (pBaseFeat->fVmxEntryLoadEferMsr & EmuFeat.fVmxEntryLoadEferMsr );
1693	pGuestFeat->fVmxEntryLoadPatMsr = (pBaseFeat->fVmxEntryLoadPatMsr & EmuFeat.fVmxEntryLoadPatMsr );
1694	pGuestFeat->fVmxExitSaveDebugCtls = (pBaseFeat->fVmxExitSaveDebugCtls & EmuFeat.fVmxExitSaveDebugCtls );
1695	pGuestFeat->fVmxHostAddrSpaceSize = (pBaseFeat->fVmxHostAddrSpaceSize & EmuFeat.fVmxHostAddrSpaceSize );
1696	pGuestFeat->fVmxExitAckExtInt = (pBaseFeat->fVmxExitAckExtInt & EmuFeat.fVmxExitAckExtInt );
1697	pGuestFeat->fVmxExitSavePatMsr = (pBaseFeat->fVmxExitSavePatMsr & EmuFeat.fVmxExitSavePatMsr );
1698	pGuestFeat->fVmxExitLoadPatMsr = (pBaseFeat->fVmxExitLoadPatMsr & EmuFeat.fVmxExitLoadPatMsr );
1699	pGuestFeat->fVmxExitSaveEferMsr = (pBaseFeat->fVmxExitSaveEferMsr & EmuFeat.fVmxExitSaveEferMsr );
1700	pGuestFeat->fVmxExitLoadEferMsr = (pBaseFeat->fVmxExitLoadEferMsr & EmuFeat.fVmxExitLoadEferMsr );
1701	pGuestFeat->fVmxSavePreemptTimer = (pBaseFeat->fVmxSavePreemptTimer & EmuFeat.fVmxSavePreemptTimer );
1702	pGuestFeat->fVmxExitSaveEferLma = (pBaseFeat->fVmxExitSaveEferLma & EmuFeat.fVmxExitSaveEferLma );
1703	pGuestFeat->fVmxIntelPt = (pBaseFeat->fVmxIntelPt & EmuFeat.fVmxIntelPt );
1704	pGuestFeat->fVmxVmwriteAll = (pBaseFeat->fVmxVmwriteAll & EmuFeat.fVmxVmwriteAll );
1705	pGuestFeat->fVmxEntryInjectSoftInt = (pBaseFeat->fVmxEntryInjectSoftInt & EmuFeat.fVmxEntryInjectSoftInt );
1706
1707	/* Paranoia. */
1708	if (!pGuestFeat->fVmxSecondaryExecCtls)
1709	{
1710	Assert(!pGuestFeat->fVmxVirtApicAccess);
1711	Assert(!pGuestFeat->fVmxEpt);
1712	Assert(!pGuestFeat->fVmxDescTableExit);
1713	Assert(!pGuestFeat->fVmxRdtscp);
1714	Assert(!pGuestFeat->fVmxVirtX2ApicMode);
1715	Assert(!pGuestFeat->fVmxVpid);
1716	Assert(!pGuestFeat->fVmxWbinvdExit);
1717	Assert(!pGuestFeat->fVmxUnrestrictedGuest);
1718	Assert(!pGuestFeat->fVmxApicRegVirt);
1719	Assert(!pGuestFeat->fVmxVirtIntDelivery);
1720	Assert(!pGuestFeat->fVmxPauseLoopExit);
1721	Assert(!pGuestFeat->fVmxRdrandExit);
1722	Assert(!pGuestFeat->fVmxInvpcid);
1723	Assert(!pGuestFeat->fVmxVmFunc);
1724	Assert(!pGuestFeat->fVmxVmcsShadowing);
1725	Assert(!pGuestFeat->fVmxRdseedExit);
1726	Assert(!pGuestFeat->fVmxPml);
1727	Assert(!pGuestFeat->fVmxEptXcptVe);
1728	Assert(!pGuestFeat->fVmxXsavesXrstors);
1729	Assert(!pGuestFeat->fVmxUseTscScaling);
1730	}
1731	if (pGuestFeat->fVmxUnrestrictedGuest)
1732	{
1733	/* See footnote in Intel spec. 27.2 "Recording VM-Exit Information And Updating VM-entry Control Fields". */
1734	Assert(pGuestFeat->fVmxExitSaveEferLma);
1735	}
1736
1737	/*
1738	* Finally initialize the VMX guest MSRs.
1739	*/
1740	cpumR3InitVmxGuestMsrs(pVM, pHostVmxMsrs, pGuestFeat, pGuestVmxMsrs);
1741	}
1742
1743
1744	/**
1745	* Gets the host hardware-virtualization MSRs.
1746	*
1747	* @returns VBox status code.
1748	* @param pMsrs Where to store the MSRs.
1749	*/
1750	static int cpumR3GetHostHwvirtMsrs(PCPUMMSRS pMsrs)
1751	{
1752	Assert(pMsrs);
1753
1754	uint32_t fCaps = 0;
1755	int rc = SUPR3QueryVTCaps(&fCaps);
1756	if (RT_SUCCESS(rc))
1757	{
1758	if (fCaps & (SUPVTCAPS_VT_X \| SUPVTCAPS_AMD_V))
1759	{
1760	SUPHWVIRTMSRS HwvirtMsrs;
1761	rc = SUPR3GetHwvirtMsrs(&HwvirtMsrs, false /* fForceRequery */);
1762	if (RT_SUCCESS(rc))
1763	{
1764	if (fCaps & SUPVTCAPS_VT_X)
1765	HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.vmx);
1766	else
1767	HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.svm);
1768	return VINF_SUCCESS;
1769	}
1770
1771	LogRel(("CPUM: Querying hardware-virtualization MSRs failed. rc=%Rrc\n", rc));
1772	return rc;
1773	}
1774	else
1775	{
1776	LogRel(("CPUM: Querying hardware-virtualization capability succeeded but did not find VT-x or AMD-V\n"));
1777	return VERR_INTERNAL_ERROR_5;
1778	}
1779	}
1780	else
1781	LogRel(("CPUM: No hardware-virtualization capability detected\n"));
1782
1783	return VINF_SUCCESS;
1784	}
1785
1786
1787	/**
1788	* Initializes the CPUM.
1789	*
1790	* @returns VBox status code.
1791	* @param pVM The cross context VM structure.
1792	*/
1793	VMMR3DECL(int) CPUMR3Init(PVM pVM)
1794	{
1795	LogFlow(("CPUMR3Init\n"));
1796
1797	/*
1798	* Assert alignment, sizes and tables.
1799	*/
1800	AssertCompileMemberAlignment(VM, cpum.s, 32);
1801	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
1802	AssertCompileSizeAlignment(CPUMCTX, 64);
1803	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
1804	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
1805	AssertCompileMemberAlignment(VM, cpum, 64);
1806	AssertCompileMemberAlignment(VM, aCpus, 64);
1807	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
1808	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
1809	#ifdef VBOX_STRICT
1810	int rc2 = cpumR3MsrStrictInitChecks();
1811	AssertRCReturn(rc2, rc2);
1812	#endif
1813
1814	/*
1815	* Initialize offsets.
1816	*/
1817
1818	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
1819	pVM->cpum.s.offCPUMCPU0 = RT_UOFFSETOF(VM, aCpus[0].cpum) - RT_UOFFSETOF(VM, cpum);
1820	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
1821
1822
1823	/* Calculate the offset from CPUMCPU to CPUM. */
1824	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1825	{
1826	PVMCPU pVCpu = &pVM->aCpus[i];
1827
1828	pVCpu->cpum.s.offCPUM = RT_UOFFSETOF_DYN(VM, aCpus[i].cpum) - RT_UOFFSETOF(VM, cpum);
1829	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
1830	}
1831
1832	/*
1833	* Gather info about the host CPU.
1834	*/
1835	if (!ASMHasCpuId())
1836	{
1837	LogRel(("The CPU doesn't support CPUID!\n"));
1838	return VERR_UNSUPPORTED_CPU;
1839	}
1840
1841	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
1842
1843	CPUMMSRS HostMsrs;
1844	RT_ZERO(HostMsrs);
1845	int rc = cpumR3GetHostHwvirtMsrs(&HostMsrs);
1846	AssertLogRelRCReturn(rc, rc);
1847
1848	PCPUMCPUIDLEAF paLeaves;
1849	uint32_t cLeaves;
1850	rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
1851	AssertLogRelRCReturn(rc, rc);
1852
1853	rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &HostMsrs, &pVM->cpum.s.HostFeatures);
1854	RTMemFree(paLeaves);
1855	AssertLogRelRCReturn(rc, rc);
1856	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
1857
1858	/*
1859	* Check that the CPU supports the minimum features we require.
1860	*/
1861	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
1862	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
1863	if (!pVM->cpum.s.HostFeatures.fMmx)
1864	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
1865	if (!pVM->cpum.s.HostFeatures.fTsc)
1866	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
1867
1868	/*
1869	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
1870	*/
1871	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
1872	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
1873
1874	/*
1875	* Figure out which XSAVE/XRSTOR features are available on the host.
1876	*/
1877	uint64_t fXcr0Host = 0;
1878	uint64_t fXStateHostMask = 0;
1879	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
1880	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
1881	{
1882	fXStateHostMask = fXcr0Host = ASMGetXcr0();
1883	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
1884	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
1885	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
1886	}
1887	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
1888	if (VM_IS_RAW_MODE_ENABLED(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
1889	fXStateHostMask = 0;
1890	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
1891	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
1892
1893	/*
1894	* Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
1895	*/
1896	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
1897	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
1898	AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
1899
1900	uint8_t *pbXStates;
1901	rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
1902	MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
1903	AssertLogRelRCReturn(rc, rc);
1904
1905	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1906	{
1907	PVMCPU pVCpu = &pVM->aCpus[i];
1908
1909	pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
1910	pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
1911	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
1912	pbXStates += cbMaxXState;
1913
1914	pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
1915	pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
1916	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
1917	pbXStates += cbMaxXState;
1918
1919	pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
1920	pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
1921	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
1922	pbXStates += cbMaxXState;
1923
1924	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
1925	}
1926
1927	/*
1928	* Register saved state data item.
1929	*/
1930	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
1931	NULL, cpumR3LiveExec, NULL,
1932	NULL, cpumR3SaveExec, NULL,
1933	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
1934	if (RT_FAILURE(rc))
1935	return rc;
1936
1937	/*
1938	* Register info handlers and registers with the debugger facility.
1939	*/
1940	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
1941	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
1942	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
1943	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
1944	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
1945	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
1946	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
1947	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
1948	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
1949	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
1950	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
1951	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
1952	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
1953	DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
1954	&cpumR3InfoVmxFeatures);
1955
1956	rc = cpumR3DbgInit(pVM);
1957	if (RT_FAILURE(rc))
1958	return rc;
1959
1960	/*
1961	* Check if we need to workaround partial/leaky FPU handling.
1962	*/
1963	cpumR3CheckLeakyFpu(pVM);
1964
1965	/*
1966	* Initialize the Guest CPUID and MSR states.
1967	*/
1968	rc = cpumR3InitCpuIdAndMsrs(pVM, &HostMsrs);
1969	if (RT_FAILURE(rc))
1970	return rc;
1971
1972	/*
1973	* Allocate memory required by the guest hardware-virtualization structures.
1974	* This must be done after initializing CPUID/MSR features as we access the
1975	* the VMX/SVM guest features below.
1976	*/
1977	if (pVM->cpum.s.GuestFeatures.fVmx)
1978	rc = cpumR3AllocVmxHwVirtState(pVM);
1979	else if (pVM->cpum.s.GuestFeatures.fSvm)
1980	rc = cpumR3AllocSvmHwVirtState(pVM);
1981	else
1982	Assert(pVM->aCpus[0].cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
1983	if (RT_FAILURE(rc))
1984	return rc;
1985
1986	/*
1987	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
1988	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1989	* of processors from (cpuid(4).eax >> 26) + 1.
1990	*
1991	* Note: this code is obsolete, but let's keep it here for reference.
1992	* Purpose is valid when we artificially cap the max std id to less than 4.
1993	*
1994	* Note: This used to be a separate function CPUMR3SetHwVirt that was called
1995	* after VMINITCOMPLETED_HM.
1996	*/
1997	if (VM_IS_RAW_MODE_ENABLED(pVM))
1998	{
1999	Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
2000	\|\| pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
2001	pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
2002	}
2003
2004	CPUMR3Reset(pVM);
2005	return VINF_SUCCESS;
2006	}
2007
2008
2009	/**
2010	* Applies relocations to data and code managed by this
2011	* component. This function will be called at init and
2012	* whenever the VMM need to relocate it self inside the GC.
2013	*
2014	* The CPUM will update the addresses used by the switcher.
2015	*
2016	* @param pVM The cross context VM structure.
2017	*/
2018	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
2019	{
2020	LogFlow(("CPUMR3Relocate\n"));
2021
2022	pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
2023	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
2024
2025	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2026	{
2027	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2028	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
2029	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
2030	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
2031
2032	/* Recheck the guest DRx values in raw-mode. */
2033	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
2034	}
2035	}
2036
2037
2038	/**
2039	* Terminates the CPUM.
2040	*
2041	* Termination means cleaning up and freeing all resources,
2042	* the VM it self is at this point powered off or suspended.
2043	*
2044	* @returns VBox status code.
2045	* @param pVM The cross context VM structure.
2046	*/
2047	VMMR3DECL(int) CPUMR3Term(PVM pVM)
2048	{
2049	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2050	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2051	{
2052	PVMCPU pVCpu = &pVM->aCpus[i];
2053	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2054
2055	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
2056	pVCpu->cpum.s.uMagic = 0;
2057	pCtx->dr[5] = 0;
2058	}
2059	#endif
2060
2061	if (pVM->cpum.s.GuestFeatures.fVmx)
2062	cpumR3FreeVmxHwVirtState(pVM);
2063	else if (pVM->cpum.s.GuestFeatures.fSvm)
2064	cpumR3FreeSvmHwVirtState(pVM);
2065	return VINF_SUCCESS;
2066	}
2067
2068
2069	/**
2070	* Resets a virtual CPU.
2071	*
2072	* Used by CPUMR3Reset and CPU hot plugging.
2073	*
2074	* @param pVM The cross context VM structure.
2075	* @param pVCpu The cross context virtual CPU structure of the CPU that is
2076	* being reset. This may differ from the current EMT.
2077	*/
2078	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2079	{
2080	/** @todo anything different for VCPU > 0? */
2081	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2082
2083	/*
2084	* Initialize everything to ZERO first.
2085	*/
2086	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
2087
2088	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
2089	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
2090	memset(pCtx, 0, RT_UOFFSETOF(CPUMCTX, pXStateR0));
2091
2092	pVCpu->cpum.s.fUseFlags = fUseFlags;
2093
2094	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
2095	pCtx->eip = 0x0000fff0;
2096	pCtx->edx = 0x00000600; /* P6 processor */
2097	pCtx->eflags.Bits.u1Reserved0 = 1;
2098
2099	pCtx->cs.Sel = 0xf000;
2100	pCtx->cs.ValidSel = 0xf000;
2101	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2102	pCtx->cs.u64Base = UINT64_C(0xffff0000);
2103	pCtx->cs.u32Limit = 0x0000ffff;
2104	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
2105	pCtx->cs.Attr.n.u1Present = 1;
2106	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
2107
2108	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
2109	pCtx->ds.u32Limit = 0x0000ffff;
2110	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
2111	pCtx->ds.Attr.n.u1Present = 1;
2112	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2113
2114	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
2115	pCtx->es.u32Limit = 0x0000ffff;
2116	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
2117	pCtx->es.Attr.n.u1Present = 1;
2118	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2119
2120	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
2121	pCtx->fs.u32Limit = 0x0000ffff;
2122	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
2123	pCtx->fs.Attr.n.u1Present = 1;
2124	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2125
2126	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
2127	pCtx->gs.u32Limit = 0x0000ffff;
2128	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
2129	pCtx->gs.Attr.n.u1Present = 1;
2130	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2131
2132	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2133	pCtx->ss.u32Limit = 0x0000ffff;
2134	pCtx->ss.Attr.n.u1Present = 1;
2135	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
2136	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2137
2138	pCtx->idtr.cbIdt = 0xffff;
2139	pCtx->gdtr.cbGdt = 0xffff;
2140
2141	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2142	pCtx->ldtr.u32Limit = 0xffff;
2143	pCtx->ldtr.Attr.n.u1Present = 1;
2144	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
2145
2146	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2147	pCtx->tr.u32Limit = 0xffff;
2148	pCtx->tr.Attr.n.u1Present = 1;
2149	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
2150
2151	pCtx->dr[6] = X86_DR6_INIT_VAL;
2152	pCtx->dr[7] = X86_DR7_INIT_VAL;
2153
2154	PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
2155	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
2156	pFpuCtx->FCW = 0x37f;
2157
2158	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
2159	IA-32 Processor States Following Power-up, Reset, or INIT */
2160	pFpuCtx->MXCSR = 0x1F80;
2161	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
2162
2163	pCtx->aXcr[0] = XSAVE_C_X87;
2164	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
2165	{
2166	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
2167	as we don't know what happened before. (Bother optimize later?) */
2168	pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
2169	}
2170
2171	/*
2172	* MSRs.
2173	*/
2174	/* Init PAT MSR */
2175	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
2176
2177	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
2178	* The Intel docs don't mention it. */
2179	Assert(!pCtx->msrEFER);
2180
2181	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
2182	is supposed to be here, just trying provide useful/sensible values. */
2183	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
2184	if (pRange)
2185	{
2186	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2187	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
2188	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
2189	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
2190	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2191	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
2192	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
2193	}
2194
2195	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
2196
2197	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
2198	* called from each EMT while we're getting called by CPUMR3Reset()
2199	* iteratively on the same thread. Fix later. */
2200	#if 0 /** @todo r=bird: This we will do in TM, not here. */
2201	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
2202	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
2203	#endif
2204
2205
2206	/* C-state control. Guesses. */
2207	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
2208	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
2209	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
2210	* functionality. The default value must be different due to incompatible write mask.
2211	*/
2212	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
2213	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
2214	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
2215	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
2216
2217	/*
2218	* Hardware virtualization state.
2219	*/
2220	CPUMSetGuestGif(pCtx, true);
2221	Assert(!pVM->cpum.s.GuestFeatures.fVmx \|\| !pVM->cpum.s.GuestFeatures.fSvm); /* Paranoia. */
2222	if (pVM->cpum.s.GuestFeatures.fVmx)
2223	cpumR3ResetVmxHwVirtState(pVCpu);
2224	else if (pVM->cpum.s.GuestFeatures.fSvm)
2225	cpumR3ResetSvmHwVirtState(pVCpu);
2226	}
2227
2228
2229	/**
2230	* Resets the CPU.
2231	*
2232	* @returns VINF_SUCCESS.
2233	* @param pVM The cross context VM structure.
2234	*/
2235	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
2236	{
2237	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2238	{
2239	CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
2240
2241	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2242	PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
2243
2244	/* Magic marker for searching in crash dumps. */
2245	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
2246	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2247	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2248	#endif
2249	}
2250	}
2251
2252
2253
2254
2255	/**
2256	* Pass 0 live exec callback.
2257	*
2258	* @returns VINF_SSM_DONT_CALL_AGAIN.
2259	* @param pVM The cross context VM structure.
2260	* @param pSSM The saved state handle.
2261	* @param uPass The pass (0).
2262	*/
2263	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2264	{
2265	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2266	cpumR3SaveCpuId(pVM, pSSM);
2267	return VINF_SSM_DONT_CALL_AGAIN;
2268	}
2269
2270
2271	/**
2272	* Execute state save operation.
2273	*
2274	* @returns VBox status code.
2275	* @param pVM The cross context VM structure.
2276	* @param pSSM SSM operation handle.
2277	*/
2278	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2279	{
2280	/*
2281	* Save.
2282	*/
2283	SSMR3PutU32(pSSM, pVM->cCpus);
2284	SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
2285	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2286	{
2287	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2288
2289	SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
2290
2291	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2292	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2293	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
2294	if (pGstCtx->fXStateMask != 0)
2295	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
2296	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2297	{
2298	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2299	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2300	}
2301	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2302	{
2303	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2304	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2305	}
2306	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2307	{
2308	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2309	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2310	}
2311	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2312	{
2313	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2314	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2315	}
2316	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2317	{
2318	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2319	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2320	}
2321	if (pVM->cpum.s.GuestFeatures.fSvm)
2322	{
2323	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
2324	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2325	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2326	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2327	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2328	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2329	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2330	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2331	g_aSvmHwvirtHostState, NULL /* pvUser */);
2332	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
2333	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
2334	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
2335	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fLocalForcedActions);
2336	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2337	}
2338	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2339	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2340	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2341	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2342	}
2343
2344	cpumR3SaveCpuId(pVM, pSSM);
2345	return VINF_SUCCESS;
2346	}
2347
2348
2349	/**
2350	* @callback_method_impl{FNSSMINTLOADPREP}
2351	*/
2352	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2353	{
2354	NOREF(pSSM);
2355	pVM->cpum.s.fPendingRestore = true;
2356	return VINF_SUCCESS;
2357	}
2358
2359
2360	/**
2361	* @callback_method_impl{FNSSMINTLOADEXEC}
2362	*/
2363	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2364	{
2365	int rc; /* Only for AssertRCReturn use. */
2366
2367	/*
2368	* Validate version.
2369	*/
2370	if ( uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2371	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2372	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2373	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2374	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2375	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
2376	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2377	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2378	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2379	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2380	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2381	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2382	{
2383	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2384	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2385	}
2386
2387	if (uPass == SSM_PASS_FINAL)
2388	{
2389	/*
2390	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2391	* really old SSM file versions.)
2392	*/
2393	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2394	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2395	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2396	SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2397
2398	/*
2399	* Figure x86 and ctx field definitions to use for older states.
2400	*/
2401	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2402	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2403	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2404	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2405	{
2406	paCpumCtx1Fields = g_aCpumX87FieldsV16;
2407	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2408	}
2409	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2410	{
2411	paCpumCtx1Fields = g_aCpumX87FieldsMem;
2412	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2413	}
2414
2415	/*
2416	* The hyper state used to preceed the CPU count. Starting with
2417	* XSAVE it was moved down till after we've got the count.
2418	*/
2419	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2420	{
2421	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2422	{
2423	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2424	X86FXSTATE Ign;
2425	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2426	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2427	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2428	SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
2429	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2430	pVCpu->cpum.s.Hyper.cr3 = uCR3;
2431	pVCpu->cpum.s.Hyper.rsp = uRSP;
2432	}
2433	}
2434
2435	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2436	{
2437	uint32_t cCpus;
2438	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2439	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2440	VERR_SSM_UNEXPECTED_DATA);
2441	}
2442	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2443	\|\| pVM->cCpus == 1,
2444	("cCpus=%u\n", pVM->cCpus),
2445	VERR_SSM_UNEXPECTED_DATA);
2446
2447	uint32_t cbMsrs = 0;
2448	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2449	{
2450	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2451	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2452	VERR_SSM_UNEXPECTED_DATA);
2453	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2454	VERR_SSM_UNEXPECTED_DATA);
2455	}
2456
2457	/*
2458	* Do the per-CPU restoring.
2459	*/
2460	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2461	{
2462	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2463	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2464
2465	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2466	{
2467	/*
2468	* The XSAVE saved state layout moved the hyper state down here.
2469	*/
2470	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2471	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2472	rc = SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
2473	pVCpu->cpum.s.Hyper.cr3 = uCR3;
2474	pVCpu->cpum.s.Hyper.rsp = uRSP;
2475	AssertRCReturn(rc, rc);
2476
2477	/*
2478	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2479	*/
2480	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2481	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
2482	AssertRCReturn(rc, rc);
2483
2484	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2485	if (pGstCtx->fXStateMask != 0)
2486	{
2487	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2488	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2489	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2490	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2491	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2492	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2493	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2494	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2495	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2496	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2497	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2498	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2499	}
2500
2501	/* Check that the XCR0 mask is valid (invalid results in #GP). */
2502	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2503	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2504	{
2505	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
2506	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2507	VERR_CPUM_INVALID_XCR0);
2508	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2509	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2510	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2511	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2512	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2513	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2514	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2515	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2516	}
2517
2518	/* Check that the XCR1 is zero, as we don't implement it yet. */
2519	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2520
2521	/*
2522	* Restore the individual extended state components we support.
2523	*/
2524	if (pGstCtx->fXStateMask != 0)
2525	{
2526	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
2527	0, g_aCpumXSaveHdrFields, NULL);
2528	AssertRCReturn(rc, rc);
2529	AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
2530	("bmXState=%#RX64 fXStateMask=%#RX64\n",
2531	pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
2532	VERR_CPUM_INVALID_XSAVE_HDR);
2533	}
2534	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2535	{
2536	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2537	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2538	}
2539	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2540	{
2541	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2542	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2543	}
2544	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2545	{
2546	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2547	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2548	}
2549	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2550	{
2551	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2552	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2553	}
2554	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2555	{
2556	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2557	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2558	}
2559	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2560	{
2561	if (pVM->cpum.s.GuestFeatures.fSvm)
2562	{
2563	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
2564	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2565	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2566	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2567	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2568	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2569	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2570	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2571	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
2572	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
2573	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
2574	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
2575	SSMR3GetU32(pSSM, &pGstCtx->hwvirt.fLocalForcedActions);
2576	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2577	}
2578	}
2579	/** @todo NSTVMX: Load VMX state. */
2580	}
2581	else
2582	{
2583	/*
2584	* Pre XSAVE saved state.
2585	*/
2586	SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
2587	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2588	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2589	}
2590
2591	/*
2592	* Restore a couple of flags and the MSRs.
2593	*/
2594	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
2595	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2596
2597	rc = VINF_SUCCESS;
2598	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2599	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2600	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2601	{
2602	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2603	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2604	}
2605	AssertRCReturn(rc, rc);
2606
2607	/* REM and other may have cleared must-be-one fields in DR6 and
2608	DR7, fix these. */
2609	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
2610	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
2611	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
2612	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
2613	}
2614
2615	/* Older states does not have the internal selector register flags
2616	and valid selector value. Supply those. */
2617	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2618	{
2619	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2620	{
2621	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2622	bool const fValid = !VM_IS_RAW_MODE_ENABLED(pVM)
2623	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2624	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2625	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2626	if (fValid)
2627	{
2628	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2629	{
2630	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2631	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2632	}
2633
2634	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2635	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2636	}
2637	else
2638	{
2639	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2640	{
2641	paSelReg[iSelReg].fFlags = 0;
2642	paSelReg[iSelReg].ValidSel = 0;
2643	}
2644
2645	/* This might not be 104% correct, but I think it's close
2646	enough for all practical purposes... (REM always loaded
2647	LDTR registers.) */
2648	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2649	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2650	}
2651	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2652	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2653	}
2654	}
2655
2656	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2657	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2658	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2659	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2660	pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2661
2662	/*
2663	* A quick sanity check.
2664	*/
2665	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2666	{
2667	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2668	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2669	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2670	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2671	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2672	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2673	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2674	}
2675	}
2676
2677	pVM->cpum.s.fPendingRestore = false;
2678
2679	/*
2680	* Guest CPUIDs.
2681	*/
2682	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
2683	{
2684	CPUMMSRS GuestMsrs;
2685	RT_ZERO(GuestMsrs);
2686	if (pVM->cpum.s.GuestFeatures.fVmx)
2687	GuestMsrs.hwvirt.vmx = pVM->aCpus[0].cpum.s.Guest.hwvirt.vmx.Msrs;
2688	return cpumR3LoadCpuId(pVM, pSSM, uVersion, &GuestMsrs);
2689	}
2690	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
2691	}
2692
2693
2694	/**
2695	* @callback_method_impl{FNSSMINTLOADDONE}
2696	*/
2697	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2698	{
2699	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2700	return VINF_SUCCESS;
2701
2702	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2703	if (pVM->cpum.s.fPendingRestore)
2704	{
2705	LogRel(("CPUM: Missing state!\n"));
2706	return VERR_INTERNAL_ERROR_2;
2707	}
2708
2709	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2710	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2711	{
2712	PVMCPU pVCpu = &pVM->aCpus[idCpu];
2713
2714	/* Notify PGM of the NXE states in case they've changed. */
2715	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2716
2717	/* During init. this is done in CPUMR3InitCompleted(). */
2718	if (fSupportsLongMode)
2719	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
2720	}
2721	return VINF_SUCCESS;
2722	}
2723
2724
2725	/**
2726	* Checks if the CPUM state restore is still pending.
2727	*
2728	* @returns true / false.
2729	* @param pVM The cross context VM structure.
2730	*/
2731	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2732	{
2733	return pVM->cpum.s.fPendingRestore;
2734	}
2735
2736
2737	/**
2738	* Formats the EFLAGS value into mnemonics.
2739	*
2740	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2741	* @param efl The EFLAGS value.
2742	*/
2743	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2744	{
2745	/*
2746	* Format the flags.
2747	*/
2748	static const struct
2749	{
2750	const char pszSet; const char pszClear; uint32_t fFlag;
2751	} s_aFlags[] =
2752	{
2753	{ "vip",NULL, X86_EFL_VIP },
2754	{ "vif",NULL, X86_EFL_VIF },
2755	{ "ac", NULL, X86_EFL_AC },
2756	{ "vm", NULL, X86_EFL_VM },
2757	{ "rf", NULL, X86_EFL_RF },
2758	{ "nt", NULL, X86_EFL_NT },
2759	{ "ov", "nv", X86_EFL_OF },
2760	{ "dn", "up", X86_EFL_DF },
2761	{ "ei", "di", X86_EFL_IF },
2762	{ "tf", NULL, X86_EFL_TF },
2763	{ "nt", "pl", X86_EFL_SF },
2764	{ "nz", "zr", X86_EFL_ZF },
2765	{ "ac", "na", X86_EFL_AF },
2766	{ "po", "pe", X86_EFL_PF },
2767	{ "cy", "nc", X86_EFL_CF },
2768	};
2769	char *psz = pszEFlags;
2770	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2771	{
2772	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2773	if (pszAdd)
2774	{
2775	strcpy(psz, pszAdd);
2776	psz += strlen(pszAdd);
2777	*psz++ = ' ';
2778	}
2779	}
2780	psz[-1] = '\0';
2781	}
2782
2783
2784	/**
2785	* Formats a full register dump.
2786	*
2787	* @param pVM The cross context VM structure.
2788	* @param pCtx The context to format.
2789	* @param pCtxCore The context core to format.
2790	* @param pHlp Output functions.
2791	* @param enmType The dump type.
2792	* @param pszPrefix Register name prefix.
2793	*/
2794	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
2795	const char *pszPrefix)
2796	{
2797	NOREF(pVM);
2798
2799	/*
2800	* Format the EFLAGS.
2801	*/
2802	uint32_t efl = pCtxCore->eflags.u32;
2803	char szEFlags[80];
2804	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2805
2806	/*
2807	* Format the registers.
2808	*/
2809	switch (enmType)
2810	{
2811	case CPUMDUMPTYPE_TERSE:
2812	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2813	pHlp->pfnPrintf(pHlp,
2814	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2815	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2816	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2817	"%sr14=%016RX64 %sr15=%016RX64\n"
2818	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2819	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2820	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2821	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2822	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2823	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2824	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2825	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2826	else
2827	pHlp->pfnPrintf(pHlp,
2828	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2829	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2830	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2831	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2832	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2833	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2834	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2835	break;
2836
2837	case CPUMDUMPTYPE_DEFAULT:
2838	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2839	pHlp->pfnPrintf(pHlp,
2840	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2841	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2842	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2843	"%sr14=%016RX64 %sr15=%016RX64\n"
2844	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2845	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2846	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2847	,
2848	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2849	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2850	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2851	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2852	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2853	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2854	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2855	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2856	else
2857	pHlp->pfnPrintf(pHlp,
2858	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2859	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2860	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2861	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2862	,
2863	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2864	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2865	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2866	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2867	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2868	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2869	break;
2870
2871	case CPUMDUMPTYPE_VERBOSE:
2872	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2873	pHlp->pfnPrintf(pHlp,
2874	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2875	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2876	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2877	"%sr14=%016RX64 %sr15=%016RX64\n"
2878	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2879	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2880	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2881	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2882	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2883	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2884	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2885	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2886	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2887	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2888	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2889	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2890	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2891	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2892	,
2893	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2894	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2895	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2896	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2897	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2898	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2899	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2900	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2901	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2902	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2903	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2904	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2905	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2906	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2907	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2908	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2909	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2910	else
2911	pHlp->pfnPrintf(pHlp,
2912	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2913	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2914	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2915	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2916	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2917	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2918	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2919	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2920	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2921	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2922	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2923	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2924	,
2925	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2926	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2927	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2928	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2929	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2930	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2931	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2932	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2933	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2934	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2935	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2936	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2937
2938	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
2939	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
2940	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
2941	if (pCtx->CTX_SUFF(pXState))
2942	{
2943	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
2944	pHlp->pfnPrintf(pHlp,
2945	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2946	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2947	,
2948	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
2949	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
2950	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
2951	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
2952	);
2953	/*
2954	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
2955	* not (FP)R0-7 as Intel SDM suggests.
2956	*/
2957	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
2958	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
2959	{
2960	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
2961	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
2962	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
2963	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
2964	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
2965	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
2966	iExponent -= 16383; /* subtract bias */
2967	/** @todo This isn't entirenly correct and needs more work! */
2968	pHlp->pfnPrintf(pHlp,
2969	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
2970	pszPrefix, iST, pszPrefix, iFPR,
2971	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
2972	uTag, chSign, iInteger, u64Fraction, iExponent);
2973	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
2974	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2975	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
2976	else
2977	pHlp->pfnPrintf(pHlp, "\n");
2978	}
2979
2980	/* XMM/YMM/ZMM registers. */
2981	if (pCtx->fXStateMask & XSAVE_C_YMM)
2982	{
2983	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2984	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
2985	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2986	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2987	pszPrefix, i, i < 10 ? " " : "",
2988	pYmmHiCtx->aYmmHi[i].au32[3],
2989	pYmmHiCtx->aYmmHi[i].au32[2],
2990	pYmmHiCtx->aYmmHi[i].au32[1],
2991	pYmmHiCtx->aYmmHi[i].au32[0],
2992	pFpuCtx->aXMM[i].au32[3],
2993	pFpuCtx->aXMM[i].au32[2],
2994	pFpuCtx->aXMM[i].au32[1],
2995	pFpuCtx->aXMM[i].au32[0]);
2996	else
2997	{
2998	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2999	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3000	pHlp->pfnPrintf(pHlp,
3001	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3002	pszPrefix, i, i < 10 ? " " : "",
3003	pZmmHi256->aHi256Regs[i].au32[7],
3004	pZmmHi256->aHi256Regs[i].au32[6],
3005	pZmmHi256->aHi256Regs[i].au32[5],
3006	pZmmHi256->aHi256Regs[i].au32[4],
3007	pZmmHi256->aHi256Regs[i].au32[3],
3008	pZmmHi256->aHi256Regs[i].au32[2],
3009	pZmmHi256->aHi256Regs[i].au32[1],
3010	pZmmHi256->aHi256Regs[i].au32[0],
3011	pYmmHiCtx->aYmmHi[i].au32[3],
3012	pYmmHiCtx->aYmmHi[i].au32[2],
3013	pYmmHiCtx->aYmmHi[i].au32[1],
3014	pYmmHiCtx->aYmmHi[i].au32[0],
3015	pFpuCtx->aXMM[i].au32[3],
3016	pFpuCtx->aXMM[i].au32[2],
3017	pFpuCtx->aXMM[i].au32[1],
3018	pFpuCtx->aXMM[i].au32[0]);
3019
3020	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
3021	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
3022	pHlp->pfnPrintf(pHlp,
3023	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3024	pszPrefix, i + 16,
3025	pZmm16Hi->aRegs[i].au32[15],
3026	pZmm16Hi->aRegs[i].au32[14],
3027	pZmm16Hi->aRegs[i].au32[13],
3028	pZmm16Hi->aRegs[i].au32[12],
3029	pZmm16Hi->aRegs[i].au32[11],
3030	pZmm16Hi->aRegs[i].au32[10],
3031	pZmm16Hi->aRegs[i].au32[9],
3032	pZmm16Hi->aRegs[i].au32[8],
3033	pZmm16Hi->aRegs[i].au32[7],
3034	pZmm16Hi->aRegs[i].au32[6],
3035	pZmm16Hi->aRegs[i].au32[5],
3036	pZmm16Hi->aRegs[i].au32[4],
3037	pZmm16Hi->aRegs[i].au32[3],
3038	pZmm16Hi->aRegs[i].au32[2],
3039	pZmm16Hi->aRegs[i].au32[1],
3040	pZmm16Hi->aRegs[i].au32[0]);
3041	}
3042	}
3043	else
3044	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3045	pHlp->pfnPrintf(pHlp,
3046	i & 1
3047	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3048	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3049	pszPrefix, i, i < 10 ? " " : "",
3050	pFpuCtx->aXMM[i].au32[3],
3051	pFpuCtx->aXMM[i].au32[2],
3052	pFpuCtx->aXMM[i].au32[1],
3053	pFpuCtx->aXMM[i].au32[0]);
3054
3055	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
3056	{
3057	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
3058	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
3059	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
3060	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
3061	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
3062	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
3063	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
3064	}
3065
3066	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
3067	{
3068	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
3069	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
3070	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
3071	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
3072	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
3073	}
3074
3075	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
3076	{
3077	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
3078	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
3079	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
3080	}
3081
3082	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
3083	if (pFpuCtx->au32RsrvdRest[i])
3084	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
3085	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
3086	}
3087
3088	pHlp->pfnPrintf(pHlp,
3089	"%sEFER =%016RX64\n"
3090	"%sPAT =%016RX64\n"
3091	"%sSTAR =%016RX64\n"
3092	"%sCSTAR =%016RX64\n"
3093	"%sLSTAR =%016RX64\n"
3094	"%sSFMASK =%016RX64\n"
3095	"%sKERNELGSBASE =%016RX64\n",
3096	pszPrefix, pCtx->msrEFER,
3097	pszPrefix, pCtx->msrPAT,
3098	pszPrefix, pCtx->msrSTAR,
3099	pszPrefix, pCtx->msrCSTAR,
3100	pszPrefix, pCtx->msrLSTAR,
3101	pszPrefix, pCtx->msrSFMASK,
3102	pszPrefix, pCtx->msrKERNELGSBASE);
3103	break;
3104	}
3105	}
3106
3107
3108	/**
3109	* Display all cpu states and any other cpum info.
3110	*
3111	* @param pVM The cross context VM structure.
3112	* @param pHlp The info helper functions.
3113	* @param pszArgs Arguments, ignored.
3114	*/
3115	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3116	{
3117	cpumR3InfoGuest(pVM, pHlp, pszArgs);
3118	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3119	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
3120	cpumR3InfoHyper(pVM, pHlp, pszArgs);
3121	cpumR3InfoHost(pVM, pHlp, pszArgs);
3122	}
3123
3124
3125	/**
3126	* Parses the info argument.
3127	*
3128	* The argument starts with 'verbose', 'terse' or 'default' and then
3129	* continues with the comment string.
3130	*
3131	* @param pszArgs The pointer to the argument string.
3132	* @param penmType Where to store the dump type request.
3133	* @param ppszComment Where to store the pointer to the comment string.
3134	*/
3135	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
3136	{
3137	if (!pszArgs)
3138	{
3139	*penmType = CPUMDUMPTYPE_DEFAULT;
3140	*ppszComment = "";
3141	}
3142	else
3143	{
3144	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3145	{
3146	pszArgs += 7;
3147	*penmType = CPUMDUMPTYPE_VERBOSE;
3148	}
3149	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3150	{
3151	pszArgs += 5;
3152	*penmType = CPUMDUMPTYPE_TERSE;
3153	}
3154	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3155	{
3156	pszArgs += 7;
3157	*penmType = CPUMDUMPTYPE_DEFAULT;
3158	}
3159	else
3160	*penmType = CPUMDUMPTYPE_DEFAULT;
3161	*ppszComment = RTStrStripL(pszArgs);
3162	}
3163	}
3164
3165
3166	/**
3167	* Display the guest cpu state.
3168	*
3169	* @param pVM The cross context VM structure.
3170	* @param pHlp The info helper functions.
3171	* @param pszArgs Arguments.
3172	*/
3173	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3174	{
3175	CPUMDUMPTYPE enmType;
3176	const char *pszComment;
3177	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3178
3179	PVMCPU pVCpu = VMMGetCpu(pVM);
3180	if (!pVCpu)
3181	pVCpu = &pVM->aCpus[0];
3182
3183	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3184
3185	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3186	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3187	}
3188
3189
3190	/**
3191	* Displays an SVM VMCB control area.
3192	*
3193	* @param pHlp The info helper functions.
3194	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
3195	* @param pszPrefix Caller specified string prefix.
3196	*/
3197	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
3198	{
3199	AssertReturnVoid(pHlp);
3200	AssertReturnVoid(pVmcbCtrl);
3201
3202	pHlp->pfnPrintf(pHlp, "%sCRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
3203	pHlp->pfnPrintf(pHlp, "%sCRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
3204	pHlp->pfnPrintf(pHlp, "%sDRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
3205	pHlp->pfnPrintf(pHlp, "%sDRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
3206	pHlp->pfnPrintf(pHlp, "%sException intercepts = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
3207	pHlp->pfnPrintf(pHlp, "%sControl intercepts = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
3208	pHlp->pfnPrintf(pHlp, "%sPause-filter threshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
3209	pHlp->pfnPrintf(pHlp, "%sPause-filter count = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
3210	pHlp->pfnPrintf(pHlp, "%sIOPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
3211	pHlp->pfnPrintf(pHlp, "%sMSRPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
3212	pHlp->pfnPrintf(pHlp, "%sTSC offset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
3213	pHlp->pfnPrintf(pHlp, "%sTLB Control\n", pszPrefix);
3214	pHlp->pfnPrintf(pHlp, " %sASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
3215	pHlp->pfnPrintf(pHlp, " %sTLB-flush type = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
3216	pHlp->pfnPrintf(pHlp, "%sInterrupt Control\n", pszPrefix);
3217	pHlp->pfnPrintf(pHlp, " %sVTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
3218	pHlp->pfnPrintf(pHlp, " %sVIRQ (Pending) = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
3219	pHlp->pfnPrintf(pHlp, " %sVINTR vector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
3220	pHlp->pfnPrintf(pHlp, " %sVGIF = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
3221	pHlp->pfnPrintf(pHlp, " %sVINTR priority = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
3222	pHlp->pfnPrintf(pHlp, " %sIgnore TPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
3223	pHlp->pfnPrintf(pHlp, " %sVINTR masking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
3224	pHlp->pfnPrintf(pHlp, " %sVGIF enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
3225	pHlp->pfnPrintf(pHlp, " %sAVIC enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
3226	pHlp->pfnPrintf(pHlp, "%sInterrupt Shadow\n", pszPrefix);
3227	pHlp->pfnPrintf(pHlp, " %sInterrupt shadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
3228	pHlp->pfnPrintf(pHlp, " %sGuest-interrupt Mask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
3229	pHlp->pfnPrintf(pHlp, "%sExit Code = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
3230	pHlp->pfnPrintf(pHlp, "%sEXITINFO1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
3231	pHlp->pfnPrintf(pHlp, "%sEXITINFO2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
3232	pHlp->pfnPrintf(pHlp, "%sExit Interrupt Info\n", pszPrefix);
3233	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
3234	pHlp->pfnPrintf(pHlp, " %sVector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
3235	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
3236	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
3237	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
3238	pHlp->pfnPrintf(pHlp, "%sNested paging and SEV\n", pszPrefix);
3239	pHlp->pfnPrintf(pHlp, " %sNested paging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
3240	pHlp->pfnPrintf(pHlp, " %sSEV (Secure Encrypted VM) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
3241	pHlp->pfnPrintf(pHlp, " %sSEV-ES (Encrypted State) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
3242	pHlp->pfnPrintf(pHlp, "%sEvent Inject\n", pszPrefix);
3243	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
3244	pHlp->pfnPrintf(pHlp, " %sVector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
3245	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
3246	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
3247	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
3248	pHlp->pfnPrintf(pHlp, "%sNested-paging CR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
3249	pHlp->pfnPrintf(pHlp, "%sLBR Virtualization\n", pszPrefix);
3250	pHlp->pfnPrintf(pHlp, " %sLBR virt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
3251	pHlp->pfnPrintf(pHlp, " %sVirt. VMSAVE/VMLOAD = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
3252	pHlp->pfnPrintf(pHlp, "%sVMCB Clean Bits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
3253	pHlp->pfnPrintf(pHlp, "%sNext-RIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
3254	pHlp->pfnPrintf(pHlp, "%sInstruction bytes fetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
3255	pHlp->pfnPrintf(pHlp, "%sInstruction bytes = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
3256	pHlp->pfnPrintf(pHlp, "%sAVIC\n", pszPrefix);
3257	pHlp->pfnPrintf(pHlp, " %sBar addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
3258	pHlp->pfnPrintf(pHlp, " %sBacking page addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
3259	pHlp->pfnPrintf(pHlp, " %sLogical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
3260	pHlp->pfnPrintf(pHlp, " %sPhysical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
3261	pHlp->pfnPrintf(pHlp, " %sLast guest core Id = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
3262	}
3263
3264
3265	/**
3266	* Helper for dumping the SVM VMCB selector registers.
3267	*
3268	* @param pHlp The info helper functions.
3269	* @param pSel Pointer to the SVM selector register.
3270	* @param pszName Name of the selector.
3271	* @param pszPrefix Caller specified string prefix.
3272	*/
3273	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
3274	{
3275	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
3276	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
3277	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
3278	}
3279
3280
3281	/**
3282	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
3283	*
3284	* @param pHlp The info helper functions.
3285	* @param pXdtr Pointer to the descriptor table register.
3286	* @param pszName Name of the descriptor table register.
3287	* @param pszPrefix Caller specified string prefix.
3288	*/
3289	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
3290	{
3291	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
3292	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
3293	}
3294
3295
3296	/**
3297	* Displays an SVM VMCB state-save area.
3298	*
3299	* @param pHlp The info helper functions.
3300	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
3301	* @param pszPrefix Caller specified string prefix.
3302	*/
3303	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
3304	{
3305	AssertReturnVoid(pHlp);
3306	AssertReturnVoid(pVmcbStateSave);
3307
3308	char szEFlags[80];
3309	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
3310
3311	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
3312	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
3313	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
3314	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
3315	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
3316	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
3317	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
3318	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
3319	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
3320	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
3321	pHlp->pfnPrintf(pHlp, "%sCPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
3322	pHlp->pfnPrintf(pHlp, "%sEFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
3323	pHlp->pfnPrintf(pHlp, "%sCR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
3324	pHlp->pfnPrintf(pHlp, "%sCR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
3325	pHlp->pfnPrintf(pHlp, "%sCR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
3326	pHlp->pfnPrintf(pHlp, "%sDR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
3327	pHlp->pfnPrintf(pHlp, "%sDR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
3328	pHlp->pfnPrintf(pHlp, "%sRFLAGS = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
3329	pHlp->pfnPrintf(pHlp, "%sRIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
3330	pHlp->pfnPrintf(pHlp, "%sRSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
3331	pHlp->pfnPrintf(pHlp, "%sRAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
3332	pHlp->pfnPrintf(pHlp, "%sSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
3333	pHlp->pfnPrintf(pHlp, "%sLSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
3334	pHlp->pfnPrintf(pHlp, "%sCSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
3335	pHlp->pfnPrintf(pHlp, "%sSFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
3336	pHlp->pfnPrintf(pHlp, "%sKERNELGSBASE = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
3337	pHlp->pfnPrintf(pHlp, "%sSysEnter CS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
3338	pHlp->pfnPrintf(pHlp, "%sSysEnter EIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
3339	pHlp->pfnPrintf(pHlp, "%sSysEnter ESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
3340	pHlp->pfnPrintf(pHlp, "%sCR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
3341	pHlp->pfnPrintf(pHlp, "%sPAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
3342	pHlp->pfnPrintf(pHlp, "%sDBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
3343	pHlp->pfnPrintf(pHlp, "%sBR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
3344	pHlp->pfnPrintf(pHlp, "%sBR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
3345	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
3346	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
3347	}
3348
3349
3350	/**
3351	* Displays a virtual-VMCS.
3352	*
3353	* @param pHlp The info helper functions.
3354	* @param pVmcs Pointer to a virtual VMCS.
3355	* @param pszPrefix Caller specified string prefix.
3356	*/
3357	static void cpumR3InfoVmxVmcs(PCDBGFINFOHLP pHlp, PCVMXVVMCS pVmcs, const char *pszPrefix)
3358	{
3359	AssertReturnVoid(pHlp);
3360	AssertReturnVoid(pVmcs);
3361
3362	/* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
3363	#define CPUMVMX_DUMP_HOST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3364	do { \
3365	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64}\n", \
3366	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u); \
3367	} while (0)
3368
3369	#define CPUMVMX_DUMP_HOST_FS_GS_TR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3370	do { \
3371	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64}\n", \
3372	(a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u); \
3373	} while (0)
3374
3375	#define CPUMVMX_DUMP_GUEST_SEGREG(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3376	do { \
3377	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
3378	(a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
3379	(a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr); \
3380	} while (0)
3381
3382	#define CPUMVMX_DUMP_GUEST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3383	do { \
3384	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64 limit=%08x}\n", \
3385	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit); \
3386	} while (0)
3387
3388	/* Header. */
3389	{
3390	pHlp->pfnPrintf(pHlp, "%sHeader:\n", pszPrefix);
3391	pHlp->pfnPrintf(pHlp, " %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId);
3392	pHlp->pfnPrintf(pHlp, " %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, HMGetVmxAbortDesc(pVmcs->enmVmxAbort));
3393	pHlp->pfnPrintf(pHlp, " %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, HMGetVmxVmcsStateDesc(pVmcs->fVmcsState));
3394	}
3395
3396	/* Control fields. */
3397	{
3398	/* 16-bit. */
3399	pHlp->pfnPrintf(pHlp, "%sControl:\n", pszPrefix);
3400	pHlp->pfnPrintf(pHlp, " %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid);
3401	pHlp->pfnPrintf(pHlp, " %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector);
3402	pHlp->pfnPrintf(pHlp, " %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex);
3403
3404	/* 32-bit. */
3405	pHlp->pfnPrintf(pHlp, " %sPinCtls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls);
3406	pHlp->pfnPrintf(pHlp, " %sProcCtls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls);
3407	pHlp->pfnPrintf(pHlp, " %sProcCtls2 = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2);
3408	pHlp->pfnPrintf(pHlp, " %sExitCtls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls);
3409	pHlp->pfnPrintf(pHlp, " %sEntryCtls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls);
3410	pHlp->pfnPrintf(pHlp, " %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap);
3411	pHlp->pfnPrintf(pHlp, " %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask);
3412	pHlp->pfnPrintf(pHlp, " %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch);
3413	pHlp->pfnPrintf(pHlp, " %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount);
3414	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount);
3415	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount);
3416	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount);
3417	pHlp->pfnPrintf(pHlp, " %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo);
3418	{
3419	uint32_t const fInfo = pVmcs->u32EntryIntInfo;
3420	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
3421	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo));
3422	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, HMGetVmxEntryIntInfoTypeDesc(uType));
3423	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo));
3424	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3425	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3426	}
3427	pHlp->pfnPrintf(pHlp, " %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode);
3428	pHlp->pfnPrintf(pHlp, " %sVM-entry instruction len = %u bytes\n", pszPrefix, pVmcs->u32EntryInstrLen);
3429	pHlp->pfnPrintf(pHlp, " %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold);
3430	pHlp->pfnPrintf(pHlp, " %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap);
3431	pHlp->pfnPrintf(pHlp, " %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow);
3432
3433	/* 64-bit. */
3434	pHlp->pfnPrintf(pHlp, " %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u);
3435	pHlp->pfnPrintf(pHlp, " %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u);
3436	pHlp->pfnPrintf(pHlp, " %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u);
3437	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u);
3438	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u);
3439	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u);
3440	pHlp->pfnPrintf(pHlp, " %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u);
3441	pHlp->pfnPrintf(pHlp, " %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u);
3442	pHlp->pfnPrintf(pHlp, " %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u);
3443	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u);
3444	pHlp->pfnPrintf(pHlp, " %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u);
3445	pHlp->pfnPrintf(pHlp, " %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u);
3446	pHlp->pfnPrintf(pHlp, " %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u);
3447	pHlp->pfnPrintf(pHlp, " %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptpPtr.u);
3448	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 0 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u);
3449	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 1 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u);
3450	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 2 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u);
3451	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 3 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u);
3452	pHlp->pfnPrintf(pHlp, " %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u);
3453	pHlp->pfnPrintf(pHlp, " %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u);
3454	pHlp->pfnPrintf(pHlp, " %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u);
3455	pHlp->pfnPrintf(pHlp, " %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u);
3456	pHlp->pfnPrintf(pHlp, " %sXSS-bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssBitmap.u);
3457	pHlp->pfnPrintf(pHlp, " %sENCLS-exiting bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEnclsBitmap.u);
3458	pHlp->pfnPrintf(pHlp, " %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u);
3459
3460	/* Natural width. */
3461	pHlp->pfnPrintf(pHlp, " %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u);
3462	pHlp->pfnPrintf(pHlp, " %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u);
3463	pHlp->pfnPrintf(pHlp, " %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u);
3464	pHlp->pfnPrintf(pHlp, " %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u);
3465	pHlp->pfnPrintf(pHlp, " %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u);
3466	pHlp->pfnPrintf(pHlp, " %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u);
3467	pHlp->pfnPrintf(pHlp, " %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u);
3468	pHlp->pfnPrintf(pHlp, " %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u);
3469	}
3470
3471	/* Guest state. */
3472	{
3473	char szEFlags[80];
3474	cpumR3InfoFormatFlags(&szEFlags[0], pVmcs->u64GuestRFlags.u);
3475	pHlp->pfnPrintf(pHlp, "%sGuest state:\n", pszPrefix);
3476
3477	/* 16-bit. */
3478	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Cs, "cs", pszPrefix);
3479	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ss, "ss", pszPrefix);
3480	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Es, "es", pszPrefix);
3481	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ds, "ds", pszPrefix);
3482	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Fs, "fs", pszPrefix);
3483	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Gs, "gs", pszPrefix);
3484	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ldtr, "ldtr", pszPrefix);
3485	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Tr, "tr", pszPrefix);
3486	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Gdtr, "gdtr", pszPrefix);
3487	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Idtr, "idtr", pszPrefix);
3488	pHlp->pfnPrintf(pHlp, " %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus);
3489	pHlp->pfnPrintf(pHlp, " %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex);
3490
3491	/* 32-bit. */
3492	pHlp->pfnPrintf(pHlp, " %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState);
3493	pHlp->pfnPrintf(pHlp, " %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState);
3494	pHlp->pfnPrintf(pHlp, " %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase);
3495	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS);
3496	pHlp->pfnPrintf(pHlp, " %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer);
3497
3498	/* 64-bit. */
3499	pHlp->pfnPrintf(pHlp, " %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u);
3500	pHlp->pfnPrintf(pHlp, " %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u);
3501	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u);
3502	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u);
3503	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u);
3504	pHlp->pfnPrintf(pHlp, " %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u);
3505	pHlp->pfnPrintf(pHlp, " %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u);
3506	pHlp->pfnPrintf(pHlp, " %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u);
3507	pHlp->pfnPrintf(pHlp, " %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u);
3508	pHlp->pfnPrintf(pHlp, " %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u);
3509
3510	/* Natural width. */
3511	pHlp->pfnPrintf(pHlp, " %scr0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u);
3512	pHlp->pfnPrintf(pHlp, " %scr3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u);
3513	pHlp->pfnPrintf(pHlp, " %scr4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u);
3514	pHlp->pfnPrintf(pHlp, " %sdr7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u);
3515	pHlp->pfnPrintf(pHlp, " %srsp = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u);
3516	pHlp->pfnPrintf(pHlp, " %srip = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u);
3517	pHlp->pfnPrintf(pHlp, " %srflags = %#RX64 %31s\n",pszPrefix, pVmcs->u64GuestRFlags.u, szEFlags);
3518	pHlp->pfnPrintf(pHlp, " %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpt.u);
3519	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u);
3520	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u);
3521	}
3522
3523	/* Host state. */
3524	{
3525	pHlp->pfnPrintf(pHlp, "%sHost state:\n", pszPrefix);
3526
3527	/* 16-bit. */
3528	pHlp->pfnPrintf(pHlp, " %scs = %#RX16\n", pszPrefix, pVmcs->HostCs);
3529	pHlp->pfnPrintf(pHlp, " %sss = %#RX16\n", pszPrefix, pVmcs->HostSs);
3530	pHlp->pfnPrintf(pHlp, " %sds = %#RX16\n", pszPrefix, pVmcs->HostDs);
3531	pHlp->pfnPrintf(pHlp, " %ses = %#RX16\n", pszPrefix, pVmcs->HostEs);
3532	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Fs, "fs", pszPrefix);
3533	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Gs, "gs", pszPrefix);
3534	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Tr, "tr", pszPrefix);
3535	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Gdtr, "gdtr", pszPrefix);
3536	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Idtr, "idtr", pszPrefix);
3537
3538	/* 32-bit. */
3539	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs);
3540
3541	/* 64-bit. */
3542	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u);
3543	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u);
3544	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u);
3545
3546	/* Natural width. */
3547	pHlp->pfnPrintf(pHlp, " %scr0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u);
3548	pHlp->pfnPrintf(pHlp, " %scr3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u);
3549	pHlp->pfnPrintf(pHlp, " %scr4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u);
3550	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u);
3551	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u);
3552	pHlp->pfnPrintf(pHlp, " %srsp = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u);
3553	pHlp->pfnPrintf(pHlp, " %srip = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u);
3554	}
3555
3556	/* Read-only fields. */
3557	{
3558	pHlp->pfnPrintf(pHlp, "%sRead-only data fields:\n", pszPrefix);
3559
3560	/* 16-bit (none currently). */
3561
3562	/* 32-bit. */
3563	pHlp->pfnPrintf(pHlp, " %sExit reason = %u (%s)\n", pszPrefix, pVmcs->u32RoExitReason, HMGetVmxExitName(pVmcs->u32RoExitReason));
3564	pHlp->pfnPrintf(pHlp, " %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u);
3565	pHlp->pfnPrintf(pHlp, " %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError);
3566	pHlp->pfnPrintf(pHlp, " %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo);
3567	{
3568	uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
3569	uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
3570	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo));
3571	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, HMGetVmxExitIntInfoTypeDesc(uType));
3572	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo));
3573	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3574	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3575	}
3576	pHlp->pfnPrintf(pHlp, " %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode);
3577	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo);
3578	{
3579	uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
3580	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
3581	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo));
3582	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, HMGetVmxIdtVectoringInfoTypeDesc(uType));
3583	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo));
3584	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo));
3585	}
3586	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode);
3587	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction length = %u bytes\n", pszPrefix, pVmcs->u32RoExitInstrLen);
3588	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo);
3589
3590	/* 64-bit. */
3591	pHlp->pfnPrintf(pHlp, " %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u);
3592
3593	/* Natural width. */
3594	pHlp->pfnPrintf(pHlp, " %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u);
3595	pHlp->pfnPrintf(pHlp, " %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u);
3596	pHlp->pfnPrintf(pHlp, " %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u);
3597	pHlp->pfnPrintf(pHlp, " %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u);
3598	pHlp->pfnPrintf(pHlp, " %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u);
3599	}
3600
3601	#undef CPUMVMX_DUMP_HOST_XDTR
3602	#undef CPUMVMX_DUMP_HOST_FS_GS_TR
3603	#undef CPUMVMX_DUMP_GUEST_SEGREG
3604	#undef CPUMVMX_DUMP_GUEST_XDTR
3605	}
3606
3607
3608	/**
3609	* Display the guest's hardware-virtualization cpu state.
3610	*
3611	* @param pVM The cross context VM structure.
3612	* @param pHlp The info helper functions.
3613	* @param pszArgs Arguments, ignored.
3614	*/
3615	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3616	{
3617	RT_NOREF(pszArgs);
3618
3619	PVMCPU pVCpu = VMMGetCpu(pVM);
3620	if (!pVCpu)
3621	pVCpu = &pVM->aCpus[0];
3622
3623	/*
3624	* Figure out what to dump.
3625	*
3626	* In the future we may need to dump everything whether or not we're actively in nested-guest mode
3627	* or not, hence the reason why we use a mask to determine what needs dumping. Currently, we only
3628	* dump hwvirt. state when the guest CPU is executing a nested-guest.
3629	*/
3630	/** @todo perhaps make this configurable through pszArgs, depending on how much
3631	* noise we wish to accept when nested hwvirt. isn't used. */
3632	#define CPUMHWVIRTDUMP_NONE (0)
3633	#define CPUMHWVIRTDUMP_SVM RT_BIT(0)
3634	#define CPUMHWVIRTDUMP_VMX RT_BIT(1)
3635	#define CPUMHWVIRTDUMP_COMMON RT_BIT(2)
3636	#define CPUMHWVIRTDUMP_LAST CPUMHWVIRTDUMP_VMX
3637
3638	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3639	static const char *const s_aHwvirtModes[] = { "No/inactive", "SVM", "VMX", "Common" };
3640	bool const fSvm = pVM->cpum.s.GuestFeatures.fSvm;
3641	bool const fVmx = pVM->cpum.s.GuestFeatures.fVmx;
3642	uint8_t const idxHwvirtState = fSvm ? CPUMHWVIRTDUMP_SVM : (fVmx ? CPUMHWVIRTDUMP_VMX : CPUMHWVIRTDUMP_NONE);
3643	AssertCompile(CPUMHWVIRTDUMP_LAST <= RT_ELEMENTS(s_aHwvirtModes));
3644	Assert(idxHwvirtState < RT_ELEMENTS(s_aHwvirtModes));
3645	const char *pcszHwvirtMode = s_aHwvirtModes[idxHwvirtState];
3646	uint32_t fDumpState = idxHwvirtState \| CPUMHWVIRTDUMP_COMMON;
3647
3648	/*
3649	* Dump it.
3650	*/
3651	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
3652
3653	if (fDumpState & CPUMHWVIRTDUMP_COMMON)
3654	pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
3655
3656	pHlp->pfnPrintf(pHlp, "%s hwvirt state%s\n", pcszHwvirtMode, (fDumpState & (CPUMHWVIRTDUMP_SVM \| CPUMHWVIRTDUMP_VMX)) ?
3657	":" : "");
3658	if (fDumpState & CPUMHWVIRTDUMP_SVM)
3659	{
3660	pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
3661
3662	char szEFlags[80];
3663	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
3664	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
3665	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
3666	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
3667	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.pVmcbR3->ctrl, " " /* pszPrefix */);
3668	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
3669	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.pVmcbR3->guest, " " /* pszPrefix */);
3670	pHlp->pfnPrintf(pHlp, " HostState:\n");
3671	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
3672	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
3673	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
3674	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
3675	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
3676	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
3677	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
3678	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
3679	PCPUMSELREG pSel = &pCtx->hwvirt.svm.HostState.es;
3680	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3681	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
3682	pSel = &pCtx->hwvirt.svm.HostState.cs;
3683	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3684	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
3685	pSel = &pCtx->hwvirt.svm.HostState.ss;
3686	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3687	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
3688	pSel = &pCtx->hwvirt.svm.HostState.ds;
3689	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3690	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
3691	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
3692	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
3693	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
3694	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
3695	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
3696	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
3697	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
3698	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR3 = %p\n", pCtx->hwvirt.svm.pvMsrBitmapR3);
3699	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvMsrBitmapR0);
3700	pHlp->pfnPrintf(pHlp, " pvIoBitmapR3 = %p\n", pCtx->hwvirt.svm.pvIoBitmapR3);
3701	pHlp->pfnPrintf(pHlp, " pvIoBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvIoBitmapR0);
3702	}
3703
3704	if (fDumpState & CPUMHWVIRTDUMP_VMX)
3705	{
3706	pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
3707	pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
3708	pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
3709	pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag));
3710	pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, HMGetVmxAbortDesc(pCtx->hwvirt.vmx.enmAbort));
3711	pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
3712	pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
3713	pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
3714	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
3715	pHlp->pfnPrintf(pHlp, " fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret);
3716	pHlp->pfnPrintf(pHlp, " uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick);
3717	pHlp->pfnPrintf(pHlp, " uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick);
3718	pHlp->pfnPrintf(pHlp, " uVmentryTick = %RX64\n", pCtx->hwvirt.vmx.uVmentryTick);
3719	pHlp->pfnPrintf(pHlp, " offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite);
3720	pHlp->pfnPrintf(pHlp, " VMCS cache:\n");
3721	cpumR3InfoVmxVmcs(pHlp, pCtx->hwvirt.vmx.pVmcsR3, " " /* pszPrefix */);
3722	}
3723
3724	#undef CPUMHWVIRTDUMP_NONE
3725	#undef CPUMHWVIRTDUMP_COMMON
3726	#undef CPUMHWVIRTDUMP_SVM
3727	#undef CPUMHWVIRTDUMP_VMX
3728	#undef CPUMHWVIRTDUMP_LAST
3729	#undef CPUMHWVIRTDUMP_ALL
3730	}
3731
3732	/**
3733	* Display the current guest instruction
3734	*
3735	* @param pVM The cross context VM structure.
3736	* @param pHlp The info helper functions.
3737	* @param pszArgs Arguments, ignored.
3738	*/
3739	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3740	{
3741	NOREF(pszArgs);
3742
3743	PVMCPU pVCpu = VMMGetCpu(pVM);
3744	if (!pVCpu)
3745	pVCpu = &pVM->aCpus[0];
3746
3747	char szInstruction[256];
3748	szInstruction[0] = '\0';
3749	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
3750	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
3751	}
3752
3753
3754	/**
3755	* Display the hypervisor cpu state.
3756	*
3757	* @param pVM The cross context VM structure.
3758	* @param pHlp The info helper functions.
3759	* @param pszArgs Arguments, ignored.
3760	*/
3761	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3762	{
3763	PVMCPU pVCpu = VMMGetCpu(pVM);
3764	if (!pVCpu)
3765	pVCpu = &pVM->aCpus[0];
3766
3767	CPUMDUMPTYPE enmType;
3768	const char *pszComment;
3769	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3770	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
3771	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
3772	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
3773	}
3774
3775
3776	/**
3777	* Display the host cpu state.
3778	*
3779	* @param pVM The cross context VM structure.
3780	* @param pHlp The info helper functions.
3781	* @param pszArgs Arguments, ignored.
3782	*/
3783	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3784	{
3785	CPUMDUMPTYPE enmType;
3786	const char *pszComment;
3787	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3788	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
3789
3790	PVMCPU pVCpu = VMMGetCpu(pVM);
3791	if (!pVCpu)
3792	pVCpu = &pVM->aCpus[0];
3793	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
3794
3795	/*
3796	* Format the EFLAGS.
3797	*/
3798	#if HC_ARCH_BITS == 32
3799	uint32_t efl = pCtx->eflags.u32;
3800	#else
3801	uint64_t efl = pCtx->rflags;
3802	#endif
3803	char szEFlags[80];
3804	cpumR3InfoFormatFlags(&szEFlags[0], efl);
3805
3806	/*
3807	* Format the registers.
3808	*/
3809	#if HC_ARCH_BITS == 32
3810	pHlp->pfnPrintf(pHlp,
3811	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
3812	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
3813	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
3814	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
3815	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
3816	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3817	,
3818	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
3819	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
3820	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3821	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
3822	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
3823	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
3824	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3825	#else
3826	pHlp->pfnPrintf(pHlp,
3827	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
3828	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
3829	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
3830	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
3831	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
3832	"r14=%016RX64 r15=%016RX64\n"
3833	"iopl=%d %31s\n"
3834	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
3835	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
3836	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
3837	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
3838	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
3839	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
3840	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3841	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
3842	,
3843	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
3844	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
3845	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
3846	/pCtx->r8, pCtx->r9,/ pCtx->r10,
3847	pCtx->r11, pCtx->r12, pCtx->r13,
3848	pCtx->r14, pCtx->r15,
3849	X86_EFL_GET_IOPL(efl), szEFlags,
3850	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3851	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
3852	pCtx->cr4, pCtx->ldtr, pCtx->tr,
3853	pCtx->dr0, pCtx->dr1, pCtx->dr2,
3854	pCtx->dr3, pCtx->dr6, pCtx->dr7,
3855	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
3856	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
3857	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
3858	#endif
3859	}
3860
3861	/**
3862	* Structure used when disassembling and instructions in DBGF.
3863	* This is used so the reader function can get the stuff it needs.
3864	*/
3865	typedef struct CPUMDISASSTATE
3866	{
3867	/** Pointer to the CPU structure. */
3868	PDISCPUSTATE pCpu;
3869	/** Pointer to the VM. */
3870	PVM pVM;
3871	/** Pointer to the VMCPU. */
3872	PVMCPU pVCpu;
3873	/** Pointer to the first byte in the segment. */
3874	RTGCUINTPTR GCPtrSegBase;
3875	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3876	RTGCUINTPTR GCPtrSegEnd;
3877	/** The size of the segment minus 1. */
3878	RTGCUINTPTR cbSegLimit;
3879	/** Pointer to the current page - R3 Ptr. */
3880	void const *pvPageR3;
3881	/** Pointer to the current page - GC Ptr. */
3882	RTGCPTR pvPageGC;
3883	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3884	PGMPAGEMAPLOCK PageMapLock;
3885	/** Whether the PageMapLock is valid or not. */
3886	bool fLocked;
3887	/** 64 bits mode or not. */
3888	bool f64Bits;
3889	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3890
3891
3892	/**
3893	* @callback_method_impl{FNDISREADBYTES}
3894	*/
3895	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
3896	{
3897	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
3898	for (;;)
3899	{
3900	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
3901
3902	/*
3903	* Need to update the page translation?
3904	*/
3905	if ( !pState->pvPageR3
3906	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3907	{
3908	int rc = VINF_SUCCESS;
3909
3910	/* translate the address */
3911	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3912	if ( VM_IS_RAW_MODE_ENABLED(pState->pVM)
3913	&& MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
3914	{
3915	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3916	if (!pState->pvPageR3)
3917	rc = VERR_INVALID_POINTER;
3918	}
3919	else
3920	{
3921	/* Release mapping lock previously acquired. */
3922	if (pState->fLocked)
3923	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3924	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3925	pState->fLocked = RT_SUCCESS_NP(rc);
3926	}
3927	if (RT_FAILURE(rc))
3928	{
3929	pState->pvPageR3 = NULL;
3930	return rc;
3931	}
3932	}
3933
3934	/*
3935	* Check the segment limit.
3936	*/
3937	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
3938	return VERR_OUT_OF_SELECTOR_BOUNDS;
3939
3940	/*
3941	* Calc how much we can read.
3942	*/
3943	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3944	if (!pState->f64Bits)
3945	{
3946	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3947	if (cb > cbSeg && cbSeg)
3948	cb = cbSeg;
3949	}
3950	if (cb > cbMaxRead)
3951	cb = cbMaxRead;
3952
3953	/*
3954	* Read and advance or exit.
3955	*/
3956	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3957	offInstr += (uint8_t)cb;
3958	if (cb >= cbMinRead)
3959	{
3960	pDis->cbCachedInstr = offInstr;
3961	return VINF_SUCCESS;
3962	}
3963	cbMinRead -= (uint8_t)cb;
3964	cbMaxRead -= (uint8_t)cb;
3965	}
3966	}
3967
3968
3969	/**
3970	* Disassemble an instruction and return the information in the provided structure.
3971	*
3972	* @returns VBox status code.
3973	* @param pVM The cross context VM structure.
3974	* @param pVCpu The cross context virtual CPU structure.
3975	* @param pCtx Pointer to the guest CPU context.
3976	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3977	* @param pCpu Disassembly state.
3978	* @param pszPrefix String prefix for logging (debug only).
3979	*
3980	*/
3981	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
3982	const char *pszPrefix)
3983	{
3984	CPUMDISASSTATE State;
3985	int rc;
3986
3987	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3988	State.pCpu = pCpu;
3989	State.pvPageGC = 0;
3990	State.pvPageR3 = NULL;
3991	State.pVM = pVM;
3992	State.pVCpu = pVCpu;
3993	State.fLocked = false;
3994	State.f64Bits = false;
3995
3996	/*
3997	* Get selector information.
3998	*/
3999	DISCPUMODE enmDisCpuMode;
4000	if ( (pCtx->cr0 & X86_CR0_PE)
4001	&& pCtx->eflags.Bits.u1VM == 0)
4002	{
4003	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4004	{
4005	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
4006	CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
4007	# endif
4008	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4009	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4010	}
4011	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4012	State.GCPtrSegBase = pCtx->cs.u64Base;
4013	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4014	State.cbSegLimit = pCtx->cs.u32Limit;
4015	enmDisCpuMode = (State.f64Bits)
4016	? DISCPUMODE_64BIT
4017	: pCtx->cs.Attr.n.u1DefBig
4018	? DISCPUMODE_32BIT
4019	: DISCPUMODE_16BIT;
4020	}
4021	else
4022	{
4023	/* real or V86 mode */
4024	enmDisCpuMode = DISCPUMODE_16BIT;
4025	State.GCPtrSegBase = pCtx->cs.Sel * 16;
4026	State.GCPtrSegEnd = 0xFFFFFFFF;
4027	State.cbSegLimit = 0xFFFFFFFF;
4028	}
4029
4030	/*
4031	* Disassemble the instruction.
4032	*/
4033	uint32_t cbInstr;
4034	#ifndef LOG_ENABLED
4035	RT_NOREF_PV(pszPrefix);
4036	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4037	if (RT_SUCCESS(rc))
4038	{
4039	#else
4040	char szOutput[160];
4041	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4042	pCpu, &cbInstr, szOutput, sizeof(szOutput));
4043	if (RT_SUCCESS(rc))
4044	{
4045	/* log it */
4046	if (pszPrefix)
4047	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4048	else
4049	Log(("%s", szOutput));
4050	#endif
4051	rc = VINF_SUCCESS;
4052	}
4053	else
4054	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4055
4056	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
4057	if (State.fLocked)
4058	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4059
4060	return rc;
4061	}
4062
4063
4064
4065	/**
4066	* API for controlling a few of the CPU features found in CR4.
4067	*
4068	* Currently only X86_CR4_TSD is accepted as input.
4069	*
4070	* @returns VBox status code.
4071	*
4072	* @param pVM The cross context VM structure.
4073	* @param fOr The CR4 OR mask.
4074	* @param fAnd The CR4 AND mask.
4075	*/
4076	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4077	{
4078	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4079	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4080
4081	pVM->cpum.s.CR4.OrMask &= fAnd;
4082	pVM->cpum.s.CR4.OrMask \|= fOr;
4083
4084	return VINF_SUCCESS;
4085	}
4086
4087
4088	/**
4089	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
4090	*
4091	* Only REM should ever call this function!
4092	*
4093	* @returns The changed flags.
4094	* @param pVCpu The cross context virtual CPU structure.
4095	* @param puCpl Where to return the current privilege level (CPL).
4096	*/
4097	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
4098	{
4099	Assert(!pVCpu->cpum.s.fRawEntered);
4100	Assert(!pVCpu->cpum.s.fRemEntered);
4101
4102	/*
4103	* Get the CPL first.
4104	*/
4105	*puCpl = CPUMGetGuestCPL(pVCpu);
4106
4107	/*
4108	* Get and reset the flags.
4109	*/
4110	uint32_t fFlags = pVCpu->cpum.s.fChanged;
4111	pVCpu->cpum.s.fChanged = 0;
4112
4113	/** @todo change the switcher to use the fChanged flags. */
4114	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
4115	{
4116	fFlags \|= CPUM_CHANGED_FPU_REM;
4117	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
4118	}
4119
4120	pVCpu->cpum.s.fRemEntered = true;
4121	return fFlags;
4122	}
4123
4124
4125	/**
4126	* Leaves REM.
4127	*
4128	* @param pVCpu The cross context virtual CPU structure.
4129	* @param fNoOutOfSyncSels This is @c false if there are out of sync
4130	* registers.
4131	*/
4132	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
4133	{
4134	Assert(!pVCpu->cpum.s.fRawEntered);
4135	Assert(pVCpu->cpum.s.fRemEntered);
4136
4137	RT_NOREF_PV(fNoOutOfSyncSels);
4138
4139	pVCpu->cpum.s.fRemEntered = false;
4140	}
4141
4142
4143	/**
4144	* Called when the ring-3 init phase completes.
4145	*
4146	* @returns VBox status code.
4147	* @param pVM The cross context VM structure.
4148	* @param enmWhat Which init phase.
4149	*/
4150	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
4151	{
4152	switch (enmWhat)
4153	{
4154	case VMINITCOMPLETED_RING3:
4155	{
4156	/*
4157	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
4158	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
4159	*/
4160	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
4161	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4162	{
4163	PVMCPU pVCpu = &pVM->aCpus[i];
4164	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
4165	if (fSupportsLongMode)
4166	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
4167	}
4168
4169	/* Register statistic counters for MSRs. */
4170	cpumR3MsrRegStats(pVM);
4171	break;
4172	}
4173
4174	default:
4175	break;
4176	}
4177	return VINF_SUCCESS;
4178	}
4179
4180
4181	/**
4182	* Called when the ring-0 init phases completed.
4183	*
4184	* @param pVM The cross context VM structure.
4185	*/
4186	VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
4187	{
4188	/*
4189	* Enable log buffering as we're going to log a lot of lines.
4190	*/
4191	bool const fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
4192
4193	/*
4194	* Log the cpuid.
4195	*/
4196	RTCPUSET OnlineSet;
4197	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4198	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4199	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4200	RTCPUID cCores = RTMpGetCoreCount();
4201	if (cCores)
4202	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
4203	LogRel(("*********************** CPUID dump **********************\n"));
4204	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4205	LogRel(("\n"));
4206	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
4207	LogRel(("****************** End of CPUID dump ********************\n"));
4208
4209	/*
4210	* Log VT-x extended features.
4211	*
4212	* SVM features are currently all covered under CPUID so there is nothing
4213	* to do here for SVM.
4214	*/
4215	if (pVM->cpum.s.HostFeatures.fVmx)
4216	{
4217	LogRel(("********************* VT-x features *********************\n"));
4218	DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
4219	LogRel(("\n"));
4220	LogRel(("***************** End of VT-x features ******************\n"));
4221	}
4222
4223	/*
4224	* Restore the log buffering state to what it was previously.
4225	*/
4226	RTLogRelSetBuffering(fOldBuffered);
4227	}
4228

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 78126

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