CPUM.cpp@ 97231

Last change on this file since 97231 was 97231, checked in by vboxsync, 2 years ago
VMM/CPUM: Define our own X86EFLAGS/X86RFLAGS structures so we can use reserved bits for internal state.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 244.4 KB

Line
1	/* $Id: CPUM.cpp 97231 2022-10-19 09:12:57Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	/** @page pg_cpum CPUM - CPU Monitor / Manager
29	*
30	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
31	* also responsible for lazy FPU handling and some of the context loading
32	* in raw mode.
33	*
34	* There are three CPU contexts, the most important one is the guest one (GC).
35	* When running in raw-mode (RC) there is a special hyper context for the VMM
36	* part that floats around inside the guest address space. When running in
37	* raw-mode, CPUM also maintains a host context for saving and restoring
38	* registers across world switches. This latter is done in cooperation with the
39	* world switcher (@see pg_vmm).
40	*
41	* @see grp_cpum
42	*
43	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
44	*
45	* TODO: proper write up, currently just some notes.
46	*
47	* The ring-0 FPU handling per OS:
48	*
49	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
50	* convention (Visual C++ doesn't seem to have a way to disable
51	* generating such code either), so CR0.TS/EM are always zero from what I
52	* can tell. We are also forced to always load/save the guest XMM0-XMM15
53	* registers when entering/leaving guest context. Interrupt handlers
54	* using FPU/SSE will offically have call save and restore functions
55	* exported by the kernel, if the really really have to use the state.
56	*
57	* - 32-bit windows does lazy FPU handling, I think, probably including
58	* lazying saving. The Windows Internals book states that it's a bad
59	* idea to use the FPU in kernel space. However, it looks like it will
60	* restore the FPU state of the current thread in case of a kernel \#NM.
61	* Interrupt handlers should be same as for 64-bit.
62	*
63	* - Darwin allows taking \#NM in kernel space, restoring current thread's
64	* state if I read the code correctly. It saves the FPU state of the
65	* outgoing thread, and uses CR0.TS to lazily load the state of the
66	* incoming one. No idea yet how the FPU is treated by interrupt
67	* handlers, i.e. whether they are allowed to disable the state or
68	* something.
69	*
70	* - Linux also allows \#NM in kernel space (don't know since when), and
71	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
72	* loads the incoming unless configured to agressivly load it. Interrupt
73	* handlers can ask whether they're allowed to use the FPU, and may
74	* freely trash the state if Linux thinks it has saved the thread's state
75	* already. This is a problem.
76	*
77	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
78	* context. When switching threads, the kernel will save the state of
79	* the outgoing thread and lazy load the incoming one using CR0.TS.
80	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
81	* to do stuff, HAT are among the users. The routines there will
82	* manually clear CR0.TS and save the XMM registers they use only if
83	* CR0.TS was zero upon entry. They will skip it when not, because as
84	* mentioned above, the FPU state is saved when switching away from a
85	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
86	* preserve. This is a problem if we restore CR0.TS to 1 after loading
87	* the guest state.
88	*
89	* - FreeBSD - no idea yet.
90	*
91	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
92	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
93	* FPU states.
94	*
95	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
96	* saving and restoring the host and guest states. The motivation for this
97	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
98	*
99	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
100	* state and only restore it once we've restore the host FPU state. This has the
101	* accidental side effect of triggering Solaris to preserve XMM registers in
102	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
103	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
104	*
105	*
106	* @section sec_cpum_logging Logging Level Assignments.
107	*
108	* Following log level assignments:
109	* - Log6 is used for FPU state management.
110	* - Log7 is used for FPU state actualization.
111	*
112	*/
113
114
115	/*********************************************************************************************************************************
116	* Header Files *
117	*********************************************************************************************************************************/
118	#define LOG_GROUP LOG_GROUP_CPUM
119	#define CPUM_WITH_NONCONST_HOST_FEATURES
120	#include <VBox/vmm/cpum.h>
121	#include <VBox/vmm/cpumdis.h>
122	#include <VBox/vmm/cpumctx-v1_6.h>
123	#include <VBox/vmm/pgm.h>
124	#include <VBox/vmm/apic.h>
125	#include <VBox/vmm/mm.h>
126	#include <VBox/vmm/em.h>
127	#include <VBox/vmm/iem.h>
128	#include <VBox/vmm/selm.h>
129	#include <VBox/vmm/dbgf.h>
130	#include <VBox/vmm/hm.h>
131	#include <VBox/vmm/hmvmxinline.h>
132	#include <VBox/vmm/ssm.h>
133	#include "CPUMInternal.h"
134	#include <VBox/vmm/vm.h>
135
136	#include <VBox/param.h>
137	#include <VBox/dis.h>
138	#include <VBox/err.h>
139	#include <VBox/log.h>
140	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
141	# include <iprt/asm-amd64-x86.h>
142	#endif
143	#include <iprt/assert.h>
144	#include <iprt/cpuset.h>
145	#include <iprt/mem.h>
146	#include <iprt/mp.h>
147	#include <iprt/rand.h>
148	#include <iprt/string.h>
149
150
151	/*********************************************************************************************************************************
152	* Defined Constants And Macros *
153	*********************************************************************************************************************************/
154	/**
155	* This was used in the saved state up to the early life of version 14.
156	*
157	* It indicates that we may have some out-of-sync hidden segement registers.
158	* It is only relevant for raw-mode.
159	*/
160	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
161
162
163	/** For saved state only: Block injection of non-maskable interrupts to the guest.
164	* @note This flag was moved to CPUMCTX::fInhibit in v7.0.2. */
165	#define CPUM_OLD_VMCPU_FF_BLOCK_NMIS RT_BIT_64(25)
166
167
168	/*********************************************************************************************************************************
169	* Structures and Typedefs *
170	*********************************************************************************************************************************/
171
172	/**
173	* What kind of cpu info dump to perform.
174	*/
175	typedef enum CPUMDUMPTYPE
176	{
177	CPUMDUMPTYPE_TERSE,
178	CPUMDUMPTYPE_DEFAULT,
179	CPUMDUMPTYPE_VERBOSE
180	} CPUMDUMPTYPE;
181	/** Pointer to a cpu info dump type. */
182	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
183
184
185	/*********************************************************************************************************************************
186	* Internal Functions *
187	*********************************************************************************************************************************/
188	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
189	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
190	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
191	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
192	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
193	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
194	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
195	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
196	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
197	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
198	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
199
200
201	/*********************************************************************************************************************************
202	* Global Variables *
203	*********************************************************************************************************************************/
204	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
205	/** Host CPU features. */
206	DECL_HIDDEN_DATA(CPUHOSTFEATURES) g_CpumHostFeatures;
207	#endif
208
209	/** Saved state field descriptors for CPUMCTX. */
210	static const SSMFIELD g_aCpumCtxFields[] =
211	{
212	SSMFIELD_ENTRY( CPUMCTX, rdi),
213	SSMFIELD_ENTRY( CPUMCTX, rsi),
214	SSMFIELD_ENTRY( CPUMCTX, rbp),
215	SSMFIELD_ENTRY( CPUMCTX, rax),
216	SSMFIELD_ENTRY( CPUMCTX, rbx),
217	SSMFIELD_ENTRY( CPUMCTX, rdx),
218	SSMFIELD_ENTRY( CPUMCTX, rcx),
219	SSMFIELD_ENTRY( CPUMCTX, rsp),
220	SSMFIELD_ENTRY( CPUMCTX, rflags),
221	SSMFIELD_ENTRY( CPUMCTX, rip),
222	SSMFIELD_ENTRY( CPUMCTX, r8),
223	SSMFIELD_ENTRY( CPUMCTX, r9),
224	SSMFIELD_ENTRY( CPUMCTX, r10),
225	SSMFIELD_ENTRY( CPUMCTX, r11),
226	SSMFIELD_ENTRY( CPUMCTX, r12),
227	SSMFIELD_ENTRY( CPUMCTX, r13),
228	SSMFIELD_ENTRY( CPUMCTX, r14),
229	SSMFIELD_ENTRY( CPUMCTX, r15),
230	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
243	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
244	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
245	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
246	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
247	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
248	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
249	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
250	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
251	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
252	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
253	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
254	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
255	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
256	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
257	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
258	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
259	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
260	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
261	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
262	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
263	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
264	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
265	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
266	SSMFIELD_ENTRY( CPUMCTX, cr0),
267	SSMFIELD_ENTRY( CPUMCTX, cr2),
268	SSMFIELD_ENTRY( CPUMCTX, cr3),
269	SSMFIELD_ENTRY( CPUMCTX, cr4),
270	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
271	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
272	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
273	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
274	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
275	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
276	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
277	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
278	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
279	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
280	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
281	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
282	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
283	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
284	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
285	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
286	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
287	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
288	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
289	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
290	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
291	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
292	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
293	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
294	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
295	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
296	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
297	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
298	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
299	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
300	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
301	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
302	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
303	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
304	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
305	SSMFIELD_ENTRY_TERM()
306	};
307
308	/** Saved state field descriptors for SVM nested hardware-virtualization
309	* Host State. */
310	static const SSMFIELD g_aSvmHwvirtHostState[] =
311	{
312	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
313	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
314	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
315	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
316	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
317	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
318	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
319	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
320	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
321	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
322	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
323	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
324	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
325	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
326	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
327	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
328	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
329	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
330	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
331	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
332	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
333	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
334	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
335	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
336	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
337	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
338	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
339	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
340	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
341	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
342	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
343	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
344	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
345	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
346	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
347	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
348	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
349	SSMFIELD_ENTRY_TERM()
350	};
351
352	/** Saved state field descriptors for VMX nested hardware-virtualization
353	* VMCS. */
354	static const SSMFIELD g_aVmxHwvirtVmcs[] =
355	{
356	SSMFIELD_ENTRY( VMXVVMCS, u32VmcsRevId),
357	SSMFIELD_ENTRY( VMXVVMCS, enmVmxAbort),
358	SSMFIELD_ENTRY( VMXVVMCS, fVmcsState),
359	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au8Padding0),
360	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved0),
361
362	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, u16Reserved0),
363
364	SSMFIELD_ENTRY( VMXVVMCS, u32RoVmInstrError),
365	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitReason),
366	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntInfo),
367	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntErrCode),
368	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringInfo),
369	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringErrCode),
370	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrLen),
371	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrInfo),
372	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32RoReserved2),
373
374	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestPhysAddr),
375	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved1),
376
377	SSMFIELD_ENTRY( VMXVVMCS, u64RoExitQual),
378	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRcx),
379	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRsi),
380	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRdi),
381	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRip),
382	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestLinearAddr),
383	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved5),
384
385	SSMFIELD_ENTRY( VMXVVMCS, u16Vpid),
386	SSMFIELD_ENTRY( VMXVVMCS, u16PostIntNotifyVector),
387	SSMFIELD_ENTRY( VMXVVMCS, u16EptpIndex),
388	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved0),
389
390	SSMFIELD_ENTRY( VMXVVMCS, u32PinCtls),
391	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls),
392	SSMFIELD_ENTRY( VMXVVMCS, u32XcptBitmap),
393	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMask),
394	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMatch),
395	SSMFIELD_ENTRY( VMXVVMCS, u32Cr3TargetCount),
396	SSMFIELD_ENTRY( VMXVVMCS, u32ExitCtls),
397	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrStoreCount),
398	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrLoadCount),
399	SSMFIELD_ENTRY( VMXVVMCS, u32EntryCtls),
400	SSMFIELD_ENTRY( VMXVVMCS, u32EntryMsrLoadCount),
401	SSMFIELD_ENTRY( VMXVVMCS, u32EntryIntInfo),
402	SSMFIELD_ENTRY( VMXVVMCS, u32EntryXcptErrCode),
403	SSMFIELD_ENTRY( VMXVVMCS, u32EntryInstrLen),
404	SSMFIELD_ENTRY( VMXVVMCS, u32TprThreshold),
405	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls2),
406	SSMFIELD_ENTRY( VMXVVMCS, u32PleGap),
407	SSMFIELD_ENTRY( VMXVVMCS, u32PleWindow),
408	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved1),
409
410	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapA),
411	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapB),
412	SSMFIELD_ENTRY( VMXVVMCS, u64AddrMsrBitmap),
413	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrStore),
414	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrLoad),
415	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEntryMsrLoad),
416	SSMFIELD_ENTRY( VMXVVMCS, u64ExecVmcsPtr),
417	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPml),
418	SSMFIELD_ENTRY( VMXVVMCS, u64TscOffset),
419	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVirtApic),
420	SSMFIELD_ENTRY( VMXVVMCS, u64AddrApicAccess),
421	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPostedIntDesc),
422	SSMFIELD_ENTRY( VMXVVMCS, u64VmFuncCtls),
423	SSMFIELD_ENTRY( VMXVVMCS, u64EptPtr),
424	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap0),
425	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap1),
426	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap2),
427	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap3),
428	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEptpList),
429	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmreadBitmap),
430	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmwriteBitmap),
431	SSMFIELD_ENTRY( VMXVVMCS, u64AddrXcptVeInfo),
432	SSMFIELD_ENTRY( VMXVVMCS, u64XssExitBitmap),
433	SSMFIELD_ENTRY( VMXVVMCS, u64EnclsExitBitmap),
434	SSMFIELD_ENTRY( VMXVVMCS, u64SppTablePtr),
435	SSMFIELD_ENTRY( VMXVVMCS, u64TscMultiplier),
436	SSMFIELD_ENTRY_VER( VMXVVMCS, u64ProcCtls3, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
437	SSMFIELD_ENTRY_VER( VMXVVMCS, u64EnclvExitBitmap, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
438	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved0),
439
440	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0Mask),
441	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4Mask),
442	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0ReadShadow),
443	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4ReadShadow),
444	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target0),
445	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target1),
446	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target2),
447	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target3),
448	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved4),
449
450	SSMFIELD_ENTRY( VMXVVMCS, HostEs),
451	SSMFIELD_ENTRY( VMXVVMCS, HostCs),
452	SSMFIELD_ENTRY( VMXVVMCS, HostSs),
453	SSMFIELD_ENTRY( VMXVVMCS, HostDs),
454	SSMFIELD_ENTRY( VMXVVMCS, HostFs),
455	SSMFIELD_ENTRY( VMXVVMCS, HostGs),
456	SSMFIELD_ENTRY( VMXVVMCS, HostTr),
457	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved2),
458
459	SSMFIELD_ENTRY( VMXVVMCS, u32HostSysenterCs),
460	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved4),
461
462	SSMFIELD_ENTRY( VMXVVMCS, u64HostPatMsr),
463	SSMFIELD_ENTRY( VMXVVMCS, u64HostEferMsr),
464	SSMFIELD_ENTRY( VMXVVMCS, u64HostPerfGlobalCtlMsr),
465	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
466	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved3),
467
468	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr0),
469	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr3),
470	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr4),
471	SSMFIELD_ENTRY( VMXVVMCS, u64HostFsBase),
472	SSMFIELD_ENTRY( VMXVVMCS, u64HostGsBase),
473	SSMFIELD_ENTRY( VMXVVMCS, u64HostTrBase),
474	SSMFIELD_ENTRY( VMXVVMCS, u64HostGdtrBase),
475	SSMFIELD_ENTRY( VMXVVMCS, u64HostIdtrBase),
476	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEsp),
477	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEip),
478	SSMFIELD_ENTRY( VMXVVMCS, u64HostRsp),
479	SSMFIELD_ENTRY( VMXVVMCS, u64HostRip),
480	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
481	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
482	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
483	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved7),
484
485	SSMFIELD_ENTRY( VMXVVMCS, GuestEs),
486	SSMFIELD_ENTRY( VMXVVMCS, GuestCs),
487	SSMFIELD_ENTRY( VMXVVMCS, GuestSs),
488	SSMFIELD_ENTRY( VMXVVMCS, GuestDs),
489	SSMFIELD_ENTRY( VMXVVMCS, GuestFs),
490	SSMFIELD_ENTRY( VMXVVMCS, GuestGs),
491	SSMFIELD_ENTRY( VMXVVMCS, GuestLdtr),
492	SSMFIELD_ENTRY( VMXVVMCS, GuestTr),
493	SSMFIELD_ENTRY( VMXVVMCS, u16GuestIntStatus),
494	SSMFIELD_ENTRY( VMXVVMCS, u16PmlIndex),
495	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved1),
496
497	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsLimit),
498	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsLimit),
499	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsLimit),
500	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsLimit),
501	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsLimit),
502	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsLimit),
503	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrLimit),
504	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrLimit),
505	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGdtrLimit),
506	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIdtrLimit),
507	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsAttr),
508	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsAttr),
509	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsAttr),
510	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsAttr),
511	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsAttr),
512	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsAttr),
513	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrAttr),
514	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrAttr),
515	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIntrState),
516	SSMFIELD_ENTRY( VMXVVMCS, u32GuestActivityState),
517	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSmBase),
518	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSysenterCS),
519	SSMFIELD_ENTRY( VMXVVMCS, u32PreemptTimer),
520	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved3),
521
522	SSMFIELD_ENTRY( VMXVVMCS, u64VmcsLinkPtr),
523	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDebugCtlMsr),
524	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPatMsr),
525	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEferMsr),
526	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPerfGlobalCtlMsr),
527	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte0),
528	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte1),
529	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte2),
530	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte3),
531	SSMFIELD_ENTRY( VMXVVMCS, u64GuestBndcfgsMsr),
532	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRtitCtlMsr),
533	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
534	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved2),
535
536	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr0),
537	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr3),
538	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr4),
539	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEsBase),
540	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCsBase),
541	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSsBase),
542	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDsBase),
543	SSMFIELD_ENTRY( VMXVVMCS, u64GuestFsBase),
544	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGsBase),
545	SSMFIELD_ENTRY( VMXVVMCS, u64GuestLdtrBase),
546	SSMFIELD_ENTRY( VMXVVMCS, u64GuestTrBase),
547	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGdtrBase),
548	SSMFIELD_ENTRY( VMXVVMCS, u64GuestIdtrBase),
549	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDr7),
550	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRsp),
551	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRip),
552	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRFlags),
553	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPendingDbgXcpts),
554	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEsp),
555	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEip),
556	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
557	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
558	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
559	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved6),
560
561	SSMFIELD_ENTRY_TERM()
562	};
563
564	/** Saved state field descriptors for CPUMCTX. */
565	static const SSMFIELD g_aCpumX87Fields[] =
566	{
567	SSMFIELD_ENTRY( X86FXSTATE, FCW),
568	SSMFIELD_ENTRY( X86FXSTATE, FSW),
569	SSMFIELD_ENTRY( X86FXSTATE, FTW),
570	SSMFIELD_ENTRY( X86FXSTATE, FOP),
571	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
572	SSMFIELD_ENTRY( X86FXSTATE, CS),
573	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
574	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
575	SSMFIELD_ENTRY( X86FXSTATE, DS),
576	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
577	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
578	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
579	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
580	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
581	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
582	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
583	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
584	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
585	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
586	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
587	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
588	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
589	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
590	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
591	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
592	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
593	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
594	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
595	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
596	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
597	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
598	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
599	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
600	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
601	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
602	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
603	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
604	SSMFIELD_ENTRY_TERM()
605	};
606
607	/** Saved state field descriptors for X86XSAVEHDR. */
608	static const SSMFIELD g_aCpumXSaveHdrFields[] =
609	{
610	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
611	SSMFIELD_ENTRY_TERM()
612	};
613
614	/** Saved state field descriptors for X86XSAVEYMMHI. */
615	static const SSMFIELD g_aCpumYmmHiFields[] =
616	{
617	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
618	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
619	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
620	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
621	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
622	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
623	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
624	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
625	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
626	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
627	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
628	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
629	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
630	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
631	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
632	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
633	SSMFIELD_ENTRY_TERM()
634	};
635
636	/** Saved state field descriptors for X86XSAVEBNDREGS. */
637	static const SSMFIELD g_aCpumBndRegsFields[] =
638	{
639	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
640	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
641	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
642	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
643	SSMFIELD_ENTRY_TERM()
644	};
645
646	/** Saved state field descriptors for X86XSAVEBNDCFG. */
647	static const SSMFIELD g_aCpumBndCfgFields[] =
648	{
649	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
650	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
651	SSMFIELD_ENTRY_TERM()
652	};
653
654	#if 0 /** @todo */
655	/** Saved state field descriptors for X86XSAVEOPMASK. */
656	static const SSMFIELD g_aCpumOpmaskFields[] =
657	{
658	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
659	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
660	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
661	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
662	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
663	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
664	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
665	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
666	SSMFIELD_ENTRY_TERM()
667	};
668	#endif
669
670	/** Saved state field descriptors for X86XSAVEZMMHI256. */
671	static const SSMFIELD g_aCpumZmmHi256Fields[] =
672	{
673	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
674	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
675	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
676	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
677	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
678	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
679	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
680	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
681	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
682	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
683	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
684	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
685	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
686	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
687	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
688	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
689	SSMFIELD_ENTRY_TERM()
690	};
691
692	/** Saved state field descriptors for X86XSAVEZMM16HI. */
693	static const SSMFIELD g_aCpumZmm16HiFields[] =
694	{
695	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
696	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
697	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
698	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
699	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
700	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
701	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
702	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
703	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
704	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
705	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
706	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
707	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
708	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
709	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
710	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
711	SSMFIELD_ENTRY_TERM()
712	};
713
714
715
716	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
717	* registeres changed. */
718	static const SSMFIELD g_aCpumX87FieldsMem[] =
719	{
720	SSMFIELD_ENTRY( X86FXSTATE, FCW),
721	SSMFIELD_ENTRY( X86FXSTATE, FSW),
722	SSMFIELD_ENTRY( X86FXSTATE, FTW),
723	SSMFIELD_ENTRY( X86FXSTATE, FOP),
724	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
725	SSMFIELD_ENTRY( X86FXSTATE, CS),
726	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
727	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
728	SSMFIELD_ENTRY( X86FXSTATE, DS),
729	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
730	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
731	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
732	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
733	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
734	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
735	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
736	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
737	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
738	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
739	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
740	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
741	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
742	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
743	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
744	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
745	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
746	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
747	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
748	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
749	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
750	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
751	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
752	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
753	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
754	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
755	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
756	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
757	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
758	};
759
760	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
761	* registeres changed. */
762	static const SSMFIELD g_aCpumCtxFieldsMem[] =
763	{
764	SSMFIELD_ENTRY( CPUMCTX, rdi),
765	SSMFIELD_ENTRY( CPUMCTX, rsi),
766	SSMFIELD_ENTRY( CPUMCTX, rbp),
767	SSMFIELD_ENTRY( CPUMCTX, rax),
768	SSMFIELD_ENTRY( CPUMCTX, rbx),
769	SSMFIELD_ENTRY( CPUMCTX, rdx),
770	SSMFIELD_ENTRY( CPUMCTX, rcx),
771	SSMFIELD_ENTRY( CPUMCTX, rsp),
772	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
773	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
774	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
775	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
776	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
777	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
778	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
779	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
780	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
781	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
782	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
783	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
784	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
785	SSMFIELD_ENTRY( CPUMCTX, rflags),
786	SSMFIELD_ENTRY( CPUMCTX, rip),
787	SSMFIELD_ENTRY( CPUMCTX, r8),
788	SSMFIELD_ENTRY( CPUMCTX, r9),
789	SSMFIELD_ENTRY( CPUMCTX, r10),
790	SSMFIELD_ENTRY( CPUMCTX, r11),
791	SSMFIELD_ENTRY( CPUMCTX, r12),
792	SSMFIELD_ENTRY( CPUMCTX, r13),
793	SSMFIELD_ENTRY( CPUMCTX, r14),
794	SSMFIELD_ENTRY( CPUMCTX, r15),
795	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
796	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
797	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
798	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
799	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
800	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
801	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
802	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
803	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
804	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
805	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
806	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
807	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
808	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
809	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
810	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
811	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
812	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
813	SSMFIELD_ENTRY( CPUMCTX, cr0),
814	SSMFIELD_ENTRY( CPUMCTX, cr2),
815	SSMFIELD_ENTRY( CPUMCTX, cr3),
816	SSMFIELD_ENTRY( CPUMCTX, cr4),
817	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
818	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
819	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
820	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
821	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
822	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
823	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
824	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
825	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
826	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
827	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
828	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
829	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
830	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
831	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
832	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
833	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
834	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
835	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
836	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
837	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
838	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
839	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
840	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
841	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
842	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
843	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
844	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
845	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
846	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
847	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
848	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
849	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
850	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
851	SSMFIELD_ENTRY_TERM()
852	};
853
854	/** Saved state field descriptors for CPUMCTX_VER1_6. */
855	static const SSMFIELD g_aCpumX87FieldsV16[] =
856	{
857	SSMFIELD_ENTRY( X86FXSTATE, FCW),
858	SSMFIELD_ENTRY( X86FXSTATE, FSW),
859	SSMFIELD_ENTRY( X86FXSTATE, FTW),
860	SSMFIELD_ENTRY( X86FXSTATE, FOP),
861	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
862	SSMFIELD_ENTRY( X86FXSTATE, CS),
863	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
864	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
865	SSMFIELD_ENTRY( X86FXSTATE, DS),
866	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
867	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
868	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
869	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
870	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
871	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
872	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
873	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
874	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
875	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
876	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
877	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
878	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
879	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
880	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
881	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
882	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
883	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
884	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
885	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
886	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
887	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
888	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
889	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
890	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
891	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
892	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
893	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
894	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
895	SSMFIELD_ENTRY_TERM()
896	};
897
898	/** Saved state field descriptors for CPUMCTX_VER1_6. */
899	static const SSMFIELD g_aCpumCtxFieldsV16[] =
900	{
901	SSMFIELD_ENTRY( CPUMCTX, rdi),
902	SSMFIELD_ENTRY( CPUMCTX, rsi),
903	SSMFIELD_ENTRY( CPUMCTX, rbp),
904	SSMFIELD_ENTRY( CPUMCTX, rax),
905	SSMFIELD_ENTRY( CPUMCTX, rbx),
906	SSMFIELD_ENTRY( CPUMCTX, rdx),
907	SSMFIELD_ENTRY( CPUMCTX, rcx),
908	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
909	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
910	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
911	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
912	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
913	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
914	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
915	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
916	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
917	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
918	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
919	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
920	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
921	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
922	SSMFIELD_ENTRY( CPUMCTX, rflags),
923	SSMFIELD_ENTRY( CPUMCTX, rip),
924	SSMFIELD_ENTRY( CPUMCTX, r8),
925	SSMFIELD_ENTRY( CPUMCTX, r9),
926	SSMFIELD_ENTRY( CPUMCTX, r10),
927	SSMFIELD_ENTRY( CPUMCTX, r11),
928	SSMFIELD_ENTRY( CPUMCTX, r12),
929	SSMFIELD_ENTRY( CPUMCTX, r13),
930	SSMFIELD_ENTRY( CPUMCTX, r14),
931	SSMFIELD_ENTRY( CPUMCTX, r15),
932	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
933	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
934	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
935	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
936	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
937	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
938	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
939	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
940	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
941	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
942	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
943	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
944	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
945	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
946	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
947	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
948	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
949	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
950	SSMFIELD_ENTRY( CPUMCTX, cr0),
951	SSMFIELD_ENTRY( CPUMCTX, cr2),
952	SSMFIELD_ENTRY( CPUMCTX, cr3),
953	SSMFIELD_ENTRY( CPUMCTX, cr4),
954	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
955	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
956	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
957	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
958	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
959	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
960	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
961	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
962	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
963	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
964	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
965	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
966	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
967	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
968	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
969	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
970	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
971	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
972	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
973	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
974	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
975	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
976	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
977	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
978	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
979	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
980	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
981	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
982	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
983	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
984	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
985	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
986	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
987	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
988	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
989	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
990	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
991	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
992	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
993	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
994	SSMFIELD_ENTRY_TERM()
995	};
996
997
998	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
999	/**
1000	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
1001	*
1002	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
1003	* (last instruction pointer, last data pointer, last opcode) except when the ES
1004	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
1005	* clear these registers there is potential, local FPU leakage from a process
1006	* using the FPU to another.
1007	*
1008	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
1009	*
1010	* @param pVM The cross context VM structure.
1011	*/
1012	static void cpumR3CheckLeakyFpu(PVM pVM)
1013	{
1014	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
1015	uint32_t const u32Family = u32CpuVersion >> 8;
1016	if ( u32Family >= 6 /* K7 and higher */
1017	&& (ASMIsAmdCpu() \|\| ASMIsHygonCpu()) )
1018	{
1019	uint32_t cExt = ASMCpuId_EAX(0x80000000);
1020	if (RTX86IsValidExtRange(cExt))
1021	{
1022	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
1023	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1024	{
1025	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1026	{
1027	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1028	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
1029	}
1030	Log(("CPUM: Host CPU has leaky fxsave/fxrstor behaviour\n"));
1031	}
1032	}
1033	}
1034	}
1035	#endif
1036
1037
1038	/**
1039	* Initialize the SVM hardware virtualization state.
1040	*
1041	* @param pVM The cross context VM structure.
1042	*/
1043	static void cpumR3InitSvmHwVirtState(PVM pVM)
1044	{
1045	LogRel(("CPUM: AMD-V nested-guest init\n"));
1046	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1047	{
1048	PVMCPU pVCpu = pVM->apCpusR3[i];
1049	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1050
1051	/* Initialize that SVM hardware virtualization is available. */
1052	pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
1053
1054	AssertCompile(sizeof(pCtx->hwvirt.svm.Vmcb) == SVM_VMCB_PAGES * X86_PAGE_SIZE);
1055	AssertCompile(sizeof(pCtx->hwvirt.svm.abMsrBitmap) == SVM_MSRPM_PAGES * X86_PAGE_SIZE);
1056	AssertCompile(sizeof(pCtx->hwvirt.svm.abIoBitmap) == SVM_IOPM_PAGES * X86_PAGE_SIZE);
1057
1058	/* Initialize non-zero values. */
1059	pCtx->hwvirt.svm.GCPhysVmcb = NIL_RTGCPHYS;
1060	}
1061	}
1062
1063
1064	/**
1065	* Resets per-VCPU SVM hardware virtualization state.
1066	*
1067	* @param pVCpu The cross context virtual CPU structure.
1068	*/
1069	DECLINLINE(void) cpumR3ResetSvmHwVirtState(PVMCPU pVCpu)
1070	{
1071	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1072	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1073
1074	RT_ZERO(pCtx->hwvirt.svm.Vmcb);
1075	RT_ZERO(pCtx->hwvirt.svm.HostState);
1076	RT_ZERO(pCtx->hwvirt.svm.abMsrBitmap);
1077	RT_ZERO(pCtx->hwvirt.svm.abIoBitmap);
1078
1079	pCtx->hwvirt.svm.uMsrHSavePa = 0;
1080	pCtx->hwvirt.svm.uPrevPauseTick = 0;
1081	pCtx->hwvirt.svm.GCPhysVmcb = NIL_RTGCPHYS;
1082	pCtx->hwvirt.svm.cPauseFilter = 0;
1083	pCtx->hwvirt.svm.cPauseFilterThreshold = 0;
1084	pCtx->hwvirt.svm.fInterceptEvents = false;
1085	}
1086
1087
1088	/**
1089	* Initializes the VMX hardware virtualization state.
1090	*
1091	* @param pVM The cross context VM structure.
1092	*/
1093	static void cpumR3InitVmxHwVirtState(PVM pVM)
1094	{
1095	LogRel(("CPUM: VT-x nested-guest init\n"));
1096	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1097	{
1098	PVMCPU pVCpu = pVM->apCpusR3[i];
1099	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1100
1101	/* Initialize that VMX hardware virtualization is available. */
1102	pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
1103
1104	AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_PAGES * X86_PAGE_SIZE);
1105	AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_SIZE);
1106	AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_PAGES * X86_PAGE_SIZE);
1107	AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_SIZE);
1108	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1109	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1110	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1111	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1112	AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1113	AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1114	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1115	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_SIZE);
1116	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1117	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1118	AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_PAGES * X86_PAGE_SIZE);
1119	AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_SIZE);
1120	AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == (VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES) * X86_PAGE_SIZE);
1121	AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
1122
1123	/* Initialize non-zero values. */
1124	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1125	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1126	pCtx->hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS;
1127	}
1128	}
1129
1130
1131	/**
1132	* Resets per-VCPU VMX hardware virtualization state.
1133	*
1134	* @param pVCpu The cross context virtual CPU structure.
1135	*/
1136	DECLINLINE(void) cpumR3ResetVmxHwVirtState(PVMCPU pVCpu)
1137	{
1138	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1139	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1140
1141	RT_ZERO(pCtx->hwvirt.vmx.Vmcs);
1142	RT_ZERO(pCtx->hwvirt.vmx.ShadowVmcs);
1143	RT_ZERO(pCtx->hwvirt.vmx.abVmreadBitmap);
1144	RT_ZERO(pCtx->hwvirt.vmx.abVmwriteBitmap);
1145	RT_ZERO(pCtx->hwvirt.vmx.aEntryMsrLoadArea);
1146	RT_ZERO(pCtx->hwvirt.vmx.aExitMsrStoreArea);
1147	RT_ZERO(pCtx->hwvirt.vmx.aExitMsrLoadArea);
1148	RT_ZERO(pCtx->hwvirt.vmx.abMsrBitmap);
1149	RT_ZERO(pCtx->hwvirt.vmx.abIoBitmap);
1150
1151	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1152	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1153	pCtx->hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS;
1154	pCtx->hwvirt.vmx.fInVmxRootMode = false;
1155	pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1156	/* Don't reset diagnostics here. */
1157
1158	pCtx->hwvirt.vmx.fInterceptEvents = false;
1159	pCtx->hwvirt.vmx.fNmiUnblockingIret = false;
1160	pCtx->hwvirt.vmx.uFirstPauseLoopTick = 0;
1161	pCtx->hwvirt.vmx.uPrevPauseTick = 0;
1162	pCtx->hwvirt.vmx.uEntryTick = 0;
1163	pCtx->hwvirt.vmx.offVirtApicWrite = 0;
1164	pCtx->hwvirt.vmx.fVirtNmiBlocking = false;
1165
1166	/* Stop any VMX-preemption timer. */
1167	CPUMStopGuestVmxPremptTimer(pVCpu);
1168
1169	/* Clear all nested-guest FFs. */
1170	VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
1171	}
1172
1173
1174	/**
1175	* Displays the host and guest VMX features.
1176	*
1177	* @param pVM The cross context VM structure.
1178	* @param pHlp The info helper functions.
1179	* @param pszArgs "terse", "default" or "verbose".
1180	*/
1181	DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1182	{
1183	RT_NOREF(pszArgs);
1184	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
1185	PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
1186	if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
1187	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA
1188	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_SHANGHAI)
1189	{
1190	#define VMXFEATDUMP(a_szDesc, a_Var) \
1191	pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
1192
1193	pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
1194	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1195	VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
1196	/* Basic. */
1197	VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
1198
1199	/* Pin-based controls. */
1200	VMXFEATDUMP("ExtIntExit - External interrupt exiting ", fVmxExtIntExit);
1201	VMXFEATDUMP("NmiExit - NMI exiting ", fVmxNmiExit);
1202	VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
1203	VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
1204	VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
1205
1206	/* Processor-based controls. */
1207	VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
1208	VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
1209	VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
1210	VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
1211	VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
1212	VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
1213	VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
1214	VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1215	VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1216	VMXFEATDUMP("TertiaryExecCtls - Activate tertiary controls ", fVmxTertiaryExecCtls);
1217	VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1218	VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1219	VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1220	VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1221	VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1222	VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1223	VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1224	VMXFEATDUMP("MonitorTrapFlag - Monitor Trap Flag ", fVmxMonitorTrapFlag);
1225	VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1226	VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1227	VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1228	VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1229
1230	/* Secondary processor-based controls. */
1231	VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1232	VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1233	VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1234	VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1235	VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
1236	VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1237	VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1238	VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1239	VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1240	VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1241	VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1242	VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1243	VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1244	VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1245	VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1246	VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1247	VMXFEATDUMP("PML - Page-Modification Log (PML) ", fVmxPml);
1248	VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1249	VMXFEATDUMP("ConcealVmxFromPt - Conceal VMX from Processor Trace ", fVmxConcealVmxFromPt);
1250	VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1251	VMXFEATDUMP("ModeBasedExecuteEpt - Mode-based execute permissions ", fVmxModeBasedExecuteEpt);
1252	VMXFEATDUMP("SppEpt - Sub-page page write permissions for EPT ", fVmxSppEpt);
1253	VMXFEATDUMP("PtEpt - Processor Trace address' translatable by EPT ", fVmxPtEpt);
1254	VMXFEATDUMP("UseTscScaling - Use TSC scaling ", fVmxUseTscScaling);
1255	VMXFEATDUMP("UserWaitPause - Enable TPAUSE, UMONITOR and UMWAIT ", fVmxUserWaitPause);
1256	VMXFEATDUMP("EnclvExit - ENCLV exiting ", fVmxEnclvExit);
1257
1258	/* Tertiary processor-based controls. */
1259	VMXFEATDUMP("LoadIwKeyExit - LOADIWKEY exiting ", fVmxLoadIwKeyExit);
1260
1261	/* VM-entry controls. */
1262	VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1263	VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1264	VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER MSR on VM-entry ", fVmxEntryLoadEferMsr);
1265	VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT MSR on VM-entry ", fVmxEntryLoadPatMsr);
1266
1267	/* VM-exit controls. */
1268	VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1269	VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1270	VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1271	VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT MSR on VM-exit ", fVmxExitSavePatMsr);
1272	VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT MSR on VM-exit ", fVmxExitLoadPatMsr);
1273	VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER MSR on VM-exit ", fVmxExitSaveEferMsr);
1274	VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER MSR on VM-exit ", fVmxExitLoadEferMsr);
1275	VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1276
1277	/* Miscellaneous data. */
1278	VMXFEATDUMP("ExitSaveEferLma - Save IA32_EFER.LMA on VM-exit ", fVmxExitSaveEferLma);
1279	VMXFEATDUMP("IntelPt - Intel PT (Processor Trace) in VMX operation ", fVmxPt);
1280	VMXFEATDUMP("VmwriteAll - VMWRITE to any supported VMCS field ", fVmxVmwriteAll);
1281	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1282	#undef VMXFEATDUMP
1283	}
1284	else
1285	pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1286	}
1287
1288
1289	/**
1290	* Checks whether nested-guest execution using hardware-assisted VMX (e.g, using HM
1291	* or NEM) is allowed.
1292	*
1293	* @returns @c true if hardware-assisted nested-guest execution is allowed, @c false
1294	* otherwise.
1295	* @param pVM The cross context VM structure.
1296	*/
1297	static bool cpumR3IsHwAssistNstGstExecAllowed(PVM pVM)
1298	{
1299	AssertMsg(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET, ("Calling this function too early!\n"));
1300	#ifndef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
1301	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT
1302	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1303	return true;
1304	#else
1305	NOREF(pVM);
1306	#endif
1307	return false;
1308	}
1309
1310
1311	/**
1312	* Initializes the VMX guest MSRs from guest CPU features based on the host MSRs.
1313	*
1314	* @param pVM The cross context VM structure.
1315	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1316	* and no hardware-assisted nested-guest execution is
1317	* possible for this VM.
1318	* @param pGuestFeatures The guest features to use (only VMX features are
1319	* accessed).
1320	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1321	*
1322	* @remarks This function ASSUMES the VMX guest-features are already exploded!
1323	*/
1324	static void cpumR3InitVmxGuestMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PCCPUMFEATURES pGuestFeatures, PVMXMSRS pGuestVmxMsrs)
1325	{
1326	bool const fIsNstGstHwExecAllowed = cpumR3IsHwAssistNstGstExecAllowed(pVM);
1327
1328	Assert(!fIsNstGstHwExecAllowed \|\| pHostVmxMsrs);
1329	Assert(pGuestFeatures->fVmx);
1330
1331	/* Basic information. */
1332	uint8_t const fTrueVmxMsrs = 1;
1333	{
1334	uint64_t const u64Basic = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1335	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1336	\| RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, !pGuestFeatures->fLongMode )
1337	\| RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1338	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1339	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1340	\| RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, fTrueVmxMsrs );
1341	pGuestVmxMsrs->u64Basic = u64Basic;
1342	}
1343
1344	/* Pin-based VM-execution controls. */
1345	{
1346	uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1347	\| (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1348	\| (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1349	\| (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1350	\| (pGuestFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1351	uint32_t const fAllowed0 = VMX_PIN_CTLS_DEFAULT1;
1352	uint32_t const fAllowed1 = fFeatures \| VMX_PIN_CTLS_DEFAULT1;
1353	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n",
1354	fAllowed0, fAllowed1, fFeatures));
1355	pGuestVmxMsrs->PinCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1356
1357	/* True pin-based VM-execution controls. */
1358	if (fTrueVmxMsrs)
1359	{
1360	/* VMX_PIN_CTLS_DEFAULT1 contains MB1 reserved bits and must be reserved MB1 in true pin-based controls as well. */
1361	pGuestVmxMsrs->TruePinCtls.u = pGuestVmxMsrs->PinCtls.u;
1362	}
1363	}
1364
1365	/* Processor-based VM-execution controls. */
1366	{
1367	uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1368	\| (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1369	\| (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1370	\| (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1371	\| (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1372	\| (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1373	\| (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1374	\| (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1375	\| (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1376	\| (pGuestFeatures->fVmxTertiaryExecCtls << VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_SHIFT )
1377	\| (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1378	\| (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1379	\| (pGuestFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1380	\| (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1381	\| (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1382	\| (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1383	\| (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1384	\| (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1385	\| (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1386	\| (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1387	\| (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1388	\| (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1389	uint32_t const fAllowed0 = VMX_PROC_CTLS_DEFAULT1;
1390	uint32_t const fAllowed1 = fFeatures \| VMX_PROC_CTLS_DEFAULT1;
1391	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1392	fAllowed1, fFeatures));
1393	pGuestVmxMsrs->ProcCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1394
1395	/* True processor-based VM-execution controls. */
1396	if (fTrueVmxMsrs)
1397	{
1398	/* VMX_PROC_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved. */
1399	uint32_t const fTrueAllowed0 = VMX_PROC_CTLS_DEFAULT1 & ~( VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK
1400	\| VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK);
1401	uint32_t const fTrueAllowed1 = fFeatures \| fTrueAllowed0;
1402	pGuestVmxMsrs->TrueProcCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1403	}
1404	}
1405
1406	/* Secondary processor-based VM-execution controls. */
1407	if (pGuestFeatures->fVmxSecondaryExecCtls)
1408	{
1409	uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1410	\| (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1411	\| (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1412	\| (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1413	\| (pGuestFeatures->fVmxVirtX2ApicMode << VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT )
1414	\| (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1415	\| (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1416	\| (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT )
1417	\| (pGuestFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1418	\| (pGuestFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1419	\| (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1420	\| (pGuestFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1421	\| (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1422	\| (pGuestFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1423	\| (pGuestFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1424	\| (pGuestFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1425	\| (pGuestFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1426	\| (pGuestFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1427	\| (pGuestFeatures->fVmxConcealVmxFromPt << VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT)
1428	\| (pGuestFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1429	\| (pGuestFeatures->fVmxModeBasedExecuteEpt << VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT)
1430	\| (pGuestFeatures->fVmxSppEpt << VMX_BF_PROC_CTLS2_SPP_EPT_SHIFT )
1431	\| (pGuestFeatures->fVmxPtEpt << VMX_BF_PROC_CTLS2_PT_EPT_SHIFT )
1432	\| (pGuestFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT )
1433	\| (pGuestFeatures->fVmxUserWaitPause << VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT )
1434	\| (pGuestFeatures->fVmxEnclvExit << VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT );
1435	uint32_t const fAllowed0 = 0;
1436	uint32_t const fAllowed1 = fFeatures;
1437	pGuestVmxMsrs->ProcCtls2.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1438	}
1439
1440	/* Tertiary processor-based VM-execution controls. */
1441	if (pGuestFeatures->fVmxTertiaryExecCtls)
1442	{
1443	pGuestVmxMsrs->u64ProcCtls3 = (pGuestFeatures->fVmxLoadIwKeyExit << VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_SHIFT);
1444	}
1445
1446	/* VM-exit controls. */
1447	{
1448	uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1449	\| (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1450	\| (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1451	\| (pGuestFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1452	\| (pGuestFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1453	\| (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1454	\| (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1455	\| (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT );
1456	/* Set the default1 class bits. See Intel spec. A.4 "VM-exit Controls". */
1457	uint32_t const fAllowed0 = VMX_EXIT_CTLS_DEFAULT1;
1458	uint32_t const fAllowed1 = fFeatures \| VMX_EXIT_CTLS_DEFAULT1;
1459	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1460	fAllowed1, fFeatures));
1461	pGuestVmxMsrs->ExitCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1462
1463	/* True VM-exit controls. */
1464	if (fTrueVmxMsrs)
1465	{
1466	/* VMX_EXIT_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved */
1467	uint32_t const fTrueAllowed0 = VMX_EXIT_CTLS_DEFAULT1 & ~VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK;
1468	uint32_t const fTrueAllowed1 = fFeatures \| fTrueAllowed0;
1469	pGuestVmxMsrs->TrueExitCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1470	}
1471	}
1472
1473	/* VM-entry controls. */
1474	{
1475	uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1476	\| (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1477	\| (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1478	\| (pGuestFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1479	uint32_t const fAllowed0 = VMX_ENTRY_CTLS_DEFAULT1;
1480	uint32_t const fAllowed1 = fFeatures \| VMX_ENTRY_CTLS_DEFAULT1;
1481	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed0=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1482	fAllowed1, fFeatures));
1483	pGuestVmxMsrs->EntryCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1484
1485	/* True VM-entry controls. */
1486	if (fTrueVmxMsrs)
1487	{
1488	/* VMX_ENTRY_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved */
1489	uint32_t const fTrueAllowed0 = VMX_ENTRY_CTLS_DEFAULT1 & ~( VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK
1490	\| VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK
1491	\| VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK
1492	\| VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK);
1493	uint32_t const fTrueAllowed1 = fFeatures \| fTrueAllowed0;
1494	pGuestVmxMsrs->TrueEntryCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1495	}
1496	}
1497
1498	/* Miscellaneous data. */
1499	{
1500	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Misc : 0;
1501
1502	uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_AUTOMSR_COUNT_MAX);
1503	uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK;
1504	pGuestVmxMsrs->u64Misc = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1505	\| RT_BF_MAKE(VMX_BF_MISC_EXIT_SAVE_EFER_LMA, pGuestFeatures->fVmxExitSaveEferLma )
1506	\| RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState )
1507	\| RT_BF_MAKE(VMX_BF_MISC_INTEL_PT, pGuestFeatures->fVmxPt )
1508	\| RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1509	\| RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1510	\| RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1511	\| RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1512	\| RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pGuestFeatures->fVmxVmwriteAll )
1513	\| RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pGuestFeatures->fVmxEntryInjectSoftInt)
1514	\| RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1515	}
1516
1517	/* CR0 Fixed-0 (we report this fixed value regardless of whether UX is supported as it does on real hardware). */
1518	pGuestVmxMsrs->u64Cr0Fixed0 = VMX_V_CR0_FIXED0;
1519
1520	/* CR0 Fixed-1. */
1521	{
1522	/*
1523	* All CPUs I've looked at so far report CR0 fixed-1 bits as 0xffffffff.
1524	* This is different from CR4 fixed-1 bits which are reported as per the
1525	* CPU features and/or micro-architecture/generation. Why? Ask Intel.
1526	*/
1527	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr0Fixed1 : VMX_V_CR0_FIXED1;
1528	pGuestVmxMsrs->u64Cr0Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr0Fixed0; /* Make sure the CR0 MB1 bits are not clear. */
1529	}
1530
1531	/* CR4 Fixed-0. */
1532	pGuestVmxMsrs->u64Cr4Fixed0 = VMX_V_CR4_FIXED0;
1533
1534	/* CR4 Fixed-1. */
1535	{
1536	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr4Fixed1 : CPUMGetGuestCR4ValidMask(pVM);
1537	pGuestVmxMsrs->u64Cr4Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr4Fixed0; /* Make sure the CR4 MB1 bits are not clear. */
1538	}
1539
1540	/* VMCS Enumeration. */
1541	pGuestVmxMsrs->u64VmcsEnum = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1542
1543	/* VPID and EPT Capabilities. */
1544	if (pGuestFeatures->fVmxEpt)
1545	{
1546	/*
1547	* INVVPID instruction always causes a VM-exit unconditionally, so we are free to fake
1548	* and emulate any INVVPID flush type. However, it only makes sense to expose the types
1549	* when INVVPID instruction is supported just to be more compatible with guest
1550	* hypervisors that may make assumptions by only looking at this MSR even though they
1551	* are technically supposed to refer to VMX_PROC_CTLS2_VPID first.
1552	*
1553	* See Intel spec. 25.1.2 "Instructions That Cause VM Exits Unconditionally".
1554	* See Intel spec. 30.3 "VMX Instructions".
1555	*/
1556	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64EptVpidCaps : UINT64_MAX;
1557	uint8_t const fVpid = pGuestFeatures->fVmxVpid;
1558
1559	uint8_t const fExecOnly = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EXEC_ONLY);
1560	uint8_t const fPml4 = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1561	uint8_t const fMemTypeUc = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC);
1562	uint8_t const fMemTypeWb = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB);
1563	uint8_t const f2MPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDE_2M);
1564	uint8_t const fInvept = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT);
1565	/** @todo Nested VMX: Support accessed/dirty bits, see @bugref{10092#c25}. */
1566	/* uint8_t const fAccessDirty = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY); */
1567	uint8_t const fEptSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
1568	uint8_t const fEptAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
1569	uint8_t const fVpidIndiv = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1570	uint8_t const fVpidSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
1571	uint8_t const fVpidAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
1572	uint8_t const fVpidSingleGlobal = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
1573	pGuestVmxMsrs->u64EptVpidCaps = RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_EXEC_ONLY, fExecOnly)
1574	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4, fPml4)
1575	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_UC, fMemTypeUc)
1576	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_WB, fMemTypeWb)
1577	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDE_2M, f2MPage)
1578	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDPTE_1G, 0)
1579	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT, fInvept)
1580	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY, 0)
1581	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION, 0)
1582	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK, 0)
1583	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX, fEptSingle)
1584	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX, fEptAll)
1585	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID, fVpid)
1586	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR, fVpid & fVpidIndiv)
1587	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX, fVpid & fVpidSingle)
1588	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX, fVpid & fVpidAll)
1589	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS, fVpid & fVpidSingleGlobal);
1590	}
1591
1592	/* VM Functions. */
1593	if (pGuestFeatures->fVmxVmFunc)
1594	pGuestVmxMsrs->u64VmFunc = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1595	}
1596
1597
1598	/**
1599	* Checks whether the given guest CPU VMX features are compatible with the provided
1600	* base features.
1601	*
1602	* @returns @c true if compatible, @c false otherwise.
1603	* @param pVM The cross context VM structure.
1604	* @param pBase The base VMX CPU features.
1605	* @param pGst The guest VMX CPU features.
1606	*
1607	* @remarks Only VMX feature bits are examined.
1608	*/
1609	static bool cpumR3AreVmxCpuFeaturesCompatible(PVM pVM, PCCPUMFEATURES pBase, PCCPUMFEATURES pGst)
1610	{
1611	if (!cpumR3IsHwAssistNstGstExecAllowed(pVM))
1612	return false;
1613
1614	#define CPUM_VMX_FEAT_SHIFT(a_pFeat, a_FeatName, a_cShift) ((uint64_t)(a_pFeat->a_FeatName) << (a_cShift))
1615	#define CPUM_VMX_MAKE_FEATURES_1(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInsOutInfo , 0) \
1616	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExtIntExit , 1) \
1617	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiExit , 2) \
1618	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtNmi , 3) \
1619	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPreemptTimer , 4) \
1620	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPostedInt , 5) \
1621	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIntWindowExit , 6) \
1622	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTscOffsetting , 7) \
1623	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHltExit , 8) \
1624	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvlpgExit , 9) \
1625	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMwaitExit , 10) \
1626	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdpmcExit , 12) \
1627	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscExit , 13) \
1628	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3LoadExit , 14) \
1629	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3StoreExit , 15) \
1630	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTertiaryExecCtls , 16) \
1631	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8LoadExit , 17) \
1632	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8StoreExit , 18) \
1633	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTprShadow , 19) \
1634	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiWindowExit , 20) \
1635	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMovDRxExit , 21) \
1636	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUncondIoExit , 22) \
1637	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseIoBitmaps , 23) \
1638	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorTrapFlag , 24) \
1639	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseMsrBitmaps , 25) \
1640	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorExit , 26) \
1641	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseExit , 27) \
1642	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSecondaryExecCtls , 28) \
1643	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtApicAccess , 29) \
1644	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEpt , 30) \
1645	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxDescTableExit , 31) \
1646	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscp , 32) \
1647	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtX2ApicMode , 33) \
1648	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVpid , 34) \
1649	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxWbinvdExit , 35) \
1650	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUnrestrictedGuest , 36) \
1651	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxApicRegVirt , 37) \
1652	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtIntDelivery , 38) \
1653	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseLoopExit , 39) \
1654	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdrandExit , 40) \
1655	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvpcid , 41) \
1656	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmFunc , 42) \
1657	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmcsShadowing , 43) \
1658	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdseedExit , 44) \
1659	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPml , 45) \
1660	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEptXcptVe , 46) \
1661	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxConcealVmxFromPt , 47) \
1662	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxXsavesXrstors , 48) \
1663	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxModeBasedExecuteEpt, 49) \
1664	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSppEpt , 50) \
1665	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPtEpt , 51) \
1666	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTscScaling , 52) \
1667	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUserWaitPause , 53) \
1668	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEnclvExit , 54) \
1669	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxLoadIwKeyExit , 55) \
1670	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadDebugCtls , 56) \
1671	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIa32eModeGuest , 57) \
1672	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadEferMsr , 58) \
1673	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadPatMsr , 59) \
1674	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveDebugCtls , 60) \
1675	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHostAddrSpaceSize , 61) \
1676	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitAckExtInt , 62) \
1677	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSavePatMsr , 63))
1678
1679	#define CPUM_VMX_MAKE_FEATURES_2(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadPatMsr , 0) \
1680	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferMsr , 1) \
1681	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadEferMsr , 2) \
1682	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSavePreemptTimer , 3) \
1683	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferLma , 4) \
1684	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPt , 5) \
1685	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmwriteAll , 6) \
1686	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryInjectSoftInt , 7))
1687
1688	/* Check first set of feature bits. */
1689	{
1690	uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_1(pBase);
1691	uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_1(pGst);
1692	if ((fBase \| fGst) != fBase)
1693	{
1694	uint64_t const fDiff = fBase ^ fGst;
1695	LogRel(("CPUM: VMX features (1) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1696	fBase, fGst, fDiff));
1697	return false;
1698	}
1699	}
1700
1701	/* Check second set of feature bits. */
1702	{
1703	uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_2(pBase);
1704	uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_2(pGst);
1705	if ((fBase \| fGst) != fBase)
1706	{
1707	uint64_t const fDiff = fBase ^ fGst;
1708	LogRel(("CPUM: VMX features (2) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1709	fBase, fGst, fDiff));
1710	return false;
1711	}
1712	}
1713	#undef CPUM_VMX_FEAT_SHIFT
1714	#undef CPUM_VMX_MAKE_FEATURES_1
1715	#undef CPUM_VMX_MAKE_FEATURES_2
1716
1717	return true;
1718	}
1719
1720
1721	/**
1722	* Initializes VMX guest features and MSRs.
1723	*
1724	* @param pVM The cross context VM structure.
1725	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1726	* and no hardware-assisted nested-guest execution is
1727	* possible for this VM.
1728	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1729	*/
1730	void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs)
1731	{
1732	Assert(pVM);
1733	Assert(pGuestVmxMsrs);
1734
1735	/*
1736	* While it would be nice to check this earlier while initializing
1737	* fNestedVmxEpt but we would not have enumearted host features then, so do
1738	* it at least now.
1739	*/
1740	/** @todo r=bird: Why don't we just ditch the fNestedVmxEpt and
1741	* fNestedVmxUnrestrictedGuest state members and read the CFGM stuff
1742	* here? Neither of them have any purpose beyond keeping the two value
1743	* read in cpumR3CpuIdReadConfig for use here. They aren't even
1744	* necessarily correct after the feature merging has taken place. */
1745	if (pVM->cpum.s.fNestedVmxEpt)
1746	{
1747	const char *pszWhy = NULL;
1748	if (!VM_IS_HM_ENABLED(pVM) && !VM_IS_EXEC_ENGINE_IEM(pVM))
1749	pszWhy = "execution engine is neither HM nor IEM";
1750	else if (VM_IS_HM_ENABLED(pVM) && !HMIsNestedPagingActive(pVM))
1751	pszWhy = "nested paging is not enabled for the VM or it is not supported by the host";
1752	else if (VM_IS_HM_ENABLED(pVM) && !pVM->cpum.s.HostFeatures.fNoExecute)
1753	pszWhy = "NX is not available on the host";
1754	if (pszWhy)
1755	{
1756	LogRel(("CPUM: Warning! EPT not exposed to the guest because %s.\n", pszWhy));
1757	pVM->cpum.s.fNestedVmxEpt = false;
1758	}
1759	}
1760	if ( pVM->cpum.s.fNestedVmxUnrestrictedGuest
1761	&& !pVM->cpum.s.fNestedVmxEpt)
1762	{
1763	LogRel(("CPUM: Warning! Can't expose \"Unrestricted Guest\" to the guest when EPT is not exposed!\n"));
1764	pVM->cpum.s.fNestedVmxUnrestrictedGuest = false;
1765	}
1766
1767	/*
1768	* Initialize the set of VMX features we emulate.
1769	*
1770	* Note! Some bits might be reported as 1 always if they fall under the
1771	* default1 class bits (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1772	*/
1773	CPUMFEATURES EmuFeat;
1774	RT_ZERO(EmuFeat);
1775	EmuFeat.fVmx = 1;
1776	EmuFeat.fVmxInsOutInfo = 1;
1777	EmuFeat.fVmxExtIntExit = 1;
1778	EmuFeat.fVmxNmiExit = 1;
1779	EmuFeat.fVmxVirtNmi = 1;
1780	EmuFeat.fVmxPreemptTimer = pVM->cpum.s.fNestedVmxPreemptTimer;
1781	EmuFeat.fVmxPostedInt = 0;
1782	EmuFeat.fVmxIntWindowExit = 1;
1783	EmuFeat.fVmxTscOffsetting = 1;
1784	EmuFeat.fVmxHltExit = 1;
1785	EmuFeat.fVmxInvlpgExit = 1;
1786	EmuFeat.fVmxMwaitExit = 1;
1787	EmuFeat.fVmxRdpmcExit = 1;
1788	EmuFeat.fVmxRdtscExit = 1;
1789	EmuFeat.fVmxCr3LoadExit = 1;
1790	EmuFeat.fVmxCr3StoreExit = 1;
1791	EmuFeat.fVmxTertiaryExecCtls = 0;
1792	EmuFeat.fVmxCr8LoadExit = 1;
1793	EmuFeat.fVmxCr8StoreExit = 1;
1794	EmuFeat.fVmxUseTprShadow = 1;
1795	EmuFeat.fVmxNmiWindowExit = 0;
1796	EmuFeat.fVmxMovDRxExit = 1;
1797	EmuFeat.fVmxUncondIoExit = 1;
1798	EmuFeat.fVmxUseIoBitmaps = 1;
1799	EmuFeat.fVmxMonitorTrapFlag = 0;
1800	EmuFeat.fVmxUseMsrBitmaps = 1;
1801	EmuFeat.fVmxMonitorExit = 1;
1802	EmuFeat.fVmxPauseExit = 1;
1803	EmuFeat.fVmxSecondaryExecCtls = 1;
1804	EmuFeat.fVmxVirtApicAccess = 1;
1805	EmuFeat.fVmxEpt = pVM->cpum.s.fNestedVmxEpt;
1806	EmuFeat.fVmxDescTableExit = 1;
1807	EmuFeat.fVmxRdtscp = 1;
1808	EmuFeat.fVmxVirtX2ApicMode = 0;
1809	EmuFeat.fVmxVpid = 0; /** @todo Consider enabling this when EPT works. */
1810	EmuFeat.fVmxWbinvdExit = 1;
1811	EmuFeat.fVmxUnrestrictedGuest = pVM->cpum.s.fNestedVmxUnrestrictedGuest;
1812	EmuFeat.fVmxApicRegVirt = 0;
1813	EmuFeat.fVmxVirtIntDelivery = 0;
1814	EmuFeat.fVmxPauseLoopExit = 0;
1815	EmuFeat.fVmxRdrandExit = 0;
1816	EmuFeat.fVmxInvpcid = 1;
1817	EmuFeat.fVmxVmFunc = 0;
1818	EmuFeat.fVmxVmcsShadowing = 0;
1819	EmuFeat.fVmxRdseedExit = 0;
1820	EmuFeat.fVmxPml = 0;
1821	EmuFeat.fVmxEptXcptVe = 0;
1822	EmuFeat.fVmxConcealVmxFromPt = 0;
1823	EmuFeat.fVmxXsavesXrstors = 0;
1824	EmuFeat.fVmxModeBasedExecuteEpt = 0;
1825	EmuFeat.fVmxSppEpt = 0;
1826	EmuFeat.fVmxPtEpt = 0;
1827	EmuFeat.fVmxUseTscScaling = 0;
1828	EmuFeat.fVmxUserWaitPause = 0;
1829	EmuFeat.fVmxEnclvExit = 0;
1830	EmuFeat.fVmxLoadIwKeyExit = 0;
1831	EmuFeat.fVmxEntryLoadDebugCtls = 1;
1832	EmuFeat.fVmxIa32eModeGuest = 1;
1833	EmuFeat.fVmxEntryLoadEferMsr = 1;
1834	EmuFeat.fVmxEntryLoadPatMsr = 0;
1835	EmuFeat.fVmxExitSaveDebugCtls = 1;
1836	EmuFeat.fVmxHostAddrSpaceSize = 1;
1837	EmuFeat.fVmxExitAckExtInt = 1;
1838	EmuFeat.fVmxExitSavePatMsr = 0;
1839	EmuFeat.fVmxExitLoadPatMsr = 0;
1840	EmuFeat.fVmxExitSaveEferMsr = 1;
1841	EmuFeat.fVmxExitLoadEferMsr = 1;
1842	EmuFeat.fVmxSavePreemptTimer = 0; /* Cannot be enabled if VMX-preemption timer is disabled. */
1843	EmuFeat.fVmxExitSaveEferLma = 1; /* Cannot be disabled if unrestricted guest is enabled. */
1844	EmuFeat.fVmxPt = 0;
1845	EmuFeat.fVmxVmwriteAll = 0; /** @todo NSTVMX: enable this when nested VMCS shadowing is enabled. */
1846	EmuFeat.fVmxEntryInjectSoftInt = 1;
1847
1848	/*
1849	* Merge guest features.
1850	*
1851	* When hardware-assisted VMX may be used, any feature we emulate must also be supported
1852	* by the hardware, hence we merge our emulated features with the host features below.
1853	*/
1854	PCCPUMFEATURES pBaseFeat = cpumR3IsHwAssistNstGstExecAllowed(pVM) ? &pVM->cpum.s.HostFeatures : &EmuFeat;
1855	PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1856	Assert(pBaseFeat->fVmx);
1857	pGuestFeat->fVmxInsOutInfo = (pBaseFeat->fVmxInsOutInfo & EmuFeat.fVmxInsOutInfo );
1858	pGuestFeat->fVmxExtIntExit = (pBaseFeat->fVmxExtIntExit & EmuFeat.fVmxExtIntExit );
1859	pGuestFeat->fVmxNmiExit = (pBaseFeat->fVmxNmiExit & EmuFeat.fVmxNmiExit );
1860	pGuestFeat->fVmxVirtNmi = (pBaseFeat->fVmxVirtNmi & EmuFeat.fVmxVirtNmi );
1861	pGuestFeat->fVmxPreemptTimer = (pBaseFeat->fVmxPreemptTimer & EmuFeat.fVmxPreemptTimer );
1862	pGuestFeat->fVmxPostedInt = (pBaseFeat->fVmxPostedInt & EmuFeat.fVmxPostedInt );
1863	pGuestFeat->fVmxIntWindowExit = (pBaseFeat->fVmxIntWindowExit & EmuFeat.fVmxIntWindowExit );
1864	pGuestFeat->fVmxTscOffsetting = (pBaseFeat->fVmxTscOffsetting & EmuFeat.fVmxTscOffsetting );
1865	pGuestFeat->fVmxHltExit = (pBaseFeat->fVmxHltExit & EmuFeat.fVmxHltExit );
1866	pGuestFeat->fVmxInvlpgExit = (pBaseFeat->fVmxInvlpgExit & EmuFeat.fVmxInvlpgExit );
1867	pGuestFeat->fVmxMwaitExit = (pBaseFeat->fVmxMwaitExit & EmuFeat.fVmxMwaitExit );
1868	pGuestFeat->fVmxRdpmcExit = (pBaseFeat->fVmxRdpmcExit & EmuFeat.fVmxRdpmcExit );
1869	pGuestFeat->fVmxRdtscExit = (pBaseFeat->fVmxRdtscExit & EmuFeat.fVmxRdtscExit );
1870	pGuestFeat->fVmxCr3LoadExit = (pBaseFeat->fVmxCr3LoadExit & EmuFeat.fVmxCr3LoadExit );
1871	pGuestFeat->fVmxCr3StoreExit = (pBaseFeat->fVmxCr3StoreExit & EmuFeat.fVmxCr3StoreExit );
1872	pGuestFeat->fVmxTertiaryExecCtls = (pBaseFeat->fVmxTertiaryExecCtls & EmuFeat.fVmxTertiaryExecCtls );
1873	pGuestFeat->fVmxCr8LoadExit = (pBaseFeat->fVmxCr8LoadExit & EmuFeat.fVmxCr8LoadExit );
1874	pGuestFeat->fVmxCr8StoreExit = (pBaseFeat->fVmxCr8StoreExit & EmuFeat.fVmxCr8StoreExit );
1875	pGuestFeat->fVmxUseTprShadow = (pBaseFeat->fVmxUseTprShadow & EmuFeat.fVmxUseTprShadow );
1876	pGuestFeat->fVmxNmiWindowExit = (pBaseFeat->fVmxNmiWindowExit & EmuFeat.fVmxNmiWindowExit );
1877	pGuestFeat->fVmxMovDRxExit = (pBaseFeat->fVmxMovDRxExit & EmuFeat.fVmxMovDRxExit );
1878	pGuestFeat->fVmxUncondIoExit = (pBaseFeat->fVmxUncondIoExit & EmuFeat.fVmxUncondIoExit );
1879	pGuestFeat->fVmxUseIoBitmaps = (pBaseFeat->fVmxUseIoBitmaps & EmuFeat.fVmxUseIoBitmaps );
1880	pGuestFeat->fVmxMonitorTrapFlag = (pBaseFeat->fVmxMonitorTrapFlag & EmuFeat.fVmxMonitorTrapFlag );
1881	pGuestFeat->fVmxUseMsrBitmaps = (pBaseFeat->fVmxUseMsrBitmaps & EmuFeat.fVmxUseMsrBitmaps );
1882	pGuestFeat->fVmxMonitorExit = (pBaseFeat->fVmxMonitorExit & EmuFeat.fVmxMonitorExit );
1883	pGuestFeat->fVmxPauseExit = (pBaseFeat->fVmxPauseExit & EmuFeat.fVmxPauseExit );
1884	pGuestFeat->fVmxSecondaryExecCtls = (pBaseFeat->fVmxSecondaryExecCtls & EmuFeat.fVmxSecondaryExecCtls );
1885	pGuestFeat->fVmxVirtApicAccess = (pBaseFeat->fVmxVirtApicAccess & EmuFeat.fVmxVirtApicAccess );
1886	pGuestFeat->fVmxEpt = (pBaseFeat->fVmxEpt & EmuFeat.fVmxEpt );
1887	pGuestFeat->fVmxDescTableExit = (pBaseFeat->fVmxDescTableExit & EmuFeat.fVmxDescTableExit );
1888	pGuestFeat->fVmxRdtscp = (pBaseFeat->fVmxRdtscp & EmuFeat.fVmxRdtscp );
1889	pGuestFeat->fVmxVirtX2ApicMode = (pBaseFeat->fVmxVirtX2ApicMode & EmuFeat.fVmxVirtX2ApicMode );
1890	pGuestFeat->fVmxVpid = (pBaseFeat->fVmxVpid & EmuFeat.fVmxVpid );
1891	pGuestFeat->fVmxWbinvdExit = (pBaseFeat->fVmxWbinvdExit & EmuFeat.fVmxWbinvdExit );
1892	pGuestFeat->fVmxUnrestrictedGuest = (pBaseFeat->fVmxUnrestrictedGuest & EmuFeat.fVmxUnrestrictedGuest );
1893	pGuestFeat->fVmxApicRegVirt = (pBaseFeat->fVmxApicRegVirt & EmuFeat.fVmxApicRegVirt );
1894	pGuestFeat->fVmxVirtIntDelivery = (pBaseFeat->fVmxVirtIntDelivery & EmuFeat.fVmxVirtIntDelivery );
1895	pGuestFeat->fVmxPauseLoopExit = (pBaseFeat->fVmxPauseLoopExit & EmuFeat.fVmxPauseLoopExit );
1896	pGuestFeat->fVmxRdrandExit = (pBaseFeat->fVmxRdrandExit & EmuFeat.fVmxRdrandExit );
1897	pGuestFeat->fVmxInvpcid = (pBaseFeat->fVmxInvpcid & EmuFeat.fVmxInvpcid );
1898	pGuestFeat->fVmxVmFunc = (pBaseFeat->fVmxVmFunc & EmuFeat.fVmxVmFunc );
1899	pGuestFeat->fVmxVmcsShadowing = (pBaseFeat->fVmxVmcsShadowing & EmuFeat.fVmxVmcsShadowing );
1900	pGuestFeat->fVmxRdseedExit = (pBaseFeat->fVmxRdseedExit & EmuFeat.fVmxRdseedExit );
1901	pGuestFeat->fVmxPml = (pBaseFeat->fVmxPml & EmuFeat.fVmxPml );
1902	pGuestFeat->fVmxEptXcptVe = (pBaseFeat->fVmxEptXcptVe & EmuFeat.fVmxEptXcptVe );
1903	pGuestFeat->fVmxConcealVmxFromPt = (pBaseFeat->fVmxConcealVmxFromPt & EmuFeat.fVmxConcealVmxFromPt );
1904	pGuestFeat->fVmxXsavesXrstors = (pBaseFeat->fVmxXsavesXrstors & EmuFeat.fVmxXsavesXrstors );
1905	pGuestFeat->fVmxModeBasedExecuteEpt = (pBaseFeat->fVmxModeBasedExecuteEpt & EmuFeat.fVmxModeBasedExecuteEpt );
1906	pGuestFeat->fVmxSppEpt = (pBaseFeat->fVmxSppEpt & EmuFeat.fVmxSppEpt );
1907	pGuestFeat->fVmxPtEpt = (pBaseFeat->fVmxPtEpt & EmuFeat.fVmxPtEpt );
1908	pGuestFeat->fVmxUseTscScaling = (pBaseFeat->fVmxUseTscScaling & EmuFeat.fVmxUseTscScaling );
1909	pGuestFeat->fVmxUserWaitPause = (pBaseFeat->fVmxUserWaitPause & EmuFeat.fVmxUserWaitPause );
1910	pGuestFeat->fVmxEnclvExit = (pBaseFeat->fVmxEnclvExit & EmuFeat.fVmxEnclvExit );
1911	pGuestFeat->fVmxLoadIwKeyExit = (pBaseFeat->fVmxLoadIwKeyExit & EmuFeat.fVmxLoadIwKeyExit );
1912	pGuestFeat->fVmxEntryLoadDebugCtls = (pBaseFeat->fVmxEntryLoadDebugCtls & EmuFeat.fVmxEntryLoadDebugCtls );
1913	pGuestFeat->fVmxIa32eModeGuest = (pBaseFeat->fVmxIa32eModeGuest & EmuFeat.fVmxIa32eModeGuest );
1914	pGuestFeat->fVmxEntryLoadEferMsr = (pBaseFeat->fVmxEntryLoadEferMsr & EmuFeat.fVmxEntryLoadEferMsr );
1915	pGuestFeat->fVmxEntryLoadPatMsr = (pBaseFeat->fVmxEntryLoadPatMsr & EmuFeat.fVmxEntryLoadPatMsr );
1916	pGuestFeat->fVmxExitSaveDebugCtls = (pBaseFeat->fVmxExitSaveDebugCtls & EmuFeat.fVmxExitSaveDebugCtls );
1917	pGuestFeat->fVmxHostAddrSpaceSize = (pBaseFeat->fVmxHostAddrSpaceSize & EmuFeat.fVmxHostAddrSpaceSize );
1918	pGuestFeat->fVmxExitAckExtInt = (pBaseFeat->fVmxExitAckExtInt & EmuFeat.fVmxExitAckExtInt );
1919	pGuestFeat->fVmxExitSavePatMsr = (pBaseFeat->fVmxExitSavePatMsr & EmuFeat.fVmxExitSavePatMsr );
1920	pGuestFeat->fVmxExitLoadPatMsr = (pBaseFeat->fVmxExitLoadPatMsr & EmuFeat.fVmxExitLoadPatMsr );
1921	pGuestFeat->fVmxExitSaveEferMsr = (pBaseFeat->fVmxExitSaveEferMsr & EmuFeat.fVmxExitSaveEferMsr );
1922	pGuestFeat->fVmxExitLoadEferMsr = (pBaseFeat->fVmxExitLoadEferMsr & EmuFeat.fVmxExitLoadEferMsr );
1923	pGuestFeat->fVmxSavePreemptTimer = (pBaseFeat->fVmxSavePreemptTimer & EmuFeat.fVmxSavePreemptTimer );
1924	pGuestFeat->fVmxExitSaveEferLma = (pBaseFeat->fVmxExitSaveEferLma & EmuFeat.fVmxExitSaveEferLma );
1925	pGuestFeat->fVmxPt = (pBaseFeat->fVmxPt & EmuFeat.fVmxPt );
1926	pGuestFeat->fVmxVmwriteAll = (pBaseFeat->fVmxVmwriteAll & EmuFeat.fVmxVmwriteAll );
1927	pGuestFeat->fVmxEntryInjectSoftInt = (pBaseFeat->fVmxEntryInjectSoftInt & EmuFeat.fVmxEntryInjectSoftInt );
1928
1929	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1930	/* Don't expose VMX preemption timer if host is subject to VMX-preemption timer erratum. */
1931	if ( pGuestFeat->fVmxPreemptTimer
1932	&& HMIsSubjectToVmxPreemptTimerErratum())
1933	{
1934	LogRel(("CPUM: Warning! VMX-preemption timer not exposed to guest due to host CPU erratum.\n"));
1935	pGuestFeat->fVmxPreemptTimer = 0;
1936	pGuestFeat->fVmxSavePreemptTimer = 0;
1937	}
1938	#endif
1939
1940	/* Sanity checking. */
1941	if (!pGuestFeat->fVmxSecondaryExecCtls)
1942	{
1943	Assert(!pGuestFeat->fVmxVirtApicAccess);
1944	Assert(!pGuestFeat->fVmxEpt);
1945	Assert(!pGuestFeat->fVmxDescTableExit);
1946	Assert(!pGuestFeat->fVmxRdtscp);
1947	Assert(!pGuestFeat->fVmxVirtX2ApicMode);
1948	Assert(!pGuestFeat->fVmxVpid);
1949	Assert(!pGuestFeat->fVmxWbinvdExit);
1950	Assert(!pGuestFeat->fVmxUnrestrictedGuest);
1951	Assert(!pGuestFeat->fVmxApicRegVirt);
1952	Assert(!pGuestFeat->fVmxVirtIntDelivery);
1953	Assert(!pGuestFeat->fVmxPauseLoopExit);
1954	Assert(!pGuestFeat->fVmxRdrandExit);
1955	Assert(!pGuestFeat->fVmxInvpcid);
1956	Assert(!pGuestFeat->fVmxVmFunc);
1957	Assert(!pGuestFeat->fVmxVmcsShadowing);
1958	Assert(!pGuestFeat->fVmxRdseedExit);
1959	Assert(!pGuestFeat->fVmxPml);
1960	Assert(!pGuestFeat->fVmxEptXcptVe);
1961	Assert(!pGuestFeat->fVmxConcealVmxFromPt);
1962	Assert(!pGuestFeat->fVmxXsavesXrstors);
1963	Assert(!pGuestFeat->fVmxModeBasedExecuteEpt);
1964	Assert(!pGuestFeat->fVmxSppEpt);
1965	Assert(!pGuestFeat->fVmxPtEpt);
1966	Assert(!pGuestFeat->fVmxUseTscScaling);
1967	Assert(!pGuestFeat->fVmxUserWaitPause);
1968	Assert(!pGuestFeat->fVmxEnclvExit);
1969	}
1970	else if (pGuestFeat->fVmxUnrestrictedGuest)
1971	{
1972	/* See footnote in Intel spec. 27.2 "Recording VM-Exit Information And Updating VM-entry Control Fields". */
1973	Assert(pGuestFeat->fVmxExitSaveEferLma);
1974	/* Unrestricted guest execution requires EPT. See Intel spec. 25.2.1.1 "VM-Execution Control Fields". */
1975	Assert(pGuestFeat->fVmxEpt);
1976	}
1977
1978	if (!pGuestFeat->fVmxTertiaryExecCtls)
1979	Assert(!pGuestFeat->fVmxLoadIwKeyExit);
1980
1981	/*
1982	* Finally initialize the VMX guest MSRs.
1983	*/
1984	cpumR3InitVmxGuestMsrs(pVM, pHostVmxMsrs, pGuestFeat, pGuestVmxMsrs);
1985	}
1986
1987
1988	/**
1989	* Gets the host hardware-virtualization MSRs.
1990	*
1991	* @returns VBox status code.
1992	* @param pMsrs Where to store the MSRs.
1993	*/
1994	static int cpumR3GetHostHwvirtMsrs(PCPUMMSRS pMsrs)
1995	{
1996	Assert(pMsrs);
1997
1998	uint32_t fCaps = 0;
1999	int rc = SUPR3QueryVTCaps(&fCaps);
2000	if (RT_SUCCESS(rc))
2001	{
2002	if (fCaps & (SUPVTCAPS_VT_X \| SUPVTCAPS_AMD_V))
2003	{
2004	SUPHWVIRTMSRS HwvirtMsrs;
2005	rc = SUPR3GetHwvirtMsrs(&HwvirtMsrs, false /* fForceRequery */);
2006	if (RT_SUCCESS(rc))
2007	{
2008	if (fCaps & SUPVTCAPS_VT_X)
2009	HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.vmx);
2010	else
2011	HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.svm);
2012	return VINF_SUCCESS;
2013	}
2014
2015	LogRel(("CPUM: Querying hardware-virtualization MSRs failed. rc=%Rrc\n", rc));
2016	return rc;
2017	}
2018
2019	LogRel(("CPUM: Querying hardware-virtualization capability succeeded but did not find VT-x or AMD-V\n"));
2020	return VERR_INTERNAL_ERROR_5;
2021	}
2022	LogRel(("CPUM: No hardware-virtualization capability detected\n"));
2023	return VINF_SUCCESS;
2024	}
2025
2026
2027	/**
2028	* @callback_method_impl{FNTMTIMERINT,
2029	* Callback that fires when the nested VMX-preemption timer expired.}
2030	*/
2031	static DECLCALLBACK(void) cpumR3VmxPreemptTimerCallback(PVM pVM, TMTIMERHANDLE hTimer, void *pvUser)
2032	{
2033	RT_NOREF(pVM, hTimer);
2034	PVMCPU pVCpu = (PVMCPUR3)pvUser;
2035	AssertPtr(pVCpu);
2036	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
2037	}
2038
2039
2040	/**
2041	* Initializes the CPUM.
2042	*
2043	* @returns VBox status code.
2044	* @param pVM The cross context VM structure.
2045	*/
2046	VMMR3DECL(int) CPUMR3Init(PVM pVM)
2047	{
2048	LogFlow(("CPUMR3Init\n"));
2049
2050	/*
2051	* Assert alignment, sizes and tables.
2052	*/
2053	AssertCompileMemberAlignment(VM, cpum.s, 32);
2054	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
2055	AssertCompileSizeAlignment(CPUMCTX, 64);
2056	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
2057	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
2058	AssertCompileMemberAlignment(VM, cpum, 64);
2059	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
2060	#ifdef VBOX_STRICT
2061	int rc2 = cpumR3MsrStrictInitChecks();
2062	AssertRCReturn(rc2, rc2);
2063	#endif
2064
2065	/*
2066	* Gather info about the host CPU.
2067	*/
2068	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2069	if (!ASMHasCpuId())
2070	{
2071	LogRel(("The CPU doesn't support CPUID!\n"));
2072	return VERR_UNSUPPORTED_CPU;
2073	}
2074
2075	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
2076	#endif
2077
2078	CPUMMSRS HostMsrs;
2079	RT_ZERO(HostMsrs);
2080	int rc = cpumR3GetHostHwvirtMsrs(&HostMsrs);
2081	AssertLogRelRCReturn(rc, rc);
2082
2083	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2084	/* Use the host features detected by CPUMR0ModuleInit if available. */
2085	if (pVM->cpum.s.HostFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID)
2086	g_CpumHostFeatures.s = pVM->cpum.s.HostFeatures;
2087	else
2088	{
2089	PCPUMCPUIDLEAF paLeaves;
2090	uint32_t cLeaves;
2091	rc = CPUMCpuIdCollectLeavesX86(&paLeaves, &cLeaves);
2092	AssertLogRelRCReturn(rc, rc);
2093
2094	rc = cpumCpuIdExplodeFeaturesX86(paLeaves, cLeaves, &HostMsrs, &g_CpumHostFeatures.s);
2095	RTMemFree(paLeaves);
2096	AssertLogRelRCReturn(rc, rc);
2097	}
2098	pVM->cpum.s.HostFeatures = g_CpumHostFeatures.s;
2099	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
2100	#endif
2101
2102	/*
2103	* Check that the CPU supports the minimum features we require.
2104	*/
2105	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
2106	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
2107	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
2108	if (!pVM->cpum.s.HostFeatures.fMmx)
2109	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
2110	if (!pVM->cpum.s.HostFeatures.fTsc)
2111	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
2112	#endif
2113
2114	/*
2115	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
2116	*/
2117	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
2118	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
2119
2120	/*
2121	* Figure out which XSAVE/XRSTOR features are available on the host.
2122	*/
2123	uint64_t fXcr0Host = 0;
2124	uint64_t fXStateHostMask = 0;
2125	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2126	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
2127	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
2128	{
2129	fXStateHostMask = fXcr0Host = ASMGetXcr0();
2130	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
2131	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2132	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
2133	}
2134	#endif
2135	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
2136	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
2137	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
2138
2139	/*
2140	* Initialize the host XSAVE/XRSTOR mask.
2141	*/
2142	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2143	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
2144	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
2145	AssertLogRelReturn( pVM->cpum.s.HostFeatures.cbMaxExtendedState >= sizeof(X86FXSTATE)
2146	&& pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Host.XState)
2147	&& pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Guest.XState)
2148	, VERR_CPUM_IPE_2);
2149	#endif
2150
2151	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2152	{
2153	PVMCPU pVCpu = pVM->apCpusR3[i];
2154
2155	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
2156	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2157	}
2158
2159	/*
2160	* Register saved state data item.
2161	*/
2162	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
2163	NULL, cpumR3LiveExec, NULL,
2164	NULL, cpumR3SaveExec, NULL,
2165	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
2166	if (RT_FAILURE(rc))
2167	return rc;
2168
2169	/*
2170	* Register info handlers and registers with the debugger facility.
2171	*/
2172	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
2173	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
2174	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
2175	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
2176	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
2177	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
2178	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
2179	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
2180	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
2181	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
2182	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
2183	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
2184	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.",
2185	&cpumR3CpuIdInfo);
2186	DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
2187	&cpumR3InfoVmxFeatures);
2188
2189	rc = cpumR3DbgInit(pVM);
2190	if (RT_FAILURE(rc))
2191	return rc;
2192
2193	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2194	/*
2195	* Check if we need to workaround partial/leaky FPU handling.
2196	*/
2197	cpumR3CheckLeakyFpu(pVM);
2198	#endif
2199
2200	/*
2201	* Initialize the Guest CPUID and MSR states.
2202	*/
2203	rc = cpumR3InitCpuIdAndMsrs(pVM, &HostMsrs);
2204	if (RT_FAILURE(rc))
2205	return rc;
2206
2207	/*
2208	* Generate the RFLAGS cookie.
2209	*/
2210	pVM->cpum.s.fReservedRFlagsCookie = RTRandU64() & ~(CPUMX86EFLAGS_HW_MASK_64 \| CPUMX86EFLAGS_INT_MASK_64);
2211
2212	/*
2213	* Init the VMX/SVM state.
2214	*
2215	* This must be done after initializing CPUID/MSR features as we access the
2216	* the VMX/SVM guest features below.
2217	*
2218	* In the case of nested VT-x, we also need to create the per-VCPU
2219	* VMX preemption timers.
2220	*/
2221	if (pVM->cpum.s.GuestFeatures.fVmx)
2222	cpumR3InitVmxHwVirtState(pVM);
2223	else if (pVM->cpum.s.GuestFeatures.fSvm)
2224	cpumR3InitSvmHwVirtState(pVM);
2225	else
2226	Assert(pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
2227
2228	/*
2229	* Initialize the general guest CPU state.
2230	*/
2231	CPUMR3Reset(pVM);
2232
2233	return VINF_SUCCESS;
2234	}
2235
2236
2237	/**
2238	* Applies relocations to data and code managed by this
2239	* component. This function will be called at init and
2240	* whenever the VMM need to relocate it self inside the GC.
2241	*
2242	* The CPUM will update the addresses used by the switcher.
2243	*
2244	* @param pVM The cross context VM structure.
2245	*/
2246	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
2247	{
2248	RT_NOREF(pVM);
2249	}
2250
2251
2252	/**
2253	* Terminates the CPUM.
2254	*
2255	* Termination means cleaning up and freeing all resources,
2256	* the VM it self is at this point powered off or suspended.
2257	*
2258	* @returns VBox status code.
2259	* @param pVM The cross context VM structure.
2260	*/
2261	VMMR3DECL(int) CPUMR3Term(PVM pVM)
2262	{
2263	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2264	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2265	{
2266	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2267	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
2268	pVCpu->cpum.s.uMagic = 0;
2269	pvCpu->cpum.s.Guest.dr[5] = 0;
2270	}
2271	#endif
2272
2273	if (pVM->cpum.s.GuestFeatures.fVmx)
2274	{
2275	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2276	{
2277	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2278	if (pVCpu->cpum.s.hNestedVmxPreemptTimer != NIL_TMTIMERHANDLE)
2279	{
2280	int rc = TMR3TimerDestroy(pVM, pVCpu->cpum.s.hNestedVmxPreemptTimer); AssertRC(rc);
2281	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2282	}
2283	}
2284	}
2285	return VINF_SUCCESS;
2286	}
2287
2288
2289	/**
2290	* Resets a virtual CPU.
2291	*
2292	* Used by CPUMR3Reset and CPU hot plugging.
2293	*
2294	* @param pVM The cross context VM structure.
2295	* @param pVCpu The cross context virtual CPU structure of the CPU that is
2296	* being reset. This may differ from the current EMT.
2297	*/
2298	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2299	{
2300	/** @todo anything different for VCPU > 0? */
2301	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2302
2303	/*
2304	* Initialize everything to ZERO first.
2305	*/
2306	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
2307
2308	RT_BZERO(pCtx, RT_UOFFSETOF(CPUMCTX, aoffXState));
2309
2310	pVCpu->cpum.s.fUseFlags = fUseFlags;
2311
2312	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
2313	pCtx->eip = 0x0000fff0;
2314	pCtx->edx = 0x00000600; /* P6 processor */
2315
2316	Assert((pVM->cpum.s.fReservedRFlagsCookie & (X86_EFL_LIVE_MASK \| X86_EFL_RAZ_LO_MASK \| X86_EFL_RA1_MASK)) == 0);
2317	pCtx->rflags.uBoth = pVM->cpum.s.fReservedRFlagsCookie \| X86_EFL_RA1_MASK;
2318
2319	pCtx->cs.Sel = 0xf000;
2320	pCtx->cs.ValidSel = 0xf000;
2321	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2322	pCtx->cs.u64Base = UINT64_C(0xffff0000);
2323	pCtx->cs.u32Limit = 0x0000ffff;
2324	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
2325	pCtx->cs.Attr.n.u1Present = 1;
2326	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
2327
2328	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
2329	pCtx->ds.u32Limit = 0x0000ffff;
2330	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
2331	pCtx->ds.Attr.n.u1Present = 1;
2332	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2333
2334	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
2335	pCtx->es.u32Limit = 0x0000ffff;
2336	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
2337	pCtx->es.Attr.n.u1Present = 1;
2338	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2339
2340	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
2341	pCtx->fs.u32Limit = 0x0000ffff;
2342	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
2343	pCtx->fs.Attr.n.u1Present = 1;
2344	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2345
2346	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
2347	pCtx->gs.u32Limit = 0x0000ffff;
2348	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
2349	pCtx->gs.Attr.n.u1Present = 1;
2350	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2351
2352	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2353	pCtx->ss.u32Limit = 0x0000ffff;
2354	pCtx->ss.Attr.n.u1Present = 1;
2355	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
2356	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2357
2358	pCtx->idtr.cbIdt = 0xffff;
2359	pCtx->gdtr.cbGdt = 0xffff;
2360
2361	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2362	pCtx->ldtr.u32Limit = 0xffff;
2363	pCtx->ldtr.Attr.n.u1Present = 1;
2364	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
2365
2366	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2367	pCtx->tr.u32Limit = 0xffff;
2368	pCtx->tr.Attr.n.u1Present = 1;
2369	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
2370
2371	pCtx->dr[6] = X86_DR6_INIT_VAL;
2372	pCtx->dr[7] = X86_DR7_INIT_VAL;
2373
2374	PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
2375	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
2376	pFpuCtx->FCW = 0x37f;
2377
2378	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
2379	IA-32 Processor States Following Power-up, Reset, or INIT */
2380	pFpuCtx->MXCSR = 0x1F80;
2381	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
2382
2383	pCtx->aXcr[0] = XSAVE_C_X87;
2384	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
2385	{
2386	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
2387	as we don't know what happened before. (Bother optimize later?) */
2388	pCtx->XState.Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
2389	}
2390
2391	/*
2392	* MSRs.
2393	*/
2394	/* Init PAT MSR */
2395	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
2396
2397	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
2398	* The Intel docs don't mention it. */
2399	Assert(!pCtx->msrEFER);
2400
2401	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
2402	is supposed to be here, just trying provide useful/sensible values. */
2403	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
2404	if (pRange)
2405	{
2406	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2407	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
2408	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
2409	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
2410	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2411	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
2412	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
2413	}
2414
2415	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
2416
2417	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
2418	* called from each EMT while we're getting called by CPUMR3Reset()
2419	* iteratively on the same thread. Fix later. */
2420	#if 0 /** @todo r=bird: This we will do in TM, not here. */
2421	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
2422	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
2423	#endif
2424
2425
2426	/* C-state control. Guesses. */
2427	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
2428	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
2429	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
2430	* functionality. The default value must be different due to incompatible write mask.
2431	*/
2432	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
2433	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
2434	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
2435	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
2436
2437	/*
2438	* Hardware virtualization state.
2439	*/
2440	CPUMSetGuestGif(pCtx, true);
2441	Assert(!pVM->cpum.s.GuestFeatures.fVmx \|\| !pVM->cpum.s.GuestFeatures.fSvm); /* Paranoia. */
2442	if (pVM->cpum.s.GuestFeatures.fVmx)
2443	cpumR3ResetVmxHwVirtState(pVCpu);
2444	else if (pVM->cpum.s.GuestFeatures.fSvm)
2445	cpumR3ResetSvmHwVirtState(pVCpu);
2446	}
2447
2448
2449	/**
2450	* Resets the CPU.
2451	*
2452	* @returns VINF_SUCCESS.
2453	* @param pVM The cross context VM structure.
2454	*/
2455	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
2456	{
2457	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2458	{
2459	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2460	CPUMR3ResetCpu(pVM, pVCpu);
2461
2462	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2463
2464	/* Magic marker for searching in crash dumps. */
2465	strcpy((char *)pVCpu->.cpum.s.aMagic, "CPUMCPU Magic");
2466	pVCpu->cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2467	pVCpu->cpum.s.Guest->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2468	#endif
2469	}
2470	}
2471
2472
2473
2474
2475	/**
2476	* Pass 0 live exec callback.
2477	*
2478	* @returns VINF_SSM_DONT_CALL_AGAIN.
2479	* @param pVM The cross context VM structure.
2480	* @param pSSM The saved state handle.
2481	* @param uPass The pass (0).
2482	*/
2483	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2484	{
2485	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2486	cpumR3SaveCpuId(pVM, pSSM);
2487	return VINF_SSM_DONT_CALL_AGAIN;
2488	}
2489
2490
2491	/**
2492	* Execute state save operation.
2493	*
2494	* @returns VBox status code.
2495	* @param pVM The cross context VM structure.
2496	* @param pSSM SSM operation handle.
2497	*/
2498	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2499	{
2500	/*
2501	* Save.
2502	*/
2503	SSMR3PutU32(pSSM, pVM->cCpus);
2504	SSMR3PutU32(pSSM, sizeof(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr));
2505	CPUMCTX DummyHyperCtx;
2506	RT_ZERO(DummyHyperCtx);
2507	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2508	{
2509	PVMCPU const pVCpu = pVM->apCpusR3[idCpu];
2510	PCPUMCTX const pGstCtx = &pVCpu->cpum.s.Guest;
2511
2512	/** @todo ditch this the next time we change the saved state. */
2513	SSMR3PutStructEx(pSSM, &DummyHyperCtx, sizeof(DummyHyperCtx), 0, g_aCpumCtxFields, NULL);
2514
2515	uint64_t const fSavedRFlags = pGstCtx->rflags.uBoth;
2516	pGstCtx->rflags.uBoth &= CPUMX86EFLAGS_HW_MASK_64; /* Temporarily clear the non-hardware bits in RFLAGS while saving. */
2517	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2518	pGstCtx->rflags.uBoth = fSavedRFlags;
2519
2520	SSMR3PutStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2521	if (pGstCtx->fXStateMask != 0)
2522	SSMR3PutStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr), 0, g_aCpumXSaveHdrFields, NULL);
2523	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2524	{
2525	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2526	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2527	}
2528	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2529	{
2530	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2531	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2532	}
2533	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2534	{
2535	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2536	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2537	}
2538	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2539	{
2540	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2541	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2542	}
2543	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2544	{
2545	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2546	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2547	}
2548	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[0].u);
2549	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[1].u);
2550	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[2].u);
2551	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[3].u);
2552	if (pVM->cpum.s.GuestFeatures.fSvm)
2553	{
2554	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2555	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2556	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2557	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2558	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2559	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2560	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2561	g_aSvmHwvirtHostState, NULL /* pvUser */);
2562	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2563	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2564	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2565	/* This is saved in the old VMCPUM_FF format. Change if more flags are added. */
2566	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fSavedInhibit & CPUMCTX_INHIBIT_NMI ? CPUM_OLD_VMCPU_FF_BLOCK_NMIS : 0);
2567	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2568	}
2569	if (pVM->cpum.s.GuestFeatures.fVmx)
2570	{
2571	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmxon);
2572	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmcs);
2573	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2574	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxRootMode);
2575	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2576	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInterceptEvents);
2577	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2578	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs), 0, g_aVmxHwvirtVmcs, NULL);
2579	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2580	0, g_aVmxHwvirtVmcs, NULL);
2581	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2582	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2583	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2584	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2585	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2586	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2587	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2588	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2589	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uPrevPauseTick);
2590	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uEntryTick);
2591	SSMR3PutU16(pSSM, pGstCtx->hwvirt.vmx.offVirtApicWrite);
2592	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2593	SSMR3PutU64(pSSM, MSR_IA32_FEATURE_CONTROL_LOCK \| MSR_IA32_FEATURE_CONTROL_VMXON); /* Deprecated since 2021/09/22. Value kept backwards compatibile with 6.1.26. */
2594	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2595	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2596	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2597	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2598	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2599	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2600	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2601	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2602	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2603	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2604	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2605	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2606	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2607	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2608	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2609	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2610	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2611	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2612	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2613	}
2614	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2615	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2616	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2617	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2618	}
2619
2620	cpumR3SaveCpuId(pVM, pSSM);
2621	return VINF_SUCCESS;
2622	}
2623
2624
2625	/**
2626	* @callback_method_impl{FNSSMINTLOADPREP}
2627	*/
2628	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2629	{
2630	NOREF(pSSM);
2631	pVM->cpum.s.fPendingRestore = true;
2632	return VINF_SUCCESS;
2633	}
2634
2635
2636	/**
2637	* @callback_method_impl{FNSSMINTLOADEXEC}
2638	*/
2639	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2640	{
2641	int rc; /* Only for AssertRCReturn use. */
2642
2643	/*
2644	* Validate version.
2645	*/
2646	if ( uVersion != CPUM_SAVED_STATE_VERSION_PAE_PDPES
2647	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2
2648	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX
2649	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2650	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2651	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2652	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2653	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2654	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
2655	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2656	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2657	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2658	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2659	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2660	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2661	{
2662	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2663	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2664	}
2665
2666	if (uPass == SSM_PASS_FINAL)
2667	{
2668	/*
2669	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2670	* really old SSM file versions.)
2671	*/
2672	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2673	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2674	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2675	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR));
2676
2677	/*
2678	* Figure x86 and ctx field definitions to use for older states.
2679	*/
2680	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2681	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2682	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2683	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2684	{
2685	paCpumCtx1Fields = g_aCpumX87FieldsV16;
2686	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2687	}
2688	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2689	{
2690	paCpumCtx1Fields = g_aCpumX87FieldsMem;
2691	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2692	}
2693
2694	/*
2695	* The hyper state used to preceed the CPU count. Starting with
2696	* XSAVE it was moved down till after we've got the count.
2697	*/
2698	CPUMCTX HyperCtxIgnored;
2699	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2700	{
2701	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2702	{
2703	X86FXSTATE Ign;
2704	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2705	SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored),
2706	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2707	}
2708	}
2709
2710	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2711	{
2712	uint32_t cCpus;
2713	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2714	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2715	VERR_SSM_UNEXPECTED_DATA);
2716	}
2717	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2718	\|\| pVM->cCpus == 1,
2719	("cCpus=%u\n", pVM->cCpus),
2720	VERR_SSM_UNEXPECTED_DATA);
2721
2722	uint32_t cbMsrs = 0;
2723	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2724	{
2725	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2726	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2727	VERR_SSM_UNEXPECTED_DATA);
2728	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2729	VERR_SSM_UNEXPECTED_DATA);
2730	}
2731
2732	/*
2733	* Do the per-CPU restoring.
2734	*/
2735	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2736	{
2737	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2738	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2739
2740	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2741	{
2742	/*
2743	* The XSAVE saved state layout moved the hyper state down here.
2744	*/
2745	rc = SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored), 0, g_aCpumCtxFields, NULL);
2746	AssertRCReturn(rc, rc);
2747
2748	/*
2749	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2750	*/
2751	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2752	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2753	AssertRCReturn(rc, rc);
2754
2755	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2756	if (pGstCtx->fXStateMask != 0)
2757	{
2758	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2759	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2760	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2761	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2762	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2763	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2764	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2765	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2766	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2767	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2768	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2769	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2770	}
2771
2772	/* Check that the XCR0 mask is valid (invalid results in #GP). */
2773	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2774	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2775	{
2776	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
2777	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2778	VERR_CPUM_INVALID_XCR0);
2779	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2780	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2781	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2782	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2783	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2784	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2785	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2786	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2787	}
2788
2789	/* Check that the XCR1 is zero, as we don't implement it yet. */
2790	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2791
2792	/*
2793	* Restore the individual extended state components we support.
2794	*/
2795	if (pGstCtx->fXStateMask != 0)
2796	{
2797	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr),
2798	0, g_aCpumXSaveHdrFields, NULL);
2799	AssertRCReturn(rc, rc);
2800	AssertLogRelMsgReturn(!(pGstCtx->XState.Hdr.bmXState & ~pGstCtx->fXStateMask),
2801	("bmXState=%#RX64 fXStateMask=%#RX64\n",
2802	pGstCtx->XState.Hdr.bmXState, pGstCtx->fXStateMask),
2803	VERR_CPUM_INVALID_XSAVE_HDR);
2804	}
2805	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2806	{
2807	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2808	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2809	}
2810	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2811	{
2812	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2813	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2814	}
2815	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2816	{
2817	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2818	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2819	}
2820	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2821	{
2822	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2823	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2824	}
2825	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2826	{
2827	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2828	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2829	}
2830	if (uVersion >= CPUM_SAVED_STATE_VERSION_PAE_PDPES)
2831	{
2832	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[0].u);
2833	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[1].u);
2834	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[2].u);
2835	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[3].u);
2836	}
2837	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2838	{
2839	if (pVM->cpum.s.GuestFeatures.fSvm)
2840	{
2841	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2842	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2843	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2844	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2845	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2846	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2847	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2848	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
2849	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2850	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2851	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2852
2853	uint32_t fSavedLocalFFs = 0;
2854	rc = SSMR3GetU32(pSSM, &fSavedLocalFFs);
2855	AssertRCReturn(rc, rc);
2856	Assert(fSavedLocalFFs == 0 \|\| fSavedLocalFFs == CPUM_OLD_VMCPU_FF_BLOCK_NMIS);
2857	pGstCtx->hwvirt.fSavedInhibit = fSavedLocalFFs & CPUM_OLD_VMCPU_FF_BLOCK_NMIS ? CPUMCTX_INHIBIT_NMI : 0;
2858
2859	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2860	}
2861	}
2862	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX)
2863	{
2864	if (pVM->cpum.s.GuestFeatures.fVmx)
2865	{
2866	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmxon);
2867	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmcs);
2868	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2869	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxRootMode);
2870	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2871	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInterceptEvents);
2872	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2873	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs),
2874	0, g_aVmxHwvirtVmcs, NULL);
2875	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2876	0, g_aVmxHwvirtVmcs, NULL);
2877	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2878	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2879	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2880	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2881	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2882	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2883	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2884	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2885	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uPrevPauseTick);
2886	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uEntryTick);
2887	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.vmx.offVirtApicWrite);
2888	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2889	SSMR3Skip(pSSM, sizeof(uint64_t)); /* Unused - used to be IA32_FEATURE_CONTROL, see @bugref{10106}. */
2890	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2891	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2892	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2893	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2894	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2895	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2896	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2897	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2898	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2899	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2900	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2901	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2902	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2903	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2904	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2905	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2906	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2907	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2908	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2)
2909	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2910	}
2911	}
2912	}
2913	else
2914	{
2915	/*
2916	* Pre XSAVE saved state.
2917	*/
2918	SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87),
2919	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2920	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2921	}
2922
2923	/*
2924	* Restore a couple of flags and the MSRs.
2925	*/
2926	uint32_t fIgnoredUsedFlags = 0;
2927	rc = SSMR3GetU32(pSSM, &fIgnoredUsedFlags); /* we're recalc the two relevant flags after loading state. */
2928	AssertRCReturn(rc, rc);
2929	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2930
2931	rc = VINF_SUCCESS;
2932	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2933	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2934	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2935	{
2936	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2937	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2938	}
2939	AssertRCReturn(rc, rc);
2940
2941	/* Deal with the reusing of reserved RFLAGS bits. */
2942	pGstCtx->rflags.uBoth \|= pVM->cpum.s.fReservedRFlagsCookie;
2943
2944	/* REM and other may have cleared must-be-one fields in DR6 and
2945	DR7, fix these. */
2946	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
2947	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
2948	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
2949	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
2950	}
2951
2952	/* Older states does not have the internal selector register flags
2953	and valid selector value. Supply those. */
2954	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2955	{
2956	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2957	{
2958	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2959	bool const fValid = true /!VM_IS_RAW_MODE_ENABLED(pVM)/
2960	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2961	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2962	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2963	if (fValid)
2964	{
2965	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2966	{
2967	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2968	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2969	}
2970
2971	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2972	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2973	}
2974	else
2975	{
2976	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2977	{
2978	paSelReg[iSelReg].fFlags = 0;
2979	paSelReg[iSelReg].ValidSel = 0;
2980	}
2981
2982	/* This might not be 104% correct, but I think it's close
2983	enough for all practical purposes... (REM always loaded
2984	LDTR registers.) */
2985	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2986	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2987	}
2988	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2989	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2990	}
2991	}
2992
2993	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2994	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2995	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2996	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2997	{
2998	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2999	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3000	}
3001
3002	/*
3003	* A quick sanity check.
3004	*/
3005	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3006	{
3007	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3008	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3009	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3010	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3011	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3012	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3013	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3014	}
3015	}
3016
3017	pVM->cpum.s.fPendingRestore = false;
3018
3019	/*
3020	* Guest CPUIDs (and VMX MSR features).
3021	*/
3022	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
3023	{
3024	CPUMMSRS GuestMsrs;
3025	RT_ZERO(GuestMsrs);
3026
3027	CPUMFEATURES BaseFeatures;
3028	bool const fVmxGstFeat = pVM->cpum.s.GuestFeatures.fVmx;
3029	if (fVmxGstFeat)
3030	{
3031	/*
3032	* At this point the MSRs in the guest CPU-context are loaded with the guest VMX MSRs from the saved state.
3033	* However the VMX sub-features have not been exploded yet. So cache the base (host derived) VMX features
3034	* here so we can compare them for compatibility after exploding guest features.
3035	*/
3036	BaseFeatures = pVM->cpum.s.GuestFeatures;
3037
3038	/* Use the VMX MSR features from the saved state while exploding guest features. */
3039	GuestMsrs.hwvirt.vmx = pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.vmx.Msrs;
3040	}
3041
3042	/* Load CPUID and explode guest features. */
3043	rc = cpumR3LoadCpuId(pVM, pSSM, uVersion, &GuestMsrs);
3044	if (fVmxGstFeat)
3045	{
3046	/*
3047	* Check if the exploded VMX features from the saved state are compatible with the host-derived features
3048	* we cached earlier (above). The is required if we use hardware-assisted nested-guest execution with
3049	* VMX features presented to the guest.
3050	*/
3051	bool const fIsCompat = cpumR3AreVmxCpuFeaturesCompatible(pVM, &BaseFeatures, &pVM->cpum.s.GuestFeatures);
3052	if (!fIsCompat)
3053	return VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO;
3054	}
3055	return rc;
3056	}
3057	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
3058	}
3059
3060
3061	/**
3062	* @callback_method_impl{FNSSMINTLOADDONE}
3063	*/
3064	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
3065	{
3066	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
3067	return VINF_SUCCESS;
3068
3069	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
3070	if (pVM->cpum.s.fPendingRestore)
3071	{
3072	LogRel(("CPUM: Missing state!\n"));
3073	return VERR_INTERNAL_ERROR_2;
3074	}
3075
3076	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
3077	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3078	{
3079	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3080
3081	/* Notify PGM of the NXE states in case they've changed. */
3082	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
3083
3084	/* During init. this is done in CPUMR3InitCompleted(). */
3085	if (fSupportsLongMode)
3086	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
3087
3088	/* Recalc the CPUM_USE_DEBUG_REGS_HYPER value. */
3089	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX);
3090	}
3091	return VINF_SUCCESS;
3092	}
3093
3094
3095	/**
3096	* Checks if the CPUM state restore is still pending.
3097	*
3098	* @returns true / false.
3099	* @param pVM The cross context VM structure.
3100	*/
3101	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
3102	{
3103	return pVM->cpum.s.fPendingRestore;
3104	}
3105
3106
3107	/**
3108	* Formats the EFLAGS value into mnemonics.
3109	*
3110	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
3111	* @param efl The EFLAGS value with fInhibit in bits 31:24.
3112	*/
3113	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
3114	{
3115	/*
3116	* Format the flags.
3117	*/
3118	static const struct
3119	{
3120	const char pszSet; const char pszClear; uint32_t fFlag;
3121	} s_aFlags[] =
3122	{
3123	{ "vip",NULL, X86_EFL_VIP },
3124	{ "vif",NULL, X86_EFL_VIF },
3125	{ "ac", NULL, X86_EFL_AC },
3126	{ "vm", NULL, X86_EFL_VM },
3127	{ "rf", NULL, X86_EFL_RF },
3128	{ "nt", NULL, X86_EFL_NT },
3129	{ "ov", "nv", X86_EFL_OF },
3130	{ "dn", "up", X86_EFL_DF },
3131	{ "ei", "di", X86_EFL_IF },
3132	{ "tf", NULL, X86_EFL_TF },
3133	{ "nt", "pl", X86_EFL_SF },
3134	{ "nz", "zr", X86_EFL_ZF },
3135	{ "ac", "na", X86_EFL_AF },
3136	{ "po", "pe", X86_EFL_PF },
3137	{ "cy", "nc", X86_EFL_CF },
3138	{ "inh-ss", NULL, (uint32_t)CPUMCTX_INHIBIT_SHADOW_SS << 24 },
3139	{ "inh-sti", NULL, (uint32_t)CPUMCTX_INHIBIT_SHADOW_STI << 24 },
3140	{ "inh-nmi", NULL, (uint32_t)CPUMCTX_INHIBIT_NMI << 24 },
3141	};
3142	char *psz = pszEFlags;
3143	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
3144	{
3145	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
3146	if (pszAdd)
3147	{
3148	strcpy(psz, pszAdd);
3149	psz += strlen(pszAdd);
3150	*psz++ = ' ';
3151	}
3152	}
3153	psz[-1] = '\0';
3154	}
3155
3156
3157	/**
3158	* Formats a full register dump.
3159	*
3160	* @param pVM The cross context VM structure.
3161	* @param pCtx The context to format.
3162	* @param pHlp Output functions.
3163	* @param enmType The dump type.
3164	* @param pszPrefix Register name prefix.
3165	*/
3166	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
3167	{
3168	NOREF(pVM);
3169
3170	/*
3171	* Format the EFLAGS.
3172	*/
3173	uint32_t efl = pCtx->eflags.u;
3174	char szEFlags[80];
3175	cpumR3InfoFormatFlags(&szEFlags[0], efl \| ((uint32_t)pCtx->fInhibit << 24));
3176
3177	/*
3178	* Format the registers.
3179	*/
3180	switch (enmType)
3181	{
3182	case CPUMDUMPTYPE_TERSE:
3183	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3184	pHlp->pfnPrintf(pHlp,
3185	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3186	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3187	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3188	"%sr14=%016RX64 %sr15=%016RX64\n"
3189	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3190	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3191	pszPrefix, pCtx->rax, pszPrefix, pCtx->rbx, pszPrefix, pCtx->rcx, pszPrefix, pCtx->rdx, pszPrefix, pCtx->rsi, pszPrefix, pCtx->rdi,
3192	pszPrefix, pCtx->r8, pszPrefix, pCtx->r9, pszPrefix, pCtx->r10, pszPrefix, pCtx->r11, pszPrefix, pCtx->r12, pszPrefix, pCtx->r13,
3193	pszPrefix, pCtx->r14, pszPrefix, pCtx->r15,
3194	pszPrefix, pCtx->rip, pszPrefix, pCtx->rsp, pszPrefix, pCtx->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3195	pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3196	pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, efl);
3197	else
3198	pHlp->pfnPrintf(pHlp,
3199	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3200	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3201	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3202	pszPrefix, pCtx->eax, pszPrefix, pCtx->ebx, pszPrefix, pCtx->ecx, pszPrefix, pCtx->edx, pszPrefix, pCtx->esi, pszPrefix, pCtx->edi,
3203	pszPrefix, pCtx->eip, pszPrefix, pCtx->esp, pszPrefix, pCtx->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3204	pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3205	pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, efl);
3206	break;
3207
3208	case CPUMDUMPTYPE_DEFAULT:
3209	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3210	pHlp->pfnPrintf(pHlp,
3211	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3212	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3213	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3214	"%sr14=%016RX64 %sr15=%016RX64\n"
3215	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3216	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3217	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
3218	,
3219	pszPrefix, pCtx->rax, pszPrefix, pCtx->rbx, pszPrefix, pCtx->rcx, pszPrefix, pCtx->rdx, pszPrefix, pCtx->rsi, pszPrefix, pCtx->rdi,
3220	pszPrefix, pCtx->r8, pszPrefix, pCtx->r9, pszPrefix, pCtx->r10, pszPrefix, pCtx->r11, pszPrefix, pCtx->r12, pszPrefix, pCtx->r13,
3221	pszPrefix, pCtx->r14, pszPrefix, pCtx->r15,
3222	pszPrefix, pCtx->rip, pszPrefix, pCtx->rsp, pszPrefix, pCtx->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3223	pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3224	pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3225	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3226	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3227	else
3228	pHlp->pfnPrintf(pHlp,
3229	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3230	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3231	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3232	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
3233	,
3234	pszPrefix, pCtx->eax, pszPrefix, pCtx->ebx, pszPrefix, pCtx->ecx, pszPrefix, pCtx->edx, pszPrefix, pCtx->esi, pszPrefix, pCtx->edi,
3235	pszPrefix, pCtx->eip, pszPrefix, pCtx->esp, pszPrefix, pCtx->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3236	pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3237	pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3238	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3239	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3240	break;
3241
3242	case CPUMDUMPTYPE_VERBOSE:
3243	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3244	pHlp->pfnPrintf(pHlp,
3245	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3246	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3247	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3248	"%sr14=%016RX64 %sr15=%016RX64\n"
3249	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3250	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3251	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3252	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3253	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3254	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3255	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3256	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
3257	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
3258	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
3259	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3260	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3261	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3262	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
3263	,
3264	pszPrefix, pCtx->rax, pszPrefix, pCtx->rbx, pszPrefix, pCtx->rcx, pszPrefix, pCtx->rdx, pszPrefix, pCtx->rsi, pszPrefix, pCtx->rdi,
3265	pszPrefix, pCtx->r8, pszPrefix, pCtx->r9, pszPrefix, pCtx->r10, pszPrefix, pCtx->r11, pszPrefix, pCtx->r12, pszPrefix, pCtx->r13,
3266	pszPrefix, pCtx->r14, pszPrefix, pCtx->r15,
3267	pszPrefix, pCtx->rip, pszPrefix, pCtx->rsp, pszPrefix, pCtx->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3268	pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
3269	pszPrefix, pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
3270	pszPrefix, pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
3271	pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
3272	pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
3273	pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
3274	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3275	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3276	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3277	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3278	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3279	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3280	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3281	else
3282	pHlp->pfnPrintf(pHlp,
3283	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3284	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3285	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3286	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3287	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3288	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3289	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3290	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3291	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3292	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3293	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3294	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3295	,
3296	pszPrefix, pCtx->eax, pszPrefix, pCtx->ebx, pszPrefix, pCtx->ecx, pszPrefix, pCtx->edx, pszPrefix, pCtx->esi, pszPrefix, pCtx->edi,
3297	pszPrefix, pCtx->eip, pszPrefix, pCtx->esp, pszPrefix, pCtx->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3298	pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3299	pszPrefix, pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3300	pszPrefix, pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3301	pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3302	pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3303	pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3304	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3305	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3306	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3307	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3308
3309	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
3310	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
3311	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
3312	{
3313	PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
3314	pHlp->pfnPrintf(pHlp,
3315	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3316	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3317	,
3318	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
3319	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
3320	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
3321	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
3322	);
3323	/*
3324	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
3325	* not (FP)R0-7 as Intel SDM suggests.
3326	*/
3327	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
3328	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
3329	{
3330	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
3331	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
3332	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
3333	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
3334	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
3335	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
3336	iExponent -= 16383; /* subtract bias */
3337	/** @todo This isn't entirenly correct and needs more work! */
3338	pHlp->pfnPrintf(pHlp,
3339	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
3340	pszPrefix, iST, pszPrefix, iFPR,
3341	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
3342	uTag, chSign, iInteger, u64Fraction, iExponent);
3343	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
3344	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3345	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
3346	else
3347	pHlp->pfnPrintf(pHlp, "\n");
3348	}
3349
3350	/* XMM/YMM/ZMM registers. */
3351	if (pCtx->fXStateMask & XSAVE_C_YMM)
3352	{
3353	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
3354	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
3355	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3356	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3357	pszPrefix, i, i < 10 ? " " : "",
3358	pYmmHiCtx->aYmmHi[i].au32[3],
3359	pYmmHiCtx->aYmmHi[i].au32[2],
3360	pYmmHiCtx->aYmmHi[i].au32[1],
3361	pYmmHiCtx->aYmmHi[i].au32[0],
3362	pFpuCtx->aXMM[i].au32[3],
3363	pFpuCtx->aXMM[i].au32[2],
3364	pFpuCtx->aXMM[i].au32[1],
3365	pFpuCtx->aXMM[i].au32[0]);
3366	else
3367	{
3368	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
3369	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3370	pHlp->pfnPrintf(pHlp,
3371	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3372	pszPrefix, i, i < 10 ? " " : "",
3373	pZmmHi256->aHi256Regs[i].au32[7],
3374	pZmmHi256->aHi256Regs[i].au32[6],
3375	pZmmHi256->aHi256Regs[i].au32[5],
3376	pZmmHi256->aHi256Regs[i].au32[4],
3377	pZmmHi256->aHi256Regs[i].au32[3],
3378	pZmmHi256->aHi256Regs[i].au32[2],
3379	pZmmHi256->aHi256Regs[i].au32[1],
3380	pZmmHi256->aHi256Regs[i].au32[0],
3381	pYmmHiCtx->aYmmHi[i].au32[3],
3382	pYmmHiCtx->aYmmHi[i].au32[2],
3383	pYmmHiCtx->aYmmHi[i].au32[1],
3384	pYmmHiCtx->aYmmHi[i].au32[0],
3385	pFpuCtx->aXMM[i].au32[3],
3386	pFpuCtx->aXMM[i].au32[2],
3387	pFpuCtx->aXMM[i].au32[1],
3388	pFpuCtx->aXMM[i].au32[0]);
3389
3390	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
3391	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
3392	pHlp->pfnPrintf(pHlp,
3393	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3394	pszPrefix, i + 16,
3395	pZmm16Hi->aRegs[i].au32[15],
3396	pZmm16Hi->aRegs[i].au32[14],
3397	pZmm16Hi->aRegs[i].au32[13],
3398	pZmm16Hi->aRegs[i].au32[12],
3399	pZmm16Hi->aRegs[i].au32[11],
3400	pZmm16Hi->aRegs[i].au32[10],
3401	pZmm16Hi->aRegs[i].au32[9],
3402	pZmm16Hi->aRegs[i].au32[8],
3403	pZmm16Hi->aRegs[i].au32[7],
3404	pZmm16Hi->aRegs[i].au32[6],
3405	pZmm16Hi->aRegs[i].au32[5],
3406	pZmm16Hi->aRegs[i].au32[4],
3407	pZmm16Hi->aRegs[i].au32[3],
3408	pZmm16Hi->aRegs[i].au32[2],
3409	pZmm16Hi->aRegs[i].au32[1],
3410	pZmm16Hi->aRegs[i].au32[0]);
3411	}
3412	}
3413	else
3414	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3415	pHlp->pfnPrintf(pHlp,
3416	i & 1
3417	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3418	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3419	pszPrefix, i, i < 10 ? " " : "",
3420	pFpuCtx->aXMM[i].au32[3],
3421	pFpuCtx->aXMM[i].au32[2],
3422	pFpuCtx->aXMM[i].au32[1],
3423	pFpuCtx->aXMM[i].au32[0]);
3424
3425	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
3426	{
3427	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
3428	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
3429	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
3430	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
3431	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
3432	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
3433	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
3434	}
3435
3436	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
3437	{
3438	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
3439	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
3440	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
3441	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
3442	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
3443	}
3444
3445	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
3446	{
3447	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
3448	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
3449	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
3450	}
3451
3452	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
3453	if (pFpuCtx->au32RsrvdRest[i])
3454	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
3455	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
3456	}
3457
3458	pHlp->pfnPrintf(pHlp,
3459	"%sEFER =%016RX64\n"
3460	"%sPAT =%016RX64\n"
3461	"%sSTAR =%016RX64\n"
3462	"%sCSTAR =%016RX64\n"
3463	"%sLSTAR =%016RX64\n"
3464	"%sSFMASK =%016RX64\n"
3465	"%sKERNELGSBASE =%016RX64\n",
3466	pszPrefix, pCtx->msrEFER,
3467	pszPrefix, pCtx->msrPAT,
3468	pszPrefix, pCtx->msrSTAR,
3469	pszPrefix, pCtx->msrCSTAR,
3470	pszPrefix, pCtx->msrLSTAR,
3471	pszPrefix, pCtx->msrSFMASK,
3472	pszPrefix, pCtx->msrKERNELGSBASE);
3473
3474	if (CPUMIsGuestInPAEModeEx(pCtx))
3475	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aPaePdpes); i++)
3476	pHlp->pfnPrintf(pHlp, "%sPAE PDPTE %u =%016RX64\n", pszPrefix, i, pCtx->aPaePdpes[i]);
3477	break;
3478	}
3479	}
3480
3481
3482	/**
3483	* Display all cpu states and any other cpum info.
3484	*
3485	* @param pVM The cross context VM structure.
3486	* @param pHlp The info helper functions.
3487	* @param pszArgs Arguments, ignored.
3488	*/
3489	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3490	{
3491	cpumR3InfoGuest(pVM, pHlp, pszArgs);
3492	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3493	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
3494	cpumR3InfoHyper(pVM, pHlp, pszArgs);
3495	cpumR3InfoHost(pVM, pHlp, pszArgs);
3496	}
3497
3498
3499	/**
3500	* Parses the info argument.
3501	*
3502	* The argument starts with 'verbose', 'terse' or 'default' and then
3503	* continues with the comment string.
3504	*
3505	* @param pszArgs The pointer to the argument string.
3506	* @param penmType Where to store the dump type request.
3507	* @param ppszComment Where to store the pointer to the comment string.
3508	*/
3509	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
3510	{
3511	if (!pszArgs)
3512	{
3513	*penmType = CPUMDUMPTYPE_DEFAULT;
3514	*ppszComment = "";
3515	}
3516	else
3517	{
3518	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3519	{
3520	pszArgs += 7;
3521	*penmType = CPUMDUMPTYPE_VERBOSE;
3522	}
3523	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3524	{
3525	pszArgs += 5;
3526	*penmType = CPUMDUMPTYPE_TERSE;
3527	}
3528	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3529	{
3530	pszArgs += 7;
3531	*penmType = CPUMDUMPTYPE_DEFAULT;
3532	}
3533	else
3534	*penmType = CPUMDUMPTYPE_DEFAULT;
3535	*ppszComment = RTStrStripL(pszArgs);
3536	}
3537	}
3538
3539
3540	/**
3541	* Display the guest cpu state.
3542	*
3543	* @param pVM The cross context VM structure.
3544	* @param pHlp The info helper functions.
3545	* @param pszArgs Arguments.
3546	*/
3547	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3548	{
3549	CPUMDUMPTYPE enmType;
3550	const char *pszComment;
3551	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3552
3553	PVMCPU pVCpu = VMMGetCpu(pVM);
3554	if (!pVCpu)
3555	pVCpu = pVM->apCpusR3[0];
3556
3557	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3558
3559	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3560	cpumR3InfoOne(pVM, pCtx, pHlp, enmType, "");
3561	}
3562
3563
3564	/**
3565	* Displays an SVM VMCB control area.
3566	*
3567	* @param pHlp The info helper functions.
3568	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
3569	* @param pszPrefix Caller specified string prefix.
3570	*/
3571	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
3572	{
3573	AssertReturnVoid(pHlp);
3574	AssertReturnVoid(pVmcbCtrl);
3575
3576	pHlp->pfnPrintf(pHlp, "%sCRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
3577	pHlp->pfnPrintf(pHlp, "%sCRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
3578	pHlp->pfnPrintf(pHlp, "%sDRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
3579	pHlp->pfnPrintf(pHlp, "%sDRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
3580	pHlp->pfnPrintf(pHlp, "%sException intercepts = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
3581	pHlp->pfnPrintf(pHlp, "%sControl intercepts = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
3582	pHlp->pfnPrintf(pHlp, "%sPause-filter threshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
3583	pHlp->pfnPrintf(pHlp, "%sPause-filter count = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
3584	pHlp->pfnPrintf(pHlp, "%sIOPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
3585	pHlp->pfnPrintf(pHlp, "%sMSRPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
3586	pHlp->pfnPrintf(pHlp, "%sTSC offset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
3587	pHlp->pfnPrintf(pHlp, "%sTLB Control\n", pszPrefix);
3588	pHlp->pfnPrintf(pHlp, " %sASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
3589	pHlp->pfnPrintf(pHlp, " %sTLB-flush type = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
3590	pHlp->pfnPrintf(pHlp, "%sInterrupt Control\n", pszPrefix);
3591	pHlp->pfnPrintf(pHlp, " %sVTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
3592	pHlp->pfnPrintf(pHlp, " %sVIRQ (Pending) = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
3593	pHlp->pfnPrintf(pHlp, " %sVINTR vector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
3594	pHlp->pfnPrintf(pHlp, " %sVGIF = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
3595	pHlp->pfnPrintf(pHlp, " %sVINTR priority = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
3596	pHlp->pfnPrintf(pHlp, " %sIgnore TPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
3597	pHlp->pfnPrintf(pHlp, " %sVINTR masking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
3598	pHlp->pfnPrintf(pHlp, " %sVGIF enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
3599	pHlp->pfnPrintf(pHlp, " %sAVIC enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
3600	pHlp->pfnPrintf(pHlp, "%sInterrupt Shadow\n", pszPrefix);
3601	pHlp->pfnPrintf(pHlp, " %sInterrupt shadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
3602	pHlp->pfnPrintf(pHlp, " %sGuest-interrupt Mask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
3603	pHlp->pfnPrintf(pHlp, "%sExit Code = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
3604	pHlp->pfnPrintf(pHlp, "%sEXITINFO1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
3605	pHlp->pfnPrintf(pHlp, "%sEXITINFO2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
3606	pHlp->pfnPrintf(pHlp, "%sExit Interrupt Info\n", pszPrefix);
3607	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
3608	pHlp->pfnPrintf(pHlp, " %sVector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
3609	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
3610	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
3611	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
3612	pHlp->pfnPrintf(pHlp, "%sNested paging and SEV\n", pszPrefix);
3613	pHlp->pfnPrintf(pHlp, " %sNested paging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
3614	pHlp->pfnPrintf(pHlp, " %sSEV (Secure Encrypted VM) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
3615	pHlp->pfnPrintf(pHlp, " %sSEV-ES (Encrypted State) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
3616	pHlp->pfnPrintf(pHlp, "%sEvent Inject\n", pszPrefix);
3617	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
3618	pHlp->pfnPrintf(pHlp, " %sVector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
3619	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
3620	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
3621	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
3622	pHlp->pfnPrintf(pHlp, "%sNested-paging CR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
3623	pHlp->pfnPrintf(pHlp, "%sLBR Virtualization\n", pszPrefix);
3624	pHlp->pfnPrintf(pHlp, " %sLBR virt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
3625	pHlp->pfnPrintf(pHlp, " %sVirt. VMSAVE/VMLOAD = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
3626	pHlp->pfnPrintf(pHlp, "%sVMCB Clean Bits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
3627	pHlp->pfnPrintf(pHlp, "%sNext-RIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
3628	pHlp->pfnPrintf(pHlp, "%sInstruction bytes fetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
3629	pHlp->pfnPrintf(pHlp, "%sInstruction bytes = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
3630	pHlp->pfnPrintf(pHlp, "%sAVIC\n", pszPrefix);
3631	pHlp->pfnPrintf(pHlp, " %sBar addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
3632	pHlp->pfnPrintf(pHlp, " %sBacking page addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
3633	pHlp->pfnPrintf(pHlp, " %sLogical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
3634	pHlp->pfnPrintf(pHlp, " %sPhysical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
3635	pHlp->pfnPrintf(pHlp, " %sLast guest core Id = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
3636	}
3637
3638
3639	/**
3640	* Helper for dumping the SVM VMCB selector registers.
3641	*
3642	* @param pHlp The info helper functions.
3643	* @param pSel Pointer to the SVM selector register.
3644	* @param pszName Name of the selector.
3645	* @param pszPrefix Caller specified string prefix.
3646	*/
3647	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
3648	{
3649	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
3650	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
3651	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
3652	}
3653
3654
3655	/**
3656	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
3657	*
3658	* @param pHlp The info helper functions.
3659	* @param pXdtr Pointer to the descriptor table register.
3660	* @param pszName Name of the descriptor table register.
3661	* @param pszPrefix Caller specified string prefix.
3662	*/
3663	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
3664	{
3665	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
3666	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
3667	}
3668
3669
3670	/**
3671	* Displays an SVM VMCB state-save area.
3672	*
3673	* @param pHlp The info helper functions.
3674	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
3675	* @param pszPrefix Caller specified string prefix.
3676	*/
3677	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
3678	{
3679	AssertReturnVoid(pHlp);
3680	AssertReturnVoid(pVmcbStateSave);
3681
3682	char szEFlags[80];
3683	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
3684
3685	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
3686	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
3687	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
3688	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
3689	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
3690	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
3691	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
3692	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
3693	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
3694	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
3695	pHlp->pfnPrintf(pHlp, "%sCPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
3696	pHlp->pfnPrintf(pHlp, "%sEFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
3697	pHlp->pfnPrintf(pHlp, "%sCR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
3698	pHlp->pfnPrintf(pHlp, "%sCR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
3699	pHlp->pfnPrintf(pHlp, "%sCR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
3700	pHlp->pfnPrintf(pHlp, "%sDR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
3701	pHlp->pfnPrintf(pHlp, "%sDR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
3702	pHlp->pfnPrintf(pHlp, "%sRFLAGS = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
3703	pHlp->pfnPrintf(pHlp, "%sRIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
3704	pHlp->pfnPrintf(pHlp, "%sRSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
3705	pHlp->pfnPrintf(pHlp, "%sRAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
3706	pHlp->pfnPrintf(pHlp, "%sSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
3707	pHlp->pfnPrintf(pHlp, "%sLSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
3708	pHlp->pfnPrintf(pHlp, "%sCSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
3709	pHlp->pfnPrintf(pHlp, "%sSFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
3710	pHlp->pfnPrintf(pHlp, "%sKERNELGSBASE = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
3711	pHlp->pfnPrintf(pHlp, "%sSysEnter CS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
3712	pHlp->pfnPrintf(pHlp, "%sSysEnter EIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
3713	pHlp->pfnPrintf(pHlp, "%sSysEnter ESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
3714	pHlp->pfnPrintf(pHlp, "%sCR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
3715	pHlp->pfnPrintf(pHlp, "%sPAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
3716	pHlp->pfnPrintf(pHlp, "%sDBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
3717	pHlp->pfnPrintf(pHlp, "%sBR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
3718	pHlp->pfnPrintf(pHlp, "%sBR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
3719	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
3720	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
3721	}
3722
3723
3724	/**
3725	* Displays a virtual-VMCS.
3726	*
3727	* @param pVCpu The cross context virtual CPU structure.
3728	* @param pHlp The info helper functions.
3729	* @param pVmcs Pointer to a virtual VMCS.
3730	* @param pszPrefix Caller specified string prefix.
3731	*/
3732	static void cpumR3InfoVmxVmcs(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, PCVMXVVMCS pVmcs, const char *pszPrefix)
3733	{
3734	AssertReturnVoid(pHlp);
3735	AssertReturnVoid(pVmcs);
3736
3737	/* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
3738	#define CPUMVMX_DUMP_HOST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3739	do { \
3740	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64}\n", \
3741	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u); \
3742	} while (0)
3743
3744	#define CPUMVMX_DUMP_HOST_FS_GS_TR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3745	do { \
3746	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64}\n", \
3747	(a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u); \
3748	} while (0)
3749
3750	#define CPUMVMX_DUMP_GUEST_SEGREG(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3751	do { \
3752	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
3753	(a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
3754	(a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr); \
3755	} while (0)
3756
3757	#define CPUMVMX_DUMP_GUEST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3758	do { \
3759	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64 limit=%08x}\n", \
3760	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit); \
3761	} while (0)
3762
3763	/* Header. */
3764	{
3765	pHlp->pfnPrintf(pHlp, "%sHeader:\n", pszPrefix);
3766	pHlp->pfnPrintf(pHlp, " %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId);
3767	pHlp->pfnPrintf(pHlp, " %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, VMXGetAbortDesc(pVmcs->enmVmxAbort));
3768	pHlp->pfnPrintf(pHlp, " %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, VMXGetVmcsStateDesc(pVmcs->fVmcsState));
3769	}
3770
3771	/* Control fields. */
3772	{
3773	/* 16-bit. */
3774	pHlp->pfnPrintf(pHlp, "%sControl:\n", pszPrefix);
3775	pHlp->pfnPrintf(pHlp, " %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid);
3776	pHlp->pfnPrintf(pHlp, " %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector);
3777	pHlp->pfnPrintf(pHlp, " %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex);
3778
3779	/* 32-bit. */
3780	pHlp->pfnPrintf(pHlp, " %sPin ctls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls);
3781	pHlp->pfnPrintf(pHlp, " %sProcessor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls);
3782	pHlp->pfnPrintf(pHlp, " %sSecondary processor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2);
3783	pHlp->pfnPrintf(pHlp, " %sVM-exit ctls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls);
3784	pHlp->pfnPrintf(pHlp, " %sVM-entry ctls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls);
3785	pHlp->pfnPrintf(pHlp, " %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap);
3786	pHlp->pfnPrintf(pHlp, " %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask);
3787	pHlp->pfnPrintf(pHlp, " %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch);
3788	pHlp->pfnPrintf(pHlp, " %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount);
3789	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount);
3790	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount);
3791	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount);
3792	pHlp->pfnPrintf(pHlp, " %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo);
3793	{
3794	uint32_t const fInfo = pVmcs->u32EntryIntInfo;
3795	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
3796	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo));
3797	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetEntryIntInfoTypeDesc(uType));
3798	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo));
3799	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3800	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3801	}
3802	pHlp->pfnPrintf(pHlp, " %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode);
3803	pHlp->pfnPrintf(pHlp, " %sVM-entry instr length = %u byte(s)\n", pszPrefix, pVmcs->u32EntryInstrLen);
3804	pHlp->pfnPrintf(pHlp, " %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold);
3805	pHlp->pfnPrintf(pHlp, " %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap);
3806	pHlp->pfnPrintf(pHlp, " %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow);
3807
3808	/* 64-bit. */
3809	pHlp->pfnPrintf(pHlp, " %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u);
3810	pHlp->pfnPrintf(pHlp, " %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u);
3811	pHlp->pfnPrintf(pHlp, " %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u);
3812	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u);
3813	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u);
3814	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u);
3815	pHlp->pfnPrintf(pHlp, " %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u);
3816	pHlp->pfnPrintf(pHlp, " %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u);
3817	pHlp->pfnPrintf(pHlp, " %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u);
3818	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u);
3819	pHlp->pfnPrintf(pHlp, " %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u);
3820	pHlp->pfnPrintf(pHlp, " %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u);
3821	pHlp->pfnPrintf(pHlp, " %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u);
3822	pHlp->pfnPrintf(pHlp, " %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptPtr.u);
3823	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 0 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u);
3824	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 1 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u);
3825	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 2 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u);
3826	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 3 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u);
3827	pHlp->pfnPrintf(pHlp, " %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u);
3828	pHlp->pfnPrintf(pHlp, " %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u);
3829	pHlp->pfnPrintf(pHlp, " %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u);
3830	pHlp->pfnPrintf(pHlp, " %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u);
3831	pHlp->pfnPrintf(pHlp, " %sXSS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssExitBitmap.u);
3832	pHlp->pfnPrintf(pHlp, " %sENCLS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclsExitBitmap.u);
3833	pHlp->pfnPrintf(pHlp, " %sSPP-table ptr = %#RX64\n", pszPrefix, pVmcs->u64SppTablePtr.u);
3834	pHlp->pfnPrintf(pHlp, " %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u);
3835	pHlp->pfnPrintf(pHlp, " %sTertiary processor ctls = %#RX64\n", pszPrefix, pVmcs->u64ProcCtls3.u);
3836	pHlp->pfnPrintf(pHlp, " %sENCLV-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclvExitBitmap.u);
3837
3838	/* Natural width. */
3839	pHlp->pfnPrintf(pHlp, " %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u);
3840	pHlp->pfnPrintf(pHlp, " %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u);
3841	pHlp->pfnPrintf(pHlp, " %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u);
3842	pHlp->pfnPrintf(pHlp, " %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u);
3843	pHlp->pfnPrintf(pHlp, " %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u);
3844	pHlp->pfnPrintf(pHlp, " %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u);
3845	pHlp->pfnPrintf(pHlp, " %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u);
3846	pHlp->pfnPrintf(pHlp, " %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u);
3847	}
3848
3849	/* Guest state. */
3850	{
3851	char szEFlags[80];
3852	cpumR3InfoFormatFlags(&szEFlags[0], pVmcs->u64GuestRFlags.u);
3853	pHlp->pfnPrintf(pHlp, "%sGuest state:\n", pszPrefix);
3854
3855	/* 16-bit. */
3856	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Cs, "CS", pszPrefix);
3857	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ss, "SS", pszPrefix);
3858	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Es, "ES", pszPrefix);
3859	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ds, "DS", pszPrefix);
3860	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Fs, "FS", pszPrefix);
3861	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Gs, "GS", pszPrefix);
3862	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ldtr, "LDTR", pszPrefix);
3863	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Tr, "TR", pszPrefix);
3864	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
3865	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
3866	pHlp->pfnPrintf(pHlp, " %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus);
3867	pHlp->pfnPrintf(pHlp, " %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex);
3868
3869	/* 32-bit. */
3870	pHlp->pfnPrintf(pHlp, " %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState);
3871	pHlp->pfnPrintf(pHlp, " %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState);
3872	pHlp->pfnPrintf(pHlp, " %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase);
3873	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS);
3874	pHlp->pfnPrintf(pHlp, " %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer);
3875
3876	/* 64-bit. */
3877	pHlp->pfnPrintf(pHlp, " %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u);
3878	pHlp->pfnPrintf(pHlp, " %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u);
3879	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u);
3880	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u);
3881	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u);
3882	pHlp->pfnPrintf(pHlp, " %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u);
3883	pHlp->pfnPrintf(pHlp, " %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u);
3884	pHlp->pfnPrintf(pHlp, " %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u);
3885	pHlp->pfnPrintf(pHlp, " %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u);
3886	pHlp->pfnPrintf(pHlp, " %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u);
3887	pHlp->pfnPrintf(pHlp, " %sRTIT_CTL = %#RX64\n", pszPrefix, pVmcs->u64GuestRtitCtlMsr.u);
3888	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64GuestPkrsMsr.u);
3889
3890	/* Natural width. */
3891	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u);
3892	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u);
3893	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u);
3894	pHlp->pfnPrintf(pHlp, " %sDR7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u);
3895	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u);
3896	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u);
3897	pHlp->pfnPrintf(pHlp, " %sRFLAGS = %#RX64 %31s\n",pszPrefix, pVmcs->u64GuestRFlags.u, szEFlags);
3898	pHlp->pfnPrintf(pHlp, " %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpts.u);
3899	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u);
3900	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u);
3901	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64GuestSCetMsr.u);
3902	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64GuestSsp.u);
3903	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64GuestIntrSspTableAddrMsr.u);
3904	}
3905
3906	/* Host state. */
3907	{
3908	pHlp->pfnPrintf(pHlp, "%sHost state:\n", pszPrefix);
3909
3910	/* 16-bit. */
3911	pHlp->pfnPrintf(pHlp, " %sCS = %#RX16\n", pszPrefix, pVmcs->HostCs);
3912	pHlp->pfnPrintf(pHlp, " %sSS = %#RX16\n", pszPrefix, pVmcs->HostSs);
3913	pHlp->pfnPrintf(pHlp, " %sDS = %#RX16\n", pszPrefix, pVmcs->HostDs);
3914	pHlp->pfnPrintf(pHlp, " %sES = %#RX16\n", pszPrefix, pVmcs->HostEs);
3915	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Fs, "FS", pszPrefix);
3916	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Gs, "GS", pszPrefix);
3917	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Tr, "TR", pszPrefix);
3918	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
3919	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
3920
3921	/* 32-bit. */
3922	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs);
3923
3924	/* 64-bit. */
3925	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u);
3926	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u);
3927	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u);
3928	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64HostPkrsMsr.u);
3929
3930	/* Natural width. */
3931	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u);
3932	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u);
3933	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u);
3934	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u);
3935	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u);
3936	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u);
3937	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u);
3938	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64HostSCetMsr.u);
3939	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64HostSsp.u);
3940	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64HostIntrSspTableAddrMsr.u);
3941
3942	}
3943
3944	/* Read-only fields. */
3945	{
3946	pHlp->pfnPrintf(pHlp, "%sRead-only data fields:\n", pszPrefix);
3947
3948	/* 16-bit (none currently). */
3949
3950	/* 32-bit. */
3951	pHlp->pfnPrintf(pHlp, " %sExit reason = %u (%s)\n", pszPrefix, pVmcs->u32RoExitReason, HMGetVmxExitName(pVmcs->u32RoExitReason));
3952	pHlp->pfnPrintf(pHlp, " %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u);
3953	pHlp->pfnPrintf(pHlp, " %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError);
3954	pHlp->pfnPrintf(pHlp, " %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo);
3955	{
3956	uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
3957	uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
3958	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo));
3959	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetExitIntInfoTypeDesc(uType));
3960	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo));
3961	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3962	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3963	}
3964	pHlp->pfnPrintf(pHlp, " %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode);
3965	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo);
3966	{
3967	uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
3968	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
3969	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo));
3970	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetIdtVectoringInfoTypeDesc(uType));
3971	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo));
3972	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo));
3973	}
3974	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode);
3975	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction length = %u byte(s)\n", pszPrefix, pVmcs->u32RoExitInstrLen);
3976	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo);
3977
3978	/* 64-bit. */
3979	pHlp->pfnPrintf(pHlp, " %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u);
3980
3981	/* Natural width. */
3982	pHlp->pfnPrintf(pHlp, " %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u);
3983	pHlp->pfnPrintf(pHlp, " %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u);
3984	pHlp->pfnPrintf(pHlp, " %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u);
3985	pHlp->pfnPrintf(pHlp, " %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u);
3986	pHlp->pfnPrintf(pHlp, " %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u);
3987	}
3988
3989	#ifdef DEBUG_ramshankar
3990	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
3991	{
3992	void *pvPage = RTMemTmpAllocZ(VMX_V_VIRT_APIC_SIZE);
3993	Assert(pvPage);
3994	RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3995	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pvPage, GCPhysVirtApic, VMX_V_VIRT_APIC_SIZE);
3996	if (RT_SUCCESS(rc))
3997	{
3998	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC page\n", pszPrefix);
3999	pHlp->pfnPrintf(pHlp, "%.*Rhxs\n", VMX_V_VIRT_APIC_SIZE, pvPage);
4000	pHlp->pfnPrintf(pHlp, "\n");
4001	}
4002	RTMemTmpFree(pvPage);
4003	}
4004	#else
4005	NOREF(pVCpu);
4006	#endif
4007
4008	#undef CPUMVMX_DUMP_HOST_XDTR
4009	#undef CPUMVMX_DUMP_HOST_FS_GS_TR
4010	#undef CPUMVMX_DUMP_GUEST_SEGREG
4011	#undef CPUMVMX_DUMP_GUEST_XDTR
4012	}
4013
4014
4015	/**
4016	* Display the guest's hardware-virtualization cpu state.
4017	*
4018	* @param pVM The cross context VM structure.
4019	* @param pHlp The info helper functions.
4020	* @param pszArgs Arguments, ignored.
4021	*/
4022	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4023	{
4024	RT_NOREF(pszArgs);
4025
4026	PVMCPU pVCpu = VMMGetCpu(pVM);
4027	if (!pVCpu)
4028	pVCpu = pVM->apCpusR3[0];
4029
4030	PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4031	bool const fSvm = pVM->cpum.s.GuestFeatures.fSvm;
4032	bool const fVmx = pVM->cpum.s.GuestFeatures.fVmx;
4033
4034	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
4035	pHlp->pfnPrintf(pHlp, "fSavedInhibit = %#RX32\n", pCtx->hwvirt.fSavedInhibit);
4036	pHlp->pfnPrintf(pHlp, "In nested-guest hwvirt mode = %RTbool\n", CPUMIsGuestInNestedHwvirtMode(pCtx));
4037
4038	if (fSvm)
4039	{
4040	pHlp->pfnPrintf(pHlp, "SVM hwvirt state:\n");
4041	pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
4042
4043	char szEFlags[80];
4044	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
4045	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
4046	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
4047	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
4048	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.Vmcb.ctrl, " " /* pszPrefix */);
4049	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
4050	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.Vmcb.guest, " " /* pszPrefix */);
4051	pHlp->pfnPrintf(pHlp, " HostState:\n");
4052	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
4053	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
4054	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
4055	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
4056	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
4057	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
4058	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
4059	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
4060	PCCPUMSELREG pSelEs = &pCtx->hwvirt.svm.HostState.es;
4061	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4062	pSelEs->Sel, pSelEs->u64Base, pSelEs->u32Limit, pSelEs->Attr.u);
4063	PCCPUMSELREG pSelCs = &pCtx->hwvirt.svm.HostState.cs;
4064	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4065	pSelCs->Sel, pSelCs->u64Base, pSelCs->u32Limit, pSelCs->Attr.u);
4066	PCCPUMSELREG pSelSs = &pCtx->hwvirt.svm.HostState.ss;
4067	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4068	pSelSs->Sel, pSelSs->u64Base, pSelSs->u32Limit, pSelSs->Attr.u);
4069	PCCPUMSELREG pSelDs = &pCtx->hwvirt.svm.HostState.ds;
4070	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4071	pSelDs->Sel, pSelDs->u64Base, pSelDs->u32Limit, pSelDs->Attr.u);
4072	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
4073	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
4074	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
4075	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
4076	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
4077	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
4078	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
4079	}
4080	else if (fVmx)
4081	{
4082	pHlp->pfnPrintf(pHlp, "VMX hwvirt state:\n");
4083	pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
4084	pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
4085	pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
4086	pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag));
4087	pHlp->pfnPrintf(pHlp, " uDiagAux = %#RX64\n", pCtx->hwvirt.vmx.uDiagAux);
4088	pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, VMXGetAbortDesc(pCtx->hwvirt.vmx.enmAbort));
4089	pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
4090	pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
4091	pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
4092	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
4093	pHlp->pfnPrintf(pHlp, " fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret);
4094	pHlp->pfnPrintf(pHlp, " uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick);
4095	pHlp->pfnPrintf(pHlp, " uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick);
4096	pHlp->pfnPrintf(pHlp, " uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick);
4097	pHlp->pfnPrintf(pHlp, " offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite);
4098	pHlp->pfnPrintf(pHlp, " fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking);
4099	pHlp->pfnPrintf(pHlp, " VMCS cache:\n");
4100	cpumR3InfoVmxVmcs(pVCpu, pHlp, &pCtx->hwvirt.vmx.Vmcs, " " /* pszPrefix */);
4101	}
4102	else
4103	pHlp->pfnPrintf(pHlp, "Hwvirt state disabled.\n");
4104
4105	#undef CPUMHWVIRTDUMP_NONE
4106	#undef CPUMHWVIRTDUMP_COMMON
4107	#undef CPUMHWVIRTDUMP_SVM
4108	#undef CPUMHWVIRTDUMP_VMX
4109	#undef CPUMHWVIRTDUMP_LAST
4110	#undef CPUMHWVIRTDUMP_ALL
4111	}
4112
4113	/**
4114	* Display the current guest instruction
4115	*
4116	* @param pVM The cross context VM structure.
4117	* @param pHlp The info helper functions.
4118	* @param pszArgs Arguments, ignored.
4119	*/
4120	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4121	{
4122	NOREF(pszArgs);
4123
4124	PVMCPU pVCpu = VMMGetCpu(pVM);
4125	if (!pVCpu)
4126	pVCpu = pVM->apCpusR3[0];
4127
4128	char szInstruction[256];
4129	szInstruction[0] = '\0';
4130	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
4131	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
4132	}
4133
4134
4135	/**
4136	* Display the hypervisor cpu state.
4137	*
4138	* @param pVM The cross context VM structure.
4139	* @param pHlp The info helper functions.
4140	* @param pszArgs Arguments, ignored.
4141	*/
4142	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4143	{
4144	PVMCPU pVCpu = VMMGetCpu(pVM);
4145	if (!pVCpu)
4146	pVCpu = pVM->apCpusR3[0];
4147
4148	CPUMDUMPTYPE enmType;
4149	const char *pszComment;
4150	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4151	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
4152
4153	pHlp->pfnPrintf(pHlp,
4154	".dr0=%016RX64 .dr1=%016RX64 .dr2=%016RX64 .dr3=%016RX64\n"
4155	".dr4=%016RX64 .dr5=%016RX64 .dr6=%016RX64 .dr7=%016RX64\n",
4156	pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1], pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3],
4157	pVCpu->cpum.s.Hyper.dr[4], pVCpu->cpum.s.Hyper.dr[5], pVCpu->cpum.s.Hyper.dr[6], pVCpu->cpum.s.Hyper.dr[7]);
4158	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
4159	}
4160
4161
4162	/**
4163	* Display the host cpu state.
4164	*
4165	* @param pVM The cross context VM structure.
4166	* @param pHlp The info helper functions.
4167	* @param pszArgs Arguments, ignored.
4168	*/
4169	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4170	{
4171	CPUMDUMPTYPE enmType;
4172	const char *pszComment;
4173	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4174	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
4175
4176	PVMCPU pVCpu = VMMGetCpu(pVM);
4177	if (!pVCpu)
4178	pVCpu = pVM->apCpusR3[0];
4179	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
4180
4181	/*
4182	* Format the EFLAGS.
4183	*/
4184	uint64_t efl = pCtx->rflags;
4185	char szEFlags[80];
4186	cpumR3InfoFormatFlags(&szEFlags[0], efl);
4187
4188	/*
4189	* Format the registers.
4190	*/
4191	pHlp->pfnPrintf(pHlp,
4192	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
4193	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
4194	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
4195	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
4196	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
4197	"r14=%016RX64 r15=%016RX64\n"
4198	"iopl=%d %31s\n"
4199	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
4200	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
4201	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
4202	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
4203	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
4204	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
4205	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
4206	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
4207	,
4208	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
4209	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
4210	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
4211	/pCtx->r8, pCtx->r9,/ pCtx->r10,
4212	pCtx->r11, pCtx->r12, pCtx->r13,
4213	pCtx->r14, pCtx->r15,
4214	X86_EFL_GET_IOPL(efl), szEFlags,
4215	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
4216	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
4217	pCtx->cr4, pCtx->ldtr, pCtx->tr,
4218	pCtx->dr0, pCtx->dr1, pCtx->dr2,
4219	pCtx->dr3, pCtx->dr6, pCtx->dr7,
4220	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
4221	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
4222	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
4223	}
4224
4225	/**
4226	* Structure used when disassembling and instructions in DBGF.
4227	* This is used so the reader function can get the stuff it needs.
4228	*/
4229	typedef struct CPUMDISASSTATE
4230	{
4231	/** Pointer to the CPU structure. */
4232	PDISCPUSTATE pCpu;
4233	/** Pointer to the VM. */
4234	PVM pVM;
4235	/** Pointer to the VMCPU. */
4236	PVMCPU pVCpu;
4237	/** Pointer to the first byte in the segment. */
4238	RTGCUINTPTR GCPtrSegBase;
4239	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
4240	RTGCUINTPTR GCPtrSegEnd;
4241	/** The size of the segment minus 1. */
4242	RTGCUINTPTR cbSegLimit;
4243	/** Pointer to the current page - R3 Ptr. */
4244	void const *pvPageR3;
4245	/** Pointer to the current page - GC Ptr. */
4246	RTGCPTR pvPageGC;
4247	/** The lock information that PGMPhysReleasePageMappingLock needs. */
4248	PGMPAGEMAPLOCK PageMapLock;
4249	/** Whether the PageMapLock is valid or not. */
4250	bool fLocked;
4251	/** 64 bits mode or not. */
4252	bool f64Bits;
4253	} CPUMDISASSTATE, *PCPUMDISASSTATE;
4254
4255
4256	/**
4257	* @callback_method_impl{FNDISREADBYTES}
4258	*/
4259	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4260	{
4261	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4262	for (;;)
4263	{
4264	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4265
4266	/*
4267	* Need to update the page translation?
4268	*/
4269	if ( !pState->pvPageR3
4270	\|\| (GCPtr >> GUEST_PAGE_SHIFT) != (pState->pvPageGC >> GUEST_PAGE_SHIFT))
4271	{
4272	/* translate the address */
4273	pState->pvPageGC = GCPtr & ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
4274
4275	/* Release mapping lock previously acquired. */
4276	if (pState->fLocked)
4277	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4278	int rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4279	if (RT_SUCCESS(rc))
4280	pState->fLocked = true;
4281	else
4282	{
4283	pState->fLocked = false;
4284	pState->pvPageR3 = NULL;
4285	return rc;
4286	}
4287	}
4288
4289	/*
4290	* Check the segment limit.
4291	*/
4292	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4293	return VERR_OUT_OF_SELECTOR_BOUNDS;
4294
4295	/*
4296	* Calc how much we can read.
4297	*/
4298	uint32_t cb = GUEST_PAGE_SIZE - (GCPtr & GUEST_PAGE_OFFSET_MASK);
4299	if (!pState->f64Bits)
4300	{
4301	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4302	if (cb > cbSeg && cbSeg)
4303	cb = cbSeg;
4304	}
4305	if (cb > cbMaxRead)
4306	cb = cbMaxRead;
4307
4308	/*
4309	* Read and advance or exit.
4310	*/
4311	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & GUEST_PAGE_OFFSET_MASK), cb);
4312	offInstr += (uint8_t)cb;
4313	if (cb >= cbMinRead)
4314	{
4315	pDis->cbCachedInstr = offInstr;
4316	return VINF_SUCCESS;
4317	}
4318	cbMinRead -= (uint8_t)cb;
4319	cbMaxRead -= (uint8_t)cb;
4320	}
4321	}
4322
4323
4324	/**
4325	* Disassemble an instruction and return the information in the provided structure.
4326	*
4327	* @returns VBox status code.
4328	* @param pVM The cross context VM structure.
4329	* @param pVCpu The cross context virtual CPU structure.
4330	* @param pCtx Pointer to the guest CPU context.
4331	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
4332	* @param pCpu Disassembly state.
4333	* @param pszPrefix String prefix for logging (debug only).
4334	*
4335	*/
4336	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
4337	const char *pszPrefix)
4338	{
4339	CPUMDISASSTATE State;
4340	int rc;
4341
4342	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4343	State.pCpu = pCpu;
4344	State.pvPageGC = 0;
4345	State.pvPageR3 = NULL;
4346	State.pVM = pVM;
4347	State.pVCpu = pVCpu;
4348	State.fLocked = false;
4349	State.f64Bits = false;
4350
4351	/*
4352	* Get selector information.
4353	*/
4354	DISCPUMODE enmDisCpuMode;
4355	if ( (pCtx->cr0 & X86_CR0_PE)
4356	&& pCtx->eflags.Bits.u1VM == 0)
4357	{
4358	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4359	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4360	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4361	State.GCPtrSegBase = pCtx->cs.u64Base;
4362	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4363	State.cbSegLimit = pCtx->cs.u32Limit;
4364	enmDisCpuMode = (State.f64Bits)
4365	? DISCPUMODE_64BIT
4366	: pCtx->cs.Attr.n.u1DefBig
4367	? DISCPUMODE_32BIT
4368	: DISCPUMODE_16BIT;
4369	}
4370	else
4371	{
4372	/* real or V86 mode */
4373	enmDisCpuMode = DISCPUMODE_16BIT;
4374	State.GCPtrSegBase = pCtx->cs.Sel * 16;
4375	State.GCPtrSegEnd = 0xFFFFFFFF;
4376	State.cbSegLimit = 0xFFFFFFFF;
4377	}
4378
4379	/*
4380	* Disassemble the instruction.
4381	*/
4382	uint32_t cbInstr;
4383	#ifndef LOG_ENABLED
4384	RT_NOREF_PV(pszPrefix);
4385	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4386	if (RT_SUCCESS(rc))
4387	{
4388	#else
4389	char szOutput[160];
4390	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4391	pCpu, &cbInstr, szOutput, sizeof(szOutput));
4392	if (RT_SUCCESS(rc))
4393	{
4394	/* log it */
4395	if (pszPrefix)
4396	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4397	else
4398	Log(("%s", szOutput));
4399	#endif
4400	rc = VINF_SUCCESS;
4401	}
4402	else
4403	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4404
4405	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
4406	if (State.fLocked)
4407	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4408
4409	return rc;
4410	}
4411
4412
4413
4414	/**
4415	* API for controlling a few of the CPU features found in CR4.
4416	*
4417	* Currently only X86_CR4_TSD is accepted as input.
4418	*
4419	* @returns VBox status code.
4420	*
4421	* @param pVM The cross context VM structure.
4422	* @param fOr The CR4 OR mask.
4423	* @param fAnd The CR4 AND mask.
4424	*/
4425	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4426	{
4427	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4428	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4429
4430	pVM->cpum.s.CR4.OrMask &= fAnd;
4431	pVM->cpum.s.CR4.OrMask \|= fOr;
4432
4433	return VINF_SUCCESS;
4434	}
4435
4436
4437	/**
4438	* Called when the ring-3 init phase completes.
4439	*
4440	* @returns VBox status code.
4441	* @param pVM The cross context VM structure.
4442	* @param enmWhat Which init phase.
4443	*/
4444	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
4445	{
4446	switch (enmWhat)
4447	{
4448	case VMINITCOMPLETED_RING3:
4449	{
4450	/*
4451	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
4452	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
4453	*/
4454	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
4455	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4456	{
4457	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4458
4459	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
4460	if (fSupportsLongMode)
4461	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
4462	}
4463
4464	/* Register statistic counters for MSRs. */
4465	cpumR3MsrRegStats(pVM);
4466
4467	/* There shouldn't be any more calls to CPUMR3SetGuestCpuIdFeature and
4468	CPUMR3ClearGuestCpuIdFeature now, so do some final CPUID polishing (NX). */
4469	cpumR3CpuIdRing3InitDone(pVM);
4470
4471	/* Create VMX-preemption timer for nested guests if required. Must be
4472	done here as CPUM is initialized before TM. */
4473	if (pVM->cpum.s.GuestFeatures.fVmx)
4474	{
4475	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4476	{
4477	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4478	char szName[32];
4479	RTStrPrintf(szName, sizeof(szName), "Nested VMX-preemption %u", idCpu);
4480	int rc = TMR3TimerCreate(pVM, TMCLOCK_VIRTUAL_SYNC, cpumR3VmxPreemptTimerCallback, pVCpu,
4481	TMTIMER_FLAGS_RING0, szName, &pVCpu->cpum.s.hNestedVmxPreemptTimer);
4482	AssertLogRelRCReturn(rc, rc);
4483	}
4484	}
4485	break;
4486	}
4487
4488	default:
4489	break;
4490	}
4491	return VINF_SUCCESS;
4492	}
4493
4494
4495	/**
4496	* Called when the ring-0 init phases completed.
4497	*
4498	* @param pVM The cross context VM structure.
4499	*/
4500	VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
4501	{
4502	/*
4503	* Enable log buffering as we're going to log a lot of lines.
4504	*/
4505	bool const fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
4506
4507	/*
4508	* Log the cpuid.
4509	*/
4510	RTCPUSET OnlineSet;
4511	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4512	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4513	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4514	RTCPUID cCores = RTMpGetCoreCount();
4515	if (cCores)
4516	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
4517	LogRel(("*********************** CPUID dump **********************\n"));
4518	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4519	LogRel(("\n"));
4520	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
4521	LogRel(("****************** End of CPUID dump ********************\n"));
4522
4523	/*
4524	* Log VT-x extended features.
4525	*
4526	* SVM features are currently all covered under CPUID so there is nothing
4527	* to do here for SVM.
4528	*/
4529	if (pVM->cpum.s.HostFeatures.fVmx)
4530	{
4531	LogRel(("********************* VT-x features *********************\n"));
4532	DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
4533	LogRel(("\n"));
4534	LogRel(("***************** End of VT-x features ******************\n"));
4535	}
4536
4537	/*
4538	* Restore the log buffering state to what it was previously.
4539	*/
4540	RTLogRelSetBuffering(fOldBuffered);
4541	}
4542
4543
4544	/**
4545	* Marks the guest debug state as active.
4546	*
4547	* @returns nothing.
4548	* @param pVCpu The cross context virtual CPU structure.
4549	*
4550	* @note This is used solely by NEM (hence the name) to set the correct flags here
4551	* without loading the host's DRx registers, which is not possible from ring-3 anyway.
4552	* The specific NEM backends have to make sure to load the correct values.
4553	*/
4554	VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu)
4555	{
4556	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HYPER);
4557	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
4558	}
4559
4560
4561	/**
4562	* Marks the hyper debug state as active.
4563	*
4564	* @returns nothing.
4565	* @param pVCpu The cross context virtual CPU structure.
4566	*
4567	* @note This is used solely by NEM (hence the name) to set the correct flags here
4568	* without loading the host's DRx registers, which is not possible from ring-3 anyway.
4569	* The specific NEM backends have to make sure to load the correct values.
4570	*/
4571	VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu)
4572	{
4573	/*
4574	* Make sure the hypervisor values are up to date.
4575	*/
4576	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */);
4577
4578	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_GUEST);
4579	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
4580	}

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 97231

Download in other formats: